drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                 } else {
 435                         MLX5_ASSERT(item->spec);
 436                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 437                                                    field->offset, field->size);
 438                         /* Shift out the trailing masked bits from data. */
 439                         data = (data & mask) >> off_b;
 440                         actions[i].data1 = rte_cpu_to_be_32(data);
 441                 }
 442                 ++i;
 443                 ++field;
 444         } while (field->size);
 445         if (resource->actions_num == i)
 446                 return rte_flow_error_set(error, EINVAL,
 447                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 448                                           "invalid modification flow item");
 449         resource->actions_num = i;
 450         return 0;
 451 }
 452
 453 /**
 454  * Convert modify-header set IPv4 address action to DV specification.
 455  *
 456  * @param[in,out] resource
 457  *   Pointer to the modify-header resource.
 458  * @param[in] action
 459  *   Pointer to action specification.
 460  * @param[out] error
 461  *   Pointer to the error structure.
 462  *
 463  * @return
 464  *   0 on success, a negative errno value otherwise and rte_errno is set.
 465  */
 466 static int
 467 flow_dv_convert_action_modify_ipv4
 468                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 469                          const struct rte_flow_action *action,
 470                          struct rte_flow_error *error)
 471 {
 472         const struct rte_flow_action_set_ipv4 *conf =
 473                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 474         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 475         struct rte_flow_item_ipv4 ipv4;
 476         struct rte_flow_item_ipv4 ipv4_mask;
 477
 478         memset(&ipv4, 0, sizeof(ipv4));
 479         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 480         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 481                 ipv4.hdr.src_addr = conf->ipv4_addr;
 482                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 483         } else {
 484                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 485                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 486         }
 487         item.spec = &ipv4;
 488         item.mask = &ipv4_mask;
 489         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 490                                              MLX5_MODIFICATION_TYPE_SET, error);
 491 }
 492
 493 /**
 494  * Convert modify-header set IPv6 address action to DV specification.
 495  *
 496  * @param[in,out] resource
 497  *   Pointer to the modify-header resource.
 498  * @param[in] action
 499  *   Pointer to action specification.
 500  * @param[out] error
 501  *   Pointer to the error structure.
 502  *
 503  * @return
 504  *   0 on success, a negative errno value otherwise and rte_errno is set.
 505  */
 506 static int
 507 flow_dv_convert_action_modify_ipv6
 508                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 509                          const struct rte_flow_action *action,
 510                          struct rte_flow_error *error)
 511 {
 512         const struct rte_flow_action_set_ipv6 *conf =
 513                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 514         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 515         struct rte_flow_item_ipv6 ipv6;
 516         struct rte_flow_item_ipv6 ipv6_mask;
 517
 518         memset(&ipv6, 0, sizeof(ipv6));
 519         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 520         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 521                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 522                        sizeof(ipv6.hdr.src_addr));
 523                 memcpy(&ipv6_mask.hdr.src_addr,
 524                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 525                        sizeof(ipv6.hdr.src_addr));
 526         } else {
 527                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 528                        sizeof(ipv6.hdr.dst_addr));
 529                 memcpy(&ipv6_mask.hdr.dst_addr,
 530                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 531                        sizeof(ipv6.hdr.dst_addr));
 532         }
 533         item.spec = &ipv6;
 534         item.mask = &ipv6_mask;
 535         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 536                                              MLX5_MODIFICATION_TYPE_SET, error);
 537 }
 538
 539 /**
 540  * Convert modify-header set MAC address action to DV specification.
 541  *
 542  * @param[in,out] resource
 543  *   Pointer to the modify-header resource.
 544  * @param[in] action
 545  *   Pointer to action specification.
 546  * @param[out] error
 547  *   Pointer to the error structure.
 548  *
 549  * @return
 550  *   0 on success, a negative errno value otherwise and rte_errno is set.
 551  */
 552 static int
 553 flow_dv_convert_action_modify_mac
 554                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 555                          const struct rte_flow_action *action,
 556                          struct rte_flow_error *error)
 557 {
 558         const struct rte_flow_action_set_mac *conf =
 559                 (const struct rte_flow_action_set_mac *)(action->conf);
 560         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 561         struct rte_flow_item_eth eth;
 562         struct rte_flow_item_eth eth_mask;
 563
 564         memset(&eth, 0, sizeof(eth));
 565         memset(&eth_mask, 0, sizeof(eth_mask));
 566         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 567                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 568                        sizeof(eth.src.addr_bytes));
 569                 memcpy(&eth_mask.src.addr_bytes,
 570                        &rte_flow_item_eth_mask.src.addr_bytes,
 571                        sizeof(eth_mask.src.addr_bytes));
 572         } else {
 573                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 574                        sizeof(eth.dst.addr_bytes));
 575                 memcpy(&eth_mask.dst.addr_bytes,
 576                        &rte_flow_item_eth_mask.dst.addr_bytes,
 577                        sizeof(eth_mask.dst.addr_bytes));
 578         }
 579         item.spec = &eth;
 580         item.mask = &eth_mask;
 581         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 582                                              MLX5_MODIFICATION_TYPE_SET, error);
 583 }
 584
 585 /**
 586  * Convert modify-header set VLAN VID action to DV specification.
 587  *
 588  * @param[in,out] resource
 589  *   Pointer to the modify-header resource.
 590  * @param[in] action
 591  *   Pointer to action specification.
 592  * @param[out] error
 593  *   Pointer to the error structure.
 594  *
 595  * @return
 596  *   0 on success, a negative errno value otherwise and rte_errno is set.
 597  */
 598 static int
 599 flow_dv_convert_action_modify_vlan_vid
 600                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 601                          const struct rte_flow_action *action,
 602                          struct rte_flow_error *error)
 603 {
 604         const struct rte_flow_action_of_set_vlan_vid *conf =
 605                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 606         int i = resource->actions_num;
 607         struct mlx5_modification_cmd *actions = resource->actions;
 608         struct field_modify_info *field = modify_vlan_out_first_vid;
 609
 610         if (i >= MLX5_MAX_MODIFY_NUM)
 611                 return rte_flow_error_set(error, EINVAL,
 612                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 613                          "too many items to modify");
 614         actions[i] = (struct mlx5_modification_cmd) {
 615                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 616                 .field = field->id,
 617                 .length = field->size,
 618                 .offset = field->offset,
 619         };
 620         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 621         actions[i].data1 = conf->vlan_vid;
 622         actions[i].data1 = actions[i].data1 << 16;
 623         resource->actions_num = ++i;
 624         return 0;
 625 }
 626
 627 /**
 628  * Convert modify-header set TP action to DV specification.
 629  *
 630  * @param[in,out] resource
 631  *   Pointer to the modify-header resource.
 632  * @param[in] action
 633  *   Pointer to action specification.
 634  * @param[in] items
 635  *   Pointer to rte_flow_item objects list.
 636  * @param[in] attr
 637  *   Pointer to flow attributes structure.
 638  * @param[in] dev_flow
 639  *   Pointer to the sub flow.
 640  * @param[in] tunnel_decap
 641  *   Whether action is after tunnel decapsulation.
 642  * @param[out] error
 643  *   Pointer to the error structure.
 644  *
 645  * @return
 646  *   0 on success, a negative errno value otherwise and rte_errno is set.
 647  */
 648 static int
 649 flow_dv_convert_action_modify_tp
 650                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 651                          const struct rte_flow_action *action,
 652                          const struct rte_flow_item *items,
 653                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 654                          bool tunnel_decap, struct rte_flow_error *error)
 655 {
 656         const struct rte_flow_action_set_tp *conf =
 657                 (const struct rte_flow_action_set_tp *)(action->conf);
 658         struct rte_flow_item item;
 659         struct rte_flow_item_udp udp;
 660         struct rte_flow_item_udp udp_mask;
 661         struct rte_flow_item_tcp tcp;
 662         struct rte_flow_item_tcp tcp_mask;
 663         struct field_modify_info *field;
 664
 665         if (!attr->valid)
 666                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 667         if (attr->udp) {
 668                 memset(&udp, 0, sizeof(udp));
 669                 memset(&udp_mask, 0, sizeof(udp_mask));
 670                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 671                         udp.hdr.src_port = conf->port;
 672                         udp_mask.hdr.src_port =
 673                                         rte_flow_item_udp_mask.hdr.src_port;
 674                 } else {
 675                         udp.hdr.dst_port = conf->port;
 676                         udp_mask.hdr.dst_port =
 677                                         rte_flow_item_udp_mask.hdr.dst_port;
 678                 }
 679                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 680                 item.spec = &udp;
 681                 item.mask = &udp_mask;
 682                 field = modify_udp;
 683         } else {
 684                 MLX5_ASSERT(attr->tcp);
 685                 memset(&tcp, 0, sizeof(tcp));
 686                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 687                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 688                         tcp.hdr.src_port = conf->port;
 689                         tcp_mask.hdr.src_port =
 690                                         rte_flow_item_tcp_mask.hdr.src_port;
 691                 } else {
 692                         tcp.hdr.dst_port = conf->port;
 693                         tcp_mask.hdr.dst_port =
 694                                         rte_flow_item_tcp_mask.hdr.dst_port;
 695                 }
 696                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 697                 item.spec = &tcp;
 698                 item.mask = &tcp_mask;
 699                 field = modify_tcp;
 700         }
 701         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 702                                              MLX5_MODIFICATION_TYPE_SET, error);
 703 }
 704
 705 /**
 706  * Convert modify-header set TTL action to DV specification.
 707  *
 708  * @param[in,out] resource
 709  *   Pointer to the modify-header resource.
 710  * @param[in] action
 711  *   Pointer to action specification.
 712  * @param[in] items
 713  *   Pointer to rte_flow_item objects list.
 714  * @param[in] attr
 715  *   Pointer to flow attributes structure.
 716  * @param[in] dev_flow
 717  *   Pointer to the sub flow.
 718  * @param[in] tunnel_decap
 719  *   Whether action is after tunnel decapsulation.
 720  * @param[out] error
 721  *   Pointer to the error structure.
 722  *
 723  * @return
 724  *   0 on success, a negative errno value otherwise and rte_errno is set.
 725  */
 726 static int
 727 flow_dv_convert_action_modify_ttl
 728                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 729                          const struct rte_flow_action *action,
 730                          const struct rte_flow_item *items,
 731                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 732                          bool tunnel_decap, struct rte_flow_error *error)
 733 {
 734         const struct rte_flow_action_set_ttl *conf =
 735                 (const struct rte_flow_action_set_ttl *)(action->conf);
 736         struct rte_flow_item item;
 737         struct rte_flow_item_ipv4 ipv4;
 738         struct rte_flow_item_ipv4 ipv4_mask;
 739         struct rte_flow_item_ipv6 ipv6;
 740         struct rte_flow_item_ipv6 ipv6_mask;
 741         struct field_modify_info *field;
 742
 743         if (!attr->valid)
 744                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 745         if (attr->ipv4) {
 746                 memset(&ipv4, 0, sizeof(ipv4));
 747                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 748                 ipv4.hdr.time_to_live = conf->ttl_value;
 749                 ipv4_mask.hdr.time_to_live = 0xFF;
 750                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 751                 item.spec = &ipv4;
 752                 item.mask = &ipv4_mask;
 753                 field = modify_ipv4;
 754         } else {
 755                 MLX5_ASSERT(attr->ipv6);
 756                 memset(&ipv6, 0, sizeof(ipv6));
 757                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 758                 ipv6.hdr.hop_limits = conf->ttl_value;
 759                 ipv6_mask.hdr.hop_limits = 0xFF;
 760                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 761                 item.spec = &ipv6;
 762                 item.mask = &ipv6_mask;
 763                 field = modify_ipv6;
 764         }
 765         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 766                                              MLX5_MODIFICATION_TYPE_SET, error);
 767 }
 768
 769 /**
 770  * Convert modify-header decrement TTL action to DV specification.
 771  *
 772  * @param[in,out] resource
 773  *   Pointer to the modify-header resource.
 774  * @param[in] action
 775  *   Pointer to action specification.
 776  * @param[in] items
 777  *   Pointer to rte_flow_item objects list.
 778  * @param[in] attr
 779  *   Pointer to flow attributes structure.
 780  * @param[in] dev_flow
 781  *   Pointer to the sub flow.
 782  * @param[in] tunnel_decap
 783  *   Whether action is after tunnel decapsulation.
 784  * @param[out] error
 785  *   Pointer to the error structure.
 786  *
 787  * @return
 788  *   0 on success, a negative errno value otherwise and rte_errno is set.
 789  */
 790 static int
 791 flow_dv_convert_action_modify_dec_ttl
 792                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 793                          const struct rte_flow_item *items,
 794                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 795                          bool tunnel_decap, struct rte_flow_error *error)
 796 {
 797         struct rte_flow_item item;
 798         struct rte_flow_item_ipv4 ipv4;
 799         struct rte_flow_item_ipv4 ipv4_mask;
 800         struct rte_flow_item_ipv6 ipv6;
 801         struct rte_flow_item_ipv6 ipv6_mask;
 802         struct field_modify_info *field;
 803
 804         if (!attr->valid)
 805                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 806         if (attr->ipv4) {
 807                 memset(&ipv4, 0, sizeof(ipv4));
 808                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 809                 ipv4.hdr.time_to_live = 0xFF;
 810                 ipv4_mask.hdr.time_to_live = 0xFF;
 811                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 812                 item.spec = &ipv4;
 813                 item.mask = &ipv4_mask;
 814                 field = modify_ipv4;
 815         } else {
 816                 MLX5_ASSERT(attr->ipv6);
 817                 memset(&ipv6, 0, sizeof(ipv6));
 818                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 819                 ipv6.hdr.hop_limits = 0xFF;
 820                 ipv6_mask.hdr.hop_limits = 0xFF;
 821                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 822                 item.spec = &ipv6;
 823                 item.mask = &ipv6_mask;
 824                 field = modify_ipv6;
 825         }
 826         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 827                                              MLX5_MODIFICATION_TYPE_ADD, error);
 828 }
 829
 830 /**
 831  * Convert modify-header increment/decrement TCP Sequence number
 832  * to DV specification.
 833  *
 834  * @param[in,out] resource
 835  *   Pointer to the modify-header resource.
 836  * @param[in] action
 837  *   Pointer to action specification.
 838  * @param[out] error
 839  *   Pointer to the error structure.
 840  *
 841  * @return
 842  *   0 on success, a negative errno value otherwise and rte_errno is set.
 843  */
 844 static int
 845 flow_dv_convert_action_modify_tcp_seq
 846                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 847                          const struct rte_flow_action *action,
 848                          struct rte_flow_error *error)
 849 {
 850         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 851         uint64_t value = rte_be_to_cpu_32(*conf);
 852         struct rte_flow_item item;
 853         struct rte_flow_item_tcp tcp;
 854         struct rte_flow_item_tcp tcp_mask;
 855
 856         memset(&tcp, 0, sizeof(tcp));
 857         memset(&tcp_mask, 0, sizeof(tcp_mask));
 858         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 859                 /*
 860                  * The HW has no decrement operation, only increment operation.
 861                  * To simulate decrement X from Y using increment operation
 862                  * we need to add UINT32_MAX X times to Y.
 863                  * Each adding of UINT32_MAX decrements Y by 1.
 864                  */
 865                 value *= UINT32_MAX;
 866         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 867         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 868         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 869         item.spec = &tcp;
 870         item.mask = &tcp_mask;
 871         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 872                                              MLX5_MODIFICATION_TYPE_ADD, error);
 873 }
 874
 875 /**
 876  * Convert modify-header increment/decrement TCP Acknowledgment number
 877  * to DV specification.
 878  *
 879  * @param[in,out] resource
 880  *   Pointer to the modify-header resource.
 881  * @param[in] action
 882  *   Pointer to action specification.
 883  * @param[out] error
 884  *   Pointer to the error structure.
 885  *
 886  * @return
 887  *   0 on success, a negative errno value otherwise and rte_errno is set.
 888  */
 889 static int
 890 flow_dv_convert_action_modify_tcp_ack
 891                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 892                          const struct rte_flow_action *action,
 893                          struct rte_flow_error *error)
 894 {
 895         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 896         uint64_t value = rte_be_to_cpu_32(*conf);
 897         struct rte_flow_item item;
 898         struct rte_flow_item_tcp tcp;
 899         struct rte_flow_item_tcp tcp_mask;
 900
 901         memset(&tcp, 0, sizeof(tcp));
 902         memset(&tcp_mask, 0, sizeof(tcp_mask));
 903         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 904                 /*
 905                  * The HW has no decrement operation, only increment operation.
 906                  * To simulate decrement X from Y using increment operation
 907                  * we need to add UINT32_MAX X times to Y.
 908                  * Each adding of UINT32_MAX decrements Y by 1.
 909                  */
 910                 value *= UINT32_MAX;
 911         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 912         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 913         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 914         item.spec = &tcp;
 915         item.mask = &tcp_mask;
 916         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 917                                              MLX5_MODIFICATION_TYPE_ADD, error);
 918 }
 919
 920 static enum mlx5_modification_field reg_to_field[] = {
 921         [REG_NON] = MLX5_MODI_OUT_NONE,
 922         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 923         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 924         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 925         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 926         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 927         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 928         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 929         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 930         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 931         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 932 };
 933
 934 /**
 935  * Convert register set to DV specification.
 936  *
 937  * @param[in,out] resource
 938  *   Pointer to the modify-header resource.
 939  * @param[in] action
 940  *   Pointer to action specification.
 941  * @param[out] error
 942  *   Pointer to the error structure.
 943  *
 944  * @return
 945  *   0 on success, a negative errno value otherwise and rte_errno is set.
 946  */
 947 static int
 948 flow_dv_convert_action_set_reg
 949                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 950                          const struct rte_flow_action *action,
 951                          struct rte_flow_error *error)
 952 {
 953         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 954         struct mlx5_modification_cmd *actions = resource->actions;
 955         uint32_t i = resource->actions_num;
 956
 957         if (i >= MLX5_MAX_MODIFY_NUM)
 958                 return rte_flow_error_set(error, EINVAL,
 959                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 960                                           "too many items to modify");
 961         MLX5_ASSERT(conf->id != REG_NON);
 962         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 963         actions[i] = (struct mlx5_modification_cmd) {
 964                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 965                 .field = reg_to_field[conf->id],
 966         };
 967         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 968         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 969         ++i;
 970         resource->actions_num = i;
 971         return 0;
 972 }
 973
 974 /**
 975  * Convert SET_TAG action to DV specification.
 976  *
 977  * @param[in] dev
 978  *   Pointer to the rte_eth_dev structure.
 979  * @param[in,out] resource
 980  *   Pointer to the modify-header resource.
 981  * @param[in] conf
 982  *   Pointer to action specification.
 983  * @param[out] error
 984  *   Pointer to the error structure.
 985  *
 986  * @return
 987  *   0 on success, a negative errno value otherwise and rte_errno is set.
 988  */
 989 static int
 990 flow_dv_convert_action_set_tag
 991                         (struct rte_eth_dev *dev,
 992                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 993                          const struct rte_flow_action_set_tag *conf,
 994                          struct rte_flow_error *error)
 995 {
 996         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 997         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 998         struct rte_flow_item item = {
 999                 .spec = &data,
1000                 .mask = &mask,
1001         };
1002         struct field_modify_info reg_c_x[] = {
1003                 [1] = {0, 0, 0},
1004         };
1005         enum mlx5_modification_field reg_type;
1006         int ret;
1007
1008         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1009         if (ret < 0)
1010                 return ret;
1011         MLX5_ASSERT(ret != REG_NON);
1012         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1013         reg_type = reg_to_field[ret];
1014         MLX5_ASSERT(reg_type > 0);
1015         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1016         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1017                                              MLX5_MODIFICATION_TYPE_SET, error);
1018 }
1019
1020 /**
1021  * Convert internal COPY_REG action to DV specification.
1022  *
1023  * @param[in] dev
1024  *   Pointer to the rte_eth_dev structure.
1025  * @param[in,out] res
1026  *   Pointer to the modify-header resource.
1027  * @param[in] action
1028  *   Pointer to action specification.
1029  * @param[out] error
1030  *   Pointer to the error structure.
1031  *
1032  * @return
1033  *   0 on success, a negative errno value otherwise and rte_errno is set.
1034  */
1035 static int
1036 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1037                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1038                                  const struct rte_flow_action *action,
1039                                  struct rte_flow_error *error)
1040 {
1041         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1042         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1043         struct rte_flow_item item = {
1044                 .spec = NULL,
1045                 .mask = &mask,
1046         };
1047         struct field_modify_info reg_src[] = {
1048                 {4, 0, reg_to_field[conf->src]},
1049                 {0, 0, 0},
1050         };
1051         struct field_modify_info reg_dst = {
1052                 .offset = 0,
1053                 .id = reg_to_field[conf->dst],
1054         };
1055         /* Adjust reg_c[0] usage according to reported mask. */
1056         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1057                 struct mlx5_priv *priv = dev->data->dev_private;
1058                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1059
1060                 MLX5_ASSERT(reg_c0);
1061                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1062                 if (conf->dst == REG_C_0) {
1063                         /* Copy to reg_c[0], within mask only. */
1064                         reg_dst.offset = rte_bsf32(reg_c0);
1065                         /*
1066                          * Mask is ignoring the enianness, because
1067                          * there is no conversion in datapath.
1068                          */
1069 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1070                         /* Copy from destination lower bits to reg_c[0]. */
1071                         mask = reg_c0 >> reg_dst.offset;
1072 #else
1073                         /* Copy from destination upper bits to reg_c[0]. */
1074                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1075                                           rte_fls_u32(reg_c0));
1076 #endif
1077                 } else {
1078                         mask = rte_cpu_to_be_32(reg_c0);
1079 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1080                         /* Copy from reg_c[0] to destination lower bits. */
1081                         reg_dst.offset = 0;
1082 #else
1083                         /* Copy from reg_c[0] to destination upper bits. */
1084                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1085                                          (rte_fls_u32(reg_c0) -
1086                                           rte_bsf32(reg_c0));
1087 #endif
1088                 }
1089         }
1090         return flow_dv_convert_modify_action(&item,
1091                                              reg_src, &reg_dst, res,
1092                                              MLX5_MODIFICATION_TYPE_COPY,
1093                                              error);
1094 }
1095
1096 /**
1097  * Convert MARK action to DV specification. This routine is used
1098  * in extensive metadata only and requires metadata register to be
1099  * handled. In legacy mode hardware tag resource is engaged.
1100  *
1101  * @param[in] dev
1102  *   Pointer to the rte_eth_dev structure.
1103  * @param[in] conf
1104  *   Pointer to MARK action specification.
1105  * @param[in,out] resource
1106  *   Pointer to the modify-header resource.
1107  * @param[out] error
1108  *   Pointer to the error structure.
1109  *
1110  * @return
1111  *   0 on success, a negative errno value otherwise and rte_errno is set.
1112  */
1113 static int
1114 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1115                             const struct rte_flow_action_mark *conf,
1116                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1117                             struct rte_flow_error *error)
1118 {
1119         struct mlx5_priv *priv = dev->data->dev_private;
1120         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1121                                            priv->sh->dv_mark_mask);
1122         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1123         struct rte_flow_item item = {
1124                 .spec = &data,
1125                 .mask = &mask,
1126         };
1127         struct field_modify_info reg_c_x[] = {
1128                 [1] = {0, 0, 0},
1129         };
1130         int reg;
1131
1132         if (!mask)
1133                 return rte_flow_error_set(error, EINVAL,
1134                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1135                                           NULL, "zero mark action mask");
1136         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1137         if (reg < 0)
1138                 return reg;
1139         MLX5_ASSERT(reg > 0);
1140         if (reg == REG_C_0) {
1141                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1142                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1143
1144                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1145                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1146                 mask = rte_cpu_to_be_32(mask << shl_c0);
1147         }
1148         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1149         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1150                                              MLX5_MODIFICATION_TYPE_SET, error);
1151 }
1152
1153 /**
1154  * Get metadata register index for specified steering domain.
1155  *
1156  * @param[in] dev
1157  *   Pointer to the rte_eth_dev structure.
1158  * @param[in] attr
1159  *   Attributes of flow to determine steering domain.
1160  * @param[out] error
1161  *   Pointer to the error structure.
1162  *
1163  * @return
1164  *   positive index on success, a negative errno value otherwise
1165  *   and rte_errno is set.
1166  */
1167 static enum modify_reg
1168 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1169                          const struct rte_flow_attr *attr,
1170                          struct rte_flow_error *error)
1171 {
1172         int reg =
1173                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1174                                           MLX5_METADATA_FDB :
1175                                             attr->egress ?
1176                                             MLX5_METADATA_TX :
1177                                             MLX5_METADATA_RX, 0, error);
1178         if (reg < 0)
1179                 return rte_flow_error_set(error,
1180                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1181                                           NULL, "unavailable "
1182                                           "metadata register");
1183         return reg;
1184 }
1185
1186 /**
1187  * Convert SET_META action to DV specification.
1188  *
1189  * @param[in] dev
1190  *   Pointer to the rte_eth_dev structure.
1191  * @param[in,out] resource
1192  *   Pointer to the modify-header resource.
1193  * @param[in] attr
1194  *   Attributes of flow that includes this item.
1195  * @param[in] conf
1196  *   Pointer to action specification.
1197  * @param[out] error
1198  *   Pointer to the error structure.
1199  *
1200  * @return
1201  *   0 on success, a negative errno value otherwise and rte_errno is set.
1202  */
1203 static int
1204 flow_dv_convert_action_set_meta
1205                         (struct rte_eth_dev *dev,
1206                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1207                          const struct rte_flow_attr *attr,
1208                          const struct rte_flow_action_set_meta *conf,
1209                          struct rte_flow_error *error)
1210 {
1211         uint32_t data = conf->data;
1212         uint32_t mask = conf->mask;
1213         struct rte_flow_item item = {
1214                 .spec = &data,
1215                 .mask = &mask,
1216         };
1217         struct field_modify_info reg_c_x[] = {
1218                 [1] = {0, 0, 0},
1219         };
1220         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1221
1222         if (reg < 0)
1223                 return reg;
1224         MLX5_ASSERT(reg != REG_NON);
1225         /*
1226          * In datapath code there is no endianness
1227          * coversions for perfromance reasons, all
1228          * pattern conversions are done in rte_flow.
1229          */
1230         if (reg == REG_C_0) {
1231                 struct mlx5_priv *priv = dev->data->dev_private;
1232                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1233                 uint32_t shl_c0;
1234
1235                 MLX5_ASSERT(msk_c0);
1236 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1237                 shl_c0 = rte_bsf32(msk_c0);
1238 #else
1239                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1240 #endif
1241                 mask <<= shl_c0;
1242                 data <<= shl_c0;
1243                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1244         }
1245         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1246         /* The routine expects parameters in memory as big-endian ones. */
1247         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1248                                              MLX5_MODIFICATION_TYPE_SET, error);
1249 }
1250
1251 /**
1252  * Convert modify-header set IPv4 DSCP action to DV specification.
1253  *
1254  * @param[in,out] resource
1255  *   Pointer to the modify-header resource.
1256  * @param[in] action
1257  *   Pointer to action specification.
1258  * @param[out] error
1259  *   Pointer to the error structure.
1260  *
1261  * @return
1262  *   0 on success, a negative errno value otherwise and rte_errno is set.
1263  */
1264 static int
1265 flow_dv_convert_action_modify_ipv4_dscp
1266                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1267                          const struct rte_flow_action *action,
1268                          struct rte_flow_error *error)
1269 {
1270         const struct rte_flow_action_set_dscp *conf =
1271                 (const struct rte_flow_action_set_dscp *)(action->conf);
1272         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1273         struct rte_flow_item_ipv4 ipv4;
1274         struct rte_flow_item_ipv4 ipv4_mask;
1275
1276         memset(&ipv4, 0, sizeof(ipv4));
1277         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1278         ipv4.hdr.type_of_service = conf->dscp;
1279         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1280         item.spec = &ipv4;
1281         item.mask = &ipv4_mask;
1282         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1283                                              MLX5_MODIFICATION_TYPE_SET, error);
1284 }
1285
1286 /**
1287  * Convert modify-header set IPv6 DSCP action to DV specification.
1288  *
1289  * @param[in,out] resource
1290  *   Pointer to the modify-header resource.
1291  * @param[in] action
1292  *   Pointer to action specification.
1293  * @param[out] error
1294  *   Pointer to the error structure.
1295  *
1296  * @return
1297  *   0 on success, a negative errno value otherwise and rte_errno is set.
1298  */
1299 static int
1300 flow_dv_convert_action_modify_ipv6_dscp
1301                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1302                          const struct rte_flow_action *action,
1303                          struct rte_flow_error *error)
1304 {
1305         const struct rte_flow_action_set_dscp *conf =
1306                 (const struct rte_flow_action_set_dscp *)(action->conf);
1307         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1308         struct rte_flow_item_ipv6 ipv6;
1309         struct rte_flow_item_ipv6 ipv6_mask;
1310
1311         memset(&ipv6, 0, sizeof(ipv6));
1312         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1313         /*
1314          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1315          * rdma-core only accept the DSCP bits byte aligned start from
1316          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1317          * bits in IPv6 case as rdma-core requires byte aligned value.
1318          */
1319         ipv6.hdr.vtc_flow = conf->dscp;
1320         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1321         item.spec = &ipv6;
1322         item.mask = &ipv6_mask;
1323         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1324                                              MLX5_MODIFICATION_TYPE_SET, error);
1325 }
1326
1327 /**
1328  * Validate MARK item.
1329  *
1330  * @param[in] dev
1331  *   Pointer to the rte_eth_dev structure.
1332  * @param[in] item
1333  *   Item specification.
1334  * @param[in] attr
1335  *   Attributes of flow that includes this item.
1336  * @param[out] error
1337  *   Pointer to error structure.
1338  *
1339  * @return
1340  *   0 on success, a negative errno value otherwise and rte_errno is set.
1341  */
1342 static int
1343 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1344                            const struct rte_flow_item *item,
1345                            const struct rte_flow_attr *attr __rte_unused,
1346                            struct rte_flow_error *error)
1347 {
1348         struct mlx5_priv *priv = dev->data->dev_private;
1349         struct mlx5_dev_config *config = &priv->config;
1350         const struct rte_flow_item_mark *spec = item->spec;
1351         const struct rte_flow_item_mark *mask = item->mask;
1352         const struct rte_flow_item_mark nic_mask = {
1353                 .id = priv->sh->dv_mark_mask,
1354         };
1355         int ret;
1356
1357         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1358                 return rte_flow_error_set(error, ENOTSUP,
1359                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1360                                           "extended metadata feature"
1361                                           " isn't enabled");
1362         if (!mlx5_flow_ext_mreg_supported(dev))
1363                 return rte_flow_error_set(error, ENOTSUP,
1364                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1365                                           "extended metadata register"
1366                                           " isn't supported");
1367         if (!nic_mask.id)
1368                 return rte_flow_error_set(error, ENOTSUP,
1369                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1370                                           "extended metadata register"
1371                                           " isn't available");
1372         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1373         if (ret < 0)
1374                 return ret;
1375         if (!spec)
1376                 return rte_flow_error_set(error, EINVAL,
1377                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1378                                           item->spec,
1379                                           "data cannot be empty");
1380         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1381                 return rte_flow_error_set(error, EINVAL,
1382                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1383                                           &spec->id,
1384                                           "mark id exceeds the limit");
1385         if (!mask)
1386                 mask = &nic_mask;
1387         if (!mask->id)
1388                 return rte_flow_error_set(error, EINVAL,
1389                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1390                                         "mask cannot be zero");
1391
1392         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1393                                         (const uint8_t *)&nic_mask,
1394                                         sizeof(struct rte_flow_item_mark),
1395                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1396         if (ret < 0)
1397                 return ret;
1398         return 0;
1399 }
1400
1401 /**
1402  * Validate META item.
1403  *
1404  * @param[in] dev
1405  *   Pointer to the rte_eth_dev structure.
1406  * @param[in] item
1407  *   Item specification.
1408  * @param[in] attr
1409  *   Attributes of flow that includes this item.
1410  * @param[out] error
1411  *   Pointer to error structure.
1412  *
1413  * @return
1414  *   0 on success, a negative errno value otherwise and rte_errno is set.
1415  */
1416 static int
1417 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1418                            const struct rte_flow_item *item,
1419                            const struct rte_flow_attr *attr,
1420                            struct rte_flow_error *error)
1421 {
1422         struct mlx5_priv *priv = dev->data->dev_private;
1423         struct mlx5_dev_config *config = &priv->config;
1424         const struct rte_flow_item_meta *spec = item->spec;
1425         const struct rte_flow_item_meta *mask = item->mask;
1426         struct rte_flow_item_meta nic_mask = {
1427                 .data = UINT32_MAX
1428         };
1429         int reg;
1430         int ret;
1431
1432         if (!spec)
1433                 return rte_flow_error_set(error, EINVAL,
1434                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1435                                           item->spec,
1436                                           "data cannot be empty");
1437         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1438                 if (!mlx5_flow_ext_mreg_supported(dev))
1439                         return rte_flow_error_set(error, ENOTSUP,
1440                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1441                                           "extended metadata register"
1442                                           " isn't supported");
1443                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1444                 if (reg < 0)
1445                         return reg;
1446                 if (reg == REG_NON)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                         "unavalable extended metadata register");
1450                 if (reg == REG_B)
1451                         return rte_flow_error_set(error, ENOTSUP,
1452                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1453                                           "match on reg_b "
1454                                           "isn't supported");
1455                 if (reg != REG_A)
1456                         nic_mask.data = priv->sh->dv_meta_mask;
1457         } else if (attr->transfer) {
1458                 return rte_flow_error_set(error, ENOTSUP,
1459                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1460                                         "extended metadata feature "
1461                                         "should be enabled when "
1462                                         "meta item is requested "
1463                                         "with e-switch mode ");
1464         }
1465         if (!mask)
1466                 mask = &rte_flow_item_meta_mask;
1467         if (!mask->data)
1468                 return rte_flow_error_set(error, EINVAL,
1469                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1470                                         "mask cannot be zero");
1471
1472         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1473                                         (const uint8_t *)&nic_mask,
1474                                         sizeof(struct rte_flow_item_meta),
1475                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1476         return ret;
1477 }
1478
1479 /**
1480  * Validate TAG item.
1481  *
1482  * @param[in] dev
1483  *   Pointer to the rte_eth_dev structure.
1484  * @param[in] item
1485  *   Item specification.
1486  * @param[in] attr
1487  *   Attributes of flow that includes this item.
1488  * @param[out] error
1489  *   Pointer to error structure.
1490  *
1491  * @return
1492  *   0 on success, a negative errno value otherwise and rte_errno is set.
1493  */
1494 static int
1495 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1496                           const struct rte_flow_item *item,
1497                           const struct rte_flow_attr *attr __rte_unused,
1498                           struct rte_flow_error *error)
1499 {
1500         const struct rte_flow_item_tag *spec = item->spec;
1501         const struct rte_flow_item_tag *mask = item->mask;
1502         const struct rte_flow_item_tag nic_mask = {
1503                 .data = RTE_BE32(UINT32_MAX),
1504                 .index = 0xff,
1505         };
1506         int ret;
1507
1508         if (!mlx5_flow_ext_mreg_supported(dev))
1509                 return rte_flow_error_set(error, ENOTSUP,
1510                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1511                                           "extensive metadata register"
1512                                           " isn't supported");
1513         if (!spec)
1514                 return rte_flow_error_set(error, EINVAL,
1515                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1516                                           item->spec,
1517                                           "data cannot be empty");
1518         if (!mask)
1519                 mask = &rte_flow_item_tag_mask;
1520         if (!mask->data)
1521                 return rte_flow_error_set(error, EINVAL,
1522                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1523                                         "mask cannot be zero");
1524
1525         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1526                                         (const uint8_t *)&nic_mask,
1527                                         sizeof(struct rte_flow_item_tag),
1528                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1529         if (ret < 0)
1530                 return ret;
1531         if (mask->index != 0xff)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534                                           "partial mask for tag index"
1535                                           " is not supported");
1536         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1537         if (ret < 0)
1538                 return ret;
1539         MLX5_ASSERT(ret != REG_NON);
1540         return 0;
1541 }
1542
1543 /**
1544  * Validate vport item.
1545  *
1546  * @param[in] dev
1547  *   Pointer to the rte_eth_dev structure.
1548  * @param[in] item
1549  *   Item specification.
1550  * @param[in] attr
1551  *   Attributes of flow that includes this item.
1552  * @param[in] item_flags
1553  *   Bit-fields that holds the items detected until now.
1554  * @param[out] error
1555  *   Pointer to error structure.
1556  *
1557  * @return
1558  *   0 on success, a negative errno value otherwise and rte_errno is set.
1559  */
1560 static int
1561 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1562                               const struct rte_flow_item *item,
1563                               const struct rte_flow_attr *attr,
1564                               uint64_t item_flags,
1565                               struct rte_flow_error *error)
1566 {
1567         const struct rte_flow_item_port_id *spec = item->spec;
1568         const struct rte_flow_item_port_id *mask = item->mask;
1569         const struct rte_flow_item_port_id switch_mask = {
1570                         .id = 0xffffffff,
1571         };
1572         struct mlx5_priv *esw_priv;
1573         struct mlx5_priv *dev_priv;
1574         int ret;
1575
1576         if (!attr->transfer)
1577                 return rte_flow_error_set(error, EINVAL,
1578                                           RTE_FLOW_ERROR_TYPE_ITEM,
1579                                           NULL,
1580                                           "match on port id is valid only"
1581                                           " when transfer flag is enabled");
1582         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1583                 return rte_flow_error_set(error, ENOTSUP,
1584                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1585                                           "multiple source ports are not"
1586                                           " supported");
1587         if (!mask)
1588                 mask = &switch_mask;
1589         if (mask->id != 0xffffffff)
1590                 return rte_flow_error_set(error, ENOTSUP,
1591                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1592                                            mask,
1593                                            "no support for partial mask on"
1594                                            " \"id\" field");
1595         ret = mlx5_flow_item_acceptable
1596                                 (item, (const uint8_t *)mask,
1597                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1598                                  sizeof(struct rte_flow_item_port_id),
1599                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1600         if (ret)
1601                 return ret;
1602         if (!spec)
1603                 return 0;
1604         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1605         if (!esw_priv)
1606                 return rte_flow_error_set(error, rte_errno,
1607                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1608                                           "failed to obtain E-Switch info for"
1609                                           " port");
1610         dev_priv = mlx5_dev_to_eswitch_info(dev);
1611         if (!dev_priv)
1612                 return rte_flow_error_set(error, rte_errno,
1613                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1614                                           NULL,
1615                                           "failed to obtain E-Switch info");
1616         if (esw_priv->domain_id != dev_priv->domain_id)
1617                 return rte_flow_error_set(error, EINVAL,
1618                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619                                           "cannot match on a port from a"
1620                                           " different E-Switch");
1621         return 0;
1622 }
1623
1624 /**
1625  * Validate VLAN item.
1626  *
1627  * @param[in] item
1628  *   Item specification.
1629  * @param[in] item_flags
1630  *   Bit-fields that holds the items detected until now.
1631  * @param[in] dev
1632  *   Ethernet device flow is being created on.
1633  * @param[out] error
1634  *   Pointer to error structure.
1635  *
1636  * @return
1637  *   0 on success, a negative errno value otherwise and rte_errno is set.
1638  */
1639 static int
1640 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1641                            uint64_t item_flags,
1642                            struct rte_eth_dev *dev,
1643                            struct rte_flow_error *error)
1644 {
1645         const struct rte_flow_item_vlan *mask = item->mask;
1646         const struct rte_flow_item_vlan nic_mask = {
1647                 .tci = RTE_BE16(UINT16_MAX),
1648                 .inner_type = RTE_BE16(UINT16_MAX),
1649                 .has_more_vlan = 1,
1650         };
1651         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1652         int ret;
1653         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1654                                         MLX5_FLOW_LAYER_INNER_L4) :
1655                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1656                                         MLX5_FLOW_LAYER_OUTER_L4);
1657         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1658                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1659
1660         if (item_flags & vlanm)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "multiple VLAN layers not supported");
1664         else if ((item_flags & l34m) != 0)
1665                 return rte_flow_error_set(error, EINVAL,
1666                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1667                                           "VLAN cannot follow L3/L4 layer");
1668         if (!mask)
1669                 mask = &rte_flow_item_vlan_mask;
1670         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1671                                         (const uint8_t *)&nic_mask,
1672                                         sizeof(struct rte_flow_item_vlan),
1673                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1674         if (ret)
1675                 return ret;
1676         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1677                 struct mlx5_priv *priv = dev->data->dev_private;
1678
1679                 if (priv->vmwa_context) {
1680                         /*
1681                          * Non-NULL context means we have a virtual machine
1682                          * and SR-IOV enabled, we have to create VLAN interface
1683                          * to make hypervisor to setup E-Switch vport
1684                          * context correctly. We avoid creating the multiple
1685                          * VLAN interfaces, so we cannot support VLAN tag mask.
1686                          */
1687                         return rte_flow_error_set(error, EINVAL,
1688                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1689                                                   item,
1690                                                   "VLAN tag mask is not"
1691                                                   " supported in virtual"
1692                                                   " environment");
1693                 }
1694         }
1695         return 0;
1696 }
1697
1698 /*
1699  * GTP flags are contained in 1 byte of the format:
1700  * -------------------------------------------
1701  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1702  * |-----------------------------------------|
1703  * | value | Version | PT | Res | E | S | PN |
1704  * -------------------------------------------
1705  *
1706  * Matching is supported only for GTP flags E, S, PN.
1707  */
1708 #define MLX5_GTP_FLAGS_MASK     0x07
1709
1710 /**
1711  * Validate GTP item.
1712  *
1713  * @param[in] dev
1714  *   Pointer to the rte_eth_dev structure.
1715  * @param[in] item
1716  *   Item specification.
1717  * @param[in] item_flags
1718  *   Bit-fields that holds the items detected until now.
1719  * @param[out] error
1720  *   Pointer to error structure.
1721  *
1722  * @return
1723  *   0 on success, a negative errno value otherwise and rte_errno is set.
1724  */
1725 static int
1726 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1727                           const struct rte_flow_item *item,
1728                           uint64_t item_flags,
1729                           struct rte_flow_error *error)
1730 {
1731         struct mlx5_priv *priv = dev->data->dev_private;
1732         const struct rte_flow_item_gtp *spec = item->spec;
1733         const struct rte_flow_item_gtp *mask = item->mask;
1734         const struct rte_flow_item_gtp nic_mask = {
1735                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1736                 .msg_type = 0xff,
1737                 .teid = RTE_BE32(0xffffffff),
1738         };
1739
1740         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "GTP support is not enabled");
1744         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1745                 return rte_flow_error_set(error, ENOTSUP,
1746                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1747                                           "multiple tunnel layers not"
1748                                           " supported");
1749         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1750                 return rte_flow_error_set(error, EINVAL,
1751                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1752                                           "no outer UDP layer found");
1753         if (!mask)
1754                 mask = &rte_flow_item_gtp_mask;
1755         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1756                 return rte_flow_error_set(error, ENOTSUP,
1757                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1758                                           "Match is supported for GTP"
1759                                           " flags only");
1760         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1761                                          (const uint8_t *)&nic_mask,
1762                                          sizeof(struct rte_flow_item_gtp),
1763                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1764 }
1765
1766 /**
1767  * Validate GTP PSC item.
1768  *
1769  * @param[in] item
1770  *   Item specification.
1771  * @param[in] last_item
1772  *   Previous validated item in the pattern items.
1773  * @param[in] gtp_item
1774  *   Previous GTP item specification.
1775  * @param[in] attr
1776  *   Pointer to flow attributes.
1777  * @param[out] error
1778  *   Pointer to error structure.
1779  *
1780  * @return
1781  *   0 on success, a negative errno value otherwise and rte_errno is set.
1782  */
1783 static int
1784 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1785                               uint64_t last_item,
1786                               const struct rte_flow_item *gtp_item,
1787                               const struct rte_flow_attr *attr,
1788                               struct rte_flow_error *error)
1789 {
1790         const struct rte_flow_item_gtp *gtp_spec;
1791         const struct rte_flow_item_gtp *gtp_mask;
1792         const struct rte_flow_item_gtp_psc *spec;
1793         const struct rte_flow_item_gtp_psc *mask;
1794         const struct rte_flow_item_gtp_psc nic_mask = {
1795                 .pdu_type = 0xFF,
1796                 .qfi = 0xFF,
1797         };
1798
1799         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1800                 return rte_flow_error_set
1801                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1802                          "GTP PSC item must be preceded with GTP item");
1803         gtp_spec = gtp_item->spec;
1804         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1805         /* GTP spec and E flag is requested to match zero. */
1806         if (gtp_spec &&
1807                 (gtp_mask->v_pt_rsv_flags &
1808                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1809                 return rte_flow_error_set
1810                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1811                          "GTP E flag must be 1 to match GTP PSC");
1812         /* Check the flow is not created in group zero. */
1813         if (!attr->transfer && !attr->group)
1814                 return rte_flow_error_set
1815                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1816                          "GTP PSC is not supported for group 0");
1817         /* GTP spec is here and E flag is requested to match zero. */
1818         if (!item->spec)
1819                 return 0;
1820         spec = item->spec;
1821         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1822         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1823                 return rte_flow_error_set
1824                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1825                          "PDU type should be smaller than 16");
1826         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1827                                          (const uint8_t *)&nic_mask,
1828                                          sizeof(struct rte_flow_item_gtp_psc),
1829                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1830 }
1831
1832 /**
1833  * Validate IPV4 item.
1834  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1835  * add specific validation of fragment_offset field,
1836  *
1837  * @param[in] item
1838  *   Item specification.
1839  * @param[in] item_flags
1840  *   Bit-fields that holds the items detected until now.
1841  * @param[out] error
1842  *   Pointer to error structure.
1843  *
1844  * @return
1845  *   0 on success, a negative errno value otherwise and rte_errno is set.
1846  */
1847 static int
1848 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1849                            uint64_t item_flags,
1850                            uint64_t last_item,
1851                            uint16_t ether_type,
1852                            struct rte_flow_error *error)
1853 {
1854         int ret;
1855         const struct rte_flow_item_ipv4 *spec = item->spec;
1856         const struct rte_flow_item_ipv4 *last = item->last;
1857         const struct rte_flow_item_ipv4 *mask = item->mask;
1858         rte_be16_t fragment_offset_spec = 0;
1859         rte_be16_t fragment_offset_last = 0;
1860         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1861                 .hdr = {
1862                         .src_addr = RTE_BE32(0xffffffff),
1863                         .dst_addr = RTE_BE32(0xffffffff),
1864                         .type_of_service = 0xff,
1865                         .fragment_offset = RTE_BE16(0xffff),
1866                         .next_proto_id = 0xff,
1867                         .time_to_live = 0xff,
1868                 },
1869         };
1870
1871         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1872                                            ether_type, &nic_ipv4_mask,
1873                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1874         if (ret < 0)
1875                 return ret;
1876         if (spec && mask)
1877                 fragment_offset_spec = spec->hdr.fragment_offset &
1878                                        mask->hdr.fragment_offset;
1879         if (!fragment_offset_spec)
1880                 return 0;
1881         /*
1882          * spec and mask are valid, enforce using full mask to make sure the
1883          * complete value is used correctly.
1884          */
1885         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1886                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1887                 return rte_flow_error_set(error, EINVAL,
1888                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1889                                           item, "must use full mask for"
1890                                           " fragment_offset");
1891         /*
1892          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1893          * indicating this is 1st fragment of fragmented packet.
1894          * This is not yet supported in MLX5, return appropriate error message.
1895          */
1896         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1897                 return rte_flow_error_set(error, ENOTSUP,
1898                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1899                                           "match on first fragment not "
1900                                           "supported");
1901         if (fragment_offset_spec && !last)
1902                 return rte_flow_error_set(error, ENOTSUP,
1903                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1904                                           "specified value not supported");
1905         /* spec and last are valid, validate the specified range. */
1906         fragment_offset_last = last->hdr.fragment_offset &
1907                                mask->hdr.fragment_offset;
1908         /*
1909          * Match on fragment_offset spec 0x2001 and last 0x3fff
1910          * means MF is 1 and frag-offset is > 0.
1911          * This packet is fragment 2nd and onward, excluding last.
1912          * This is not yet supported in MLX5, return appropriate
1913          * error message.
1914          */
1915         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1916             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1917                 return rte_flow_error_set(error, ENOTSUP,
1918                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1919                                           last, "match on following "
1920                                           "fragments not supported");
1921         /*
1922          * Match on fragment_offset spec 0x0001 and last 0x1fff
1923          * means MF is 0 and frag-offset is > 0.
1924          * This packet is last fragment of fragmented packet.
1925          * This is not yet supported in MLX5, return appropriate
1926          * error message.
1927          */
1928         if (fragment_offset_spec == RTE_BE16(1) &&
1929             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1930                 return rte_flow_error_set(error, ENOTSUP,
1931                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1932                                           last, "match on last "
1933                                           "fragment not supported");
1934         /*
1935          * Match on fragment_offset spec 0x0001 and last 0x3fff
1936          * means MF and/or frag-offset is not 0.
1937          * This is a fragmented packet.
1938          * Other range values are invalid and rejected.
1939          */
1940         if (!(fragment_offset_spec == RTE_BE16(1) &&
1941               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1942                 return rte_flow_error_set(error, ENOTSUP,
1943                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1944                                           "specified range not supported");
1945         return 0;
1946 }
1947
1948 /**
1949  * Validate IPV6 fragment extension item.
1950  *
1951  * @param[in] item
1952  *   Item specification.
1953  * @param[in] item_flags
1954  *   Bit-fields that holds the items detected until now.
1955  * @param[out] error
1956  *   Pointer to error structure.
1957  *
1958  * @return
1959  *   0 on success, a negative errno value otherwise and rte_errno is set.
1960  */
1961 static int
1962 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1963                                     uint64_t item_flags,
1964                                     struct rte_flow_error *error)
1965 {
1966         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1967         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1968         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1969         rte_be16_t frag_data_spec = 0;
1970         rte_be16_t frag_data_last = 0;
1971         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1972         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1973                                       MLX5_FLOW_LAYER_OUTER_L4;
1974         int ret = 0;
1975         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1976                 .hdr = {
1977                         .next_header = 0xff,
1978                         .frag_data = RTE_BE16(0xffff),
1979                 },
1980         };
1981
1982         if (item_flags & l4m)
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1985                                           "ipv6 fragment extension item cannot "
1986                                           "follow L4 item.");
1987         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1988             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1989                 return rte_flow_error_set(error, EINVAL,
1990                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1991                                           "ipv6 fragment extension item must "
1992                                           "follow ipv6 item");
1993         if (spec && mask)
1994                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1995         if (!frag_data_spec)
1996                 return 0;
1997         /*
1998          * spec and mask are valid, enforce using full mask to make sure the
1999          * complete value is used correctly.
2000          */
2001         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2002                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2003                 return rte_flow_error_set(error, EINVAL,
2004                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2005                                           item, "must use full mask for"
2006                                           " frag_data");
2007         /*
2008          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2009          * This is 1st fragment of fragmented packet.
2010          */
2011         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2012                 return rte_flow_error_set(error, ENOTSUP,
2013                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2014                                           "match on first fragment not "
2015                                           "supported");
2016         if (frag_data_spec && !last)
2017                 return rte_flow_error_set(error, EINVAL,
2018                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2019                                           "specified value not supported");
2020         ret = mlx5_flow_item_acceptable
2021                                 (item, (const uint8_t *)mask,
2022                                  (const uint8_t *)&nic_mask,
2023                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2024                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2025         if (ret)
2026                 return ret;
2027         /* spec and last are valid, validate the specified range. */
2028         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2029         /*
2030          * Match on frag_data spec 0x0009 and last 0xfff9
2031          * means M is 1 and frag-offset is > 0.
2032          * This packet is fragment 2nd and onward, excluding last.
2033          * This is not yet supported in MLX5, return appropriate
2034          * error message.
2035          */
2036         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2037                                        RTE_IPV6_EHDR_MF_MASK) &&
2038             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2039                 return rte_flow_error_set(error, ENOTSUP,
2040                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2041                                           last, "match on following "
2042                                           "fragments not supported");
2043         /*
2044          * Match on frag_data spec 0x0008 and last 0xfff8
2045          * means M is 0 and frag-offset is > 0.
2046          * This packet is last fragment of fragmented packet.
2047          * This is not yet supported in MLX5, return appropriate
2048          * error message.
2049          */
2050         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2051             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2052                 return rte_flow_error_set(error, ENOTSUP,
2053                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2054                                           last, "match on last "
2055                                           "fragment not supported");
2056         /* Other range values are invalid and rejected. */
2057         return rte_flow_error_set(error, EINVAL,
2058                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2059                                   "specified range not supported");
2060 }
2061
2062 /**
2063  * Validate the pop VLAN action.
2064  *
2065  * @param[in] dev
2066  *   Pointer to the rte_eth_dev structure.
2067  * @param[in] action_flags
2068  *   Holds the actions detected until now.
2069  * @param[in] action
2070  *   Pointer to the pop vlan action.
2071  * @param[in] item_flags
2072  *   The items found in this flow rule.
2073  * @param[in] attr
2074  *   Pointer to flow attributes.
2075  * @param[out] error
2076  *   Pointer to error structure.
2077  *
2078  * @return
2079  *   0 on success, a negative errno value otherwise and rte_errno is set.
2080  */
2081 static int
2082 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2083                                  uint64_t action_flags,
2084                                  const struct rte_flow_action *action,
2085                                  uint64_t item_flags,
2086                                  const struct rte_flow_attr *attr,
2087                                  struct rte_flow_error *error)
2088 {
2089         const struct mlx5_priv *priv = dev->data->dev_private;
2090
2091         (void)action;
2092         (void)attr;
2093         if (!priv->sh->pop_vlan_action)
2094                 return rte_flow_error_set(error, ENOTSUP,
2095                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2096                                           NULL,
2097                                           "pop vlan action is not supported");
2098         if (attr->egress)
2099                 return rte_flow_error_set(error, ENOTSUP,
2100                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2101                                           NULL,
2102                                           "pop vlan action not supported for "
2103                                           "egress");
2104         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2105                 return rte_flow_error_set(error, ENOTSUP,
2106                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2107                                           "no support for multiple VLAN "
2108                                           "actions");
2109         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2110         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2111             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2112                 return rte_flow_error_set(error, ENOTSUP,
2113                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2114                                           NULL,
2115                                           "cannot pop vlan after decap without "
2116                                           "match on inner vlan in the flow");
2117         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2118         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2119             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2120                 return rte_flow_error_set(error, ENOTSUP,
2121                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2122                                           NULL,
2123                                           "cannot pop vlan without a "
2124                                           "match on (outer) vlan in the flow");
2125         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2126                 return rte_flow_error_set(error, EINVAL,
2127                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2128                                           "wrong action order, port_id should "
2129                                           "be after pop VLAN action");
2130         if (!attr->transfer && priv->representor)
2131                 return rte_flow_error_set(error, ENOTSUP,
2132                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2133                                           "pop vlan action for VF representor "
2134                                           "not supported on NIC table");
2135         return 0;
2136 }
2137
2138 /**
2139  * Get VLAN default info from vlan match info.
2140  *
2141  * @param[in] items
2142  *   the list of item specifications.
2143  * @param[out] vlan
2144  *   pointer VLAN info to fill to.
2145  *
2146  * @return
2147  *   0 on success, a negative errno value otherwise and rte_errno is set.
2148  */
2149 static void
2150 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2151                                   struct rte_vlan_hdr *vlan)
2152 {
2153         const struct rte_flow_item_vlan nic_mask = {
2154                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2155                                 MLX5DV_FLOW_VLAN_VID_MASK),
2156                 .inner_type = RTE_BE16(0xffff),
2157         };
2158
2159         if (items == NULL)
2160                 return;
2161         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2162                 int type = items->type;
2163
2164                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2165                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2166                         break;
2167         }
2168         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2169                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2170                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2171
2172                 /* If VLAN item in pattern doesn't contain data, return here. */
2173                 if (!vlan_v)
2174                         return;
2175                 if (!vlan_m)
2176                         vlan_m = &nic_mask;
2177                 /* Only full match values are accepted */
2178                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2179                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2180                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2181                         vlan->vlan_tci |=
2182                                 rte_be_to_cpu_16(vlan_v->tci &
2183                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2184                 }
2185                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2186                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2187                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2188                         vlan->vlan_tci |=
2189                                 rte_be_to_cpu_16(vlan_v->tci &
2190                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2191                 }
2192                 if (vlan_m->inner_type == nic_mask.inner_type)
2193                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2194                                                            vlan_m->inner_type);
2195         }
2196 }
2197
2198 /**
2199  * Validate the push VLAN action.
2200  *
2201  * @param[in] dev
2202  *   Pointer to the rte_eth_dev structure.
2203  * @param[in] action_flags
2204  *   Holds the actions detected until now.
2205  * @param[in] item_flags
2206  *   The items found in this flow rule.
2207  * @param[in] action
2208  *   Pointer to the action structure.
2209  * @param[in] attr
2210  *   Pointer to flow attributes
2211  * @param[out] error
2212  *   Pointer to error structure.
2213  *
2214  * @return
2215  *   0 on success, a negative errno value otherwise and rte_errno is set.
2216  */
2217 static int
2218 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2219                                   uint64_t action_flags,
2220                                   const struct rte_flow_item_vlan *vlan_m,
2221                                   const struct rte_flow_action *action,
2222                                   const struct rte_flow_attr *attr,
2223                                   struct rte_flow_error *error)
2224 {
2225         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2226         const struct mlx5_priv *priv = dev->data->dev_private;
2227
2228         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2229             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2230                 return rte_flow_error_set(error, EINVAL,
2231                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2232                                           "invalid vlan ethertype");
2233         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2234                 return rte_flow_error_set(error, EINVAL,
2235                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2236                                           "wrong action order, port_id should "
2237                                           "be after push VLAN");
2238         if (!attr->transfer && priv->representor)
2239                 return rte_flow_error_set(error, ENOTSUP,
2240                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2241                                           "push vlan action for VF representor "
2242                                           "not supported on NIC table");
2243         if (vlan_m &&
2244             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2245             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2246                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2247             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2248             !(mlx5_flow_find_action
2249                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2250                 return rte_flow_error_set(error, EINVAL,
2251                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2252                                           "not full match mask on VLAN PCP and "
2253                                           "there is no of_set_vlan_pcp action, "
2254                                           "push VLAN action cannot figure out "
2255                                           "PCP value");
2256         if (vlan_m &&
2257             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2258             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2259                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2260             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2261             !(mlx5_flow_find_action
2262                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2263                 return rte_flow_error_set(error, EINVAL,
2264                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2265                                           "not full match mask on VLAN VID and "
2266                                           "there is no of_set_vlan_vid action, "
2267                                           "push VLAN action cannot figure out "
2268                                           "VID value");
2269         (void)attr;
2270         return 0;
2271 }
2272
2273 /**
2274  * Validate the set VLAN PCP.
2275  *
2276  * @param[in] action_flags
2277  *   Holds the actions detected until now.
2278  * @param[in] actions
2279  *   Pointer to the list of actions remaining in the flow rule.
2280  * @param[out] error
2281  *   Pointer to error structure.
2282  *
2283  * @return
2284  *   0 on success, a negative errno value otherwise and rte_errno is set.
2285  */
2286 static int
2287 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2288                                      const struct rte_flow_action actions[],
2289                                      struct rte_flow_error *error)
2290 {
2291         const struct rte_flow_action *action = actions;
2292         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2293
2294         if (conf->vlan_pcp > 7)
2295                 return rte_flow_error_set(error, EINVAL,
2296                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2297                                           "VLAN PCP value is too big");
2298         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2299                 return rte_flow_error_set(error, ENOTSUP,
2300                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2301                                           "set VLAN PCP action must follow "
2302                                           "the push VLAN action");
2303         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2304                 return rte_flow_error_set(error, ENOTSUP,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "Multiple VLAN PCP modification are "
2307                                           "not supported");
2308         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "wrong action order, port_id should "
2312                                           "be after set VLAN PCP");
2313         return 0;
2314 }
2315
2316 /**
2317  * Validate the set VLAN VID.
2318  *
2319  * @param[in] item_flags
2320  *   Holds the items detected in this rule.
2321  * @param[in] action_flags
2322  *   Holds the actions detected until now.
2323  * @param[in] actions
2324  *   Pointer to the list of actions remaining in the flow rule.
2325  * @param[out] error
2326  *   Pointer to error structure.
2327  *
2328  * @return
2329  *   0 on success, a negative errno value otherwise and rte_errno is set.
2330  */
2331 static int
2332 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2333                                      uint64_t action_flags,
2334                                      const struct rte_flow_action actions[],
2335                                      struct rte_flow_error *error)
2336 {
2337         const struct rte_flow_action *action = actions;
2338         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2339
2340         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2341                 return rte_flow_error_set(error, EINVAL,
2342                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2343                                           "VLAN VID value is too big");
2344         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2345             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2346                 return rte_flow_error_set(error, ENOTSUP,
2347                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2348                                           "set VLAN VID action must follow push"
2349                                           " VLAN action or match on VLAN item");
2350         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2351                 return rte_flow_error_set(error, ENOTSUP,
2352                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2353                                           "Multiple VLAN VID modifications are "
2354                                           "not supported");
2355         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2356                 return rte_flow_error_set(error, EINVAL,
2357                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2358                                           "wrong action order, port_id should "
2359                                           "be after set VLAN VID");
2360         return 0;
2361 }
2362
2363 /*
2364  * Validate the FLAG action.
2365  *
2366  * @param[in] dev
2367  *   Pointer to the rte_eth_dev structure.
2368  * @param[in] action_flags
2369  *   Holds the actions detected until now.
2370  * @param[in] attr
2371  *   Pointer to flow attributes
2372  * @param[out] error
2373  *   Pointer to error structure.
2374  *
2375  * @return
2376  *   0 on success, a negative errno value otherwise and rte_errno is set.
2377  */
2378 static int
2379 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2380                              uint64_t action_flags,
2381                              const struct rte_flow_attr *attr,
2382                              struct rte_flow_error *error)
2383 {
2384         struct mlx5_priv *priv = dev->data->dev_private;
2385         struct mlx5_dev_config *config = &priv->config;
2386         int ret;
2387
2388         /* Fall back if no extended metadata register support. */
2389         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2390                 return mlx5_flow_validate_action_flag(action_flags, attr,
2391                                                       error);
2392         /* Extensive metadata mode requires registers. */
2393         if (!mlx5_flow_ext_mreg_supported(dev))
2394                 return rte_flow_error_set(error, ENOTSUP,
2395                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2396                                           "no metadata registers "
2397                                           "to support flag action");
2398         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2399                 return rte_flow_error_set(error, ENOTSUP,
2400                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2401                                           "extended metadata register"
2402                                           " isn't available");
2403         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2404         if (ret < 0)
2405                 return ret;
2406         MLX5_ASSERT(ret > 0);
2407         if (action_flags & MLX5_FLOW_ACTION_MARK)
2408                 return rte_flow_error_set(error, EINVAL,
2409                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410                                           "can't mark and flag in same flow");
2411         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2412                 return rte_flow_error_set(error, EINVAL,
2413                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2414                                           "can't have 2 flag"
2415                                           " actions in same flow");
2416         return 0;
2417 }
2418
2419 /**
2420  * Validate MARK action.
2421  *
2422  * @param[in] dev
2423  *   Pointer to the rte_eth_dev structure.
2424  * @param[in] action
2425  *   Pointer to action.
2426  * @param[in] action_flags
2427  *   Holds the actions detected until now.
2428  * @param[in] attr
2429  *   Pointer to flow attributes
2430  * @param[out] error
2431  *   Pointer to error structure.
2432  *
2433  * @return
2434  *   0 on success, a negative errno value otherwise and rte_errno is set.
2435  */
2436 static int
2437 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2438                              const struct rte_flow_action *action,
2439                              uint64_t action_flags,
2440                              const struct rte_flow_attr *attr,
2441                              struct rte_flow_error *error)
2442 {
2443         struct mlx5_priv *priv = dev->data->dev_private;
2444         struct mlx5_dev_config *config = &priv->config;
2445         const struct rte_flow_action_mark *mark = action->conf;
2446         int ret;
2447
2448         if (is_tunnel_offload_active(dev))
2449                 return rte_flow_error_set(error, ENOTSUP,
2450                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2451                                           "no mark action "
2452                                           "if tunnel offload active");
2453         /* Fall back if no extended metadata register support. */
2454         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2455                 return mlx5_flow_validate_action_mark(action, action_flags,
2456                                                       attr, error);
2457         /* Extensive metadata mode requires registers. */
2458         if (!mlx5_flow_ext_mreg_supported(dev))
2459                 return rte_flow_error_set(error, ENOTSUP,
2460                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2461                                           "no metadata registers "
2462                                           "to support mark action");
2463         if (!priv->sh->dv_mark_mask)
2464                 return rte_flow_error_set(error, ENOTSUP,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2466                                           "extended metadata register"
2467                                           " isn't available");
2468         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2469         if (ret < 0)
2470                 return ret;
2471         MLX5_ASSERT(ret > 0);
2472         if (!mark)
2473                 return rte_flow_error_set(error, EINVAL,
2474                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2475                                           "configuration cannot be null");
2476         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2477                 return rte_flow_error_set(error, EINVAL,
2478                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2479                                           &mark->id,
2480                                           "mark id exceeds the limit");
2481         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2482                 return rte_flow_error_set(error, EINVAL,
2483                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2484                                           "can't flag and mark in same flow");
2485         if (action_flags & MLX5_FLOW_ACTION_MARK)
2486                 return rte_flow_error_set(error, EINVAL,
2487                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2488                                           "can't have 2 mark actions in same"
2489                                           " flow");
2490         return 0;
2491 }
2492
2493 /**
2494  * Validate SET_META action.
2495  *
2496  * @param[in] dev
2497  *   Pointer to the rte_eth_dev structure.
2498  * @param[in] action
2499  *   Pointer to the action structure.
2500  * @param[in] action_flags
2501  *   Holds the actions detected until now.
2502  * @param[in] attr
2503  *   Pointer to flow attributes
2504  * @param[out] error
2505  *   Pointer to error structure.
2506  *
2507  * @return
2508  *   0 on success, a negative errno value otherwise and rte_errno is set.
2509  */
2510 static int
2511 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2512                                  const struct rte_flow_action *action,
2513                                  uint64_t action_flags __rte_unused,
2514                                  const struct rte_flow_attr *attr,
2515                                  struct rte_flow_error *error)
2516 {
2517         const struct rte_flow_action_set_meta *conf;
2518         uint32_t nic_mask = UINT32_MAX;
2519         int reg;
2520
2521         if (!mlx5_flow_ext_mreg_supported(dev))
2522                 return rte_flow_error_set(error, ENOTSUP,
2523                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2524                                           "extended metadata register"
2525                                           " isn't supported");
2526         reg = flow_dv_get_metadata_reg(dev, attr, error);
2527         if (reg < 0)
2528                 return reg;
2529         if (reg == REG_NON)
2530                 return rte_flow_error_set(error, ENOTSUP,
2531                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2532                                           "unavalable extended metadata register");
2533         if (reg != REG_A && reg != REG_B) {
2534                 struct mlx5_priv *priv = dev->data->dev_private;
2535
2536                 nic_mask = priv->sh->dv_meta_mask;
2537         }
2538         if (!(action->conf))
2539                 return rte_flow_error_set(error, EINVAL,
2540                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2541                                           "configuration cannot be null");
2542         conf = (const struct rte_flow_action_set_meta *)action->conf;
2543         if (!conf->mask)
2544                 return rte_flow_error_set(error, EINVAL,
2545                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2546                                           "zero mask doesn't have any effect");
2547         if (conf->mask & ~nic_mask)
2548                 return rte_flow_error_set(error, EINVAL,
2549                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2550                                           "meta data must be within reg C0");
2551         return 0;
2552 }
2553
2554 /**
2555  * Validate SET_TAG action.
2556  *
2557  * @param[in] dev
2558  *   Pointer to the rte_eth_dev structure.
2559  * @param[in] action
2560  *   Pointer to the action structure.
2561  * @param[in] action_flags
2562  *   Holds the actions detected until now.
2563  * @param[in] attr
2564  *   Pointer to flow attributes
2565  * @param[out] error
2566  *   Pointer to error structure.
2567  *
2568  * @return
2569  *   0 on success, a negative errno value otherwise and rte_errno is set.
2570  */
2571 static int
2572 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2573                                 const struct rte_flow_action *action,
2574                                 uint64_t action_flags,
2575                                 const struct rte_flow_attr *attr,
2576                                 struct rte_flow_error *error)
2577 {
2578         const struct rte_flow_action_set_tag *conf;
2579         const uint64_t terminal_action_flags =
2580                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2581                 MLX5_FLOW_ACTION_RSS;
2582         int ret;
2583
2584         if (!mlx5_flow_ext_mreg_supported(dev))
2585                 return rte_flow_error_set(error, ENOTSUP,
2586                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2587                                           "extensive metadata register"
2588                                           " isn't supported");
2589         if (!(action->conf))
2590                 return rte_flow_error_set(error, EINVAL,
2591                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2592                                           "configuration cannot be null");
2593         conf = (const struct rte_flow_action_set_tag *)action->conf;
2594         if (!conf->mask)
2595                 return rte_flow_error_set(error, EINVAL,
2596                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2597                                           "zero mask doesn't have any effect");
2598         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2599         if (ret < 0)
2600                 return ret;
2601         if (!attr->transfer && attr->ingress &&
2602             (action_flags & terminal_action_flags))
2603                 return rte_flow_error_set(error, EINVAL,
2604                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2605                                           "set_tag has no effect"
2606                                           " with terminal actions");
2607         return 0;
2608 }
2609
2610 /**
2611  * Validate count action.
2612  *
2613  * @param[in] dev
2614  *   Pointer to rte_eth_dev structure.
2615  * @param[out] error
2616  *   Pointer to error structure.
2617  *
2618  * @return
2619  *   0 on success, a negative errno value otherwise and rte_errno is set.
2620  */
2621 static int
2622 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2623                               struct rte_flow_error *error)
2624 {
2625         struct mlx5_priv *priv = dev->data->dev_private;
2626
2627         if (!priv->config.devx)
2628                 goto notsup_err;
2629 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2630         return 0;
2631 #endif
2632 notsup_err:
2633         return rte_flow_error_set
2634                       (error, ENOTSUP,
2635                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2636                        NULL,
2637                        "count action not supported");
2638 }
2639
2640 /**
2641  * Validate the L2 encap action.
2642  *
2643  * @param[in] dev
2644  *   Pointer to the rte_eth_dev structure.
2645  * @param[in] action_flags
2646  *   Holds the actions detected until now.
2647  * @param[in] action
2648  *   Pointer to the action structure.
2649  * @param[in] attr
2650  *   Pointer to flow attributes.
2651  * @param[out] error
2652  *   Pointer to error structure.
2653  *
2654  * @return
2655  *   0 on success, a negative errno value otherwise and rte_errno is set.
2656  */
2657 static int
2658 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2659                                  uint64_t action_flags,
2660                                  const struct rte_flow_action *action,
2661                                  const struct rte_flow_attr *attr,
2662                                  struct rte_flow_error *error)
2663 {
2664         const struct mlx5_priv *priv = dev->data->dev_private;
2665
2666         if (!(action->conf))
2667                 return rte_flow_error_set(error, EINVAL,
2668                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2669                                           "configuration cannot be null");
2670         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2671                 return rte_flow_error_set(error, EINVAL,
2672                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2673                                           "can only have a single encap action "
2674                                           "in a flow");
2675         if (!attr->transfer && priv->representor)
2676                 return rte_flow_error_set(error, ENOTSUP,
2677                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2678                                           "encap action for VF representor "
2679                                           "not supported on NIC table");
2680         return 0;
2681 }
2682
2683 /**
2684  * Validate a decap action.
2685  *
2686  * @param[in] dev
2687  *   Pointer to the rte_eth_dev structure.
2688  * @param[in] action_flags
2689  *   Holds the actions detected until now.
2690  * @param[in] action
2691  *   Pointer to the action structure.
2692  * @param[in] item_flags
2693  *   Holds the items detected.
2694  * @param[in] attr
2695  *   Pointer to flow attributes
2696  * @param[out] error
2697  *   Pointer to error structure.
2698  *
2699  * @return
2700  *   0 on success, a negative errno value otherwise and rte_errno is set.
2701  */
2702 static int
2703 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2704                               uint64_t action_flags,
2705                               const struct rte_flow_action *action,
2706                               const uint64_t item_flags,
2707                               const struct rte_flow_attr *attr,
2708                               struct rte_flow_error *error)
2709 {
2710         const struct mlx5_priv *priv = dev->data->dev_private;
2711
2712         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2713             !priv->config.decap_en)
2714                 return rte_flow_error_set(error, ENOTSUP,
2715                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2716                                           "decap is not enabled");
2717         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2718                 return rte_flow_error_set(error, ENOTSUP,
2719                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2720                                           action_flags &
2721                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2722                                           "have a single decap action" : "decap "
2723                                           "after encap is not supported");
2724         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2725                 return rte_flow_error_set(error, EINVAL,
2726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2727                                           "can't have decap action after"
2728                                           " modify action");
2729         if (attr->egress)
2730                 return rte_flow_error_set(error, ENOTSUP,
2731                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2732                                           NULL,
2733                                           "decap action not supported for "
2734                                           "egress");
2735         if (!attr->transfer && priv->representor)
2736                 return rte_flow_error_set(error, ENOTSUP,
2737                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2738                                           "decap action for VF representor "
2739                                           "not supported on NIC table");
2740         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2741             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2742                 return rte_flow_error_set(error, ENOTSUP,
2743                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2744                                 "VXLAN item should be present for VXLAN decap");
2745         return 0;
2746 }
2747
2748 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2749
2750 /**
2751  * Validate the raw encap and decap actions.
2752  *
2753  * @param[in] dev
2754  *   Pointer to the rte_eth_dev structure.
2755  * @param[in] decap
2756  *   Pointer to the decap action.
2757  * @param[in] encap
2758  *   Pointer to the encap action.
2759  * @param[in] attr
2760  *   Pointer to flow attributes
2761  * @param[in/out] action_flags
2762  *   Holds the actions detected until now.
2763  * @param[out] actions_n
2764  *   pointer to the number of actions counter.
2765  * @param[in] action
2766  *   Pointer to the action structure.
2767  * @param[in] item_flags
2768  *   Holds the items detected.
2769  * @param[out] error
2770  *   Pointer to error structure.
2771  *
2772  * @return
2773  *   0 on success, a negative errno value otherwise and rte_errno is set.
2774  */
2775 static int
2776 flow_dv_validate_action_raw_encap_decap
2777         (struct rte_eth_dev *dev,
2778          const struct rte_flow_action_raw_decap *decap,
2779          const struct rte_flow_action_raw_encap *encap,
2780          const struct rte_flow_attr *attr, uint64_t *action_flags,
2781          int *actions_n, const struct rte_flow_action *action,
2782          uint64_t item_flags, struct rte_flow_error *error)
2783 {
2784         const struct mlx5_priv *priv = dev->data->dev_private;
2785         int ret;
2786
2787         if (encap && (!encap->size || !encap->data))
2788                 return rte_flow_error_set(error, EINVAL,
2789                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2790                                           "raw encap data cannot be empty");
2791         if (decap && encap) {
2792                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2793                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2794                         /* L3 encap. */
2795                         decap = NULL;
2796                 else if (encap->size <=
2797                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2798                            decap->size >
2799                            MLX5_ENCAPSULATION_DECISION_SIZE)
2800                         /* L3 decap. */
2801                         encap = NULL;
2802                 else if (encap->size >
2803                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2804                            decap->size >
2805                            MLX5_ENCAPSULATION_DECISION_SIZE)
2806                         /* 2 L2 actions: encap and decap. */
2807                         ;
2808                 else
2809                         return rte_flow_error_set(error,
2810                                 ENOTSUP,
2811                                 RTE_FLOW_ERROR_TYPE_ACTION,
2812                                 NULL, "unsupported too small "
2813                                 "raw decap and too small raw "
2814                                 "encap combination");
2815         }
2816         if (decap) {
2817                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2818                                                     item_flags, attr, error);
2819                 if (ret < 0)
2820                         return ret;
2821                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2822                 ++(*actions_n);
2823         }
2824         if (encap) {
2825                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2826                         return rte_flow_error_set(error, ENOTSUP,
2827                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2828                                                   NULL,
2829                                                   "small raw encap size");
2830                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2831                         return rte_flow_error_set(error, EINVAL,
2832                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2833                                                   NULL,
2834                                                   "more than one encap action");
2835                 if (!attr->transfer && priv->representor)
2836                         return rte_flow_error_set
2837                                         (error, ENOTSUP,
2838                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2839                                          "encap action for VF representor "
2840                                          "not supported on NIC table");
2841                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2842                 ++(*actions_n);
2843         }
2844         return 0;
2845 }
2846
2847 /**
2848  * Match encap_decap resource.
2849  *
2850  * @param list
2851  *   Pointer to the hash list.
2852  * @param entry
2853  *   Pointer to exist resource entry object.
2854  * @param key
2855  *   Key of the new entry.
2856  * @param ctx_cb
2857  *   Pointer to new encap_decap resource.
2858  *
2859  * @return
2860  *   0 on matching, none-zero otherwise.
2861  */
2862 int
2863 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2864                              struct mlx5_hlist_entry *entry,
2865                              uint64_t key __rte_unused, void *cb_ctx)
2866 {
2867         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2868         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2869         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2870
2871         cache_resource = container_of(entry,
2872                                       struct mlx5_flow_dv_encap_decap_resource,
2873                                       entry);
2874         if (resource->reformat_type == cache_resource->reformat_type &&
2875             resource->ft_type == cache_resource->ft_type &&
2876             resource->flags == cache_resource->flags &&
2877             resource->size == cache_resource->size &&
2878             !memcmp((const void *)resource->buf,
2879                     (const void *)cache_resource->buf,
2880                     resource->size))
2881                 return 0;
2882         return -1;
2883 }
2884
2885 /**
2886  * Allocate encap_decap resource.
2887  *
2888  * @param list
2889  *   Pointer to the hash list.
2890  * @param entry
2891  *   Pointer to exist resource entry object.
2892  * @param ctx_cb
2893  *   Pointer to new encap_decap resource.
2894  *
2895  * @return
2896  *   0 on matching, none-zero otherwise.
2897  */
2898 struct mlx5_hlist_entry *
2899 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2900                               uint64_t key __rte_unused,
2901                               void *cb_ctx)
2902 {
2903         struct mlx5_dev_ctx_shared *sh = list->ctx;
2904         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2905         struct mlx5dv_dr_domain *domain;
2906         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2907         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2908         uint32_t idx;
2909         int ret;
2910
2911         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2912                 domain = sh->fdb_domain;
2913         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2914                 domain = sh->rx_domain;
2915         else
2916                 domain = sh->tx_domain;
2917         /* Register new encap/decap resource. */
2918         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2919                                        &idx);
2920         if (!cache_resource) {
2921                 rte_flow_error_set(ctx->error, ENOMEM,
2922                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2923                                    "cannot allocate resource memory");
2924                 return NULL;
2925         }
2926         *cache_resource = *resource;
2927         cache_resource->idx = idx;
2928         ret = mlx5_flow_os_create_flow_action_packet_reformat
2929                                         (sh->ctx, domain, cache_resource,
2930                                          &cache_resource->action);
2931         if (ret) {
2932                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2933                 rte_flow_error_set(ctx->error, ENOMEM,
2934                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2935                                    NULL, "cannot create action");
2936                 return NULL;
2937         }
2938
2939         return &cache_resource->entry;
2940 }
2941
2942 /**
2943  * Find existing encap/decap resource or create and register a new one.
2944  *
2945  * @param[in, out] dev
2946  *   Pointer to rte_eth_dev structure.
2947  * @param[in, out] resource
2948  *   Pointer to encap/decap resource.
2949  * @parm[in, out] dev_flow
2950  *   Pointer to the dev_flow.
2951  * @param[out] error
2952  *   pointer to error structure.
2953  *
2954  * @return
2955  *   0 on success otherwise -errno and errno is set.
2956  */
2957 static int
2958 flow_dv_encap_decap_resource_register
2959                         (struct rte_eth_dev *dev,
2960                          struct mlx5_flow_dv_encap_decap_resource *resource,
2961                          struct mlx5_flow *dev_flow,
2962                          struct rte_flow_error *error)
2963 {
2964         struct mlx5_priv *priv = dev->data->dev_private;
2965         struct mlx5_dev_ctx_shared *sh = priv->sh;
2966         struct mlx5_hlist_entry *entry;
2967         union {
2968                 struct {
2969                         uint32_t ft_type:8;
2970                         uint32_t refmt_type:8;
2971                         /*
2972                          * Header reformat actions can be shared between
2973                          * non-root tables. One bit to indicate non-root
2974                          * table or not.
2975                          */
2976                         uint32_t is_root:1;
2977                         uint32_t reserve:15;
2978                 };
2979                 uint32_t v32;
2980         } encap_decap_key = {
2981                 {
2982                         .ft_type = resource->ft_type,
2983                         .refmt_type = resource->reformat_type,
2984                         .is_root = !!dev_flow->dv.group,
2985                         .reserve = 0,
2986                 }
2987         };
2988         struct mlx5_flow_cb_ctx ctx = {
2989                 .error = error,
2990                 .data = resource,
2991         };
2992         uint64_t key64;
2993
2994         resource->flags = dev_flow->dv.group ? 0 : 1;
2995         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2996                                  sizeof(encap_decap_key.v32), 0);
2997         if (resource->reformat_type !=
2998             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2999             resource->size)
3000                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3001         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3002         if (!entry)
3003                 return -rte_errno;
3004         resource = container_of(entry, typeof(*resource), entry);
3005         dev_flow->dv.encap_decap = resource;
3006         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3007         return 0;
3008 }
3009
3010 /**
3011  * Find existing table jump resource or create and register a new one.
3012  *
3013  * @param[in, out] dev
3014  *   Pointer to rte_eth_dev structure.
3015  * @param[in, out] tbl
3016  *   Pointer to flow table resource.
3017  * @parm[in, out] dev_flow
3018  *   Pointer to the dev_flow.
3019  * @param[out] error
3020  *   pointer to error structure.
3021  *
3022  * @return
3023  *   0 on success otherwise -errno and errno is set.
3024  */
3025 static int
3026 flow_dv_jump_tbl_resource_register
3027                         (struct rte_eth_dev *dev __rte_unused,
3028                          struct mlx5_flow_tbl_resource *tbl,
3029                          struct mlx5_flow *dev_flow,
3030                          struct rte_flow_error *error __rte_unused)
3031 {
3032         struct mlx5_flow_tbl_data_entry *tbl_data =
3033                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3034
3035         MLX5_ASSERT(tbl);
3036         MLX5_ASSERT(tbl_data->jump.action);
3037         dev_flow->handle->rix_jump = tbl_data->idx;
3038         dev_flow->dv.jump = &tbl_data->jump;
3039         return 0;
3040 }
3041
3042 int
3043 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3044                          struct mlx5_cache_entry *entry, void *cb_ctx)
3045 {
3046         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3047         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3048         struct mlx5_flow_dv_port_id_action_resource *res =
3049                         container_of(entry, typeof(*res), entry);
3050
3051         return ref->port_id != res->port_id;
3052 }
3053
3054 struct mlx5_cache_entry *
3055 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3056                           struct mlx5_cache_entry *entry __rte_unused,
3057                           void *cb_ctx)
3058 {
3059         struct mlx5_dev_ctx_shared *sh = list->ctx;
3060         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3061         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3062         struct mlx5_flow_dv_port_id_action_resource *cache;
3063         uint32_t idx;
3064         int ret;
3065
3066         /* Register new port id action resource. */
3067         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3068         if (!cache) {
3069                 rte_flow_error_set(ctx->error, ENOMEM,
3070                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3071                                    "cannot allocate port_id action cache memory");
3072                 return NULL;
3073         }
3074         *cache = *ref;
3075         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3076                                                         ref->port_id,
3077                                                         &cache->action);
3078         if (ret) {
3079                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3080                 rte_flow_error_set(ctx->error, ENOMEM,
3081                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3082                                    "cannot create action");
3083                 return NULL;
3084         }
3085         return &cache->entry;
3086 }
3087
3088 /**
3089  * Find existing table port ID resource or create and register a new one.
3090  *
3091  * @param[in, out] dev
3092  *   Pointer to rte_eth_dev structure.
3093  * @param[in, out] resource
3094  *   Pointer to port ID action resource.
3095  * @parm[in, out] dev_flow
3096  *   Pointer to the dev_flow.
3097  * @param[out] error
3098  *   pointer to error structure.
3099  *
3100  * @return
3101  *   0 on success otherwise -errno and errno is set.
3102  */
3103 static int
3104 flow_dv_port_id_action_resource_register
3105                         (struct rte_eth_dev *dev,
3106                          struct mlx5_flow_dv_port_id_action_resource *resource,
3107                          struct mlx5_flow *dev_flow,
3108                          struct rte_flow_error *error)
3109 {
3110         struct mlx5_priv *priv = dev->data->dev_private;
3111         struct mlx5_cache_entry *entry;
3112         struct mlx5_flow_dv_port_id_action_resource *cache;
3113         struct mlx5_flow_cb_ctx ctx = {
3114                 .error = error,
3115                 .data = resource,
3116         };
3117
3118         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3119         if (!entry)
3120                 return -rte_errno;
3121         cache = container_of(entry, typeof(*cache), entry);
3122         dev_flow->dv.port_id_action = cache;
3123         dev_flow->handle->rix_port_id_action = cache->idx;
3124         return 0;
3125 }
3126
3127 int
3128 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3129                          struct mlx5_cache_entry *entry, void *cb_ctx)
3130 {
3131         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3132         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3133         struct mlx5_flow_dv_push_vlan_action_resource *res =
3134                         container_of(entry, typeof(*res), entry);
3135
3136         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3137 }
3138
3139 struct mlx5_cache_entry *
3140 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3141                           struct mlx5_cache_entry *entry __rte_unused,
3142                           void *cb_ctx)
3143 {
3144         struct mlx5_dev_ctx_shared *sh = list->ctx;
3145         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3146         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3147         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3148         struct mlx5dv_dr_domain *domain;
3149         uint32_t idx;
3150         int ret;
3151
3152         /* Register new port id action resource. */
3153         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3154         if (!cache) {
3155                 rte_flow_error_set(ctx->error, ENOMEM,
3156                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3157                                    "cannot allocate push_vlan action cache memory");
3158                 return NULL;
3159         }
3160         *cache = *ref;
3161         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3162                 domain = sh->fdb_domain;
3163         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3164                 domain = sh->rx_domain;
3165         else
3166                 domain = sh->tx_domain;
3167         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3168                                                         &cache->action);
3169         if (ret) {
3170                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3171                 rte_flow_error_set(ctx->error, ENOMEM,
3172                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173                                    "cannot create push vlan action");
3174                 return NULL;
3175         }
3176         return &cache->entry;
3177 }
3178
3179 /**
3180  * Find existing push vlan resource or create and register a new one.
3181  *
3182  * @param [in, out] dev
3183  *   Pointer to rte_eth_dev structure.
3184  * @param[in, out] resource
3185  *   Pointer to port ID action resource.
3186  * @parm[in, out] dev_flow
3187  *   Pointer to the dev_flow.
3188  * @param[out] error
3189  *   pointer to error structure.
3190  *
3191  * @return
3192  *   0 on success otherwise -errno and errno is set.
3193  */
3194 static int
3195 flow_dv_push_vlan_action_resource_register
3196                        (struct rte_eth_dev *dev,
3197                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3198                         struct mlx5_flow *dev_flow,
3199                         struct rte_flow_error *error)
3200 {
3201         struct mlx5_priv *priv = dev->data->dev_private;
3202         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3203         struct mlx5_cache_entry *entry;
3204         struct mlx5_flow_cb_ctx ctx = {
3205                 .error = error,
3206                 .data = resource,
3207         };
3208
3209         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3210         if (!entry)
3211                 return -rte_errno;
3212         cache = container_of(entry, typeof(*cache), entry);
3213
3214         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3215         dev_flow->dv.push_vlan_res = cache;
3216         return 0;
3217 }
3218
3219 /**
3220  * Get the size of specific rte_flow_item_type hdr size
3221  *
3222  * @param[in] item_type
3223  *   Tested rte_flow_item_type.
3224  *
3225  * @return
3226  *   sizeof struct item_type, 0 if void or irrelevant.
3227  */
3228 static size_t
3229 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3230 {
3231         size_t retval;
3232
3233         switch (item_type) {
3234         case RTE_FLOW_ITEM_TYPE_ETH:
3235                 retval = sizeof(struct rte_ether_hdr);
3236                 break;
3237         case RTE_FLOW_ITEM_TYPE_VLAN:
3238                 retval = sizeof(struct rte_vlan_hdr);
3239                 break;
3240         case RTE_FLOW_ITEM_TYPE_IPV4:
3241                 retval = sizeof(struct rte_ipv4_hdr);
3242                 break;
3243         case RTE_FLOW_ITEM_TYPE_IPV6:
3244                 retval = sizeof(struct rte_ipv6_hdr);
3245                 break;
3246         case RTE_FLOW_ITEM_TYPE_UDP:
3247                 retval = sizeof(struct rte_udp_hdr);
3248                 break;
3249         case RTE_FLOW_ITEM_TYPE_TCP:
3250                 retval = sizeof(struct rte_tcp_hdr);
3251                 break;
3252         case RTE_FLOW_ITEM_TYPE_VXLAN:
3253         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3254                 retval = sizeof(struct rte_vxlan_hdr);
3255                 break;
3256         case RTE_FLOW_ITEM_TYPE_GRE:
3257         case RTE_FLOW_ITEM_TYPE_NVGRE:
3258                 retval = sizeof(struct rte_gre_hdr);
3259                 break;
3260         case RTE_FLOW_ITEM_TYPE_MPLS:
3261                 retval = sizeof(struct rte_mpls_hdr);
3262                 break;
3263         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3264         default:
3265                 retval = 0;
3266                 break;
3267         }
3268         return retval;
3269 }
3270
3271 #define MLX5_ENCAP_IPV4_VERSION         0x40
3272 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3273 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3274 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3275 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3276 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3277 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3278
3279 /**
3280  * Convert the encap action data from list of rte_flow_item to raw buffer
3281  *
3282  * @param[in] items
3283  *   Pointer to rte_flow_item objects list.
3284  * @param[out] buf
3285  *   Pointer to the output buffer.
3286  * @param[out] size
3287  *   Pointer to the output buffer size.
3288  * @param[out] error
3289  *   Pointer to the error structure.
3290  *
3291  * @return
3292  *   0 on success, a negative errno value otherwise and rte_errno is set.
3293  */
3294 static int
3295 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3296                            size_t *size, struct rte_flow_error *error)
3297 {
3298         struct rte_ether_hdr *eth = NULL;
3299         struct rte_vlan_hdr *vlan = NULL;
3300         struct rte_ipv4_hdr *ipv4 = NULL;
3301         struct rte_ipv6_hdr *ipv6 = NULL;
3302         struct rte_udp_hdr *udp = NULL;
3303         struct rte_vxlan_hdr *vxlan = NULL;
3304         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3305         struct rte_gre_hdr *gre = NULL;
3306         size_t len;
3307         size_t temp_size = 0;
3308
3309         if (!items)
3310                 return rte_flow_error_set(error, EINVAL,
3311                                           RTE_FLOW_ERROR_TYPE_ACTION,
3312                                           NULL, "invalid empty data");
3313         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3314                 len = flow_dv_get_item_hdr_len(items->type);
3315                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3316                         return rte_flow_error_set(error, EINVAL,
3317                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3318                                                   (void *)items->type,
3319                                                   "items total size is too big"
3320                                                   " for encap action");
3321                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3322                 switch (items->type) {
3323                 case RTE_FLOW_ITEM_TYPE_ETH:
3324                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3325                         break;
3326                 case RTE_FLOW_ITEM_TYPE_VLAN:
3327                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3328                         if (!eth)
3329                                 return rte_flow_error_set(error, EINVAL,
3330                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3331                                                 (void *)items->type,
3332                                                 "eth header not found");
3333                         if (!eth->ether_type)
3334                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3335                         break;
3336                 case RTE_FLOW_ITEM_TYPE_IPV4:
3337                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3338                         if (!vlan && !eth)
3339                                 return rte_flow_error_set(error, EINVAL,
3340                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3341                                                 (void *)items->type,
3342                                                 "neither eth nor vlan"
3343                                                 " header found");
3344                         if (vlan && !vlan->eth_proto)
3345                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3346                         else if (eth && !eth->ether_type)
3347                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3348                         if (!ipv4->version_ihl)
3349                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3350                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3351                         if (!ipv4->time_to_live)
3352                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3353                         break;
3354                 case RTE_FLOW_ITEM_TYPE_IPV6:
3355                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3356                         if (!vlan && !eth)
3357                                 return rte_flow_error_set(error, EINVAL,
3358                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3359                                                 (void *)items->type,
3360                                                 "neither eth nor vlan"
3361                                                 " header found");
3362                         if (vlan && !vlan->eth_proto)
3363                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3364                         else if (eth && !eth->ether_type)
3365                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3366                         if (!ipv6->vtc_flow)
3367                                 ipv6->vtc_flow =
3368                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3369                         if (!ipv6->hop_limits)
3370                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3371                         break;
3372                 case RTE_FLOW_ITEM_TYPE_UDP:
3373                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3374                         if (!ipv4 && !ipv6)
3375                                 return rte_flow_error_set(error, EINVAL,
3376                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3377                                                 (void *)items->type,
3378                                                 "ip header not found");
3379                         if (ipv4 && !ipv4->next_proto_id)
3380                                 ipv4->next_proto_id = IPPROTO_UDP;
3381                         else if (ipv6 && !ipv6->proto)
3382                                 ipv6->proto = IPPROTO_UDP;
3383                         break;
3384                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3385                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3386                         if (!udp)
3387                                 return rte_flow_error_set(error, EINVAL,
3388                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3389                                                 (void *)items->type,
3390                                                 "udp header not found");
3391                         if (!udp->dst_port)
3392                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3393                         if (!vxlan->vx_flags)
3394                                 vxlan->vx_flags =
3395                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3396                         break;
3397                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3398                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3399                         if (!udp)
3400                                 return rte_flow_error_set(error, EINVAL,
3401                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3402                                                 (void *)items->type,
3403                                                 "udp header not found");
3404                         if (!vxlan_gpe->proto)
3405                                 return rte_flow_error_set(error, EINVAL,
3406                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3407                                                 (void *)items->type,
3408                                                 "next protocol not found");
3409                         if (!udp->dst_port)
3410                                 udp->dst_port =
3411                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3412                         if (!vxlan_gpe->vx_flags)
3413                                 vxlan_gpe->vx_flags =
3414                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3415                         break;
3416                 case RTE_FLOW_ITEM_TYPE_GRE:
3417                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3418                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3419                         if (!gre->proto)
3420                                 return rte_flow_error_set(error, EINVAL,
3421                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3422                                                 (void *)items->type,
3423                                                 "next protocol not found");
3424                         if (!ipv4 && !ipv6)
3425                                 return rte_flow_error_set(error, EINVAL,
3426                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3427                                                 (void *)items->type,
3428                                                 "ip header not found");
3429                         if (ipv4 && !ipv4->next_proto_id)
3430                                 ipv4->next_proto_id = IPPROTO_GRE;
3431                         else if (ipv6 && !ipv6->proto)
3432                                 ipv6->proto = IPPROTO_GRE;
3433                         break;
3434                 case RTE_FLOW_ITEM_TYPE_VOID:
3435                         break;
3436                 default:
3437                         return rte_flow_error_set(error, EINVAL,
3438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3439                                                   (void *)items->type,
3440                                                   "unsupported item type");
3441                         break;
3442                 }
3443                 temp_size += len;
3444         }
3445         *size = temp_size;
3446         return 0;
3447 }
3448
3449 static int
3450 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3451 {
3452         struct rte_ether_hdr *eth = NULL;
3453         struct rte_vlan_hdr *vlan = NULL;
3454         struct rte_ipv6_hdr *ipv6 = NULL;
3455         struct rte_udp_hdr *udp = NULL;
3456         char *next_hdr;
3457         uint16_t proto;
3458
3459         eth = (struct rte_ether_hdr *)data;
3460         next_hdr = (char *)(eth + 1);
3461         proto = RTE_BE16(eth->ether_type);
3462
3463         /* VLAN skipping */
3464         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3465                 vlan = (struct rte_vlan_hdr *)next_hdr;
3466                 proto = RTE_BE16(vlan->eth_proto);
3467                 next_hdr += sizeof(struct rte_vlan_hdr);
3468         }
3469
3470         /* HW calculates IPv4 csum. no need to proceed */
3471         if (proto == RTE_ETHER_TYPE_IPV4)
3472                 return 0;
3473
3474         /* non IPv4/IPv6 header. not supported */
3475         if (proto != RTE_ETHER_TYPE_IPV6) {
3476                 return rte_flow_error_set(error, ENOTSUP,
3477                                           RTE_FLOW_ERROR_TYPE_ACTION,
3478                                           NULL, "Cannot offload non IPv4/IPv6");
3479         }
3480
3481         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3482
3483         /* ignore non UDP */
3484         if (ipv6->proto != IPPROTO_UDP)
3485                 return 0;
3486
3487         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3488         udp->dgram_cksum = 0;
3489
3490         return 0;
3491 }
3492
3493 /**
3494  * Convert L2 encap action to DV specification.
3495  *
3496  * @param[in] dev
3497  *   Pointer to rte_eth_dev structure.
3498  * @param[in] action
3499  *   Pointer to action structure.
3500  * @param[in, out] dev_flow
3501  *   Pointer to the mlx5_flow.
3502  * @param[in] transfer
3503  *   Mark if the flow is E-Switch flow.
3504  * @param[out] error
3505  *   Pointer to the error structure.
3506  *
3507  * @return
3508  *   0 on success, a negative errno value otherwise and rte_errno is set.
3509  */
3510 static int
3511 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3512                                const struct rte_flow_action *action,
3513                                struct mlx5_flow *dev_flow,
3514                                uint8_t transfer,
3515                                struct rte_flow_error *error)
3516 {
3517         const struct rte_flow_item *encap_data;
3518         const struct rte_flow_action_raw_encap *raw_encap_data;
3519         struct mlx5_flow_dv_encap_decap_resource res = {
3520                 .reformat_type =
3521                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3522                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3523                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3524         };
3525
3526         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3527                 raw_encap_data =
3528                         (const struct rte_flow_action_raw_encap *)action->conf;
3529                 res.size = raw_encap_data->size;
3530                 memcpy(res.buf, raw_encap_data->data, res.size);
3531         } else {
3532                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3533                         encap_data =
3534                                 ((const struct rte_flow_action_vxlan_encap *)
3535                                                 action->conf)->definition;
3536                 else
3537                         encap_data =
3538                                 ((const struct rte_flow_action_nvgre_encap *)
3539                                                 action->conf)->definition;
3540                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3541                                                &res.size, error))
3542                         return -rte_errno;
3543         }
3544         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3545                 return -rte_errno;
3546         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3547                 return rte_flow_error_set(error, EINVAL,
3548                                           RTE_FLOW_ERROR_TYPE_ACTION,
3549                                           NULL, "can't create L2 encap action");
3550         return 0;
3551 }
3552
3553 /**
3554  * Convert L2 decap action to DV specification.
3555  *
3556  * @param[in] dev
3557  *   Pointer to rte_eth_dev structure.
3558  * @param[in, out] dev_flow
3559  *   Pointer to the mlx5_flow.
3560  * @param[in] transfer
3561  *   Mark if the flow is E-Switch flow.
3562  * @param[out] error
3563  *   Pointer to the error structure.
3564  *
3565  * @return
3566  *   0 on success, a negative errno value otherwise and rte_errno is set.
3567  */
3568 static int
3569 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3570                                struct mlx5_flow *dev_flow,
3571                                uint8_t transfer,
3572                                struct rte_flow_error *error)
3573 {
3574         struct mlx5_flow_dv_encap_decap_resource res = {
3575                 .size = 0,
3576                 .reformat_type =
3577                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3578                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3579                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3580         };
3581
3582         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3583                 return rte_flow_error_set(error, EINVAL,
3584                                           RTE_FLOW_ERROR_TYPE_ACTION,
3585                                           NULL, "can't create L2 decap action");
3586         return 0;
3587 }
3588
3589 /**
3590  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3591  *
3592  * @param[in] dev
3593  *   Pointer to rte_eth_dev structure.
3594  * @param[in] action
3595  *   Pointer to action structure.
3596  * @param[in, out] dev_flow
3597  *   Pointer to the mlx5_flow.
3598  * @param[in] attr
3599  *   Pointer to the flow attributes.
3600  * @param[out] error
3601  *   Pointer to the error structure.
3602  *
3603  * @return
3604  *   0 on success, a negative errno value otherwise and rte_errno is set.
3605  */
3606 static int
3607 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3608                                 const struct rte_flow_action *action,
3609                                 struct mlx5_flow *dev_flow,
3610                                 const struct rte_flow_attr *attr,
3611                                 struct rte_flow_error *error)
3612 {
3613         const struct rte_flow_action_raw_encap *encap_data;
3614         struct mlx5_flow_dv_encap_decap_resource res;
3615
3616         memset(&res, 0, sizeof(res));
3617         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3618         res.size = encap_data->size;
3619         memcpy(res.buf, encap_data->data, res.size);
3620         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3621                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3622                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3623         if (attr->transfer)
3624                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3625         else
3626                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3627                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3628         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3629                 return rte_flow_error_set(error, EINVAL,
3630                                           RTE_FLOW_ERROR_TYPE_ACTION,
3631                                           NULL, "can't create encap action");
3632         return 0;
3633 }
3634
3635 /**
3636  * Create action push VLAN.
3637  *
3638  * @param[in] dev
3639  *   Pointer to rte_eth_dev structure.
3640  * @param[in] attr
3641  *   Pointer to the flow attributes.
3642  * @param[in] vlan
3643  *   Pointer to the vlan to push to the Ethernet header.
3644  * @param[in, out] dev_flow
3645  *   Pointer to the mlx5_flow.
3646  * @param[out] error
3647  *   Pointer to the error structure.
3648  *
3649  * @return
3650  *   0 on success, a negative errno value otherwise and rte_errno is set.
3651  */
3652 static int
3653 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3654                                 const struct rte_flow_attr *attr,
3655                                 const struct rte_vlan_hdr *vlan,
3656                                 struct mlx5_flow *dev_flow,
3657                                 struct rte_flow_error *error)
3658 {
3659         struct mlx5_flow_dv_push_vlan_action_resource res;
3660
3661         memset(&res, 0, sizeof(res));
3662         res.vlan_tag =
3663                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3664                                  vlan->vlan_tci);
3665         if (attr->transfer)
3666                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3667         else
3668                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3669                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3670         return flow_dv_push_vlan_action_resource_register
3671                                             (dev, &res, dev_flow, error);
3672 }
3673
3674 /**
3675  * Validate the modify-header actions.
3676  *
3677  * @param[in] action_flags
3678  *   Holds the actions detected until now.
3679  * @param[in] action
3680  *   Pointer to the modify action.
3681  * @param[out] error
3682  *   Pointer to error structure.
3683  *
3684  * @return
3685  *   0 on success, a negative errno value otherwise and rte_errno is set.
3686  */
3687 static int
3688 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3689                                    const struct rte_flow_action *action,
3690                                    struct rte_flow_error *error)
3691 {
3692         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3693                 return rte_flow_error_set(error, EINVAL,
3694                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3695                                           NULL, "action configuration not set");
3696         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3697                 return rte_flow_error_set(error, EINVAL,
3698                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699                                           "can't have encap action before"
3700                                           " modify action");
3701         return 0;
3702 }
3703
3704 /**
3705  * Validate the modify-header MAC address actions.
3706  *
3707  * @param[in] action_flags
3708  *   Holds the actions detected until now.
3709  * @param[in] action
3710  *   Pointer to the modify action.
3711  * @param[in] item_flags
3712  *   Holds the items detected.
3713  * @param[out] error
3714  *   Pointer to error structure.
3715  *
3716  * @return
3717  *   0 on success, a negative errno value otherwise and rte_errno is set.
3718  */
3719 static int
3720 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3721                                    const struct rte_flow_action *action,
3722                                    const uint64_t item_flags,
3723                                    struct rte_flow_error *error)
3724 {
3725         int ret = 0;
3726
3727         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3728         if (!ret) {
3729                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3730                         return rte_flow_error_set(error, EINVAL,
3731                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3732                                                   NULL,
3733                                                   "no L2 item in pattern");
3734         }
3735         return ret;
3736 }
3737
3738 /**
3739  * Validate the modify-header IPv4 address actions.
3740  *
3741  * @param[in] action_flags
3742  *   Holds the actions detected until now.
3743  * @param[in] action
3744  *   Pointer to the modify action.
3745  * @param[in] item_flags
3746  *   Holds the items detected.
3747  * @param[out] error
3748  *   Pointer to error structure.
3749  *
3750  * @return
3751  *   0 on success, a negative errno value otherwise and rte_errno is set.
3752  */
3753 static int
3754 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3755                                     const struct rte_flow_action *action,
3756                                     const uint64_t item_flags,
3757                                     struct rte_flow_error *error)
3758 {
3759         int ret = 0;
3760         uint64_t layer;
3761
3762         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3763         if (!ret) {
3764                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3765                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3766                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3767                 if (!(item_flags & layer))
3768                         return rte_flow_error_set(error, EINVAL,
3769                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3770                                                   NULL,
3771                                                   "no ipv4 item in pattern");
3772         }
3773         return ret;
3774 }
3775
3776 /**
3777  * Validate the modify-header IPv6 address actions.
3778  *
3779  * @param[in] action_flags
3780  *   Holds the actions detected until now.
3781  * @param[in] action
3782  *   Pointer to the modify action.
3783  * @param[in] item_flags
3784  *   Holds the items detected.
3785  * @param[out] error
3786  *   Pointer to error structure.
3787  *
3788  * @return
3789  *   0 on success, a negative errno value otherwise and rte_errno is set.
3790  */
3791 static int
3792 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3793                                     const struct rte_flow_action *action,
3794                                     const uint64_t item_flags,
3795                                     struct rte_flow_error *error)
3796 {
3797         int ret = 0;
3798         uint64_t layer;
3799
3800         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3801         if (!ret) {
3802                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3803                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3804                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3805                 if (!(item_flags & layer))
3806                         return rte_flow_error_set(error, EINVAL,
3807                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3808                                                   NULL,
3809                                                   "no ipv6 item in pattern");
3810         }
3811         return ret;
3812 }
3813
3814 /**
3815  * Validate the modify-header TP actions.
3816  *
3817  * @param[in] action_flags
3818  *   Holds the actions detected until now.
3819  * @param[in] action
3820  *   Pointer to the modify action.
3821  * @param[in] item_flags
3822  *   Holds the items detected.
3823  * @param[out] error
3824  *   Pointer to error structure.
3825  *
3826  * @return
3827  *   0 on success, a negative errno value otherwise and rte_errno is set.
3828  */
3829 static int
3830 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3831                                   const struct rte_flow_action *action,
3832                                   const uint64_t item_flags,
3833                                   struct rte_flow_error *error)
3834 {
3835         int ret = 0;
3836         uint64_t layer;
3837
3838         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3839         if (!ret) {
3840                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3841                                  MLX5_FLOW_LAYER_INNER_L4 :
3842                                  MLX5_FLOW_LAYER_OUTER_L4;
3843                 if (!(item_flags & layer))
3844                         return rte_flow_error_set(error, EINVAL,
3845                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3846                                                   NULL, "no transport layer "
3847                                                   "in pattern");
3848         }
3849         return ret;
3850 }
3851
3852 /**
3853  * Validate the modify-header actions of increment/decrement
3854  * TCP Sequence-number.
3855  *
3856  * @param[in] action_flags
3857  *   Holds the actions detected until now.
3858  * @param[in] action
3859  *   Pointer to the modify action.
3860  * @param[in] item_flags
3861  *   Holds the items detected.
3862  * @param[out] error
3863  *   Pointer to error structure.
3864  *
3865  * @return
3866  *   0 on success, a negative errno value otherwise and rte_errno is set.
3867  */
3868 static int
3869 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3870                                        const struct rte_flow_action *action,
3871                                        const uint64_t item_flags,
3872                                        struct rte_flow_error *error)
3873 {
3874         int ret = 0;
3875         uint64_t layer;
3876
3877         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3878         if (!ret) {
3879                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3880                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3881                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3882                 if (!(item_flags & layer))
3883                         return rte_flow_error_set(error, EINVAL,
3884                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3885                                                   NULL, "no TCP item in"
3886                                                   " pattern");
3887                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3888                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3889                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3890                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3891                         return rte_flow_error_set(error, EINVAL,
3892                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3893                                                   NULL,
3894                                                   "cannot decrease and increase"
3895                                                   " TCP sequence number"
3896                                                   " at the same time");
3897         }
3898         return ret;
3899 }
3900
3901 /**
3902  * Validate the modify-header actions of increment/decrement
3903  * TCP Acknowledgment number.
3904  *
3905  * @param[in] action_flags
3906  *   Holds the actions detected until now.
3907  * @param[in] action
3908  *   Pointer to the modify action.
3909  * @param[in] item_flags
3910  *   Holds the items detected.
3911  * @param[out] error
3912  *   Pointer to error structure.
3913  *
3914  * @return
3915  *   0 on success, a negative errno value otherwise and rte_errno is set.
3916  */
3917 static int
3918 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3919                                        const struct rte_flow_action *action,
3920                                        const uint64_t item_flags,
3921                                        struct rte_flow_error *error)
3922 {
3923         int ret = 0;
3924         uint64_t layer;
3925
3926         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3927         if (!ret) {
3928                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3929                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3930                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3931                 if (!(item_flags & layer))
3932                         return rte_flow_error_set(error, EINVAL,
3933                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3934                                                   NULL, "no TCP item in"
3935                                                   " pattern");
3936                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3937                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3938                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3939                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3940                         return rte_flow_error_set(error, EINVAL,
3941                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3942                                                   NULL,
3943                                                   "cannot decrease and increase"
3944                                                   " TCP acknowledgment number"
3945                                                   " at the same time");
3946         }
3947         return ret;
3948 }
3949
3950 /**
3951  * Validate the modify-header TTL actions.
3952  *
3953  * @param[in] action_flags
3954  *   Holds the actions detected until now.
3955  * @param[in] action
3956  *   Pointer to the modify action.
3957  * @param[in] item_flags
3958  *   Holds the items detected.
3959  * @param[out] error
3960  *   Pointer to error structure.
3961  *
3962  * @return
3963  *   0 on success, a negative errno value otherwise and rte_errno is set.
3964  */
3965 static int
3966 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3967                                    const struct rte_flow_action *action,
3968                                    const uint64_t item_flags,
3969                                    struct rte_flow_error *error)
3970 {
3971         int ret = 0;
3972         uint64_t layer;
3973
3974         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3975         if (!ret) {
3976                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3977                                  MLX5_FLOW_LAYER_INNER_L3 :
3978                                  MLX5_FLOW_LAYER_OUTER_L3;
3979                 if (!(item_flags & layer))
3980                         return rte_flow_error_set(error, EINVAL,
3981                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3982                                                   NULL,
3983                                                   "no IP protocol in pattern");
3984         }
3985         return ret;
3986 }
3987
3988 /**
3989  * Validate jump action.
3990  *
3991  * @param[in] action
3992  *   Pointer to the jump action.
3993  * @param[in] action_flags
3994  *   Holds the actions detected until now.
3995  * @param[in] attributes
3996  *   Pointer to flow attributes
3997  * @param[in] external
3998  *   Action belongs to flow rule created by request external to PMD.
3999  * @param[out] error
4000  *   Pointer to error structure.
4001  *
4002  * @return
4003  *   0 on success, a negative errno value otherwise and rte_errno is set.
4004  */
4005 static int
4006 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4007                              const struct mlx5_flow_tunnel *tunnel,
4008                              const struct rte_flow_action *action,
4009                              uint64_t action_flags,
4010                              const struct rte_flow_attr *attributes,
4011                              bool external, struct rte_flow_error *error)
4012 {
4013         uint32_t target_group, table;
4014         int ret = 0;
4015         struct flow_grp_info grp_info = {
4016                 .external = !!external,
4017                 .transfer = !!attributes->transfer,
4018                 .fdb_def_rule = 1,
4019                 .std_tbl_fix = 0
4020         };
4021         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4022                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4023                 return rte_flow_error_set(error, EINVAL,
4024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4025                                           "can't have 2 fate actions in"
4026                                           " same flow");
4027         if (action_flags & MLX5_FLOW_ACTION_METER)
4028                 return rte_flow_error_set(error, ENOTSUP,
4029                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4030                                           "jump with meter not support");
4031         if (!action->conf)
4032                 return rte_flow_error_set(error, EINVAL,
4033                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4034                                           NULL, "action configuration not set");
4035         target_group =
4036                 ((const struct rte_flow_action_jump *)action->conf)->group;
4037         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4038                                        &grp_info, error);
4039         if (ret)
4040                 return ret;
4041         if (attributes->group == target_group &&
4042             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4043                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4044                 return rte_flow_error_set(error, EINVAL,
4045                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4046                                           "target group must be other than"
4047                                           " the current flow group");
4048         return 0;
4049 }
4050
4051 /*
4052  * Validate the port_id action.
4053  *
4054  * @param[in] dev
4055  *   Pointer to rte_eth_dev structure.
4056  * @param[in] action_flags
4057  *   Bit-fields that holds the actions detected until now.
4058  * @param[in] action
4059  *   Port_id RTE action structure.
4060  * @param[in] attr
4061  *   Attributes of flow that includes this action.
4062  * @param[out] error
4063  *   Pointer to error structure.
4064  *
4065  * @return
4066  *   0 on success, a negative errno value otherwise and rte_errno is set.
4067  */
4068 static int
4069 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4070                                 uint64_t action_flags,
4071                                 const struct rte_flow_action *action,
4072                                 const struct rte_flow_attr *attr,
4073                                 struct rte_flow_error *error)
4074 {
4075         const struct rte_flow_action_port_id *port_id;
4076         struct mlx5_priv *act_priv;
4077         struct mlx5_priv *dev_priv;
4078         uint16_t port;
4079
4080         if (!attr->transfer)
4081                 return rte_flow_error_set(error, ENOTSUP,
4082                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4083                                           NULL,
4084                                           "port id action is valid in transfer"
4085                                           " mode only");
4086         if (!action || !action->conf)
4087                 return rte_flow_error_set(error, ENOTSUP,
4088                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4089                                           NULL,
4090                                           "port id action parameters must be"
4091                                           " specified");
4092         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4093                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4094                 return rte_flow_error_set(error, EINVAL,
4095                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4096                                           "can have only one fate actions in"
4097                                           " a flow");
4098         dev_priv = mlx5_dev_to_eswitch_info(dev);
4099         if (!dev_priv)
4100                 return rte_flow_error_set(error, rte_errno,
4101                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4102                                           NULL,
4103                                           "failed to obtain E-Switch info");
4104         port_id = action->conf;
4105         port = port_id->original ? dev->data->port_id : port_id->id;
4106         act_priv = mlx5_port_to_eswitch_info(port, false);
4107         if (!act_priv)
4108                 return rte_flow_error_set
4109                                 (error, rte_errno,
4110                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4111                                  "failed to obtain E-Switch port id for port");
4112         if (act_priv->domain_id != dev_priv->domain_id)
4113                 return rte_flow_error_set
4114                                 (error, EINVAL,
4115                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4116                                  "port does not belong to"
4117                                  " E-Switch being configured");
4118         return 0;
4119 }
4120
4121 /**
4122  * Get the maximum number of modify header actions.
4123  *
4124  * @param dev
4125  *   Pointer to rte_eth_dev structure.
4126  * @param flags
4127  *   Flags bits to check if root level.
4128  *
4129  * @return
4130  *   Max number of modify header actions device can support.
4131  */
4132 static inline unsigned int
4133 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4134                               uint64_t flags)
4135 {
4136         /*
4137          * There's no way to directly query the max capacity from FW.
4138          * The maximal value on root table should be assumed to be supported.
4139          */
4140         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4141                 return MLX5_MAX_MODIFY_NUM;
4142         else
4143                 return MLX5_ROOT_TBL_MODIFY_NUM;
4144 }
4145
4146 /**
4147  * Validate the meter action.
4148  *
4149  * @param[in] dev
4150  *   Pointer to rte_eth_dev structure.
4151  * @param[in] action_flags
4152  *   Bit-fields that holds the actions detected until now.
4153  * @param[in] action
4154  *   Pointer to the meter action.
4155  * @param[in] attr
4156  *   Attributes of flow that includes this action.
4157  * @param[out] error
4158  *   Pointer to error structure.
4159  *
4160  * @return
4161  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4162  */
4163 static int
4164 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4165                                 uint64_t action_flags,
4166                                 const struct rte_flow_action *action,
4167                                 const struct rte_flow_attr *attr,
4168                                 struct rte_flow_error *error)
4169 {
4170         struct mlx5_priv *priv = dev->data->dev_private;
4171         const struct rte_flow_action_meter *am = action->conf;
4172         struct mlx5_flow_meter *fm;
4173
4174         if (!am)
4175                 return rte_flow_error_set(error, EINVAL,
4176                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4177                                           "meter action conf is NULL");
4178
4179         if (action_flags & MLX5_FLOW_ACTION_METER)
4180                 return rte_flow_error_set(error, ENOTSUP,
4181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4182                                           "meter chaining not support");
4183         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4184                 return rte_flow_error_set(error, ENOTSUP,
4185                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4186                                           "meter with jump not support");
4187         if (!priv->mtr_en)
4188                 return rte_flow_error_set(error, ENOTSUP,
4189                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4190                                           NULL,
4191                                           "meter action not supported");
4192         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4193         if (!fm)
4194                 return rte_flow_error_set(error, EINVAL,
4195                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4196                                           "Meter not found");
4197         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4198               (!fm->ingress && !attr->ingress && attr->egress) ||
4199               (!fm->egress && !attr->egress && attr->ingress))))
4200                 return rte_flow_error_set(error, EINVAL,
4201                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4202                                           "Flow attributes are either invalid "
4203                                           "or have a conflict with current "
4204                                           "meter attributes");
4205         return 0;
4206 }
4207
4208 /**
4209  * Validate the age action.
4210  *
4211  * @param[in] action_flags
4212  *   Holds the actions detected until now.
4213  * @param[in] action
4214  *   Pointer to the age action.
4215  * @param[in] dev
4216  *   Pointer to the Ethernet device structure.
4217  * @param[out] error
4218  *   Pointer to error structure.
4219  *
4220  * @return
4221  *   0 on success, a negative errno value otherwise and rte_errno is set.
4222  */
4223 static int
4224 flow_dv_validate_action_age(uint64_t action_flags,
4225                             const struct rte_flow_action *action,
4226                             struct rte_eth_dev *dev,
4227                             struct rte_flow_error *error)
4228 {
4229         struct mlx5_priv *priv = dev->data->dev_private;
4230         const struct rte_flow_action_age *age = action->conf;
4231
4232         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4233             !priv->sh->aso_age_mng))
4234                 return rte_flow_error_set(error, ENOTSUP,
4235                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4236                                           NULL,
4237                                           "age action not supported");
4238         if (!(action->conf))
4239                 return rte_flow_error_set(error, EINVAL,
4240                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4241                                           "configuration cannot be null");
4242         if (!(age->timeout))
4243                 return rte_flow_error_set(error, EINVAL,
4244                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4245                                           "invalid timeout value 0");
4246         if (action_flags & MLX5_FLOW_ACTION_AGE)
4247                 return rte_flow_error_set(error, EINVAL,
4248                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4249                                           "duplicate age actions set");
4250         return 0;
4251 }
4252
4253 /**
4254  * Validate the modify-header IPv4 DSCP actions.
4255  *
4256  * @param[in] action_flags
4257  *   Holds the actions detected until now.
4258  * @param[in] action
4259  *   Pointer to the modify action.
4260  * @param[in] item_flags
4261  *   Holds the items detected.
4262  * @param[out] error
4263  *   Pointer to error structure.
4264  *
4265  * @return
4266  *   0 on success, a negative errno value otherwise and rte_errno is set.
4267  */
4268 static int
4269 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4270                                          const struct rte_flow_action *action,
4271                                          const uint64_t item_flags,
4272                                          struct rte_flow_error *error)
4273 {
4274         int ret = 0;
4275
4276         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4277         if (!ret) {
4278                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4279                         return rte_flow_error_set(error, EINVAL,
4280                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4281                                                   NULL,
4282                                                   "no ipv4 item in pattern");
4283         }
4284         return ret;
4285 }
4286
4287 /**
4288  * Validate the modify-header IPv6 DSCP actions.
4289  *
4290  * @param[in] action_flags
4291  *   Holds the actions detected until now.
4292  * @param[in] action
4293  *   Pointer to the modify action.
4294  * @param[in] item_flags
4295  *   Holds the items detected.
4296  * @param[out] error
4297  *   Pointer to error structure.
4298  *
4299  * @return
4300  *   0 on success, a negative errno value otherwise and rte_errno is set.
4301  */
4302 static int
4303 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4304                                          const struct rte_flow_action *action,
4305                                          const uint64_t item_flags,
4306                                          struct rte_flow_error *error)
4307 {
4308         int ret = 0;
4309
4310         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4311         if (!ret) {
4312                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4313                         return rte_flow_error_set(error, EINVAL,
4314                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4315                                                   NULL,
4316                                                   "no ipv6 item in pattern");
4317         }
4318         return ret;
4319 }
4320
4321 /**
4322  * Match modify-header resource.
4323  *
4324  * @param list
4325  *   Pointer to the hash list.
4326  * @param entry
4327  *   Pointer to exist resource entry object.
4328  * @param key
4329  *   Key of the new entry.
4330  * @param ctx
4331  *   Pointer to new modify-header resource.
4332  *
4333  * @return
4334  *   0 on matching, non-zero otherwise.
4335  */
4336 int
4337 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4338                         struct mlx5_hlist_entry *entry,
4339                         uint64_t key __rte_unused, void *cb_ctx)
4340 {
4341         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4342         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4343         struct mlx5_flow_dv_modify_hdr_resource *resource =
4344                         container_of(entry, typeof(*resource), entry);
4345         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4346
4347         key_len += ref->actions_num * sizeof(ref->actions[0]);
4348         return ref->actions_num != resource->actions_num ||
4349                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4350 }
4351
4352 struct mlx5_hlist_entry *
4353 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4354                          void *cb_ctx)
4355 {
4356         struct mlx5_dev_ctx_shared *sh = list->ctx;
4357         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4358         struct mlx5dv_dr_domain *ns;
4359         struct mlx5_flow_dv_modify_hdr_resource *entry;
4360         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4361         int ret;
4362         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4363         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4364
4365         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4366                             SOCKET_ID_ANY);
4367         if (!entry) {
4368                 rte_flow_error_set(ctx->error, ENOMEM,
4369                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4370                                    "cannot allocate resource memory");
4371                 return NULL;
4372         }
4373         rte_memcpy(&entry->ft_type,
4374                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4375                    key_len + data_len);
4376         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4377                 ns = sh->fdb_domain;
4378         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4379                 ns = sh->tx_domain;
4380         else
4381                 ns = sh->rx_domain;
4382         ret = mlx5_flow_os_create_flow_action_modify_header
4383                                         (sh->ctx, ns, entry,
4384                                          data_len, &entry->action);
4385         if (ret) {
4386                 mlx5_free(entry);
4387                 rte_flow_error_set(ctx->error, ENOMEM,
4388                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4389                                    NULL, "cannot create modification action");
4390                 return NULL;
4391         }
4392         return &entry->entry;
4393 }
4394
4395 /**
4396  * Validate the sample action.
4397  *
4398  * @param[in] action_flags
4399  *   Holds the actions detected until now.
4400  * @param[in] action
4401  *   Pointer to the sample action.
4402  * @param[in] dev
4403  *   Pointer to the Ethernet device structure.
4404  * @param[in] attr
4405  *   Attributes of flow that includes this action.
4406  * @param[in] item_flags
4407  *   Holds the items detected.
4408  * @param[in] rss
4409  *   Pointer to the RSS action.
4410  * @param[out] sample_rss
4411  *   Pointer to the RSS action in sample action list.
4412  * @param[out] error
4413  *   Pointer to error structure.
4414  *
4415  * @return
4416  *   0 on success, a negative errno value otherwise and rte_errno is set.
4417  */
4418 static int
4419 flow_dv_validate_action_sample(uint64_t action_flags,
4420                                const struct rte_flow_action *action,
4421                                struct rte_eth_dev *dev,
4422                                const struct rte_flow_attr *attr,
4423                                uint64_t item_flags,
4424                                const struct rte_flow_action_rss *rss,
4425                                const struct rte_flow_action_rss **sample_rss,
4426                                struct rte_flow_error *error)
4427 {
4428         struct mlx5_priv *priv = dev->data->dev_private;
4429         struct mlx5_dev_config *dev_conf = &priv->config;
4430         const struct rte_flow_action_sample *sample = action->conf;
4431         const struct rte_flow_action *act;
4432         uint64_t sub_action_flags = 0;
4433         uint16_t queue_index = 0xFFFF;
4434         int actions_n = 0;
4435         int ret;
4436
4437         if (!sample)
4438                 return rte_flow_error_set(error, EINVAL,
4439                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4440                                           "configuration cannot be NULL");
4441         if (sample->ratio == 0)
4442                 return rte_flow_error_set(error, EINVAL,
4443                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4444                                           "ratio value starts from 1");
4445         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4446                 return rte_flow_error_set(error, ENOTSUP,
4447                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4448                                           NULL,
4449                                           "sample action not supported");
4450         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4451                 return rte_flow_error_set(error, EINVAL,
4452                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4453                                           "Multiple sample actions not "
4454                                           "supported");
4455         if (action_flags & MLX5_FLOW_ACTION_METER)
4456                 return rte_flow_error_set(error, EINVAL,
4457                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4458                                           "wrong action order, meter should "
4459                                           "be after sample action");
4460         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4461                 return rte_flow_error_set(error, EINVAL,
4462                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4463                                           "wrong action order, jump should "
4464                                           "be after sample action");
4465         act = sample->actions;
4466         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4467                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4468                         return rte_flow_error_set(error, ENOTSUP,
4469                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4470                                                   act, "too many actions");
4471                 switch (act->type) {
4472                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4473                         ret = mlx5_flow_validate_action_queue(act,
4474                                                               sub_action_flags,
4475                                                               dev,
4476                                                               attr, error);
4477                         if (ret < 0)
4478                                 return ret;
4479                         queue_index = ((const struct rte_flow_action_queue *)
4480                                                         (act->conf))->index;
4481                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4482                         ++actions_n;
4483                         break;
4484                 case RTE_FLOW_ACTION_TYPE_RSS:
4485                         *sample_rss = act->conf;
4486                         ret = mlx5_flow_validate_action_rss(act,
4487                                                             sub_action_flags,
4488                                                             dev, attr,
4489                                                             item_flags,
4490                                                             error);
4491                         if (ret < 0)
4492                                 return ret;
4493                         if (rss && *sample_rss &&
4494                             ((*sample_rss)->level != rss->level ||
4495                             (*sample_rss)->types != rss->types))
4496                                 return rte_flow_error_set(error, ENOTSUP,
4497                                         RTE_FLOW_ERROR_TYPE_ACTION,
4498                                         NULL,
4499                                         "Can't use the different RSS types "
4500                                         "or level in the same flow");
4501                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
4502                                 queue_index = (*sample_rss)->queue[0];
4503                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
4504                         ++actions_n;
4505                         break;
4506                 case RTE_FLOW_ACTION_TYPE_MARK:
4507                         ret = flow_dv_validate_action_mark(dev, act,
4508                                                            sub_action_flags,
4509                                                            attr, error);
4510                         if (ret < 0)
4511                                 return ret;
4512                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4513                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4514                                                 MLX5_FLOW_ACTION_MARK_EXT;
4515                         else
4516                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4517                         ++actions_n;
4518                         break;
4519                 case RTE_FLOW_ACTION_TYPE_COUNT:
4520                         ret = flow_dv_validate_action_count(dev, error);
4521                         if (ret < 0)
4522                                 return ret;
4523                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4524                         ++actions_n;
4525                         break;
4526                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4527                         ret = flow_dv_validate_action_port_id(dev,
4528                                                               sub_action_flags,
4529                                                               act,
4530                                                               attr,
4531                                                               error);
4532                         if (ret)
4533                                 return ret;
4534                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4535                         ++actions_n;
4536                         break;
4537                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4538                         ret = flow_dv_validate_action_raw_encap_decap
4539                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4540                                  &actions_n, action, item_flags, error);
4541                         if (ret < 0)
4542                                 return ret;
4543                         ++actions_n;
4544                         break;
4545                 default:
4546                         return rte_flow_error_set(error, ENOTSUP,
4547                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4548                                                   NULL,
4549                                                   "Doesn't support optional "
4550                                                   "action");
4551                 }
4552         }
4553         if (attr->ingress && !attr->transfer) {
4554                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
4555                                           MLX5_FLOW_ACTION_RSS)))
4556                         return rte_flow_error_set(error, EINVAL,
4557                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4558                                                   NULL,
4559                                                   "Ingress must has a dest "
4560                                                   "QUEUE for Sample");
4561         } else if (attr->egress && !attr->transfer) {
4562                 return rte_flow_error_set(error, ENOTSUP,
4563                                           RTE_FLOW_ERROR_TYPE_ACTION,
4564                                           NULL,
4565                                           "Sample Only support Ingress "
4566                                           "or E-Switch");
4567         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4568                 MLX5_ASSERT(attr->transfer);
4569                 if (sample->ratio > 1)
4570                         return rte_flow_error_set(error, ENOTSUP,
4571                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4572                                                   NULL,
4573                                                   "E-Switch doesn't support "
4574                                                   "any optional action "
4575                                                   "for sampling");
4576                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4577                         return rte_flow_error_set(error, ENOTSUP,
4578                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4579                                                   NULL,
4580                                                   "unsupported action QUEUE");
4581                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
4582                         return rte_flow_error_set(error, ENOTSUP,
4583                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4584                                                   NULL,
4585                                                   "unsupported action QUEUE");
4586                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4587                         return rte_flow_error_set(error, EINVAL,
4588                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4589                                                   NULL,
4590                                                   "E-Switch must has a dest "
4591                                                   "port for mirroring");
4592         }
4593         /* Continue validation for Xcap actions.*/
4594         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4595             (queue_index == 0xFFFF ||
4596              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4597                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4598                      MLX5_FLOW_XCAP_ACTIONS)
4599                         return rte_flow_error_set(error, ENOTSUP,
4600                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4601                                                   NULL, "encap and decap "
4602                                                   "combination aren't "
4603                                                   "supported");
4604                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4605                                                         MLX5_FLOW_ACTION_ENCAP))
4606                         return rte_flow_error_set(error, ENOTSUP,
4607                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4608                                                   NULL, "encap is not supported"
4609                                                   " for ingress traffic");
4610         }
4611         return 0;
4612 }
4613
4614 /**
4615  * Find existing modify-header resource or create and register a new one.
4616  *
4617  * @param dev[in, out]
4618  *   Pointer to rte_eth_dev structure.
4619  * @param[in, out] resource
4620  *   Pointer to modify-header resource.
4621  * @parm[in, out] dev_flow
4622  *   Pointer to the dev_flow.
4623  * @param[out] error
4624  *   pointer to error structure.
4625  *
4626  * @return
4627  *   0 on success otherwise -errno and errno is set.
4628  */
4629 static int
4630 flow_dv_modify_hdr_resource_register
4631                         (struct rte_eth_dev *dev,
4632                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4633                          struct mlx5_flow *dev_flow,
4634                          struct rte_flow_error *error)
4635 {
4636         struct mlx5_priv *priv = dev->data->dev_private;
4637         struct mlx5_dev_ctx_shared *sh = priv->sh;
4638         uint32_t key_len = sizeof(*resource) -
4639                            offsetof(typeof(*resource), ft_type) +
4640                            resource->actions_num * sizeof(resource->actions[0]);
4641         struct mlx5_hlist_entry *entry;
4642         struct mlx5_flow_cb_ctx ctx = {
4643                 .error = error,
4644                 .data = resource,
4645         };
4646         uint64_t key64;
4647
4648         resource->flags = dev_flow->dv.group ? 0 :
4649                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4650         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4651                                     resource->flags))
4652                 return rte_flow_error_set(error, EOVERFLOW,
4653                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4654                                           "too many modify header items");
4655         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4656         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4657         if (!entry)
4658                 return -rte_errno;
4659         resource = container_of(entry, typeof(*resource), entry);
4660         dev_flow->handle->dvh.modify_hdr = resource;
4661         return 0;
4662 }
4663
4664 /**
4665  * Get DV flow counter by index.
4666  *
4667  * @param[in] dev
4668  *   Pointer to the Ethernet device structure.
4669  * @param[in] idx
4670  *   mlx5 flow counter index in the container.
4671  * @param[out] ppool
4672  *   mlx5 flow counter pool in the container,
4673  *
4674  * @return
4675  *   Pointer to the counter, NULL otherwise.
4676  */
4677 static struct mlx5_flow_counter *
4678 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4679                            uint32_t idx,
4680                            struct mlx5_flow_counter_pool **ppool)
4681 {
4682         struct mlx5_priv *priv = dev->data->dev_private;
4683         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4684         struct mlx5_flow_counter_pool *pool;
4685
4686         /* Decrease to original index and clear shared bit. */
4687         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4688         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4689         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4690         MLX5_ASSERT(pool);
4691         if (ppool)
4692                 *ppool = pool;
4693         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4694 }
4695
4696 /**
4697  * Check the devx counter belongs to the pool.
4698  *
4699  * @param[in] pool
4700  *   Pointer to the counter pool.
4701  * @param[in] id
4702  *   The counter devx ID.
4703  *
4704  * @return
4705  *   True if counter belongs to the pool, false otherwise.
4706  */
4707 static bool
4708 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4709 {
4710         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4711                    MLX5_COUNTERS_PER_POOL;
4712
4713         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4714                 return true;
4715         return false;
4716 }
4717
4718 /**
4719  * Get a pool by devx counter ID.
4720  *
4721  * @param[in] cmng
4722  *   Pointer to the counter management.
4723  * @param[in] id
4724  *   The counter devx ID.
4725  *
4726  * @return
4727  *   The counter pool pointer if exists, NULL otherwise,
4728  */
4729 static struct mlx5_flow_counter_pool *
4730 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4731 {
4732         uint32_t i;
4733         struct mlx5_flow_counter_pool *pool = NULL;
4734
4735         rte_spinlock_lock(&cmng->pool_update_sl);
4736         /* Check last used pool. */
4737         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4738             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4739                 pool = cmng->pools[cmng->last_pool_idx];
4740                 goto out;
4741         }
4742         /* ID out of range means no suitable pool in the container. */
4743         if (id > cmng->max_id || id < cmng->min_id)
4744                 goto out;
4745         /*
4746          * Find the pool from the end of the container, since mostly counter
4747          * ID is sequence increasing, and the last pool should be the needed
4748          * one.
4749          */
4750         i = cmng->n_valid;
4751         while (i--) {
4752                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4753
4754                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4755                         pool = pool_tmp;
4756                         break;
4757                 }
4758         }
4759 out:
4760         rte_spinlock_unlock(&cmng->pool_update_sl);
4761         return pool;
4762 }
4763
4764 /**
4765  * Resize a counter container.
4766  *
4767  * @param[in] dev
4768  *   Pointer to the Ethernet device structure.
4769  *
4770  * @return
4771  *   0 on success, otherwise negative errno value and rte_errno is set.
4772  */
4773 static int
4774 flow_dv_container_resize(struct rte_eth_dev *dev)
4775 {
4776         struct mlx5_priv *priv = dev->data->dev_private;
4777         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4778         void *old_pools = cmng->pools;
4779         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4780         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4781         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4782
4783         if (!pools) {
4784                 rte_errno = ENOMEM;
4785                 return -ENOMEM;
4786         }
4787         if (old_pools)
4788                 memcpy(pools, old_pools, cmng->n *
4789                                        sizeof(struct mlx5_flow_counter_pool *));
4790         cmng->n = resize;
4791         cmng->pools = pools;
4792         if (old_pools)
4793                 mlx5_free(old_pools);
4794         return 0;
4795 }
4796
4797 /**
4798  * Query a devx flow counter.
4799  *
4800  * @param[in] dev
4801  *   Pointer to the Ethernet device structure.
4802  * @param[in] cnt
4803  *   Index to the flow counter.
4804  * @param[out] pkts
4805  *   The statistics value of packets.
4806  * @param[out] bytes
4807  *   The statistics value of bytes.
4808  *
4809  * @return
4810  *   0 on success, otherwise a negative errno value and rte_errno is set.
4811  */
4812 static inline int
4813 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4814                      uint64_t *bytes)
4815 {
4816         struct mlx5_priv *priv = dev->data->dev_private;
4817         struct mlx5_flow_counter_pool *pool = NULL;
4818         struct mlx5_flow_counter *cnt;
4819         int offset;
4820
4821         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4822         MLX5_ASSERT(pool);
4823         if (priv->sh->cmng.counter_fallback)
4824                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4825                                         0, pkts, bytes, 0, NULL, NULL, 0);
4826         rte_spinlock_lock(&pool->sl);
4827         if (!pool->raw) {
4828                 *pkts = 0;
4829                 *bytes = 0;
4830         } else {
4831                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4832                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4833                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4834         }
4835         rte_spinlock_unlock(&pool->sl);
4836         return 0;
4837 }
4838
4839 /**
4840  * Create and initialize a new counter pool.
4841  *
4842  * @param[in] dev
4843  *   Pointer to the Ethernet device structure.
4844  * @param[out] dcs
4845  *   The devX counter handle.
4846  * @param[in] age
4847  *   Whether the pool is for counter that was allocated for aging.
4848  * @param[in/out] cont_cur
4849  *   Pointer to the container pointer, it will be update in pool resize.
4850  *
4851  * @return
4852  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4853  */
4854 static struct mlx5_flow_counter_pool *
4855 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4856                     uint32_t age)
4857 {
4858         struct mlx5_priv *priv = dev->data->dev_private;
4859         struct mlx5_flow_counter_pool *pool;
4860         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4861         bool fallback = priv->sh->cmng.counter_fallback;
4862         uint32_t size = sizeof(*pool);
4863
4864         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4865         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4866         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4867         if (!pool) {
4868                 rte_errno = ENOMEM;
4869                 return NULL;
4870         }
4871         pool->raw = NULL;
4872         pool->is_aged = !!age;
4873         pool->query_gen = 0;
4874         pool->min_dcs = dcs;
4875         rte_spinlock_init(&pool->sl);
4876         rte_spinlock_init(&pool->csl);
4877         TAILQ_INIT(&pool->counters[0]);
4878         TAILQ_INIT(&pool->counters[1]);
4879         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4880         rte_spinlock_lock(&cmng->pool_update_sl);
4881         pool->index = cmng->n_valid;
4882         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4883                 mlx5_free(pool);
4884                 rte_spinlock_unlock(&cmng->pool_update_sl);
4885                 return NULL;
4886         }
4887         cmng->pools[pool->index] = pool;
4888         cmng->n_valid++;
4889         if (unlikely(fallback)) {
4890                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4891
4892                 if (base < cmng->min_id)
4893                         cmng->min_id = base;
4894                 if (base > cmng->max_id)
4895                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4896                 cmng->last_pool_idx = pool->index;
4897         }
4898         rte_spinlock_unlock(&cmng->pool_update_sl);
4899         return pool;
4900 }
4901
4902 /**
4903  * Prepare a new counter and/or a new counter pool.
4904  *
4905  * @param[in] dev
4906  *   Pointer to the Ethernet device structure.
4907  * @param[out] cnt_free
4908  *   Where to put the pointer of a new counter.
4909  * @param[in] age
4910  *   Whether the pool is for counter that was allocated for aging.
4911  *
4912  * @return
4913  *   The counter pool pointer and @p cnt_free is set on success,
4914  *   NULL otherwise and rte_errno is set.
4915  */
4916 static struct mlx5_flow_counter_pool *
4917 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4918                              struct mlx5_flow_counter **cnt_free,
4919                              uint32_t age)
4920 {
4921         struct mlx5_priv *priv = dev->data->dev_private;
4922         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4923         struct mlx5_flow_counter_pool *pool;
4924         struct mlx5_counters tmp_tq;
4925         struct mlx5_devx_obj *dcs = NULL;
4926         struct mlx5_flow_counter *cnt;
4927         enum mlx5_counter_type cnt_type =
4928                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4929         bool fallback = priv->sh->cmng.counter_fallback;
4930         uint32_t i;
4931
4932         if (fallback) {
4933                 /* bulk_bitmap must be 0 for single counter allocation. */
4934                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4935                 if (!dcs)
4936                         return NULL;
4937                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4938                 if (!pool) {
4939                         pool = flow_dv_pool_create(dev, dcs, age);
4940                         if (!pool) {
4941                                 mlx5_devx_cmd_destroy(dcs);
4942                                 return NULL;
4943                         }
4944                 }
4945                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4946                 cnt = MLX5_POOL_GET_CNT(pool, i);
4947                 cnt->pool = pool;
4948                 cnt->dcs_when_free = dcs;
4949                 *cnt_free = cnt;
4950                 return pool;
4951         }
4952         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4953         if (!dcs) {
4954                 rte_errno = ENODATA;
4955                 return NULL;
4956         }
4957         pool = flow_dv_pool_create(dev, dcs, age);
4958         if (!pool) {
4959                 mlx5_devx_cmd_destroy(dcs);
4960                 return NULL;
4961         }
4962         TAILQ_INIT(&tmp_tq);
4963         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4964                 cnt = MLX5_POOL_GET_CNT(pool, i);
4965                 cnt->pool = pool;
4966                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4967         }
4968         rte_spinlock_lock(&cmng->csl[cnt_type]);
4969         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4970         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4971         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4972         (*cnt_free)->pool = pool;
4973         return pool;
4974 }
4975
4976 /**
4977  * Allocate a flow counter.
4978  *
4979  * @param[in] dev
4980  *   Pointer to the Ethernet device structure.
4981  * @param[in] age
4982  *   Whether the counter was allocated for aging.
4983  *
4984  * @return
4985  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4986  */
4987 static uint32_t
4988 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4989 {
4990         struct mlx5_priv *priv = dev->data->dev_private;
4991         struct mlx5_flow_counter_pool *pool = NULL;
4992         struct mlx5_flow_counter *cnt_free = NULL;
4993         bool fallback = priv->sh->cmng.counter_fallback;
4994         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4995         enum mlx5_counter_type cnt_type =
4996                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4997         uint32_t cnt_idx;
4998
4999         if (!priv->config.devx) {
5000                 rte_errno = ENOTSUP;
5001                 return 0;
5002         }
5003         /* Get free counters from container. */
5004         rte_spinlock_lock(&cmng->csl[cnt_type]);
5005         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5006         if (cnt_free)
5007                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5008         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5009         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5010                 goto err;
5011         pool = cnt_free->pool;
5012         if (fallback)
5013                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5014         /* Create a DV counter action only in the first time usage. */
5015         if (!cnt_free->action) {
5016                 uint16_t offset;
5017                 struct mlx5_devx_obj *dcs;
5018                 int ret;
5019
5020                 if (!fallback) {
5021                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5022                         dcs = pool->min_dcs;
5023                 } else {
5024                         offset = 0;
5025                         dcs = cnt_free->dcs_when_free;
5026                 }
5027                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5028                                                             &cnt_free->action);
5029                 if (ret) {
5030                         rte_errno = errno;
5031                         goto err;
5032                 }
5033         }
5034         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5035                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5036         /* Update the counter reset values. */
5037         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5038                                  &cnt_free->bytes))
5039                 goto err;
5040         if (!fallback && !priv->sh->cmng.query_thread_on)
5041                 /* Start the asynchronous batch query by the host thread. */
5042                 mlx5_set_query_alarm(priv->sh);
5043         return cnt_idx;
5044 err:
5045         if (cnt_free) {
5046                 cnt_free->pool = pool;
5047                 if (fallback)
5048                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5049                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5050                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5051                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5052         }
5053         return 0;
5054 }
5055
5056 /**
5057  * Allocate a shared flow counter.
5058  *
5059  * @param[in] ctx
5060  *   Pointer to the shared counter configuration.
5061  * @param[in] data
5062  *   Pointer to save the allocated counter index.
5063  *
5064  * @return
5065  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5066  */
5067
5068 static int32_t
5069 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5070 {
5071         struct mlx5_shared_counter_conf *conf = ctx;
5072         struct rte_eth_dev *dev = conf->dev;
5073         struct mlx5_flow_counter *cnt;
5074
5075         data->dword = flow_dv_counter_alloc(dev, 0);
5076         data->dword |= MLX5_CNT_SHARED_OFFSET;
5077         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5078         cnt->shared_info.id = conf->id;
5079         return 0;
5080 }
5081
5082 /**
5083  * Get a shared flow counter.
5084  *
5085  * @param[in] dev
5086  *   Pointer to the Ethernet device structure.
5087  * @param[in] id
5088  *   Counter identifier.
5089  *
5090  * @return
5091  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5092  */
5093 static uint32_t
5094 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5095 {
5096         struct mlx5_priv *priv = dev->data->dev_private;
5097         struct mlx5_shared_counter_conf conf = {
5098                 .dev = dev,
5099                 .id = id,
5100         };
5101         union mlx5_l3t_data data = {
5102                 .dword = 0,
5103         };
5104
5105         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5106                                flow_dv_counter_alloc_shared_cb, &conf);
5107         return data.dword;
5108 }
5109
5110 /**
5111  * Get age param from counter index.
5112  *
5113  * @param[in] dev
5114  *   Pointer to the Ethernet device structure.
5115  * @param[in] counter
5116  *   Index to the counter handler.
5117  *
5118  * @return
5119  *   The aging parameter specified for the counter index.
5120  */
5121 static struct mlx5_age_param*
5122 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5123                                 uint32_t counter)
5124 {
5125         struct mlx5_flow_counter *cnt;
5126         struct mlx5_flow_counter_pool *pool = NULL;
5127
5128         flow_dv_counter_get_by_idx(dev, counter, &pool);
5129         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5130         cnt = MLX5_POOL_GET_CNT(pool, counter);
5131         return MLX5_CNT_TO_AGE(cnt);
5132 }
5133
5134 /**
5135  * Remove a flow counter from aged counter list.
5136  *
5137  * @param[in] dev
5138  *   Pointer to the Ethernet device structure.
5139  * @param[in] counter
5140  *   Index to the counter handler.
5141  * @param[in] cnt
5142  *   Pointer to the counter handler.
5143  */
5144 static void
5145 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5146                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5147 {
5148         struct mlx5_age_info *age_info;
5149         struct mlx5_age_param *age_param;
5150         struct mlx5_priv *priv = dev->data->dev_private;
5151         uint16_t expected = AGE_CANDIDATE;
5152
5153         age_info = GET_PORT_AGE_INFO(priv);
5154         age_param = flow_dv_counter_idx_get_age(dev, counter);
5155         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5156                                          AGE_FREE, false, __ATOMIC_RELAXED,
5157                                          __ATOMIC_RELAXED)) {
5158                 /**
5159                  * We need the lock even it is age timeout,
5160                  * since counter may still in process.
5161                  */
5162                 rte_spinlock_lock(&age_info->aged_sl);
5163                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5164                 rte_spinlock_unlock(&age_info->aged_sl);
5165                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5166         }
5167 }
5168
5169 /**
5170  * Release a flow counter.
5171  *
5172  * @param[in] dev
5173  *   Pointer to the Ethernet device structure.
5174  * @param[in] counter
5175  *   Index to the counter handler.
5176  */
5177 static void
5178 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5179 {
5180         struct mlx5_priv *priv = dev->data->dev_private;
5181         struct mlx5_flow_counter_pool *pool = NULL;
5182         struct mlx5_flow_counter *cnt;
5183         enum mlx5_counter_type cnt_type;
5184
5185         if (!counter)
5186                 return;
5187         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5188         MLX5_ASSERT(pool);
5189         if (IS_SHARED_CNT(counter) &&
5190             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5191                 return;
5192         if (pool->is_aged)
5193                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5194         cnt->pool = pool;
5195         /*
5196          * Put the counter back to list to be updated in none fallback mode.
5197          * Currently, we are using two list alternately, while one is in query,
5198          * add the freed counter to the other list based on the pool query_gen
5199          * value. After query finishes, add counter the list to the global
5200          * container counter list. The list changes while query starts. In
5201          * this case, lock will not be needed as query callback and release
5202          * function both operate with the different list.
5203          *
5204          */
5205         if (!priv->sh->cmng.counter_fallback) {
5206                 rte_spinlock_lock(&pool->csl);
5207                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5208                 rte_spinlock_unlock(&pool->csl);
5209         } else {
5210                 cnt->dcs_when_free = cnt->dcs_when_active;
5211                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5212                                            MLX5_COUNTER_TYPE_ORIGIN;
5213                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5214                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5215                                   cnt, next);
5216                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5217         }
5218 }
5219
5220 /**
5221  * Verify the @p attributes will be correctly understood by the NIC and store
5222  * them in the @p flow if everything is correct.
5223  *
5224  * @param[in] dev
5225  *   Pointer to dev struct.
5226  * @param[in] attributes
5227  *   Pointer to flow attributes
5228  * @param[in] external
5229  *   This flow rule is created by request external to PMD.
5230  * @param[out] error
5231  *   Pointer to error structure.
5232  *
5233  * @return
5234  *   - 0 on success and non root table.
5235  *   - 1 on success and root table.
5236  *   - a negative errno value otherwise and rte_errno is set.
5237  */
5238 static int
5239 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5240                             const struct mlx5_flow_tunnel *tunnel,
5241                             const struct rte_flow_attr *attributes,
5242                             const struct flow_grp_info *grp_info,
5243                             struct rte_flow_error *error)
5244 {
5245         struct mlx5_priv *priv = dev->data->dev_private;
5246         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5247         int ret = 0;
5248
5249 #ifndef HAVE_MLX5DV_DR
5250         RTE_SET_USED(tunnel);
5251         RTE_SET_USED(grp_info);
5252         if (attributes->group)
5253                 return rte_flow_error_set(error, ENOTSUP,
5254                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5255                                           NULL,
5256                                           "groups are not supported");
5257 #else
5258         uint32_t table = 0;
5259
5260         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5261                                        grp_info, error);
5262         if (ret)
5263                 return ret;
5264         if (!table)
5265                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5266 #endif
5267         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5268             attributes->priority > lowest_priority)
5269                 return rte_flow_error_set(error, ENOTSUP,
5270                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5271                                           NULL,
5272                                           "priority out of range");
5273         if (attributes->transfer) {
5274                 if (!priv->config.dv_esw_en)
5275                         return rte_flow_error_set
5276                                 (error, ENOTSUP,
5277                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5278                                  "E-Switch dr is not supported");
5279                 if (!(priv->representor || priv->master))
5280                         return rte_flow_error_set
5281                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5282                                  NULL, "E-Switch configuration can only be"
5283                                  " done by a master or a representor device");
5284                 if (attributes->egress)
5285                         return rte_flow_error_set
5286                                 (error, ENOTSUP,
5287                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5288                                  "egress is not supported");
5289         }
5290         if (!(attributes->egress ^ attributes->ingress))
5291                 return rte_flow_error_set(error, ENOTSUP,
5292                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5293                                           "must specify exactly one of "
5294                                           "ingress or egress");
5295         return ret;
5296 }
5297
5298 /**
5299  * Internal validation function. For validating both actions and items.
5300  *
5301  * @param[in] dev
5302  *   Pointer to the rte_eth_dev structure.
5303  * @param[in] attr
5304  *   Pointer to the flow attributes.
5305  * @param[in] items
5306  *   Pointer to the list of items.
5307  * @param[in] actions
5308  *   Pointer to the list of actions.
5309  * @param[in] external
5310  *   This flow rule is created by request external to PMD.
5311  * @param[in] hairpin
5312  *   Number of hairpin TX actions, 0 means classic flow.
5313  * @param[out] error
5314  *   Pointer to the error structure.
5315  *
5316  * @return
5317  *   0 on success, a negative errno value otherwise and rte_errno is set.
5318  */
5319 static int
5320 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5321                  const struct rte_flow_item items[],
5322                  const struct rte_flow_action actions[],
5323                  bool external, int hairpin, struct rte_flow_error *error)
5324 {
5325         int ret;
5326         uint64_t action_flags = 0;
5327         uint64_t item_flags = 0;
5328         uint64_t last_item = 0;
5329         uint8_t next_protocol = 0xff;
5330         uint16_t ether_type = 0;
5331         int actions_n = 0;
5332         uint8_t item_ipv6_proto = 0;
5333         const struct rte_flow_item *geneve_item = NULL;
5334         const struct rte_flow_item *gre_item = NULL;
5335         const struct rte_flow_item *gtp_item = NULL;
5336         const struct rte_flow_action_raw_decap *decap;
5337         const struct rte_flow_action_raw_encap *encap;
5338         const struct rte_flow_action_rss *rss = NULL;
5339         const struct rte_flow_action_rss *sample_rss = NULL;
5340         const struct rte_flow_item_tcp nic_tcp_mask = {
5341                 .hdr = {
5342                         .tcp_flags = 0xFF,
5343                         .src_port = RTE_BE16(UINT16_MAX),
5344                         .dst_port = RTE_BE16(UINT16_MAX),
5345                 }
5346         };
5347         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5348                 .hdr = {
5349                         .src_addr =
5350                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5351                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5352                         .dst_addr =
5353                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5354                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5355                         .vtc_flow = RTE_BE32(0xffffffff),
5356                         .proto = 0xff,
5357                         .hop_limits = 0xff,
5358                 },
5359                 .has_frag_ext = 1,
5360         };
5361         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5362                 .hdr = {
5363                         .common = {
5364                                 .u32 =
5365                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5366                                         .type = 0xFF,
5367                                         }).u32),
5368                         },
5369                         .dummy[0] = 0xffffffff,
5370                 },
5371         };
5372         struct mlx5_priv *priv = dev->data->dev_private;
5373         struct mlx5_dev_config *dev_conf = &priv->config;
5374         uint16_t queue_index = 0xFFFF;
5375         const struct rte_flow_item_vlan *vlan_m = NULL;
5376         int16_t rw_act_num = 0;
5377         uint64_t is_root;
5378         const struct mlx5_flow_tunnel *tunnel;
5379         struct flow_grp_info grp_info = {
5380                 .external = !!external,
5381                 .transfer = !!attr->transfer,
5382                 .fdb_def_rule = !!priv->fdb_def_rule,
5383         };
5384         const struct rte_eth_hairpin_conf *conf;
5385
5386         if (items == NULL)
5387                 return -1;
5388         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5389                 tunnel = flow_items_to_tunnel(items);
5390                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5391                                 MLX5_FLOW_ACTION_DECAP;
5392         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5393                 tunnel = flow_actions_to_tunnel(actions);
5394                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5395         } else {
5396                 tunnel = NULL;
5397         }
5398         if (tunnel && priv->representor)
5399                 return rte_flow_error_set(error, ENOTSUP,
5400                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5401                                           "decap not supported "
5402                                           "for VF representor");
5403         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5404                                 (dev, tunnel, attr, items, actions);
5405         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5406         if (ret < 0)
5407                 return ret;
5408         is_root = (uint64_t)ret;
5409         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5410                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5411                 int type = items->type;
5412
5413                 if (!mlx5_flow_os_item_supported(type))
5414                         return rte_flow_error_set(error, ENOTSUP,
5415                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5416                                                   NULL, "item not supported");
5417                 switch (type) {
5418                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5419                         if (items[0].type != (typeof(items[0].type))
5420                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5421                                 return rte_flow_error_set
5422                                                 (error, EINVAL,
5423                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5424                                                 NULL, "MLX5 private items "
5425                                                 "must be the first");
5426                         break;
5427                 case RTE_FLOW_ITEM_TYPE_VOID:
5428                         break;
5429                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5430                         ret = flow_dv_validate_item_port_id
5431                                         (dev, items, attr, item_flags, error);
5432                         if (ret < 0)
5433                                 return ret;
5434                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5435                         break;
5436                 case RTE_FLOW_ITEM_TYPE_ETH:
5437                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5438                                                           true, error);
5439                         if (ret < 0)
5440                                 return ret;
5441                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5442                                              MLX5_FLOW_LAYER_OUTER_L2;
5443                         if (items->mask != NULL && items->spec != NULL) {
5444                                 ether_type =
5445                                         ((const struct rte_flow_item_eth *)
5446                                          items->spec)->type;
5447                                 ether_type &=
5448                                         ((const struct rte_flow_item_eth *)
5449                                          items->mask)->type;
5450                                 ether_type = rte_be_to_cpu_16(ether_type);
5451                         } else {
5452                                 ether_type = 0;
5453                         }
5454                         break;
5455                 case RTE_FLOW_ITEM_TYPE_VLAN:
5456                         ret = flow_dv_validate_item_vlan(items, item_flags,
5457                                                          dev, error);
5458                         if (ret < 0)
5459                                 return ret;
5460                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5461                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5462                         if (items->mask != NULL && items->spec != NULL) {
5463                                 ether_type =
5464                                         ((const struct rte_flow_item_vlan *)
5465                                          items->spec)->inner_type;
5466                                 ether_type &=
5467                                         ((const struct rte_flow_item_vlan *)
5468                                          items->mask)->inner_type;
5469                                 ether_type = rte_be_to_cpu_16(ether_type);
5470                         } else {
5471                                 ether_type = 0;
5472                         }
5473                         /* Store outer VLAN mask for of_push_vlan action. */
5474                         if (!tunnel)
5475                                 vlan_m = items->mask;
5476                         break;
5477                 case RTE_FLOW_ITEM_TYPE_IPV4:
5478                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5479                                                   &item_flags, &tunnel);
5480                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5481                                                          last_item, ether_type,
5482                                                          error);
5483                         if (ret < 0)
5484                                 return ret;
5485                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5486                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5487                         if (items->mask != NULL &&
5488                             ((const struct rte_flow_item_ipv4 *)
5489                              items->mask)->hdr.next_proto_id) {
5490                                 next_protocol =
5491                                         ((const struct rte_flow_item_ipv4 *)
5492                                          (items->spec))->hdr.next_proto_id;
5493                                 next_protocol &=
5494                                         ((const struct rte_flow_item_ipv4 *)
5495                                          (items->mask))->hdr.next_proto_id;
5496                         } else {
5497                                 /* Reset for inner layer. */
5498                                 next_protocol = 0xff;
5499                         }
5500                         break;
5501                 case RTE_FLOW_ITEM_TYPE_IPV6:
5502                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5503                                                   &item_flags, &tunnel);
5504                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5505                                                            last_item,
5506                                                            ether_type,
5507                                                            &nic_ipv6_mask,
5508                                                            error);
5509                         if (ret < 0)
5510                                 return ret;
5511                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5512                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5513                         if (items->mask != NULL &&
5514                             ((const struct rte_flow_item_ipv6 *)
5515                              items->mask)->hdr.proto) {
5516                                 item_ipv6_proto =
5517                                         ((const struct rte_flow_item_ipv6 *)
5518                                          items->spec)->hdr.proto;
5519                                 next_protocol =
5520                                         ((const struct rte_flow_item_ipv6 *)
5521                                          items->spec)->hdr.proto;
5522                                 next_protocol &=
5523                                         ((const struct rte_flow_item_ipv6 *)
5524                                          items->mask)->hdr.proto;
5525                         } else {
5526                                 /* Reset for inner layer. */
5527                                 next_protocol = 0xff;
5528                         }
5529                         break;
5530                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5531                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5532                                                                   item_flags,
5533                                                                   error);
5534                         if (ret < 0)
5535                                 return ret;
5536                         last_item = tunnel ?
5537                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5538                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5539                         if (items->mask != NULL &&
5540                             ((const struct rte_flow_item_ipv6_frag_ext *)
5541                              items->mask)->hdr.next_header) {
5542                                 next_protocol =
5543                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5544                                  items->spec)->hdr.next_header;
5545                                 next_protocol &=
5546                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5547                                  items->mask)->hdr.next_header;
5548                         } else {
5549                                 /* Reset for inner layer. */
5550                                 next_protocol = 0xff;
5551                         }
5552                         break;
5553                 case RTE_FLOW_ITEM_TYPE_TCP:
5554                         ret = mlx5_flow_validate_item_tcp
5555                                                 (items, item_flags,
5556                                                  next_protocol,
5557                                                  &nic_tcp_mask,
5558                                                  error);
5559                         if (ret < 0)
5560                                 return ret;
5561                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5562                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5563                         break;
5564                 case RTE_FLOW_ITEM_TYPE_UDP:
5565                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5566                                                           next_protocol,
5567                                                           error);
5568                         if (ret < 0)
5569                                 return ret;
5570                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5571                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5572                         break;
5573                 case RTE_FLOW_ITEM_TYPE_GRE:
5574                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5575                                                           next_protocol, error);
5576                         if (ret < 0)
5577                                 return ret;
5578                         gre_item = items;
5579                         last_item = MLX5_FLOW_LAYER_GRE;
5580                         break;
5581                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5582                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5583                                                             next_protocol,
5584                                                             error);
5585                         if (ret < 0)
5586                                 return ret;
5587                         last_item = MLX5_FLOW_LAYER_NVGRE;
5588                         break;
5589                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5590                         ret = mlx5_flow_validate_item_gre_key
5591                                 (items, item_flags, gre_item, error);
5592                         if (ret < 0)
5593                                 return ret;
5594                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5595                         break;
5596                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5597                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5598                                                             error);
5599                         if (ret < 0)
5600                                 return ret;
5601                         last_item = MLX5_FLOW_LAYER_VXLAN;
5602                         break;
5603                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5604                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5605                                                                 item_flags, dev,
5606                                                                 error);
5607                         if (ret < 0)
5608                                 return ret;
5609                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5610                         break;
5611                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5612                         ret = mlx5_flow_validate_item_geneve(items,
5613                                                              item_flags, dev,
5614                                                              error);
5615                         if (ret < 0)
5616                                 return ret;
5617                         geneve_item = items;
5618                         last_item = MLX5_FLOW_LAYER_GENEVE;
5619                         break;
5620                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
5621                         ret = mlx5_flow_validate_item_geneve_opt(items,
5622                                                                  last_item,
5623                                                                  geneve_item,
5624                                                                  dev,
5625                                                                  error);
5626                         if (ret < 0)
5627                                 return ret;
5628                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
5629                         break;
5630                 case RTE_FLOW_ITEM_TYPE_MPLS:
5631                         ret = mlx5_flow_validate_item_mpls(dev, items,
5632                                                            item_flags,
5633                                                            last_item, error);
5634                         if (ret < 0)
5635                                 return ret;
5636                         last_item = MLX5_FLOW_LAYER_MPLS;
5637                         break;
5638
5639                 case RTE_FLOW_ITEM_TYPE_MARK:
5640                         ret = flow_dv_validate_item_mark(dev, items, attr,
5641                                                          error);
5642                         if (ret < 0)
5643                                 return ret;
5644                         last_item = MLX5_FLOW_ITEM_MARK;
5645                         break;
5646                 case RTE_FLOW_ITEM_TYPE_META:
5647                         ret = flow_dv_validate_item_meta(dev, items, attr,
5648                                                          error);
5649                         if (ret < 0)
5650                                 return ret;
5651                         last_item = MLX5_FLOW_ITEM_METADATA;
5652                         break;
5653                 case RTE_FLOW_ITEM_TYPE_ICMP:
5654                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5655                                                            next_protocol,
5656                                                            error);
5657                         if (ret < 0)
5658                                 return ret;
5659                         last_item = MLX5_FLOW_LAYER_ICMP;
5660                         break;
5661                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5662                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5663                                                             next_protocol,
5664                                                             error);
5665                         if (ret < 0)
5666                                 return ret;
5667                         item_ipv6_proto = IPPROTO_ICMPV6;
5668                         last_item = MLX5_FLOW_LAYER_ICMP6;
5669                         break;
5670                 case RTE_FLOW_ITEM_TYPE_TAG:
5671                         ret = flow_dv_validate_item_tag(dev, items,
5672                                                         attr, error);
5673                         if (ret < 0)
5674                                 return ret;
5675                         last_item = MLX5_FLOW_ITEM_TAG;
5676                         break;
5677                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5678                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5679                         break;
5680                 case RTE_FLOW_ITEM_TYPE_GTP:
5681                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5682                                                         error);
5683                         if (ret < 0)
5684                                 return ret;
5685                         gtp_item = items;
5686                         last_item = MLX5_FLOW_LAYER_GTP;
5687                         break;
5688                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5689                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
5690                                                             gtp_item, attr,
5691                                                             error);
5692                         if (ret < 0)
5693                                 return ret;
5694                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
5695                         break;
5696                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5697                         /* Capacity will be checked in the translate stage. */
5698                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5699                                                             last_item,
5700                                                             ether_type,
5701                                                             &nic_ecpri_mask,
5702                                                             error);
5703                         if (ret < 0)
5704                                 return ret;
5705                         last_item = MLX5_FLOW_LAYER_ECPRI;
5706                         break;
5707                 default:
5708                         return rte_flow_error_set(error, ENOTSUP,
5709                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5710                                                   NULL, "item not supported");
5711                 }
5712                 item_flags |= last_item;
5713         }
5714         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5715                 int type = actions->type;
5716
5717                 if (!mlx5_flow_os_action_supported(type))
5718                         return rte_flow_error_set(error, ENOTSUP,
5719                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5720                                                   actions,
5721                                                   "action not supported");
5722                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5723                         return rte_flow_error_set(error, ENOTSUP,
5724                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5725                                                   actions, "too many actions");
5726                 switch (type) {
5727                 case RTE_FLOW_ACTION_TYPE_VOID:
5728                         break;
5729                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5730                         ret = flow_dv_validate_action_port_id(dev,
5731                                                               action_flags,
5732                                                               actions,
5733                                                               attr,
5734                                                               error);
5735                         if (ret)
5736                                 return ret;
5737                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5738                         ++actions_n;
5739                         break;
5740                 case RTE_FLOW_ACTION_TYPE_FLAG:
5741                         ret = flow_dv_validate_action_flag(dev, action_flags,
5742                                                            attr, error);
5743                         if (ret < 0)
5744                                 return ret;
5745                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5746                                 /* Count all modify-header actions as one. */
5747                                 if (!(action_flags &
5748                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5749                                         ++actions_n;
5750                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5751                                                 MLX5_FLOW_ACTION_MARK_EXT;
5752                         } else {
5753                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5754                                 ++actions_n;
5755                         }
5756                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5757                         break;
5758                 case RTE_FLOW_ACTION_TYPE_MARK:
5759                         ret = flow_dv_validate_action_mark(dev, actions,
5760                                                            action_flags,
5761                                                            attr, error);
5762                         if (ret < 0)
5763                                 return ret;
5764                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5765                                 /* Count all modify-header actions as one. */
5766                                 if (!(action_flags &
5767                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5768                                         ++actions_n;
5769                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5770                                                 MLX5_FLOW_ACTION_MARK_EXT;
5771                         } else {
5772                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5773                                 ++actions_n;
5774                         }
5775                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5776                         break;
5777                 case RTE_FLOW_ACTION_TYPE_SET_META:
5778                         ret = flow_dv_validate_action_set_meta(dev, actions,
5779                                                                action_flags,
5780                                                                attr, error);
5781                         if (ret < 0)
5782                                 return ret;
5783                         /* Count all modify-header actions as one action. */
5784                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5785                                 ++actions_n;
5786                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5787                         rw_act_num += MLX5_ACT_NUM_SET_META;
5788                         break;
5789                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5790                         ret = flow_dv_validate_action_set_tag(dev, actions,
5791                                                               action_flags,
5792                                                               attr, error);
5793                         if (ret < 0)
5794                                 return ret;
5795                         /* Count all modify-header actions as one action. */
5796                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5797                                 ++actions_n;
5798                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5799                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5800                         break;
5801                 case RTE_FLOW_ACTION_TYPE_DROP:
5802                         ret = mlx5_flow_validate_action_drop(action_flags,
5803                                                              attr, error);
5804                         if (ret < 0)
5805                                 return ret;
5806                         action_flags |= MLX5_FLOW_ACTION_DROP;
5807                         ++actions_n;
5808                         break;
5809                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5810                         ret = mlx5_flow_validate_action_queue(actions,
5811                                                               action_flags, dev,
5812                                                               attr, error);
5813                         if (ret < 0)
5814                                 return ret;
5815                         queue_index = ((const struct rte_flow_action_queue *)
5816                                                         (actions->conf))->index;
5817                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5818                         ++actions_n;
5819                         break;
5820                 case RTE_FLOW_ACTION_TYPE_RSS:
5821                         rss = actions->conf;
5822                         ret = mlx5_flow_validate_action_rss(actions,
5823                                                             action_flags, dev,
5824                                                             attr, item_flags,
5825                                                             error);
5826                         if (ret < 0)
5827                                 return ret;
5828                         if (rss && sample_rss &&
5829                             (sample_rss->level != rss->level ||
5830                             sample_rss->types != rss->types))
5831                                 return rte_flow_error_set(error, ENOTSUP,
5832                                         RTE_FLOW_ERROR_TYPE_ACTION,
5833                                         NULL,
5834                                         "Can't use the different RSS types "
5835                                         "or level in the same flow");
5836                         if (rss != NULL && rss->queue_num)
5837                                 queue_index = rss->queue[0];
5838                         action_flags |= MLX5_FLOW_ACTION_RSS;
5839                         ++actions_n;
5840                         break;
5841                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5842                         ret =
5843                         mlx5_flow_validate_action_default_miss(action_flags,
5844                                         attr, error);
5845                         if (ret < 0)
5846                                 return ret;
5847                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5848                         ++actions_n;
5849                         break;
5850                 case RTE_FLOW_ACTION_TYPE_COUNT:
5851                         ret = flow_dv_validate_action_count(dev, error);
5852                         if (ret < 0)
5853                                 return ret;
5854                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5855                         ++actions_n;
5856                         break;
5857                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5858                         if (flow_dv_validate_action_pop_vlan(dev,
5859                                                              action_flags,
5860                                                              actions,
5861                                                              item_flags, attr,
5862                                                              error))
5863                                 return -rte_errno;
5864                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5865                         ++actions_n;
5866                         break;
5867                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5868                         ret = flow_dv_validate_action_push_vlan(dev,
5869                                                                 action_flags,
5870                                                                 vlan_m,
5871                                                                 actions, attr,
5872                                                                 error);
5873                         if (ret < 0)
5874                                 return ret;
5875                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5876                         ++actions_n;
5877                         break;
5878                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5879                         ret = flow_dv_validate_action_set_vlan_pcp
5880                                                 (action_flags, actions, error);
5881                         if (ret < 0)
5882                                 return ret;
5883                         /* Count PCP with push_vlan command. */
5884                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5885                         break;
5886                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5887                         ret = flow_dv_validate_action_set_vlan_vid
5888                                                 (item_flags, action_flags,
5889                                                  actions, error);
5890                         if (ret < 0)
5891                                 return ret;
5892                         /* Count VID with push_vlan command. */
5893                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5894                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5895                         break;
5896                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5897                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5898                         ret = flow_dv_validate_action_l2_encap(dev,
5899                                                                action_flags,
5900                                                                actions, attr,
5901                                                                error);
5902                         if (ret < 0)
5903                                 return ret;
5904                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5905                         ++actions_n;
5906                         break;
5907                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5908                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5909                         ret = flow_dv_validate_action_decap(dev, action_flags,
5910                                                             actions, item_flags,
5911                                                             attr, error);
5912                         if (ret < 0)
5913                                 return ret;
5914                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5915                         ++actions_n;
5916                         break;
5917                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5918                         ret = flow_dv_validate_action_raw_encap_decap
5919                                 (dev, NULL, actions->conf, attr, &action_flags,
5920                                  &actions_n, actions, item_flags, error);
5921                         if (ret < 0)
5922                                 return ret;
5923                         break;
5924                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5925                         decap = actions->conf;
5926                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5927                                 ;
5928                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5929                                 encap = NULL;
5930                                 actions--;
5931                         } else {
5932                                 encap = actions->conf;
5933                         }
5934                         ret = flow_dv_validate_action_raw_encap_decap
5935                                            (dev,
5936                                             decap ? decap : &empty_decap, encap,
5937                                             attr, &action_flags, &actions_n,
5938                                             actions, item_flags, error);
5939                         if (ret < 0)
5940                                 return ret;
5941                         break;
5942                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5943                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5944                         ret = flow_dv_validate_action_modify_mac(action_flags,
5945                                                                  actions,
5946                                                                  item_flags,
5947                                                                  error);
5948                         if (ret < 0)
5949                                 return ret;
5950                         /* Count all modify-header actions as one action. */
5951                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5952                                 ++actions_n;
5953                         action_flags |= actions->type ==
5954                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5955                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5956                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5957                         /*
5958                          * Even if the source and destination MAC addresses have
5959                          * overlap in the header with 4B alignment, the convert
5960                          * function will handle them separately and 4 SW actions
5961                          * will be created. And 2 actions will be added each
5962                          * time no matter how many bytes of address will be set.
5963                          */
5964                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5965                         break;
5966                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5967                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5968                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5969                                                                   actions,
5970                                                                   item_flags,
5971                                                                   error);
5972                         if (ret < 0)
5973                                 return ret;
5974                         /* Count all modify-header actions as one action. */
5975                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5976                                 ++actions_n;
5977                         action_flags |= actions->type ==
5978                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5979                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5980                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5981                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5982                         break;
5983                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5984                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5985                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5986                                                                   actions,
5987                                                                   item_flags,
5988                                                                   error);
5989                         if (ret < 0)
5990                                 return ret;
5991                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5992                                 return rte_flow_error_set(error, ENOTSUP,
5993                                         RTE_FLOW_ERROR_TYPE_ACTION,
5994                                         actions,
5995                                         "Can't change header "
5996                                         "with ICMPv6 proto");
5997                         /* Count all modify-header actions as one action. */
5998                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5999                                 ++actions_n;
6000                         action_flags |= actions->type ==
6001                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6002                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6003                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6004                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6005                         break;
6006                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6007                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6008                         ret = flow_dv_validate_action_modify_tp(action_flags,
6009                                                                 actions,
6010                                                                 item_flags,
6011                                                                 error);
6012                         if (ret < 0)
6013                                 return ret;
6014                         /* Count all modify-header actions as one action. */
6015                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6016                                 ++actions_n;
6017                         action_flags |= actions->type ==
6018                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6019                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6020                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6021                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6022                         break;
6023                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6024                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6025                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6026                                                                  actions,
6027                                                                  item_flags,
6028                                                                  error);
6029                         if (ret < 0)
6030                                 return ret;
6031                         /* Count all modify-header actions as one action. */
6032                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6033                                 ++actions_n;
6034                         action_flags |= actions->type ==
6035                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6036                                                 MLX5_FLOW_ACTION_SET_TTL :
6037                                                 MLX5_FLOW_ACTION_DEC_TTL;
6038                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6039                         break;
6040                 case RTE_FLOW_ACTION_TYPE_JUMP:
6041                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6042                                                            action_flags,
6043                                                            attr, external,
6044                                                            error);
6045                         if (ret)
6046                                 return ret;
6047                         ++actions_n;
6048                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6049                         break;
6050                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6051                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6052                         ret = flow_dv_validate_action_modify_tcp_seq
6053                                                                 (action_flags,
6054                                                                  actions,
6055                                                                  item_flags,
6056                                                                  error);
6057                         if (ret < 0)
6058                                 return ret;
6059                         /* Count all modify-header actions as one action. */
6060                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6061                                 ++actions_n;
6062                         action_flags |= actions->type ==
6063                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6064                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6065                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6066                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6067                         break;
6068                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6069                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6070                         ret = flow_dv_validate_action_modify_tcp_ack
6071                                                                 (action_flags,
6072                                                                  actions,
6073                                                                  item_flags,
6074                                                                  error);
6075                         if (ret < 0)
6076                                 return ret;
6077                         /* Count all modify-header actions as one action. */
6078                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6079                                 ++actions_n;
6080                         action_flags |= actions->type ==
6081                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6082                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6083                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6084                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6085                         break;
6086                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6087                         break;
6088                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6089                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6090                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6091                         break;
6092                 case RTE_FLOW_ACTION_TYPE_METER:
6093                         ret = mlx5_flow_validate_action_meter(dev,
6094                                                               action_flags,
6095                                                               actions, attr,
6096                                                               error);
6097                         if (ret < 0)
6098                                 return ret;
6099                         action_flags |= MLX5_FLOW_ACTION_METER;
6100                         ++actions_n;
6101                         /* Meter action will add one more TAG action. */
6102                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6103                         break;
6104                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6105                         if (!attr->transfer && !attr->group)
6106                                 return rte_flow_error_set(error, ENOTSUP,
6107                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6108                                                                            NULL,
6109                           "Shared ASO age action is not supported for group 0");
6110                         action_flags |= MLX5_FLOW_ACTION_AGE;
6111                         ++actions_n;
6112                         break;
6113                 case RTE_FLOW_ACTION_TYPE_AGE:
6114                         ret = flow_dv_validate_action_age(action_flags,
6115                                                           actions, dev,
6116                                                           error);
6117                         if (ret < 0)
6118                                 return ret;
6119                         action_flags |= MLX5_FLOW_ACTION_AGE;
6120                         ++actions_n;
6121                         break;
6122                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6123                         ret = flow_dv_validate_action_modify_ipv4_dscp
6124                                                          (action_flags,
6125                                                           actions,
6126                                                           item_flags,
6127                                                           error);
6128                         if (ret < 0)
6129                                 return ret;
6130                         /* Count all modify-header actions as one action. */
6131                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6132                                 ++actions_n;
6133                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6134                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6135                         break;
6136                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6137                         ret = flow_dv_validate_action_modify_ipv6_dscp
6138                                                                 (action_flags,
6139                                                                  actions,
6140                                                                  item_flags,
6141                                                                  error);
6142                         if (ret < 0)
6143                                 return ret;
6144                         /* Count all modify-header actions as one action. */
6145                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6146                                 ++actions_n;
6147                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6148                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6149                         break;
6150                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6151                         ret = flow_dv_validate_action_sample(action_flags,
6152                                                              actions, dev,
6153                                                              attr, item_flags,
6154                                                              rss, &sample_rss,
6155                                                              error);
6156                         if (ret < 0)
6157                                 return ret;
6158                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6159                         ++actions_n;
6160                         break;
6161                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6162                         if (actions[0].type != (typeof(actions[0].type))
6163                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6164                                 return rte_flow_error_set
6165                                                 (error, EINVAL,
6166                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6167                                                 NULL, "MLX5 private action "
6168                                                 "must be the first");
6169
6170                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6171                         break;
6172                 default:
6173                         return rte_flow_error_set(error, ENOTSUP,
6174                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6175                                                   actions,
6176                                                   "action not supported");
6177                 }
6178         }
6179         /*
6180          * Validate actions in flow rules
6181          * - Explicit decap action is prohibited by the tunnel offload API.
6182          * - Drop action in tunnel steer rule is prohibited by the API.
6183          * - Application cannot use MARK action because it's value can mask
6184          *   tunnel default miss nitification.
6185          * - JUMP in tunnel match rule has no support in current PMD
6186          *   implementation.
6187          * - TAG & META are reserved for future uses.
6188          */
6189         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6190                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6191                                             MLX5_FLOW_ACTION_MARK     |
6192                                             MLX5_FLOW_ACTION_SET_TAG  |
6193                                             MLX5_FLOW_ACTION_SET_META |
6194                                             MLX5_FLOW_ACTION_DROP;
6195
6196                 if (action_flags & bad_actions_mask)
6197                         return rte_flow_error_set
6198                                         (error, EINVAL,
6199                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6200                                         "Invalid RTE action in tunnel "
6201                                         "set decap rule");
6202                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6203                         return rte_flow_error_set
6204                                         (error, EINVAL,
6205                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6206                                         "tunnel set decap rule must terminate "
6207                                         "with JUMP");
6208                 if (!attr->ingress)
6209                         return rte_flow_error_set
6210                                         (error, EINVAL,
6211                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6212                                         "tunnel flows for ingress traffic only");
6213         }
6214         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6215                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6216                                             MLX5_FLOW_ACTION_MARK    |
6217                                             MLX5_FLOW_ACTION_SET_TAG |
6218                                             MLX5_FLOW_ACTION_SET_META;
6219
6220                 if (action_flags & bad_actions_mask)
6221                         return rte_flow_error_set
6222                                         (error, EINVAL,
6223                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6224                                         "Invalid RTE action in tunnel "
6225                                         "set match rule");
6226         }
6227         /*
6228          * Validate the drop action mutual exclusion with other actions.
6229          * Drop action is mutually-exclusive with any other action, except for
6230          * Count action.
6231          */
6232         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6233             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6234                 return rte_flow_error_set(error, EINVAL,
6235                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6236                                           "Drop action is mutually-exclusive "
6237                                           "with any other action, except for "
6238                                           "Count action");
6239         /* Eswitch has few restrictions on using items and actions */
6240         if (attr->transfer) {
6241                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6242                     action_flags & MLX5_FLOW_ACTION_FLAG)
6243                         return rte_flow_error_set(error, ENOTSUP,
6244                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6245                                                   NULL,
6246                                                   "unsupported action FLAG");
6247                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6248                     action_flags & MLX5_FLOW_ACTION_MARK)
6249                         return rte_flow_error_set(error, ENOTSUP,
6250                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6251                                                   NULL,
6252                                                   "unsupported action MARK");
6253                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6254                         return rte_flow_error_set(error, ENOTSUP,
6255                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6256                                                   NULL,
6257                                                   "unsupported action QUEUE");
6258                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6259                         return rte_flow_error_set(error, ENOTSUP,
6260                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6261                                                   NULL,
6262                                                   "unsupported action RSS");
6263                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6264                         return rte_flow_error_set(error, EINVAL,
6265                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6266                                                   actions,
6267                                                   "no fate action is found");
6268         } else {
6269                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6270                         return rte_flow_error_set(error, EINVAL,
6271                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6272                                                   actions,
6273                                                   "no fate action is found");
6274         }
6275         /*
6276          * Continue validation for Xcap and VLAN actions.
6277          * If hairpin is working in explicit TX rule mode, there is no actions
6278          * splitting and the validation of hairpin ingress flow should be the
6279          * same as other standard flows.
6280          */
6281         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6282                              MLX5_FLOW_VLAN_ACTIONS)) &&
6283             (queue_index == 0xFFFF ||
6284              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6285              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6286              conf->tx_explicit != 0))) {
6287                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6288                     MLX5_FLOW_XCAP_ACTIONS)
6289                         return rte_flow_error_set(error, ENOTSUP,
6290                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6291                                                   NULL, "encap and decap "
6292                                                   "combination aren't supported");
6293                 if (!attr->transfer && attr->ingress) {
6294                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6295                                 return rte_flow_error_set
6296                                                 (error, ENOTSUP,
6297                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6298                                                  NULL, "encap is not supported"
6299                                                  " for ingress traffic");
6300                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6301                                 return rte_flow_error_set
6302                                                 (error, ENOTSUP,
6303                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6304                                                  NULL, "push VLAN action not "
6305                                                  "supported for ingress");
6306                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6307                                         MLX5_FLOW_VLAN_ACTIONS)
6308                                 return rte_flow_error_set
6309                                                 (error, ENOTSUP,
6310                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6311                                                  NULL, "no support for "
6312                                                  "multiple VLAN actions");
6313                 }
6314         }
6315         /*
6316          * Hairpin flow will add one more TAG action in TX implicit mode.
6317          * In TX explicit mode, there will be no hairpin flow ID.
6318          */
6319         if (hairpin > 0)
6320                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6321         /* extra metadata enabled: one more TAG action will be add. */
6322         if (dev_conf->dv_flow_en &&
6323             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6324             mlx5_flow_ext_mreg_supported(dev))
6325                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6326         if ((uint32_t)rw_act_num >
6327                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6328                 return rte_flow_error_set(error, ENOTSUP,
6329                                           RTE_FLOW_ERROR_TYPE_ACTION,
6330                                           NULL, "too many header modify"
6331                                           " actions to support");
6332         }
6333         return 0;
6334 }
6335
6336 /**
6337  * Internal preparation function. Allocates the DV flow size,
6338  * this size is constant.
6339  *
6340  * @param[in] dev
6341  *   Pointer to the rte_eth_dev structure.
6342  * @param[in] attr
6343  *   Pointer to the flow attributes.
6344  * @param[in] items
6345  *   Pointer to the list of items.
6346  * @param[in] actions
6347  *   Pointer to the list of actions.
6348  * @param[out] error
6349  *   Pointer to the error structure.
6350  *
6351  * @return
6352  *   Pointer to mlx5_flow object on success,
6353  *   otherwise NULL and rte_errno is set.
6354  */
6355 static struct mlx5_flow *
6356 flow_dv_prepare(struct rte_eth_dev *dev,
6357                 const struct rte_flow_attr *attr __rte_unused,
6358                 const struct rte_flow_item items[] __rte_unused,
6359                 const struct rte_flow_action actions[] __rte_unused,
6360                 struct rte_flow_error *error)
6361 {
6362         uint32_t handle_idx = 0;
6363         struct mlx5_flow *dev_flow;
6364         struct mlx5_flow_handle *dev_handle;
6365         struct mlx5_priv *priv = dev->data->dev_private;
6366         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6367
6368         MLX5_ASSERT(wks);
6369         /* In case of corrupting the memory. */
6370         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6371                 rte_flow_error_set(error, ENOSPC,
6372                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6373                                    "not free temporary device flow");
6374                 return NULL;
6375         }
6376         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6377                                    &handle_idx);
6378         if (!dev_handle) {
6379                 rte_flow_error_set(error, ENOMEM,
6380                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6381                                    "not enough memory to create flow handle");
6382                 return NULL;
6383         }
6384         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6385         dev_flow = &wks->flows[wks->flow_idx++];
6386         memset(dev_flow, 0, sizeof(*dev_flow));
6387         dev_flow->handle = dev_handle;
6388         dev_flow->handle_idx = handle_idx;
6389         /*
6390          * In some old rdma-core releases, before continuing, a check of the
6391          * length of matching parameter will be done at first. It needs to use
6392          * the length without misc4 param. If the flow has misc4 support, then
6393          * the length needs to be adjusted accordingly. Each param member is
6394          * aligned with a 64B boundary naturally.
6395          */
6396         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6397                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6398         dev_flow->ingress = attr->ingress;
6399         dev_flow->dv.transfer = attr->transfer;
6400         return dev_flow;
6401 }
6402
6403 #ifdef RTE_LIBRTE_MLX5_DEBUG
6404 /**
6405  * Sanity check for match mask and value. Similar to check_valid_spec() in
6406  * kernel driver. If unmasked bit is present in value, it returns failure.
6407  *
6408  * @param match_mask
6409  *   pointer to match mask buffer.
6410  * @param match_value
6411  *   pointer to match value buffer.
6412  *
6413  * @return
6414  *   0 if valid, -EINVAL otherwise.
6415  */
6416 static int
6417 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6418 {
6419         uint8_t *m = match_mask;
6420         uint8_t *v = match_value;
6421         unsigned int i;
6422
6423         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6424                 if (v[i] & ~m[i]) {
6425                         DRV_LOG(ERR,
6426                                 "match_value differs from match_criteria"
6427                                 " %p[%u] != %p[%u]",
6428                                 match_value, i, match_mask, i);
6429                         return -EINVAL;
6430                 }
6431         }
6432         return 0;
6433 }
6434 #endif
6435
6436 /**
6437  * Add match of ip_version.
6438  *
6439  * @param[in] group
6440  *   Flow group.
6441  * @param[in] headers_v
6442  *   Values header pointer.
6443  * @param[in] headers_m
6444  *   Masks header pointer.
6445  * @param[in] ip_version
6446  *   The IP version to set.
6447  */
6448 static inline void
6449 flow_dv_set_match_ip_version(uint32_t group,
6450                              void *headers_v,
6451                              void *headers_m,
6452                              uint8_t ip_version)
6453 {
6454         if (group == 0)
6455                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6456         else
6457                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6458                          ip_version);
6459         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6460         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6461         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6462 }
6463
6464 /**
6465  * Add Ethernet item to matcher and to the value.
6466  *
6467  * @param[in, out] matcher
6468  *   Flow matcher.
6469  * @param[in, out] key
6470  *   Flow matcher value.
6471  * @param[in] item
6472  *   Flow pattern to translate.
6473  * @param[in] inner
6474  *   Item is inner pattern.
6475  */
6476 static void
6477 flow_dv_translate_item_eth(void *matcher, void *key,
6478                            const struct rte_flow_item *item, int inner,
6479                            uint32_t group)
6480 {
6481         const struct rte_flow_item_eth *eth_m = item->mask;
6482         const struct rte_flow_item_eth *eth_v = item->spec;
6483         const struct rte_flow_item_eth nic_mask = {
6484                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6485                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6486                 .type = RTE_BE16(0xffff),
6487                 .has_vlan = 0,
6488         };
6489         void *hdrs_m;
6490         void *hdrs_v;
6491         char *l24_v;
6492         unsigned int i;
6493
6494         if (!eth_v)
6495                 return;
6496         if (!eth_m)
6497                 eth_m = &nic_mask;
6498         if (inner) {
6499                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6500                                          inner_headers);
6501                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6502         } else {
6503                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6504                                          outer_headers);
6505                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6506         }
6507         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6508                &eth_m->dst, sizeof(eth_m->dst));
6509         /* The value must be in the range of the mask. */
6510         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6511         for (i = 0; i < sizeof(eth_m->dst); ++i)
6512                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6513         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6514                &eth_m->src, sizeof(eth_m->src));
6515         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6516         /* The value must be in the range of the mask. */
6517         for (i = 0; i < sizeof(eth_m->dst); ++i)
6518                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6519         /*
6520          * HW supports match on one Ethertype, the Ethertype following the last
6521          * VLAN tag of the packet (see PRM).
6522          * Set match on ethertype only if ETH header is not followed by VLAN.
6523          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6524          * ethertype, and use ip_version field instead.
6525          * eCPRI over Ether layer will use type value 0xAEFE.
6526          */
6527         if (eth_m->type == 0xFFFF) {
6528                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6529                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6530                 switch (eth_v->type) {
6531                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6532                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6533                         return;
6534                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6535                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6536                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6537                         return;
6538                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6539                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6540                         return;
6541                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6542                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6543                         return;
6544                 default:
6545                         break;
6546                 }
6547         }
6548         if (eth_m->has_vlan) {
6549                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6550                 if (eth_v->has_vlan) {
6551                         /*
6552                          * Here, when also has_more_vlan field in VLAN item is
6553                          * not set, only single-tagged packets will be matched.
6554                          */
6555                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6556                         return;
6557                 }
6558         }
6559         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6560                  rte_be_to_cpu_16(eth_m->type));
6561         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6562         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6563 }
6564
6565 /**
6566  * Add VLAN item to matcher and to the value.
6567  *
6568  * @param[in, out] dev_flow
6569  *   Flow descriptor.
6570  * @param[in, out] matcher
6571  *   Flow matcher.
6572  * @param[in, out] key
6573  *   Flow matcher value.
6574  * @param[in] item
6575  *   Flow pattern to translate.
6576  * @param[in] inner
6577  *   Item is inner pattern.
6578  */
6579 static void
6580 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6581                             void *matcher, void *key,
6582                             const struct rte_flow_item *item,
6583                             int inner, uint32_t group)
6584 {
6585         const struct rte_flow_item_vlan *vlan_m = item->mask;
6586         const struct rte_flow_item_vlan *vlan_v = item->spec;
6587         void *hdrs_m;
6588         void *hdrs_v;
6589         uint16_t tci_m;
6590         uint16_t tci_v;
6591
6592         if (inner) {
6593                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6594                                          inner_headers);
6595                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6596         } else {
6597                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6598                                          outer_headers);
6599                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6600                 /*
6601                  * This is workaround, masks are not supported,
6602                  * and pre-validated.
6603                  */
6604                 if (vlan_v)
6605                         dev_flow->handle->vf_vlan.tag =
6606                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6607         }
6608         /*
6609          * When VLAN item exists in flow, mark packet as tagged,
6610          * even if TCI is not specified.
6611          */
6612         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6613                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6614                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6615         }
6616         if (!vlan_v)
6617                 return;
6618         if (!vlan_m)
6619                 vlan_m = &rte_flow_item_vlan_mask;
6620         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6621         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6622         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6623         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6624         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6625         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6626         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6627         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6628         /*
6629          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6630          * ethertype, and use ip_version field instead.
6631          */
6632         if (vlan_m->inner_type == 0xFFFF) {
6633                 switch (vlan_v->inner_type) {
6634                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6635                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6636                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6637                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6638                         return;
6639                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6640                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6641                         return;
6642                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6643                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6644                         return;
6645                 default:
6646                         break;
6647                 }
6648         }
6649         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6650                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6651                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6652                 /* Only one vlan_tag bit can be set. */
6653                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6654                 return;
6655         }
6656         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6657                  rte_be_to_cpu_16(vlan_m->inner_type));
6658         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6659                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6660 }
6661
6662 /**
6663  * Add IPV4 item to matcher and to the value.
6664  *
6665  * @param[in, out] matcher
6666  *   Flow matcher.
6667  * @param[in, out] key
6668  *   Flow matcher value.
6669  * @param[in] item
6670  *   Flow pattern to translate.
6671  * @param[in] inner
6672  *   Item is inner pattern.
6673  * @param[in] group
6674  *   The group to insert the rule.
6675  */
6676 static void
6677 flow_dv_translate_item_ipv4(void *matcher, void *key,
6678                             const struct rte_flow_item *item,
6679                             int inner, uint32_t group)
6680 {
6681         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6682         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6683         const struct rte_flow_item_ipv4 nic_mask = {
6684                 .hdr = {
6685                         .src_addr = RTE_BE32(0xffffffff),
6686                         .dst_addr = RTE_BE32(0xffffffff),
6687                         .type_of_service = 0xff,
6688                         .next_proto_id = 0xff,
6689                         .time_to_live = 0xff,
6690                 },
6691         };
6692         void *headers_m;
6693         void *headers_v;
6694         char *l24_m;
6695         char *l24_v;
6696         uint8_t tos;
6697
6698         if (inner) {
6699                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6700                                          inner_headers);
6701                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6702         } else {
6703                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6704                                          outer_headers);
6705                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6706         }
6707         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6708         if (!ipv4_v)
6709                 return;
6710         if (!ipv4_m)
6711                 ipv4_m = &nic_mask;
6712         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6713                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6714         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6715                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6716         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6717         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6718         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6719                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6720         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6721                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6722         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6723         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6724         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6725         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6726                  ipv4_m->hdr.type_of_service);
6727         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6728         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6729                  ipv4_m->hdr.type_of_service >> 2);
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6731         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6732                  ipv4_m->hdr.next_proto_id);
6733         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6734                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6735         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6736                  ipv4_m->hdr.time_to_live);
6737         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6738                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6739         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6740                  !!(ipv4_m->hdr.fragment_offset));
6741         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6742                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6743 }
6744
6745 /**
6746  * Add IPV6 item to matcher and to the value.
6747  *
6748  * @param[in, out] matcher
6749  *   Flow matcher.
6750  * @param[in, out] key
6751  *   Flow matcher value.
6752  * @param[in] item
6753  *   Flow pattern to translate.
6754  * @param[in] inner
6755  *   Item is inner pattern.
6756  * @param[in] group
6757  *   The group to insert the rule.
6758  */
6759 static void
6760 flow_dv_translate_item_ipv6(void *matcher, void *key,
6761                             const struct rte_flow_item *item,
6762                             int inner, uint32_t group)
6763 {
6764         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6765         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6766         const struct rte_flow_item_ipv6 nic_mask = {
6767                 .hdr = {
6768                         .src_addr =
6769                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6770                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6771                         .dst_addr =
6772                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6773                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6774                         .vtc_flow = RTE_BE32(0xffffffff),
6775                         .proto = 0xff,
6776                         .hop_limits = 0xff,
6777                 },
6778         };
6779         void *headers_m;
6780         void *headers_v;
6781         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6782         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6783         char *l24_m;
6784         char *l24_v;
6785         uint32_t vtc_m;
6786         uint32_t vtc_v;
6787         int i;
6788         int size;
6789
6790         if (inner) {
6791                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6792                                          inner_headers);
6793                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6794         } else {
6795                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6796                                          outer_headers);
6797                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6798         }
6799         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6800         if (!ipv6_v)
6801                 return;
6802         if (!ipv6_m)
6803                 ipv6_m = &nic_mask;
6804         size = sizeof(ipv6_m->hdr.dst_addr);
6805         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6806                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6807         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6808                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6809         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6810         for (i = 0; i < size; ++i)
6811                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6812         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6813                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6814         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6815                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6816         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6817         for (i = 0; i < size; ++i)
6818                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6819         /* TOS. */
6820         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6821         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6822         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6823         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6824         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6825         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6826         /* Label. */
6827         if (inner) {
6828                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6829                          vtc_m);
6830                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6831                          vtc_v);
6832         } else {
6833                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6834                          vtc_m);
6835                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6836                          vtc_v);
6837         }
6838         /* Protocol. */
6839         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6840                  ipv6_m->hdr.proto);
6841         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6842                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6843         /* Hop limit. */
6844         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6845                  ipv6_m->hdr.hop_limits);
6846         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6847                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6848         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6849                  !!(ipv6_m->has_frag_ext));
6850         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6851                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6852 }
6853
6854 /**
6855  * Add IPV6 fragment extension item to matcher and to the value.
6856  *
6857  * @param[in, out] matcher
6858  *   Flow matcher.
6859  * @param[in, out] key
6860  *   Flow matcher value.
6861  * @param[in] item
6862  *   Flow pattern to translate.
6863  * @param[in] inner
6864  *   Item is inner pattern.
6865  */
6866 static void
6867 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6868                                      const struct rte_flow_item *item,
6869                                      int inner)
6870 {
6871         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6872         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6873         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6874                 .hdr = {
6875                         .next_header = 0xff,
6876                         .frag_data = RTE_BE16(0xffff),
6877                 },
6878         };
6879         void *headers_m;
6880         void *headers_v;
6881
6882         if (inner) {
6883                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6884                                          inner_headers);
6885                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6886         } else {
6887                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6888                                          outer_headers);
6889                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6890         }
6891         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6892         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6893         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6894         if (!ipv6_frag_ext_v)
6895                 return;
6896         if (!ipv6_frag_ext_m)
6897                 ipv6_frag_ext_m = &nic_mask;
6898         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6899                  ipv6_frag_ext_m->hdr.next_header);
6900         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6901                  ipv6_frag_ext_v->hdr.next_header &
6902                  ipv6_frag_ext_m->hdr.next_header);
6903 }
6904
6905 /**
6906  * Add TCP item to matcher and to the value.
6907  *
6908  * @param[in, out] matcher
6909  *   Flow matcher.
6910  * @param[in, out] key
6911  *   Flow matcher value.
6912  * @param[in] item
6913  *   Flow pattern to translate.
6914  * @param[in] inner
6915  *   Item is inner pattern.
6916  */
6917 static void
6918 flow_dv_translate_item_tcp(void *matcher, void *key,
6919                            const struct rte_flow_item *item,
6920                            int inner)
6921 {
6922         const struct rte_flow_item_tcp *tcp_m = item->mask;
6923         const struct rte_flow_item_tcp *tcp_v = item->spec;
6924         void *headers_m;
6925         void *headers_v;
6926
6927         if (inner) {
6928                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6929                                          inner_headers);
6930                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6931         } else {
6932                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6933                                          outer_headers);
6934                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6935         }
6936         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6937         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6938         if (!tcp_v)
6939                 return;
6940         if (!tcp_m)
6941                 tcp_m = &rte_flow_item_tcp_mask;
6942         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6943                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6944         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6945                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6946         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6947                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6948         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6949                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6950         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6951                  tcp_m->hdr.tcp_flags);
6952         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6953                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6954 }
6955
6956 /**
6957  * Add UDP item to matcher and to the value.
6958  *
6959  * @param[in, out] matcher
6960  *   Flow matcher.
6961  * @param[in, out] key
6962  *   Flow matcher value.
6963  * @param[in] item
6964  *   Flow pattern to translate.
6965  * @param[in] inner
6966  *   Item is inner pattern.
6967  */
6968 static void
6969 flow_dv_translate_item_udp(void *matcher, void *key,
6970                            const struct rte_flow_item *item,
6971                            int inner)
6972 {
6973         const struct rte_flow_item_udp *udp_m = item->mask;
6974         const struct rte_flow_item_udp *udp_v = item->spec;
6975         void *headers_m;
6976         void *headers_v;
6977
6978         if (inner) {
6979                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6980                                          inner_headers);
6981                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6982         } else {
6983                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6984                                          outer_headers);
6985                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6986         }
6987         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6988         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6989         if (!udp_v)
6990                 return;
6991         if (!udp_m)
6992                 udp_m = &rte_flow_item_udp_mask;
6993         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6994                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6995         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6996                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6997         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6998                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6999         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7000                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7001 }
7002
7003 /**
7004  * Add GRE optional Key item to matcher and to the value.
7005  *
7006  * @param[in, out] matcher
7007  *   Flow matcher.
7008  * @param[in, out] key
7009  *   Flow matcher value.
7010  * @param[in] item
7011  *   Flow pattern to translate.
7012  * @param[in] inner
7013  *   Item is inner pattern.
7014  */
7015 static void
7016 flow_dv_translate_item_gre_key(void *matcher, void *key,
7017                                    const struct rte_flow_item *item)
7018 {
7019         const rte_be32_t *key_m = item->mask;
7020         const rte_be32_t *key_v = item->spec;
7021         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7022         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7023         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7024
7025         /* GRE K bit must be on and should already be validated */
7026         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7027         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7028         if (!key_v)
7029                 return;
7030         if (!key_m)
7031                 key_m = &gre_key_default_mask;
7032         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7033                  rte_be_to_cpu_32(*key_m) >> 8);
7034         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7035                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7036         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7037                  rte_be_to_cpu_32(*key_m) & 0xFF);
7038         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7039                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7040 }
7041
7042 /**
7043  * Add GRE item to matcher and to the value.
7044  *
7045  * @param[in, out] matcher
7046  *   Flow matcher.
7047  * @param[in, out] key
7048  *   Flow matcher value.
7049  * @param[in] item
7050  *   Flow pattern to translate.
7051  * @param[in] inner
7052  *   Item is inner pattern.
7053  */
7054 static void
7055 flow_dv_translate_item_gre(void *matcher, void *key,
7056                            const struct rte_flow_item *item,
7057                            int inner)
7058 {
7059         const struct rte_flow_item_gre *gre_m = item->mask;
7060         const struct rte_flow_item_gre *gre_v = item->spec;
7061         void *headers_m;
7062         void *headers_v;
7063         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7064         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7065         struct {
7066                 union {
7067                         __extension__
7068                         struct {
7069                                 uint16_t version:3;
7070                                 uint16_t rsvd0:9;
7071                                 uint16_t s_present:1;
7072                                 uint16_t k_present:1;
7073                                 uint16_t rsvd_bit1:1;
7074                                 uint16_t c_present:1;
7075                         };
7076                         uint16_t value;
7077                 };
7078         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7079
7080         if (inner) {
7081                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7082                                          inner_headers);
7083                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7084         } else {
7085                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7086                                          outer_headers);
7087                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7088         }
7089         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7090         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7091         if (!gre_v)
7092                 return;
7093         if (!gre_m)
7094                 gre_m = &rte_flow_item_gre_mask;
7095         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7096                  rte_be_to_cpu_16(gre_m->protocol));
7097         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7098                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7099         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7100         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7101         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7102                  gre_crks_rsvd0_ver_m.c_present);
7103         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7104                  gre_crks_rsvd0_ver_v.c_present &
7105                  gre_crks_rsvd0_ver_m.c_present);
7106         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7107                  gre_crks_rsvd0_ver_m.k_present);
7108         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7109                  gre_crks_rsvd0_ver_v.k_present &
7110                  gre_crks_rsvd0_ver_m.k_present);
7111         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7112                  gre_crks_rsvd0_ver_m.s_present);
7113         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7114                  gre_crks_rsvd0_ver_v.s_present &
7115                  gre_crks_rsvd0_ver_m.s_present);
7116 }
7117
7118 /**
7119  * Add NVGRE item to matcher and to the value.
7120  *
7121  * @param[in, out] matcher
7122  *   Flow matcher.
7123  * @param[in, out] key
7124  *   Flow matcher value.
7125  * @param[in] item
7126  *   Flow pattern to translate.
7127  * @param[in] inner
7128  *   Item is inner pattern.
7129  */
7130 static void
7131 flow_dv_translate_item_nvgre(void *matcher, void *key,
7132                              const struct rte_flow_item *item,
7133                              int inner)
7134 {
7135         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7136         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7137         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7138         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7139         const char *tni_flow_id_m;
7140         const char *tni_flow_id_v;
7141         char *gre_key_m;
7142         char *gre_key_v;
7143         int size;
7144         int i;
7145
7146         /* For NVGRE, GRE header fields must be set with defined values. */
7147         const struct rte_flow_item_gre gre_spec = {
7148                 .c_rsvd0_ver = RTE_BE16(0x2000),
7149                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7150         };
7151         const struct rte_flow_item_gre gre_mask = {
7152                 .c_rsvd0_ver = RTE_BE16(0xB000),
7153                 .protocol = RTE_BE16(UINT16_MAX),
7154         };
7155         const struct rte_flow_item gre_item = {
7156                 .spec = &gre_spec,
7157                 .mask = &gre_mask,
7158                 .last = NULL,
7159         };
7160         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7161         if (!nvgre_v)
7162                 return;
7163         if (!nvgre_m)
7164                 nvgre_m = &rte_flow_item_nvgre_mask;
7165         tni_flow_id_m = (const char *)nvgre_m->tni;
7166         tni_flow_id_v = (const char *)nvgre_v->tni;
7167         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7168         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7169         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7170         memcpy(gre_key_m, tni_flow_id_m, size);
7171         for (i = 0; i < size; ++i)
7172                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7173 }
7174
7175 /**
7176  * Add VXLAN item to matcher and to the value.
7177  *
7178  * @param[in, out] matcher
7179  *   Flow matcher.
7180  * @param[in, out] key
7181  *   Flow matcher value.
7182  * @param[in] item
7183  *   Flow pattern to translate.
7184  * @param[in] inner
7185  *   Item is inner pattern.
7186  */
7187 static void
7188 flow_dv_translate_item_vxlan(void *matcher, void *key,
7189                              const struct rte_flow_item *item,
7190                              int inner)
7191 {
7192         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7193         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7194         void *headers_m;
7195         void *headers_v;
7196         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7197         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7198         char *vni_m;
7199         char *vni_v;
7200         uint16_t dport;
7201         int size;
7202         int i;
7203
7204         if (inner) {
7205                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7206                                          inner_headers);
7207                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7208         } else {
7209                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7210                                          outer_headers);
7211                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7212         }
7213         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7214                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7215         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7216                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7217                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7218         }
7219         if (!vxlan_v)
7220                 return;
7221         if (!vxlan_m)
7222                 vxlan_m = &rte_flow_item_vxlan_mask;
7223         size = sizeof(vxlan_m->vni);
7224         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7225         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7226         memcpy(vni_m, vxlan_m->vni, size);
7227         for (i = 0; i < size; ++i)
7228                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7229 }
7230
7231 /**
7232  * Add VXLAN-GPE item to matcher and to the value.
7233  *
7234  * @param[in, out] matcher
7235  *   Flow matcher.
7236  * @param[in, out] key
7237  *   Flow matcher value.
7238  * @param[in] item
7239  *   Flow pattern to translate.
7240  * @param[in] inner
7241  *   Item is inner pattern.
7242  */
7243
7244 static void
7245 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7246                                  const struct rte_flow_item *item, int inner)
7247 {
7248         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7249         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7250         void *headers_m;
7251         void *headers_v;
7252         void *misc_m =
7253                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7254         void *misc_v =
7255                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7256         char *vni_m;
7257         char *vni_v;
7258         uint16_t dport;
7259         int size;
7260         int i;
7261         uint8_t flags_m = 0xff;
7262         uint8_t flags_v = 0xc;
7263
7264         if (inner) {
7265                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7266                                          inner_headers);
7267                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7268         } else {
7269                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7270                                          outer_headers);
7271                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7272         }
7273         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7274                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7275         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7276                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7277                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7278         }
7279         if (!vxlan_v)
7280                 return;
7281         if (!vxlan_m)
7282                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7283         size = sizeof(vxlan_m->vni);
7284         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7285         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7286         memcpy(vni_m, vxlan_m->vni, size);
7287         for (i = 0; i < size; ++i)
7288                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7289         if (vxlan_m->flags) {
7290                 flags_m = vxlan_m->flags;
7291                 flags_v = vxlan_v->flags;
7292         }
7293         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7294         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7295         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7296                  vxlan_m->protocol);
7297         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7298                  vxlan_v->protocol);
7299 }
7300
7301 /**
7302  * Add Geneve item to matcher and to the value.
7303  *
7304  * @param[in, out] matcher
7305  *   Flow matcher.
7306  * @param[in, out] key
7307  *   Flow matcher value.
7308  * @param[in] item
7309  *   Flow pattern to translate.
7310  * @param[in] inner
7311  *   Item is inner pattern.
7312  */
7313
7314 static void
7315 flow_dv_translate_item_geneve(void *matcher, void *key,
7316                               const struct rte_flow_item *item, int inner)
7317 {
7318         const struct rte_flow_item_geneve *geneve_m = item->mask;
7319         const struct rte_flow_item_geneve *geneve_v = item->spec;
7320         void *headers_m;
7321         void *headers_v;
7322         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7323         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7324         uint16_t dport;
7325         uint16_t gbhdr_m;
7326         uint16_t gbhdr_v;
7327         char *vni_m;
7328         char *vni_v;
7329         size_t size, i;
7330
7331         if (inner) {
7332                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7333                                          inner_headers);
7334                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7335         } else {
7336                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7337                                          outer_headers);
7338                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7339         }
7340         dport = MLX5_UDP_PORT_GENEVE;
7341         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7342                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7343                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7344         }
7345         if (!geneve_v)
7346                 return;
7347         if (!geneve_m)
7348                 geneve_m = &rte_flow_item_geneve_mask;
7349         size = sizeof(geneve_m->vni);
7350         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7351         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7352         memcpy(vni_m, geneve_m->vni, size);
7353         for (i = 0; i < size; ++i)
7354                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7355         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7356                  rte_be_to_cpu_16(geneve_m->protocol));
7357         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7358                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7359         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7360         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7361         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7362                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7363         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7364                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7365         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7366                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7367         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7368                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7369                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7370 }
7371
7372 /**
7373  * Create Geneve TLV option resource.
7374  *
7375  * @param dev[in, out]
7376  *   Pointer to rte_eth_dev structure.
7377  * @param[in, out] tag_be24
7378  *   Tag value in big endian then R-shift 8.
7379  * @parm[in, out] dev_flow
7380  *   Pointer to the dev_flow.
7381  * @param[out] error
7382  *   pointer to error structure.
7383  *
7384  * @return
7385  *   0 on success otherwise -errno and errno is set.
7386  */
7387
7388 int
7389 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7390                                              const struct rte_flow_item *item,
7391                                              struct rte_flow_error *error)
7392 {
7393         struct mlx5_priv *priv = dev->data->dev_private;
7394         struct mlx5_dev_ctx_shared *sh = priv->sh;
7395         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7396                         sh->geneve_tlv_option_resource;
7397         struct mlx5_devx_obj *obj;
7398         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7399         int ret = 0;
7400
7401         if (!geneve_opt_v)
7402                 return -1;
7403         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7404         if (geneve_opt_resource != NULL) {
7405                 if (geneve_opt_resource->option_class ==
7406                         geneve_opt_v->option_class &&
7407                         geneve_opt_resource->option_type ==
7408                         geneve_opt_v->option_type &&
7409                         geneve_opt_resource->length ==
7410                         geneve_opt_v->option_len) {
7411                         /* We already have GENVE TLV option obj allocated. */
7412                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7413                                            __ATOMIC_RELAXED);
7414                 } else {
7415                         ret = rte_flow_error_set(error, ENOMEM,
7416                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7417                                 "Only one GENEVE TLV option supported");
7418                         goto exit;
7419                 }
7420         } else {
7421                 /* Create a GENEVE TLV object and resource. */
7422                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7423                                 geneve_opt_v->option_class,
7424                                 geneve_opt_v->option_type,
7425                                 geneve_opt_v->option_len);
7426                 if (!obj) {
7427                         ret = rte_flow_error_set(error, ENODATA,
7428                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7429                                 "Failed to create GENEVE TLV Devx object");
7430                         goto exit;
7431                 }
7432                 sh->geneve_tlv_option_resource =
7433                                 mlx5_malloc(MLX5_MEM_ZERO,
7434                                                 sizeof(*geneve_opt_resource),
7435                                                 0, SOCKET_ID_ANY);
7436                 if (!sh->geneve_tlv_option_resource) {
7437                         claim_zero(mlx5_devx_cmd_destroy(obj));
7438                         ret = rte_flow_error_set(error, ENOMEM,
7439                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7440                                 "GENEVE TLV object memory allocation failed");
7441                         goto exit;
7442                 }
7443                 geneve_opt_resource = sh->geneve_tlv_option_resource;
7444                 geneve_opt_resource->obj = obj;
7445                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7446                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7447                 geneve_opt_resource->length = geneve_opt_v->option_len;
7448                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7449                                 __ATOMIC_RELAXED);
7450         }
7451 exit:
7452         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7453         return ret;
7454 }
7455
7456 /**
7457  * Add Geneve TLV option item to matcher.
7458  *
7459  * @param[in, out] dev
7460  *   Pointer to rte_eth_dev structure.
7461  * @param[in, out] matcher
7462  *   Flow matcher.
7463  * @param[in, out] key
7464  *   Flow matcher value.
7465  * @param[in] item
7466  *   Flow pattern to translate.
7467  * @param[out] error
7468  *   Pointer to error structure.
7469  */
7470 static int
7471 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
7472                                   void *key, const struct rte_flow_item *item,
7473                                   struct rte_flow_error *error)
7474 {
7475         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
7476         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7477         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7478         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7479         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7480                         misc_parameters_3);
7481         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7482         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
7483         int ret = 0;
7484
7485         if (!geneve_opt_v)
7486                 return -1;
7487         if (!geneve_opt_m)
7488                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
7489         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
7490                                                            error);
7491         if (ret) {
7492                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
7493                 return ret;
7494         }
7495         /*
7496          * Set the option length in GENEVE header if not requested.
7497          * The GENEVE TLV option length is expressed by the option length field
7498          * in the GENEVE header.
7499          * If the option length was not requested but the GENEVE TLV option item
7500          * is present we set the option length field implicitly.
7501          */
7502         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
7503                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7504                          MLX5_GENEVE_OPTLEN_MASK);
7505                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7506                          geneve_opt_v->option_len + 1);
7507         }
7508         /* Set the data. */
7509         if (geneve_opt_v->data) {
7510                 memcpy(&opt_data_key, geneve_opt_v->data,
7511                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7512                                 sizeof(opt_data_key)));
7513                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7514                                 sizeof(opt_data_key));
7515                 memcpy(&opt_data_mask, geneve_opt_m->data,
7516                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7517                                 sizeof(opt_data_mask)));
7518                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7519                                 sizeof(opt_data_mask));
7520                 MLX5_SET(fte_match_set_misc3, misc3_m,
7521                                 geneve_tlv_option_0_data,
7522                                 rte_be_to_cpu_32(opt_data_mask));
7523                 MLX5_SET(fte_match_set_misc3, misc3_v,
7524                                 geneve_tlv_option_0_data,
7525                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
7526         }
7527         return ret;
7528 }
7529
7530 /**
7531  * Add MPLS item to matcher and to the value.
7532  *
7533  * @param[in, out] matcher
7534  *   Flow matcher.
7535  * @param[in, out] key
7536  *   Flow matcher value.
7537  * @param[in] item
7538  *   Flow pattern to translate.
7539  * @param[in] prev_layer
7540  *   The protocol layer indicated in previous item.
7541  * @param[in] inner
7542  *   Item is inner pattern.
7543  */
7544 static void
7545 flow_dv_translate_item_mpls(void *matcher, void *key,
7546                             const struct rte_flow_item *item,
7547                             uint64_t prev_layer,
7548                             int inner)
7549 {
7550         const uint32_t *in_mpls_m = item->mask;
7551         const uint32_t *in_mpls_v = item->spec;
7552         uint32_t *out_mpls_m = 0;
7553         uint32_t *out_mpls_v = 0;
7554         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7555         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7556         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7557                                      misc_parameters_2);
7558         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7559         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7560         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7561
7562         switch (prev_layer) {
7563         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7564                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7565                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7566                          MLX5_UDP_PORT_MPLS);
7567                 break;
7568         case MLX5_FLOW_LAYER_GRE:
7569                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7570                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7571                          RTE_ETHER_TYPE_MPLS);
7572                 break;
7573         default:
7574                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7575                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7576                          IPPROTO_MPLS);
7577                 break;
7578         }
7579         if (!in_mpls_v)
7580                 return;
7581         if (!in_mpls_m)
7582                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7583         switch (prev_layer) {
7584         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7585                 out_mpls_m =
7586                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7587                                                  outer_first_mpls_over_udp);
7588                 out_mpls_v =
7589                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7590                                                  outer_first_mpls_over_udp);
7591                 break;
7592         case MLX5_FLOW_LAYER_GRE:
7593                 out_mpls_m =
7594                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7595                                                  outer_first_mpls_over_gre);
7596                 out_mpls_v =
7597                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7598                                                  outer_first_mpls_over_gre);
7599                 break;
7600         default:
7601                 /* Inner MPLS not over GRE is not supported. */
7602                 if (!inner) {
7603                         out_mpls_m =
7604                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7605                                                          misc2_m,
7606                                                          outer_first_mpls);
7607                         out_mpls_v =
7608                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7609                                                          misc2_v,
7610                                                          outer_first_mpls);
7611                 }
7612                 break;
7613         }
7614         if (out_mpls_m && out_mpls_v) {
7615                 *out_mpls_m = *in_mpls_m;
7616                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7617         }
7618 }
7619
7620 /**
7621  * Add metadata register item to matcher
7622  *
7623  * @param[in, out] matcher
7624  *   Flow matcher.
7625  * @param[in, out] key
7626  *   Flow matcher value.
7627  * @param[in] reg_type
7628  *   Type of device metadata register
7629  * @param[in] value
7630  *   Register value
7631  * @param[in] mask
7632  *   Register mask
7633  */
7634 static void
7635 flow_dv_match_meta_reg(void *matcher, void *key,
7636                        enum modify_reg reg_type,
7637                        uint32_t data, uint32_t mask)
7638 {
7639         void *misc2_m =
7640                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7641         void *misc2_v =
7642                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7643         uint32_t temp;
7644
7645         data &= mask;
7646         switch (reg_type) {
7647         case REG_A:
7648                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7649                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7650                 break;
7651         case REG_B:
7652                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7653                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7654                 break;
7655         case REG_C_0:
7656                 /*
7657                  * The metadata register C0 field might be divided into
7658                  * source vport index and META item value, we should set
7659                  * this field according to specified mask, not as whole one.
7660                  */
7661                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7662                 temp |= mask;
7663                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7664                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7665                 temp &= ~mask;
7666                 temp |= data;
7667                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7668                 break;
7669         case REG_C_1:
7670                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7671                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7672                 break;
7673         case REG_C_2:
7674                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7675                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7676                 break;
7677         case REG_C_3:
7678                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7679                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7680                 break;
7681         case REG_C_4:
7682                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7683                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7684                 break;
7685         case REG_C_5:
7686                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7687                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7688                 break;
7689         case REG_C_6:
7690                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7691                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7692                 break;
7693         case REG_C_7:
7694                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7695                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7696                 break;
7697         default:
7698                 MLX5_ASSERT(false);
7699                 break;
7700         }
7701 }
7702
7703 /**
7704  * Add MARK item to matcher
7705  *
7706  * @param[in] dev
7707  *   The device to configure through.
7708  * @param[in, out] matcher
7709  *   Flow matcher.
7710  * @param[in, out] key
7711  *   Flow matcher value.
7712  * @param[in] item
7713  *   Flow pattern to translate.
7714  */
7715 static void
7716 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7717                             void *matcher, void *key,
7718                             const struct rte_flow_item *item)
7719 {
7720         struct mlx5_priv *priv = dev->data->dev_private;
7721         const struct rte_flow_item_mark *mark;
7722         uint32_t value;
7723         uint32_t mask;
7724
7725         mark = item->mask ? (const void *)item->mask :
7726                             &rte_flow_item_mark_mask;
7727         mask = mark->id & priv->sh->dv_mark_mask;
7728         mark = (const void *)item->spec;
7729         MLX5_ASSERT(mark);
7730         value = mark->id & priv->sh->dv_mark_mask & mask;
7731         if (mask) {
7732                 enum modify_reg reg;
7733
7734                 /* Get the metadata register index for the mark. */
7735                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7736                 MLX5_ASSERT(reg > 0);
7737                 if (reg == REG_C_0) {
7738                         struct mlx5_priv *priv = dev->data->dev_private;
7739                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7740                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7741
7742                         mask &= msk_c0;
7743                         mask <<= shl_c0;
7744                         value <<= shl_c0;
7745                 }
7746                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7747         }
7748 }
7749
7750 /**
7751  * Add META item to matcher
7752  *
7753  * @param[in] dev
7754  *   The devich to configure through.
7755  * @param[in, out] matcher
7756  *   Flow matcher.
7757  * @param[in, out] key
7758  *   Flow matcher value.
7759  * @param[in] attr
7760  *   Attributes of flow that includes this item.
7761  * @param[in] item
7762  *   Flow pattern to translate.
7763  */
7764 static void
7765 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7766                             void *matcher, void *key,
7767                             const struct rte_flow_attr *attr,
7768                             const struct rte_flow_item *item)
7769 {
7770         const struct rte_flow_item_meta *meta_m;
7771         const struct rte_flow_item_meta *meta_v;
7772
7773         meta_m = (const void *)item->mask;
7774         if (!meta_m)
7775                 meta_m = &rte_flow_item_meta_mask;
7776         meta_v = (const void *)item->spec;
7777         if (meta_v) {
7778                 int reg;
7779                 uint32_t value = meta_v->data;
7780                 uint32_t mask = meta_m->data;
7781
7782                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7783                 if (reg < 0)
7784                         return;
7785                 MLX5_ASSERT(reg != REG_NON);
7786                 /*
7787                  * In datapath code there is no endianness
7788                  * coversions for perfromance reasons, all
7789                  * pattern conversions are done in rte_flow.
7790                  */
7791                 value = rte_cpu_to_be_32(value);
7792                 mask = rte_cpu_to_be_32(mask);
7793                 if (reg == REG_C_0) {
7794                         struct mlx5_priv *priv = dev->data->dev_private;
7795                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7796                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7797 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7798                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7799
7800                         value >>= shr_c0;
7801                         mask >>= shr_c0;
7802 #endif
7803                         value <<= shl_c0;
7804                         mask <<= shl_c0;
7805                         MLX5_ASSERT(msk_c0);
7806                         MLX5_ASSERT(!(~msk_c0 & mask));
7807                 }
7808                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7809         }
7810 }
7811
7812 /**
7813  * Add vport metadata Reg C0 item to matcher
7814  *
7815  * @param[in, out] matcher
7816  *   Flow matcher.
7817  * @param[in, out] key
7818  *   Flow matcher value.
7819  * @param[in] reg
7820  *   Flow pattern to translate.
7821  */
7822 static void
7823 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7824                                   uint32_t value, uint32_t mask)
7825 {
7826         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7827 }
7828
7829 /**
7830  * Add tag item to matcher
7831  *
7832  * @param[in] dev
7833  *   The devich to configure through.
7834  * @param[in, out] matcher
7835  *   Flow matcher.
7836  * @param[in, out] key
7837  *   Flow matcher value.
7838  * @param[in] item
7839  *   Flow pattern to translate.
7840  */
7841 static void
7842 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7843                                 void *matcher, void *key,
7844                                 const struct rte_flow_item *item)
7845 {
7846         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7847         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7848         uint32_t mask, value;
7849
7850         MLX5_ASSERT(tag_v);
7851         value = tag_v->data;
7852         mask = tag_m ? tag_m->data : UINT32_MAX;
7853         if (tag_v->id == REG_C_0) {
7854                 struct mlx5_priv *priv = dev->data->dev_private;
7855                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7856                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7857
7858                 mask &= msk_c0;
7859                 mask <<= shl_c0;
7860                 value <<= shl_c0;
7861         }
7862         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7863 }
7864
7865 /**
7866  * Add TAG item to matcher
7867  *
7868  * @param[in] dev
7869  *   The devich to configure through.
7870  * @param[in, out] matcher
7871  *   Flow matcher.
7872  * @param[in, out] key
7873  *   Flow matcher value.
7874  * @param[in] item
7875  *   Flow pattern to translate.
7876  */
7877 static void
7878 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7879                            void *matcher, void *key,
7880                            const struct rte_flow_item *item)
7881 {
7882         const struct rte_flow_item_tag *tag_v = item->spec;
7883         const struct rte_flow_item_tag *tag_m = item->mask;
7884         enum modify_reg reg;
7885
7886         MLX5_ASSERT(tag_v);
7887         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7888         /* Get the metadata register index for the tag. */
7889         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7890         MLX5_ASSERT(reg > 0);
7891         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7892 }
7893
7894 /**
7895  * Add source vport match to the specified matcher.
7896  *
7897  * @param[in, out] matcher
7898  *   Flow matcher.
7899  * @param[in, out] key
7900  *   Flow matcher value.
7901  * @param[in] port
7902  *   Source vport value to match
7903  * @param[in] mask
7904  *   Mask
7905  */
7906 static void
7907 flow_dv_translate_item_source_vport(void *matcher, void *key,
7908                                     int16_t port, uint16_t mask)
7909 {
7910         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7911         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7912
7913         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7914         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7915 }
7916
7917 /**
7918  * Translate port-id item to eswitch match on  port-id.
7919  *
7920  * @param[in] dev
7921  *   The devich to configure through.
7922  * @param[in, out] matcher
7923  *   Flow matcher.
7924  * @param[in, out] key
7925  *   Flow matcher value.
7926  * @param[in] item
7927  *   Flow pattern to translate.
7928  * @param[in]
7929  *   Flow attributes.
7930  *
7931  * @return
7932  *   0 on success, a negative errno value otherwise.
7933  */
7934 static int
7935 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7936                                void *key, const struct rte_flow_item *item,
7937                                const struct rte_flow_attr *attr)
7938 {
7939         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7940         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7941         struct mlx5_priv *priv;
7942         uint16_t mask, id;
7943
7944         mask = pid_m ? pid_m->id : 0xffff;
7945         id = pid_v ? pid_v->id : dev->data->port_id;
7946         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7947         if (!priv)
7948                 return -rte_errno;
7949         /*
7950          * Translate to vport field or to metadata, depending on mode.
7951          * Kernel can use either misc.source_port or half of C0 metadata
7952          * register.
7953          */
7954         if (priv->vport_meta_mask) {
7955                 /*
7956                  * Provide the hint for SW steering library
7957                  * to insert the flow into ingress domain and
7958                  * save the extra vport match.
7959                  */
7960                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7961                     priv->pf_bond < 0 && attr->transfer)
7962                         flow_dv_translate_item_source_vport
7963                                 (matcher, key, priv->vport_id, mask);
7964                 else
7965                         flow_dv_translate_item_meta_vport
7966                                 (matcher, key,
7967                                  priv->vport_meta_tag,
7968                                  priv->vport_meta_mask);
7969         } else {
7970                 flow_dv_translate_item_source_vport(matcher, key,
7971                                                     priv->vport_id, mask);
7972         }
7973         return 0;
7974 }
7975
7976 /**
7977  * Add ICMP6 item to matcher and to the value.
7978  *
7979  * @param[in, out] matcher
7980  *   Flow matcher.
7981  * @param[in, out] key
7982  *   Flow matcher value.
7983  * @param[in] item
7984  *   Flow pattern to translate.
7985  * @param[in] inner
7986  *   Item is inner pattern.
7987  */
7988 static void
7989 flow_dv_translate_item_icmp6(void *matcher, void *key,
7990                               const struct rte_flow_item *item,
7991                               int inner)
7992 {
7993         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7994         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7995         void *headers_m;
7996         void *headers_v;
7997         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7998                                      misc_parameters_3);
7999         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8000         if (inner) {
8001                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8002                                          inner_headers);
8003                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8004         } else {
8005                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8006                                          outer_headers);
8007                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8008         }
8009         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8010         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8011         if (!icmp6_v)
8012                 return;
8013         if (!icmp6_m)
8014                 icmp6_m = &rte_flow_item_icmp6_mask;
8015         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8016         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8017                  icmp6_v->type & icmp6_m->type);
8018         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8019         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8020                  icmp6_v->code & icmp6_m->code);
8021 }
8022
8023 /**
8024  * Add ICMP item to matcher and to the value.
8025  *
8026  * @param[in, out] matcher
8027  *   Flow matcher.
8028  * @param[in, out] key
8029  *   Flow matcher value.
8030  * @param[in] item
8031  *   Flow pattern to translate.
8032  * @param[in] inner
8033  *   Item is inner pattern.
8034  */
8035 static void
8036 flow_dv_translate_item_icmp(void *matcher, void *key,
8037                             const struct rte_flow_item *item,
8038                             int inner)
8039 {
8040         const struct rte_flow_item_icmp *icmp_m = item->mask;
8041         const struct rte_flow_item_icmp *icmp_v = item->spec;
8042         uint32_t icmp_header_data_m = 0;
8043         uint32_t icmp_header_data_v = 0;
8044         void *headers_m;
8045         void *headers_v;
8046         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8047                                      misc_parameters_3);
8048         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8049         if (inner) {
8050                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8051                                          inner_headers);
8052                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8053         } else {
8054                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8055                                          outer_headers);
8056                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8057         }
8058         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8059         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8060         if (!icmp_v)
8061                 return;
8062         if (!icmp_m)
8063                 icmp_m = &rte_flow_item_icmp_mask;
8064         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8065                  icmp_m->hdr.icmp_type);
8066         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8067                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8068         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8069                  icmp_m->hdr.icmp_code);
8070         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8071                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8072         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8073         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8074         if (icmp_header_data_m) {
8075                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8076                 icmp_header_data_v |=
8077                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8078                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8079                          icmp_header_data_m);
8080                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8081                          icmp_header_data_v & icmp_header_data_m);
8082         }
8083 }
8084
8085 /**
8086  * Add GTP item to matcher and to the value.
8087  *
8088  * @param[in, out] matcher
8089  *   Flow matcher.
8090  * @param[in, out] key
8091  *   Flow matcher value.
8092  * @param[in] item
8093  *   Flow pattern to translate.
8094  * @param[in] inner
8095  *   Item is inner pattern.
8096  */
8097 static void
8098 flow_dv_translate_item_gtp(void *matcher, void *key,
8099                            const struct rte_flow_item *item, int inner)
8100 {
8101         const struct rte_flow_item_gtp *gtp_m = item->mask;
8102         const struct rte_flow_item_gtp *gtp_v = item->spec;
8103         void *headers_m;
8104         void *headers_v;
8105         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8106                                      misc_parameters_3);
8107         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8108         uint16_t dport = RTE_GTPU_UDP_PORT;
8109
8110         if (inner) {
8111                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8112                                          inner_headers);
8113                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8114         } else {
8115                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8116                                          outer_headers);
8117                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8118         }
8119         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8120                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8121                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8122         }
8123         if (!gtp_v)
8124                 return;
8125         if (!gtp_m)
8126                 gtp_m = &rte_flow_item_gtp_mask;
8127         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8128                  gtp_m->v_pt_rsv_flags);
8129         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8130                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8131         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8132         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8133                  gtp_v->msg_type & gtp_m->msg_type);
8134         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8135                  rte_be_to_cpu_32(gtp_m->teid));
8136         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8137                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8138 }
8139
8140 /**
8141  * Add GTP PSC item to matcher.
8142  *
8143  * @param[in, out] matcher
8144  *   Flow matcher.
8145  * @param[in, out] key
8146  *   Flow matcher value.
8147  * @param[in] item
8148  *   Flow pattern to translate.
8149  */
8150 static int
8151 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8152                                const struct rte_flow_item *item)
8153 {
8154         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8155         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8156         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8157                         misc_parameters_3);
8158         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8159         union {
8160                 uint32_t w32;
8161                 struct {
8162                         uint16_t seq_num;
8163                         uint8_t npdu_num;
8164                         uint8_t next_ext_header_type;
8165                 };
8166         } dw_2;
8167         uint8_t gtp_flags;
8168
8169         /* Always set E-flag match on one, regardless of GTP item settings. */
8170         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8171         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8172         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8173         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8174         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8175         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8176         /*Set next extension header type. */
8177         dw_2.seq_num = 0;
8178         dw_2.npdu_num = 0;
8179         dw_2.next_ext_header_type = 0xff;
8180         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8181                  rte_cpu_to_be_32(dw_2.w32));
8182         dw_2.seq_num = 0;
8183         dw_2.npdu_num = 0;
8184         dw_2.next_ext_header_type = 0x85;
8185         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8186                  rte_cpu_to_be_32(dw_2.w32));
8187         if (gtp_psc_v) {
8188                 union {
8189                         uint32_t w32;
8190                         struct {
8191                                 uint8_t len;
8192                                 uint8_t type_flags;
8193                                 uint8_t qfi;
8194                                 uint8_t reserved;
8195                         };
8196                 } dw_0;
8197
8198                 /*Set extension header PDU type and Qos. */
8199                 if (!gtp_psc_m)
8200                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8201                 dw_0.w32 = 0;
8202                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8203                 dw_0.qfi = gtp_psc_m->qfi;
8204                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8205                          rte_cpu_to_be_32(dw_0.w32));
8206                 dw_0.w32 = 0;
8207                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8208                                                         gtp_psc_m->pdu_type);
8209                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8210                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8211                          rte_cpu_to_be_32(dw_0.w32));
8212         }
8213         return 0;
8214 }
8215
8216 /**
8217  * Add eCPRI item to matcher and to the value.
8218  *
8219  * @param[in] dev
8220  *   The devich to configure through.
8221  * @param[in, out] matcher
8222  *   Flow matcher.
8223  * @param[in, out] key
8224  *   Flow matcher value.
8225  * @param[in] item
8226  *   Flow pattern to translate.
8227  * @param[in] samples
8228  *   Sample IDs to be used in the matching.
8229  */
8230 static void
8231 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8232                              void *key, const struct rte_flow_item *item)
8233 {
8234         struct mlx5_priv *priv = dev->data->dev_private;
8235         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8236         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8237         struct rte_ecpri_common_hdr common;
8238         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8239                                      misc_parameters_4);
8240         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8241         uint32_t *samples;
8242         void *dw_m;
8243         void *dw_v;
8244
8245         if (!ecpri_v)
8246                 return;
8247         if (!ecpri_m)
8248                 ecpri_m = &rte_flow_item_ecpri_mask;
8249         /*
8250          * Maximal four DW samples are supported in a single matching now.
8251          * Two are used now for a eCPRI matching:
8252          * 1. Type: one byte, mask should be 0x00ff0000 in network order
8253          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8254          *    if any.
8255          */
8256         if (!ecpri_m->hdr.common.u32)
8257                 return;
8258         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8259         /* Need to take the whole DW as the mask to fill the entry. */
8260         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8261                             prog_sample_field_value_0);
8262         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8263                             prog_sample_field_value_0);
8264         /* Already big endian (network order) in the header. */
8265         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8266         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8267         /* Sample#0, used for matching type, offset 0. */
8268         MLX5_SET(fte_match_set_misc4, misc4_m,
8269                  prog_sample_field_id_0, samples[0]);
8270         /* It makes no sense to set the sample ID in the mask field. */
8271         MLX5_SET(fte_match_set_misc4, misc4_v,
8272                  prog_sample_field_id_0, samples[0]);
8273         /*
8274          * Checking if message body part needs to be matched.
8275          * Some wildcard rules only matching type field should be supported.
8276          */
8277         if (ecpri_m->hdr.dummy[0]) {
8278                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8279                 switch (common.type) {
8280                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8281                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8282                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8283                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8284                                             prog_sample_field_value_1);
8285                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8286                                             prog_sample_field_value_1);
8287                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8288                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8289                                             ecpri_m->hdr.dummy[0];
8290                         /* Sample#1, to match message body, offset 4. */
8291                         MLX5_SET(fte_match_set_misc4, misc4_m,
8292                                  prog_sample_field_id_1, samples[1]);
8293                         MLX5_SET(fte_match_set_misc4, misc4_v,
8294                                  prog_sample_field_id_1, samples[1]);
8295                         break;
8296                 default:
8297                         /* Others, do not match any sample ID. */
8298                         break;
8299                 }
8300         }
8301 }
8302
8303 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8304
8305 #define HEADER_IS_ZERO(match_criteria, headers)                              \
8306         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
8307                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8308
8309 /**
8310  * Calculate flow matcher enable bitmap.
8311  *
8312  * @param match_criteria
8313  *   Pointer to flow matcher criteria.
8314  *
8315  * @return
8316  *   Bitmap of enabled fields.
8317  */
8318 static uint8_t
8319 flow_dv_matcher_enable(uint32_t *match_criteria)
8320 {
8321         uint8_t match_criteria_enable;
8322
8323         match_criteria_enable =
8324                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8325                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8326         match_criteria_enable |=
8327                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8328                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8329         match_criteria_enable |=
8330                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8331                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8332         match_criteria_enable |=
8333                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8334                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8335         match_criteria_enable |=
8336                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8337                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8338         match_criteria_enable |=
8339                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8340                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8341         return match_criteria_enable;
8342 }
8343
8344 struct mlx5_hlist_entry *
8345 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8346 {
8347         struct mlx5_dev_ctx_shared *sh = list->ctx;
8348         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8349         struct rte_eth_dev *dev = ctx->dev;
8350         struct mlx5_flow_tbl_data_entry *tbl_data;
8351         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8352         struct rte_flow_error *error = ctx->error;
8353         union mlx5_flow_tbl_key key = { .v64 = key64 };
8354         struct mlx5_flow_tbl_resource *tbl;
8355         void *domain;
8356         uint32_t idx = 0;
8357         int ret;
8358
8359         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8360         if (!tbl_data) {
8361                 rte_flow_error_set(error, ENOMEM,
8362                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8363                                    NULL,
8364                                    "cannot allocate flow table data entry");
8365                 return NULL;
8366         }
8367         tbl_data->idx = idx;
8368         tbl_data->tunnel = tt_prm->tunnel;
8369         tbl_data->group_id = tt_prm->group_id;
8370         tbl_data->external = !!tt_prm->external;
8371         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8372         tbl_data->is_egress = !!key.direction;
8373         tbl_data->is_transfer = !!key.domain;
8374         tbl_data->dummy = !!key.dummy;
8375         tbl_data->table_id = key.table_id;
8376         tbl = &tbl_data->tbl;
8377         if (key.dummy)
8378                 return &tbl_data->entry;
8379         if (key.domain)
8380                 domain = sh->fdb_domain;
8381         else if (key.direction)
8382                 domain = sh->tx_domain;
8383         else
8384                 domain = sh->rx_domain;
8385         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8386         if (ret) {
8387                 rte_flow_error_set(error, ENOMEM,
8388                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8389                                    NULL, "cannot create flow table object");
8390                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8391                 return NULL;
8392         }
8393         if (key.table_id) {
8394                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8395                                         (tbl->obj, &tbl_data->jump.action);
8396                 if (ret) {
8397                         rte_flow_error_set(error, ENOMEM,
8398                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8399                                            NULL,
8400                                            "cannot create flow jump action");
8401                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8402                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8403                         return NULL;
8404                 }
8405         }
8406         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8407               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8408               key.table_id);
8409         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8410                              flow_dv_matcher_create_cb,
8411                              flow_dv_matcher_match_cb,
8412                              flow_dv_matcher_remove_cb);
8413         return &tbl_data->entry;
8414 }
8415
8416 int
8417 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8418                      struct mlx5_hlist_entry *entry, uint64_t key64,
8419                      void *cb_ctx __rte_unused)
8420 {
8421         struct mlx5_flow_tbl_data_entry *tbl_data =
8422                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8423         union mlx5_flow_tbl_key key = { .v64 = key64 };
8424
8425         return tbl_data->table_id != key.table_id ||
8426                tbl_data->dummy != key.dummy ||
8427                tbl_data->is_transfer != key.domain ||
8428                tbl_data->is_egress != key.direction;
8429 }
8430
8431 /**
8432  * Get a flow table.
8433  *
8434  * @param[in, out] dev
8435  *   Pointer to rte_eth_dev structure.
8436  * @param[in] table_id
8437  *   Table id to use.
8438  * @param[in] egress
8439  *   Direction of the table.
8440  * @param[in] transfer
8441  *   E-Switch or NIC flow.
8442  * @param[in] dummy
8443  *   Dummy entry for dv API.
8444  * @param[out] error
8445  *   pointer to error structure.
8446  *
8447  * @return
8448  *   Returns tables resource based on the index, NULL in case of failed.
8449  */
8450 struct mlx5_flow_tbl_resource *
8451 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8452                          uint32_t table_id, uint8_t egress,
8453                          uint8_t transfer,
8454                          bool external,
8455                          const struct mlx5_flow_tunnel *tunnel,
8456                          uint32_t group_id, uint8_t dummy,
8457                          struct rte_flow_error *error)
8458 {
8459         struct mlx5_priv *priv = dev->data->dev_private;
8460         union mlx5_flow_tbl_key table_key = {
8461                 {
8462                         .table_id = table_id,
8463                         .dummy = dummy,
8464                         .domain = !!transfer,
8465                         .direction = !!egress,
8466                 }
8467         };
8468         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8469                 .tunnel = tunnel,
8470                 .group_id = group_id,
8471                 .external = external,
8472         };
8473         struct mlx5_flow_cb_ctx ctx = {
8474                 .dev = dev,
8475                 .error = error,
8476                 .data = &tt_prm,
8477         };
8478         struct mlx5_hlist_entry *entry;
8479         struct mlx5_flow_tbl_data_entry *tbl_data;
8480
8481         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8482         if (!entry) {
8483                 rte_flow_error_set(error, ENOMEM,
8484                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8485                                    "cannot get table");
8486                 return NULL;
8487         }
8488         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8489                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8490         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8491         return &tbl_data->tbl;
8492 }
8493
8494 void
8495 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8496                       struct mlx5_hlist_entry *entry)
8497 {
8498         struct mlx5_dev_ctx_shared *sh = list->ctx;
8499         struct mlx5_flow_tbl_data_entry *tbl_data =
8500                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8501
8502         MLX5_ASSERT(entry && sh);
8503         if (tbl_data->jump.action)
8504                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8505         if (tbl_data->tbl.obj)
8506                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8507         if (tbl_data->tunnel_offload && tbl_data->external) {
8508                 struct mlx5_hlist_entry *he;
8509                 struct mlx5_hlist *tunnel_grp_hash;
8510                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8511                 union tunnel_tbl_key tunnel_key = {
8512                         .tunnel_id = tbl_data->tunnel ?
8513                                         tbl_data->tunnel->tunnel_id : 0,
8514                         .group = tbl_data->group_id
8515                 };
8516                 uint32_t table_id = tbl_data->table_id;
8517
8518                 tunnel_grp_hash = tbl_data->tunnel ?
8519                                         tbl_data->tunnel->groups :
8520                                         thub->groups;
8521                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8522                 if (he)
8523                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8524                 DRV_LOG(DEBUG,
8525                         "Table_id %u tunnel %u group %u released.",
8526                         table_id,
8527                         tbl_data->tunnel ?
8528                         tbl_data->tunnel->tunnel_id : 0,
8529                         tbl_data->group_id);
8530         }
8531         mlx5_cache_list_destroy(&tbl_data->matchers);
8532         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8533 }
8534
8535 /**
8536  * Release a flow table.
8537  *
8538  * @param[in] sh
8539  *   Pointer to device shared structure.
8540  * @param[in] tbl
8541  *   Table resource to be released.
8542  *
8543  * @return
8544  *   Returns 0 if table was released, else return 1;
8545  */
8546 static int
8547 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8548                              struct mlx5_flow_tbl_resource *tbl)
8549 {
8550         struct mlx5_flow_tbl_data_entry *tbl_data =
8551                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8552
8553         if (!tbl)
8554                 return 0;
8555         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8556 }
8557
8558 int
8559 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8560                          struct mlx5_cache_entry *entry, void *cb_ctx)
8561 {
8562         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8563         struct mlx5_flow_dv_matcher *ref = ctx->data;
8564         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8565                                                         entry);
8566
8567         return cur->crc != ref->crc ||
8568                cur->priority != ref->priority ||
8569                memcmp((const void *)cur->mask.buf,
8570                       (const void *)ref->mask.buf, ref->mask.size);
8571 }
8572
8573 struct mlx5_cache_entry *
8574 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8575                           struct mlx5_cache_entry *entry __rte_unused,
8576                           void *cb_ctx)
8577 {
8578         struct mlx5_dev_ctx_shared *sh = list->ctx;
8579         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8580         struct mlx5_flow_dv_matcher *ref = ctx->data;
8581         struct mlx5_flow_dv_matcher *cache;
8582         struct mlx5dv_flow_matcher_attr dv_attr = {
8583                 .type = IBV_FLOW_ATTR_NORMAL,
8584                 .match_mask = (void *)&ref->mask,
8585         };
8586         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8587                                                             typeof(*tbl), tbl);
8588         int ret;
8589
8590         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8591         if (!cache) {
8592                 rte_flow_error_set(ctx->error, ENOMEM,
8593                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8594                                    "cannot create matcher");
8595                 return NULL;
8596         }
8597         *cache = *ref;
8598         dv_attr.match_criteria_enable =
8599                 flow_dv_matcher_enable(cache->mask.buf);
8600         dv_attr.priority = ref->priority;
8601         if (tbl->is_egress)
8602                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8603         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8604                                                &cache->matcher_object);
8605         if (ret) {
8606                 mlx5_free(cache);
8607                 rte_flow_error_set(ctx->error, ENOMEM,
8608                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8609                                    "cannot create matcher");
8610                 return NULL;
8611         }
8612         return &cache->entry;
8613 }
8614
8615 /**
8616  * Register the flow matcher.
8617  *
8618  * @param[in, out] dev
8619  *   Pointer to rte_eth_dev structure.
8620  * @param[in, out] matcher
8621  *   Pointer to flow matcher.
8622  * @param[in, out] key
8623  *   Pointer to flow table key.
8624  * @parm[in, out] dev_flow
8625  *   Pointer to the dev_flow.
8626  * @param[out] error
8627  *   pointer to error structure.
8628  *
8629  * @return
8630  *   0 on success otherwise -errno and errno is set.
8631  */
8632 static int
8633 flow_dv_matcher_register(struct rte_eth_dev *dev,
8634                          struct mlx5_flow_dv_matcher *ref,
8635                          union mlx5_flow_tbl_key *key,
8636                          struct mlx5_flow *dev_flow,
8637                          const struct mlx5_flow_tunnel *tunnel,
8638                          uint32_t group_id,
8639                          struct rte_flow_error *error)
8640 {
8641         struct mlx5_cache_entry *entry;
8642         struct mlx5_flow_dv_matcher *cache;
8643         struct mlx5_flow_tbl_resource *tbl;
8644         struct mlx5_flow_tbl_data_entry *tbl_data;
8645         struct mlx5_flow_cb_ctx ctx = {
8646                 .error = error,
8647                 .data = ref,
8648         };
8649
8650         /**
8651          * tunnel offload API requires this registration for cases when
8652          * tunnel match rule was inserted before tunnel set rule.
8653          */
8654         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8655                                        key->direction, key->domain,
8656                                        dev_flow->external, tunnel,
8657                                        group_id, 0, error);
8658         if (!tbl)
8659                 return -rte_errno;      /* No need to refill the error info */
8660         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8661         ref->tbl = tbl;
8662         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8663         if (!entry) {
8664                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8665                 return rte_flow_error_set(error, ENOMEM,
8666                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8667                                           "cannot allocate ref memory");
8668         }
8669         cache = container_of(entry, typeof(*cache), entry);
8670         dev_flow->handle->dvh.matcher = cache;
8671         return 0;
8672 }
8673
8674 struct mlx5_hlist_entry *
8675 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8676 {
8677         struct mlx5_dev_ctx_shared *sh = list->ctx;
8678         struct rte_flow_error *error = ctx;
8679         struct mlx5_flow_dv_tag_resource *entry;
8680         uint32_t idx = 0;
8681         int ret;
8682
8683         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8684         if (!entry) {
8685                 rte_flow_error_set(error, ENOMEM,
8686                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8687                                    "cannot allocate resource memory");
8688                 return NULL;
8689         }
8690         entry->idx = idx;
8691         entry->tag_id = key;
8692         ret = mlx5_flow_os_create_flow_action_tag(key,
8693                                                   &entry->action);
8694         if (ret) {
8695                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8696                 rte_flow_error_set(error, ENOMEM,
8697                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8698                                    NULL, "cannot create action");
8699                 return NULL;
8700         }
8701         return &entry->entry;
8702 }
8703
8704 int
8705 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8706                      struct mlx5_hlist_entry *entry, uint64_t key,
8707                      void *cb_ctx __rte_unused)
8708 {
8709         struct mlx5_flow_dv_tag_resource *tag =
8710                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8711
8712         return key != tag->tag_id;
8713 }
8714
8715 /**
8716  * Find existing tag resource or create and register a new one.
8717  *
8718  * @param dev[in, out]
8719  *   Pointer to rte_eth_dev structure.
8720  * @param[in, out] tag_be24
8721  *   Tag value in big endian then R-shift 8.
8722  * @parm[in, out] dev_flow
8723  *   Pointer to the dev_flow.
8724  * @param[out] error
8725  *   pointer to error structure.
8726  *
8727  * @return
8728  *   0 on success otherwise -errno and errno is set.
8729  */
8730 static int
8731 flow_dv_tag_resource_register
8732                         (struct rte_eth_dev *dev,
8733                          uint32_t tag_be24,
8734                          struct mlx5_flow *dev_flow,
8735                          struct rte_flow_error *error)
8736 {
8737         struct mlx5_priv *priv = dev->data->dev_private;
8738         struct mlx5_flow_dv_tag_resource *cache_resource;
8739         struct mlx5_hlist_entry *entry;
8740
8741         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8742         if (entry) {
8743                 cache_resource = container_of
8744                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8745                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8746                 dev_flow->dv.tag_resource = cache_resource;
8747                 return 0;
8748         }
8749         return -rte_errno;
8750 }
8751
8752 void
8753 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8754                       struct mlx5_hlist_entry *entry)
8755 {
8756         struct mlx5_dev_ctx_shared *sh = list->ctx;
8757         struct mlx5_flow_dv_tag_resource *tag =
8758                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8759
8760         MLX5_ASSERT(tag && sh && tag->action);
8761         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8762         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8763         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8764 }
8765
8766 /**
8767  * Release the tag.
8768  *
8769  * @param dev
8770  *   Pointer to Ethernet device.
8771  * @param tag_idx
8772  *   Tag index.
8773  *
8774  * @return
8775  *   1 while a reference on it exists, 0 when freed.
8776  */
8777 static int
8778 flow_dv_tag_release(struct rte_eth_dev *dev,
8779                     uint32_t tag_idx)
8780 {
8781         struct mlx5_priv *priv = dev->data->dev_private;
8782         struct mlx5_flow_dv_tag_resource *tag;
8783
8784         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8785         if (!tag)
8786                 return 0;
8787         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8788                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8789         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8790 }
8791
8792 /**
8793  * Translate port ID action to vport.
8794  *
8795  * @param[in] dev
8796  *   Pointer to rte_eth_dev structure.
8797  * @param[in] action
8798  *   Pointer to the port ID action.
8799  * @param[out] dst_port_id
8800  *   The target port ID.
8801  * @param[out] error
8802  *   Pointer to the error structure.
8803  *
8804  * @return
8805  *   0 on success, a negative errno value otherwise and rte_errno is set.
8806  */
8807 static int
8808 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8809                                  const struct rte_flow_action *action,
8810                                  uint32_t *dst_port_id,
8811                                  struct rte_flow_error *error)
8812 {
8813         uint32_t port;
8814         struct mlx5_priv *priv;
8815         const struct rte_flow_action_port_id *conf =
8816                         (const struct rte_flow_action_port_id *)action->conf;
8817
8818         port = conf->original ? dev->data->port_id : conf->id;
8819         priv = mlx5_port_to_eswitch_info(port, false);
8820         if (!priv)
8821                 return rte_flow_error_set(error, -rte_errno,
8822                                           RTE_FLOW_ERROR_TYPE_ACTION,
8823                                           NULL,
8824                                           "No eswitch info was found for port");
8825 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8826         /*
8827          * This parameter is transferred to
8828          * mlx5dv_dr_action_create_dest_ib_port().
8829          */
8830         *dst_port_id = priv->dev_port;
8831 #else
8832         /*
8833          * Legacy mode, no LAG configurations is supported.
8834          * This parameter is transferred to
8835          * mlx5dv_dr_action_create_dest_vport().
8836          */
8837         *dst_port_id = priv->vport_id;
8838 #endif
8839         return 0;
8840 }
8841
8842 /**
8843  * Create a counter with aging configuration.
8844  *
8845  * @param[in] dev
8846  *   Pointer to rte_eth_dev structure.
8847  * @param[out] count
8848  *   Pointer to the counter action configuration.
8849  * @param[in] age
8850  *   Pointer to the aging action configuration.
8851  *
8852  * @return
8853  *   Index to flow counter on success, 0 otherwise.
8854  */
8855 static uint32_t
8856 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8857                                 struct mlx5_flow *dev_flow,
8858                                 const struct rte_flow_action_count *count,
8859                                 const struct rte_flow_action_age *age)
8860 {
8861         uint32_t counter;
8862         struct mlx5_age_param *age_param;
8863
8864         if (count && count->shared)
8865                 counter = flow_dv_counter_get_shared(dev, count->id);
8866         else
8867                 counter = flow_dv_counter_alloc(dev, !!age);
8868         if (!counter || age == NULL)
8869                 return counter;
8870         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8871         age_param->context = age->context ? age->context :
8872                 (void *)(uintptr_t)(dev_flow->flow_idx);
8873         age_param->timeout = age->timeout;
8874         age_param->port_id = dev->data->port_id;
8875         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8876         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8877         return counter;
8878 }
8879
8880 /**
8881  * Add Tx queue matcher
8882  *
8883  * @param[in] dev
8884  *   Pointer to the dev struct.
8885  * @param[in, out] matcher
8886  *   Flow matcher.
8887  * @param[in, out] key
8888  *   Flow matcher value.
8889  * @param[in] item
8890  *   Flow pattern to translate.
8891  * @param[in] inner
8892  *   Item is inner pattern.
8893  */
8894 static void
8895 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8896                                 void *matcher, void *key,
8897                                 const struct rte_flow_item *item)
8898 {
8899         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8900         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8901         void *misc_m =
8902                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8903         void *misc_v =
8904                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8905         struct mlx5_txq_ctrl *txq;
8906         uint32_t queue;
8907
8908
8909         queue_m = (const void *)item->mask;
8910         if (!queue_m)
8911                 return;
8912         queue_v = (const void *)item->spec;
8913         if (!queue_v)
8914                 return;
8915         txq = mlx5_txq_get(dev, queue_v->queue);
8916         if (!txq)
8917                 return;
8918         queue = txq->obj->sq->id;
8919         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8920         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8921                  queue & queue_m->queue);
8922         mlx5_txq_release(dev, queue_v->queue);
8923 }
8924
8925 /**
8926  * Set the hash fields according to the @p flow information.
8927  *
8928  * @param[in] dev_flow
8929  *   Pointer to the mlx5_flow.
8930  * @param[in] rss_desc
8931  *   Pointer to the mlx5_flow_rss_desc.
8932  */
8933 static void
8934 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8935                        struct mlx5_flow_rss_desc *rss_desc)
8936 {
8937         uint64_t items = dev_flow->handle->layers;
8938         int rss_inner = 0;
8939         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8940
8941         dev_flow->hash_fields = 0;
8942 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8943         if (rss_desc->level >= 2) {
8944                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8945                 rss_inner = 1;
8946         }
8947 #endif
8948         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8949             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8950                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8951                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8952                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8953                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8954                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8955                         else
8956                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8957                 }
8958         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8959                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8960                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8961                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8962                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8963                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8964                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8965                         else
8966                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8967                 }
8968         }
8969         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8970             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8971                 if (rss_types & ETH_RSS_UDP) {
8972                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8973                                 dev_flow->hash_fields |=
8974                                                 IBV_RX_HASH_SRC_PORT_UDP;
8975                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8976                                 dev_flow->hash_fields |=
8977                                                 IBV_RX_HASH_DST_PORT_UDP;
8978                         else
8979                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8980                 }
8981         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8982                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8983                 if (rss_types & ETH_RSS_TCP) {
8984                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8985                                 dev_flow->hash_fields |=
8986                                                 IBV_RX_HASH_SRC_PORT_TCP;
8987                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8988                                 dev_flow->hash_fields |=
8989                                                 IBV_RX_HASH_DST_PORT_TCP;
8990                         else
8991                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8992                 }
8993         }
8994 }
8995
8996 /**
8997  * Prepare an Rx Hash queue.
8998  *
8999  * @param dev
9000  *   Pointer to Ethernet device.
9001  * @param[in] dev_flow
9002  *   Pointer to the mlx5_flow.
9003  * @param[in] rss_desc
9004  *   Pointer to the mlx5_flow_rss_desc.
9005  * @param[out] hrxq_idx
9006  *   Hash Rx queue index.
9007  *
9008  * @return
9009  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9010  */
9011 static struct mlx5_hrxq *
9012 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9013                      struct mlx5_flow *dev_flow,
9014                      struct mlx5_flow_rss_desc *rss_desc,
9015                      uint32_t *hrxq_idx)
9016 {
9017         struct mlx5_priv *priv = dev->data->dev_private;
9018         struct mlx5_flow_handle *dh = dev_flow->handle;
9019         struct mlx5_hrxq *hrxq;
9020
9021         MLX5_ASSERT(rss_desc->queue_num);
9022         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9023         rss_desc->hash_fields = dev_flow->hash_fields;
9024         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9025         rss_desc->shared_rss = 0;
9026         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9027         if (!*hrxq_idx)
9028                 return NULL;
9029         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9030                               *hrxq_idx);
9031         return hrxq;
9032 }
9033
9034 /**
9035  * Release sample sub action resource.
9036  *
9037  * @param[in, out] dev
9038  *   Pointer to rte_eth_dev structure.
9039  * @param[in] act_res
9040  *   Pointer to sample sub action resource.
9041  */
9042 static void
9043 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9044                                    struct mlx5_flow_sub_actions_idx *act_res)
9045 {
9046         if (act_res->rix_hrxq) {
9047                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9048                 act_res->rix_hrxq = 0;
9049         }
9050         if (act_res->rix_encap_decap) {
9051                 flow_dv_encap_decap_resource_release(dev,
9052                                                      act_res->rix_encap_decap);
9053                 act_res->rix_encap_decap = 0;
9054         }
9055         if (act_res->rix_port_id_action) {
9056                 flow_dv_port_id_action_resource_release(dev,
9057                                                 act_res->rix_port_id_action);
9058                 act_res->rix_port_id_action = 0;
9059         }
9060         if (act_res->rix_tag) {
9061                 flow_dv_tag_release(dev, act_res->rix_tag);
9062                 act_res->rix_tag = 0;
9063         }
9064         if (act_res->cnt) {
9065                 flow_dv_counter_free(dev, act_res->cnt);
9066                 act_res->cnt = 0;
9067         }
9068         if (act_res->rix_jump) {
9069                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9070                 act_res->rix_jump = 0;
9071         }
9072 }
9073
9074 int
9075 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9076                         struct mlx5_cache_entry *entry, void *cb_ctx)
9077 {
9078         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9079         struct rte_eth_dev *dev = ctx->dev;
9080         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9081         struct mlx5_flow_dv_sample_resource *cache_resource =
9082                         container_of(entry, typeof(*cache_resource), entry);
9083
9084         if (resource->ratio == cache_resource->ratio &&
9085             resource->ft_type == cache_resource->ft_type &&
9086             resource->ft_id == cache_resource->ft_id &&
9087             resource->set_action == cache_resource->set_action &&
9088             !memcmp((void *)&resource->sample_act,
9089                     (void *)&cache_resource->sample_act,
9090                     sizeof(struct mlx5_flow_sub_actions_list))) {
9091                 /*
9092                  * Existing sample action should release the prepared
9093                  * sub-actions reference counter.
9094                  */
9095                 flow_dv_sample_sub_actions_release(dev,
9096                                                 &resource->sample_idx);
9097                 return 0;
9098         }
9099         return 1;
9100 }
9101
9102 struct mlx5_cache_entry *
9103 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9104                          struct mlx5_cache_entry *entry __rte_unused,
9105                          void *cb_ctx)
9106 {
9107         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9108         struct rte_eth_dev *dev = ctx->dev;
9109         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9110         void **sample_dv_actions = resource->sub_actions;
9111         struct mlx5_flow_dv_sample_resource *cache_resource;
9112         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9113         struct mlx5_priv *priv = dev->data->dev_private;
9114         struct mlx5_dev_ctx_shared *sh = priv->sh;
9115         struct mlx5_flow_tbl_resource *tbl;
9116         uint32_t idx = 0;
9117         const uint32_t next_ft_step = 1;
9118         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9119         uint8_t is_egress = 0;
9120         uint8_t is_transfer = 0;
9121         struct rte_flow_error *error = ctx->error;
9122
9123         /* Register new sample resource. */
9124         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9125         if (!cache_resource) {
9126                 rte_flow_error_set(error, ENOMEM,
9127                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9128                                           NULL,
9129                                           "cannot allocate resource memory");
9130                 return NULL;
9131         }
9132         *cache_resource = *resource;
9133         /* Create normal path table level */
9134         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9135                 is_transfer = 1;
9136         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9137                 is_egress = 1;
9138         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9139                                         is_egress, is_transfer,
9140                                         true, NULL, 0, 0, error);
9141         if (!tbl) {
9142                 rte_flow_error_set(error, ENOMEM,
9143                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9144                                           NULL,
9145                                           "fail to create normal path table "
9146                                           "for sample");
9147                 goto error;
9148         }
9149         int ret;
9150
9151         cache_resource->normal_path_tbl = tbl;
9152         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9153                 ret = mlx5_flow_os_create_flow_action_default_miss
9154                         (&cache_resource->default_miss);
9155                 if (!ret) {
9156                         rte_flow_error_set(error, ENOMEM,
9157                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9158                                                 NULL,
9159                                                 "cannot create default miss "
9160                                                 "action");
9161                         goto error;
9162                 }
9163                 sample_dv_actions[resource->sample_act.actions_num++] =
9164                                                 cache_resource->default_miss;
9165         }
9166         /* Create a DR sample action */
9167         sampler_attr.sample_ratio = cache_resource->ratio;
9168         sampler_attr.default_next_table = tbl->obj;
9169         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9170         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9171                                                         &sample_dv_actions[0];
9172         sampler_attr.action = cache_resource->set_action;
9173         if (mlx5_os_flow_dr_create_flow_action_sampler
9174                         (&sampler_attr, &cache_resource->verbs_action)) {
9175                 rte_flow_error_set(error, ENOMEM,
9176                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9177                                         NULL, "cannot create sample action");
9178                 goto error;
9179         }
9180         cache_resource->idx = idx;
9181         cache_resource->dev = dev;
9182         return &cache_resource->entry;
9183 error:
9184         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
9185             cache_resource->default_miss)
9186                 claim_zero(mlx5_flow_os_destroy_flow_action
9187                                 (cache_resource->default_miss));
9188         else
9189                 flow_dv_sample_sub_actions_release(dev,
9190                                                    &cache_resource->sample_idx);
9191         if (cache_resource->normal_path_tbl)
9192                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9193                                 cache_resource->normal_path_tbl);
9194         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9195         return NULL;
9196
9197 }
9198
9199 /**
9200  * Find existing sample resource or create and register a new one.
9201  *
9202  * @param[in, out] dev
9203  *   Pointer to rte_eth_dev structure.
9204  * @param[in] resource
9205  *   Pointer to sample resource.
9206  * @parm[in, out] dev_flow
9207  *   Pointer to the dev_flow.
9208  * @param[out] error
9209  *   pointer to error structure.
9210  *
9211  * @return
9212  *   0 on success otherwise -errno and errno is set.
9213  */
9214 static int
9215 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9216                          struct mlx5_flow_dv_sample_resource *resource,
9217                          struct mlx5_flow *dev_flow,
9218                          struct rte_flow_error *error)
9219 {
9220         struct mlx5_flow_dv_sample_resource *cache_resource;
9221         struct mlx5_cache_entry *entry;
9222         struct mlx5_priv *priv = dev->data->dev_private;
9223         struct mlx5_flow_cb_ctx ctx = {
9224                 .dev = dev,
9225                 .error = error,
9226                 .data = resource,
9227         };
9228
9229         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9230         if (!entry)
9231                 return -rte_errno;
9232         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9233         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9234         dev_flow->dv.sample_res = cache_resource;
9235         return 0;
9236 }
9237
9238 int
9239 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9240                             struct mlx5_cache_entry *entry, void *cb_ctx)
9241 {
9242         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9243         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9244         struct rte_eth_dev *dev = ctx->dev;
9245         struct mlx5_flow_dv_dest_array_resource *cache_resource =
9246                         container_of(entry, typeof(*cache_resource), entry);
9247         uint32_t idx = 0;
9248
9249         if (resource->num_of_dest == cache_resource->num_of_dest &&
9250             resource->ft_type == cache_resource->ft_type &&
9251             !memcmp((void *)cache_resource->sample_act,
9252                     (void *)resource->sample_act,
9253                    (resource->num_of_dest *
9254                    sizeof(struct mlx5_flow_sub_actions_list)))) {
9255                 /*
9256                  * Existing sample action should release the prepared
9257                  * sub-actions reference counter.
9258                  */
9259                 for (idx = 0; idx < resource->num_of_dest; idx++)
9260                         flow_dv_sample_sub_actions_release(dev,
9261                                         &resource->sample_idx[idx]);
9262                 return 0;
9263         }
9264         return 1;
9265 }
9266
9267 struct mlx5_cache_entry *
9268 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9269                          struct mlx5_cache_entry *entry __rte_unused,
9270                          void *cb_ctx)
9271 {
9272         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9273         struct rte_eth_dev *dev = ctx->dev;
9274         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9275         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9276         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9277         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9278         struct mlx5_priv *priv = dev->data->dev_private;
9279         struct mlx5_dev_ctx_shared *sh = priv->sh;
9280         struct mlx5_flow_sub_actions_list *sample_act;
9281         struct mlx5dv_dr_domain *domain;
9282         uint32_t idx = 0, res_idx = 0;
9283         struct rte_flow_error *error = ctx->error;
9284         uint64_t action_flags;
9285         int ret;
9286
9287         /* Register new destination array resource. */
9288         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9289                                             &res_idx);
9290         if (!cache_resource) {
9291                 rte_flow_error_set(error, ENOMEM,
9292                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9293                                           NULL,
9294                                           "cannot allocate resource memory");
9295                 return NULL;
9296         }
9297         *cache_resource = *resource;
9298         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9299                 domain = sh->fdb_domain;
9300         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9301                 domain = sh->rx_domain;
9302         else
9303                 domain = sh->tx_domain;
9304         for (idx = 0; idx < resource->num_of_dest; idx++) {
9305                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9306                                  mlx5_malloc(MLX5_MEM_ZERO,
9307                                  sizeof(struct mlx5dv_dr_action_dest_attr),
9308                                  0, SOCKET_ID_ANY);
9309                 if (!dest_attr[idx]) {
9310                         rte_flow_error_set(error, ENOMEM,
9311                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9312                                            NULL,
9313                                            "cannot allocate resource memory");
9314                         goto error;
9315                 }
9316                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9317                 sample_act = &resource->sample_act[idx];
9318                 action_flags = sample_act->action_flags;
9319                 switch (action_flags) {
9320                 case MLX5_FLOW_ACTION_QUEUE:
9321                         dest_attr[idx]->dest = sample_act->dr_queue_action;
9322                         break;
9323                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
9324                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9325                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9326                         dest_attr[idx]->dest_reformat->reformat =
9327                                         sample_act->dr_encap_action;
9328                         dest_attr[idx]->dest_reformat->dest =
9329                                         sample_act->dr_port_id_action;
9330                         break;
9331                 case MLX5_FLOW_ACTION_PORT_ID:
9332                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
9333                         break;
9334                 case MLX5_FLOW_ACTION_JUMP:
9335                         dest_attr[idx]->dest = sample_act->dr_jump_action;
9336                         break;
9337                 default:
9338                         rte_flow_error_set(error, EINVAL,
9339                                            RTE_FLOW_ERROR_TYPE_ACTION,
9340                                            NULL,
9341                                            "unsupported actions type");
9342                         goto error;
9343                 }
9344         }
9345         /* create a dest array actioin */
9346         ret = mlx5_os_flow_dr_create_flow_action_dest_array
9347                                                 (domain,
9348                                                  cache_resource->num_of_dest,
9349                                                  dest_attr,
9350                                                  &cache_resource->action);
9351         if (ret) {
9352                 rte_flow_error_set(error, ENOMEM,
9353                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9354                                    NULL,
9355                                    "cannot create destination array action");
9356                 goto error;
9357         }
9358         cache_resource->idx = res_idx;
9359         cache_resource->dev = dev;
9360         for (idx = 0; idx < resource->num_of_dest; idx++)
9361                 mlx5_free(dest_attr[idx]);
9362         return &cache_resource->entry;
9363 error:
9364         for (idx = 0; idx < resource->num_of_dest; idx++) {
9365                 struct mlx5_flow_sub_actions_idx *act_res =
9366                                         &cache_resource->sample_idx[idx];
9367                 if (act_res->rix_hrxq &&
9368                     !mlx5_hrxq_release(dev,
9369                                 act_res->rix_hrxq))
9370                         act_res->rix_hrxq = 0;
9371                 if (act_res->rix_encap_decap &&
9372                         !flow_dv_encap_decap_resource_release(dev,
9373                                 act_res->rix_encap_decap))
9374                         act_res->rix_encap_decap = 0;
9375                 if (act_res->rix_port_id_action &&
9376                         !flow_dv_port_id_action_resource_release(dev,
9377                                 act_res->rix_port_id_action))
9378                         act_res->rix_port_id_action = 0;
9379                 if (act_res->rix_jump &&
9380                         !flow_dv_jump_tbl_resource_release(dev,
9381                                 act_res->rix_jump))
9382                         act_res->rix_jump = 0;
9383                 if (dest_attr[idx])
9384                         mlx5_free(dest_attr[idx]);
9385         }
9386
9387         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9388         return NULL;
9389 }
9390
9391 /**
9392  * Find existing destination array resource or create and register a new one.
9393  *
9394  * @param[in, out] dev
9395  *   Pointer to rte_eth_dev structure.
9396  * @param[in] resource
9397  *   Pointer to destination array resource.
9398  * @parm[in, out] dev_flow
9399  *   Pointer to the dev_flow.
9400  * @param[out] error
9401  *   pointer to error structure.
9402  *
9403  * @return
9404  *   0 on success otherwise -errno and errno is set.
9405  */
9406 static int
9407 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9408                          struct mlx5_flow_dv_dest_array_resource *resource,
9409                          struct mlx5_flow *dev_flow,
9410                          struct rte_flow_error *error)
9411 {
9412         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9413         struct mlx5_priv *priv = dev->data->dev_private;
9414         struct mlx5_cache_entry *entry;
9415         struct mlx5_flow_cb_ctx ctx = {
9416                 .dev = dev,
9417                 .error = error,
9418                 .data = resource,
9419         };
9420
9421         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9422         if (!entry)
9423                 return -rte_errno;
9424         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9425         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9426         dev_flow->dv.dest_array_res = cache_resource;
9427         return 0;
9428 }
9429
9430 /**
9431  * Convert Sample action to DV specification.
9432  *
9433  * @param[in] dev
9434  *   Pointer to rte_eth_dev structure.
9435  * @param[in] action
9436  *   Pointer to sample action structure.
9437  * @param[in, out] dev_flow
9438  *   Pointer to the mlx5_flow.
9439  * @param[in] attr
9440  *   Pointer to the flow attributes.
9441  * @param[in, out] num_of_dest
9442  *   Pointer to the num of destination.
9443  * @param[in, out] sample_actions
9444  *   Pointer to sample actions list.
9445  * @param[in, out] res
9446  *   Pointer to sample resource.
9447  * @param[out] error
9448  *   Pointer to the error structure.
9449  *
9450  * @return
9451  *   0 on success, a negative errno value otherwise and rte_errno is set.
9452  */
9453 static int
9454 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9455                                 const struct rte_flow_action_sample *action,
9456                                 struct mlx5_flow *dev_flow,
9457                                 const struct rte_flow_attr *attr,
9458                                 uint32_t *num_of_dest,
9459                                 void **sample_actions,
9460                                 struct mlx5_flow_dv_sample_resource *res,
9461                                 struct rte_flow_error *error)
9462 {
9463         struct mlx5_priv *priv = dev->data->dev_private;
9464         const struct rte_flow_action *sub_actions;
9465         struct mlx5_flow_sub_actions_list *sample_act;
9466         struct mlx5_flow_sub_actions_idx *sample_idx;
9467         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9468         struct mlx5_flow_rss_desc *rss_desc;
9469         uint64_t action_flags = 0;
9470
9471         MLX5_ASSERT(wks);
9472         rss_desc = &wks->rss_desc;
9473         sample_act = &res->sample_act;
9474         sample_idx = &res->sample_idx;
9475         res->ratio = action->ratio;
9476         sub_actions = action->actions;
9477         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9478                 int type = sub_actions->type;
9479                 uint32_t pre_rix = 0;
9480                 void *pre_r;
9481                 switch (type) {
9482                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9483                 {
9484                         const struct rte_flow_action_queue *queue;
9485                         struct mlx5_hrxq *hrxq;
9486                         uint32_t hrxq_idx;
9487
9488                         queue = sub_actions->conf;
9489                         rss_desc->queue_num = 1;
9490                         rss_desc->queue[0] = queue->index;
9491                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9492                                                     rss_desc, &hrxq_idx);
9493                         if (!hrxq)
9494                                 return rte_flow_error_set
9495                                         (error, rte_errno,
9496                                          RTE_FLOW_ERROR_TYPE_ACTION,
9497                                          NULL,
9498                                          "cannot create fate queue");
9499                         sample_act->dr_queue_action = hrxq->action;
9500                         sample_idx->rix_hrxq = hrxq_idx;
9501                         sample_actions[sample_act->actions_num++] =
9502                                                 hrxq->action;
9503                         (*num_of_dest)++;
9504                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9505                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9506                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9507                         dev_flow->handle->fate_action =
9508                                         MLX5_FLOW_FATE_QUEUE;
9509                         break;
9510                 }
9511                 case RTE_FLOW_ACTION_TYPE_RSS:
9512                 {
9513                         struct mlx5_hrxq *hrxq;
9514                         uint32_t hrxq_idx;
9515                         const struct rte_flow_action_rss *rss;
9516                         const uint8_t *rss_key;
9517
9518                         rss = sub_actions->conf;
9519                         memcpy(rss_desc->queue, rss->queue,
9520                                rss->queue_num * sizeof(uint16_t));
9521                         rss_desc->queue_num = rss->queue_num;
9522                         /* NULL RSS key indicates default RSS key. */
9523                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9524                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9525                         /*
9526                          * rss->level and rss.types should be set in advance
9527                          * when expanding items for RSS.
9528                          */
9529                         flow_dv_hashfields_set(dev_flow, rss_desc);
9530                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9531                                                     rss_desc, &hrxq_idx);
9532                         if (!hrxq)
9533                                 return rte_flow_error_set
9534                                         (error, rte_errno,
9535                                          RTE_FLOW_ERROR_TYPE_ACTION,
9536                                          NULL,
9537                                          "cannot create fate queue");
9538                         sample_act->dr_queue_action = hrxq->action;
9539                         sample_idx->rix_hrxq = hrxq_idx;
9540                         sample_actions[sample_act->actions_num++] =
9541                                                 hrxq->action;
9542                         (*num_of_dest)++;
9543                         action_flags |= MLX5_FLOW_ACTION_RSS;
9544                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9545                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9546                         dev_flow->handle->fate_action =
9547                                         MLX5_FLOW_FATE_QUEUE;
9548                         break;
9549                 }
9550                 case RTE_FLOW_ACTION_TYPE_MARK:
9551                 {
9552                         uint32_t tag_be = mlx5_flow_mark_set
9553                                 (((const struct rte_flow_action_mark *)
9554                                 (sub_actions->conf))->id);
9555
9556                         dev_flow->handle->mark = 1;
9557                         pre_rix = dev_flow->handle->dvh.rix_tag;
9558                         /* Save the mark resource before sample */
9559                         pre_r = dev_flow->dv.tag_resource;
9560                         if (flow_dv_tag_resource_register(dev, tag_be,
9561                                                   dev_flow, error))
9562                                 return -rte_errno;
9563                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9564                         sample_act->dr_tag_action =
9565                                 dev_flow->dv.tag_resource->action;
9566                         sample_idx->rix_tag =
9567                                 dev_flow->handle->dvh.rix_tag;
9568                         sample_actions[sample_act->actions_num++] =
9569                                                 sample_act->dr_tag_action;
9570                         /* Recover the mark resource after sample */
9571                         dev_flow->dv.tag_resource = pre_r;
9572                         dev_flow->handle->dvh.rix_tag = pre_rix;
9573                         action_flags |= MLX5_FLOW_ACTION_MARK;
9574                         break;
9575                 }
9576                 case RTE_FLOW_ACTION_TYPE_COUNT:
9577                 {
9578                         uint32_t counter;
9579
9580                         counter = flow_dv_translate_create_counter(dev,
9581                                         dev_flow, sub_actions->conf, 0);
9582                         if (!counter)
9583                                 return rte_flow_error_set
9584                                                 (error, rte_errno,
9585                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9586                                                  NULL,
9587                                                  "cannot create counter"
9588                                                  " object.");
9589                         sample_idx->cnt = counter;
9590                         sample_act->dr_cnt_action =
9591                                   (flow_dv_counter_get_by_idx(dev,
9592                                   counter, NULL))->action;
9593                         sample_actions[sample_act->actions_num++] =
9594                                                 sample_act->dr_cnt_action;
9595                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9596                         break;
9597                 }
9598                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9599                 {
9600                         struct mlx5_flow_dv_port_id_action_resource
9601                                         port_id_resource;
9602                         uint32_t port_id = 0;
9603
9604                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9605                         /* Save the port id resource before sample */
9606                         pre_rix = dev_flow->handle->rix_port_id_action;
9607                         pre_r = dev_flow->dv.port_id_action;
9608                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9609                                                              &port_id, error))
9610                                 return -rte_errno;
9611                         port_id_resource.port_id = port_id;
9612                         if (flow_dv_port_id_action_resource_register
9613                             (dev, &port_id_resource, dev_flow, error))
9614                                 return -rte_errno;
9615                         sample_act->dr_port_id_action =
9616                                 dev_flow->dv.port_id_action->action;
9617                         sample_idx->rix_port_id_action =
9618                                 dev_flow->handle->rix_port_id_action;
9619                         sample_actions[sample_act->actions_num++] =
9620                                                 sample_act->dr_port_id_action;
9621                         /* Recover the port id resource after sample */
9622                         dev_flow->dv.port_id_action = pre_r;
9623                         dev_flow->handle->rix_port_id_action = pre_rix;
9624                         (*num_of_dest)++;
9625                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9626                         break;
9627                 }
9628                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9629                         /* Save the encap resource before sample */
9630                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9631                         pre_r = dev_flow->dv.encap_decap;
9632                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9633                                                            dev_flow,
9634                                                            attr->transfer,
9635                                                            error))
9636                                 return -rte_errno;
9637                         sample_act->dr_encap_action =
9638                                 dev_flow->dv.encap_decap->action;
9639                         sample_idx->rix_encap_decap =
9640                                 dev_flow->handle->dvh.rix_encap_decap;
9641                         sample_actions[sample_act->actions_num++] =
9642                                                 sample_act->dr_encap_action;
9643                         /* Recover the encap resource after sample */
9644                         dev_flow->dv.encap_decap = pre_r;
9645                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9646                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9647                         break;
9648                 default:
9649                         return rte_flow_error_set(error, EINVAL,
9650                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9651                                 NULL,
9652                                 "Not support for sampler action");
9653                 }
9654         }
9655         sample_act->action_flags = action_flags;
9656         res->ft_id = dev_flow->dv.group;
9657         if (attr->transfer) {
9658                 union {
9659                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9660                         uint64_t set_action;
9661                 } action_ctx = { .set_action = 0 };
9662
9663                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9664                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9665                          MLX5_MODIFICATION_TYPE_SET);
9666                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9667                          MLX5_MODI_META_REG_C_0);
9668                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9669                          priv->vport_meta_tag);
9670                 res->set_action = action_ctx.set_action;
9671         } else if (attr->ingress) {
9672                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9673         } else {
9674                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9675         }
9676         return 0;
9677 }
9678
9679 /**
9680  * Convert Sample action to DV specification.
9681  *
9682  * @param[in] dev
9683  *   Pointer to rte_eth_dev structure.
9684  * @param[in, out] dev_flow
9685  *   Pointer to the mlx5_flow.
9686  * @param[in] num_of_dest
9687  *   The num of destination.
9688  * @param[in, out] res
9689  *   Pointer to sample resource.
9690  * @param[in, out] mdest_res
9691  *   Pointer to destination array resource.
9692  * @param[in] sample_actions
9693  *   Pointer to sample path actions list.
9694  * @param[in] action_flags
9695  *   Holds the actions detected until now.
9696  * @param[out] error
9697  *   Pointer to the error structure.
9698  *
9699  * @return
9700  *   0 on success, a negative errno value otherwise and rte_errno is set.
9701  */
9702 static int
9703 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9704                              struct mlx5_flow *dev_flow,
9705                              uint32_t num_of_dest,
9706                              struct mlx5_flow_dv_sample_resource *res,
9707                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9708                              void **sample_actions,
9709                              uint64_t action_flags,
9710                              struct rte_flow_error *error)
9711 {
9712         /* update normal path action resource into last index of array */
9713         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9714         struct mlx5_flow_sub_actions_list *sample_act =
9715                                         &mdest_res->sample_act[dest_index];
9716         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9717         struct mlx5_flow_rss_desc *rss_desc;
9718         uint32_t normal_idx = 0;
9719         struct mlx5_hrxq *hrxq;
9720         uint32_t hrxq_idx;
9721
9722         MLX5_ASSERT(wks);
9723         rss_desc = &wks->rss_desc;
9724         if (num_of_dest > 1) {
9725                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9726                         /* Handle QP action for mirroring */
9727                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9728                                                     rss_desc, &hrxq_idx);
9729                         if (!hrxq)
9730                                 return rte_flow_error_set
9731                                      (error, rte_errno,
9732                                       RTE_FLOW_ERROR_TYPE_ACTION,
9733                                       NULL,
9734                                       "cannot create rx queue");
9735                         normal_idx++;
9736                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9737                         sample_act->dr_queue_action = hrxq->action;
9738                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9739                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9740                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9741                 }
9742                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9743                         normal_idx++;
9744                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9745                                 dev_flow->handle->dvh.rix_encap_decap;
9746                         sample_act->dr_encap_action =
9747                                 dev_flow->dv.encap_decap->action;
9748                 }
9749                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9750                         normal_idx++;
9751                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9752                                 dev_flow->handle->rix_port_id_action;
9753                         sample_act->dr_port_id_action =
9754                                 dev_flow->dv.port_id_action->action;
9755                 }
9756                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
9757                         normal_idx++;
9758                         mdest_res->sample_idx[dest_index].rix_jump =
9759                                 dev_flow->handle->rix_jump;
9760                         sample_act->dr_jump_action =
9761                                 dev_flow->dv.jump->action;
9762                         dev_flow->handle->rix_jump = 0;
9763                 }
9764                 sample_act->actions_num = normal_idx;
9765                 /* update sample action resource into first index of array */
9766                 mdest_res->ft_type = res->ft_type;
9767                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9768                                 sizeof(struct mlx5_flow_sub_actions_idx));
9769                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9770                                 sizeof(struct mlx5_flow_sub_actions_list));
9771                 mdest_res->num_of_dest = num_of_dest;
9772                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9773                                                          dev_flow, error))
9774                         return rte_flow_error_set(error, EINVAL,
9775                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9776                                                   NULL, "can't create sample "
9777                                                   "action");
9778         } else {
9779                 res->sub_actions = sample_actions;
9780                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9781                         return rte_flow_error_set(error, EINVAL,
9782                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9783                                                   NULL,
9784                                                   "can't create sample action");
9785         }
9786         return 0;
9787 }
9788
9789 /**
9790  * Remove an ASO age action from age actions list.
9791  *
9792  * @param[in] dev
9793  *   Pointer to the Ethernet device structure.
9794  * @param[in] age
9795  *   Pointer to the aso age action handler.
9796  */
9797 static void
9798 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9799                                 struct mlx5_aso_age_action *age)
9800 {
9801         struct mlx5_age_info *age_info;
9802         struct mlx5_age_param *age_param = &age->age_params;
9803         struct mlx5_priv *priv = dev->data->dev_private;
9804         uint16_t expected = AGE_CANDIDATE;
9805
9806         age_info = GET_PORT_AGE_INFO(priv);
9807         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9808                                          AGE_FREE, false, __ATOMIC_RELAXED,
9809                                          __ATOMIC_RELAXED)) {
9810                 /**
9811                  * We need the lock even it is age timeout,
9812                  * since age action may still in process.
9813                  */
9814                 rte_spinlock_lock(&age_info->aged_sl);
9815                 LIST_REMOVE(age, next);
9816                 rte_spinlock_unlock(&age_info->aged_sl);
9817                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9818         }
9819 }
9820
9821 /**
9822  * Release an ASO age action.
9823  *
9824  * @param[in] dev
9825  *   Pointer to the Ethernet device structure.
9826  * @param[in] age_idx
9827  *   Index of ASO age action to release.
9828  * @param[in] flow
9829  *   True if the release operation is during flow destroy operation.
9830  *   False if the release operation is during action destroy operation.
9831  *
9832  * @return
9833  *   0 when age action was removed, otherwise the number of references.
9834  */
9835 static int
9836 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9837 {
9838         struct mlx5_priv *priv = dev->data->dev_private;
9839         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9840         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9841         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9842
9843         if (!ret) {
9844                 flow_dv_aso_age_remove_from_age(dev, age);
9845                 rte_spinlock_lock(&mng->free_sl);
9846                 LIST_INSERT_HEAD(&mng->free, age, next);
9847                 rte_spinlock_unlock(&mng->free_sl);
9848         }
9849         return ret;
9850 }
9851
9852 /**
9853  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9854  *
9855  * @param[in] dev
9856  *   Pointer to the Ethernet device structure.
9857  *
9858  * @return
9859  *   0 on success, otherwise negative errno value and rte_errno is set.
9860  */
9861 static int
9862 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9863 {
9864         struct mlx5_priv *priv = dev->data->dev_private;
9865         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9866         void *old_pools = mng->pools;
9867         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9868         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9869         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9870
9871         if (!pools) {
9872                 rte_errno = ENOMEM;
9873                 return -ENOMEM;
9874         }
9875         if (old_pools) {
9876                 memcpy(pools, old_pools,
9877                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9878                 mlx5_free(old_pools);
9879         } else {
9880                 /* First ASO flow hit allocation - starting ASO data-path. */
9881                 int ret = mlx5_aso_queue_start(priv->sh);
9882
9883                 if (ret) {
9884                         mlx5_free(pools);
9885                         return ret;
9886                 }
9887         }
9888         mng->n = resize;
9889         mng->pools = pools;
9890         return 0;
9891 }
9892
9893 /**
9894  * Create and initialize a new ASO aging pool.
9895  *
9896  * @param[in] dev
9897  *   Pointer to the Ethernet device structure.
9898  * @param[out] age_free
9899  *   Where to put the pointer of a new age action.
9900  *
9901  * @return
9902  *   The age actions pool pointer and @p age_free is set on success,
9903  *   NULL otherwise and rte_errno is set.
9904  */
9905 static struct mlx5_aso_age_pool *
9906 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9907                         struct mlx5_aso_age_action **age_free)
9908 {
9909         struct mlx5_priv *priv = dev->data->dev_private;
9910         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9911         struct mlx5_aso_age_pool *pool = NULL;
9912         struct mlx5_devx_obj *obj = NULL;
9913         uint32_t i;
9914
9915         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9916                                                     priv->sh->pdn);
9917         if (!obj) {
9918                 rte_errno = ENODATA;
9919                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9920                 return NULL;
9921         }
9922         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9923         if (!pool) {
9924                 claim_zero(mlx5_devx_cmd_destroy(obj));
9925                 rte_errno = ENOMEM;
9926                 return NULL;
9927         }
9928         pool->flow_hit_aso_obj = obj;
9929         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9930         rte_spinlock_lock(&mng->resize_sl);
9931         pool->index = mng->next;
9932         /* Resize pools array if there is no room for the new pool in it. */
9933         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9934                 claim_zero(mlx5_devx_cmd_destroy(obj));
9935                 mlx5_free(pool);
9936                 rte_spinlock_unlock(&mng->resize_sl);
9937                 return NULL;
9938         }
9939         mng->pools[pool->index] = pool;
9940         mng->next++;
9941         rte_spinlock_unlock(&mng->resize_sl);
9942         /* Assign the first action in the new pool, the rest go to free list. */
9943         *age_free = &pool->actions[0];
9944         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9945                 pool->actions[i].offset = i;
9946                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9947         }
9948         return pool;
9949 }
9950
9951 /**
9952  * Allocate a ASO aging bit.
9953  *
9954  * @param[in] dev
9955  *   Pointer to the Ethernet device structure.
9956  * @param[out] error
9957  *   Pointer to the error structure.
9958  *
9959  * @return
9960  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9961  */
9962 static uint32_t
9963 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9964 {
9965         struct mlx5_priv *priv = dev->data->dev_private;
9966         const struct mlx5_aso_age_pool *pool;
9967         struct mlx5_aso_age_action *age_free = NULL;
9968         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9969
9970         MLX5_ASSERT(mng);
9971         /* Try to get the next free age action bit. */
9972         rte_spinlock_lock(&mng->free_sl);
9973         age_free = LIST_FIRST(&mng->free);
9974         if (age_free) {
9975                 LIST_REMOVE(age_free, next);
9976         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9977                 rte_spinlock_unlock(&mng->free_sl);
9978                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9979                                    NULL, "failed to create ASO age pool");
9980                 return 0; /* 0 is an error. */
9981         }
9982         rte_spinlock_unlock(&mng->free_sl);
9983         pool = container_of
9984           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9985                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9986                                                                        actions);
9987         if (!age_free->dr_action) {
9988                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9989                                                  error);
9990
9991                 if (reg_c < 0) {
9992                         rte_flow_error_set(error, rte_errno,
9993                                            RTE_FLOW_ERROR_TYPE_ACTION,
9994                                            NULL, "failed to get reg_c "
9995                                            "for ASO flow hit");
9996                         return 0; /* 0 is an error. */
9997                 }
9998 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9999                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10000                                 (priv->sh->rx_domain,
10001                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10002                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10003                                  (reg_c - REG_C_0));
10004 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10005                 if (!age_free->dr_action) {
10006                         rte_errno = errno;
10007                         rte_spinlock_lock(&mng->free_sl);
10008                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10009                         rte_spinlock_unlock(&mng->free_sl);
10010                         rte_flow_error_set(error, rte_errno,
10011                                            RTE_FLOW_ERROR_TYPE_ACTION,
10012                                            NULL, "failed to create ASO "
10013                                            "flow hit action");
10014                         return 0; /* 0 is an error. */
10015                 }
10016         }
10017         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10018         return pool->index | ((age_free->offset + 1) << 16);
10019 }
10020
10021 /**
10022  * Create a age action using ASO mechanism.
10023  *
10024  * @param[in] dev
10025  *   Pointer to rte_eth_dev structure.
10026  * @param[in] age
10027  *   Pointer to the aging action configuration.
10028  * @param[out] error
10029  *   Pointer to the error structure.
10030  *
10031  * @return
10032  *   Index to flow counter on success, 0 otherwise.
10033  */
10034 static uint32_t
10035 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10036                                  const struct rte_flow_action_age *age,
10037                                  struct rte_flow_error *error)
10038 {
10039         uint32_t age_idx = 0;
10040         struct mlx5_aso_age_action *aso_age;
10041
10042         age_idx = flow_dv_aso_age_alloc(dev, error);
10043         if (!age_idx)
10044                 return 0;
10045         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10046         aso_age->age_params.context = age->context;
10047         aso_age->age_params.timeout = age->timeout;
10048         aso_age->age_params.port_id = dev->data->port_id;
10049         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10050                          __ATOMIC_RELAXED);
10051         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10052                          __ATOMIC_RELAXED);
10053         return age_idx;
10054 }
10055
10056 /**
10057  * Fill the flow with DV spec, lock free
10058  * (mutex should be acquired by caller).
10059  *
10060  * @param[in] dev
10061  *   Pointer to rte_eth_dev structure.
10062  * @param[in, out] dev_flow
10063  *   Pointer to the sub flow.
10064  * @param[in] attr
10065  *   Pointer to the flow attributes.
10066  * @param[in] items
10067  *   Pointer to the list of items.
10068  * @param[in] actions
10069  *   Pointer to the list of actions.
10070  * @param[out] error
10071  *   Pointer to the error structure.
10072  *
10073  * @return
10074  *   0 on success, a negative errno value otherwise and rte_errno is set.
10075  */
10076 static int
10077 flow_dv_translate(struct rte_eth_dev *dev,
10078                   struct mlx5_flow *dev_flow,
10079                   const struct rte_flow_attr *attr,
10080                   const struct rte_flow_item items[],
10081                   const struct rte_flow_action actions[],
10082                   struct rte_flow_error *error)
10083 {
10084         struct mlx5_priv *priv = dev->data->dev_private;
10085         struct mlx5_dev_config *dev_conf = &priv->config;
10086         struct rte_flow *flow = dev_flow->flow;
10087         struct mlx5_flow_handle *handle = dev_flow->handle;
10088         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10089         struct mlx5_flow_rss_desc *rss_desc;
10090         uint64_t item_flags = 0;
10091         uint64_t last_item = 0;
10092         uint64_t action_flags = 0;
10093         struct mlx5_flow_dv_matcher matcher = {
10094                 .mask = {
10095                         .size = sizeof(matcher.mask.buf) -
10096                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10097                 },
10098         };
10099         int actions_n = 0;
10100         bool actions_end = false;
10101         union {
10102                 struct mlx5_flow_dv_modify_hdr_resource res;
10103                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10104                             sizeof(struct mlx5_modification_cmd) *
10105                             (MLX5_MAX_MODIFY_NUM + 1)];
10106         } mhdr_dummy;
10107         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10108         const struct rte_flow_action_count *count = NULL;
10109         const struct rte_flow_action_age *age = NULL;
10110         union flow_dv_attr flow_attr = { .attr = 0 };
10111         uint32_t tag_be;
10112         union mlx5_flow_tbl_key tbl_key;
10113         uint32_t modify_action_position = UINT32_MAX;
10114         void *match_mask = matcher.mask.buf;
10115         void *match_value = dev_flow->dv.value.buf;
10116         uint8_t next_protocol = 0xff;
10117         struct rte_vlan_hdr vlan = { 0 };
10118         struct mlx5_flow_dv_dest_array_resource mdest_res;
10119         struct mlx5_flow_dv_sample_resource sample_res;
10120         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10121         const struct rte_flow_action_sample *sample = NULL;
10122         struct mlx5_flow_sub_actions_list *sample_act;
10123         uint32_t sample_act_pos = UINT32_MAX;
10124         uint32_t num_of_dest = 0;
10125         int tmp_actions_n = 0;
10126         uint32_t table;
10127         int ret = 0;
10128         const struct mlx5_flow_tunnel *tunnel;
10129         struct flow_grp_info grp_info = {
10130                 .external = !!dev_flow->external,
10131                 .transfer = !!attr->transfer,
10132                 .fdb_def_rule = !!priv->fdb_def_rule,
10133                 .skip_scale = dev_flow->skip_scale &
10134                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10135         };
10136
10137         if (!wks)
10138                 return rte_flow_error_set(error, ENOMEM,
10139                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10140                                           NULL,
10141                                           "failed to push flow workspace");
10142         rss_desc = &wks->rss_desc;
10143         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10144         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10145         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10146                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10147         /* update normal path action resource into last index of array */
10148         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10149         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10150                  flow_items_to_tunnel(items) :
10151                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10152                  flow_actions_to_tunnel(actions) :
10153                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10154         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10155                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10156         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10157                                 (dev, tunnel, attr, items, actions);
10158         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10159                                        &grp_info, error);
10160         if (ret)
10161                 return ret;
10162         dev_flow->dv.group = table;
10163         if (attr->transfer)
10164                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10165         /* number of actions must be set to 0 in case of dirty stack. */
10166         mhdr_res->actions_num = 0;
10167         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10168                 /*
10169                  * do not add decap action if match rule drops packet
10170                  * HW rejects rules with decap & drop
10171                  *
10172                  * if tunnel match rule was inserted before matching tunnel set
10173                  * rule flow table used in the match rule must be registered.
10174                  * current implementation handles that in the
10175                  * flow_dv_match_register() at the function end.
10176                  */
10177                 bool add_decap = true;
10178                 const struct rte_flow_action *ptr = actions;
10179
10180                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10181                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10182                                 add_decap = false;
10183                                 break;
10184                         }
10185                 }
10186                 if (add_decap) {
10187                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10188                                                            attr->transfer,
10189                                                            error))
10190                                 return -rte_errno;
10191                         dev_flow->dv.actions[actions_n++] =
10192                                         dev_flow->dv.encap_decap->action;
10193                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10194                 }
10195         }
10196         for (; !actions_end ; actions++) {
10197                 const struct rte_flow_action_queue *queue;
10198                 const struct rte_flow_action_rss *rss;
10199                 const struct rte_flow_action *action = actions;
10200                 const uint8_t *rss_key;
10201                 const struct rte_flow_action_meter *mtr;
10202                 struct mlx5_flow_tbl_resource *tbl;
10203                 struct mlx5_aso_age_action *age_act;
10204                 uint32_t port_id = 0;
10205                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10206                 int action_type = actions->type;
10207                 const struct rte_flow_action *found_action = NULL;
10208                 struct mlx5_flow_meter *fm = NULL;
10209                 uint32_t jump_group = 0;
10210
10211                 if (!mlx5_flow_os_action_supported(action_type))
10212                         return rte_flow_error_set(error, ENOTSUP,
10213                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10214                                                   actions,
10215                                                   "action not supported");
10216                 switch (action_type) {
10217                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10218                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10219                         break;
10220                 case RTE_FLOW_ACTION_TYPE_VOID:
10221                         break;
10222                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10223                         if (flow_dv_translate_action_port_id(dev, action,
10224                                                              &port_id, error))
10225                                 return -rte_errno;
10226                         port_id_resource.port_id = port_id;
10227                         MLX5_ASSERT(!handle->rix_port_id_action);
10228                         if (flow_dv_port_id_action_resource_register
10229                             (dev, &port_id_resource, dev_flow, error))
10230                                 return -rte_errno;
10231                         dev_flow->dv.actions[actions_n++] =
10232                                         dev_flow->dv.port_id_action->action;
10233                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10234                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10235                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10236                         num_of_dest++;
10237                         break;
10238                 case RTE_FLOW_ACTION_TYPE_FLAG:
10239                         action_flags |= MLX5_FLOW_ACTION_FLAG;
10240                         dev_flow->handle->mark = 1;
10241                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10242                                 struct rte_flow_action_mark mark = {
10243                                         .id = MLX5_FLOW_MARK_DEFAULT,
10244                                 };
10245
10246                                 if (flow_dv_convert_action_mark(dev, &mark,
10247                                                                 mhdr_res,
10248                                                                 error))
10249                                         return -rte_errno;
10250                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10251                                 break;
10252                         }
10253                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10254                         /*
10255                          * Only one FLAG or MARK is supported per device flow
10256                          * right now. So the pointer to the tag resource must be
10257                          * zero before the register process.
10258                          */
10259                         MLX5_ASSERT(!handle->dvh.rix_tag);
10260                         if (flow_dv_tag_resource_register(dev, tag_be,
10261                                                           dev_flow, error))
10262                                 return -rte_errno;
10263                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10264                         dev_flow->dv.actions[actions_n++] =
10265                                         dev_flow->dv.tag_resource->action;
10266                         break;
10267                 case RTE_FLOW_ACTION_TYPE_MARK:
10268                         action_flags |= MLX5_FLOW_ACTION_MARK;
10269                         dev_flow->handle->mark = 1;
10270                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10271                                 const struct rte_flow_action_mark *mark =
10272                                         (const struct rte_flow_action_mark *)
10273                                                 actions->conf;
10274
10275                                 if (flow_dv_convert_action_mark(dev, mark,
10276                                                                 mhdr_res,
10277                                                                 error))
10278                                         return -rte_errno;
10279                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10280                                 break;
10281                         }
10282                         /* Fall-through */
10283                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10284                         /* Legacy (non-extensive) MARK action. */
10285                         tag_be = mlx5_flow_mark_set
10286                               (((const struct rte_flow_action_mark *)
10287                                (actions->conf))->id);
10288                         MLX5_ASSERT(!handle->dvh.rix_tag);
10289                         if (flow_dv_tag_resource_register(dev, tag_be,
10290                                                           dev_flow, error))
10291                                 return -rte_errno;
10292                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10293                         dev_flow->dv.actions[actions_n++] =
10294                                         dev_flow->dv.tag_resource->action;
10295                         break;
10296                 case RTE_FLOW_ACTION_TYPE_SET_META:
10297                         if (flow_dv_convert_action_set_meta
10298                                 (dev, mhdr_res, attr,
10299                                  (const struct rte_flow_action_set_meta *)
10300                                   actions->conf, error))
10301                                 return -rte_errno;
10302                         action_flags |= MLX5_FLOW_ACTION_SET_META;
10303                         break;
10304                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10305                         if (flow_dv_convert_action_set_tag
10306                                 (dev, mhdr_res,
10307                                  (const struct rte_flow_action_set_tag *)
10308                                   actions->conf, error))
10309                                 return -rte_errno;
10310                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10311                         break;
10312                 case RTE_FLOW_ACTION_TYPE_DROP:
10313                         action_flags |= MLX5_FLOW_ACTION_DROP;
10314                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10315                         break;
10316                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10317                         queue = actions->conf;
10318                         rss_desc->queue_num = 1;
10319                         rss_desc->queue[0] = queue->index;
10320                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10321                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10322                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10323                         num_of_dest++;
10324                         break;
10325                 case RTE_FLOW_ACTION_TYPE_RSS:
10326                         rss = actions->conf;
10327                         memcpy(rss_desc->queue, rss->queue,
10328                                rss->queue_num * sizeof(uint16_t));
10329                         rss_desc->queue_num = rss->queue_num;
10330                         /* NULL RSS key indicates default RSS key. */
10331                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10332                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10333                         /*
10334                          * rss->level and rss.types should be set in advance
10335                          * when expanding items for RSS.
10336                          */
10337                         action_flags |= MLX5_FLOW_ACTION_RSS;
10338                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
10339                                 MLX5_FLOW_FATE_SHARED_RSS :
10340                                 MLX5_FLOW_FATE_QUEUE;
10341                         break;
10342                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10343                         flow->age = (uint32_t)(uintptr_t)(action->conf);
10344                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
10345                         __atomic_fetch_add(&age_act->refcnt, 1,
10346                                            __ATOMIC_RELAXED);
10347                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10348                         action_flags |= MLX5_FLOW_ACTION_AGE;
10349                         break;
10350                 case RTE_FLOW_ACTION_TYPE_AGE:
10351                         if (priv->sh->flow_hit_aso_en && attr->group) {
10352                                 /*
10353                                  * Create one shared age action, to be used
10354                                  * by all sub-flows.
10355                                  */
10356                                 if (!flow->age) {
10357                                         flow->age =
10358                                                 flow_dv_translate_create_aso_age
10359                                                         (dev, action->conf,
10360                                                          error);
10361                                         if (!flow->age)
10362                                                 return rte_flow_error_set
10363                                                 (error, rte_errno,
10364                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10365                                                  NULL,
10366                                                  "can't create ASO age action");
10367                                 }
10368                                 dev_flow->dv.actions[actions_n++] =
10369                                           (flow_aso_age_get_by_idx
10370                                                 (dev, flow->age))->dr_action;
10371                                 action_flags |= MLX5_FLOW_ACTION_AGE;
10372                                 break;
10373                         }
10374                         /* Fall-through */
10375                 case RTE_FLOW_ACTION_TYPE_COUNT:
10376                         if (!dev_conf->devx) {
10377                                 return rte_flow_error_set
10378                                               (error, ENOTSUP,
10379                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10380                                                NULL,
10381                                                "count action not supported");
10382                         }
10383                         /* Save information first, will apply later. */
10384                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10385                                 count = action->conf;
10386                         else
10387                                 age = action->conf;
10388                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10389                         break;
10390                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10391                         dev_flow->dv.actions[actions_n++] =
10392                                                 priv->sh->pop_vlan_action;
10393                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10394                         break;
10395                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10396                         if (!(action_flags &
10397                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10398                                 flow_dev_get_vlan_info_from_items(items, &vlan);
10399                         vlan.eth_proto = rte_be_to_cpu_16
10400                              ((((const struct rte_flow_action_of_push_vlan *)
10401                                                    actions->conf)->ethertype));
10402                         found_action = mlx5_flow_find_action
10403                                         (actions + 1,
10404                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10405                         if (found_action)
10406                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10407                         found_action = mlx5_flow_find_action
10408                                         (actions + 1,
10409                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10410                         if (found_action)
10411                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10412                         if (flow_dv_create_action_push_vlan
10413                                             (dev, attr, &vlan, dev_flow, error))
10414                                 return -rte_errno;
10415                         dev_flow->dv.actions[actions_n++] =
10416                                         dev_flow->dv.push_vlan_res->action;
10417                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10418                         break;
10419                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10420                         /* of_vlan_push action handled this action */
10421                         MLX5_ASSERT(action_flags &
10422                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10423                         break;
10424                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10425                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10426                                 break;
10427                         flow_dev_get_vlan_info_from_items(items, &vlan);
10428                         mlx5_update_vlan_vid_pcp(actions, &vlan);
10429                         /* If no VLAN push - this is a modify header action */
10430                         if (flow_dv_convert_action_modify_vlan_vid
10431                                                 (mhdr_res, actions, error))
10432                                 return -rte_errno;
10433                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10434                         break;
10435                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10436                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10437                         if (flow_dv_create_action_l2_encap(dev, actions,
10438                                                            dev_flow,
10439                                                            attr->transfer,
10440                                                            error))
10441                                 return -rte_errno;
10442                         dev_flow->dv.actions[actions_n++] =
10443                                         dev_flow->dv.encap_decap->action;
10444                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10445                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10446                                 sample_act->action_flags |=
10447                                                         MLX5_FLOW_ACTION_ENCAP;
10448                         break;
10449                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10450                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10451                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10452                                                            attr->transfer,
10453                                                            error))
10454                                 return -rte_errno;
10455                         dev_flow->dv.actions[actions_n++] =
10456                                         dev_flow->dv.encap_decap->action;
10457                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10458                         break;
10459                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10460                         /* Handle encap with preceding decap. */
10461                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10462                                 if (flow_dv_create_action_raw_encap
10463                                         (dev, actions, dev_flow, attr, error))
10464                                         return -rte_errno;
10465                                 dev_flow->dv.actions[actions_n++] =
10466                                         dev_flow->dv.encap_decap->action;
10467                         } else {
10468                                 /* Handle encap without preceding decap. */
10469                                 if (flow_dv_create_action_l2_encap
10470                                     (dev, actions, dev_flow, attr->transfer,
10471                                      error))
10472                                         return -rte_errno;
10473                                 dev_flow->dv.actions[actions_n++] =
10474                                         dev_flow->dv.encap_decap->action;
10475                         }
10476                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10477                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10478                                 sample_act->action_flags |=
10479                                                         MLX5_FLOW_ACTION_ENCAP;
10480                         break;
10481                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10482                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10483                                 ;
10484                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10485                                 if (flow_dv_create_action_l2_decap
10486                                     (dev, dev_flow, attr->transfer, error))
10487                                         return -rte_errno;
10488                                 dev_flow->dv.actions[actions_n++] =
10489                                         dev_flow->dv.encap_decap->action;
10490                         }
10491                         /* If decap is followed by encap, handle it at encap. */
10492                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10493                         break;
10494                 case RTE_FLOW_ACTION_TYPE_JUMP:
10495                         jump_group = ((const struct rte_flow_action_jump *)
10496                                                         action->conf)->group;
10497                         grp_info.std_tbl_fix = 0;
10498                         if (dev_flow->skip_scale &
10499                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
10500                                 grp_info.skip_scale = 1;
10501                         else
10502                                 grp_info.skip_scale = 0;
10503                         ret = mlx5_flow_group_to_table(dev, tunnel,
10504                                                        jump_group,
10505                                                        &table,
10506                                                        &grp_info, error);
10507                         if (ret)
10508                                 return ret;
10509                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10510                                                        attr->transfer,
10511                                                        !!dev_flow->external,
10512                                                        tunnel, jump_group, 0,
10513                                                        error);
10514                         if (!tbl)
10515                                 return rte_flow_error_set
10516                                                 (error, errno,
10517                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10518                                                  NULL,
10519                                                  "cannot create jump action.");
10520                         if (flow_dv_jump_tbl_resource_register
10521                             (dev, tbl, dev_flow, error)) {
10522                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10523                                 return rte_flow_error_set
10524                                                 (error, errno,
10525                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10526                                                  NULL,
10527                                                  "cannot create jump action.");
10528                         }
10529                         dev_flow->dv.actions[actions_n++] =
10530                                         dev_flow->dv.jump->action;
10531                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10532                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10533                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
10534                         num_of_dest++;
10535                         break;
10536                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10537                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10538                         if (flow_dv_convert_action_modify_mac
10539                                         (mhdr_res, actions, error))
10540                                 return -rte_errno;
10541                         action_flags |= actions->type ==
10542                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10543                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10544                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10545                         break;
10546                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10547                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10548                         if (flow_dv_convert_action_modify_ipv4
10549                                         (mhdr_res, actions, error))
10550                                 return -rte_errno;
10551                         action_flags |= actions->type ==
10552                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10553                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10554                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10555                         break;
10556                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10557                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10558                         if (flow_dv_convert_action_modify_ipv6
10559                                         (mhdr_res, actions, error))
10560                                 return -rte_errno;
10561                         action_flags |= actions->type ==
10562                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10563                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10564                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10565                         break;
10566                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10567                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10568                         if (flow_dv_convert_action_modify_tp
10569                                         (mhdr_res, actions, items,
10570                                          &flow_attr, dev_flow, !!(action_flags &
10571                                          MLX5_FLOW_ACTION_DECAP), error))
10572                                 return -rte_errno;
10573                         action_flags |= actions->type ==
10574                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10575                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10576                                         MLX5_FLOW_ACTION_SET_TP_DST;
10577                         break;
10578                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10579                         if (flow_dv_convert_action_modify_dec_ttl
10580                                         (mhdr_res, items, &flow_attr, dev_flow,
10581                                          !!(action_flags &
10582                                          MLX5_FLOW_ACTION_DECAP), error))
10583                                 return -rte_errno;
10584                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10585                         break;
10586                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10587                         if (flow_dv_convert_action_modify_ttl
10588                                         (mhdr_res, actions, items, &flow_attr,
10589                                          dev_flow, !!(action_flags &
10590                                          MLX5_FLOW_ACTION_DECAP), error))
10591                                 return -rte_errno;
10592                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10593                         break;
10594                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10595                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10596                         if (flow_dv_convert_action_modify_tcp_seq
10597                                         (mhdr_res, actions, error))
10598                                 return -rte_errno;
10599                         action_flags |= actions->type ==
10600                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10601                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10602                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10603                         break;
10604
10605                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10606                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10607                         if (flow_dv_convert_action_modify_tcp_ack
10608                                         (mhdr_res, actions, error))
10609                                 return -rte_errno;
10610                         action_flags |= actions->type ==
10611                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10612                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10613                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10614                         break;
10615                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10616                         if (flow_dv_convert_action_set_reg
10617                                         (mhdr_res, actions, error))
10618                                 return -rte_errno;
10619                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10620                         break;
10621                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10622                         if (flow_dv_convert_action_copy_mreg
10623                                         (dev, mhdr_res, actions, error))
10624                                 return -rte_errno;
10625                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10626                         break;
10627                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10628                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10629                         dev_flow->handle->fate_action =
10630                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10631                         break;
10632                 case RTE_FLOW_ACTION_TYPE_METER:
10633                         mtr = actions->conf;
10634                         if (!flow->meter) {
10635                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10636                                                             attr, error);
10637                                 if (!fm)
10638                                         return rte_flow_error_set(error,
10639                                                 rte_errno,
10640                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10641                                                 NULL,
10642                                                 "meter not found "
10643                                                 "or invalid parameters");
10644                                 flow->meter = fm->idx;
10645                         }
10646                         /* Set the meter action. */
10647                         if (!fm) {
10648                                 fm = mlx5_ipool_get(priv->sh->ipool
10649                                                 [MLX5_IPOOL_MTR], flow->meter);
10650                                 if (!fm)
10651                                         return rte_flow_error_set(error,
10652                                                 rte_errno,
10653                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10654                                                 NULL,
10655                                                 "meter not found "
10656                                                 "or invalid parameters");
10657                         }
10658                         dev_flow->dv.actions[actions_n++] =
10659                                 fm->mfts->meter_action;
10660                         action_flags |= MLX5_FLOW_ACTION_METER;
10661                         break;
10662                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10663                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10664                                                               actions, error))
10665                                 return -rte_errno;
10666                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10667                         break;
10668                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10669                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10670                                                               actions, error))
10671                                 return -rte_errno;
10672                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10673                         break;
10674                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10675                         sample_act_pos = actions_n;
10676                         sample = (const struct rte_flow_action_sample *)
10677                                  action->conf;
10678                         actions_n++;
10679                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10680                         /* put encap action into group if work with port id */
10681                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10682                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10683                                 sample_act->action_flags |=
10684                                                         MLX5_FLOW_ACTION_ENCAP;
10685                         break;
10686                 case RTE_FLOW_ACTION_TYPE_END:
10687                         actions_end = true;
10688                         if (mhdr_res->actions_num) {
10689                                 /* create modify action if needed. */
10690                                 if (flow_dv_modify_hdr_resource_register
10691                                         (dev, mhdr_res, dev_flow, error))
10692                                         return -rte_errno;
10693                                 dev_flow->dv.actions[modify_action_position] =
10694                                         handle->dvh.modify_hdr->action;
10695                         }
10696                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10697                                 /*
10698                                  * Create one count action, to be used
10699                                  * by all sub-flows.
10700                                  */
10701                                 if (!flow->counter) {
10702                                         flow->counter =
10703                                                 flow_dv_translate_create_counter
10704                                                         (dev, dev_flow, count,
10705                                                          age);
10706                                         if (!flow->counter)
10707                                                 return rte_flow_error_set
10708                                                 (error, rte_errno,
10709                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10710                                                  NULL, "cannot create counter"
10711                                                  " object.");
10712                                 }
10713                                 dev_flow->dv.actions[actions_n] =
10714                                           (flow_dv_counter_get_by_idx(dev,
10715                                           flow->counter, NULL))->action;
10716                                 actions_n++;
10717                         }
10718                 default:
10719                         break;
10720                 }
10721                 if (mhdr_res->actions_num &&
10722                     modify_action_position == UINT32_MAX)
10723                         modify_action_position = actions_n++;
10724         }
10725         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10726                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10727                 int item_type = items->type;
10728
10729                 if (!mlx5_flow_os_item_supported(item_type))
10730                         return rte_flow_error_set(error, ENOTSUP,
10731                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10732                                                   NULL, "item not supported");
10733                 switch (item_type) {
10734                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10735                         flow_dv_translate_item_port_id
10736                                 (dev, match_mask, match_value, items, attr);
10737                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10738                         break;
10739                 case RTE_FLOW_ITEM_TYPE_ETH:
10740                         flow_dv_translate_item_eth(match_mask, match_value,
10741                                                    items, tunnel,
10742                                                    dev_flow->dv.group);
10743                         matcher.priority = action_flags &
10744                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10745                                         !dev_flow->external ?
10746                                         MLX5_PRIORITY_MAP_L3 :
10747                                         MLX5_PRIORITY_MAP_L2;
10748                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10749                                              MLX5_FLOW_LAYER_OUTER_L2;
10750                         break;
10751                 case RTE_FLOW_ITEM_TYPE_VLAN:
10752                         flow_dv_translate_item_vlan(dev_flow,
10753                                                     match_mask, match_value,
10754                                                     items, tunnel,
10755                                                     dev_flow->dv.group);
10756                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10757                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10758                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10759                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10760                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10761                         break;
10762                 case RTE_FLOW_ITEM_TYPE_IPV4:
10763                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10764                                                   &item_flags, &tunnel);
10765                         flow_dv_translate_item_ipv4(match_mask, match_value,
10766                                                     items, tunnel,
10767                                                     dev_flow->dv.group);
10768                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10769                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10770                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10771                         if (items->mask != NULL &&
10772                             ((const struct rte_flow_item_ipv4 *)
10773                              items->mask)->hdr.next_proto_id) {
10774                                 next_protocol =
10775                                         ((const struct rte_flow_item_ipv4 *)
10776                                          (items->spec))->hdr.next_proto_id;
10777                                 next_protocol &=
10778                                         ((const struct rte_flow_item_ipv4 *)
10779                                          (items->mask))->hdr.next_proto_id;
10780                         } else {
10781                                 /* Reset for inner layer. */
10782                                 next_protocol = 0xff;
10783                         }
10784                         break;
10785                 case RTE_FLOW_ITEM_TYPE_IPV6:
10786                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10787                                                   &item_flags, &tunnel);
10788                         flow_dv_translate_item_ipv6(match_mask, match_value,
10789                                                     items, tunnel,
10790                                                     dev_flow->dv.group);
10791                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10792                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10793                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10794                         if (items->mask != NULL &&
10795                             ((const struct rte_flow_item_ipv6 *)
10796                              items->mask)->hdr.proto) {
10797                                 next_protocol =
10798                                         ((const struct rte_flow_item_ipv6 *)
10799                                          items->spec)->hdr.proto;
10800                                 next_protocol &=
10801                                         ((const struct rte_flow_item_ipv6 *)
10802                                          items->mask)->hdr.proto;
10803                         } else {
10804                                 /* Reset for inner layer. */
10805                                 next_protocol = 0xff;
10806                         }
10807                         break;
10808                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10809                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10810                                                              match_value,
10811                                                              items, tunnel);
10812                         last_item = tunnel ?
10813                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10814                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10815                         if (items->mask != NULL &&
10816                             ((const struct rte_flow_item_ipv6_frag_ext *)
10817                              items->mask)->hdr.next_header) {
10818                                 next_protocol =
10819                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10820                                  items->spec)->hdr.next_header;
10821                                 next_protocol &=
10822                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10823                                  items->mask)->hdr.next_header;
10824                         } else {
10825                                 /* Reset for inner layer. */
10826                                 next_protocol = 0xff;
10827                         }
10828                         break;
10829                 case RTE_FLOW_ITEM_TYPE_TCP:
10830                         flow_dv_translate_item_tcp(match_mask, match_value,
10831                                                    items, tunnel);
10832                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10833                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10834                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10835                         break;
10836                 case RTE_FLOW_ITEM_TYPE_UDP:
10837                         flow_dv_translate_item_udp(match_mask, match_value,
10838                                                    items, tunnel);
10839                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10840                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10841                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10842                         break;
10843                 case RTE_FLOW_ITEM_TYPE_GRE:
10844                         flow_dv_translate_item_gre(match_mask, match_value,
10845                                                    items, tunnel);
10846                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10847                         last_item = MLX5_FLOW_LAYER_GRE;
10848                         break;
10849                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10850                         flow_dv_translate_item_gre_key(match_mask,
10851                                                        match_value, items);
10852                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10853                         break;
10854                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10855                         flow_dv_translate_item_nvgre(match_mask, match_value,
10856                                                      items, tunnel);
10857                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10858                         last_item = MLX5_FLOW_LAYER_GRE;
10859                         break;
10860                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10861                         flow_dv_translate_item_vxlan(match_mask, match_value,
10862                                                      items, tunnel);
10863                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10864                         last_item = MLX5_FLOW_LAYER_VXLAN;
10865                         break;
10866                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10867                         flow_dv_translate_item_vxlan_gpe(match_mask,
10868                                                          match_value, items,
10869                                                          tunnel);
10870                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10871                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10872                         break;
10873                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10874                         flow_dv_translate_item_geneve(match_mask, match_value,
10875                                                       items, tunnel);
10876                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10877                         last_item = MLX5_FLOW_LAYER_GENEVE;
10878                         break;
10879                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
10880                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
10881                                                           match_value,
10882                                                           items, error);
10883                         if (ret)
10884                                 return rte_flow_error_set(error, -ret,
10885                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10886                                         "cannot create GENEVE TLV option");
10887                         flow->geneve_tlv_option = 1;
10888                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
10889                         break;
10890                 case RTE_FLOW_ITEM_TYPE_MPLS:
10891                         flow_dv_translate_item_mpls(match_mask, match_value,
10892                                                     items, last_item, tunnel);
10893                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10894                         last_item = MLX5_FLOW_LAYER_MPLS;
10895                         break;
10896                 case RTE_FLOW_ITEM_TYPE_MARK:
10897                         flow_dv_translate_item_mark(dev, match_mask,
10898                                                     match_value, items);
10899                         last_item = MLX5_FLOW_ITEM_MARK;
10900                         break;
10901                 case RTE_FLOW_ITEM_TYPE_META:
10902                         flow_dv_translate_item_meta(dev, match_mask,
10903                                                     match_value, attr, items);
10904                         last_item = MLX5_FLOW_ITEM_METADATA;
10905                         break;
10906                 case RTE_FLOW_ITEM_TYPE_ICMP:
10907                         flow_dv_translate_item_icmp(match_mask, match_value,
10908                                                     items, tunnel);
10909                         last_item = MLX5_FLOW_LAYER_ICMP;
10910                         break;
10911                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10912                         flow_dv_translate_item_icmp6(match_mask, match_value,
10913                                                       items, tunnel);
10914                         last_item = MLX5_FLOW_LAYER_ICMP6;
10915                         break;
10916                 case RTE_FLOW_ITEM_TYPE_TAG:
10917                         flow_dv_translate_item_tag(dev, match_mask,
10918                                                    match_value, items);
10919                         last_item = MLX5_FLOW_ITEM_TAG;
10920                         break;
10921                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10922                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10923                                                         match_value, items);
10924                         last_item = MLX5_FLOW_ITEM_TAG;
10925                         break;
10926                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10927                         flow_dv_translate_item_tx_queue(dev, match_mask,
10928                                                         match_value,
10929                                                         items);
10930                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10931                         break;
10932                 case RTE_FLOW_ITEM_TYPE_GTP:
10933                         flow_dv_translate_item_gtp(match_mask, match_value,
10934                                                    items, tunnel);
10935                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10936                         last_item = MLX5_FLOW_LAYER_GTP;
10937                         break;
10938                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10939                         ret = flow_dv_translate_item_gtp_psc(match_mask,
10940                                                           match_value,
10941                                                           items);
10942                         if (ret)
10943                                 return rte_flow_error_set(error, -ret,
10944                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10945                                         "cannot create GTP PSC item");
10946                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
10947                         break;
10948                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10949                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10950                                 /* Create it only the first time to be used. */
10951                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10952                                 if (ret)
10953                                         return rte_flow_error_set
10954                                                 (error, -ret,
10955                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10956                                                 NULL,
10957                                                 "cannot create eCPRI parser");
10958                         }
10959                         /* Adjust the length matcher and device flow value. */
10960                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10961                         dev_flow->dv.value.size =
10962                                         MLX5_ST_SZ_BYTES(fte_match_param);
10963                         flow_dv_translate_item_ecpri(dev, match_mask,
10964                                                      match_value, items);
10965                         /* No other protocol should follow eCPRI layer. */
10966                         last_item = MLX5_FLOW_LAYER_ECPRI;
10967                         break;
10968                 default:
10969                         break;
10970                 }
10971                 item_flags |= last_item;
10972         }
10973         /*
10974          * When E-Switch mode is enabled, we have two cases where we need to
10975          * set the source port manually.
10976          * The first one, is in case of Nic steering rule, and the second is
10977          * E-Switch rule where no port_id item was found. In both cases
10978          * the source port is set according the current port in use.
10979          */
10980         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10981             (priv->representor || priv->master)) {
10982                 if (flow_dv_translate_item_port_id(dev, match_mask,
10983                                                    match_value, NULL, attr))
10984                         return -rte_errno;
10985         }
10986 #ifdef RTE_LIBRTE_MLX5_DEBUG
10987         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10988                                               dev_flow->dv.value.buf));
10989 #endif
10990         /*
10991          * Layers may be already initialized from prefix flow if this dev_flow
10992          * is the suffix flow.
10993          */
10994         handle->layers |= item_flags;
10995         if (action_flags & MLX5_FLOW_ACTION_RSS)
10996                 flow_dv_hashfields_set(dev_flow, rss_desc);
10997         /* If has RSS action in the sample action, the Sample/Mirror resource
10998          * should be registered after the hash filed be update.
10999          */
11000         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11001                 ret = flow_dv_translate_action_sample(dev,
11002                                                       sample,
11003                                                       dev_flow, attr,
11004                                                       &num_of_dest,
11005                                                       sample_actions,
11006                                                       &sample_res,
11007                                                       error);
11008                 if (ret < 0)
11009                         return ret;
11010                 ret = flow_dv_create_action_sample(dev,
11011                                                    dev_flow,
11012                                                    num_of_dest,
11013                                                    &sample_res,
11014                                                    &mdest_res,
11015                                                    sample_actions,
11016                                                    action_flags,
11017                                                    error);
11018                 if (ret < 0)
11019                         return rte_flow_error_set
11020                                                 (error, rte_errno,
11021                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11022                                                 NULL,
11023                                                 "cannot create sample action");
11024                 if (num_of_dest > 1) {
11025                         dev_flow->dv.actions[sample_act_pos] =
11026                         dev_flow->dv.dest_array_res->action;
11027                 } else {
11028                         dev_flow->dv.actions[sample_act_pos] =
11029                         dev_flow->dv.sample_res->verbs_action;
11030                 }
11031         }
11032         /*
11033          * For multiple destination (sample action with ratio=1), the encap
11034          * action and port id action will be combined into group action.
11035          * So need remove the original these actions in the flow and only
11036          * use the sample action instead of.
11037          */
11038         if (num_of_dest > 1 &&
11039             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11040                 int i;
11041                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11042
11043                 for (i = 0; i < actions_n; i++) {
11044                         if ((sample_act->dr_encap_action &&
11045                                 sample_act->dr_encap_action ==
11046                                 dev_flow->dv.actions[i]) ||
11047                                 (sample_act->dr_port_id_action &&
11048                                 sample_act->dr_port_id_action ==
11049                                 dev_flow->dv.actions[i]) ||
11050                                 (sample_act->dr_jump_action &&
11051                                 sample_act->dr_jump_action ==
11052                                 dev_flow->dv.actions[i]))
11053                                 continue;
11054                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11055                 }
11056                 memcpy((void *)dev_flow->dv.actions,
11057                                 (void *)temp_actions,
11058                                 tmp_actions_n * sizeof(void *));
11059                 actions_n = tmp_actions_n;
11060         }
11061         dev_flow->dv.actions_n = actions_n;
11062         dev_flow->act_flags = action_flags;
11063         /* Register matcher. */
11064         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11065                                     matcher.mask.size);
11066         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11067                                         matcher.priority);
11068         /* reserved field no needs to be set to 0 here. */
11069         tbl_key.domain = attr->transfer;
11070         tbl_key.direction = attr->egress;
11071         tbl_key.table_id = dev_flow->dv.group;
11072         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11073                                      tunnel, attr->group, error))
11074                 return -rte_errno;
11075         return 0;
11076 }
11077
11078 /**
11079  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11080  * and tunnel.
11081  *
11082  * @param[in, out] action
11083  *   Shred RSS action holding hash RX queue objects.
11084  * @param[in] hash_fields
11085  *   Defines combination of packet fields to participate in RX hash.
11086  * @param[in] tunnel
11087  *   Tunnel type
11088  * @param[in] hrxq_idx
11089  *   Hash RX queue index to set.
11090  *
11091  * @return
11092  *   0 on success, otherwise negative errno value.
11093  */
11094 static int
11095 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11096                               const uint64_t hash_fields,
11097                               const int tunnel,
11098                               uint32_t hrxq_idx)
11099 {
11100         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11101
11102         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11103         case MLX5_RSS_HASH_IPV4:
11104                 hrxqs[0] = hrxq_idx;
11105                 return 0;
11106         case MLX5_RSS_HASH_IPV4_TCP:
11107                 hrxqs[1] = hrxq_idx;
11108                 return 0;
11109         case MLX5_RSS_HASH_IPV4_UDP:
11110                 hrxqs[2] = hrxq_idx;
11111                 return 0;
11112         case MLX5_RSS_HASH_IPV6:
11113                 hrxqs[3] = hrxq_idx;
11114                 return 0;
11115         case MLX5_RSS_HASH_IPV6_TCP:
11116                 hrxqs[4] = hrxq_idx;
11117                 return 0;
11118         case MLX5_RSS_HASH_IPV6_UDP:
11119                 hrxqs[5] = hrxq_idx;
11120                 return 0;
11121         case MLX5_RSS_HASH_NONE:
11122                 hrxqs[6] = hrxq_idx;
11123                 return 0;
11124         default:
11125                 return -1;
11126         }
11127 }
11128
11129 /**
11130  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11131  * and tunnel.
11132  *
11133  * @param[in] dev
11134  *   Pointer to the Ethernet device structure.
11135  * @param[in] idx
11136  *   Shared RSS action ID holding hash RX queue objects.
11137  * @param[in] hash_fields
11138  *   Defines combination of packet fields to participate in RX hash.
11139  * @param[in] tunnel
11140  *   Tunnel type
11141  *
11142  * @return
11143  *   Valid hash RX queue index, otherwise 0.
11144  */
11145 static uint32_t
11146 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11147                                  const uint64_t hash_fields,
11148                                  const int tunnel)
11149 {
11150         struct mlx5_priv *priv = dev->data->dev_private;
11151         struct mlx5_shared_action_rss *shared_rss =
11152             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11153         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11154                                                         shared_rss->hrxq_tunnel;
11155
11156         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11157         case MLX5_RSS_HASH_IPV4:
11158                 return hrxqs[0];
11159         case MLX5_RSS_HASH_IPV4_TCP:
11160                 return hrxqs[1];
11161         case MLX5_RSS_HASH_IPV4_UDP:
11162                 return hrxqs[2];
11163         case MLX5_RSS_HASH_IPV6:
11164                 return hrxqs[3];
11165         case MLX5_RSS_HASH_IPV6_TCP:
11166                 return hrxqs[4];
11167         case MLX5_RSS_HASH_IPV6_UDP:
11168                 return hrxqs[5];
11169         case MLX5_RSS_HASH_NONE:
11170                 return hrxqs[6];
11171         default:
11172                 return 0;
11173         }
11174 }
11175
11176 /**
11177  * Apply the flow to the NIC, lock free,
11178  * (mutex should be acquired by caller).
11179  *
11180  * @param[in] dev
11181  *   Pointer to the Ethernet device structure.
11182  * @param[in, out] flow
11183  *   Pointer to flow structure.
11184  * @param[out] error
11185  *   Pointer to error structure.
11186  *
11187  * @return
11188  *   0 on success, a negative errno value otherwise and rte_errno is set.
11189  */
11190 static int
11191 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11192               struct rte_flow_error *error)
11193 {
11194         struct mlx5_flow_dv_workspace *dv;
11195         struct mlx5_flow_handle *dh;
11196         struct mlx5_flow_handle_dv *dv_h;
11197         struct mlx5_flow *dev_flow;
11198         struct mlx5_priv *priv = dev->data->dev_private;
11199         uint32_t handle_idx;
11200         int n;
11201         int err;
11202         int idx;
11203         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11204         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11205
11206         MLX5_ASSERT(wks);
11207         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11208                 dev_flow = &wks->flows[idx];
11209                 dv = &dev_flow->dv;
11210                 dh = dev_flow->handle;
11211                 dv_h = &dh->dvh;
11212                 n = dv->actions_n;
11213                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11214                         if (dv->transfer) {
11215                                 dv->actions[n++] = priv->sh->esw_drop_action;
11216                         } else {
11217                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11218                                 dv->actions[n++] =
11219                                                 priv->drop_queue.hrxq->action;
11220                         }
11221                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11222                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11223                         struct mlx5_hrxq *hrxq;
11224                         uint32_t hrxq_idx;
11225
11226                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11227                                                     &hrxq_idx);
11228                         if (!hrxq) {
11229                                 rte_flow_error_set
11230                                         (error, rte_errno,
11231                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11232                                          "cannot get hash queue");
11233                                 goto error;
11234                         }
11235                         dh->rix_hrxq = hrxq_idx;
11236                         dv->actions[n++] = hrxq->action;
11237                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11238                         struct mlx5_hrxq *hrxq = NULL;
11239                         uint32_t hrxq_idx;
11240
11241                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11242                                                 rss_desc->shared_rss,
11243                                                 dev_flow->hash_fields,
11244                                                 !!(dh->layers &
11245                                                 MLX5_FLOW_LAYER_TUNNEL));
11246                         if (hrxq_idx)
11247                                 hrxq = mlx5_ipool_get
11248                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11249                                          hrxq_idx);
11250                         if (!hrxq) {
11251                                 rte_flow_error_set
11252                                         (error, rte_errno,
11253                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11254                                          "cannot get hash queue");
11255                                 goto error;
11256                         }
11257                         dh->rix_srss = rss_desc->shared_rss;
11258                         dv->actions[n++] = hrxq->action;
11259                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11260                         if (!priv->sh->default_miss_action) {
11261                                 rte_flow_error_set
11262                                         (error, rte_errno,
11263                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11264                                          "default miss action not be created.");
11265                                 goto error;
11266                         }
11267                         dv->actions[n++] = priv->sh->default_miss_action;
11268                 }
11269                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11270                                                (void *)&dv->value, n,
11271                                                dv->actions, &dh->drv_flow);
11272                 if (err) {
11273                         rte_flow_error_set(error, errno,
11274                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11275                                            NULL,
11276                                            "hardware refuses to create flow");
11277                         goto error;
11278                 }
11279                 if (priv->vmwa_context &&
11280                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
11281                         /*
11282                          * The rule contains the VLAN pattern.
11283                          * For VF we are going to create VLAN
11284                          * interface to make hypervisor set correct
11285                          * e-Switch vport context.
11286                          */
11287                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11288                 }
11289         }
11290         return 0;
11291 error:
11292         err = rte_errno; /* Save rte_errno before cleanup. */
11293         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11294                        handle_idx, dh, next) {
11295                 /* hrxq is union, don't clear it if the flag is not set. */
11296                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11297                         mlx5_hrxq_release(dev, dh->rix_hrxq);
11298                         dh->rix_hrxq = 0;
11299                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11300                         dh->rix_srss = 0;
11301                 }
11302                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11303                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11304         }
11305         rte_errno = err; /* Restore rte_errno. */
11306         return -rte_errno;
11307 }
11308
11309 void
11310 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11311                           struct mlx5_cache_entry *entry)
11312 {
11313         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11314                                                           entry);
11315
11316         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11317         mlx5_free(cache);
11318 }
11319
11320 /**
11321  * Release the flow matcher.
11322  *
11323  * @param dev
11324  *   Pointer to Ethernet device.
11325  * @param port_id
11326  *   Index to port ID action resource.
11327  *
11328  * @return
11329  *   1 while a reference on it exists, 0 when freed.
11330  */
11331 static int
11332 flow_dv_matcher_release(struct rte_eth_dev *dev,
11333                         struct mlx5_flow_handle *handle)
11334 {
11335         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11336         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11337                                                             typeof(*tbl), tbl);
11338         int ret;
11339
11340         MLX5_ASSERT(matcher->matcher_object);
11341         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11342         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11343         return ret;
11344 }
11345
11346 /**
11347  * Release encap_decap resource.
11348  *
11349  * @param list
11350  *   Pointer to the hash list.
11351  * @param entry
11352  *   Pointer to exist resource entry object.
11353  */
11354 void
11355 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11356                               struct mlx5_hlist_entry *entry)
11357 {
11358         struct mlx5_dev_ctx_shared *sh = list->ctx;
11359         struct mlx5_flow_dv_encap_decap_resource *res =
11360                 container_of(entry, typeof(*res), entry);
11361
11362         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11363         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11364 }
11365
11366 /**
11367  * Release an encap/decap resource.
11368  *
11369  * @param dev
11370  *   Pointer to Ethernet device.
11371  * @param encap_decap_idx
11372  *   Index of encap decap resource.
11373  *
11374  * @return
11375  *   1 while a reference on it exists, 0 when freed.
11376  */
11377 static int
11378 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11379                                      uint32_t encap_decap_idx)
11380 {
11381         struct mlx5_priv *priv = dev->data->dev_private;
11382         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11383
11384         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11385                                         encap_decap_idx);
11386         if (!cache_resource)
11387                 return 0;
11388         MLX5_ASSERT(cache_resource->action);
11389         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11390                                      &cache_resource->entry);
11391 }
11392
11393 /**
11394  * Release an jump to table action resource.
11395  *
11396  * @param dev
11397  *   Pointer to Ethernet device.
11398  * @param rix_jump
11399  *   Index to the jump action resource.
11400  *
11401  * @return
11402  *   1 while a reference on it exists, 0 when freed.
11403  */
11404 static int
11405 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11406                                   uint32_t rix_jump)
11407 {
11408         struct mlx5_priv *priv = dev->data->dev_private;
11409         struct mlx5_flow_tbl_data_entry *tbl_data;
11410
11411         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11412                                   rix_jump);
11413         if (!tbl_data)
11414                 return 0;
11415         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11416 }
11417
11418 void
11419 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11420                          struct mlx5_hlist_entry *entry)
11421 {
11422         struct mlx5_flow_dv_modify_hdr_resource *res =
11423                 container_of(entry, typeof(*res), entry);
11424
11425         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11426         mlx5_free(entry);
11427 }
11428
11429 /**
11430  * Release a modify-header resource.
11431  *
11432  * @param dev
11433  *   Pointer to Ethernet device.
11434  * @param handle
11435  *   Pointer to mlx5_flow_handle.
11436  *
11437  * @return
11438  *   1 while a reference on it exists, 0 when freed.
11439  */
11440 static int
11441 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11442                                     struct mlx5_flow_handle *handle)
11443 {
11444         struct mlx5_priv *priv = dev->data->dev_private;
11445         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11446
11447         MLX5_ASSERT(entry->action);
11448         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11449 }
11450
11451 void
11452 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11453                           struct mlx5_cache_entry *entry)
11454 {
11455         struct mlx5_dev_ctx_shared *sh = list->ctx;
11456         struct mlx5_flow_dv_port_id_action_resource *cache =
11457                         container_of(entry, typeof(*cache), entry);
11458
11459         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11460         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11461 }
11462
11463 /**
11464  * Release port ID action resource.
11465  *
11466  * @param dev
11467  *   Pointer to Ethernet device.
11468  * @param handle
11469  *   Pointer to mlx5_flow_handle.
11470  *
11471  * @return
11472  *   1 while a reference on it exists, 0 when freed.
11473  */
11474 static int
11475 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11476                                         uint32_t port_id)
11477 {
11478         struct mlx5_priv *priv = dev->data->dev_private;
11479         struct mlx5_flow_dv_port_id_action_resource *cache;
11480
11481         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11482         if (!cache)
11483                 return 0;
11484         MLX5_ASSERT(cache->action);
11485         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11486                                      &cache->entry);
11487 }
11488
11489 /**
11490  * Release shared RSS action resource.
11491  *
11492  * @param dev
11493  *   Pointer to Ethernet device.
11494  * @param srss
11495  *   Shared RSS action index.
11496  */
11497 static void
11498 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11499 {
11500         struct mlx5_priv *priv = dev->data->dev_private;
11501         struct mlx5_shared_action_rss *shared_rss;
11502
11503         shared_rss = mlx5_ipool_get
11504                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11505         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11506 }
11507
11508 void
11509 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11510                             struct mlx5_cache_entry *entry)
11511 {
11512         struct mlx5_dev_ctx_shared *sh = list->ctx;
11513         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11514                         container_of(entry, typeof(*cache), entry);
11515
11516         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11517         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11518 }
11519
11520 /**
11521  * Release push vlan action resource.
11522  *
11523  * @param dev
11524  *   Pointer to Ethernet device.
11525  * @param handle
11526  *   Pointer to mlx5_flow_handle.
11527  *
11528  * @return
11529  *   1 while a reference on it exists, 0 when freed.
11530  */
11531 static int
11532 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11533                                           struct mlx5_flow_handle *handle)
11534 {
11535         struct mlx5_priv *priv = dev->data->dev_private;
11536         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11537         uint32_t idx = handle->dvh.rix_push_vlan;
11538
11539         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11540         if (!cache)
11541                 return 0;
11542         MLX5_ASSERT(cache->action);
11543         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11544                                      &cache->entry);
11545 }
11546
11547 /**
11548  * Release the fate resource.
11549  *
11550  * @param dev
11551  *   Pointer to Ethernet device.
11552  * @param handle
11553  *   Pointer to mlx5_flow_handle.
11554  */
11555 static void
11556 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11557                                struct mlx5_flow_handle *handle)
11558 {
11559         if (!handle->rix_fate)
11560                 return;
11561         switch (handle->fate_action) {
11562         case MLX5_FLOW_FATE_QUEUE:
11563                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11564                 break;
11565         case MLX5_FLOW_FATE_JUMP:
11566                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
11567                 break;
11568         case MLX5_FLOW_FATE_PORT_ID:
11569                 flow_dv_port_id_action_resource_release(dev,
11570                                 handle->rix_port_id_action);
11571                 break;
11572         default:
11573                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11574                 break;
11575         }
11576         handle->rix_fate = 0;
11577 }
11578
11579 void
11580 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11581                          struct mlx5_cache_entry *entry)
11582 {
11583         struct mlx5_flow_dv_sample_resource *cache_resource =
11584                         container_of(entry, typeof(*cache_resource), entry);
11585         struct rte_eth_dev *dev = cache_resource->dev;
11586         struct mlx5_priv *priv = dev->data->dev_private;
11587
11588         if (cache_resource->verbs_action)
11589                 claim_zero(mlx5_flow_os_destroy_flow_action
11590                                 (cache_resource->verbs_action));
11591         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11592                 if (cache_resource->default_miss)
11593                         claim_zero(mlx5_flow_os_destroy_flow_action
11594                           (cache_resource->default_miss));
11595         }
11596         if (cache_resource->normal_path_tbl)
11597                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11598                         cache_resource->normal_path_tbl);
11599         flow_dv_sample_sub_actions_release(dev,
11600                                 &cache_resource->sample_idx);
11601         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11602                         cache_resource->idx);
11603         DRV_LOG(DEBUG, "sample resource %p: removed",
11604                 (void *)cache_resource);
11605 }
11606
11607 /**
11608  * Release an sample resource.
11609  *
11610  * @param dev
11611  *   Pointer to Ethernet device.
11612  * @param handle
11613  *   Pointer to mlx5_flow_handle.
11614  *
11615  * @return
11616  *   1 while a reference on it exists, 0 when freed.
11617  */
11618 static int
11619 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11620                                      struct mlx5_flow_handle *handle)
11621 {
11622         struct mlx5_priv *priv = dev->data->dev_private;
11623         struct mlx5_flow_dv_sample_resource *cache_resource;
11624
11625         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11626                          handle->dvh.rix_sample);
11627         if (!cache_resource)
11628                 return 0;
11629         MLX5_ASSERT(cache_resource->verbs_action);
11630         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11631                                      &cache_resource->entry);
11632 }
11633
11634 void
11635 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11636                              struct mlx5_cache_entry *entry)
11637 {
11638         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11639                         container_of(entry, typeof(*cache_resource), entry);
11640         struct rte_eth_dev *dev = cache_resource->dev;
11641         struct mlx5_priv *priv = dev->data->dev_private;
11642         uint32_t i = 0;
11643
11644         MLX5_ASSERT(cache_resource->action);
11645         if (cache_resource->action)
11646                 claim_zero(mlx5_flow_os_destroy_flow_action
11647                                         (cache_resource->action));
11648         for (; i < cache_resource->num_of_dest; i++)
11649                 flow_dv_sample_sub_actions_release(dev,
11650                                 &cache_resource->sample_idx[i]);
11651         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11652                         cache_resource->idx);
11653         DRV_LOG(DEBUG, "destination array resource %p: removed",
11654                 (void *)cache_resource);
11655 }
11656
11657 /**
11658  * Release an destination array resource.
11659  *
11660  * @param dev
11661  *   Pointer to Ethernet device.
11662  * @param handle
11663  *   Pointer to mlx5_flow_handle.
11664  *
11665  * @return
11666  *   1 while a reference on it exists, 0 when freed.
11667  */
11668 static int
11669 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11670                                     struct mlx5_flow_handle *handle)
11671 {
11672         struct mlx5_priv *priv = dev->data->dev_private;
11673         struct mlx5_flow_dv_dest_array_resource *cache;
11674
11675         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11676                                handle->dvh.rix_dest_array);
11677         if (!cache)
11678                 return 0;
11679         MLX5_ASSERT(cache->action);
11680         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11681                                      &cache->entry);
11682 }
11683
11684 static void
11685 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11686 {
11687         struct mlx5_priv *priv = dev->data->dev_private;
11688         struct mlx5_dev_ctx_shared *sh = priv->sh;
11689         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11690                                 sh->geneve_tlv_option_resource;
11691         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11692         if (geneve_opt_resource) {
11693                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11694                                          __ATOMIC_RELAXED))) {
11695                         claim_zero(mlx5_devx_cmd_destroy
11696                                         (geneve_opt_resource->obj));
11697                         mlx5_free(sh->geneve_tlv_option_resource);
11698                         sh->geneve_tlv_option_resource = NULL;
11699                 }
11700         }
11701         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11702 }
11703
11704 /**
11705  * Remove the flow from the NIC but keeps it in memory.
11706  * Lock free, (mutex should be acquired by caller).
11707  *
11708  * @param[in] dev
11709  *   Pointer to Ethernet device.
11710  * @param[in, out] flow
11711  *   Pointer to flow structure.
11712  */
11713 static void
11714 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11715 {
11716         struct mlx5_flow_handle *dh;
11717         uint32_t handle_idx;
11718         struct mlx5_priv *priv = dev->data->dev_private;
11719
11720         if (!flow)
11721                 return;
11722         handle_idx = flow->dev_handles;
11723         while (handle_idx) {
11724                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11725                                     handle_idx);
11726                 if (!dh)
11727                         return;
11728                 if (dh->drv_flow) {
11729                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11730                         dh->drv_flow = NULL;
11731                 }
11732                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11733                         flow_dv_fate_resource_release(dev, dh);
11734                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11735                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11736                 handle_idx = dh->next.next;
11737         }
11738 }
11739
11740 /**
11741  * Remove the flow from the NIC and the memory.
11742  * Lock free, (mutex should be acquired by caller).
11743  *
11744  * @param[in] dev
11745  *   Pointer to the Ethernet device structure.
11746  * @param[in, out] flow
11747  *   Pointer to flow structure.
11748  */
11749 static void
11750 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11751 {
11752         struct mlx5_flow_handle *dev_handle;
11753         struct mlx5_priv *priv = dev->data->dev_private;
11754         uint32_t srss = 0;
11755
11756         if (!flow)
11757                 return;
11758         flow_dv_remove(dev, flow);
11759         if (flow->counter) {
11760                 flow_dv_counter_free(dev, flow->counter);
11761                 flow->counter = 0;
11762         }
11763         if (flow->meter) {
11764                 struct mlx5_flow_meter *fm;
11765
11766                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11767                                     flow->meter);
11768                 if (fm)
11769                         mlx5_flow_meter_detach(fm);
11770                 flow->meter = 0;
11771         }
11772         if (flow->age)
11773                 flow_dv_aso_age_release(dev, flow->age);
11774         if (flow->geneve_tlv_option) {
11775                 flow_dv_geneve_tlv_option_resource_release(dev);
11776                 flow->geneve_tlv_option = 0;
11777         }
11778         while (flow->dev_handles) {
11779                 uint32_t tmp_idx = flow->dev_handles;
11780
11781                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11782                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11783                 if (!dev_handle)
11784                         return;
11785                 flow->dev_handles = dev_handle->next.next;
11786                 if (dev_handle->dvh.matcher)
11787                         flow_dv_matcher_release(dev, dev_handle);
11788                 if (dev_handle->dvh.rix_sample)
11789                         flow_dv_sample_resource_release(dev, dev_handle);
11790                 if (dev_handle->dvh.rix_dest_array)
11791                         flow_dv_dest_array_resource_release(dev, dev_handle);
11792                 if (dev_handle->dvh.rix_encap_decap)
11793                         flow_dv_encap_decap_resource_release(dev,
11794                                 dev_handle->dvh.rix_encap_decap);
11795                 if (dev_handle->dvh.modify_hdr)
11796                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11797                 if (dev_handle->dvh.rix_push_vlan)
11798                         flow_dv_push_vlan_action_resource_release(dev,
11799                                                                   dev_handle);
11800                 if (dev_handle->dvh.rix_tag)
11801                         flow_dv_tag_release(dev,
11802                                             dev_handle->dvh.rix_tag);
11803                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11804                         flow_dv_fate_resource_release(dev, dev_handle);
11805                 else if (!srss)
11806                         srss = dev_handle->rix_srss;
11807                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11808                            tmp_idx);
11809         }
11810         if (srss)
11811                 flow_dv_shared_rss_action_release(dev, srss);
11812 }
11813
11814 /**
11815  * Release array of hash RX queue objects.
11816  * Helper function.
11817  *
11818  * @param[in] dev
11819  *   Pointer to the Ethernet device structure.
11820  * @param[in, out] hrxqs
11821  *   Array of hash RX queue objects.
11822  *
11823  * @return
11824  *   Total number of references to hash RX queue objects in *hrxqs* array
11825  *   after this operation.
11826  */
11827 static int
11828 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11829                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11830 {
11831         size_t i;
11832         int remaining = 0;
11833
11834         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11835                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11836
11837                 if (!ret)
11838                         (*hrxqs)[i] = 0;
11839                 remaining += ret;
11840         }
11841         return remaining;
11842 }
11843
11844 /**
11845  * Release all hash RX queue objects representing shared RSS action.
11846  *
11847  * @param[in] dev
11848  *   Pointer to the Ethernet device structure.
11849  * @param[in, out] action
11850  *   Shared RSS action to remove hash RX queue objects from.
11851  *
11852  * @return
11853  *   Total number of references to hash RX queue objects stored in *action*
11854  *   after this operation.
11855  *   Expected to be 0 if no external references held.
11856  */
11857 static int
11858 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11859                                  struct mlx5_shared_action_rss *action)
11860 {
11861         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11862                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11863 }
11864
11865 /**
11866  * Setup shared RSS action.
11867  * Prepare set of hash RX queue objects sufficient to handle all valid
11868  * hash_fields combinations (see enum ibv_rx_hash_fields).
11869  *
11870  * @param[in] dev
11871  *   Pointer to the Ethernet device structure.
11872  * @param[in] action_idx
11873  *   Shared RSS action ipool index.
11874  * @param[in, out] action
11875  *   Partially initialized shared RSS action.
11876  * @param[out] error
11877  *   Perform verbose error reporting if not NULL. Initialized in case of
11878  *   error only.
11879  *
11880  * @return
11881  *   0 on success, otherwise negative errno value.
11882  */
11883 static int
11884 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11885                            uint32_t action_idx,
11886                            struct mlx5_shared_action_rss *action,
11887                            struct rte_flow_error *error)
11888 {
11889         struct mlx5_flow_rss_desc rss_desc = { 0 };
11890         size_t i;
11891         int err;
11892
11893         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11894                 return rte_flow_error_set(error, rte_errno,
11895                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11896                                           "cannot setup indirection table");
11897         }
11898         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11899         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11900         rss_desc.const_q = action->origin.queue;
11901         rss_desc.queue_num = action->origin.queue_num;
11902         /* Set non-zero value to indicate a shared RSS. */
11903         rss_desc.shared_rss = action_idx;
11904         rss_desc.ind_tbl = action->ind_tbl;
11905         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11906                 uint32_t hrxq_idx;
11907                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11908                 int tunnel;
11909
11910                 for (tunnel = 0; tunnel < 2; tunnel++) {
11911                         rss_desc.tunnel = tunnel;
11912                         rss_desc.hash_fields = hash_fields;
11913                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11914                         if (!hrxq_idx) {
11915                                 rte_flow_error_set
11916                                         (error, rte_errno,
11917                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11918                                          "cannot get hash queue");
11919                                 goto error_hrxq_new;
11920                         }
11921                         err = __flow_dv_action_rss_hrxq_set
11922                                 (action, hash_fields, tunnel, hrxq_idx);
11923                         MLX5_ASSERT(!err);
11924                 }
11925         }
11926         return 0;
11927 error_hrxq_new:
11928         err = rte_errno;
11929         __flow_dv_action_rss_hrxqs_release(dev, action);
11930         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11931                 action->ind_tbl = NULL;
11932         rte_errno = err;
11933         return -rte_errno;
11934 }
11935
11936 /**
11937  * Create shared RSS action.
11938  *
11939  * @param[in] dev
11940  *   Pointer to the Ethernet device structure.
11941  * @param[in] conf
11942  *   Shared action configuration.
11943  * @param[in] rss
11944  *   RSS action specification used to create shared action.
11945  * @param[out] error
11946  *   Perform verbose error reporting if not NULL. Initialized in case of
11947  *   error only.
11948  *
11949  * @return
11950  *   A valid shared action ID in case of success, 0 otherwise and
11951  *   rte_errno is set.
11952  */
11953 static uint32_t
11954 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11955                             const struct rte_flow_shared_action_conf *conf,
11956                             const struct rte_flow_action_rss *rss,
11957                             struct rte_flow_error *error)
11958 {
11959         struct mlx5_priv *priv = dev->data->dev_private;
11960         struct mlx5_shared_action_rss *shared_action = NULL;
11961         void *queue = NULL;
11962         struct rte_flow_action_rss *origin;
11963         const uint8_t *rss_key;
11964         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11965         uint32_t idx;
11966
11967         RTE_SET_USED(conf);
11968         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11969                             0, SOCKET_ID_ANY);
11970         shared_action = mlx5_ipool_zmalloc
11971                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11972         if (!shared_action || !queue) {
11973                 rte_flow_error_set(error, ENOMEM,
11974                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11975                                    "cannot allocate resource memory");
11976                 goto error_rss_init;
11977         }
11978         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11979                 rte_flow_error_set(error, E2BIG,
11980                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11981                                    "rss action number out of range");
11982                 goto error_rss_init;
11983         }
11984         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11985                                              sizeof(*shared_action->ind_tbl),
11986                                              0, SOCKET_ID_ANY);
11987         if (!shared_action->ind_tbl) {
11988                 rte_flow_error_set(error, ENOMEM,
11989                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11990                                    "cannot allocate resource memory");
11991                 goto error_rss_init;
11992         }
11993         memcpy(queue, rss->queue, queue_size);
11994         shared_action->ind_tbl->queues = queue;
11995         shared_action->ind_tbl->queues_n = rss->queue_num;
11996         origin = &shared_action->origin;
11997         origin->func = rss->func;
11998         origin->level = rss->level;
11999         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12000         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12001         /* NULL RSS key indicates default RSS key. */
12002         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12003         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12004         origin->key = &shared_action->key[0];
12005         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12006         origin->queue = queue;
12007         origin->queue_num = rss->queue_num;
12008         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
12009                 goto error_rss_init;
12010         rte_spinlock_init(&shared_action->action_rss_sl);
12011         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
12012         rte_spinlock_lock(&priv->shared_act_sl);
12013         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12014                      &priv->rss_shared_actions, idx, shared_action, next);
12015         rte_spinlock_unlock(&priv->shared_act_sl);
12016         return idx;
12017 error_rss_init:
12018         if (shared_action) {
12019                 if (shared_action->ind_tbl)
12020                         mlx5_free(shared_action->ind_tbl);
12021                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12022                                 idx);
12023         }
12024         if (queue)
12025                 mlx5_free(queue);
12026         return 0;
12027 }
12028
12029 /**
12030  * Destroy the shared RSS action.
12031  * Release related hash RX queue objects.
12032  *
12033  * @param[in] dev
12034  *   Pointer to the Ethernet device structure.
12035  * @param[in] idx
12036  *   The shared RSS action object ID to be removed.
12037  * @param[out] error
12038  *   Perform verbose error reporting if not NULL. Initialized in case of
12039  *   error only.
12040  *
12041  * @return
12042  *   0 on success, otherwise negative errno value.
12043  */
12044 static int
12045 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12046                              struct rte_flow_error *error)
12047 {
12048         struct mlx5_priv *priv = dev->data->dev_private;
12049         struct mlx5_shared_action_rss *shared_rss =
12050             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12051         uint32_t old_refcnt = 1;
12052         int remaining;
12053         uint16_t *queue = NULL;
12054
12055         if (!shared_rss)
12056                 return rte_flow_error_set(error, EINVAL,
12057                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12058                                           "invalid shared action");
12059         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12060         if (remaining)
12061                 return rte_flow_error_set(error, EBUSY,
12062                                           RTE_FLOW_ERROR_TYPE_ACTION,
12063                                           NULL,
12064                                           "shared rss hrxq has references");
12065         queue = shared_rss->ind_tbl->queues;
12066         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12067         if (remaining)
12068                 return rte_flow_error_set(error, EBUSY,
12069                                           RTE_FLOW_ERROR_TYPE_ACTION,
12070                                           NULL,
12071                                           "shared rss indirection table has"
12072                                           " references");
12073         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12074                                          0, 0, __ATOMIC_ACQUIRE,
12075                                          __ATOMIC_RELAXED))
12076                 return rte_flow_error_set(error, EBUSY,
12077                                           RTE_FLOW_ERROR_TYPE_ACTION,
12078                                           NULL,
12079                                           "shared rss has references");
12080         mlx5_free(queue);
12081         rte_spinlock_lock(&priv->shared_act_sl);
12082         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12083                      &priv->rss_shared_actions, idx, shared_rss, next);
12084         rte_spinlock_unlock(&priv->shared_act_sl);
12085         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12086                         idx);
12087         return 0;
12088 }
12089
12090 /**
12091  * Create shared action, lock free,
12092  * (mutex should be acquired by caller).
12093  * Dispatcher for action type specific call.
12094  *
12095  * @param[in] dev
12096  *   Pointer to the Ethernet device structure.
12097  * @param[in] conf
12098  *   Shared action configuration.
12099  * @param[in] action
12100  *   Action specification used to create shared action.
12101  * @param[out] error
12102  *   Perform verbose error reporting if not NULL. Initialized in case of
12103  *   error only.
12104  *
12105  * @return
12106  *   A valid shared action handle in case of success, NULL otherwise and
12107  *   rte_errno is set.
12108  */
12109 static struct rte_flow_shared_action *
12110 flow_dv_action_create(struct rte_eth_dev *dev,
12111                       const struct rte_flow_shared_action_conf *conf,
12112                       const struct rte_flow_action *action,
12113                       struct rte_flow_error *err)
12114 {
12115         uint32_t idx = 0;
12116         uint32_t ret = 0;
12117
12118         switch (action->type) {
12119         case RTE_FLOW_ACTION_TYPE_RSS:
12120                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12121                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12122                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12123                 break;
12124         case RTE_FLOW_ACTION_TYPE_AGE:
12125                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12126                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12127                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12128                 if (ret) {
12129                         struct mlx5_aso_age_action *aso_age =
12130                                               flow_aso_age_get_by_idx(dev, ret);
12131
12132                         if (!aso_age->age_params.context)
12133                                 aso_age->age_params.context =
12134                                                          (void *)(uintptr_t)idx;
12135                 }
12136                 break;
12137         default:
12138                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12139                                    NULL, "action type not supported");
12140                 break;
12141         }
12142         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12143 }
12144
12145 /**
12146  * Destroy the shared action.
12147  * Release action related resources on the NIC and the memory.
12148  * Lock free, (mutex should be acquired by caller).
12149  * Dispatcher for action type specific call.
12150  *
12151  * @param[in] dev
12152  *   Pointer to the Ethernet device structure.
12153  * @param[in] action
12154  *   The shared action object to be removed.
12155  * @param[out] error
12156  *   Perform verbose error reporting if not NULL. Initialized in case of
12157  *   error only.
12158  *
12159  * @return
12160  *   0 on success, otherwise negative errno value.
12161  */
12162 static int
12163 flow_dv_action_destroy(struct rte_eth_dev *dev,
12164                        struct rte_flow_shared_action *action,
12165                        struct rte_flow_error *error)
12166 {
12167         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12168         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12169         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12170         int ret;
12171
12172         switch (type) {
12173         case MLX5_SHARED_ACTION_TYPE_RSS:
12174                 return __flow_dv_action_rss_release(dev, idx, error);
12175         case MLX5_SHARED_ACTION_TYPE_AGE:
12176                 ret = flow_dv_aso_age_release(dev, idx);
12177                 if (ret)
12178                         /*
12179                          * In this case, the last flow has a reference will
12180                          * actually release the age action.
12181                          */
12182                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12183                                 " released with references %d.", idx, ret);
12184                 return 0;
12185         default:
12186                 return rte_flow_error_set(error, ENOTSUP,
12187                                           RTE_FLOW_ERROR_TYPE_ACTION,
12188                                           NULL,
12189                                           "action type not supported");
12190         }
12191 }
12192
12193 /**
12194  * Updates in place shared RSS action configuration.
12195  *
12196  * @param[in] dev
12197  *   Pointer to the Ethernet device structure.
12198  * @param[in] idx
12199  *   The shared RSS action object ID to be updated.
12200  * @param[in] action_conf
12201  *   RSS action specification used to modify *shared_rss*.
12202  * @param[out] error
12203  *   Perform verbose error reporting if not NULL. Initialized in case of
12204  *   error only.
12205  *
12206  * @return
12207  *   0 on success, otherwise negative errno value.
12208  * @note: currently only support update of RSS queues.
12209  */
12210 static int
12211 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12212                             const struct rte_flow_action_rss *action_conf,
12213                             struct rte_flow_error *error)
12214 {
12215         struct mlx5_priv *priv = dev->data->dev_private;
12216         struct mlx5_shared_action_rss *shared_rss =
12217             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12218         int ret = 0;
12219         void *queue = NULL;
12220         uint16_t *queue_old = NULL;
12221         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12222
12223         if (!shared_rss)
12224                 return rte_flow_error_set(error, EINVAL,
12225                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12226                                           "invalid shared action to update");
12227         queue = mlx5_malloc(MLX5_MEM_ZERO,
12228                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12229                             0, SOCKET_ID_ANY);
12230         if (!queue)
12231                 return rte_flow_error_set(error, ENOMEM,
12232                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12233                                           NULL,
12234                                           "cannot allocate resource memory");
12235         memcpy(queue, action_conf->queue, queue_size);
12236         MLX5_ASSERT(shared_rss->ind_tbl);
12237         rte_spinlock_lock(&shared_rss->action_rss_sl);
12238         queue_old = shared_rss->ind_tbl->queues;
12239         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12240                                         queue, action_conf->queue_num, true);
12241         if (ret) {
12242                 mlx5_free(queue);
12243                 ret = rte_flow_error_set(error, rte_errno,
12244                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12245                                           "cannot update indirection table");
12246         } else {
12247                 mlx5_free(queue_old);
12248                 shared_rss->origin.queue = queue;
12249                 shared_rss->origin.queue_num = action_conf->queue_num;
12250         }
12251         rte_spinlock_unlock(&shared_rss->action_rss_sl);
12252         return ret;
12253 }
12254
12255 /**
12256  * Updates in place shared action configuration, lock free,
12257  * (mutex should be acquired by caller).
12258  *
12259  * @param[in] dev
12260  *   Pointer to the Ethernet device structure.
12261  * @param[in] action
12262  *   The shared action object to be updated.
12263  * @param[in] action_conf
12264  *   Action specification used to modify *action*.
12265  *   *action_conf* should be of type correlating with type of the *action*,
12266  *   otherwise considered as invalid.
12267  * @param[out] error
12268  *   Perform verbose error reporting if not NULL. Initialized in case of
12269  *   error only.
12270  *
12271  * @return
12272  *   0 on success, otherwise negative errno value.
12273  */
12274 static int
12275 flow_dv_action_update(struct rte_eth_dev *dev,
12276                         struct rte_flow_shared_action *action,
12277                         const void *action_conf,
12278                         struct rte_flow_error *err)
12279 {
12280         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12281         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12282         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12283
12284         switch (type) {
12285         case MLX5_SHARED_ACTION_TYPE_RSS:
12286                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12287         default:
12288                 return rte_flow_error_set(err, ENOTSUP,
12289                                           RTE_FLOW_ERROR_TYPE_ACTION,
12290                                           NULL,
12291                                           "action type update not supported");
12292         }
12293 }
12294
12295 static int
12296 flow_dv_action_query(struct rte_eth_dev *dev,
12297                      const struct rte_flow_shared_action *action, void *data,
12298                      struct rte_flow_error *error)
12299 {
12300         struct mlx5_age_param *age_param;
12301         struct rte_flow_query_age *resp;
12302         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12303         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12304         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12305
12306         switch (type) {
12307         case MLX5_SHARED_ACTION_TYPE_AGE:
12308                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12309                 resp = data;
12310                 resp->aged = __atomic_load_n(&age_param->state,
12311                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
12312                                                                           1 : 0;
12313                 resp->sec_since_last_hit_valid = !resp->aged;
12314                 if (resp->sec_since_last_hit_valid)
12315                         resp->sec_since_last_hit = __atomic_load_n
12316                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12317                 return 0;
12318         default:
12319                 return rte_flow_error_set(error, ENOTSUP,
12320                                           RTE_FLOW_ERROR_TYPE_ACTION,
12321                                           NULL,
12322                                           "action type query not supported");
12323         }
12324 }
12325
12326 /**
12327  * Query a dv flow  rule for its statistics via devx.
12328  *
12329  * @param[in] dev
12330  *   Pointer to Ethernet device.
12331  * @param[in] flow
12332  *   Pointer to the sub flow.
12333  * @param[out] data
12334  *   data retrieved by the query.
12335  * @param[out] error
12336  *   Perform verbose error reporting if not NULL.
12337  *
12338  * @return
12339  *   0 on success, a negative errno value otherwise and rte_errno is set.
12340  */
12341 static int
12342 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12343                     void *data, struct rte_flow_error *error)
12344 {
12345         struct mlx5_priv *priv = dev->data->dev_private;
12346         struct rte_flow_query_count *qc = data;
12347
12348         if (!priv->config.devx)
12349                 return rte_flow_error_set(error, ENOTSUP,
12350                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12351                                           NULL,
12352                                           "counters are not supported");
12353         if (flow->counter) {
12354                 uint64_t pkts, bytes;
12355                 struct mlx5_flow_counter *cnt;
12356
12357                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12358                                                  NULL);
12359                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12360                                                &bytes);
12361
12362                 if (err)
12363                         return rte_flow_error_set(error, -err,
12364                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12365                                         NULL, "cannot read counters");
12366                 qc->hits_set = 1;
12367                 qc->bytes_set = 1;
12368                 qc->hits = pkts - cnt->hits;
12369                 qc->bytes = bytes - cnt->bytes;
12370                 if (qc->reset) {
12371                         cnt->hits = pkts;
12372                         cnt->bytes = bytes;
12373                 }
12374                 return 0;
12375         }
12376         return rte_flow_error_set(error, EINVAL,
12377                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12378                                   NULL,
12379                                   "counters are not available");
12380 }
12381
12382 /**
12383  * Query a flow rule AGE action for aging information.
12384  *
12385  * @param[in] dev
12386  *   Pointer to Ethernet device.
12387  * @param[in] flow
12388  *   Pointer to the sub flow.
12389  * @param[out] data
12390  *   data retrieved by the query.
12391  * @param[out] error
12392  *   Perform verbose error reporting if not NULL.
12393  *
12394  * @return
12395  *   0 on success, a negative errno value otherwise and rte_errno is set.
12396  */
12397 static int
12398 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12399                   void *data, struct rte_flow_error *error)
12400 {
12401         struct rte_flow_query_age *resp = data;
12402         struct mlx5_age_param *age_param;
12403
12404         if (flow->age) {
12405                 struct mlx5_aso_age_action *act =
12406                                      flow_aso_age_get_by_idx(dev, flow->age);
12407
12408                 age_param = &act->age_params;
12409         } else if (flow->counter) {
12410                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12411
12412                 if (!age_param || !age_param->timeout)
12413                         return rte_flow_error_set
12414                                         (error, EINVAL,
12415                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12416                                          NULL, "cannot read age data");
12417         } else {
12418                 return rte_flow_error_set(error, EINVAL,
12419                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12420                                           NULL, "age data not available");
12421         }
12422         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12423                                      AGE_TMOUT ? 1 : 0;
12424         resp->sec_since_last_hit_valid = !resp->aged;
12425         if (resp->sec_since_last_hit_valid)
12426                 resp->sec_since_last_hit = __atomic_load_n
12427                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12428         return 0;
12429 }
12430
12431 /**
12432  * Query a flow.
12433  *
12434  * @see rte_flow_query()
12435  * @see rte_flow_ops
12436  */
12437 static int
12438 flow_dv_query(struct rte_eth_dev *dev,
12439               struct rte_flow *flow __rte_unused,
12440               const struct rte_flow_action *actions __rte_unused,
12441               void *data __rte_unused,
12442               struct rte_flow_error *error __rte_unused)
12443 {
12444         int ret = -EINVAL;
12445
12446         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12447                 switch (actions->type) {
12448                 case RTE_FLOW_ACTION_TYPE_VOID:
12449                         break;
12450                 case RTE_FLOW_ACTION_TYPE_COUNT:
12451                         ret = flow_dv_query_count(dev, flow, data, error);
12452                         break;
12453                 case RTE_FLOW_ACTION_TYPE_AGE:
12454                         ret = flow_dv_query_age(dev, flow, data, error);
12455                         break;
12456                 default:
12457                         return rte_flow_error_set(error, ENOTSUP,
12458                                                   RTE_FLOW_ERROR_TYPE_ACTION,
12459                                                   actions,
12460                                                   "action not supported");
12461                 }
12462         }
12463         return ret;
12464 }
12465
12466 /**
12467  * Destroy the meter table set.
12468  * Lock free, (mutex should be acquired by caller).
12469  *
12470  * @param[in] dev
12471  *   Pointer to Ethernet device.
12472  * @param[in] tbl
12473  *   Pointer to the meter table set.
12474  *
12475  * @return
12476  *   Always 0.
12477  */
12478 static int
12479 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12480                         struct mlx5_meter_domains_infos *tbl)
12481 {
12482         struct mlx5_priv *priv = dev->data->dev_private;
12483         struct mlx5_meter_domains_infos *mtd =
12484                                 (struct mlx5_meter_domains_infos *)tbl;
12485
12486         if (!mtd || !priv->config.dv_flow_en)
12487                 return 0;
12488         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12489                 claim_zero(mlx5_flow_os_destroy_flow
12490                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12491         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12492                 claim_zero(mlx5_flow_os_destroy_flow
12493                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12494         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12495                 claim_zero(mlx5_flow_os_destroy_flow
12496                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12497         if (mtd->egress.color_matcher)
12498                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12499                            (mtd->egress.color_matcher));
12500         if (mtd->egress.any_matcher)
12501                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12502                            (mtd->egress.any_matcher));
12503         if (mtd->egress.tbl)
12504                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12505         if (mtd->egress.sfx_tbl)
12506                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12507         if (mtd->ingress.color_matcher)
12508                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12509                            (mtd->ingress.color_matcher));
12510         if (mtd->ingress.any_matcher)
12511                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12512                            (mtd->ingress.any_matcher));
12513         if (mtd->ingress.tbl)
12514                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12515         if (mtd->ingress.sfx_tbl)
12516                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12517                                              mtd->ingress.sfx_tbl);
12518         if (mtd->transfer.color_matcher)
12519                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12520                            (mtd->transfer.color_matcher));
12521         if (mtd->transfer.any_matcher)
12522                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12523                            (mtd->transfer.any_matcher));
12524         if (mtd->transfer.tbl)
12525                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12526         if (mtd->transfer.sfx_tbl)
12527                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12528                                              mtd->transfer.sfx_tbl);
12529         if (mtd->drop_actn)
12530                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12531         mlx5_free(mtd);
12532         return 0;
12533 }
12534
12535 /* Number of meter flow actions, count and jump or count and drop. */
12536 #define METER_ACTIONS 2
12537
12538 /**
12539  * Create specify domain meter table and suffix table.
12540  *
12541  * @param[in] dev
12542  *   Pointer to Ethernet device.
12543  * @param[in,out] mtb
12544  *   Pointer to DV meter table set.
12545  * @param[in] egress
12546  *   Table attribute.
12547  * @param[in] transfer
12548  *   Table attribute.
12549  * @param[in] color_reg_c_idx
12550  *   Reg C index for color match.
12551  *
12552  * @return
12553  *   0 on success, -1 otherwise and rte_errno is set.
12554  */
12555 static int
12556 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12557                            struct mlx5_meter_domains_infos *mtb,
12558                            uint8_t egress, uint8_t transfer,
12559                            uint32_t color_reg_c_idx)
12560 {
12561         struct mlx5_priv *priv = dev->data->dev_private;
12562         struct mlx5_dev_ctx_shared *sh = priv->sh;
12563         struct mlx5_flow_dv_match_params mask = {
12564                 .size = sizeof(mask.buf),
12565         };
12566         struct mlx5_flow_dv_match_params value = {
12567                 .size = sizeof(value.buf),
12568         };
12569         struct mlx5dv_flow_matcher_attr dv_attr = {
12570                 .type = IBV_FLOW_ATTR_NORMAL,
12571                 .priority = 0,
12572                 .match_criteria_enable = 0,
12573                 .match_mask = (void *)&mask,
12574         };
12575         void *actions[METER_ACTIONS];
12576         struct mlx5_meter_domain_info *dtb;
12577         struct rte_flow_error error;
12578         int i = 0;
12579         int ret;
12580
12581         if (transfer)
12582                 dtb = &mtb->transfer;
12583         else if (egress)
12584                 dtb = &mtb->egress;
12585         else
12586                 dtb = &mtb->ingress;
12587         /* Create the meter table with METER level. */
12588         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12589                                             egress, transfer, false, NULL, 0,
12590                                             0, &error);
12591         if (!dtb->tbl) {
12592                 DRV_LOG(ERR, "Failed to create meter policer table.");
12593                 return -1;
12594         }
12595         /* Create the meter suffix table with SUFFIX level. */
12596         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12597                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12598                                             egress, transfer, false, NULL, 0,
12599                                             0, &error);
12600         if (!dtb->sfx_tbl) {
12601                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12602                 return -1;
12603         }
12604         /* Create matchers, Any and Color. */
12605         dv_attr.priority = 3;
12606         dv_attr.match_criteria_enable = 0;
12607         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12608                                                &dtb->any_matcher);
12609         if (ret) {
12610                 DRV_LOG(ERR, "Failed to create meter"
12611                              " policer default matcher.");
12612                 goto error_exit;
12613         }
12614         dv_attr.priority = 0;
12615         dv_attr.match_criteria_enable =
12616                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12617         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12618                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12619         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12620                                                &dtb->color_matcher);
12621         if (ret) {
12622                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12623                 goto error_exit;
12624         }
12625         if (mtb->count_actns[RTE_MTR_DROPPED])
12626                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12627         actions[i++] = mtb->drop_actn;
12628         /* Default rule: lowest priority, match any, actions: drop. */
12629         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12630                                        actions,
12631                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12632         if (ret) {
12633                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12634                 goto error_exit;
12635         }
12636         return 0;
12637 error_exit:
12638         return -1;
12639 }
12640
12641 /**
12642  * Create the needed meter and suffix tables.
12643  * Lock free, (mutex should be acquired by caller).
12644  *
12645  * @param[in] dev
12646  *   Pointer to Ethernet device.
12647  * @param[in] fm
12648  *   Pointer to the flow meter.
12649  *
12650  * @return
12651  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12652  */
12653 static struct mlx5_meter_domains_infos *
12654 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12655                        const struct mlx5_flow_meter *fm)
12656 {
12657         struct mlx5_priv *priv = dev->data->dev_private;
12658         struct mlx5_meter_domains_infos *mtb;
12659         int ret;
12660         int i;
12661
12662         if (!priv->mtr_en) {
12663                 rte_errno = ENOTSUP;
12664                 return NULL;
12665         }
12666         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12667         if (!mtb) {
12668                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12669                 return NULL;
12670         }
12671         /* Create meter count actions */
12672         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12673                 struct mlx5_flow_counter *cnt;
12674                 if (!fm->policer_stats.cnt[i])
12675                         continue;
12676                 cnt = flow_dv_counter_get_by_idx(dev,
12677                       fm->policer_stats.cnt[i], NULL);
12678                 mtb->count_actns[i] = cnt->action;
12679         }
12680         /* Create drop action. */
12681         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12682         if (ret) {
12683                 DRV_LOG(ERR, "Failed to create drop action.");
12684                 goto error_exit;
12685         }
12686         /* Egress meter table. */
12687         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12688         if (ret) {
12689                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12690                 goto error_exit;
12691         }
12692         /* Ingress meter table. */
12693         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12694         if (ret) {
12695                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12696                 goto error_exit;
12697         }
12698         /* FDB meter table. */
12699         if (priv->config.dv_esw_en) {
12700                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12701                                                  priv->mtr_color_reg);
12702                 if (ret) {
12703                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12704                         goto error_exit;
12705                 }
12706         }
12707         return mtb;
12708 error_exit:
12709         flow_dv_destroy_mtr_tbl(dev, mtb);
12710         return NULL;
12711 }
12712
12713 /**
12714  * Destroy domain policer rule.
12715  *
12716  * @param[in] dt
12717  *   Pointer to domain table.
12718  */
12719 static void
12720 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12721 {
12722         int i;
12723
12724         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12725                 if (dt->policer_rules[i]) {
12726                         claim_zero(mlx5_flow_os_destroy_flow
12727                                    (dt->policer_rules[i]));
12728                         dt->policer_rules[i] = NULL;
12729                 }
12730         }
12731         if (dt->jump_actn) {
12732                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12733                 dt->jump_actn = NULL;
12734         }
12735 }
12736
12737 /**
12738  * Destroy policer rules.
12739  *
12740  * @param[in] dev
12741  *   Pointer to Ethernet device.
12742  * @param[in] fm
12743  *   Pointer to flow meter structure.
12744  * @param[in] attr
12745  *   Pointer to flow attributes.
12746  *
12747  * @return
12748  *   Always 0.
12749  */
12750 static int
12751 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12752                               const struct mlx5_flow_meter *fm,
12753                               const struct rte_flow_attr *attr)
12754 {
12755         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12756
12757         if (!mtb)
12758                 return 0;
12759         if (attr->egress)
12760                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12761         if (attr->ingress)
12762                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12763         if (attr->transfer)
12764                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12765         return 0;
12766 }
12767
12768 /**
12769  * Create specify domain meter policer rule.
12770  *
12771  * @param[in] fm
12772  *   Pointer to flow meter structure.
12773  * @param[in] mtb
12774  *   Pointer to DV meter table set.
12775  * @param[in] mtr_reg_c
12776  *   Color match REG_C.
12777  *
12778  * @return
12779  *   0 on success, -1 otherwise.
12780  */
12781 static int
12782 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12783                                     struct mlx5_meter_domain_info *dtb,
12784                                     uint8_t mtr_reg_c)
12785 {
12786         struct mlx5_flow_dv_match_params matcher = {
12787                 .size = sizeof(matcher.buf),
12788         };
12789         struct mlx5_flow_dv_match_params value = {
12790                 .size = sizeof(value.buf),
12791         };
12792         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12793         void *actions[METER_ACTIONS];
12794         int i;
12795         int ret = 0;
12796
12797         /* Create jump action. */
12798         if (!dtb->jump_actn)
12799                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12800                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12801         if (ret) {
12802                 DRV_LOG(ERR, "Failed to create policer jump action.");
12803                 goto error;
12804         }
12805         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12806                 int j = 0;
12807
12808                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12809                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12810                 if (mtb->count_actns[i])
12811                         actions[j++] = mtb->count_actns[i];
12812                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12813                         actions[j++] = mtb->drop_actn;
12814                 else
12815                         actions[j++] = dtb->jump_actn;
12816                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12817                                                (void *)&value, j, actions,
12818                                                &dtb->policer_rules[i]);
12819                 if (ret) {
12820                         DRV_LOG(ERR, "Failed to create policer rule.");
12821                         goto error;
12822                 }
12823         }
12824         return 0;
12825 error:
12826         rte_errno = errno;
12827         return -1;
12828 }
12829
12830 /**
12831  * Create policer rules.
12832  *
12833  * @param[in] dev
12834  *   Pointer to Ethernet device.
12835  * @param[in] fm
12836  *   Pointer to flow meter structure.
12837  * @param[in] attr
12838  *   Pointer to flow attributes.
12839  *
12840  * @return
12841  *   0 on success, -1 otherwise.
12842  */
12843 static int
12844 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12845                              struct mlx5_flow_meter *fm,
12846                              const struct rte_flow_attr *attr)
12847 {
12848         struct mlx5_priv *priv = dev->data->dev_private;
12849         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12850         int ret;
12851
12852         if (attr->egress) {
12853                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12854                                                 priv->mtr_color_reg);
12855                 if (ret) {
12856                         DRV_LOG(ERR, "Failed to create egress policer.");
12857                         goto error;
12858                 }
12859         }
12860         if (attr->ingress) {
12861                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12862                                                 priv->mtr_color_reg);
12863                 if (ret) {
12864                         DRV_LOG(ERR, "Failed to create ingress policer.");
12865                         goto error;
12866                 }
12867         }
12868         if (attr->transfer) {
12869                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12870                                                 priv->mtr_color_reg);
12871                 if (ret) {
12872                         DRV_LOG(ERR, "Failed to create transfer policer.");
12873                         goto error;
12874                 }
12875         }
12876         return 0;
12877 error:
12878         flow_dv_destroy_policer_rules(dev, fm, attr);
12879         return -1;
12880 }
12881
12882 /**
12883  * Validate the batch counter support in root table.
12884  *
12885  * Create a simple flow with invalid counter and drop action on root table to
12886  * validate if batch counter with offset on root table is supported or not.
12887  *
12888  * @param[in] dev
12889  *   Pointer to rte_eth_dev structure.
12890  *
12891  * @return
12892  *   0 on success, a negative errno value otherwise and rte_errno is set.
12893  */
12894 int
12895 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12896 {
12897         struct mlx5_priv *priv = dev->data->dev_private;
12898         struct mlx5_dev_ctx_shared *sh = priv->sh;
12899         struct mlx5_flow_dv_match_params mask = {
12900                 .size = sizeof(mask.buf),
12901         };
12902         struct mlx5_flow_dv_match_params value = {
12903                 .size = sizeof(value.buf),
12904         };
12905         struct mlx5dv_flow_matcher_attr dv_attr = {
12906                 .type = IBV_FLOW_ATTR_NORMAL,
12907                 .priority = 0,
12908                 .match_criteria_enable = 0,
12909                 .match_mask = (void *)&mask,
12910         };
12911         void *actions[2] = { 0 };
12912         struct mlx5_flow_tbl_resource *tbl = NULL;
12913         struct mlx5_devx_obj *dcs = NULL;
12914         void *matcher = NULL;
12915         void *flow = NULL;
12916         int ret = -1;
12917
12918         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12919         if (!tbl)
12920                 goto err;
12921         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12922         if (!dcs)
12923                 goto err;
12924         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12925                                                     &actions[0]);
12926         if (ret)
12927                 goto err;
12928         actions[1] = priv->drop_queue.hrxq->action;
12929         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12930         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12931                                                &matcher);
12932         if (ret)
12933                 goto err;
12934         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12935                                        actions, &flow);
12936 err:
12937         /*
12938          * If batch counter with offset is not supported, the driver will not
12939          * validate the invalid offset value, flow create should success.
12940          * In this case, it means batch counter is not supported in root table.
12941          *
12942          * Otherwise, if flow create is failed, counter offset is supported.
12943          */
12944         if (flow) {
12945                 DRV_LOG(INFO, "Batch counter is not supported in root "
12946                               "table. Switch to fallback mode.");
12947                 rte_errno = ENOTSUP;
12948                 ret = -rte_errno;
12949                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12950         } else {
12951                 /* Check matcher to make sure validate fail at flow create. */
12952                 if (!matcher || (matcher && errno != EINVAL))
12953                         DRV_LOG(ERR, "Unexpected error in counter offset "
12954                                      "support detection");
12955                 ret = 0;
12956         }
12957         if (actions[0])
12958                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12959         if (matcher)
12960                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12961         if (tbl)
12962                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12963         if (dcs)
12964                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12965         return ret;
12966 }
12967
12968 /**
12969  * Query a devx counter.
12970  *
12971  * @param[in] dev
12972  *   Pointer to the Ethernet device structure.
12973  * @param[in] cnt
12974  *   Index to the flow counter.
12975  * @param[in] clear
12976  *   Set to clear the counter statistics.
12977  * @param[out] pkts
12978  *   The statistics value of packets.
12979  * @param[out] bytes
12980  *   The statistics value of bytes.
12981  *
12982  * @return
12983  *   0 on success, otherwise return -1.
12984  */
12985 static int
12986 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12987                       uint64_t *pkts, uint64_t *bytes)
12988 {
12989         struct mlx5_priv *priv = dev->data->dev_private;
12990         struct mlx5_flow_counter *cnt;
12991         uint64_t inn_pkts, inn_bytes;
12992         int ret;
12993
12994         if (!priv->config.devx)
12995                 return -1;
12996
12997         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12998         if (ret)
12999                 return -1;
13000         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13001         *pkts = inn_pkts - cnt->hits;
13002         *bytes = inn_bytes - cnt->bytes;
13003         if (clear) {
13004                 cnt->hits = inn_pkts;
13005                 cnt->bytes = inn_bytes;
13006         }
13007         return 0;
13008 }
13009
13010 /**
13011  * Get aged-out flows.
13012  *
13013  * @param[in] dev
13014  *   Pointer to the Ethernet device structure.
13015  * @param[in] context
13016  *   The address of an array of pointers to the aged-out flows contexts.
13017  * @param[in] nb_contexts
13018  *   The length of context array pointers.
13019  * @param[out] error
13020  *   Perform verbose error reporting if not NULL. Initialized in case of
13021  *   error only.
13022  *
13023  * @return
13024  *   how many contexts get in success, otherwise negative errno value.
13025  *   if nb_contexts is 0, return the amount of all aged contexts.
13026  *   if nb_contexts is not 0 , return the amount of aged flows reported
13027  *   in the context array.
13028  * @note: only stub for now
13029  */
13030 static int
13031 flow_get_aged_flows(struct rte_eth_dev *dev,
13032                     void **context,
13033                     uint32_t nb_contexts,
13034                     struct rte_flow_error *error)
13035 {
13036         struct mlx5_priv *priv = dev->data->dev_private;
13037         struct mlx5_age_info *age_info;
13038         struct mlx5_age_param *age_param;
13039         struct mlx5_flow_counter *counter;
13040         struct mlx5_aso_age_action *act;
13041         int nb_flows = 0;
13042
13043         if (nb_contexts && !context)
13044                 return rte_flow_error_set(error, EINVAL,
13045                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13046                                           NULL, "empty context");
13047         age_info = GET_PORT_AGE_INFO(priv);
13048         rte_spinlock_lock(&age_info->aged_sl);
13049         LIST_FOREACH(act, &age_info->aged_aso, next) {
13050                 nb_flows++;
13051                 if (nb_contexts) {
13052                         context[nb_flows - 1] =
13053                                                 act->age_params.context;
13054                         if (!(--nb_contexts))
13055                                 break;
13056                 }
13057         }
13058         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13059                 nb_flows++;
13060                 if (nb_contexts) {
13061                         age_param = MLX5_CNT_TO_AGE(counter);
13062                         context[nb_flows - 1] = age_param->context;
13063                         if (!(--nb_contexts))
13064                                 break;
13065                 }
13066         }
13067         rte_spinlock_unlock(&age_info->aged_sl);
13068         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13069         return nb_flows;
13070 }
13071
13072 /*
13073  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13074  */
13075 static uint32_t
13076 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13077 {
13078         return flow_dv_counter_alloc(dev, 0);
13079 }
13080
13081 /**
13082  * Validate shared action.
13083  * Dispatcher for action type specific validation.
13084  *
13085  * @param[in] dev
13086  *   Pointer to the Ethernet device structure.
13087  * @param[in] conf
13088  *   Shared action configuration.
13089  * @param[in] action
13090  *   The shared action object to validate.
13091  * @param[out] error
13092  *   Perform verbose error reporting if not NULL. Initialized in case of
13093  *   error only.
13094  *
13095  * @return
13096  *   0 on success, otherwise negative errno value.
13097  */
13098 static int
13099 flow_dv_action_validate(struct rte_eth_dev *dev,
13100                         const struct rte_flow_shared_action_conf *conf,
13101                         const struct rte_flow_action *action,
13102                         struct rte_flow_error *err)
13103 {
13104         struct mlx5_priv *priv = dev->data->dev_private;
13105
13106         RTE_SET_USED(conf);
13107         switch (action->type) {
13108         case RTE_FLOW_ACTION_TYPE_RSS:
13109                 return mlx5_validate_action_rss(dev, action, err);
13110         case RTE_FLOW_ACTION_TYPE_AGE:
13111                 if (!priv->sh->aso_age_mng)
13112                         return rte_flow_error_set(err, ENOTSUP,
13113                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13114                                                 NULL,
13115                                              "shared age action not supported");
13116                 return flow_dv_validate_action_age(0, action, dev, err);
13117         default:
13118                 return rte_flow_error_set(err, ENOTSUP,
13119                                           RTE_FLOW_ERROR_TYPE_ACTION,
13120                                           NULL,
13121                                           "action type not supported");
13122         }
13123 }
13124
13125 static int
13126 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13127 {
13128         struct mlx5_priv *priv = dev->data->dev_private;
13129         int ret = 0;
13130
13131         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13132                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13133                                                 flags);
13134                 if (ret != 0)
13135                         return ret;
13136         }
13137         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13138                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13139                 if (ret != 0)
13140                         return ret;
13141         }
13142         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13143                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13144                 if (ret != 0)
13145                         return ret;
13146         }
13147         return 0;
13148 }
13149
13150 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13151         .validate = flow_dv_validate,
13152         .prepare = flow_dv_prepare,
13153         .translate = flow_dv_translate,
13154         .apply = flow_dv_apply,
13155         .remove = flow_dv_remove,
13156         .destroy = flow_dv_destroy,
13157         .query = flow_dv_query,
13158         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13159         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13160         .create_policer_rules = flow_dv_create_policer_rules,
13161         .destroy_policer_rules = flow_dv_destroy_policer_rules,
13162         .counter_alloc = flow_dv_counter_allocate,
13163         .counter_free = flow_dv_counter_free,
13164         .counter_query = flow_dv_counter_query,
13165         .get_aged_flows = flow_get_aged_flows,
13166         .action_validate = flow_dv_action_validate,
13167         .action_create = flow_dv_action_create,
13168         .action_destroy = flow_dv_action_destroy,
13169         .action_update = flow_dv_action_update,
13170         .action_query = flow_dv_action_query,
13171         .sync_domain = flow_dv_sync_domain,
13172 };
13173
13174 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
13175