1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_dv_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_dv_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_NONE] = MLX5_MODI_OUT_NONE,
836 [REG_A] = MLX5_MODI_META_DATA_REG_A,
837 [REG_B] = MLX5_MODI_META_DATA_REG_B,
838 [REG_C_0] = MLX5_MODI_META_REG_C_0,
839 [REG_C_1] = MLX5_MODI_META_REG_C_1,
840 [REG_C_2] = MLX5_MODI_META_REG_C_2,
841 [REG_C_3] = MLX5_MODI_META_REG_C_3,
842 [REG_C_4] = MLX5_MODI_META_REG_C_4,
843 [REG_C_5] = MLX5_MODI_META_REG_C_5,
844 [REG_C_6] = MLX5_MODI_META_REG_C_6,
845 [REG_C_7] = MLX5_MODI_META_REG_C_7,
849 * Convert register set to DV specification.
851 * @param[in,out] resource
852 * Pointer to the modify-header resource.
854 * Pointer to action specification.
856 * Pointer to the error structure.
859 * 0 on success, a negative errno value otherwise and rte_errno is set.
862 flow_dv_convert_action_set_reg
863 (struct mlx5_flow_dv_modify_hdr_resource *resource,
864 const struct rte_flow_action *action,
865 struct rte_flow_error *error)
867 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
868 struct mlx5_modification_cmd *actions = resource->actions;
869 uint32_t i = resource->actions_num;
871 if (i >= MLX5_MODIFY_NUM)
872 return rte_flow_error_set(error, EINVAL,
873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
874 "too many items to modify");
875 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
876 actions[i].field = reg_to_field[conf->id];
877 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
878 actions[i].data1 = conf->data;
880 resource->actions_num = i;
881 if (!resource->actions_num)
882 return rte_flow_error_set(error, EINVAL,
883 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
884 "invalid modification flow item");
889 * Convert internal COPY_REG action to DV specification.
892 * Pointer to the rte_eth_dev structure.
894 * Pointer to the modify-header resource.
896 * Pointer to action specification.
898 * Pointer to the error structure.
901 * 0 on success, a negative errno value otherwise and rte_errno is set.
904 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
905 struct mlx5_flow_dv_modify_hdr_resource *res,
906 const struct rte_flow_action *action,
907 struct rte_flow_error *error)
909 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
910 rte_be32_t mask = RTE_BE32(UINT32_MAX);
911 struct rte_flow_item item = {
915 struct field_modify_info reg_src[] = {
916 {4, 0, reg_to_field[conf->src]},
919 struct field_modify_info reg_dst = {
921 .id = reg_to_field[conf->dst],
923 /* Adjust reg_c[0] usage according to reported mask. */
924 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
925 struct mlx5_priv *priv = dev->data->dev_private;
926 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
929 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
930 if (conf->dst == REG_C_0) {
931 /* Copy to reg_c[0], within mask only. */
932 reg_dst.offset = rte_bsf32(reg_c0);
934 * Mask is ignoring the enianness, because
935 * there is no conversion in datapath.
937 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
938 /* Copy from destination lower bits to reg_c[0]. */
939 mask = reg_c0 >> reg_dst.offset;
941 /* Copy from destination upper bits to reg_c[0]. */
942 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
943 rte_fls_u32(reg_c0));
946 mask = rte_cpu_to_be_32(reg_c0);
947 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
948 /* Copy from reg_c[0] to destination lower bits. */
951 /* Copy from reg_c[0] to destination upper bits. */
952 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
953 (rte_fls_u32(reg_c0) -
958 return flow_dv_convert_modify_action(&item,
959 reg_src, ®_dst, res,
960 MLX5_MODIFICATION_TYPE_COPY,
965 * Validate META item.
968 * Pointer to the rte_eth_dev structure.
970 * Item specification.
972 * Attributes of flow that includes this item.
974 * Pointer to error structure.
977 * 0 on success, a negative errno value otherwise and rte_errno is set.
980 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
981 const struct rte_flow_item *item,
982 const struct rte_flow_attr *attr,
983 struct rte_flow_error *error)
985 const struct rte_flow_item_meta *spec = item->spec;
986 const struct rte_flow_item_meta *mask = item->mask;
987 const struct rte_flow_item_meta nic_mask = {
993 return rte_flow_error_set(error, EINVAL,
994 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
996 "data cannot be empty");
998 return rte_flow_error_set(error, EINVAL,
999 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1001 "data cannot be zero");
1003 mask = &rte_flow_item_meta_mask;
1004 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1005 (const uint8_t *)&nic_mask,
1006 sizeof(struct rte_flow_item_meta),
1011 return rte_flow_error_set(error, ENOTSUP,
1012 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1014 "pattern not supported for ingress");
1019 * Validate vport item.
1022 * Pointer to the rte_eth_dev structure.
1024 * Item specification.
1026 * Attributes of flow that includes this item.
1027 * @param[in] item_flags
1028 * Bit-fields that holds the items detected until now.
1030 * Pointer to error structure.
1033 * 0 on success, a negative errno value otherwise and rte_errno is set.
1036 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1037 const struct rte_flow_item *item,
1038 const struct rte_flow_attr *attr,
1039 uint64_t item_flags,
1040 struct rte_flow_error *error)
1042 const struct rte_flow_item_port_id *spec = item->spec;
1043 const struct rte_flow_item_port_id *mask = item->mask;
1044 const struct rte_flow_item_port_id switch_mask = {
1047 struct mlx5_priv *esw_priv;
1048 struct mlx5_priv *dev_priv;
1051 if (!attr->transfer)
1052 return rte_flow_error_set(error, EINVAL,
1053 RTE_FLOW_ERROR_TYPE_ITEM,
1055 "match on port id is valid only"
1056 " when transfer flag is enabled");
1057 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1058 return rte_flow_error_set(error, ENOTSUP,
1059 RTE_FLOW_ERROR_TYPE_ITEM, item,
1060 "multiple source ports are not"
1063 mask = &switch_mask;
1064 if (mask->id != 0xffffffff)
1065 return rte_flow_error_set(error, ENOTSUP,
1066 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1068 "no support for partial mask on"
1070 ret = mlx5_flow_item_acceptable
1071 (item, (const uint8_t *)mask,
1072 (const uint8_t *)&rte_flow_item_port_id_mask,
1073 sizeof(struct rte_flow_item_port_id),
1079 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1081 return rte_flow_error_set(error, rte_errno,
1082 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1083 "failed to obtain E-Switch info for"
1085 dev_priv = mlx5_dev_to_eswitch_info(dev);
1087 return rte_flow_error_set(error, rte_errno,
1088 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1090 "failed to obtain E-Switch info");
1091 if (esw_priv->domain_id != dev_priv->domain_id)
1092 return rte_flow_error_set(error, EINVAL,
1093 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1094 "cannot match on a port from a"
1095 " different E-Switch");
1100 * Validate the pop VLAN action.
1103 * Pointer to the rte_eth_dev structure.
1104 * @param[in] action_flags
1105 * Holds the actions detected until now.
1107 * Pointer to the pop vlan action.
1108 * @param[in] item_flags
1109 * The items found in this flow rule.
1111 * Pointer to flow attributes.
1113 * Pointer to error structure.
1116 * 0 on success, a negative errno value otherwise and rte_errno is set.
1119 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1120 uint64_t action_flags,
1121 const struct rte_flow_action *action,
1122 uint64_t item_flags,
1123 const struct rte_flow_attr *attr,
1124 struct rte_flow_error *error)
1126 struct mlx5_priv *priv = dev->data->dev_private;
1130 if (!priv->sh->pop_vlan_action)
1131 return rte_flow_error_set(error, ENOTSUP,
1132 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1134 "pop vlan action is not supported");
1136 * Check for inconsistencies:
1137 * fail strip_vlan in a flow that matches packets without VLAN tags.
1138 * fail strip_vlan in a flow that matches packets without explicitly a
1139 * matching on VLAN tag ?
1141 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1142 return rte_flow_error_set(error, ENOTSUP,
1143 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1145 "no support for multiple vlan pop "
1147 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1148 return rte_flow_error_set(error, ENOTSUP,
1149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1151 "cannot pop vlan without a "
1152 "match on (outer) vlan in the flow");
1153 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1154 return rte_flow_error_set(error, EINVAL,
1155 RTE_FLOW_ERROR_TYPE_ACTION, action,
1156 "wrong action order, port_id should "
1157 "be after pop VLAN action");
1162 * Get VLAN default info from vlan match info.
1165 * Pointer to the rte_eth_dev structure.
1167 * the list of item specifications.
1169 * pointer VLAN info to fill to.
1171 * Pointer to error structure.
1174 * 0 on success, a negative errno value otherwise and rte_errno is set.
1177 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1178 struct rte_vlan_hdr *vlan)
1180 const struct rte_flow_item_vlan nic_mask = {
1181 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1182 MLX5DV_FLOW_VLAN_VID_MASK),
1183 .inner_type = RTE_BE16(0xffff),
1188 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1189 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1191 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1192 const struct rte_flow_item_vlan *vlan_m = items->mask;
1193 const struct rte_flow_item_vlan *vlan_v = items->spec;
1197 /* Only full match values are accepted */
1198 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1199 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1200 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1202 rte_be_to_cpu_16(vlan_v->tci &
1203 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1205 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1206 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1207 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1209 rte_be_to_cpu_16(vlan_v->tci &
1210 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1212 if (vlan_m->inner_type == nic_mask.inner_type)
1213 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1214 vlan_m->inner_type);
1219 * Validate the push VLAN action.
1221 * @param[in] action_flags
1222 * Holds the actions detected until now.
1224 * Pointer to the encap action.
1226 * Pointer to flow attributes
1228 * Pointer to error structure.
1231 * 0 on success, a negative errno value otherwise and rte_errno is set.
1234 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1235 uint64_t item_flags,
1236 const struct rte_flow_action *action,
1237 const struct rte_flow_attr *attr,
1238 struct rte_flow_error *error)
1240 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1242 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1243 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1244 return rte_flow_error_set(error, EINVAL,
1245 RTE_FLOW_ERROR_TYPE_ACTION, action,
1246 "invalid vlan ethertype");
1248 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1249 return rte_flow_error_set(error, ENOTSUP,
1250 RTE_FLOW_ERROR_TYPE_ACTION, action,
1251 "no support for multiple VLAN "
1253 if (!mlx5_flow_find_action
1254 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1255 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1256 return rte_flow_error_set(error, ENOTSUP,
1257 RTE_FLOW_ERROR_TYPE_ACTION, action,
1258 "push VLAN needs to match on VLAN in order to "
1259 "get VLAN VID information because there is "
1260 "no followed set VLAN VID action");
1261 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1262 return rte_flow_error_set(error, EINVAL,
1263 RTE_FLOW_ERROR_TYPE_ACTION, action,
1264 "wrong action order, port_id should "
1265 "be after push VLAN");
1271 * Validate the set VLAN PCP.
1273 * @param[in] action_flags
1274 * Holds the actions detected until now.
1275 * @param[in] actions
1276 * Pointer to the list of actions remaining in the flow rule.
1278 * Pointer to flow attributes
1280 * Pointer to error structure.
1283 * 0 on success, a negative errno value otherwise and rte_errno is set.
1286 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1287 const struct rte_flow_action actions[],
1288 struct rte_flow_error *error)
1290 const struct rte_flow_action *action = actions;
1291 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1293 if (conf->vlan_pcp > 7)
1294 return rte_flow_error_set(error, EINVAL,
1295 RTE_FLOW_ERROR_TYPE_ACTION, action,
1296 "VLAN PCP value is too big");
1297 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1298 return rte_flow_error_set(error, ENOTSUP,
1299 RTE_FLOW_ERROR_TYPE_ACTION, action,
1300 "set VLAN PCP action must follow "
1301 "the push VLAN action");
1302 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1303 return rte_flow_error_set(error, ENOTSUP,
1304 RTE_FLOW_ERROR_TYPE_ACTION, action,
1305 "Multiple VLAN PCP modification are "
1307 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1308 return rte_flow_error_set(error, EINVAL,
1309 RTE_FLOW_ERROR_TYPE_ACTION, action,
1310 "wrong action order, port_id should "
1311 "be after set VLAN PCP");
1316 * Validate the set VLAN VID.
1318 * @param[in] item_flags
1319 * Holds the items detected in this rule.
1320 * @param[in] actions
1321 * Pointer to the list of actions remaining in the flow rule.
1323 * Pointer to flow attributes
1325 * Pointer to error structure.
1328 * 0 on success, a negative errno value otherwise and rte_errno is set.
1331 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1332 uint64_t action_flags,
1333 const struct rte_flow_action actions[],
1334 struct rte_flow_error *error)
1336 const struct rte_flow_action *action = actions;
1337 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1339 if (conf->vlan_vid > RTE_BE16(0xFFE))
1340 return rte_flow_error_set(error, EINVAL,
1341 RTE_FLOW_ERROR_TYPE_ACTION, action,
1342 "VLAN VID value is too big");
1343 /* there is an of_push_vlan action before us */
1344 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1345 if (mlx5_flow_find_action(actions + 1,
1346 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1347 return rte_flow_error_set(error, ENOTSUP,
1348 RTE_FLOW_ERROR_TYPE_ACTION, action,
1349 "Multiple VLAN VID modifications are "
1356 * Action is on an existing VLAN header:
1357 * Need to verify this is a single modify CID action.
1358 * Rule mast include a match on outer VLAN.
1360 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1361 return rte_flow_error_set(error, ENOTSUP,
1362 RTE_FLOW_ERROR_TYPE_ACTION, action,
1363 "Multiple VLAN VID modifications are "
1365 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1366 return rte_flow_error_set(error, EINVAL,
1367 RTE_FLOW_ERROR_TYPE_ACTION, action,
1368 "match on VLAN is required in order "
1370 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1371 return rte_flow_error_set(error, EINVAL,
1372 RTE_FLOW_ERROR_TYPE_ACTION, action,
1373 "wrong action order, port_id should "
1374 "be after set VLAN VID");
1379 * Validate count action.
1384 * Pointer to error structure.
1387 * 0 on success, a negative errno value otherwise and rte_errno is set.
1390 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1391 struct rte_flow_error *error)
1393 struct mlx5_priv *priv = dev->data->dev_private;
1395 if (!priv->config.devx)
1397 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1401 return rte_flow_error_set
1403 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1405 "count action not supported");
1409 * Validate the L2 encap action.
1411 * @param[in] action_flags
1412 * Holds the actions detected until now.
1414 * Pointer to the encap action.
1416 * Pointer to flow attributes
1418 * Pointer to error structure.
1421 * 0 on success, a negative errno value otherwise and rte_errno is set.
1424 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1425 const struct rte_flow_action *action,
1426 const struct rte_flow_attr *attr,
1427 struct rte_flow_error *error)
1429 if (!(action->conf))
1430 return rte_flow_error_set(error, EINVAL,
1431 RTE_FLOW_ERROR_TYPE_ACTION, action,
1432 "configuration cannot be null");
1433 if (action_flags & MLX5_FLOW_ACTION_DROP)
1434 return rte_flow_error_set(error, EINVAL,
1435 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1436 "can't drop and encap in same flow");
1437 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1438 return rte_flow_error_set(error, EINVAL,
1439 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1440 "can only have a single encap or"
1441 " decap action in a flow");
1442 if (!attr->transfer && attr->ingress)
1443 return rte_flow_error_set(error, ENOTSUP,
1444 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1446 "encap action not supported for "
1452 * Validate the L2 decap action.
1454 * @param[in] action_flags
1455 * Holds the actions detected until now.
1457 * Pointer to flow attributes
1459 * Pointer to error structure.
1462 * 0 on success, a negative errno value otherwise and rte_errno is set.
1465 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1466 const struct rte_flow_attr *attr,
1467 struct rte_flow_error *error)
1469 if (action_flags & MLX5_FLOW_ACTION_DROP)
1470 return rte_flow_error_set(error, EINVAL,
1471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1472 "can't drop and decap in same flow");
1473 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1474 return rte_flow_error_set(error, EINVAL,
1475 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1476 "can only have a single encap or"
1477 " decap action in a flow");
1478 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1479 return rte_flow_error_set(error, EINVAL,
1480 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1481 "can't have decap action after"
1484 return rte_flow_error_set(error, ENOTSUP,
1485 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1487 "decap action not supported for "
1493 * Validate the raw encap action.
1495 * @param[in] action_flags
1496 * Holds the actions detected until now.
1498 * Pointer to the encap action.
1500 * Pointer to flow attributes
1502 * Pointer to error structure.
1505 * 0 on success, a negative errno value otherwise and rte_errno is set.
1508 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1509 const struct rte_flow_action *action,
1510 const struct rte_flow_attr *attr,
1511 struct rte_flow_error *error)
1513 const struct rte_flow_action_raw_encap *raw_encap =
1514 (const struct rte_flow_action_raw_encap *)action->conf;
1515 if (!(action->conf))
1516 return rte_flow_error_set(error, EINVAL,
1517 RTE_FLOW_ERROR_TYPE_ACTION, action,
1518 "configuration cannot be null");
1519 if (action_flags & MLX5_FLOW_ACTION_DROP)
1520 return rte_flow_error_set(error, EINVAL,
1521 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1522 "can't drop and encap in same flow");
1523 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1524 return rte_flow_error_set(error, EINVAL,
1525 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1526 "can only have a single encap"
1527 " action in a flow");
1528 /* encap without preceding decap is not supported for ingress */
1529 if (!attr->transfer && attr->ingress &&
1530 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1531 return rte_flow_error_set(error, ENOTSUP,
1532 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1534 "encap action not supported for "
1536 if (!raw_encap->size || !raw_encap->data)
1537 return rte_flow_error_set(error, EINVAL,
1538 RTE_FLOW_ERROR_TYPE_ACTION, action,
1539 "raw encap data cannot be empty");
1544 * Validate the raw decap action.
1546 * @param[in] action_flags
1547 * Holds the actions detected until now.
1549 * Pointer to the encap action.
1551 * Pointer to flow attributes
1553 * Pointer to error structure.
1556 * 0 on success, a negative errno value otherwise and rte_errno is set.
1559 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1560 const struct rte_flow_action *action,
1561 const struct rte_flow_attr *attr,
1562 struct rte_flow_error *error)
1564 if (action_flags & MLX5_FLOW_ACTION_DROP)
1565 return rte_flow_error_set(error, EINVAL,
1566 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1567 "can't drop and decap in same flow");
1568 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1569 return rte_flow_error_set(error, EINVAL,
1570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1571 "can't have encap action before"
1573 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1574 return rte_flow_error_set(error, EINVAL,
1575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1576 "can only have a single decap"
1577 " action in a flow");
1578 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1579 return rte_flow_error_set(error, EINVAL,
1580 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1581 "can't have decap action after"
1583 /* decap action is valid on egress only if it is followed by encap */
1585 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1586 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1589 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1590 return rte_flow_error_set
1592 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1593 NULL, "decap action not supported"
1600 * Find existing encap/decap resource or create and register a new one.
1602 * @param dev[in, out]
1603 * Pointer to rte_eth_dev structure.
1604 * @param[in, out] resource
1605 * Pointer to encap/decap resource.
1606 * @parm[in, out] dev_flow
1607 * Pointer to the dev_flow.
1609 * pointer to error structure.
1612 * 0 on success otherwise -errno and errno is set.
1615 flow_dv_encap_decap_resource_register
1616 (struct rte_eth_dev *dev,
1617 struct mlx5_flow_dv_encap_decap_resource *resource,
1618 struct mlx5_flow *dev_flow,
1619 struct rte_flow_error *error)
1621 struct mlx5_priv *priv = dev->data->dev_private;
1622 struct mlx5_ibv_shared *sh = priv->sh;
1623 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1624 struct mlx5dv_dr_domain *domain;
1626 resource->flags = dev_flow->group ? 0 : 1;
1627 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1628 domain = sh->fdb_domain;
1629 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1630 domain = sh->rx_domain;
1632 domain = sh->tx_domain;
1634 /* Lookup a matching resource from cache. */
1635 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1636 if (resource->reformat_type == cache_resource->reformat_type &&
1637 resource->ft_type == cache_resource->ft_type &&
1638 resource->flags == cache_resource->flags &&
1639 resource->size == cache_resource->size &&
1640 !memcmp((const void *)resource->buf,
1641 (const void *)cache_resource->buf,
1643 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1644 (void *)cache_resource,
1645 rte_atomic32_read(&cache_resource->refcnt));
1646 rte_atomic32_inc(&cache_resource->refcnt);
1647 dev_flow->dv.encap_decap = cache_resource;
1651 /* Register new encap/decap resource. */
1652 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1653 if (!cache_resource)
1654 return rte_flow_error_set(error, ENOMEM,
1655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1656 "cannot allocate resource memory");
1657 *cache_resource = *resource;
1658 cache_resource->verbs_action =
1659 mlx5_glue->dv_create_flow_action_packet_reformat
1660 (sh->ctx, cache_resource->reformat_type,
1661 cache_resource->ft_type, domain, cache_resource->flags,
1662 cache_resource->size,
1663 (cache_resource->size ? cache_resource->buf : NULL));
1664 if (!cache_resource->verbs_action) {
1665 rte_free(cache_resource);
1666 return rte_flow_error_set(error, ENOMEM,
1667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1668 NULL, "cannot create action");
1670 rte_atomic32_init(&cache_resource->refcnt);
1671 rte_atomic32_inc(&cache_resource->refcnt);
1672 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1673 dev_flow->dv.encap_decap = cache_resource;
1674 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1675 (void *)cache_resource,
1676 rte_atomic32_read(&cache_resource->refcnt));
1681 * Find existing table jump resource or create and register a new one.
1683 * @param dev[in, out]
1684 * Pointer to rte_eth_dev structure.
1685 * @param[in, out] resource
1686 * Pointer to jump table resource.
1687 * @parm[in, out] dev_flow
1688 * Pointer to the dev_flow.
1690 * pointer to error structure.
1693 * 0 on success otherwise -errno and errno is set.
1696 flow_dv_jump_tbl_resource_register
1697 (struct rte_eth_dev *dev,
1698 struct mlx5_flow_dv_jump_tbl_resource *resource,
1699 struct mlx5_flow *dev_flow,
1700 struct rte_flow_error *error)
1702 struct mlx5_priv *priv = dev->data->dev_private;
1703 struct mlx5_ibv_shared *sh = priv->sh;
1704 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1706 /* Lookup a matching resource from cache. */
1707 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1708 if (resource->tbl == cache_resource->tbl) {
1709 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1710 (void *)cache_resource,
1711 rte_atomic32_read(&cache_resource->refcnt));
1712 rte_atomic32_inc(&cache_resource->refcnt);
1713 dev_flow->dv.jump = cache_resource;
1717 /* Register new jump table resource. */
1718 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1719 if (!cache_resource)
1720 return rte_flow_error_set(error, ENOMEM,
1721 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1722 "cannot allocate resource memory");
1723 *cache_resource = *resource;
1724 cache_resource->action =
1725 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1726 (resource->tbl->obj);
1727 if (!cache_resource->action) {
1728 rte_free(cache_resource);
1729 return rte_flow_error_set(error, ENOMEM,
1730 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1731 NULL, "cannot create action");
1733 rte_atomic32_init(&cache_resource->refcnt);
1734 rte_atomic32_inc(&cache_resource->refcnt);
1735 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1736 dev_flow->dv.jump = cache_resource;
1737 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1738 (void *)cache_resource,
1739 rte_atomic32_read(&cache_resource->refcnt));
1744 * Find existing table port ID resource or create and register a new one.
1746 * @param dev[in, out]
1747 * Pointer to rte_eth_dev structure.
1748 * @param[in, out] resource
1749 * Pointer to port ID action resource.
1750 * @parm[in, out] dev_flow
1751 * Pointer to the dev_flow.
1753 * pointer to error structure.
1756 * 0 on success otherwise -errno and errno is set.
1759 flow_dv_port_id_action_resource_register
1760 (struct rte_eth_dev *dev,
1761 struct mlx5_flow_dv_port_id_action_resource *resource,
1762 struct mlx5_flow *dev_flow,
1763 struct rte_flow_error *error)
1765 struct mlx5_priv *priv = dev->data->dev_private;
1766 struct mlx5_ibv_shared *sh = priv->sh;
1767 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1769 /* Lookup a matching resource from cache. */
1770 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1771 if (resource->port_id == cache_resource->port_id) {
1772 DRV_LOG(DEBUG, "port id action resource resource %p: "
1774 (void *)cache_resource,
1775 rte_atomic32_read(&cache_resource->refcnt));
1776 rte_atomic32_inc(&cache_resource->refcnt);
1777 dev_flow->dv.port_id_action = cache_resource;
1781 /* Register new port id action resource. */
1782 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1783 if (!cache_resource)
1784 return rte_flow_error_set(error, ENOMEM,
1785 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1786 "cannot allocate resource memory");
1787 *cache_resource = *resource;
1788 cache_resource->action =
1789 mlx5_glue->dr_create_flow_action_dest_vport
1790 (priv->sh->fdb_domain, resource->port_id);
1791 if (!cache_resource->action) {
1792 rte_free(cache_resource);
1793 return rte_flow_error_set(error, ENOMEM,
1794 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1795 NULL, "cannot create action");
1797 rte_atomic32_init(&cache_resource->refcnt);
1798 rte_atomic32_inc(&cache_resource->refcnt);
1799 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1800 dev_flow->dv.port_id_action = cache_resource;
1801 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1802 (void *)cache_resource,
1803 rte_atomic32_read(&cache_resource->refcnt));
1808 * Find existing push vlan resource or create and register a new one.
1810 * @param dev[in, out]
1811 * Pointer to rte_eth_dev structure.
1812 * @param[in, out] resource
1813 * Pointer to port ID action resource.
1814 * @parm[in, out] dev_flow
1815 * Pointer to the dev_flow.
1817 * pointer to error structure.
1820 * 0 on success otherwise -errno and errno is set.
1823 flow_dv_push_vlan_action_resource_register
1824 (struct rte_eth_dev *dev,
1825 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1826 struct mlx5_flow *dev_flow,
1827 struct rte_flow_error *error)
1829 struct mlx5_priv *priv = dev->data->dev_private;
1830 struct mlx5_ibv_shared *sh = priv->sh;
1831 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1832 struct mlx5dv_dr_domain *domain;
1834 /* Lookup a matching resource from cache. */
1835 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1836 if (resource->vlan_tag == cache_resource->vlan_tag &&
1837 resource->ft_type == cache_resource->ft_type) {
1838 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1840 (void *)cache_resource,
1841 rte_atomic32_read(&cache_resource->refcnt));
1842 rte_atomic32_inc(&cache_resource->refcnt);
1843 dev_flow->dv.push_vlan_res = cache_resource;
1847 /* Register new push_vlan action resource. */
1848 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1849 if (!cache_resource)
1850 return rte_flow_error_set(error, ENOMEM,
1851 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1852 "cannot allocate resource memory");
1853 *cache_resource = *resource;
1854 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1855 domain = sh->fdb_domain;
1856 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1857 domain = sh->rx_domain;
1859 domain = sh->tx_domain;
1860 cache_resource->action =
1861 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1862 resource->vlan_tag);
1863 if (!cache_resource->action) {
1864 rte_free(cache_resource);
1865 return rte_flow_error_set(error, ENOMEM,
1866 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1867 NULL, "cannot create action");
1869 rte_atomic32_init(&cache_resource->refcnt);
1870 rte_atomic32_inc(&cache_resource->refcnt);
1871 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1872 dev_flow->dv.push_vlan_res = cache_resource;
1873 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1874 (void *)cache_resource,
1875 rte_atomic32_read(&cache_resource->refcnt));
1879 * Get the size of specific rte_flow_item_type
1881 * @param[in] item_type
1882 * Tested rte_flow_item_type.
1885 * sizeof struct item_type, 0 if void or irrelevant.
1888 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1892 switch (item_type) {
1893 case RTE_FLOW_ITEM_TYPE_ETH:
1894 retval = sizeof(struct rte_flow_item_eth);
1896 case RTE_FLOW_ITEM_TYPE_VLAN:
1897 retval = sizeof(struct rte_flow_item_vlan);
1899 case RTE_FLOW_ITEM_TYPE_IPV4:
1900 retval = sizeof(struct rte_flow_item_ipv4);
1902 case RTE_FLOW_ITEM_TYPE_IPV6:
1903 retval = sizeof(struct rte_flow_item_ipv6);
1905 case RTE_FLOW_ITEM_TYPE_UDP:
1906 retval = sizeof(struct rte_flow_item_udp);
1908 case RTE_FLOW_ITEM_TYPE_TCP:
1909 retval = sizeof(struct rte_flow_item_tcp);
1911 case RTE_FLOW_ITEM_TYPE_VXLAN:
1912 retval = sizeof(struct rte_flow_item_vxlan);
1914 case RTE_FLOW_ITEM_TYPE_GRE:
1915 retval = sizeof(struct rte_flow_item_gre);
1917 case RTE_FLOW_ITEM_TYPE_NVGRE:
1918 retval = sizeof(struct rte_flow_item_nvgre);
1920 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1921 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1923 case RTE_FLOW_ITEM_TYPE_MPLS:
1924 retval = sizeof(struct rte_flow_item_mpls);
1926 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1934 #define MLX5_ENCAP_IPV4_VERSION 0x40
1935 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1936 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1937 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1938 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1939 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1940 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1943 * Convert the encap action data from list of rte_flow_item to raw buffer
1946 * Pointer to rte_flow_item objects list.
1948 * Pointer to the output buffer.
1950 * Pointer to the output buffer size.
1952 * Pointer to the error structure.
1955 * 0 on success, a negative errno value otherwise and rte_errno is set.
1958 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1959 size_t *size, struct rte_flow_error *error)
1961 struct rte_ether_hdr *eth = NULL;
1962 struct rte_vlan_hdr *vlan = NULL;
1963 struct rte_ipv4_hdr *ipv4 = NULL;
1964 struct rte_ipv6_hdr *ipv6 = NULL;
1965 struct rte_udp_hdr *udp = NULL;
1966 struct rte_vxlan_hdr *vxlan = NULL;
1967 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1968 struct rte_gre_hdr *gre = NULL;
1970 size_t temp_size = 0;
1973 return rte_flow_error_set(error, EINVAL,
1974 RTE_FLOW_ERROR_TYPE_ACTION,
1975 NULL, "invalid empty data");
1976 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1977 len = flow_dv_get_item_len(items->type);
1978 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1979 return rte_flow_error_set(error, EINVAL,
1980 RTE_FLOW_ERROR_TYPE_ACTION,
1981 (void *)items->type,
1982 "items total size is too big"
1983 " for encap action");
1984 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1985 switch (items->type) {
1986 case RTE_FLOW_ITEM_TYPE_ETH:
1987 eth = (struct rte_ether_hdr *)&buf[temp_size];
1989 case RTE_FLOW_ITEM_TYPE_VLAN:
1990 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1992 return rte_flow_error_set(error, EINVAL,
1993 RTE_FLOW_ERROR_TYPE_ACTION,
1994 (void *)items->type,
1995 "eth header not found");
1996 if (!eth->ether_type)
1997 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1999 case RTE_FLOW_ITEM_TYPE_IPV4:
2000 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2002 return rte_flow_error_set(error, EINVAL,
2003 RTE_FLOW_ERROR_TYPE_ACTION,
2004 (void *)items->type,
2005 "neither eth nor vlan"
2007 if (vlan && !vlan->eth_proto)
2008 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2009 else if (eth && !eth->ether_type)
2010 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2011 if (!ipv4->version_ihl)
2012 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2013 MLX5_ENCAP_IPV4_IHL_MIN;
2014 if (!ipv4->time_to_live)
2015 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2017 case RTE_FLOW_ITEM_TYPE_IPV6:
2018 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2020 return rte_flow_error_set(error, EINVAL,
2021 RTE_FLOW_ERROR_TYPE_ACTION,
2022 (void *)items->type,
2023 "neither eth nor vlan"
2025 if (vlan && !vlan->eth_proto)
2026 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2027 else if (eth && !eth->ether_type)
2028 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2029 if (!ipv6->vtc_flow)
2031 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2032 if (!ipv6->hop_limits)
2033 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2035 case RTE_FLOW_ITEM_TYPE_UDP:
2036 udp = (struct rte_udp_hdr *)&buf[temp_size];
2038 return rte_flow_error_set(error, EINVAL,
2039 RTE_FLOW_ERROR_TYPE_ACTION,
2040 (void *)items->type,
2041 "ip header not found");
2042 if (ipv4 && !ipv4->next_proto_id)
2043 ipv4->next_proto_id = IPPROTO_UDP;
2044 else if (ipv6 && !ipv6->proto)
2045 ipv6->proto = IPPROTO_UDP;
2047 case RTE_FLOW_ITEM_TYPE_VXLAN:
2048 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2050 return rte_flow_error_set(error, EINVAL,
2051 RTE_FLOW_ERROR_TYPE_ACTION,
2052 (void *)items->type,
2053 "udp header not found");
2055 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2056 if (!vxlan->vx_flags)
2058 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2060 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2061 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2063 return rte_flow_error_set(error, EINVAL,
2064 RTE_FLOW_ERROR_TYPE_ACTION,
2065 (void *)items->type,
2066 "udp header not found");
2067 if (!vxlan_gpe->proto)
2068 return rte_flow_error_set(error, EINVAL,
2069 RTE_FLOW_ERROR_TYPE_ACTION,
2070 (void *)items->type,
2071 "next protocol not found");
2074 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2075 if (!vxlan_gpe->vx_flags)
2076 vxlan_gpe->vx_flags =
2077 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2079 case RTE_FLOW_ITEM_TYPE_GRE:
2080 case RTE_FLOW_ITEM_TYPE_NVGRE:
2081 gre = (struct rte_gre_hdr *)&buf[temp_size];
2083 return rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION,
2085 (void *)items->type,
2086 "next protocol not found");
2088 return rte_flow_error_set(error, EINVAL,
2089 RTE_FLOW_ERROR_TYPE_ACTION,
2090 (void *)items->type,
2091 "ip header not found");
2092 if (ipv4 && !ipv4->next_proto_id)
2093 ipv4->next_proto_id = IPPROTO_GRE;
2094 else if (ipv6 && !ipv6->proto)
2095 ipv6->proto = IPPROTO_GRE;
2097 case RTE_FLOW_ITEM_TYPE_VOID:
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ACTION,
2102 (void *)items->type,
2103 "unsupported item type");
2113 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2115 struct rte_ether_hdr *eth = NULL;
2116 struct rte_vlan_hdr *vlan = NULL;
2117 struct rte_ipv6_hdr *ipv6 = NULL;
2118 struct rte_udp_hdr *udp = NULL;
2122 eth = (struct rte_ether_hdr *)data;
2123 next_hdr = (char *)(eth + 1);
2124 proto = RTE_BE16(eth->ether_type);
2127 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2128 vlan = (struct rte_vlan_hdr *)next_hdr;
2129 proto = RTE_BE16(vlan->eth_proto);
2130 next_hdr += sizeof(struct rte_vlan_hdr);
2133 /* HW calculates IPv4 csum. no need to proceed */
2134 if (proto == RTE_ETHER_TYPE_IPV4)
2137 /* non IPv4/IPv6 header. not supported */
2138 if (proto != RTE_ETHER_TYPE_IPV6) {
2139 return rte_flow_error_set(error, ENOTSUP,
2140 RTE_FLOW_ERROR_TYPE_ACTION,
2141 NULL, "Cannot offload non IPv4/IPv6");
2144 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2146 /* ignore non UDP */
2147 if (ipv6->proto != IPPROTO_UDP)
2150 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2151 udp->dgram_cksum = 0;
2157 * Convert L2 encap action to DV specification.
2160 * Pointer to rte_eth_dev structure.
2162 * Pointer to action structure.
2163 * @param[in, out] dev_flow
2164 * Pointer to the mlx5_flow.
2165 * @param[in] transfer
2166 * Mark if the flow is E-Switch flow.
2168 * Pointer to the error structure.
2171 * 0 on success, a negative errno value otherwise and rte_errno is set.
2174 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2175 const struct rte_flow_action *action,
2176 struct mlx5_flow *dev_flow,
2178 struct rte_flow_error *error)
2180 const struct rte_flow_item *encap_data;
2181 const struct rte_flow_action_raw_encap *raw_encap_data;
2182 struct mlx5_flow_dv_encap_decap_resource res = {
2184 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2185 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2186 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2189 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2191 (const struct rte_flow_action_raw_encap *)action->conf;
2192 res.size = raw_encap_data->size;
2193 memcpy(res.buf, raw_encap_data->data, res.size);
2194 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2197 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2199 ((const struct rte_flow_action_vxlan_encap *)
2200 action->conf)->definition;
2203 ((const struct rte_flow_action_nvgre_encap *)
2204 action->conf)->definition;
2205 if (flow_dv_convert_encap_data(encap_data, res.buf,
2209 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2210 return rte_flow_error_set(error, EINVAL,
2211 RTE_FLOW_ERROR_TYPE_ACTION,
2212 NULL, "can't create L2 encap action");
2217 * Convert L2 decap action to DV specification.
2220 * Pointer to rte_eth_dev structure.
2221 * @param[in, out] dev_flow
2222 * Pointer to the mlx5_flow.
2223 * @param[in] transfer
2224 * Mark if the flow is E-Switch flow.
2226 * Pointer to the error structure.
2229 * 0 on success, a negative errno value otherwise and rte_errno is set.
2232 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2233 struct mlx5_flow *dev_flow,
2235 struct rte_flow_error *error)
2237 struct mlx5_flow_dv_encap_decap_resource res = {
2240 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2241 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2242 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2245 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2246 return rte_flow_error_set(error, EINVAL,
2247 RTE_FLOW_ERROR_TYPE_ACTION,
2248 NULL, "can't create L2 decap action");
2253 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2256 * Pointer to rte_eth_dev structure.
2258 * Pointer to action structure.
2259 * @param[in, out] dev_flow
2260 * Pointer to the mlx5_flow.
2262 * Pointer to the flow attributes.
2264 * Pointer to the error structure.
2267 * 0 on success, a negative errno value otherwise and rte_errno is set.
2270 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2271 const struct rte_flow_action *action,
2272 struct mlx5_flow *dev_flow,
2273 const struct rte_flow_attr *attr,
2274 struct rte_flow_error *error)
2276 const struct rte_flow_action_raw_encap *encap_data;
2277 struct mlx5_flow_dv_encap_decap_resource res;
2279 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2280 res.size = encap_data->size;
2281 memcpy(res.buf, encap_data->data, res.size);
2282 res.reformat_type = attr->egress ?
2283 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2284 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2286 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2288 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2289 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2290 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2291 return rte_flow_error_set(error, EINVAL,
2292 RTE_FLOW_ERROR_TYPE_ACTION,
2293 NULL, "can't create encap action");
2298 * Create action push VLAN.
2301 * Pointer to rte_eth_dev structure.
2302 * @param[in] vlan_tag
2303 * the vlan tag to push to the Ethernet header.
2304 * @param[in, out] dev_flow
2305 * Pointer to the mlx5_flow.
2307 * Pointer to the flow attributes.
2309 * Pointer to the error structure.
2312 * 0 on success, a negative errno value otherwise and rte_errno is set.
2315 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2316 const struct rte_flow_attr *attr,
2317 const struct rte_vlan_hdr *vlan,
2318 struct mlx5_flow *dev_flow,
2319 struct rte_flow_error *error)
2321 struct mlx5_flow_dv_push_vlan_action_resource res;
2324 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2327 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2329 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2330 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2331 return flow_dv_push_vlan_action_resource_register
2332 (dev, &res, dev_flow, error);
2336 * Validate the modify-header actions.
2338 * @param[in] action_flags
2339 * Holds the actions detected until now.
2341 * Pointer to the modify action.
2343 * Pointer to error structure.
2346 * 0 on success, a negative errno value otherwise and rte_errno is set.
2349 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2350 const struct rte_flow_action *action,
2351 struct rte_flow_error *error)
2353 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2354 return rte_flow_error_set(error, EINVAL,
2355 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2356 NULL, "action configuration not set");
2357 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2358 return rte_flow_error_set(error, EINVAL,
2359 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2360 "can't have encap action before"
2366 * Validate the modify-header MAC address actions.
2368 * @param[in] action_flags
2369 * Holds the actions detected until now.
2371 * Pointer to the modify action.
2372 * @param[in] item_flags
2373 * Holds the items detected.
2375 * Pointer to error structure.
2378 * 0 on success, a negative errno value otherwise and rte_errno is set.
2381 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2382 const struct rte_flow_action *action,
2383 const uint64_t item_flags,
2384 struct rte_flow_error *error)
2388 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2390 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2391 return rte_flow_error_set(error, EINVAL,
2392 RTE_FLOW_ERROR_TYPE_ACTION,
2394 "no L2 item in pattern");
2400 * Validate the modify-header IPv4 address actions.
2402 * @param[in] action_flags
2403 * Holds the actions detected until now.
2405 * Pointer to the modify action.
2406 * @param[in] item_flags
2407 * Holds the items detected.
2409 * Pointer to error structure.
2412 * 0 on success, a negative errno value otherwise and rte_errno is set.
2415 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2416 const struct rte_flow_action *action,
2417 const uint64_t item_flags,
2418 struct rte_flow_error *error)
2422 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2424 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2425 return rte_flow_error_set(error, EINVAL,
2426 RTE_FLOW_ERROR_TYPE_ACTION,
2428 "no ipv4 item in pattern");
2434 * Validate the modify-header IPv6 address actions.
2436 * @param[in] action_flags
2437 * Holds the actions detected until now.
2439 * Pointer to the modify action.
2440 * @param[in] item_flags
2441 * Holds the items detected.
2443 * Pointer to error structure.
2446 * 0 on success, a negative errno value otherwise and rte_errno is set.
2449 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2450 const struct rte_flow_action *action,
2451 const uint64_t item_flags,
2452 struct rte_flow_error *error)
2456 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2458 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2459 return rte_flow_error_set(error, EINVAL,
2460 RTE_FLOW_ERROR_TYPE_ACTION,
2462 "no ipv6 item in pattern");
2468 * Validate the modify-header TP actions.
2470 * @param[in] action_flags
2471 * Holds the actions detected until now.
2473 * Pointer to the modify action.
2474 * @param[in] item_flags
2475 * Holds the items detected.
2477 * Pointer to error structure.
2480 * 0 on success, a negative errno value otherwise and rte_errno is set.
2483 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2484 const struct rte_flow_action *action,
2485 const uint64_t item_flags,
2486 struct rte_flow_error *error)
2490 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2492 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2493 return rte_flow_error_set(error, EINVAL,
2494 RTE_FLOW_ERROR_TYPE_ACTION,
2495 NULL, "no transport layer "
2502 * Validate the modify-header actions of increment/decrement
2503 * TCP Sequence-number.
2505 * @param[in] action_flags
2506 * Holds the actions detected until now.
2508 * Pointer to the modify action.
2509 * @param[in] item_flags
2510 * Holds the items detected.
2512 * Pointer to error structure.
2515 * 0 on success, a negative errno value otherwise and rte_errno is set.
2518 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2519 const struct rte_flow_action *action,
2520 const uint64_t item_flags,
2521 struct rte_flow_error *error)
2525 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2527 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2528 return rte_flow_error_set(error, EINVAL,
2529 RTE_FLOW_ERROR_TYPE_ACTION,
2530 NULL, "no TCP item in"
2532 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2533 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2534 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2535 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2536 return rte_flow_error_set(error, EINVAL,
2537 RTE_FLOW_ERROR_TYPE_ACTION,
2539 "cannot decrease and increase"
2540 " TCP sequence number"
2541 " at the same time");
2547 * Validate the modify-header actions of increment/decrement
2548 * TCP Acknowledgment number.
2550 * @param[in] action_flags
2551 * Holds the actions detected until now.
2553 * Pointer to the modify action.
2554 * @param[in] item_flags
2555 * Holds the items detected.
2557 * Pointer to error structure.
2560 * 0 on success, a negative errno value otherwise and rte_errno is set.
2563 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2564 const struct rte_flow_action *action,
2565 const uint64_t item_flags,
2566 struct rte_flow_error *error)
2570 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2572 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2573 return rte_flow_error_set(error, EINVAL,
2574 RTE_FLOW_ERROR_TYPE_ACTION,
2575 NULL, "no TCP item in"
2577 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2578 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2579 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2580 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2581 return rte_flow_error_set(error, EINVAL,
2582 RTE_FLOW_ERROR_TYPE_ACTION,
2584 "cannot decrease and increase"
2585 " TCP acknowledgment number"
2586 " at the same time");
2592 * Validate the modify-header TTL actions.
2594 * @param[in] action_flags
2595 * Holds the actions detected until now.
2597 * Pointer to the modify action.
2598 * @param[in] item_flags
2599 * Holds the items detected.
2601 * Pointer to error structure.
2604 * 0 on success, a negative errno value otherwise and rte_errno is set.
2607 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2608 const struct rte_flow_action *action,
2609 const uint64_t item_flags,
2610 struct rte_flow_error *error)
2614 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2616 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2617 return rte_flow_error_set(error, EINVAL,
2618 RTE_FLOW_ERROR_TYPE_ACTION,
2620 "no IP protocol in pattern");
2626 * Validate jump action.
2629 * Pointer to the jump action.
2630 * @param[in] action_flags
2631 * Holds the actions detected until now.
2632 * @param[in] attributes
2633 * Pointer to flow attributes
2634 * @param[in] external
2635 * Action belongs to flow rule created by request external to PMD.
2637 * Pointer to error structure.
2640 * 0 on success, a negative errno value otherwise and rte_errno is set.
2643 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2644 uint64_t action_flags,
2645 const struct rte_flow_attr *attributes,
2646 bool external, struct rte_flow_error *error)
2648 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2650 uint32_t target_group, table;
2653 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2654 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2655 return rte_flow_error_set(error, EINVAL,
2656 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2657 "can't have 2 fate actions in"
2660 return rte_flow_error_set(error, EINVAL,
2661 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2662 NULL, "action configuration not set");
2664 ((const struct rte_flow_action_jump *)action->conf)->group;
2665 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2669 if (table >= max_group)
2670 return rte_flow_error_set(error, EINVAL,
2671 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2672 "target group index out of range");
2673 if (attributes->group >= target_group)
2674 return rte_flow_error_set(error, EINVAL,
2675 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2676 "target group must be higher than"
2677 " the current flow group");
2682 * Validate the port_id action.
2685 * Pointer to rte_eth_dev structure.
2686 * @param[in] action_flags
2687 * Bit-fields that holds the actions detected until now.
2689 * Port_id RTE action structure.
2691 * Attributes of flow that includes this action.
2693 * Pointer to error structure.
2696 * 0 on success, a negative errno value otherwise and rte_errno is set.
2699 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2700 uint64_t action_flags,
2701 const struct rte_flow_action *action,
2702 const struct rte_flow_attr *attr,
2703 struct rte_flow_error *error)
2705 const struct rte_flow_action_port_id *port_id;
2706 struct mlx5_priv *act_priv;
2707 struct mlx5_priv *dev_priv;
2710 if (!attr->transfer)
2711 return rte_flow_error_set(error, ENOTSUP,
2712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2714 "port id action is valid in transfer"
2716 if (!action || !action->conf)
2717 return rte_flow_error_set(error, ENOTSUP,
2718 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2720 "port id action parameters must be"
2722 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2723 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2724 return rte_flow_error_set(error, EINVAL,
2725 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2726 "can have only one fate actions in"
2728 dev_priv = mlx5_dev_to_eswitch_info(dev);
2730 return rte_flow_error_set(error, rte_errno,
2731 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2733 "failed to obtain E-Switch info");
2734 port_id = action->conf;
2735 port = port_id->original ? dev->data->port_id : port_id->id;
2736 act_priv = mlx5_port_to_eswitch_info(port, false);
2738 return rte_flow_error_set
2740 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2741 "failed to obtain E-Switch port id for port");
2742 if (act_priv->domain_id != dev_priv->domain_id)
2743 return rte_flow_error_set
2745 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2746 "port does not belong to"
2747 " E-Switch being configured");
2752 * Get the maximum number of modify header actions.
2755 * Pointer to rte_eth_dev structure.
2758 * Max number of modify header actions device can support.
2761 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev)
2764 * There's no way to directly query the max cap. Although it has to be
2765 * acquried by iterative trial, it is a safe assumption that more
2766 * actions are supported by FW if extensive metadata register is
2769 return mlx5_flow_ext_mreg_supported(dev) ? MLX5_MODIFY_NUM :
2770 MLX5_MODIFY_NUM_NO_MREG;
2773 * Find existing modify-header resource or create and register a new one.
2775 * @param dev[in, out]
2776 * Pointer to rte_eth_dev structure.
2777 * @param[in, out] resource
2778 * Pointer to modify-header resource.
2779 * @parm[in, out] dev_flow
2780 * Pointer to the dev_flow.
2782 * pointer to error structure.
2785 * 0 on success otherwise -errno and errno is set.
2788 flow_dv_modify_hdr_resource_register
2789 (struct rte_eth_dev *dev,
2790 struct mlx5_flow_dv_modify_hdr_resource *resource,
2791 struct mlx5_flow *dev_flow,
2792 struct rte_flow_error *error)
2794 struct mlx5_priv *priv = dev->data->dev_private;
2795 struct mlx5_ibv_shared *sh = priv->sh;
2796 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2797 struct mlx5dv_dr_domain *ns;
2799 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev))
2800 return rte_flow_error_set(error, EOVERFLOW,
2801 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2802 "too many modify header items");
2803 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2804 ns = sh->fdb_domain;
2805 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2810 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2811 /* Lookup a matching resource from cache. */
2812 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2813 if (resource->ft_type == cache_resource->ft_type &&
2814 resource->actions_num == cache_resource->actions_num &&
2815 resource->flags == cache_resource->flags &&
2816 !memcmp((const void *)resource->actions,
2817 (const void *)cache_resource->actions,
2818 (resource->actions_num *
2819 sizeof(resource->actions[0])))) {
2820 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2821 (void *)cache_resource,
2822 rte_atomic32_read(&cache_resource->refcnt));
2823 rte_atomic32_inc(&cache_resource->refcnt);
2824 dev_flow->dv.modify_hdr = cache_resource;
2828 /* Register new modify-header resource. */
2829 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2830 if (!cache_resource)
2831 return rte_flow_error_set(error, ENOMEM,
2832 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2833 "cannot allocate resource memory");
2834 *cache_resource = *resource;
2835 cache_resource->verbs_action =
2836 mlx5_glue->dv_create_flow_action_modify_header
2837 (sh->ctx, cache_resource->ft_type,
2838 ns, cache_resource->flags,
2839 cache_resource->actions_num *
2840 sizeof(cache_resource->actions[0]),
2841 (uint64_t *)cache_resource->actions);
2842 if (!cache_resource->verbs_action) {
2843 rte_free(cache_resource);
2844 return rte_flow_error_set(error, ENOMEM,
2845 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2846 NULL, "cannot create action");
2848 rte_atomic32_init(&cache_resource->refcnt);
2849 rte_atomic32_inc(&cache_resource->refcnt);
2850 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2851 dev_flow->dv.modify_hdr = cache_resource;
2852 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2853 (void *)cache_resource,
2854 rte_atomic32_read(&cache_resource->refcnt));
2858 #define MLX5_CNT_CONTAINER_RESIZE 64
2861 * Get or create a flow counter.
2864 * Pointer to the Ethernet device structure.
2866 * Indicate if this counter is shared with other flows.
2868 * Counter identifier.
2871 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2873 static struct mlx5_flow_counter *
2874 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2877 struct mlx5_priv *priv = dev->data->dev_private;
2878 struct mlx5_flow_counter *cnt = NULL;
2879 struct mlx5_devx_obj *dcs = NULL;
2881 if (!priv->config.devx) {
2882 rte_errno = ENOTSUP;
2886 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2887 if (cnt->shared && cnt->id == id) {
2893 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2896 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2898 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2902 struct mlx5_flow_counter tmpl = {
2908 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2910 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2916 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2921 * Release a flow counter.
2924 * Pointer to the Ethernet device structure.
2925 * @param[in] counter
2926 * Pointer to the counter handler.
2929 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2930 struct mlx5_flow_counter *counter)
2932 struct mlx5_priv *priv = dev->data->dev_private;
2936 if (--counter->ref_cnt == 0) {
2937 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2938 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2944 * Query a devx flow counter.
2947 * Pointer to the Ethernet device structure.
2949 * Pointer to the flow counter.
2951 * The statistics value of packets.
2953 * The statistics value of bytes.
2956 * 0 on success, otherwise a negative errno value and rte_errno is set.
2959 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2960 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2963 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2968 * Get a pool by a counter.
2971 * Pointer to the counter.
2976 static struct mlx5_flow_counter_pool *
2977 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2980 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2981 return (struct mlx5_flow_counter_pool *)cnt - 1;
2987 * Get a pool by devx counter ID.
2990 * Pointer to the counter container.
2992 * The counter devx ID.
2995 * The counter pool pointer if exists, NULL otherwise,
2997 static struct mlx5_flow_counter_pool *
2998 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3000 struct mlx5_flow_counter_pool *pool;
3002 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3003 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3004 MLX5_COUNTERS_PER_POOL;
3006 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3013 * Allocate a new memory for the counter values wrapped by all the needed
3017 * Pointer to the Ethernet device structure.
3019 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3022 * The new memory management pointer on success, otherwise NULL and rte_errno
3025 static struct mlx5_counter_stats_mem_mng *
3026 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3028 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3029 (dev->data->dev_private))->sh;
3030 struct mlx5_devx_mkey_attr mkey_attr;
3031 struct mlx5_counter_stats_mem_mng *mem_mng;
3032 volatile struct flow_counter_stats *raw_data;
3033 int size = (sizeof(struct flow_counter_stats) *
3034 MLX5_COUNTERS_PER_POOL +
3035 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3036 sizeof(struct mlx5_counter_stats_mem_mng);
3037 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3044 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3045 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3046 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3047 IBV_ACCESS_LOCAL_WRITE);
3048 if (!mem_mng->umem) {
3053 mkey_attr.addr = (uintptr_t)mem;
3054 mkey_attr.size = size;
3055 mkey_attr.umem_id = mem_mng->umem->umem_id;
3056 mkey_attr.pd = sh->pdn;
3057 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3059 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3064 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3065 raw_data = (volatile struct flow_counter_stats *)mem;
3066 for (i = 0; i < raws_n; ++i) {
3067 mem_mng->raws[i].mem_mng = mem_mng;
3068 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3070 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3075 * Resize a counter container.
3078 * Pointer to the Ethernet device structure.
3080 * Whether the pool is for counter that was allocated by batch command.
3083 * The new container pointer on success, otherwise NULL and rte_errno is set.
3085 static struct mlx5_pools_container *
3086 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3088 struct mlx5_priv *priv = dev->data->dev_private;
3089 struct mlx5_pools_container *cont =
3090 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3091 struct mlx5_pools_container *new_cont =
3092 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3093 struct mlx5_counter_stats_mem_mng *mem_mng;
3094 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3095 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3098 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3099 /* The last resize still hasn't detected by the host thread. */
3103 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3104 if (!new_cont->pools) {
3109 memcpy(new_cont->pools, cont->pools, cont->n *
3110 sizeof(struct mlx5_flow_counter_pool *));
3111 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3112 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3114 rte_free(new_cont->pools);
3117 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3118 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3119 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3121 new_cont->n = resize;
3122 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3123 TAILQ_INIT(&new_cont->pool_list);
3124 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3125 new_cont->init_mem_mng = mem_mng;
3127 /* Flip the master container. */
3128 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3133 * Query a devx flow counter.
3136 * Pointer to the Ethernet device structure.
3138 * Pointer to the flow counter.
3140 * The statistics value of packets.
3142 * The statistics value of bytes.
3145 * 0 on success, otherwise a negative errno value and rte_errno is set.
3148 _flow_dv_query_count(struct rte_eth_dev *dev,
3149 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3152 struct mlx5_priv *priv = dev->data->dev_private;
3153 struct mlx5_flow_counter_pool *pool =
3154 flow_dv_counter_pool_get(cnt);
3155 int offset = cnt - &pool->counters_raw[0];
3157 if (priv->counter_fallback)
3158 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3160 rte_spinlock_lock(&pool->sl);
3162 * The single counters allocation may allocate smaller ID than the
3163 * current allocated in parallel to the host reading.
3164 * In this case the new counter values must be reported as 0.
3166 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3170 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3171 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3173 rte_spinlock_unlock(&pool->sl);
3178 * Create and initialize a new counter pool.
3181 * Pointer to the Ethernet device structure.
3183 * The devX counter handle.
3185 * Whether the pool is for counter that was allocated by batch command.
3188 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3190 static struct mlx5_flow_counter_pool *
3191 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3194 struct mlx5_priv *priv = dev->data->dev_private;
3195 struct mlx5_flow_counter_pool *pool;
3196 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3198 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3201 if (cont->n == n_valid) {
3202 cont = flow_dv_container_resize(dev, batch);
3206 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3207 sizeof(struct mlx5_flow_counter);
3208 pool = rte_calloc(__func__, 1, size, 0);
3213 pool->min_dcs = dcs;
3214 pool->raw = cont->init_mem_mng->raws + n_valid %
3215 MLX5_CNT_CONTAINER_RESIZE;
3216 pool->raw_hw = NULL;
3217 rte_spinlock_init(&pool->sl);
3219 * The generation of the new allocated counters in this pool is 0, 2 in
3220 * the pool generation makes all the counters valid for allocation.
3222 rte_atomic64_set(&pool->query_gen, 0x2);
3223 TAILQ_INIT(&pool->counters);
3224 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3225 cont->pools[n_valid] = pool;
3226 /* Pool initialization must be updated before host thread access. */
3228 rte_atomic16_add(&cont->n_valid, 1);
3233 * Prepare a new counter and/or a new counter pool.
3236 * Pointer to the Ethernet device structure.
3237 * @param[out] cnt_free
3238 * Where to put the pointer of a new counter.
3240 * Whether the pool is for counter that was allocated by batch command.
3243 * The free counter pool pointer and @p cnt_free is set on success,
3244 * NULL otherwise and rte_errno is set.
3246 static struct mlx5_flow_counter_pool *
3247 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3248 struct mlx5_flow_counter **cnt_free,
3251 struct mlx5_priv *priv = dev->data->dev_private;
3252 struct mlx5_flow_counter_pool *pool;
3253 struct mlx5_devx_obj *dcs = NULL;
3254 struct mlx5_flow_counter *cnt;
3258 /* bulk_bitmap must be 0 for single counter allocation. */
3259 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3262 pool = flow_dv_find_pool_by_id
3263 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3265 pool = flow_dv_pool_create(dev, dcs, batch);
3267 mlx5_devx_cmd_destroy(dcs);
3270 } else if (dcs->id < pool->min_dcs->id) {
3271 rte_atomic64_set(&pool->a64_dcs,
3272 (int64_t)(uintptr_t)dcs);
3274 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3275 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3280 /* bulk_bitmap is in 128 counters units. */
3281 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3282 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3284 rte_errno = ENODATA;
3287 pool = flow_dv_pool_create(dev, dcs, batch);
3289 mlx5_devx_cmd_destroy(dcs);
3292 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3293 cnt = &pool->counters_raw[i];
3295 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3297 *cnt_free = &pool->counters_raw[0];
3302 * Search for existed shared counter.
3305 * Pointer to the relevant counter pool container.
3307 * The shared counter ID to search.
3310 * NULL if not existed, otherwise pointer to the shared counter.
3312 static struct mlx5_flow_counter *
3313 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3316 static struct mlx5_flow_counter *cnt;
3317 struct mlx5_flow_counter_pool *pool;
3320 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3321 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3322 cnt = &pool->counters_raw[i];
3323 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3331 * Allocate a flow counter.
3334 * Pointer to the Ethernet device structure.
3336 * Indicate if this counter is shared with other flows.
3338 * Counter identifier.
3340 * Counter flow group.
3343 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3345 static struct mlx5_flow_counter *
3346 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3349 struct mlx5_priv *priv = dev->data->dev_private;
3350 struct mlx5_flow_counter_pool *pool = NULL;
3351 struct mlx5_flow_counter *cnt_free = NULL;
3353 * Currently group 0 flow counter cannot be assigned to a flow if it is
3354 * not the first one in the batch counter allocation, so it is better
3355 * to allocate counters one by one for these flows in a separate
3357 * A counter can be shared between different groups so need to take
3358 * shared counters from the single container.
3360 uint32_t batch = (group && !shared) ? 1 : 0;
3361 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3364 if (priv->counter_fallback)
3365 return flow_dv_counter_alloc_fallback(dev, shared, id);
3366 if (!priv->config.devx) {
3367 rte_errno = ENOTSUP;
3371 cnt_free = flow_dv_counter_shared_search(cont, id);
3373 if (cnt_free->ref_cnt + 1 == 0) {
3377 cnt_free->ref_cnt++;
3381 /* Pools which has a free counters are in the start. */
3382 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3384 * The free counter reset values must be updated between the
3385 * counter release to the counter allocation, so, at least one
3386 * query must be done in this time. ensure it by saving the
3387 * query generation in the release time.
3388 * The free list is sorted according to the generation - so if
3389 * the first one is not updated, all the others are not
3392 cnt_free = TAILQ_FIRST(&pool->counters);
3393 if (cnt_free && cnt_free->query_gen + 1 <
3394 rte_atomic64_read(&pool->query_gen))
3399 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3403 cnt_free->batch = batch;
3404 /* Create a DV counter action only in the first time usage. */
3405 if (!cnt_free->action) {
3407 struct mlx5_devx_obj *dcs;
3410 offset = cnt_free - &pool->counters_raw[0];
3411 dcs = pool->min_dcs;
3414 dcs = cnt_free->dcs;
3416 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3418 if (!cnt_free->action) {
3423 /* Update the counter reset values. */
3424 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3427 cnt_free->shared = shared;
3428 cnt_free->ref_cnt = 1;
3430 if (!priv->sh->cmng.query_thread_on)
3431 /* Start the asynchronous batch query by the host thread. */
3432 mlx5_set_query_alarm(priv->sh);
3433 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3434 if (TAILQ_EMPTY(&pool->counters)) {
3435 /* Move the pool to the end of the container pool list. */
3436 TAILQ_REMOVE(&cont->pool_list, pool, next);
3437 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3443 * Release a flow counter.
3446 * Pointer to the Ethernet device structure.
3447 * @param[in] counter
3448 * Pointer to the counter handler.
3451 flow_dv_counter_release(struct rte_eth_dev *dev,
3452 struct mlx5_flow_counter *counter)
3454 struct mlx5_priv *priv = dev->data->dev_private;
3458 if (priv->counter_fallback) {
3459 flow_dv_counter_release_fallback(dev, counter);
3462 if (--counter->ref_cnt == 0) {
3463 struct mlx5_flow_counter_pool *pool =
3464 flow_dv_counter_pool_get(counter);
3466 /* Put the counter in the end - the last updated one. */
3467 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3468 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3473 * Verify the @p attributes will be correctly understood by the NIC and store
3474 * them in the @p flow if everything is correct.
3477 * Pointer to dev struct.
3478 * @param[in] attributes
3479 * Pointer to flow attributes
3480 * @param[in] external
3481 * This flow rule is created by request external to PMD.
3483 * Pointer to error structure.
3486 * 0 on success, a negative errno value otherwise and rte_errno is set.
3489 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3490 const struct rte_flow_attr *attributes,
3491 bool external __rte_unused,
3492 struct rte_flow_error *error)
3494 struct mlx5_priv *priv = dev->data->dev_private;
3495 uint32_t priority_max = priv->config.flow_prio - 1;
3497 #ifndef HAVE_MLX5DV_DR
3498 if (attributes->group)
3499 return rte_flow_error_set(error, ENOTSUP,
3500 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3502 "groups are not supported");
3504 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3509 ret = mlx5_flow_group_to_table(attributes, external,
3514 if (table >= max_group)
3515 return rte_flow_error_set(error, EINVAL,
3516 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3517 "group index out of range");
3519 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3520 attributes->priority >= priority_max)
3521 return rte_flow_error_set(error, ENOTSUP,
3522 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3524 "priority out of range");
3525 if (attributes->transfer) {
3526 if (!priv->config.dv_esw_en)
3527 return rte_flow_error_set
3529 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3530 "E-Switch dr is not supported");
3531 if (!(priv->representor || priv->master))
3532 return rte_flow_error_set
3533 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3534 NULL, "E-Switch configuration can only be"
3535 " done by a master or a representor device");
3536 if (attributes->egress)
3537 return rte_flow_error_set
3539 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3540 "egress is not supported");
3542 if (!(attributes->egress ^ attributes->ingress))
3543 return rte_flow_error_set(error, ENOTSUP,
3544 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3545 "must specify exactly one of "
3546 "ingress or egress");
3551 * Internal validation function. For validating both actions and items.
3554 * Pointer to the rte_eth_dev structure.
3556 * Pointer to the flow attributes.
3558 * Pointer to the list of items.
3559 * @param[in] actions
3560 * Pointer to the list of actions.
3561 * @param[in] external
3562 * This flow rule is created by request external to PMD.
3564 * Pointer to the error structure.
3567 * 0 on success, a negative errno value otherwise and rte_errno is set.
3570 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3571 const struct rte_flow_item items[],
3572 const struct rte_flow_action actions[],
3573 bool external, struct rte_flow_error *error)
3576 uint64_t action_flags = 0;
3577 uint64_t item_flags = 0;
3578 uint64_t last_item = 0;
3579 uint8_t next_protocol = 0xff;
3580 uint16_t ether_type = 0;
3582 const struct rte_flow_item *gre_item = NULL;
3583 struct rte_flow_item_tcp nic_tcp_mask = {
3586 .src_port = RTE_BE16(UINT16_MAX),
3587 .dst_port = RTE_BE16(UINT16_MAX),
3593 ret = flow_dv_validate_attributes(dev, attr, external, error);
3596 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3597 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3598 int type = items->type;
3601 case RTE_FLOW_ITEM_TYPE_VOID:
3603 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3604 ret = flow_dv_validate_item_port_id
3605 (dev, items, attr, item_flags, error);
3608 last_item = MLX5_FLOW_ITEM_PORT_ID;
3610 case RTE_FLOW_ITEM_TYPE_ETH:
3611 ret = mlx5_flow_validate_item_eth(items, item_flags,
3615 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3616 MLX5_FLOW_LAYER_OUTER_L2;
3617 if (items->mask != NULL && items->spec != NULL) {
3619 ((const struct rte_flow_item_eth *)
3622 ((const struct rte_flow_item_eth *)
3624 ether_type = rte_be_to_cpu_16(ether_type);
3629 case RTE_FLOW_ITEM_TYPE_VLAN:
3630 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3634 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3635 MLX5_FLOW_LAYER_OUTER_VLAN;
3636 if (items->mask != NULL && items->spec != NULL) {
3638 ((const struct rte_flow_item_vlan *)
3639 items->spec)->inner_type;
3641 ((const struct rte_flow_item_vlan *)
3642 items->mask)->inner_type;
3643 ether_type = rte_be_to_cpu_16(ether_type);
3648 case RTE_FLOW_ITEM_TYPE_IPV4:
3649 mlx5_flow_tunnel_ip_check(items, next_protocol,
3650 &item_flags, &tunnel);
3651 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3657 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3658 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3659 if (items->mask != NULL &&
3660 ((const struct rte_flow_item_ipv4 *)
3661 items->mask)->hdr.next_proto_id) {
3663 ((const struct rte_flow_item_ipv4 *)
3664 (items->spec))->hdr.next_proto_id;
3666 ((const struct rte_flow_item_ipv4 *)
3667 (items->mask))->hdr.next_proto_id;
3669 /* Reset for inner layer. */
3670 next_protocol = 0xff;
3673 case RTE_FLOW_ITEM_TYPE_IPV6:
3674 mlx5_flow_tunnel_ip_check(items, next_protocol,
3675 &item_flags, &tunnel);
3676 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3682 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3683 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3684 if (items->mask != NULL &&
3685 ((const struct rte_flow_item_ipv6 *)
3686 items->mask)->hdr.proto) {
3688 ((const struct rte_flow_item_ipv6 *)
3689 items->spec)->hdr.proto;
3691 ((const struct rte_flow_item_ipv6 *)
3692 items->mask)->hdr.proto;
3694 /* Reset for inner layer. */
3695 next_protocol = 0xff;
3698 case RTE_FLOW_ITEM_TYPE_TCP:
3699 ret = mlx5_flow_validate_item_tcp
3706 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3707 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3709 case RTE_FLOW_ITEM_TYPE_UDP:
3710 ret = mlx5_flow_validate_item_udp(items, item_flags,
3715 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3716 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3718 case RTE_FLOW_ITEM_TYPE_GRE:
3719 ret = mlx5_flow_validate_item_gre(items, item_flags,
3720 next_protocol, error);
3724 last_item = MLX5_FLOW_LAYER_GRE;
3726 case RTE_FLOW_ITEM_TYPE_NVGRE:
3727 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3732 last_item = MLX5_FLOW_LAYER_NVGRE;
3734 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3735 ret = mlx5_flow_validate_item_gre_key
3736 (items, item_flags, gre_item, error);
3739 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3741 case RTE_FLOW_ITEM_TYPE_VXLAN:
3742 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3746 last_item = MLX5_FLOW_LAYER_VXLAN;
3748 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3749 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3754 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3756 case RTE_FLOW_ITEM_TYPE_GENEVE:
3757 ret = mlx5_flow_validate_item_geneve(items,
3762 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3764 case RTE_FLOW_ITEM_TYPE_MPLS:
3765 ret = mlx5_flow_validate_item_mpls(dev, items,
3770 last_item = MLX5_FLOW_LAYER_MPLS;
3772 case RTE_FLOW_ITEM_TYPE_META:
3773 ret = flow_dv_validate_item_meta(dev, items, attr,
3777 last_item = MLX5_FLOW_ITEM_METADATA;
3779 case RTE_FLOW_ITEM_TYPE_ICMP:
3780 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3785 last_item = MLX5_FLOW_LAYER_ICMP;
3787 case RTE_FLOW_ITEM_TYPE_ICMP6:
3788 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3793 last_item = MLX5_FLOW_LAYER_ICMP6;
3795 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3796 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3799 return rte_flow_error_set(error, ENOTSUP,
3800 RTE_FLOW_ERROR_TYPE_ITEM,
3801 NULL, "item not supported");
3803 item_flags |= last_item;
3805 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3806 int type = actions->type;
3807 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3808 return rte_flow_error_set(error, ENOTSUP,
3809 RTE_FLOW_ERROR_TYPE_ACTION,
3810 actions, "too many actions");
3812 case RTE_FLOW_ACTION_TYPE_VOID:
3814 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3815 ret = flow_dv_validate_action_port_id(dev,
3822 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3825 case RTE_FLOW_ACTION_TYPE_FLAG:
3826 ret = mlx5_flow_validate_action_flag(action_flags,
3830 action_flags |= MLX5_FLOW_ACTION_FLAG;
3833 case RTE_FLOW_ACTION_TYPE_MARK:
3834 ret = mlx5_flow_validate_action_mark(actions,
3839 action_flags |= MLX5_FLOW_ACTION_MARK;
3842 case RTE_FLOW_ACTION_TYPE_DROP:
3843 ret = mlx5_flow_validate_action_drop(action_flags,
3847 action_flags |= MLX5_FLOW_ACTION_DROP;
3850 case RTE_FLOW_ACTION_TYPE_QUEUE:
3851 ret = mlx5_flow_validate_action_queue(actions,
3856 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3859 case RTE_FLOW_ACTION_TYPE_RSS:
3860 ret = mlx5_flow_validate_action_rss(actions,
3866 action_flags |= MLX5_FLOW_ACTION_RSS;
3869 case RTE_FLOW_ACTION_TYPE_COUNT:
3870 ret = flow_dv_validate_action_count(dev, error);
3873 action_flags |= MLX5_FLOW_ACTION_COUNT;
3876 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3877 if (flow_dv_validate_action_pop_vlan(dev,
3883 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3886 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3887 ret = flow_dv_validate_action_push_vlan(action_flags,
3893 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3896 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3897 ret = flow_dv_validate_action_set_vlan_pcp
3898 (action_flags, actions, error);
3901 /* Count PCP with push_vlan command. */
3902 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3904 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3905 ret = flow_dv_validate_action_set_vlan_vid
3906 (item_flags, action_flags,
3910 /* Count VID with push_vlan command. */
3911 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3913 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3914 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3915 ret = flow_dv_validate_action_l2_encap(action_flags,
3920 action_flags |= actions->type ==
3921 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3922 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3923 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3926 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3927 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3928 ret = flow_dv_validate_action_l2_decap(action_flags,
3932 action_flags |= actions->type ==
3933 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3934 MLX5_FLOW_ACTION_VXLAN_DECAP :
3935 MLX5_FLOW_ACTION_NVGRE_DECAP;
3938 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3939 ret = flow_dv_validate_action_raw_encap(action_flags,
3944 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3947 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3948 ret = flow_dv_validate_action_raw_decap(action_flags,
3953 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3956 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3957 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3958 ret = flow_dv_validate_action_modify_mac(action_flags,
3964 /* Count all modify-header actions as one action. */
3965 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3967 action_flags |= actions->type ==
3968 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3969 MLX5_FLOW_ACTION_SET_MAC_SRC :
3970 MLX5_FLOW_ACTION_SET_MAC_DST;
3973 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3974 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3975 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3981 /* Count all modify-header actions as one action. */
3982 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3984 action_flags |= actions->type ==
3985 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3986 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3987 MLX5_FLOW_ACTION_SET_IPV4_DST;
3989 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3990 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3991 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3997 /* Count all modify-header actions as one action. */
3998 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4000 action_flags |= actions->type ==
4001 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4002 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4003 MLX5_FLOW_ACTION_SET_IPV6_DST;
4005 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4006 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4007 ret = flow_dv_validate_action_modify_tp(action_flags,
4013 /* Count all modify-header actions as one action. */
4014 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4016 action_flags |= actions->type ==
4017 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4018 MLX5_FLOW_ACTION_SET_TP_SRC :
4019 MLX5_FLOW_ACTION_SET_TP_DST;
4021 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4022 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4023 ret = flow_dv_validate_action_modify_ttl(action_flags,
4029 /* Count all modify-header actions as one action. */
4030 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4032 action_flags |= actions->type ==
4033 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4034 MLX5_FLOW_ACTION_SET_TTL :
4035 MLX5_FLOW_ACTION_DEC_TTL;
4037 case RTE_FLOW_ACTION_TYPE_JUMP:
4038 ret = flow_dv_validate_action_jump(actions,
4045 action_flags |= MLX5_FLOW_ACTION_JUMP;
4047 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4048 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4049 ret = flow_dv_validate_action_modify_tcp_seq
4056 /* Count all modify-header actions as one action. */
4057 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4059 action_flags |= actions->type ==
4060 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4061 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4062 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4064 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4065 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4066 ret = flow_dv_validate_action_modify_tcp_ack
4073 /* Count all modify-header actions as one action. */
4074 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4076 action_flags |= actions->type ==
4077 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4078 MLX5_FLOW_ACTION_INC_TCP_ACK :
4079 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4081 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4082 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4085 return rte_flow_error_set(error, ENOTSUP,
4086 RTE_FLOW_ERROR_TYPE_ACTION,
4088 "action not supported");
4091 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4092 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4093 return rte_flow_error_set(error, ENOTSUP,
4094 RTE_FLOW_ERROR_TYPE_ACTION,
4096 "can't have vxlan and vlan"
4097 " actions in the same rule");
4098 /* Eswitch has few restrictions on using items and actions */
4099 if (attr->transfer) {
4100 if (action_flags & MLX5_FLOW_ACTION_FLAG)
4101 return rte_flow_error_set(error, ENOTSUP,
4102 RTE_FLOW_ERROR_TYPE_ACTION,
4104 "unsupported action FLAG");
4105 if (action_flags & MLX5_FLOW_ACTION_MARK)
4106 return rte_flow_error_set(error, ENOTSUP,
4107 RTE_FLOW_ERROR_TYPE_ACTION,
4109 "unsupported action MARK");
4110 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4111 return rte_flow_error_set(error, ENOTSUP,
4112 RTE_FLOW_ERROR_TYPE_ACTION,
4114 "unsupported action QUEUE");
4115 if (action_flags & MLX5_FLOW_ACTION_RSS)
4116 return rte_flow_error_set(error, ENOTSUP,
4117 RTE_FLOW_ERROR_TYPE_ACTION,
4119 "unsupported action RSS");
4120 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4121 return rte_flow_error_set(error, EINVAL,
4122 RTE_FLOW_ERROR_TYPE_ACTION,
4124 "no fate action is found");
4126 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4127 return rte_flow_error_set(error, EINVAL,
4128 RTE_FLOW_ERROR_TYPE_ACTION,
4130 "no fate action is found");
4136 * Internal preparation function. Allocates the DV flow size,
4137 * this size is constant.
4140 * Pointer to the flow attributes.
4142 * Pointer to the list of items.
4143 * @param[in] actions
4144 * Pointer to the list of actions.
4146 * Pointer to the error structure.
4149 * Pointer to mlx5_flow object on success,
4150 * otherwise NULL and rte_errno is set.
4152 static struct mlx5_flow *
4153 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4154 const struct rte_flow_item items[] __rte_unused,
4155 const struct rte_flow_action actions[] __rte_unused,
4156 struct rte_flow_error *error)
4158 size_t size = sizeof(struct mlx5_flow);
4159 struct mlx5_flow *dev_flow;
4161 dev_flow = rte_calloc(__func__, 1, size, 0);
4163 rte_flow_error_set(error, ENOMEM,
4164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4165 "not enough memory to create flow");
4168 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4169 dev_flow->ingress = attr->ingress;
4170 dev_flow->transfer = attr->transfer;
4176 * Sanity check for match mask and value. Similar to check_valid_spec() in
4177 * kernel driver. If unmasked bit is present in value, it returns failure.
4180 * pointer to match mask buffer.
4181 * @param match_value
4182 * pointer to match value buffer.
4185 * 0 if valid, -EINVAL otherwise.
4188 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4190 uint8_t *m = match_mask;
4191 uint8_t *v = match_value;
4194 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4197 "match_value differs from match_criteria"
4198 " %p[%u] != %p[%u]",
4199 match_value, i, match_mask, i);
4208 * Add Ethernet item to matcher and to the value.
4210 * @param[in, out] matcher
4212 * @param[in, out] key
4213 * Flow matcher value.
4215 * Flow pattern to translate.
4217 * Item is inner pattern.
4220 flow_dv_translate_item_eth(void *matcher, void *key,
4221 const struct rte_flow_item *item, int inner)
4223 const struct rte_flow_item_eth *eth_m = item->mask;
4224 const struct rte_flow_item_eth *eth_v = item->spec;
4225 const struct rte_flow_item_eth nic_mask = {
4226 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4227 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4228 .type = RTE_BE16(0xffff),
4240 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4242 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4244 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4246 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4248 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4249 ð_m->dst, sizeof(eth_m->dst));
4250 /* The value must be in the range of the mask. */
4251 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4252 for (i = 0; i < sizeof(eth_m->dst); ++i)
4253 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4254 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4255 ð_m->src, sizeof(eth_m->src));
4256 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4257 /* The value must be in the range of the mask. */
4258 for (i = 0; i < sizeof(eth_m->dst); ++i)
4259 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4260 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4261 rte_be_to_cpu_16(eth_m->type));
4262 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4263 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4267 * Add VLAN item to matcher and to the value.
4269 * @param[in, out] dev_flow
4271 * @param[in, out] matcher
4273 * @param[in, out] key
4274 * Flow matcher value.
4276 * Flow pattern to translate.
4278 * Item is inner pattern.
4281 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4282 void *matcher, void *key,
4283 const struct rte_flow_item *item,
4286 const struct rte_flow_item_vlan *vlan_m = item->mask;
4287 const struct rte_flow_item_vlan *vlan_v = item->spec;
4296 vlan_m = &rte_flow_item_vlan_mask;
4298 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4300 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4302 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4304 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4306 * This is workaround, masks are not supported,
4307 * and pre-validated.
4309 dev_flow->dv.vf_vlan.tag =
4310 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4312 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4313 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4314 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4315 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4316 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4317 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4318 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4319 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4320 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4321 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4322 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4323 rte_be_to_cpu_16(vlan_m->inner_type));
4324 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4325 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4329 * Add IPV4 item to matcher and to the value.
4331 * @param[in, out] matcher
4333 * @param[in, out] key
4334 * Flow matcher value.
4336 * Flow pattern to translate.
4338 * Item is inner pattern.
4340 * The group to insert the rule.
4343 flow_dv_translate_item_ipv4(void *matcher, void *key,
4344 const struct rte_flow_item *item,
4345 int inner, uint32_t group)
4347 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4348 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4349 const struct rte_flow_item_ipv4 nic_mask = {
4351 .src_addr = RTE_BE32(0xffffffff),
4352 .dst_addr = RTE_BE32(0xffffffff),
4353 .type_of_service = 0xff,
4354 .next_proto_id = 0xff,
4364 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4366 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4368 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4370 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4373 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4375 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4376 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4381 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4382 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4383 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4384 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4385 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4386 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4387 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4388 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4389 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4390 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4391 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4392 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4393 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4394 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4395 ipv4_m->hdr.type_of_service);
4396 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4397 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4398 ipv4_m->hdr.type_of_service >> 2);
4399 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4400 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4401 ipv4_m->hdr.next_proto_id);
4402 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4403 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4407 * Add IPV6 item to matcher and to the value.
4409 * @param[in, out] matcher
4411 * @param[in, out] key
4412 * Flow matcher value.
4414 * Flow pattern to translate.
4416 * Item is inner pattern.
4418 * The group to insert the rule.
4421 flow_dv_translate_item_ipv6(void *matcher, void *key,
4422 const struct rte_flow_item *item,
4423 int inner, uint32_t group)
4425 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4426 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4427 const struct rte_flow_item_ipv6 nic_mask = {
4430 "\xff\xff\xff\xff\xff\xff\xff\xff"
4431 "\xff\xff\xff\xff\xff\xff\xff\xff",
4433 "\xff\xff\xff\xff\xff\xff\xff\xff"
4434 "\xff\xff\xff\xff\xff\xff\xff\xff",
4435 .vtc_flow = RTE_BE32(0xffffffff),
4442 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4443 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4452 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4454 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4456 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4458 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4461 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4463 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4464 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4469 size = sizeof(ipv6_m->hdr.dst_addr);
4470 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4471 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4472 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4473 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4474 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4475 for (i = 0; i < size; ++i)
4476 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4477 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4478 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4479 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4480 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4481 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4482 for (i = 0; i < size; ++i)
4483 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4485 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4486 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4487 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4488 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4489 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4490 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4493 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4495 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4498 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4500 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4504 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4506 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4507 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4511 * Add TCP item to matcher and to the value.
4513 * @param[in, out] matcher
4515 * @param[in, out] key
4516 * Flow matcher value.
4518 * Flow pattern to translate.
4520 * Item is inner pattern.
4523 flow_dv_translate_item_tcp(void *matcher, void *key,
4524 const struct rte_flow_item *item,
4527 const struct rte_flow_item_tcp *tcp_m = item->mask;
4528 const struct rte_flow_item_tcp *tcp_v = item->spec;
4533 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4535 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4537 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4539 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4541 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4542 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4546 tcp_m = &rte_flow_item_tcp_mask;
4547 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4548 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4549 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4550 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4551 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4552 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4553 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4554 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4555 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4556 tcp_m->hdr.tcp_flags);
4557 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4558 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4562 * Add UDP item to matcher and to the value.
4564 * @param[in, out] matcher
4566 * @param[in, out] key
4567 * Flow matcher value.
4569 * Flow pattern to translate.
4571 * Item is inner pattern.
4574 flow_dv_translate_item_udp(void *matcher, void *key,
4575 const struct rte_flow_item *item,
4578 const struct rte_flow_item_udp *udp_m = item->mask;
4579 const struct rte_flow_item_udp *udp_v = item->spec;
4584 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4586 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4588 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4590 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4592 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4597 udp_m = &rte_flow_item_udp_mask;
4598 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4599 rte_be_to_cpu_16(udp_m->hdr.src_port));
4600 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4601 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4602 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4603 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4604 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4605 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4609 * Add GRE optional Key item to matcher and to the value.
4611 * @param[in, out] matcher
4613 * @param[in, out] key
4614 * Flow matcher value.
4616 * Flow pattern to translate.
4618 * Item is inner pattern.
4621 flow_dv_translate_item_gre_key(void *matcher, void *key,
4622 const struct rte_flow_item *item)
4624 const rte_be32_t *key_m = item->mask;
4625 const rte_be32_t *key_v = item->spec;
4626 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4627 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4628 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4633 key_m = &gre_key_default_mask;
4634 /* GRE K bit must be on and should already be validated */
4635 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4636 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4637 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4638 rte_be_to_cpu_32(*key_m) >> 8);
4639 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4640 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4641 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4642 rte_be_to_cpu_32(*key_m) & 0xFF);
4643 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4644 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4648 * Add GRE item to matcher and to the value.
4650 * @param[in, out] matcher
4652 * @param[in, out] key
4653 * Flow matcher value.
4655 * Flow pattern to translate.
4657 * Item is inner pattern.
4660 flow_dv_translate_item_gre(void *matcher, void *key,
4661 const struct rte_flow_item *item,
4664 const struct rte_flow_item_gre *gre_m = item->mask;
4665 const struct rte_flow_item_gre *gre_v = item->spec;
4668 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4669 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4676 uint16_t s_present:1;
4677 uint16_t k_present:1;
4678 uint16_t rsvd_bit1:1;
4679 uint16_t c_present:1;
4683 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4686 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4688 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4690 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4692 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4695 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4699 gre_m = &rte_flow_item_gre_mask;
4700 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4701 rte_be_to_cpu_16(gre_m->protocol));
4702 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4703 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4704 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4705 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4706 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4707 gre_crks_rsvd0_ver_m.c_present);
4708 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4709 gre_crks_rsvd0_ver_v.c_present &
4710 gre_crks_rsvd0_ver_m.c_present);
4711 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4712 gre_crks_rsvd0_ver_m.k_present);
4713 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4714 gre_crks_rsvd0_ver_v.k_present &
4715 gre_crks_rsvd0_ver_m.k_present);
4716 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4717 gre_crks_rsvd0_ver_m.s_present);
4718 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4719 gre_crks_rsvd0_ver_v.s_present &
4720 gre_crks_rsvd0_ver_m.s_present);
4724 * Add NVGRE item to matcher and to the value.
4726 * @param[in, out] matcher
4728 * @param[in, out] key
4729 * Flow matcher value.
4731 * Flow pattern to translate.
4733 * Item is inner pattern.
4736 flow_dv_translate_item_nvgre(void *matcher, void *key,
4737 const struct rte_flow_item *item,
4740 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4741 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4742 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4743 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4744 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4745 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4751 /* For NVGRE, GRE header fields must be set with defined values. */
4752 const struct rte_flow_item_gre gre_spec = {
4753 .c_rsvd0_ver = RTE_BE16(0x2000),
4754 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4756 const struct rte_flow_item_gre gre_mask = {
4757 .c_rsvd0_ver = RTE_BE16(0xB000),
4758 .protocol = RTE_BE16(UINT16_MAX),
4760 const struct rte_flow_item gre_item = {
4765 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4769 nvgre_m = &rte_flow_item_nvgre_mask;
4770 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4771 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4772 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4773 memcpy(gre_key_m, tni_flow_id_m, size);
4774 for (i = 0; i < size; ++i)
4775 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4779 * Add VXLAN item to matcher and to the value.
4781 * @param[in, out] matcher
4783 * @param[in, out] key
4784 * Flow matcher value.
4786 * Flow pattern to translate.
4788 * Item is inner pattern.
4791 flow_dv_translate_item_vxlan(void *matcher, void *key,
4792 const struct rte_flow_item *item,
4795 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4796 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4799 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4800 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4808 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4810 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4812 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4814 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4816 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4817 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4818 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4819 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4820 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4825 vxlan_m = &rte_flow_item_vxlan_mask;
4826 size = sizeof(vxlan_m->vni);
4827 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4828 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4829 memcpy(vni_m, vxlan_m->vni, size);
4830 for (i = 0; i < size; ++i)
4831 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4835 * Add Geneve item to matcher and to the value.
4837 * @param[in, out] matcher
4839 * @param[in, out] key
4840 * Flow matcher value.
4842 * Flow pattern to translate.
4844 * Item is inner pattern.
4848 flow_dv_translate_item_geneve(void *matcher, void *key,
4849 const struct rte_flow_item *item, int inner)
4851 const struct rte_flow_item_geneve *geneve_m = item->mask;
4852 const struct rte_flow_item_geneve *geneve_v = item->spec;
4855 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4856 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4865 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4867 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4869 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4871 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4873 dport = MLX5_UDP_PORT_GENEVE;
4874 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4875 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4876 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4881 geneve_m = &rte_flow_item_geneve_mask;
4882 size = sizeof(geneve_m->vni);
4883 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4884 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4885 memcpy(vni_m, geneve_m->vni, size);
4886 for (i = 0; i < size; ++i)
4887 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4888 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4889 rte_be_to_cpu_16(geneve_m->protocol));
4890 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4891 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4892 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4893 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4894 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4895 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4896 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4897 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4898 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4899 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4900 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4901 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4902 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4906 * Add MPLS item to matcher and to the value.
4908 * @param[in, out] matcher
4910 * @param[in, out] key
4911 * Flow matcher value.
4913 * Flow pattern to translate.
4914 * @param[in] prev_layer
4915 * The protocol layer indicated in previous item.
4917 * Item is inner pattern.
4920 flow_dv_translate_item_mpls(void *matcher, void *key,
4921 const struct rte_flow_item *item,
4922 uint64_t prev_layer,
4925 const uint32_t *in_mpls_m = item->mask;
4926 const uint32_t *in_mpls_v = item->spec;
4927 uint32_t *out_mpls_m = 0;
4928 uint32_t *out_mpls_v = 0;
4929 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4930 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4931 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4933 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4934 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4935 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4937 switch (prev_layer) {
4938 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4939 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4940 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4941 MLX5_UDP_PORT_MPLS);
4943 case MLX5_FLOW_LAYER_GRE:
4944 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4945 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4946 RTE_ETHER_TYPE_MPLS);
4949 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4950 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4957 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4958 switch (prev_layer) {
4959 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4961 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4962 outer_first_mpls_over_udp);
4964 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4965 outer_first_mpls_over_udp);
4967 case MLX5_FLOW_LAYER_GRE:
4969 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4970 outer_first_mpls_over_gre);
4972 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4973 outer_first_mpls_over_gre);
4976 /* Inner MPLS not over GRE is not supported. */
4979 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4983 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4989 if (out_mpls_m && out_mpls_v) {
4990 *out_mpls_m = *in_mpls_m;
4991 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4996 * Add metadata register item to matcher
4998 * @param[in, out] matcher
5000 * @param[in, out] key
5001 * Flow matcher value.
5002 * @param[in] reg_type
5003 * Type of device metadata register
5010 flow_dv_match_meta_reg(void *matcher, void *key,
5011 enum modify_reg reg_type,
5012 uint32_t data, uint32_t mask)
5015 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5017 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5022 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5023 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5026 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5027 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5030 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
5031 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
5034 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5035 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5038 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5039 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5042 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5043 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5046 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5047 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
5050 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
5051 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
5054 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
5055 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
5058 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
5059 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5068 * Add META item to matcher
5070 * @param[in, out] matcher
5072 * @param[in, out] key
5073 * Flow matcher value.
5075 * Flow pattern to translate.
5077 * Item is inner pattern.
5080 flow_dv_translate_item_meta(void *matcher, void *key,
5081 const struct rte_flow_item *item)
5083 const struct rte_flow_item_meta *meta_m;
5084 const struct rte_flow_item_meta *meta_v;
5086 meta_m = (const void *)item->mask;
5088 meta_m = &rte_flow_item_meta_mask;
5089 meta_v = (const void *)item->spec;
5091 flow_dv_match_meta_reg(matcher, key, REG_A,
5092 rte_cpu_to_be_32(meta_v->data),
5093 rte_cpu_to_be_32(meta_m->data));
5097 * Add vport metadata Reg C0 item to matcher
5099 * @param[in, out] matcher
5101 * @param[in, out] key
5102 * Flow matcher value.
5104 * Flow pattern to translate.
5107 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5108 uint32_t value, uint32_t mask)
5110 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5114 * Add tag item to matcher
5116 * @param[in, out] matcher
5118 * @param[in, out] key
5119 * Flow matcher value.
5121 * Flow pattern to translate.
5124 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5125 const struct rte_flow_item *item)
5127 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5128 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5129 enum modify_reg reg = tag_v->id;
5131 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5135 * Add source vport match to the specified matcher.
5137 * @param[in, out] matcher
5139 * @param[in, out] key
5140 * Flow matcher value.
5142 * Source vport value to match
5147 flow_dv_translate_item_source_vport(void *matcher, void *key,
5148 int16_t port, uint16_t mask)
5150 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5151 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5153 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5154 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5158 * Translate port-id item to eswitch match on port-id.
5161 * The devich to configure through.
5162 * @param[in, out] matcher
5164 * @param[in, out] key
5165 * Flow matcher value.
5167 * Flow pattern to translate.
5170 * 0 on success, a negative errno value otherwise.
5173 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5174 void *key, const struct rte_flow_item *item)
5176 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5177 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5178 struct mlx5_priv *priv;
5181 mask = pid_m ? pid_m->id : 0xffff;
5182 id = pid_v ? pid_v->id : dev->data->port_id;
5183 priv = mlx5_port_to_eswitch_info(id, item == NULL);
5186 /* Translate to vport field or to metadata, depending on mode. */
5187 if (priv->vport_meta_mask)
5188 flow_dv_translate_item_meta_vport(matcher, key,
5189 priv->vport_meta_tag,
5190 priv->vport_meta_mask);
5192 flow_dv_translate_item_source_vport(matcher, key,
5193 priv->vport_id, mask);
5198 * Add ICMP6 item to matcher and to the value.
5200 * @param[in, out] matcher
5202 * @param[in, out] key
5203 * Flow matcher value.
5205 * Flow pattern to translate.
5207 * Item is inner pattern.
5210 flow_dv_translate_item_icmp6(void *matcher, void *key,
5211 const struct rte_flow_item *item,
5214 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5215 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5218 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5220 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5222 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5224 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5226 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5228 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5230 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5231 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5235 icmp6_m = &rte_flow_item_icmp6_mask;
5236 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5237 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5238 icmp6_v->type & icmp6_m->type);
5239 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5240 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5241 icmp6_v->code & icmp6_m->code);
5245 * Add ICMP item to matcher and to the value.
5247 * @param[in, out] matcher
5249 * @param[in, out] key
5250 * Flow matcher value.
5252 * Flow pattern to translate.
5254 * Item is inner pattern.
5257 flow_dv_translate_item_icmp(void *matcher, void *key,
5258 const struct rte_flow_item *item,
5261 const struct rte_flow_item_icmp *icmp_m = item->mask;
5262 const struct rte_flow_item_icmp *icmp_v = item->spec;
5265 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5267 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5269 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5271 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5273 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5275 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5277 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5278 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5282 icmp_m = &rte_flow_item_icmp_mask;
5283 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5284 icmp_m->hdr.icmp_type);
5285 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5286 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5287 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5288 icmp_m->hdr.icmp_code);
5289 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5290 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5293 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5295 #define HEADER_IS_ZERO(match_criteria, headers) \
5296 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5297 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5300 * Calculate flow matcher enable bitmap.
5302 * @param match_criteria
5303 * Pointer to flow matcher criteria.
5306 * Bitmap of enabled fields.
5309 flow_dv_matcher_enable(uint32_t *match_criteria)
5311 uint8_t match_criteria_enable;
5313 match_criteria_enable =
5314 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5315 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5316 match_criteria_enable |=
5317 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5318 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5319 match_criteria_enable |=
5320 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5321 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5322 match_criteria_enable |=
5323 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5324 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5325 match_criteria_enable |=
5326 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5327 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5328 return match_criteria_enable;
5335 * @param dev[in, out]
5336 * Pointer to rte_eth_dev structure.
5337 * @param[in] table_id
5340 * Direction of the table.
5341 * @param[in] transfer
5342 * E-Switch or NIC flow.
5344 * pointer to error structure.
5347 * Returns tables resource based on the index, NULL in case of failed.
5349 static struct mlx5_flow_tbl_resource *
5350 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5351 uint32_t table_id, uint8_t egress,
5353 struct rte_flow_error *error)
5355 struct mlx5_priv *priv = dev->data->dev_private;
5356 struct mlx5_ibv_shared *sh = priv->sh;
5357 struct mlx5_flow_tbl_resource *tbl;
5359 #ifdef HAVE_MLX5DV_DR
5361 tbl = &sh->fdb_tbl[table_id];
5363 tbl->obj = mlx5_glue->dr_create_flow_tbl
5364 (sh->fdb_domain, table_id);
5365 } else if (egress) {
5366 tbl = &sh->tx_tbl[table_id];
5368 tbl->obj = mlx5_glue->dr_create_flow_tbl
5369 (sh->tx_domain, table_id);
5371 tbl = &sh->rx_tbl[table_id];
5373 tbl->obj = mlx5_glue->dr_create_flow_tbl
5374 (sh->rx_domain, table_id);
5377 rte_flow_error_set(error, ENOMEM,
5378 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5379 NULL, "cannot create table");
5382 rte_atomic32_inc(&tbl->refcnt);
5388 return &sh->fdb_tbl[table_id];
5390 return &sh->tx_tbl[table_id];
5392 return &sh->rx_tbl[table_id];
5397 * Release a flow table.
5400 * Table resource to be released.
5403 * Returns 0 if table was released, else return 1;
5406 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5410 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5411 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5419 * Register the flow matcher.
5421 * @param dev[in, out]
5422 * Pointer to rte_eth_dev structure.
5423 * @param[in, out] matcher
5424 * Pointer to flow matcher.
5425 * @parm[in, out] dev_flow
5426 * Pointer to the dev_flow.
5428 * pointer to error structure.
5431 * 0 on success otherwise -errno and errno is set.
5434 flow_dv_matcher_register(struct rte_eth_dev *dev,
5435 struct mlx5_flow_dv_matcher *matcher,
5436 struct mlx5_flow *dev_flow,
5437 struct rte_flow_error *error)
5439 struct mlx5_priv *priv = dev->data->dev_private;
5440 struct mlx5_ibv_shared *sh = priv->sh;
5441 struct mlx5_flow_dv_matcher *cache_matcher;
5442 struct mlx5dv_flow_matcher_attr dv_attr = {
5443 .type = IBV_FLOW_ATTR_NORMAL,
5444 .match_mask = (void *)&matcher->mask,
5446 struct mlx5_flow_tbl_resource *tbl = NULL;
5448 /* Lookup from cache. */
5449 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5450 if (matcher->crc == cache_matcher->crc &&
5451 matcher->priority == cache_matcher->priority &&
5452 matcher->egress == cache_matcher->egress &&
5453 matcher->group == cache_matcher->group &&
5454 matcher->transfer == cache_matcher->transfer &&
5455 !memcmp((const void *)matcher->mask.buf,
5456 (const void *)cache_matcher->mask.buf,
5457 cache_matcher->mask.size)) {
5459 "priority %hd use %s matcher %p: refcnt %d++",
5460 cache_matcher->priority,
5461 cache_matcher->egress ? "tx" : "rx",
5462 (void *)cache_matcher,
5463 rte_atomic32_read(&cache_matcher->refcnt));
5464 rte_atomic32_inc(&cache_matcher->refcnt);
5465 dev_flow->dv.matcher = cache_matcher;
5469 /* Register new matcher. */
5470 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5472 return rte_flow_error_set(error, ENOMEM,
5473 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5474 "cannot allocate matcher memory");
5475 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5476 matcher->egress, matcher->transfer,
5479 rte_free(cache_matcher);
5480 return rte_flow_error_set(error, ENOMEM,
5481 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5482 NULL, "cannot create table");
5484 *cache_matcher = *matcher;
5485 dv_attr.match_criteria_enable =
5486 flow_dv_matcher_enable(cache_matcher->mask.buf);
5487 dv_attr.priority = matcher->priority;
5488 if (matcher->egress)
5489 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5490 cache_matcher->matcher_object =
5491 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5492 if (!cache_matcher->matcher_object) {
5493 rte_free(cache_matcher);
5494 #ifdef HAVE_MLX5DV_DR
5495 flow_dv_tbl_resource_release(tbl);
5497 return rte_flow_error_set(error, ENOMEM,
5498 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5499 NULL, "cannot create matcher");
5501 rte_atomic32_inc(&cache_matcher->refcnt);
5502 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5503 dev_flow->dv.matcher = cache_matcher;
5504 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5505 cache_matcher->priority,
5506 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5507 rte_atomic32_read(&cache_matcher->refcnt));
5508 rte_atomic32_inc(&tbl->refcnt);
5513 * Find existing tag resource or create and register a new one.
5515 * @param dev[in, out]
5516 * Pointer to rte_eth_dev structure.
5517 * @param[in, out] resource
5518 * Pointer to tag resource.
5519 * @parm[in, out] dev_flow
5520 * Pointer to the dev_flow.
5522 * pointer to error structure.
5525 * 0 on success otherwise -errno and errno is set.
5528 flow_dv_tag_resource_register
5529 (struct rte_eth_dev *dev,
5530 struct mlx5_flow_dv_tag_resource *resource,
5531 struct mlx5_flow *dev_flow,
5532 struct rte_flow_error *error)
5534 struct mlx5_priv *priv = dev->data->dev_private;
5535 struct mlx5_ibv_shared *sh = priv->sh;
5536 struct mlx5_flow_dv_tag_resource *cache_resource;
5538 /* Lookup a matching resource from cache. */
5539 LIST_FOREACH(cache_resource, &sh->tags, next) {
5540 if (resource->tag == cache_resource->tag) {
5541 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5542 (void *)cache_resource,
5543 rte_atomic32_read(&cache_resource->refcnt));
5544 rte_atomic32_inc(&cache_resource->refcnt);
5545 dev_flow->dv.tag_resource = cache_resource;
5549 /* Register new resource. */
5550 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5551 if (!cache_resource)
5552 return rte_flow_error_set(error, ENOMEM,
5553 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5554 "cannot allocate resource memory");
5555 *cache_resource = *resource;
5556 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5558 if (!cache_resource->action) {
5559 rte_free(cache_resource);
5560 return rte_flow_error_set(error, ENOMEM,
5561 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5562 NULL, "cannot create action");
5564 rte_atomic32_init(&cache_resource->refcnt);
5565 rte_atomic32_inc(&cache_resource->refcnt);
5566 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5567 dev_flow->dv.tag_resource = cache_resource;
5568 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5569 (void *)cache_resource,
5570 rte_atomic32_read(&cache_resource->refcnt));
5578 * Pointer to Ethernet device.
5580 * Pointer to mlx5_flow.
5583 * 1 while a reference on it exists, 0 when freed.
5586 flow_dv_tag_release(struct rte_eth_dev *dev,
5587 struct mlx5_flow_dv_tag_resource *tag)
5590 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5591 dev->data->port_id, (void *)tag,
5592 rte_atomic32_read(&tag->refcnt));
5593 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5594 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5595 LIST_REMOVE(tag, next);
5596 DRV_LOG(DEBUG, "port %u tag %p: removed",
5597 dev->data->port_id, (void *)tag);
5605 * Translate port ID action to vport.
5608 * Pointer to rte_eth_dev structure.
5610 * Pointer to the port ID action.
5611 * @param[out] dst_port_id
5612 * The target port ID.
5614 * Pointer to the error structure.
5617 * 0 on success, a negative errno value otherwise and rte_errno is set.
5620 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5621 const struct rte_flow_action *action,
5622 uint32_t *dst_port_id,
5623 struct rte_flow_error *error)
5626 struct mlx5_priv *priv;
5627 const struct rte_flow_action_port_id *conf =
5628 (const struct rte_flow_action_port_id *)action->conf;
5630 port = conf->original ? dev->data->port_id : conf->id;
5631 priv = mlx5_port_to_eswitch_info(port, false);
5633 return rte_flow_error_set(error, -rte_errno,
5634 RTE_FLOW_ERROR_TYPE_ACTION,
5636 "No eswitch info was found for port");
5637 if (priv->vport_meta_mask)
5638 *dst_port_id = priv->vport_meta_tag;
5640 *dst_port_id = priv->vport_id;
5645 * Add Tx queue matcher
5648 * Pointer to the dev struct.
5649 * @param[in, out] matcher
5651 * @param[in, out] key
5652 * Flow matcher value.
5654 * Flow pattern to translate.
5656 * Item is inner pattern.
5659 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5660 void *matcher, void *key,
5661 const struct rte_flow_item *item)
5663 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5664 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5666 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5668 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5669 struct mlx5_txq_ctrl *txq;
5673 queue_m = (const void *)item->mask;
5676 queue_v = (const void *)item->spec;
5679 txq = mlx5_txq_get(dev, queue_v->queue);
5682 queue = txq->obj->sq->id;
5683 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5684 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5685 queue & queue_m->queue);
5686 mlx5_txq_release(dev, queue_v->queue);
5690 * Fill the flow with DV spec, lock free
5691 * (mutex should be acquired by caller).
5694 * Pointer to rte_eth_dev structure.
5695 * @param[in, out] dev_flow
5696 * Pointer to the sub flow.
5698 * Pointer to the flow attributes.
5700 * Pointer to the list of items.
5701 * @param[in] actions
5702 * Pointer to the list of actions.
5704 * Pointer to the error structure.
5707 * 0 on success, a negative errno value otherwise and rte_errno is set.
5710 __flow_dv_translate(struct rte_eth_dev *dev,
5711 struct mlx5_flow *dev_flow,
5712 const struct rte_flow_attr *attr,
5713 const struct rte_flow_item items[],
5714 const struct rte_flow_action actions[],
5715 struct rte_flow_error *error)
5717 struct mlx5_priv *priv = dev->data->dev_private;
5718 struct rte_flow *flow = dev_flow->flow;
5719 uint64_t item_flags = 0;
5720 uint64_t last_item = 0;
5721 uint64_t action_flags = 0;
5722 uint64_t priority = attr->priority;
5723 struct mlx5_flow_dv_matcher matcher = {
5725 .size = sizeof(matcher.mask.buf),
5729 bool actions_end = false;
5730 struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
5731 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5732 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5734 union flow_dv_attr flow_attr = { .attr = 0 };
5735 struct mlx5_flow_dv_tag_resource tag_resource;
5736 uint32_t modify_action_position = UINT32_MAX;
5737 void *match_mask = matcher.mask.buf;
5738 void *match_value = dev_flow->dv.value.buf;
5739 uint8_t next_protocol = 0xff;
5740 struct rte_vlan_hdr vlan = { 0 };
5744 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5748 dev_flow->group = table;
5750 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5751 if (priority == MLX5_FLOW_PRIO_RSVD)
5752 priority = priv->config.flow_prio - 1;
5753 for (; !actions_end ; actions++) {
5754 const struct rte_flow_action_queue *queue;
5755 const struct rte_flow_action_rss *rss;
5756 const struct rte_flow_action *action = actions;
5757 const struct rte_flow_action_count *count = action->conf;
5758 const uint8_t *rss_key;
5759 const struct rte_flow_action_jump *jump_data;
5760 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5761 struct mlx5_flow_tbl_resource *tbl;
5762 uint32_t port_id = 0;
5763 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5764 int action_type = actions->type;
5765 const struct rte_flow_action *found_action = NULL;
5767 switch (action_type) {
5768 case RTE_FLOW_ACTION_TYPE_VOID:
5770 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5771 if (flow_dv_translate_action_port_id(dev, action,
5774 port_id_resource.port_id = port_id;
5775 if (flow_dv_port_id_action_resource_register
5776 (dev, &port_id_resource, dev_flow, error))
5778 dev_flow->dv.actions[actions_n++] =
5779 dev_flow->dv.port_id_action->action;
5780 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5782 case RTE_FLOW_ACTION_TYPE_FLAG:
5784 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5785 if (!dev_flow->dv.tag_resource)
5786 if (flow_dv_tag_resource_register
5787 (dev, &tag_resource, dev_flow, error))
5789 dev_flow->dv.actions[actions_n++] =
5790 dev_flow->dv.tag_resource->action;
5791 action_flags |= MLX5_FLOW_ACTION_FLAG;
5793 case RTE_FLOW_ACTION_TYPE_MARK:
5794 tag_resource.tag = mlx5_flow_mark_set
5795 (((const struct rte_flow_action_mark *)
5796 (actions->conf))->id);
5797 if (!dev_flow->dv.tag_resource)
5798 if (flow_dv_tag_resource_register
5799 (dev, &tag_resource, dev_flow, error))
5801 dev_flow->dv.actions[actions_n++] =
5802 dev_flow->dv.tag_resource->action;
5803 action_flags |= MLX5_FLOW_ACTION_MARK;
5805 case RTE_FLOW_ACTION_TYPE_DROP:
5806 action_flags |= MLX5_FLOW_ACTION_DROP;
5808 case RTE_FLOW_ACTION_TYPE_QUEUE:
5809 assert(flow->rss.queue);
5810 queue = actions->conf;
5811 flow->rss.queue_num = 1;
5812 (*flow->rss.queue)[0] = queue->index;
5813 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5815 case RTE_FLOW_ACTION_TYPE_RSS:
5816 assert(flow->rss.queue);
5817 rss = actions->conf;
5818 if (flow->rss.queue)
5819 memcpy((*flow->rss.queue), rss->queue,
5820 rss->queue_num * sizeof(uint16_t));
5821 flow->rss.queue_num = rss->queue_num;
5822 /* NULL RSS key indicates default RSS key. */
5823 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5824 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5826 * rss->level and rss.types should be set in advance
5827 * when expanding items for RSS.
5829 action_flags |= MLX5_FLOW_ACTION_RSS;
5831 case RTE_FLOW_ACTION_TYPE_COUNT:
5832 if (!priv->config.devx) {
5833 rte_errno = ENOTSUP;
5836 flow->counter = flow_dv_counter_alloc(dev,
5840 if (flow->counter == NULL)
5842 dev_flow->dv.actions[actions_n++] =
5843 flow->counter->action;
5844 action_flags |= MLX5_FLOW_ACTION_COUNT;
5847 if (rte_errno == ENOTSUP)
5848 return rte_flow_error_set
5850 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5852 "count action not supported");
5854 return rte_flow_error_set
5856 RTE_FLOW_ERROR_TYPE_ACTION,
5858 "cannot create counter"
5861 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5862 dev_flow->dv.actions[actions_n++] =
5863 priv->sh->pop_vlan_action;
5864 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5866 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5867 flow_dev_get_vlan_info_from_items(items, &vlan);
5868 vlan.eth_proto = rte_be_to_cpu_16
5869 ((((const struct rte_flow_action_of_push_vlan *)
5870 actions->conf)->ethertype));
5871 found_action = mlx5_flow_find_action
5873 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5875 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5876 found_action = mlx5_flow_find_action
5878 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5880 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5881 if (flow_dv_create_action_push_vlan
5882 (dev, attr, &vlan, dev_flow, error))
5884 dev_flow->dv.actions[actions_n++] =
5885 dev_flow->dv.push_vlan_res->action;
5886 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5888 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5889 /* of_vlan_push action handled this action */
5890 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5892 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5893 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5895 flow_dev_get_vlan_info_from_items(items, &vlan);
5896 mlx5_update_vlan_vid_pcp(actions, &vlan);
5897 /* If no VLAN push - this is a modify header action */
5898 if (flow_dv_convert_action_modify_vlan_vid
5899 (&mhdr_res, actions, error))
5901 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5903 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5904 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5905 if (flow_dv_create_action_l2_encap(dev, actions,
5910 dev_flow->dv.actions[actions_n++] =
5911 dev_flow->dv.encap_decap->verbs_action;
5912 action_flags |= actions->type ==
5913 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5914 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5915 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5917 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5918 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5919 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5923 dev_flow->dv.actions[actions_n++] =
5924 dev_flow->dv.encap_decap->verbs_action;
5925 action_flags |= actions->type ==
5926 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5927 MLX5_FLOW_ACTION_VXLAN_DECAP :
5928 MLX5_FLOW_ACTION_NVGRE_DECAP;
5930 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5931 /* Handle encap with preceding decap. */
5932 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5933 if (flow_dv_create_action_raw_encap
5934 (dev, actions, dev_flow, attr, error))
5936 dev_flow->dv.actions[actions_n++] =
5937 dev_flow->dv.encap_decap->verbs_action;
5939 /* Handle encap without preceding decap. */
5940 if (flow_dv_create_action_l2_encap
5941 (dev, actions, dev_flow, attr->transfer,
5944 dev_flow->dv.actions[actions_n++] =
5945 dev_flow->dv.encap_decap->verbs_action;
5947 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5949 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5950 /* Check if this decap is followed by encap. */
5951 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5952 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5955 /* Handle decap only if it isn't followed by encap. */
5956 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5957 if (flow_dv_create_action_l2_decap
5958 (dev, dev_flow, attr->transfer, error))
5960 dev_flow->dv.actions[actions_n++] =
5961 dev_flow->dv.encap_decap->verbs_action;
5963 /* If decap is followed by encap, handle it at encap. */
5964 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5966 case RTE_FLOW_ACTION_TYPE_JUMP:
5967 jump_data = action->conf;
5968 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5969 jump_data->group, &table,
5973 tbl = flow_dv_tbl_resource_get(dev, table,
5975 attr->transfer, error);
5977 return rte_flow_error_set
5979 RTE_FLOW_ERROR_TYPE_ACTION,
5981 "cannot create jump action.");
5982 jump_tbl_resource.tbl = tbl;
5983 if (flow_dv_jump_tbl_resource_register
5984 (dev, &jump_tbl_resource, dev_flow, error)) {
5985 flow_dv_tbl_resource_release(tbl);
5986 return rte_flow_error_set
5988 RTE_FLOW_ERROR_TYPE_ACTION,
5990 "cannot create jump action.");
5992 dev_flow->dv.actions[actions_n++] =
5993 dev_flow->dv.jump->action;
5994 action_flags |= MLX5_FLOW_ACTION_JUMP;
5996 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5997 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5998 if (flow_dv_convert_action_modify_mac
5999 (&mhdr_res, actions, error))
6001 action_flags |= actions->type ==
6002 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6003 MLX5_FLOW_ACTION_SET_MAC_SRC :
6004 MLX5_FLOW_ACTION_SET_MAC_DST;
6006 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6007 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6008 if (flow_dv_convert_action_modify_ipv4
6009 (&mhdr_res, actions, error))
6011 action_flags |= actions->type ==
6012 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6013 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6014 MLX5_FLOW_ACTION_SET_IPV4_DST;
6016 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6017 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6018 if (flow_dv_convert_action_modify_ipv6
6019 (&mhdr_res, actions, error))
6021 action_flags |= actions->type ==
6022 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6023 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6024 MLX5_FLOW_ACTION_SET_IPV6_DST;
6026 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6027 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6028 if (flow_dv_convert_action_modify_tp
6029 (&mhdr_res, actions, items,
6032 action_flags |= actions->type ==
6033 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6034 MLX5_FLOW_ACTION_SET_TP_SRC :
6035 MLX5_FLOW_ACTION_SET_TP_DST;
6037 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6038 if (flow_dv_convert_action_modify_dec_ttl
6039 (&mhdr_res, items, &flow_attr, error))
6041 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
6043 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6044 if (flow_dv_convert_action_modify_ttl
6045 (&mhdr_res, actions, items,
6048 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
6050 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6051 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6052 if (flow_dv_convert_action_modify_tcp_seq
6053 (&mhdr_res, actions, error))
6055 action_flags |= actions->type ==
6056 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6057 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6058 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6061 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6062 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6063 if (flow_dv_convert_action_modify_tcp_ack
6064 (&mhdr_res, actions, error))
6066 action_flags |= actions->type ==
6067 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6068 MLX5_FLOW_ACTION_INC_TCP_ACK :
6069 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6071 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6072 if (flow_dv_convert_action_set_reg
6073 (&mhdr_res, actions, error))
6075 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6077 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6078 if (flow_dv_convert_action_copy_mreg
6079 (dev, &mhdr_res, actions, error))
6081 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6083 case RTE_FLOW_ACTION_TYPE_END:
6085 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
6086 /* create modify action if needed. */
6087 if (flow_dv_modify_hdr_resource_register
6088 (dev, &mhdr_res, dev_flow, error))
6090 dev_flow->dv.actions[modify_action_position] =
6091 dev_flow->dv.modify_hdr->verbs_action;
6097 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
6098 modify_action_position == UINT32_MAX)
6099 modify_action_position = actions_n++;
6101 dev_flow->dv.actions_n = actions_n;
6102 dev_flow->actions = action_flags;
6103 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6104 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6105 int item_type = items->type;
6107 switch (item_type) {
6108 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6109 flow_dv_translate_item_port_id(dev, match_mask,
6110 match_value, items);
6111 last_item = MLX5_FLOW_ITEM_PORT_ID;
6113 case RTE_FLOW_ITEM_TYPE_ETH:
6114 flow_dv_translate_item_eth(match_mask, match_value,
6116 matcher.priority = MLX5_PRIORITY_MAP_L2;
6117 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6118 MLX5_FLOW_LAYER_OUTER_L2;
6120 case RTE_FLOW_ITEM_TYPE_VLAN:
6121 flow_dv_translate_item_vlan(dev_flow,
6122 match_mask, match_value,
6124 matcher.priority = MLX5_PRIORITY_MAP_L2;
6125 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6126 MLX5_FLOW_LAYER_INNER_VLAN) :
6127 (MLX5_FLOW_LAYER_OUTER_L2 |
6128 MLX5_FLOW_LAYER_OUTER_VLAN);
6130 case RTE_FLOW_ITEM_TYPE_IPV4:
6131 mlx5_flow_tunnel_ip_check(items, next_protocol,
6132 &item_flags, &tunnel);
6133 flow_dv_translate_item_ipv4(match_mask, match_value,
6136 matcher.priority = MLX5_PRIORITY_MAP_L3;
6137 dev_flow->hash_fields |=
6138 mlx5_flow_hashfields_adjust
6140 MLX5_IPV4_LAYER_TYPES,
6141 MLX5_IPV4_IBV_RX_HASH);
6142 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6143 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6144 if (items->mask != NULL &&
6145 ((const struct rte_flow_item_ipv4 *)
6146 items->mask)->hdr.next_proto_id) {
6148 ((const struct rte_flow_item_ipv4 *)
6149 (items->spec))->hdr.next_proto_id;
6151 ((const struct rte_flow_item_ipv4 *)
6152 (items->mask))->hdr.next_proto_id;
6154 /* Reset for inner layer. */
6155 next_protocol = 0xff;
6158 case RTE_FLOW_ITEM_TYPE_IPV6:
6159 mlx5_flow_tunnel_ip_check(items, next_protocol,
6160 &item_flags, &tunnel);
6161 flow_dv_translate_item_ipv6(match_mask, match_value,
6164 matcher.priority = MLX5_PRIORITY_MAP_L3;
6165 dev_flow->hash_fields |=
6166 mlx5_flow_hashfields_adjust
6168 MLX5_IPV6_LAYER_TYPES,
6169 MLX5_IPV6_IBV_RX_HASH);
6170 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6171 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6172 if (items->mask != NULL &&
6173 ((const struct rte_flow_item_ipv6 *)
6174 items->mask)->hdr.proto) {
6176 ((const struct rte_flow_item_ipv6 *)
6177 items->spec)->hdr.proto;
6179 ((const struct rte_flow_item_ipv6 *)
6180 items->mask)->hdr.proto;
6182 /* Reset for inner layer. */
6183 next_protocol = 0xff;
6186 case RTE_FLOW_ITEM_TYPE_TCP:
6187 flow_dv_translate_item_tcp(match_mask, match_value,
6189 matcher.priority = MLX5_PRIORITY_MAP_L4;
6190 dev_flow->hash_fields |=
6191 mlx5_flow_hashfields_adjust
6192 (dev_flow, tunnel, ETH_RSS_TCP,
6193 IBV_RX_HASH_SRC_PORT_TCP |
6194 IBV_RX_HASH_DST_PORT_TCP);
6195 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6196 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6198 case RTE_FLOW_ITEM_TYPE_UDP:
6199 flow_dv_translate_item_udp(match_mask, match_value,
6201 matcher.priority = MLX5_PRIORITY_MAP_L4;
6202 dev_flow->hash_fields |=
6203 mlx5_flow_hashfields_adjust
6204 (dev_flow, tunnel, ETH_RSS_UDP,
6205 IBV_RX_HASH_SRC_PORT_UDP |
6206 IBV_RX_HASH_DST_PORT_UDP);
6207 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6208 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6210 case RTE_FLOW_ITEM_TYPE_GRE:
6211 flow_dv_translate_item_gre(match_mask, match_value,
6213 last_item = MLX5_FLOW_LAYER_GRE;
6215 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6216 flow_dv_translate_item_gre_key(match_mask,
6217 match_value, items);
6218 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6220 case RTE_FLOW_ITEM_TYPE_NVGRE:
6221 flow_dv_translate_item_nvgre(match_mask, match_value,
6223 last_item = MLX5_FLOW_LAYER_GRE;
6225 case RTE_FLOW_ITEM_TYPE_VXLAN:
6226 flow_dv_translate_item_vxlan(match_mask, match_value,
6228 last_item = MLX5_FLOW_LAYER_VXLAN;
6230 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6231 flow_dv_translate_item_vxlan(match_mask, match_value,
6233 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6235 case RTE_FLOW_ITEM_TYPE_GENEVE:
6236 flow_dv_translate_item_geneve(match_mask, match_value,
6238 last_item = MLX5_FLOW_LAYER_GENEVE;
6240 case RTE_FLOW_ITEM_TYPE_MPLS:
6241 flow_dv_translate_item_mpls(match_mask, match_value,
6242 items, last_item, tunnel);
6243 last_item = MLX5_FLOW_LAYER_MPLS;
6245 case RTE_FLOW_ITEM_TYPE_META:
6246 flow_dv_translate_item_meta(match_mask, match_value,
6248 last_item = MLX5_FLOW_ITEM_METADATA;
6250 case RTE_FLOW_ITEM_TYPE_ICMP:
6251 flow_dv_translate_item_icmp(match_mask, match_value,
6253 last_item = MLX5_FLOW_LAYER_ICMP;
6255 case RTE_FLOW_ITEM_TYPE_ICMP6:
6256 flow_dv_translate_item_icmp6(match_mask, match_value,
6258 last_item = MLX5_FLOW_LAYER_ICMP6;
6260 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6261 flow_dv_translate_mlx5_item_tag(match_mask,
6262 match_value, items);
6263 last_item = MLX5_FLOW_ITEM_TAG;
6265 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6266 flow_dv_translate_item_tx_queue(dev, match_mask,
6269 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6274 item_flags |= last_item;
6277 * In case of ingress traffic when E-Switch mode is enabled,
6278 * we have two cases where we need to set the source port manually.
6279 * The first one, is in case of Nic steering rule, and the second is
6280 * E-Switch rule where no port_id item was found. In both cases
6281 * the source port is set according the current port in use.
6283 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6284 (priv->representor || priv->master)) {
6285 if (flow_dv_translate_item_port_id(dev, match_mask,
6289 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6290 dev_flow->dv.value.buf));
6291 dev_flow->layers = item_flags;
6292 /* Register matcher. */
6293 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6295 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6297 matcher.egress = attr->egress;
6298 matcher.group = dev_flow->group;
6299 matcher.transfer = attr->transfer;
6300 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6306 * Apply the flow to the NIC, lock free,
6307 * (mutex should be acquired by caller).
6310 * Pointer to the Ethernet device structure.
6311 * @param[in, out] flow
6312 * Pointer to flow structure.
6314 * Pointer to error structure.
6317 * 0 on success, a negative errno value otherwise and rte_errno is set.
6320 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6321 struct rte_flow_error *error)
6323 struct mlx5_flow_dv *dv;
6324 struct mlx5_flow *dev_flow;
6325 struct mlx5_priv *priv = dev->data->dev_private;
6329 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6332 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6333 if (dev_flow->transfer) {
6334 dv->actions[n++] = priv->sh->esw_drop_action;
6336 dv->hrxq = mlx5_hrxq_drop_new(dev);
6340 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6342 "cannot get drop hash queue");
6345 dv->actions[n++] = dv->hrxq->action;
6347 } else if (dev_flow->actions &
6348 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6349 struct mlx5_hrxq *hrxq;
6351 assert(flow->rss.queue);
6352 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
6353 MLX5_RSS_HASH_KEY_LEN,
6354 dev_flow->hash_fields,
6356 flow->rss.queue_num);
6358 hrxq = mlx5_hrxq_new
6359 (dev, flow->rss.key,
6360 MLX5_RSS_HASH_KEY_LEN,
6361 dev_flow->hash_fields,
6363 flow->rss.queue_num,
6364 !!(dev_flow->layers &
6365 MLX5_FLOW_LAYER_TUNNEL));
6370 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6371 "cannot get hash queue");
6375 dv->actions[n++] = dv->hrxq->action;
6378 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6379 (void *)&dv->value, n,
6382 rte_flow_error_set(error, errno,
6383 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6385 "hardware refuses to create flow");
6388 if (priv->vmwa_context &&
6389 dev_flow->dv.vf_vlan.tag &&
6390 !dev_flow->dv.vf_vlan.created) {
6392 * The rule contains the VLAN pattern.
6393 * For VF we are going to create VLAN
6394 * interface to make hypervisor set correct
6395 * e-Switch vport context.
6397 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6402 err = rte_errno; /* Save rte_errno before cleanup. */
6403 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6404 struct mlx5_flow_dv *dv = &dev_flow->dv;
6406 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6407 mlx5_hrxq_drop_release(dev);
6409 mlx5_hrxq_release(dev, dv->hrxq);
6412 if (dev_flow->dv.vf_vlan.tag &&
6413 dev_flow->dv.vf_vlan.created)
6414 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6416 rte_errno = err; /* Restore rte_errno. */
6421 * Release the flow matcher.
6424 * Pointer to Ethernet device.
6426 * Pointer to mlx5_flow.
6429 * 1 while a reference on it exists, 0 when freed.
6432 flow_dv_matcher_release(struct rte_eth_dev *dev,
6433 struct mlx5_flow *flow)
6435 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6436 struct mlx5_priv *priv = dev->data->dev_private;
6437 struct mlx5_ibv_shared *sh = priv->sh;
6438 struct mlx5_flow_tbl_resource *tbl;
6440 assert(matcher->matcher_object);
6441 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6442 dev->data->port_id, (void *)matcher,
6443 rte_atomic32_read(&matcher->refcnt));
6444 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6445 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6446 (matcher->matcher_object));
6447 LIST_REMOVE(matcher, next);
6448 if (matcher->egress)
6449 tbl = &sh->tx_tbl[matcher->group];
6451 tbl = &sh->rx_tbl[matcher->group];
6452 flow_dv_tbl_resource_release(tbl);
6454 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6455 dev->data->port_id, (void *)matcher);
6462 * Release an encap/decap resource.
6465 * Pointer to mlx5_flow.
6468 * 1 while a reference on it exists, 0 when freed.
6471 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6473 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6474 flow->dv.encap_decap;
6476 assert(cache_resource->verbs_action);
6477 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6478 (void *)cache_resource,
6479 rte_atomic32_read(&cache_resource->refcnt));
6480 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6481 claim_zero(mlx5_glue->destroy_flow_action
6482 (cache_resource->verbs_action));
6483 LIST_REMOVE(cache_resource, next);
6484 rte_free(cache_resource);
6485 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6486 (void *)cache_resource);
6493 * Release an jump to table action resource.
6496 * Pointer to mlx5_flow.
6499 * 1 while a reference on it exists, 0 when freed.
6502 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6504 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6507 assert(cache_resource->action);
6508 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6509 (void *)cache_resource,
6510 rte_atomic32_read(&cache_resource->refcnt));
6511 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6512 claim_zero(mlx5_glue->destroy_flow_action
6513 (cache_resource->action));
6514 LIST_REMOVE(cache_resource, next);
6515 flow_dv_tbl_resource_release(cache_resource->tbl);
6516 rte_free(cache_resource);
6517 DRV_LOG(DEBUG, "jump table resource %p: removed",
6518 (void *)cache_resource);
6525 * Release a modify-header resource.
6528 * Pointer to mlx5_flow.
6531 * 1 while a reference on it exists, 0 when freed.
6534 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6536 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6537 flow->dv.modify_hdr;
6539 assert(cache_resource->verbs_action);
6540 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6541 (void *)cache_resource,
6542 rte_atomic32_read(&cache_resource->refcnt));
6543 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6544 claim_zero(mlx5_glue->destroy_flow_action
6545 (cache_resource->verbs_action));
6546 LIST_REMOVE(cache_resource, next);
6547 rte_free(cache_resource);
6548 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6549 (void *)cache_resource);
6556 * Release port ID action resource.
6559 * Pointer to mlx5_flow.
6562 * 1 while a reference on it exists, 0 when freed.
6565 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6567 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6568 flow->dv.port_id_action;
6570 assert(cache_resource->action);
6571 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6572 (void *)cache_resource,
6573 rte_atomic32_read(&cache_resource->refcnt));
6574 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6575 claim_zero(mlx5_glue->destroy_flow_action
6576 (cache_resource->action));
6577 LIST_REMOVE(cache_resource, next);
6578 rte_free(cache_resource);
6579 DRV_LOG(DEBUG, "port id action resource %p: removed",
6580 (void *)cache_resource);
6587 * Release push vlan action resource.
6590 * Pointer to mlx5_flow.
6593 * 1 while a reference on it exists, 0 when freed.
6596 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6598 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6599 flow->dv.push_vlan_res;
6601 assert(cache_resource->action);
6602 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6603 (void *)cache_resource,
6604 rte_atomic32_read(&cache_resource->refcnt));
6605 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6606 claim_zero(mlx5_glue->destroy_flow_action
6607 (cache_resource->action));
6608 LIST_REMOVE(cache_resource, next);
6609 rte_free(cache_resource);
6610 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6611 (void *)cache_resource);
6618 * Remove the flow from the NIC but keeps it in memory.
6619 * Lock free, (mutex should be acquired by caller).
6622 * Pointer to Ethernet device.
6623 * @param[in, out] flow
6624 * Pointer to flow structure.
6627 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6629 struct mlx5_flow_dv *dv;
6630 struct mlx5_flow *dev_flow;
6634 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6637 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6641 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6642 mlx5_hrxq_drop_release(dev);
6644 mlx5_hrxq_release(dev, dv->hrxq);
6647 if (dev_flow->dv.vf_vlan.tag &&
6648 dev_flow->dv.vf_vlan.created)
6649 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6654 * Remove the flow from the NIC and the memory.
6655 * Lock free, (mutex should be acquired by caller).
6658 * Pointer to the Ethernet device structure.
6659 * @param[in, out] flow
6660 * Pointer to flow structure.
6663 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6665 struct mlx5_flow *dev_flow;
6669 __flow_dv_remove(dev, flow);
6670 if (flow->counter) {
6671 flow_dv_counter_release(dev, flow->counter);
6672 flow->counter = NULL;
6674 while (!LIST_EMPTY(&flow->dev_flows)) {
6675 dev_flow = LIST_FIRST(&flow->dev_flows);
6676 LIST_REMOVE(dev_flow, next);
6677 if (dev_flow->dv.matcher)
6678 flow_dv_matcher_release(dev, dev_flow);
6679 if (dev_flow->dv.encap_decap)
6680 flow_dv_encap_decap_resource_release(dev_flow);
6681 if (dev_flow->dv.modify_hdr)
6682 flow_dv_modify_hdr_resource_release(dev_flow);
6683 if (dev_flow->dv.jump)
6684 flow_dv_jump_tbl_resource_release(dev_flow);
6685 if (dev_flow->dv.port_id_action)
6686 flow_dv_port_id_action_resource_release(dev_flow);
6687 if (dev_flow->dv.push_vlan_res)
6688 flow_dv_push_vlan_action_resource_release(dev_flow);
6689 if (dev_flow->dv.tag_resource)
6690 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
6696 * Query a dv flow rule for its statistics via devx.
6699 * Pointer to Ethernet device.
6701 * Pointer to the sub flow.
6703 * data retrieved by the query.
6705 * Perform verbose error reporting if not NULL.
6708 * 0 on success, a negative errno value otherwise and rte_errno is set.
6711 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6712 void *data, struct rte_flow_error *error)
6714 struct mlx5_priv *priv = dev->data->dev_private;
6715 struct rte_flow_query_count *qc = data;
6717 if (!priv->config.devx)
6718 return rte_flow_error_set(error, ENOTSUP,
6719 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6721 "counters are not supported");
6722 if (flow->counter) {
6723 uint64_t pkts, bytes;
6724 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6728 return rte_flow_error_set(error, -err,
6729 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6730 NULL, "cannot read counters");
6733 qc->hits = pkts - flow->counter->hits;
6734 qc->bytes = bytes - flow->counter->bytes;
6736 flow->counter->hits = pkts;
6737 flow->counter->bytes = bytes;
6741 return rte_flow_error_set(error, EINVAL,
6742 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6744 "counters are not available");
6750 * @see rte_flow_query()
6754 flow_dv_query(struct rte_eth_dev *dev,
6755 struct rte_flow *flow __rte_unused,
6756 const struct rte_flow_action *actions __rte_unused,
6757 void *data __rte_unused,
6758 struct rte_flow_error *error __rte_unused)
6762 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6763 switch (actions->type) {
6764 case RTE_FLOW_ACTION_TYPE_VOID:
6766 case RTE_FLOW_ACTION_TYPE_COUNT:
6767 ret = flow_dv_query_count(dev, flow, data, error);
6770 return rte_flow_error_set(error, ENOTSUP,
6771 RTE_FLOW_ERROR_TYPE_ACTION,
6773 "action not supported");
6780 * Mutex-protected thunk to lock-free __flow_dv_translate().
6783 flow_dv_translate(struct rte_eth_dev *dev,
6784 struct mlx5_flow *dev_flow,
6785 const struct rte_flow_attr *attr,
6786 const struct rte_flow_item items[],
6787 const struct rte_flow_action actions[],
6788 struct rte_flow_error *error)
6792 flow_dv_shared_lock(dev);
6793 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6794 flow_dv_shared_unlock(dev);
6799 * Mutex-protected thunk to lock-free __flow_dv_apply().
6802 flow_dv_apply(struct rte_eth_dev *dev,
6803 struct rte_flow *flow,
6804 struct rte_flow_error *error)
6808 flow_dv_shared_lock(dev);
6809 ret = __flow_dv_apply(dev, flow, error);
6810 flow_dv_shared_unlock(dev);
6815 * Mutex-protected thunk to lock-free __flow_dv_remove().
6818 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6820 flow_dv_shared_lock(dev);
6821 __flow_dv_remove(dev, flow);
6822 flow_dv_shared_unlock(dev);
6826 * Mutex-protected thunk to lock-free __flow_dv_destroy().
6829 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6831 flow_dv_shared_lock(dev);
6832 __flow_dv_destroy(dev, flow);
6833 flow_dv_shared_unlock(dev);
6836 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6837 .validate = flow_dv_validate,
6838 .prepare = flow_dv_prepare,
6839 .translate = flow_dv_translate,
6840 .apply = flow_dv_apply,
6841 .remove = flow_dv_remove,
6842 .destroy = flow_dv_destroy,
6843 .query = flow_dv_query,
6846 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */