1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
33 #include "mlx5_defs.h"
34 #include "mlx5_glue.h"
35 #include "mlx5_flow.h"
37 #include "mlx5_rxtx.h"
39 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
45 #ifndef HAVE_MLX5DV_DR_ESWITCH
46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
51 #ifndef HAVE_MLX5DV_DR
52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
55 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
56 sizeof(struct rte_flow_item_ipv4))
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
88 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
90 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
92 case RTE_FLOW_ITEM_TYPE_IPV4:
96 case RTE_FLOW_ITEM_TYPE_IPV6:
100 case RTE_FLOW_ITEM_TYPE_UDP:
104 case RTE_FLOW_ITEM_TYPE_TCP:
116 * Convert rte_mtr_color to mlx5 color.
125 rte_col_2_mlx5_col(enum rte_color rcol)
128 case RTE_COLOR_GREEN:
129 return MLX5_FLOW_COLOR_GREEN;
130 case RTE_COLOR_YELLOW:
131 return MLX5_FLOW_COLOR_YELLOW;
133 return MLX5_FLOW_COLOR_RED;
137 return MLX5_FLOW_COLOR_UNDEFINED;
140 struct field_modify_info {
141 uint32_t size; /* Size of field in protocol header, in bytes. */
142 uint32_t offset; /* Offset of field in protocol header, in bytes. */
143 enum mlx5_modification_field id;
146 struct field_modify_info modify_eth[] = {
147 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
148 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
149 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
150 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
154 struct field_modify_info modify_vlan_out_first_vid[] = {
155 /* Size in bits !!! */
156 {12, 0, MLX5_MODI_OUT_FIRST_VID},
160 struct field_modify_info modify_ipv4[] = {
161 {1, 1, MLX5_MODI_OUT_IP_DSCP},
162 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
163 {4, 12, MLX5_MODI_OUT_SIPV4},
164 {4, 16, MLX5_MODI_OUT_DIPV4},
168 struct field_modify_info modify_ipv6[] = {
169 {1, 0, MLX5_MODI_OUT_IP_DSCP},
170 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
171 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
172 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
173 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
174 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
175 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
176 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
177 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
178 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
182 struct field_modify_info modify_udp[] = {
183 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
184 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
188 struct field_modify_info modify_tcp[] = {
189 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
190 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
191 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
192 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
197 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
198 uint8_t next_protocol, uint64_t *item_flags,
201 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
202 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
203 if (next_protocol == IPPROTO_IPIP) {
204 *item_flags |= MLX5_FLOW_LAYER_IPIP;
207 if (next_protocol == IPPROTO_IPV6) {
208 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
214 * Acquire the synchronizing object to protect multithreaded access
215 * to shared dv context. Lock occurs only if context is actually
216 * shared, i.e. we have multiport IB device and representors are
220 * Pointer to the rte_eth_dev structure.
223 flow_dv_shared_lock(struct rte_eth_dev *dev)
225 struct mlx5_priv *priv = dev->data->dev_private;
226 struct mlx5_ibv_shared *sh = priv->sh;
228 if (sh->dv_refcnt > 1) {
231 ret = pthread_mutex_lock(&sh->dv_mutex);
238 flow_dv_shared_unlock(struct rte_eth_dev *dev)
240 struct mlx5_priv *priv = dev->data->dev_private;
241 struct mlx5_ibv_shared *sh = priv->sh;
243 if (sh->dv_refcnt > 1) {
246 ret = pthread_mutex_unlock(&sh->dv_mutex);
252 /* Update VLAN's VID/PCP based on input rte_flow_action.
255 * Pointer to struct rte_flow_action.
257 * Pointer to struct rte_vlan_hdr.
260 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
261 struct rte_vlan_hdr *vlan)
264 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
266 ((const struct rte_flow_action_of_set_vlan_pcp *)
267 action->conf)->vlan_pcp;
268 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
269 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
270 vlan->vlan_tci |= vlan_tci;
271 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
272 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
273 vlan->vlan_tci |= rte_be_to_cpu_16
274 (((const struct rte_flow_action_of_set_vlan_vid *)
275 action->conf)->vlan_vid);
280 * Fetch 1, 2, 3 or 4 byte field from the byte array
281 * and return as unsigned integer in host-endian format.
284 * Pointer to data array.
286 * Size of field to extract.
289 * converted field in host endian format.
291 static inline uint32_t
292 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
301 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
304 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
305 ret = (ret << 8) | *(data + sizeof(uint16_t));
308 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
319 * Convert modify-header action to DV specification.
321 * Data length of each action is determined by provided field description
322 * and the item mask. Data bit offset and width of each action is determined
323 * by provided item mask.
326 * Pointer to item specification.
328 * Pointer to field modification information.
329 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
330 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
331 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
333 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
334 * Negative offset value sets the same offset as source offset.
335 * size field is ignored, value is taken from source field.
336 * @param[in,out] resource
337 * Pointer to the modify-header resource.
339 * Type of modification.
341 * Pointer to the error structure.
344 * 0 on success, a negative errno value otherwise and rte_errno is set.
347 flow_dv_convert_modify_action(struct rte_flow_item *item,
348 struct field_modify_info *field,
349 struct field_modify_info *dcopy,
350 struct mlx5_flow_dv_modify_hdr_resource *resource,
351 uint32_t type, struct rte_flow_error *error)
353 uint32_t i = resource->actions_num;
354 struct mlx5_modification_cmd *actions = resource->actions;
357 * The item and mask are provided in big-endian format.
358 * The fields should be presented as in big-endian format either.
359 * Mask must be always present, it defines the actual field width.
369 if (i >= MLX5_MAX_MODIFY_NUM)
370 return rte_flow_error_set(error, EINVAL,
371 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
372 "too many items to modify");
373 /* Fetch variable byte size mask from the array. */
374 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
375 field->offset, field->size);
380 /* Deduce actual data width in bits from mask value. */
381 off_b = rte_bsf32(mask);
382 size_b = sizeof(uint32_t) * CHAR_BIT -
383 off_b - __builtin_clz(mask);
385 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
386 actions[i].action_type = type;
387 actions[i].field = field->id;
388 actions[i].offset = off_b;
389 actions[i].length = size_b;
390 /* Convert entire record to expected big-endian format. */
391 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
392 if (type == MLX5_MODIFICATION_TYPE_COPY) {
394 actions[i].dst_field = dcopy->id;
395 actions[i].dst_offset =
396 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
397 /* Convert entire record to big-endian format. */
398 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
401 data = flow_dv_fetch_field((const uint8_t *)item->spec +
402 field->offset, field->size);
403 /* Shift out the trailing masked bits from data. */
404 data = (data & mask) >> off_b;
405 actions[i].data1 = rte_cpu_to_be_32(data);
409 } while (field->size);
410 if (resource->actions_num == i)
411 return rte_flow_error_set(error, EINVAL,
412 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
413 "invalid modification flow item");
414 resource->actions_num = i;
419 * Convert modify-header set IPv4 address action to DV specification.
421 * @param[in,out] resource
422 * Pointer to the modify-header resource.
424 * Pointer to action specification.
426 * Pointer to the error structure.
429 * 0 on success, a negative errno value otherwise and rte_errno is set.
432 flow_dv_convert_action_modify_ipv4
433 (struct mlx5_flow_dv_modify_hdr_resource *resource,
434 const struct rte_flow_action *action,
435 struct rte_flow_error *error)
437 const struct rte_flow_action_set_ipv4 *conf =
438 (const struct rte_flow_action_set_ipv4 *)(action->conf);
439 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
440 struct rte_flow_item_ipv4 ipv4;
441 struct rte_flow_item_ipv4 ipv4_mask;
443 memset(&ipv4, 0, sizeof(ipv4));
444 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
445 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
446 ipv4.hdr.src_addr = conf->ipv4_addr;
447 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
449 ipv4.hdr.dst_addr = conf->ipv4_addr;
450 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
453 item.mask = &ipv4_mask;
454 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
455 MLX5_MODIFICATION_TYPE_SET, error);
459 * Convert modify-header set IPv6 address action to DV specification.
461 * @param[in,out] resource
462 * Pointer to the modify-header resource.
464 * Pointer to action specification.
466 * Pointer to the error structure.
469 * 0 on success, a negative errno value otherwise and rte_errno is set.
472 flow_dv_convert_action_modify_ipv6
473 (struct mlx5_flow_dv_modify_hdr_resource *resource,
474 const struct rte_flow_action *action,
475 struct rte_flow_error *error)
477 const struct rte_flow_action_set_ipv6 *conf =
478 (const struct rte_flow_action_set_ipv6 *)(action->conf);
479 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
480 struct rte_flow_item_ipv6 ipv6;
481 struct rte_flow_item_ipv6 ipv6_mask;
483 memset(&ipv6, 0, sizeof(ipv6));
484 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
485 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
486 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
487 sizeof(ipv6.hdr.src_addr));
488 memcpy(&ipv6_mask.hdr.src_addr,
489 &rte_flow_item_ipv6_mask.hdr.src_addr,
490 sizeof(ipv6.hdr.src_addr));
492 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
493 sizeof(ipv6.hdr.dst_addr));
494 memcpy(&ipv6_mask.hdr.dst_addr,
495 &rte_flow_item_ipv6_mask.hdr.dst_addr,
496 sizeof(ipv6.hdr.dst_addr));
499 item.mask = &ipv6_mask;
500 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
501 MLX5_MODIFICATION_TYPE_SET, error);
505 * Convert modify-header set MAC address action to DV specification.
507 * @param[in,out] resource
508 * Pointer to the modify-header resource.
510 * Pointer to action specification.
512 * Pointer to the error structure.
515 * 0 on success, a negative errno value otherwise and rte_errno is set.
518 flow_dv_convert_action_modify_mac
519 (struct mlx5_flow_dv_modify_hdr_resource *resource,
520 const struct rte_flow_action *action,
521 struct rte_flow_error *error)
523 const struct rte_flow_action_set_mac *conf =
524 (const struct rte_flow_action_set_mac *)(action->conf);
525 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
526 struct rte_flow_item_eth eth;
527 struct rte_flow_item_eth eth_mask;
529 memset(ð, 0, sizeof(eth));
530 memset(ð_mask, 0, sizeof(eth_mask));
531 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
532 memcpy(ð.src.addr_bytes, &conf->mac_addr,
533 sizeof(eth.src.addr_bytes));
534 memcpy(ð_mask.src.addr_bytes,
535 &rte_flow_item_eth_mask.src.addr_bytes,
536 sizeof(eth_mask.src.addr_bytes));
538 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
539 sizeof(eth.dst.addr_bytes));
540 memcpy(ð_mask.dst.addr_bytes,
541 &rte_flow_item_eth_mask.dst.addr_bytes,
542 sizeof(eth_mask.dst.addr_bytes));
545 item.mask = ð_mask;
546 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
547 MLX5_MODIFICATION_TYPE_SET, error);
551 * Convert modify-header set VLAN VID action to DV specification.
553 * @param[in,out] resource
554 * Pointer to the modify-header resource.
556 * Pointer to action specification.
558 * Pointer to the error structure.
561 * 0 on success, a negative errno value otherwise and rte_errno is set.
564 flow_dv_convert_action_modify_vlan_vid
565 (struct mlx5_flow_dv_modify_hdr_resource *resource,
566 const struct rte_flow_action *action,
567 struct rte_flow_error *error)
569 const struct rte_flow_action_of_set_vlan_vid *conf =
570 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
571 int i = resource->actions_num;
572 struct mlx5_modification_cmd *actions = &resource->actions[i];
573 struct field_modify_info *field = modify_vlan_out_first_vid;
575 if (i >= MLX5_MAX_MODIFY_NUM)
576 return rte_flow_error_set(error, EINVAL,
577 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
578 "too many items to modify");
579 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
580 actions[i].field = field->id;
581 actions[i].length = field->size;
582 actions[i].offset = field->offset;
583 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
584 actions[i].data1 = conf->vlan_vid;
585 actions[i].data1 = actions[i].data1 << 16;
586 resource->actions_num = ++i;
591 * Convert modify-header set TP action to DV specification.
593 * @param[in,out] resource
594 * Pointer to the modify-header resource.
596 * Pointer to action specification.
598 * Pointer to rte_flow_item objects list.
600 * Pointer to flow attributes structure.
602 * Pointer to the error structure.
605 * 0 on success, a negative errno value otherwise and rte_errno is set.
608 flow_dv_convert_action_modify_tp
609 (struct mlx5_flow_dv_modify_hdr_resource *resource,
610 const struct rte_flow_action *action,
611 const struct rte_flow_item *items,
612 union flow_dv_attr *attr,
613 struct rte_flow_error *error)
615 const struct rte_flow_action_set_tp *conf =
616 (const struct rte_flow_action_set_tp *)(action->conf);
617 struct rte_flow_item item;
618 struct rte_flow_item_udp udp;
619 struct rte_flow_item_udp udp_mask;
620 struct rte_flow_item_tcp tcp;
621 struct rte_flow_item_tcp tcp_mask;
622 struct field_modify_info *field;
625 flow_dv_attr_init(items, attr);
627 memset(&udp, 0, sizeof(udp));
628 memset(&udp_mask, 0, sizeof(udp_mask));
629 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
630 udp.hdr.src_port = conf->port;
631 udp_mask.hdr.src_port =
632 rte_flow_item_udp_mask.hdr.src_port;
634 udp.hdr.dst_port = conf->port;
635 udp_mask.hdr.dst_port =
636 rte_flow_item_udp_mask.hdr.dst_port;
638 item.type = RTE_FLOW_ITEM_TYPE_UDP;
640 item.mask = &udp_mask;
644 memset(&tcp, 0, sizeof(tcp));
645 memset(&tcp_mask, 0, sizeof(tcp_mask));
646 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
647 tcp.hdr.src_port = conf->port;
648 tcp_mask.hdr.src_port =
649 rte_flow_item_tcp_mask.hdr.src_port;
651 tcp.hdr.dst_port = conf->port;
652 tcp_mask.hdr.dst_port =
653 rte_flow_item_tcp_mask.hdr.dst_port;
655 item.type = RTE_FLOW_ITEM_TYPE_TCP;
657 item.mask = &tcp_mask;
660 return flow_dv_convert_modify_action(&item, field, NULL, resource,
661 MLX5_MODIFICATION_TYPE_SET, error);
665 * Convert modify-header set TTL action to DV specification.
667 * @param[in,out] resource
668 * Pointer to the modify-header resource.
670 * Pointer to action specification.
672 * Pointer to rte_flow_item objects list.
674 * Pointer to flow attributes structure.
676 * Pointer to the error structure.
679 * 0 on success, a negative errno value otherwise and rte_errno is set.
682 flow_dv_convert_action_modify_ttl
683 (struct mlx5_flow_dv_modify_hdr_resource *resource,
684 const struct rte_flow_action *action,
685 const struct rte_flow_item *items,
686 union flow_dv_attr *attr,
687 struct rte_flow_error *error)
689 const struct rte_flow_action_set_ttl *conf =
690 (const struct rte_flow_action_set_ttl *)(action->conf);
691 struct rte_flow_item item;
692 struct rte_flow_item_ipv4 ipv4;
693 struct rte_flow_item_ipv4 ipv4_mask;
694 struct rte_flow_item_ipv6 ipv6;
695 struct rte_flow_item_ipv6 ipv6_mask;
696 struct field_modify_info *field;
699 flow_dv_attr_init(items, attr);
701 memset(&ipv4, 0, sizeof(ipv4));
702 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
703 ipv4.hdr.time_to_live = conf->ttl_value;
704 ipv4_mask.hdr.time_to_live = 0xFF;
705 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
707 item.mask = &ipv4_mask;
711 memset(&ipv6, 0, sizeof(ipv6));
712 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
713 ipv6.hdr.hop_limits = conf->ttl_value;
714 ipv6_mask.hdr.hop_limits = 0xFF;
715 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
717 item.mask = &ipv6_mask;
720 return flow_dv_convert_modify_action(&item, field, NULL, resource,
721 MLX5_MODIFICATION_TYPE_SET, error);
725 * Convert modify-header decrement TTL action to DV specification.
727 * @param[in,out] resource
728 * Pointer to the modify-header resource.
730 * Pointer to action specification.
732 * Pointer to rte_flow_item objects list.
734 * Pointer to flow attributes structure.
736 * Pointer to the error structure.
739 * 0 on success, a negative errno value otherwise and rte_errno is set.
742 flow_dv_convert_action_modify_dec_ttl
743 (struct mlx5_flow_dv_modify_hdr_resource *resource,
744 const struct rte_flow_item *items,
745 union flow_dv_attr *attr,
746 struct rte_flow_error *error)
748 struct rte_flow_item item;
749 struct rte_flow_item_ipv4 ipv4;
750 struct rte_flow_item_ipv4 ipv4_mask;
751 struct rte_flow_item_ipv6 ipv6;
752 struct rte_flow_item_ipv6 ipv6_mask;
753 struct field_modify_info *field;
756 flow_dv_attr_init(items, attr);
758 memset(&ipv4, 0, sizeof(ipv4));
759 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
760 ipv4.hdr.time_to_live = 0xFF;
761 ipv4_mask.hdr.time_to_live = 0xFF;
762 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
764 item.mask = &ipv4_mask;
768 memset(&ipv6, 0, sizeof(ipv6));
769 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
770 ipv6.hdr.hop_limits = 0xFF;
771 ipv6_mask.hdr.hop_limits = 0xFF;
772 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
774 item.mask = &ipv6_mask;
777 return flow_dv_convert_modify_action(&item, field, NULL, resource,
778 MLX5_MODIFICATION_TYPE_ADD, error);
782 * Convert modify-header increment/decrement TCP Sequence number
783 * to DV specification.
785 * @param[in,out] resource
786 * Pointer to the modify-header resource.
788 * Pointer to action specification.
790 * Pointer to the error structure.
793 * 0 on success, a negative errno value otherwise and rte_errno is set.
796 flow_dv_convert_action_modify_tcp_seq
797 (struct mlx5_flow_dv_modify_hdr_resource *resource,
798 const struct rte_flow_action *action,
799 struct rte_flow_error *error)
801 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
802 uint64_t value = rte_be_to_cpu_32(*conf);
803 struct rte_flow_item item;
804 struct rte_flow_item_tcp tcp;
805 struct rte_flow_item_tcp tcp_mask;
807 memset(&tcp, 0, sizeof(tcp));
808 memset(&tcp_mask, 0, sizeof(tcp_mask));
809 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
811 * The HW has no decrement operation, only increment operation.
812 * To simulate decrement X from Y using increment operation
813 * we need to add UINT32_MAX X times to Y.
814 * Each adding of UINT32_MAX decrements Y by 1.
817 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
818 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
819 item.type = RTE_FLOW_ITEM_TYPE_TCP;
821 item.mask = &tcp_mask;
822 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
823 MLX5_MODIFICATION_TYPE_ADD, error);
827 * Convert modify-header increment/decrement TCP Acknowledgment number
828 * to DV specification.
830 * @param[in,out] resource
831 * Pointer to the modify-header resource.
833 * Pointer to action specification.
835 * Pointer to the error structure.
838 * 0 on success, a negative errno value otherwise and rte_errno is set.
841 flow_dv_convert_action_modify_tcp_ack
842 (struct mlx5_flow_dv_modify_hdr_resource *resource,
843 const struct rte_flow_action *action,
844 struct rte_flow_error *error)
846 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
847 uint64_t value = rte_be_to_cpu_32(*conf);
848 struct rte_flow_item item;
849 struct rte_flow_item_tcp tcp;
850 struct rte_flow_item_tcp tcp_mask;
852 memset(&tcp, 0, sizeof(tcp));
853 memset(&tcp_mask, 0, sizeof(tcp_mask));
854 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
856 * The HW has no decrement operation, only increment operation.
857 * To simulate decrement X from Y using increment operation
858 * we need to add UINT32_MAX X times to Y.
859 * Each adding of UINT32_MAX decrements Y by 1.
862 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
863 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
864 item.type = RTE_FLOW_ITEM_TYPE_TCP;
866 item.mask = &tcp_mask;
867 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
868 MLX5_MODIFICATION_TYPE_ADD, error);
871 static enum mlx5_modification_field reg_to_field[] = {
872 [REG_NONE] = MLX5_MODI_OUT_NONE,
873 [REG_A] = MLX5_MODI_META_DATA_REG_A,
874 [REG_B] = MLX5_MODI_META_DATA_REG_B,
875 [REG_C_0] = MLX5_MODI_META_REG_C_0,
876 [REG_C_1] = MLX5_MODI_META_REG_C_1,
877 [REG_C_2] = MLX5_MODI_META_REG_C_2,
878 [REG_C_3] = MLX5_MODI_META_REG_C_3,
879 [REG_C_4] = MLX5_MODI_META_REG_C_4,
880 [REG_C_5] = MLX5_MODI_META_REG_C_5,
881 [REG_C_6] = MLX5_MODI_META_REG_C_6,
882 [REG_C_7] = MLX5_MODI_META_REG_C_7,
886 * Convert register set to DV specification.
888 * @param[in,out] resource
889 * Pointer to the modify-header resource.
891 * Pointer to action specification.
893 * Pointer to the error structure.
896 * 0 on success, a negative errno value otherwise and rte_errno is set.
899 flow_dv_convert_action_set_reg
900 (struct mlx5_flow_dv_modify_hdr_resource *resource,
901 const struct rte_flow_action *action,
902 struct rte_flow_error *error)
904 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
905 struct mlx5_modification_cmd *actions = resource->actions;
906 uint32_t i = resource->actions_num;
908 if (i >= MLX5_MAX_MODIFY_NUM)
909 return rte_flow_error_set(error, EINVAL,
910 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
911 "too many items to modify");
912 assert(conf->id != REG_NONE);
913 assert(conf->id < RTE_DIM(reg_to_field));
914 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
915 actions[i].field = reg_to_field[conf->id];
916 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
917 actions[i].data1 = rte_cpu_to_be_32(conf->data);
919 resource->actions_num = i;
924 * Convert SET_TAG action to DV specification.
927 * Pointer to the rte_eth_dev structure.
928 * @param[in,out] resource
929 * Pointer to the modify-header resource.
931 * Pointer to action specification.
933 * Pointer to the error structure.
936 * 0 on success, a negative errno value otherwise and rte_errno is set.
939 flow_dv_convert_action_set_tag
940 (struct rte_eth_dev *dev,
941 struct mlx5_flow_dv_modify_hdr_resource *resource,
942 const struct rte_flow_action_set_tag *conf,
943 struct rte_flow_error *error)
945 rte_be32_t data = rte_cpu_to_be_32(conf->data);
946 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
947 struct rte_flow_item item = {
951 struct field_modify_info reg_c_x[] = {
954 enum mlx5_modification_field reg_type;
957 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
960 assert(ret != REG_NONE);
961 assert((unsigned int)ret < RTE_DIM(reg_to_field));
962 reg_type = reg_to_field[ret];
963 assert(reg_type > 0);
964 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
965 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
966 MLX5_MODIFICATION_TYPE_SET, error);
970 * Convert internal COPY_REG action to DV specification.
973 * Pointer to the rte_eth_dev structure.
975 * Pointer to the modify-header resource.
977 * Pointer to action specification.
979 * Pointer to the error structure.
982 * 0 on success, a negative errno value otherwise and rte_errno is set.
985 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
986 struct mlx5_flow_dv_modify_hdr_resource *res,
987 const struct rte_flow_action *action,
988 struct rte_flow_error *error)
990 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
991 rte_be32_t mask = RTE_BE32(UINT32_MAX);
992 struct rte_flow_item item = {
996 struct field_modify_info reg_src[] = {
997 {4, 0, reg_to_field[conf->src]},
1000 struct field_modify_info reg_dst = {
1002 .id = reg_to_field[conf->dst],
1004 /* Adjust reg_c[0] usage according to reported mask. */
1005 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1006 struct mlx5_priv *priv = dev->data->dev_private;
1007 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1010 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1011 if (conf->dst == REG_C_0) {
1012 /* Copy to reg_c[0], within mask only. */
1013 reg_dst.offset = rte_bsf32(reg_c0);
1015 * Mask is ignoring the enianness, because
1016 * there is no conversion in datapath.
1018 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1019 /* Copy from destination lower bits to reg_c[0]. */
1020 mask = reg_c0 >> reg_dst.offset;
1022 /* Copy from destination upper bits to reg_c[0]. */
1023 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1024 rte_fls_u32(reg_c0));
1027 mask = rte_cpu_to_be_32(reg_c0);
1028 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1029 /* Copy from reg_c[0] to destination lower bits. */
1032 /* Copy from reg_c[0] to destination upper bits. */
1033 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1034 (rte_fls_u32(reg_c0) -
1039 return flow_dv_convert_modify_action(&item,
1040 reg_src, ®_dst, res,
1041 MLX5_MODIFICATION_TYPE_COPY,
1046 * Convert MARK action to DV specification. This routine is used
1047 * in extensive metadata only and requires metadata register to be
1048 * handled. In legacy mode hardware tag resource is engaged.
1051 * Pointer to the rte_eth_dev structure.
1053 * Pointer to MARK action specification.
1054 * @param[in,out] resource
1055 * Pointer to the modify-header resource.
1057 * Pointer to the error structure.
1060 * 0 on success, a negative errno value otherwise and rte_errno is set.
1063 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1064 const struct rte_flow_action_mark *conf,
1065 struct mlx5_flow_dv_modify_hdr_resource *resource,
1066 struct rte_flow_error *error)
1068 struct mlx5_priv *priv = dev->data->dev_private;
1069 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1070 priv->sh->dv_mark_mask);
1071 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1072 struct rte_flow_item item = {
1076 struct field_modify_info reg_c_x[] = {
1077 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1080 enum modify_reg reg;
1083 return rte_flow_error_set(error, EINVAL,
1084 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1085 NULL, "zero mark action mask");
1086 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1090 if (reg == REG_C_0) {
1091 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1092 uint32_t shl_c0 = rte_bsf32(msk_c0);
1094 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1095 mask = rte_cpu_to_be_32(mask) & msk_c0;
1096 mask = rte_cpu_to_be_32(mask << shl_c0);
1098 reg_c_x[0].id = reg_to_field[reg];
1099 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1100 MLX5_MODIFICATION_TYPE_SET, error);
1104 * Get metadata register index for specified steering domain.
1107 * Pointer to the rte_eth_dev structure.
1109 * Attributes of flow to determine steering domain.
1111 * Pointer to the error structure.
1114 * positive index on success, a negative errno value otherwise
1115 * and rte_errno is set.
1117 static enum modify_reg
1118 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1119 const struct rte_flow_attr *attr,
1120 struct rte_flow_error *error)
1122 enum modify_reg reg =
1123 mlx5_flow_get_reg_id(dev, attr->transfer ?
1127 MLX5_METADATA_RX, 0, error);
1129 return rte_flow_error_set(error,
1130 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1131 NULL, "unavailable "
1132 "metadata register");
1137 * Convert SET_META action to DV specification.
1140 * Pointer to the rte_eth_dev structure.
1141 * @param[in,out] resource
1142 * Pointer to the modify-header resource.
1144 * Attributes of flow that includes this item.
1146 * Pointer to action specification.
1148 * Pointer to the error structure.
1151 * 0 on success, a negative errno value otherwise and rte_errno is set.
1154 flow_dv_convert_action_set_meta
1155 (struct rte_eth_dev *dev,
1156 struct mlx5_flow_dv_modify_hdr_resource *resource,
1157 const struct rte_flow_attr *attr,
1158 const struct rte_flow_action_set_meta *conf,
1159 struct rte_flow_error *error)
1161 uint32_t data = conf->data;
1162 uint32_t mask = conf->mask;
1163 struct rte_flow_item item = {
1167 struct field_modify_info reg_c_x[] = {
1170 enum modify_reg reg = flow_dv_get_metadata_reg(dev, attr, error);
1175 * In datapath code there is no endianness
1176 * coversions for perfromance reasons, all
1177 * pattern conversions are done in rte_flow.
1179 if (reg == REG_C_0) {
1180 struct mlx5_priv *priv = dev->data->dev_private;
1181 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1185 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1186 shl_c0 = rte_bsf32(msk_c0);
1188 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1192 assert(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1194 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1195 /* The routine expects parameters in memory as big-endian ones. */
1196 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1197 MLX5_MODIFICATION_TYPE_SET, error);
1201 * Convert modify-header set IPv4 DSCP action to DV specification.
1203 * @param[in,out] resource
1204 * Pointer to the modify-header resource.
1206 * Pointer to action specification.
1208 * Pointer to the error structure.
1211 * 0 on success, a negative errno value otherwise and rte_errno is set.
1214 flow_dv_convert_action_modify_ipv4_dscp
1215 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1216 const struct rte_flow_action *action,
1217 struct rte_flow_error *error)
1219 const struct rte_flow_action_set_dscp *conf =
1220 (const struct rte_flow_action_set_dscp *)(action->conf);
1221 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1222 struct rte_flow_item_ipv4 ipv4;
1223 struct rte_flow_item_ipv4 ipv4_mask;
1225 memset(&ipv4, 0, sizeof(ipv4));
1226 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1227 ipv4.hdr.type_of_service = conf->dscp;
1228 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1230 item.mask = &ipv4_mask;
1231 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1232 MLX5_MODIFICATION_TYPE_SET, error);
1236 * Convert modify-header set IPv6 DSCP action to DV specification.
1238 * @param[in,out] resource
1239 * Pointer to the modify-header resource.
1241 * Pointer to action specification.
1243 * Pointer to the error structure.
1246 * 0 on success, a negative errno value otherwise and rte_errno is set.
1249 flow_dv_convert_action_modify_ipv6_dscp
1250 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1251 const struct rte_flow_action *action,
1252 struct rte_flow_error *error)
1254 const struct rte_flow_action_set_dscp *conf =
1255 (const struct rte_flow_action_set_dscp *)(action->conf);
1256 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1257 struct rte_flow_item_ipv6 ipv6;
1258 struct rte_flow_item_ipv6 ipv6_mask;
1260 memset(&ipv6, 0, sizeof(ipv6));
1261 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1263 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1264 * rdma-core only accept the DSCP bits byte aligned start from
1265 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1266 * bits in IPv6 case as rdma-core requires byte aligned value.
1268 ipv6.hdr.vtc_flow = conf->dscp;
1269 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1271 item.mask = &ipv6_mask;
1272 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1273 MLX5_MODIFICATION_TYPE_SET, error);
1277 * Validate MARK item.
1280 * Pointer to the rte_eth_dev structure.
1282 * Item specification.
1284 * Attributes of flow that includes this item.
1286 * Pointer to error structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1293 const struct rte_flow_item *item,
1294 const struct rte_flow_attr *attr __rte_unused,
1295 struct rte_flow_error *error)
1297 struct mlx5_priv *priv = dev->data->dev_private;
1298 struct mlx5_dev_config *config = &priv->config;
1299 const struct rte_flow_item_mark *spec = item->spec;
1300 const struct rte_flow_item_mark *mask = item->mask;
1301 const struct rte_flow_item_mark nic_mask = {
1302 .id = priv->sh->dv_mark_mask,
1306 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1307 return rte_flow_error_set(error, ENOTSUP,
1308 RTE_FLOW_ERROR_TYPE_ITEM, item,
1309 "extended metadata feature"
1311 if (!mlx5_flow_ext_mreg_supported(dev))
1312 return rte_flow_error_set(error, ENOTSUP,
1313 RTE_FLOW_ERROR_TYPE_ITEM, item,
1314 "extended metadata register"
1315 " isn't supported");
1317 return rte_flow_error_set(error, ENOTSUP,
1318 RTE_FLOW_ERROR_TYPE_ITEM, item,
1319 "extended metadata register"
1320 " isn't available");
1321 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1325 return rte_flow_error_set(error, EINVAL,
1326 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1328 "data cannot be empty");
1329 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1330 return rte_flow_error_set(error, EINVAL,
1331 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1333 "mark id exceeds the limit");
1336 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1337 (const uint8_t *)&nic_mask,
1338 sizeof(struct rte_flow_item_mark),
1346 * Validate META item.
1349 * Pointer to the rte_eth_dev structure.
1351 * Item specification.
1353 * Attributes of flow that includes this item.
1355 * Pointer to error structure.
1358 * 0 on success, a negative errno value otherwise and rte_errno is set.
1361 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1362 const struct rte_flow_item *item,
1363 const struct rte_flow_attr *attr,
1364 struct rte_flow_error *error)
1366 struct mlx5_priv *priv = dev->data->dev_private;
1367 struct mlx5_dev_config *config = &priv->config;
1368 const struct rte_flow_item_meta *spec = item->spec;
1369 const struct rte_flow_item_meta *mask = item->mask;
1370 struct rte_flow_item_meta nic_mask = {
1373 enum modify_reg reg;
1377 return rte_flow_error_set(error, EINVAL,
1378 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1380 "data cannot be empty");
1382 return rte_flow_error_set(error, EINVAL,
1383 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1384 "data cannot be zero");
1385 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1386 if (!mlx5_flow_ext_mreg_supported(dev))
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata register"
1390 " isn't supported");
1391 reg = flow_dv_get_metadata_reg(dev, attr, error);
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1400 nic_mask.data = priv->sh->dv_meta_mask;
1403 mask = &rte_flow_item_meta_mask;
1404 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1405 (const uint8_t *)&nic_mask,
1406 sizeof(struct rte_flow_item_meta),
1412 * Validate TAG item.
1415 * Pointer to the rte_eth_dev structure.
1417 * Item specification.
1419 * Attributes of flow that includes this item.
1421 * Pointer to error structure.
1424 * 0 on success, a negative errno value otherwise and rte_errno is set.
1427 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1428 const struct rte_flow_item *item,
1429 const struct rte_flow_attr *attr __rte_unused,
1430 struct rte_flow_error *error)
1432 const struct rte_flow_item_tag *spec = item->spec;
1433 const struct rte_flow_item_tag *mask = item->mask;
1434 const struct rte_flow_item_tag nic_mask = {
1435 .data = RTE_BE32(UINT32_MAX),
1440 if (!mlx5_flow_ext_mreg_supported(dev))
1441 return rte_flow_error_set(error, ENOTSUP,
1442 RTE_FLOW_ERROR_TYPE_ITEM, item,
1443 "extensive metadata register"
1444 " isn't supported");
1446 return rte_flow_error_set(error, EINVAL,
1447 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1449 "data cannot be empty");
1451 mask = &rte_flow_item_tag_mask;
1452 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1453 (const uint8_t *)&nic_mask,
1454 sizeof(struct rte_flow_item_tag),
1458 if (mask->index != 0xff)
1459 return rte_flow_error_set(error, EINVAL,
1460 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1461 "partial mask for tag index"
1462 " is not supported");
1463 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1466 assert(ret != REG_NONE);
1471 * Validate vport item.
1474 * Pointer to the rte_eth_dev structure.
1476 * Item specification.
1478 * Attributes of flow that includes this item.
1479 * @param[in] item_flags
1480 * Bit-fields that holds the items detected until now.
1482 * Pointer to error structure.
1485 * 0 on success, a negative errno value otherwise and rte_errno is set.
1488 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1489 const struct rte_flow_item *item,
1490 const struct rte_flow_attr *attr,
1491 uint64_t item_flags,
1492 struct rte_flow_error *error)
1494 const struct rte_flow_item_port_id *spec = item->spec;
1495 const struct rte_flow_item_port_id *mask = item->mask;
1496 const struct rte_flow_item_port_id switch_mask = {
1499 struct mlx5_priv *esw_priv;
1500 struct mlx5_priv *dev_priv;
1503 if (!attr->transfer)
1504 return rte_flow_error_set(error, EINVAL,
1505 RTE_FLOW_ERROR_TYPE_ITEM,
1507 "match on port id is valid only"
1508 " when transfer flag is enabled");
1509 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1510 return rte_flow_error_set(error, ENOTSUP,
1511 RTE_FLOW_ERROR_TYPE_ITEM, item,
1512 "multiple source ports are not"
1515 mask = &switch_mask;
1516 if (mask->id != 0xffffffff)
1517 return rte_flow_error_set(error, ENOTSUP,
1518 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1520 "no support for partial mask on"
1522 ret = mlx5_flow_item_acceptable
1523 (item, (const uint8_t *)mask,
1524 (const uint8_t *)&rte_flow_item_port_id_mask,
1525 sizeof(struct rte_flow_item_port_id),
1531 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1533 return rte_flow_error_set(error, rte_errno,
1534 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1535 "failed to obtain E-Switch info for"
1537 dev_priv = mlx5_dev_to_eswitch_info(dev);
1539 return rte_flow_error_set(error, rte_errno,
1540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1542 "failed to obtain E-Switch info");
1543 if (esw_priv->domain_id != dev_priv->domain_id)
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1546 "cannot match on a port from a"
1547 " different E-Switch");
1552 * Validate GTP item.
1555 * Pointer to the rte_eth_dev structure.
1557 * Item specification.
1558 * @param[in] item_flags
1559 * Bit-fields that holds the items detected until now.
1561 * Pointer to error structure.
1564 * 0 on success, a negative errno value otherwise and rte_errno is set.
1567 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1568 const struct rte_flow_item *item,
1569 uint64_t item_flags,
1570 struct rte_flow_error *error)
1572 struct mlx5_priv *priv = dev->data->dev_private;
1573 const struct rte_flow_item_gtp *mask = item->mask;
1574 const struct rte_flow_item_gtp nic_mask = {
1576 .teid = RTE_BE32(0xffffffff),
1579 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1580 return rte_flow_error_set(error, ENOTSUP,
1581 RTE_FLOW_ERROR_TYPE_ITEM, item,
1582 "GTP support is not enabled");
1583 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1584 return rte_flow_error_set(error, ENOTSUP,
1585 RTE_FLOW_ERROR_TYPE_ITEM, item,
1586 "multiple tunnel layers not"
1588 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1589 return rte_flow_error_set(error, EINVAL,
1590 RTE_FLOW_ERROR_TYPE_ITEM, item,
1591 "no outer UDP layer found");
1593 mask = &rte_flow_item_gtp_mask;
1594 return mlx5_flow_item_acceptable
1595 (item, (const uint8_t *)mask,
1596 (const uint8_t *)&nic_mask,
1597 sizeof(struct rte_flow_item_gtp),
1602 * Validate the pop VLAN action.
1605 * Pointer to the rte_eth_dev structure.
1606 * @param[in] action_flags
1607 * Holds the actions detected until now.
1609 * Pointer to the pop vlan action.
1610 * @param[in] item_flags
1611 * The items found in this flow rule.
1613 * Pointer to flow attributes.
1615 * Pointer to error structure.
1618 * 0 on success, a negative errno value otherwise and rte_errno is set.
1621 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1622 uint64_t action_flags,
1623 const struct rte_flow_action *action,
1624 uint64_t item_flags,
1625 const struct rte_flow_attr *attr,
1626 struct rte_flow_error *error)
1628 struct mlx5_priv *priv = dev->data->dev_private;
1632 if (!priv->sh->pop_vlan_action)
1633 return rte_flow_error_set(error, ENOTSUP,
1634 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1636 "pop vlan action is not supported");
1638 return rte_flow_error_set(error, ENOTSUP,
1639 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1641 "pop vlan action not supported for "
1644 * Check for inconsistencies:
1645 * fail strip_vlan in a flow that matches packets without VLAN tags.
1646 * fail strip_vlan in a flow that matches packets without explicitly a
1647 * matching on VLAN tag ?
1649 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1650 return rte_flow_error_set(error, ENOTSUP,
1651 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1653 "no support for multiple vlan pop "
1655 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1656 return rte_flow_error_set(error, ENOTSUP,
1657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1659 "cannot pop vlan without a "
1660 "match on (outer) vlan in the flow");
1661 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1662 return rte_flow_error_set(error, EINVAL,
1663 RTE_FLOW_ERROR_TYPE_ACTION, action,
1664 "wrong action order, port_id should "
1665 "be after pop VLAN action");
1670 * Get VLAN default info from vlan match info.
1673 * Pointer to the rte_eth_dev structure.
1675 * the list of item specifications.
1677 * pointer VLAN info to fill to.
1679 * Pointer to error structure.
1682 * 0 on success, a negative errno value otherwise and rte_errno is set.
1685 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1686 struct rte_vlan_hdr *vlan)
1688 const struct rte_flow_item_vlan nic_mask = {
1689 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1690 MLX5DV_FLOW_VLAN_VID_MASK),
1691 .inner_type = RTE_BE16(0xffff),
1696 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1697 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1699 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1700 const struct rte_flow_item_vlan *vlan_m = items->mask;
1701 const struct rte_flow_item_vlan *vlan_v = items->spec;
1705 /* Only full match values are accepted */
1706 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1707 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1708 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1710 rte_be_to_cpu_16(vlan_v->tci &
1711 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1713 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1714 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1715 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1717 rte_be_to_cpu_16(vlan_v->tci &
1718 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1720 if (vlan_m->inner_type == nic_mask.inner_type)
1721 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1722 vlan_m->inner_type);
1727 * Validate the push VLAN action.
1729 * @param[in] action_flags
1730 * Holds the actions detected until now.
1732 * Pointer to the encap action.
1734 * Pointer to flow attributes
1736 * Pointer to error structure.
1739 * 0 on success, a negative errno value otherwise and rte_errno is set.
1742 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1743 uint64_t item_flags __rte_unused,
1744 const struct rte_flow_action *action,
1745 const struct rte_flow_attr *attr,
1746 struct rte_flow_error *error)
1748 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1751 return rte_flow_error_set(error, ENOTSUP,
1752 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1754 "push VLAN action not supported for "
1756 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1757 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1758 return rte_flow_error_set(error, EINVAL,
1759 RTE_FLOW_ERROR_TYPE_ACTION, action,
1760 "invalid vlan ethertype");
1761 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1762 return rte_flow_error_set(error, ENOTSUP,
1763 RTE_FLOW_ERROR_TYPE_ACTION, action,
1764 "no support for multiple VLAN "
1766 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1767 return rte_flow_error_set(error, EINVAL,
1768 RTE_FLOW_ERROR_TYPE_ACTION, action,
1769 "wrong action order, port_id should "
1770 "be after push VLAN");
1776 * Validate the set VLAN PCP.
1778 * @param[in] action_flags
1779 * Holds the actions detected until now.
1780 * @param[in] actions
1781 * Pointer to the list of actions remaining in the flow rule.
1783 * Pointer to flow attributes
1785 * Pointer to error structure.
1788 * 0 on success, a negative errno value otherwise and rte_errno is set.
1791 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1792 const struct rte_flow_action actions[],
1793 struct rte_flow_error *error)
1795 const struct rte_flow_action *action = actions;
1796 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1798 if (conf->vlan_pcp > 7)
1799 return rte_flow_error_set(error, EINVAL,
1800 RTE_FLOW_ERROR_TYPE_ACTION, action,
1801 "VLAN PCP value is too big");
1802 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1803 return rte_flow_error_set(error, ENOTSUP,
1804 RTE_FLOW_ERROR_TYPE_ACTION, action,
1805 "set VLAN PCP action must follow "
1806 "the push VLAN action");
1807 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1808 return rte_flow_error_set(error, ENOTSUP,
1809 RTE_FLOW_ERROR_TYPE_ACTION, action,
1810 "Multiple VLAN PCP modification are "
1812 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1813 return rte_flow_error_set(error, EINVAL,
1814 RTE_FLOW_ERROR_TYPE_ACTION, action,
1815 "wrong action order, port_id should "
1816 "be after set VLAN PCP");
1821 * Validate the set VLAN VID.
1823 * @param[in] item_flags
1824 * Holds the items detected in this rule.
1825 * @param[in] actions
1826 * Pointer to the list of actions remaining in the flow rule.
1828 * Pointer to flow attributes
1830 * Pointer to error structure.
1833 * 0 on success, a negative errno value otherwise and rte_errno is set.
1836 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1837 uint64_t action_flags,
1838 const struct rte_flow_action actions[],
1839 struct rte_flow_error *error)
1841 const struct rte_flow_action *action = actions;
1842 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1844 if (conf->vlan_vid > RTE_BE16(0xFFE))
1845 return rte_flow_error_set(error, EINVAL,
1846 RTE_FLOW_ERROR_TYPE_ACTION, action,
1847 "VLAN VID value is too big");
1848 /* there is an of_push_vlan action before us */
1849 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1850 if (mlx5_flow_find_action(actions + 1,
1851 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1852 return rte_flow_error_set(error, ENOTSUP,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "Multiple VLAN VID modifications are "
1861 * Action is on an existing VLAN header:
1862 * Need to verify this is a single modify CID action.
1863 * Rule mast include a match on outer VLAN.
1865 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1866 return rte_flow_error_set(error, ENOTSUP,
1867 RTE_FLOW_ERROR_TYPE_ACTION, action,
1868 "Multiple VLAN VID modifications are "
1870 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1871 return rte_flow_error_set(error, EINVAL,
1872 RTE_FLOW_ERROR_TYPE_ACTION, action,
1873 "match on VLAN is required in order "
1875 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1876 return rte_flow_error_set(error, EINVAL,
1877 RTE_FLOW_ERROR_TYPE_ACTION, action,
1878 "wrong action order, port_id should "
1879 "be after set VLAN VID");
1884 * Validate the FLAG action.
1887 * Pointer to the rte_eth_dev structure.
1888 * @param[in] action_flags
1889 * Holds the actions detected until now.
1891 * Pointer to flow attributes
1893 * Pointer to error structure.
1896 * 0 on success, a negative errno value otherwise and rte_errno is set.
1899 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1900 uint64_t action_flags,
1901 const struct rte_flow_attr *attr,
1902 struct rte_flow_error *error)
1904 struct mlx5_priv *priv = dev->data->dev_private;
1905 struct mlx5_dev_config *config = &priv->config;
1908 /* Fall back if no extended metadata register support. */
1909 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1910 return mlx5_flow_validate_action_flag(action_flags, attr,
1912 /* Extensive metadata mode requires registers. */
1913 if (!mlx5_flow_ext_mreg_supported(dev))
1914 return rte_flow_error_set(error, ENOTSUP,
1915 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1916 "no metadata registers "
1917 "to support flag action");
1918 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1919 return rte_flow_error_set(error, ENOTSUP,
1920 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1921 "extended metadata register"
1922 " isn't available");
1923 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1927 if (action_flags & MLX5_FLOW_ACTION_MARK)
1928 return rte_flow_error_set(error, EINVAL,
1929 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1930 "can't mark and flag in same flow");
1931 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1932 return rte_flow_error_set(error, EINVAL,
1933 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1935 " actions in same flow");
1940 * Validate MARK action.
1943 * Pointer to the rte_eth_dev structure.
1945 * Pointer to action.
1946 * @param[in] action_flags
1947 * Holds the actions detected until now.
1949 * Pointer to flow attributes
1951 * Pointer to error structure.
1954 * 0 on success, a negative errno value otherwise and rte_errno is set.
1957 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1958 const struct rte_flow_action *action,
1959 uint64_t action_flags,
1960 const struct rte_flow_attr *attr,
1961 struct rte_flow_error *error)
1963 struct mlx5_priv *priv = dev->data->dev_private;
1964 struct mlx5_dev_config *config = &priv->config;
1965 const struct rte_flow_action_mark *mark = action->conf;
1968 /* Fall back if no extended metadata register support. */
1969 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1970 return mlx5_flow_validate_action_mark(action, action_flags,
1972 /* Extensive metadata mode requires registers. */
1973 if (!mlx5_flow_ext_mreg_supported(dev))
1974 return rte_flow_error_set(error, ENOTSUP,
1975 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1976 "no metadata registers "
1977 "to support mark action");
1978 if (!priv->sh->dv_mark_mask)
1979 return rte_flow_error_set(error, ENOTSUP,
1980 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1981 "extended metadata register"
1982 " isn't available");
1983 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1988 return rte_flow_error_set(error, EINVAL,
1989 RTE_FLOW_ERROR_TYPE_ACTION, action,
1990 "configuration cannot be null");
1991 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1992 return rte_flow_error_set(error, EINVAL,
1993 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1995 "mark id exceeds the limit");
1996 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1997 return rte_flow_error_set(error, EINVAL,
1998 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1999 "can't flag and mark in same flow");
2000 if (action_flags & MLX5_FLOW_ACTION_MARK)
2001 return rte_flow_error_set(error, EINVAL,
2002 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2003 "can't have 2 mark actions in same"
2009 * Validate SET_META action.
2012 * Pointer to the rte_eth_dev structure.
2014 * Pointer to the encap action.
2015 * @param[in] action_flags
2016 * Holds the actions detected until now.
2018 * Pointer to flow attributes
2020 * Pointer to error structure.
2023 * 0 on success, a negative errno value otherwise and rte_errno is set.
2026 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2027 const struct rte_flow_action *action,
2028 uint64_t action_flags __rte_unused,
2029 const struct rte_flow_attr *attr,
2030 struct rte_flow_error *error)
2032 const struct rte_flow_action_set_meta *conf;
2033 uint32_t nic_mask = UINT32_MAX;
2034 enum modify_reg reg;
2036 if (!mlx5_flow_ext_mreg_supported(dev))
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ACTION, action,
2039 "extended metadata register"
2040 " isn't supported");
2041 reg = flow_dv_get_metadata_reg(dev, attr, error);
2044 if (reg != REG_A && reg != REG_B) {
2045 struct mlx5_priv *priv = dev->data->dev_private;
2047 nic_mask = priv->sh->dv_meta_mask;
2049 if (!(action->conf))
2050 return rte_flow_error_set(error, EINVAL,
2051 RTE_FLOW_ERROR_TYPE_ACTION, action,
2052 "configuration cannot be null");
2053 conf = (const struct rte_flow_action_set_meta *)action->conf;
2055 return rte_flow_error_set(error, EINVAL,
2056 RTE_FLOW_ERROR_TYPE_ACTION, action,
2057 "zero mask doesn't have any effect");
2058 if (conf->mask & ~nic_mask)
2059 return rte_flow_error_set(error, EINVAL,
2060 RTE_FLOW_ERROR_TYPE_ACTION, action,
2061 "meta data must be within reg C0");
2062 if (!(conf->data & conf->mask))
2063 return rte_flow_error_set(error, EINVAL,
2064 RTE_FLOW_ERROR_TYPE_ACTION, action,
2065 "zero value has no effect");
2070 * Validate SET_TAG action.
2073 * Pointer to the rte_eth_dev structure.
2075 * Pointer to the encap action.
2076 * @param[in] action_flags
2077 * Holds the actions detected until now.
2079 * Pointer to flow attributes
2081 * Pointer to error structure.
2084 * 0 on success, a negative errno value otherwise and rte_errno is set.
2087 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2088 const struct rte_flow_action *action,
2089 uint64_t action_flags,
2090 const struct rte_flow_attr *attr,
2091 struct rte_flow_error *error)
2093 const struct rte_flow_action_set_tag *conf;
2094 const uint64_t terminal_action_flags =
2095 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2096 MLX5_FLOW_ACTION_RSS;
2099 if (!mlx5_flow_ext_mreg_supported(dev))
2100 return rte_flow_error_set(error, ENOTSUP,
2101 RTE_FLOW_ERROR_TYPE_ACTION, action,
2102 "extensive metadata register"
2103 " isn't supported");
2104 if (!(action->conf))
2105 return rte_flow_error_set(error, EINVAL,
2106 RTE_FLOW_ERROR_TYPE_ACTION, action,
2107 "configuration cannot be null");
2108 conf = (const struct rte_flow_action_set_tag *)action->conf;
2110 return rte_flow_error_set(error, EINVAL,
2111 RTE_FLOW_ERROR_TYPE_ACTION, action,
2112 "zero mask doesn't have any effect");
2113 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2116 if (!attr->transfer && attr->ingress &&
2117 (action_flags & terminal_action_flags))
2118 return rte_flow_error_set(error, EINVAL,
2119 RTE_FLOW_ERROR_TYPE_ACTION, action,
2120 "set_tag has no effect"
2121 " with terminal actions");
2126 * Validate count action.
2131 * Pointer to error structure.
2134 * 0 on success, a negative errno value otherwise and rte_errno is set.
2137 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2138 struct rte_flow_error *error)
2140 struct mlx5_priv *priv = dev->data->dev_private;
2142 if (!priv->config.devx)
2144 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2148 return rte_flow_error_set
2150 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2152 "count action not supported");
2156 * Validate the L2 encap action.
2158 * @param[in] action_flags
2159 * Holds the actions detected until now.
2161 * Pointer to the encap action.
2163 * Pointer to flow attributes
2165 * Pointer to error structure.
2168 * 0 on success, a negative errno value otherwise and rte_errno is set.
2171 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2172 const struct rte_flow_action *action,
2173 const struct rte_flow_attr *attr,
2174 struct rte_flow_error *error)
2176 if (!(action->conf))
2177 return rte_flow_error_set(error, EINVAL,
2178 RTE_FLOW_ERROR_TYPE_ACTION, action,
2179 "configuration cannot be null");
2180 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2181 return rte_flow_error_set(error, EINVAL,
2182 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2183 "can only have a single encap or"
2184 " decap action in a flow");
2185 if (!attr->transfer && attr->ingress)
2186 return rte_flow_error_set(error, ENOTSUP,
2187 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2189 "encap action not supported for "
2195 * Validate the L2 decap action.
2197 * @param[in] action_flags
2198 * Holds the actions detected until now.
2200 * Pointer to flow attributes
2202 * Pointer to error structure.
2205 * 0 on success, a negative errno value otherwise and rte_errno is set.
2208 flow_dv_validate_action_l2_decap(uint64_t action_flags,
2209 const struct rte_flow_attr *attr,
2210 struct rte_flow_error *error)
2212 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2213 return rte_flow_error_set(error, EINVAL,
2214 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2215 "can only have a single encap or"
2216 " decap action in a flow");
2217 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2218 return rte_flow_error_set(error, EINVAL,
2219 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2220 "can't have decap action after"
2223 return rte_flow_error_set(error, ENOTSUP,
2224 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2226 "decap action not supported for "
2232 * Validate the raw encap action.
2234 * @param[in] action_flags
2235 * Holds the actions detected until now.
2237 * Pointer to the encap action.
2239 * Pointer to flow attributes
2241 * Pointer to error structure.
2244 * 0 on success, a negative errno value otherwise and rte_errno is set.
2247 flow_dv_validate_action_raw_encap(uint64_t action_flags,
2248 const struct rte_flow_action *action,
2249 const struct rte_flow_attr *attr,
2250 struct rte_flow_error *error)
2252 const struct rte_flow_action_raw_encap *raw_encap =
2253 (const struct rte_flow_action_raw_encap *)action->conf;
2254 if (!(action->conf))
2255 return rte_flow_error_set(error, EINVAL,
2256 RTE_FLOW_ERROR_TYPE_ACTION, action,
2257 "configuration cannot be null");
2258 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2261 "can only have a single encap"
2262 " action in a flow");
2263 /* encap without preceding decap is not supported for ingress */
2264 if (!attr->transfer && attr->ingress &&
2265 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
2266 return rte_flow_error_set(error, ENOTSUP,
2267 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2269 "encap action not supported for "
2271 if (!raw_encap->size || !raw_encap->data)
2272 return rte_flow_error_set(error, EINVAL,
2273 RTE_FLOW_ERROR_TYPE_ACTION, action,
2274 "raw encap data cannot be empty");
2279 * Validate the raw decap action.
2281 * @param[in] action_flags
2282 * Holds the actions detected until now.
2284 * Pointer to the encap action.
2286 * Pointer to flow attributes
2288 * Pointer to error structure.
2291 * 0 on success, a negative errno value otherwise and rte_errno is set.
2294 flow_dv_validate_action_raw_decap(uint64_t action_flags,
2295 const struct rte_flow_action *action,
2296 const struct rte_flow_attr *attr,
2297 struct rte_flow_error *error)
2299 const struct rte_flow_action_raw_decap *decap = action->conf;
2301 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2302 return rte_flow_error_set(error, EINVAL,
2303 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2304 "can't have encap action before"
2306 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
2307 return rte_flow_error_set(error, EINVAL,
2308 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2309 "can only have a single decap"
2310 " action in a flow");
2311 /* decap action is valid on egress only if it is followed by encap */
2312 if (attr->egress && decap &&
2313 decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) {
2314 return rte_flow_error_set(error, ENOTSUP,
2315 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2316 NULL, "decap action not supported"
2318 } else if (decap && decap->size > MLX5_ENCAPSULATION_DECISION_SIZE &&
2319 (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)) {
2320 return rte_flow_error_set(error, EINVAL,
2321 RTE_FLOW_ERROR_TYPE_ACTION,
2323 "can't have decap action "
2324 "after modify action");
2330 * Find existing encap/decap resource or create and register a new one.
2332 * @param[in, out] dev
2333 * Pointer to rte_eth_dev structure.
2334 * @param[in, out] resource
2335 * Pointer to encap/decap resource.
2336 * @parm[in, out] dev_flow
2337 * Pointer to the dev_flow.
2339 * pointer to error structure.
2342 * 0 on success otherwise -errno and errno is set.
2345 flow_dv_encap_decap_resource_register
2346 (struct rte_eth_dev *dev,
2347 struct mlx5_flow_dv_encap_decap_resource *resource,
2348 struct mlx5_flow *dev_flow,
2349 struct rte_flow_error *error)
2351 struct mlx5_priv *priv = dev->data->dev_private;
2352 struct mlx5_ibv_shared *sh = priv->sh;
2353 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2354 struct mlx5dv_dr_domain *domain;
2356 resource->flags = dev_flow->group ? 0 : 1;
2357 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2358 domain = sh->fdb_domain;
2359 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2360 domain = sh->rx_domain;
2362 domain = sh->tx_domain;
2363 /* Lookup a matching resource from cache. */
2364 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2365 if (resource->reformat_type == cache_resource->reformat_type &&
2366 resource->ft_type == cache_resource->ft_type &&
2367 resource->flags == cache_resource->flags &&
2368 resource->size == cache_resource->size &&
2369 !memcmp((const void *)resource->buf,
2370 (const void *)cache_resource->buf,
2372 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2373 (void *)cache_resource,
2374 rte_atomic32_read(&cache_resource->refcnt));
2375 rte_atomic32_inc(&cache_resource->refcnt);
2376 dev_flow->dv.encap_decap = cache_resource;
2380 /* Register new encap/decap resource. */
2381 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2382 if (!cache_resource)
2383 return rte_flow_error_set(error, ENOMEM,
2384 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2385 "cannot allocate resource memory");
2386 *cache_resource = *resource;
2387 cache_resource->verbs_action =
2388 mlx5_glue->dv_create_flow_action_packet_reformat
2389 (sh->ctx, cache_resource->reformat_type,
2390 cache_resource->ft_type, domain, cache_resource->flags,
2391 cache_resource->size,
2392 (cache_resource->size ? cache_resource->buf : NULL));
2393 if (!cache_resource->verbs_action) {
2394 rte_free(cache_resource);
2395 return rte_flow_error_set(error, ENOMEM,
2396 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2397 NULL, "cannot create action");
2399 rte_atomic32_init(&cache_resource->refcnt);
2400 rte_atomic32_inc(&cache_resource->refcnt);
2401 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2402 dev_flow->dv.encap_decap = cache_resource;
2403 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2404 (void *)cache_resource,
2405 rte_atomic32_read(&cache_resource->refcnt));
2410 * Find existing table jump resource or create and register a new one.
2412 * @param[in, out] dev
2413 * Pointer to rte_eth_dev structure.
2414 * @param[in, out] tbl
2415 * Pointer to flow table resource.
2416 * @parm[in, out] dev_flow
2417 * Pointer to the dev_flow.
2419 * pointer to error structure.
2422 * 0 on success otherwise -errno and errno is set.
2425 flow_dv_jump_tbl_resource_register
2426 (struct rte_eth_dev *dev __rte_unused,
2427 struct mlx5_flow_tbl_resource *tbl,
2428 struct mlx5_flow *dev_flow,
2429 struct rte_flow_error *error)
2431 struct mlx5_flow_tbl_data_entry *tbl_data =
2432 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2436 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2438 tbl_data->jump.action =
2439 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2441 if (!tbl_data->jump.action)
2442 return rte_flow_error_set(error, ENOMEM,
2443 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2444 NULL, "cannot create jump action");
2445 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2446 (void *)&tbl_data->jump, cnt);
2448 assert(tbl_data->jump.action);
2449 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2450 (void *)&tbl_data->jump, cnt);
2452 rte_atomic32_inc(&tbl_data->jump.refcnt);
2453 dev_flow->dv.jump = &tbl_data->jump;
2458 * Find existing table port ID resource or create and register a new one.
2460 * @param[in, out] dev
2461 * Pointer to rte_eth_dev structure.
2462 * @param[in, out] resource
2463 * Pointer to port ID action resource.
2464 * @parm[in, out] dev_flow
2465 * Pointer to the dev_flow.
2467 * pointer to error structure.
2470 * 0 on success otherwise -errno and errno is set.
2473 flow_dv_port_id_action_resource_register
2474 (struct rte_eth_dev *dev,
2475 struct mlx5_flow_dv_port_id_action_resource *resource,
2476 struct mlx5_flow *dev_flow,
2477 struct rte_flow_error *error)
2479 struct mlx5_priv *priv = dev->data->dev_private;
2480 struct mlx5_ibv_shared *sh = priv->sh;
2481 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2483 /* Lookup a matching resource from cache. */
2484 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2485 if (resource->port_id == cache_resource->port_id) {
2486 DRV_LOG(DEBUG, "port id action resource resource %p: "
2488 (void *)cache_resource,
2489 rte_atomic32_read(&cache_resource->refcnt));
2490 rte_atomic32_inc(&cache_resource->refcnt);
2491 dev_flow->dv.port_id_action = cache_resource;
2495 /* Register new port id action resource. */
2496 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2497 if (!cache_resource)
2498 return rte_flow_error_set(error, ENOMEM,
2499 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2500 "cannot allocate resource memory");
2501 *cache_resource = *resource;
2503 * Depending on rdma_core version the glue routine calls
2504 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2505 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2507 cache_resource->action =
2508 mlx5_glue->dr_create_flow_action_dest_port
2509 (priv->sh->fdb_domain, resource->port_id);
2510 if (!cache_resource->action) {
2511 rte_free(cache_resource);
2512 return rte_flow_error_set(error, ENOMEM,
2513 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2514 NULL, "cannot create action");
2516 rte_atomic32_init(&cache_resource->refcnt);
2517 rte_atomic32_inc(&cache_resource->refcnt);
2518 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2519 dev_flow->dv.port_id_action = cache_resource;
2520 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2521 (void *)cache_resource,
2522 rte_atomic32_read(&cache_resource->refcnt));
2527 * Find existing push vlan resource or create and register a new one.
2529 * @param [in, out] dev
2530 * Pointer to rte_eth_dev structure.
2531 * @param[in, out] resource
2532 * Pointer to port ID action resource.
2533 * @parm[in, out] dev_flow
2534 * Pointer to the dev_flow.
2536 * pointer to error structure.
2539 * 0 on success otherwise -errno and errno is set.
2542 flow_dv_push_vlan_action_resource_register
2543 (struct rte_eth_dev *dev,
2544 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2545 struct mlx5_flow *dev_flow,
2546 struct rte_flow_error *error)
2548 struct mlx5_priv *priv = dev->data->dev_private;
2549 struct mlx5_ibv_shared *sh = priv->sh;
2550 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2551 struct mlx5dv_dr_domain *domain;
2553 /* Lookup a matching resource from cache. */
2554 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2555 if (resource->vlan_tag == cache_resource->vlan_tag &&
2556 resource->ft_type == cache_resource->ft_type) {
2557 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2559 (void *)cache_resource,
2560 rte_atomic32_read(&cache_resource->refcnt));
2561 rte_atomic32_inc(&cache_resource->refcnt);
2562 dev_flow->dv.push_vlan_res = cache_resource;
2566 /* Register new push_vlan action resource. */
2567 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2568 if (!cache_resource)
2569 return rte_flow_error_set(error, ENOMEM,
2570 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2571 "cannot allocate resource memory");
2572 *cache_resource = *resource;
2573 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2574 domain = sh->fdb_domain;
2575 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2576 domain = sh->rx_domain;
2578 domain = sh->tx_domain;
2579 cache_resource->action =
2580 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2581 resource->vlan_tag);
2582 if (!cache_resource->action) {
2583 rte_free(cache_resource);
2584 return rte_flow_error_set(error, ENOMEM,
2585 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2586 NULL, "cannot create action");
2588 rte_atomic32_init(&cache_resource->refcnt);
2589 rte_atomic32_inc(&cache_resource->refcnt);
2590 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2591 dev_flow->dv.push_vlan_res = cache_resource;
2592 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2593 (void *)cache_resource,
2594 rte_atomic32_read(&cache_resource->refcnt));
2598 * Get the size of specific rte_flow_item_type
2600 * @param[in] item_type
2601 * Tested rte_flow_item_type.
2604 * sizeof struct item_type, 0 if void or irrelevant.
2607 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2611 switch (item_type) {
2612 case RTE_FLOW_ITEM_TYPE_ETH:
2613 retval = sizeof(struct rte_flow_item_eth);
2615 case RTE_FLOW_ITEM_TYPE_VLAN:
2616 retval = sizeof(struct rte_flow_item_vlan);
2618 case RTE_FLOW_ITEM_TYPE_IPV4:
2619 retval = sizeof(struct rte_flow_item_ipv4);
2621 case RTE_FLOW_ITEM_TYPE_IPV6:
2622 retval = sizeof(struct rte_flow_item_ipv6);
2624 case RTE_FLOW_ITEM_TYPE_UDP:
2625 retval = sizeof(struct rte_flow_item_udp);
2627 case RTE_FLOW_ITEM_TYPE_TCP:
2628 retval = sizeof(struct rte_flow_item_tcp);
2630 case RTE_FLOW_ITEM_TYPE_VXLAN:
2631 retval = sizeof(struct rte_flow_item_vxlan);
2633 case RTE_FLOW_ITEM_TYPE_GRE:
2634 retval = sizeof(struct rte_flow_item_gre);
2636 case RTE_FLOW_ITEM_TYPE_NVGRE:
2637 retval = sizeof(struct rte_flow_item_nvgre);
2639 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2640 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2642 case RTE_FLOW_ITEM_TYPE_MPLS:
2643 retval = sizeof(struct rte_flow_item_mpls);
2645 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2653 #define MLX5_ENCAP_IPV4_VERSION 0x40
2654 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2655 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2656 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2657 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2658 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2659 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2662 * Convert the encap action data from list of rte_flow_item to raw buffer
2665 * Pointer to rte_flow_item objects list.
2667 * Pointer to the output buffer.
2669 * Pointer to the output buffer size.
2671 * Pointer to the error structure.
2674 * 0 on success, a negative errno value otherwise and rte_errno is set.
2677 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2678 size_t *size, struct rte_flow_error *error)
2680 struct rte_ether_hdr *eth = NULL;
2681 struct rte_vlan_hdr *vlan = NULL;
2682 struct rte_ipv4_hdr *ipv4 = NULL;
2683 struct rte_ipv6_hdr *ipv6 = NULL;
2684 struct rte_udp_hdr *udp = NULL;
2685 struct rte_vxlan_hdr *vxlan = NULL;
2686 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2687 struct rte_gre_hdr *gre = NULL;
2689 size_t temp_size = 0;
2692 return rte_flow_error_set(error, EINVAL,
2693 RTE_FLOW_ERROR_TYPE_ACTION,
2694 NULL, "invalid empty data");
2695 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2696 len = flow_dv_get_item_len(items->type);
2697 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2698 return rte_flow_error_set(error, EINVAL,
2699 RTE_FLOW_ERROR_TYPE_ACTION,
2700 (void *)items->type,
2701 "items total size is too big"
2702 " for encap action");
2703 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2704 switch (items->type) {
2705 case RTE_FLOW_ITEM_TYPE_ETH:
2706 eth = (struct rte_ether_hdr *)&buf[temp_size];
2708 case RTE_FLOW_ITEM_TYPE_VLAN:
2709 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2711 return rte_flow_error_set(error, EINVAL,
2712 RTE_FLOW_ERROR_TYPE_ACTION,
2713 (void *)items->type,
2714 "eth header not found");
2715 if (!eth->ether_type)
2716 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2718 case RTE_FLOW_ITEM_TYPE_IPV4:
2719 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2721 return rte_flow_error_set(error, EINVAL,
2722 RTE_FLOW_ERROR_TYPE_ACTION,
2723 (void *)items->type,
2724 "neither eth nor vlan"
2726 if (vlan && !vlan->eth_proto)
2727 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2728 else if (eth && !eth->ether_type)
2729 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2730 if (!ipv4->version_ihl)
2731 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2732 MLX5_ENCAP_IPV4_IHL_MIN;
2733 if (!ipv4->time_to_live)
2734 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2736 case RTE_FLOW_ITEM_TYPE_IPV6:
2737 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2739 return rte_flow_error_set(error, EINVAL,
2740 RTE_FLOW_ERROR_TYPE_ACTION,
2741 (void *)items->type,
2742 "neither eth nor vlan"
2744 if (vlan && !vlan->eth_proto)
2745 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2746 else if (eth && !eth->ether_type)
2747 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2748 if (!ipv6->vtc_flow)
2750 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2751 if (!ipv6->hop_limits)
2752 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2754 case RTE_FLOW_ITEM_TYPE_UDP:
2755 udp = (struct rte_udp_hdr *)&buf[temp_size];
2757 return rte_flow_error_set(error, EINVAL,
2758 RTE_FLOW_ERROR_TYPE_ACTION,
2759 (void *)items->type,
2760 "ip header not found");
2761 if (ipv4 && !ipv4->next_proto_id)
2762 ipv4->next_proto_id = IPPROTO_UDP;
2763 else if (ipv6 && !ipv6->proto)
2764 ipv6->proto = IPPROTO_UDP;
2766 case RTE_FLOW_ITEM_TYPE_VXLAN:
2767 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2769 return rte_flow_error_set(error, EINVAL,
2770 RTE_FLOW_ERROR_TYPE_ACTION,
2771 (void *)items->type,
2772 "udp header not found");
2774 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2775 if (!vxlan->vx_flags)
2777 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2779 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2780 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2782 return rte_flow_error_set(error, EINVAL,
2783 RTE_FLOW_ERROR_TYPE_ACTION,
2784 (void *)items->type,
2785 "udp header not found");
2786 if (!vxlan_gpe->proto)
2787 return rte_flow_error_set(error, EINVAL,
2788 RTE_FLOW_ERROR_TYPE_ACTION,
2789 (void *)items->type,
2790 "next protocol not found");
2793 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2794 if (!vxlan_gpe->vx_flags)
2795 vxlan_gpe->vx_flags =
2796 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2798 case RTE_FLOW_ITEM_TYPE_GRE:
2799 case RTE_FLOW_ITEM_TYPE_NVGRE:
2800 gre = (struct rte_gre_hdr *)&buf[temp_size];
2802 return rte_flow_error_set(error, EINVAL,
2803 RTE_FLOW_ERROR_TYPE_ACTION,
2804 (void *)items->type,
2805 "next protocol not found");
2807 return rte_flow_error_set(error, EINVAL,
2808 RTE_FLOW_ERROR_TYPE_ACTION,
2809 (void *)items->type,
2810 "ip header not found");
2811 if (ipv4 && !ipv4->next_proto_id)
2812 ipv4->next_proto_id = IPPROTO_GRE;
2813 else if (ipv6 && !ipv6->proto)
2814 ipv6->proto = IPPROTO_GRE;
2816 case RTE_FLOW_ITEM_TYPE_VOID:
2819 return rte_flow_error_set(error, EINVAL,
2820 RTE_FLOW_ERROR_TYPE_ACTION,
2821 (void *)items->type,
2822 "unsupported item type");
2832 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2834 struct rte_ether_hdr *eth = NULL;
2835 struct rte_vlan_hdr *vlan = NULL;
2836 struct rte_ipv6_hdr *ipv6 = NULL;
2837 struct rte_udp_hdr *udp = NULL;
2841 eth = (struct rte_ether_hdr *)data;
2842 next_hdr = (char *)(eth + 1);
2843 proto = RTE_BE16(eth->ether_type);
2846 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2847 vlan = (struct rte_vlan_hdr *)next_hdr;
2848 proto = RTE_BE16(vlan->eth_proto);
2849 next_hdr += sizeof(struct rte_vlan_hdr);
2852 /* HW calculates IPv4 csum. no need to proceed */
2853 if (proto == RTE_ETHER_TYPE_IPV4)
2856 /* non IPv4/IPv6 header. not supported */
2857 if (proto != RTE_ETHER_TYPE_IPV6) {
2858 return rte_flow_error_set(error, ENOTSUP,
2859 RTE_FLOW_ERROR_TYPE_ACTION,
2860 NULL, "Cannot offload non IPv4/IPv6");
2863 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2865 /* ignore non UDP */
2866 if (ipv6->proto != IPPROTO_UDP)
2869 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2870 udp->dgram_cksum = 0;
2876 * Convert L2 encap action to DV specification.
2879 * Pointer to rte_eth_dev structure.
2881 * Pointer to action structure.
2882 * @param[in, out] dev_flow
2883 * Pointer to the mlx5_flow.
2884 * @param[in] transfer
2885 * Mark if the flow is E-Switch flow.
2887 * Pointer to the error structure.
2890 * 0 on success, a negative errno value otherwise and rte_errno is set.
2893 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2894 const struct rte_flow_action *action,
2895 struct mlx5_flow *dev_flow,
2897 struct rte_flow_error *error)
2899 const struct rte_flow_item *encap_data;
2900 const struct rte_flow_action_raw_encap *raw_encap_data;
2901 struct mlx5_flow_dv_encap_decap_resource res = {
2903 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2904 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2905 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2908 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2910 (const struct rte_flow_action_raw_encap *)action->conf;
2911 res.size = raw_encap_data->size;
2912 memcpy(res.buf, raw_encap_data->data, res.size);
2913 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2916 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2918 ((const struct rte_flow_action_vxlan_encap *)
2919 action->conf)->definition;
2922 ((const struct rte_flow_action_nvgre_encap *)
2923 action->conf)->definition;
2924 if (flow_dv_convert_encap_data(encap_data, res.buf,
2928 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2929 return rte_flow_error_set(error, EINVAL,
2930 RTE_FLOW_ERROR_TYPE_ACTION,
2931 NULL, "can't create L2 encap action");
2936 * Convert L2 decap action to DV specification.
2939 * Pointer to rte_eth_dev structure.
2940 * @param[in, out] dev_flow
2941 * Pointer to the mlx5_flow.
2942 * @param[in] transfer
2943 * Mark if the flow is E-Switch flow.
2945 * Pointer to the error structure.
2948 * 0 on success, a negative errno value otherwise and rte_errno is set.
2951 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2952 struct mlx5_flow *dev_flow,
2954 struct rte_flow_error *error)
2956 struct mlx5_flow_dv_encap_decap_resource res = {
2959 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2960 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2961 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2964 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2965 return rte_flow_error_set(error, EINVAL,
2966 RTE_FLOW_ERROR_TYPE_ACTION,
2967 NULL, "can't create L2 decap action");
2972 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2975 * Pointer to rte_eth_dev structure.
2977 * Pointer to action structure.
2978 * @param[in, out] dev_flow
2979 * Pointer to the mlx5_flow.
2981 * Pointer to the flow attributes.
2983 * Pointer to the error structure.
2986 * 0 on success, a negative errno value otherwise and rte_errno is set.
2989 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2990 const struct rte_flow_action *action,
2991 struct mlx5_flow *dev_flow,
2992 const struct rte_flow_attr *attr,
2993 struct rte_flow_error *error)
2995 const struct rte_flow_action_raw_encap *encap_data;
2996 struct mlx5_flow_dv_encap_decap_resource res;
2998 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2999 res.size = encap_data->size;
3000 memcpy(res.buf, encap_data->data, res.size);
3001 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3002 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3003 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3005 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3007 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3008 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3009 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3010 return rte_flow_error_set(error, EINVAL,
3011 RTE_FLOW_ERROR_TYPE_ACTION,
3012 NULL, "can't create encap action");
3017 * Create action push VLAN.
3020 * Pointer to rte_eth_dev structure.
3021 * @param[in] vlan_tag
3022 * the vlan tag to push to the Ethernet header.
3023 * @param[in, out] dev_flow
3024 * Pointer to the mlx5_flow.
3026 * Pointer to the flow attributes.
3028 * Pointer to the error structure.
3031 * 0 on success, a negative errno value otherwise and rte_errno is set.
3034 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3035 const struct rte_flow_attr *attr,
3036 const struct rte_vlan_hdr *vlan,
3037 struct mlx5_flow *dev_flow,
3038 struct rte_flow_error *error)
3040 struct mlx5_flow_dv_push_vlan_action_resource res;
3043 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3046 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3048 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3049 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3050 return flow_dv_push_vlan_action_resource_register
3051 (dev, &res, dev_flow, error);
3055 * Validate the modify-header actions.
3057 * @param[in] action_flags
3058 * Holds the actions detected until now.
3060 * Pointer to the modify action.
3062 * Pointer to error structure.
3065 * 0 on success, a negative errno value otherwise and rte_errno is set.
3068 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3069 const struct rte_flow_action *action,
3070 struct rte_flow_error *error)
3072 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3073 return rte_flow_error_set(error, EINVAL,
3074 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3075 NULL, "action configuration not set");
3076 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
3077 return rte_flow_error_set(error, EINVAL,
3078 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3079 "can't have encap action before"
3085 * Validate the modify-header MAC address actions.
3087 * @param[in] action_flags
3088 * Holds the actions detected until now.
3090 * Pointer to the modify action.
3091 * @param[in] item_flags
3092 * Holds the items detected.
3094 * Pointer to error structure.
3097 * 0 on success, a negative errno value otherwise and rte_errno is set.
3100 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3101 const struct rte_flow_action *action,
3102 const uint64_t item_flags,
3103 struct rte_flow_error *error)
3107 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3109 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3110 return rte_flow_error_set(error, EINVAL,
3111 RTE_FLOW_ERROR_TYPE_ACTION,
3113 "no L2 item in pattern");
3119 * Validate the modify-header IPv4 address actions.
3121 * @param[in] action_flags
3122 * Holds the actions detected until now.
3124 * Pointer to the modify action.
3125 * @param[in] item_flags
3126 * Holds the items detected.
3128 * Pointer to error structure.
3131 * 0 on success, a negative errno value otherwise and rte_errno is set.
3134 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3135 const struct rte_flow_action *action,
3136 const uint64_t item_flags,
3137 struct rte_flow_error *error)
3141 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3143 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3144 return rte_flow_error_set(error, EINVAL,
3145 RTE_FLOW_ERROR_TYPE_ACTION,
3147 "no ipv4 item in pattern");
3153 * Validate the modify-header IPv6 address actions.
3155 * @param[in] action_flags
3156 * Holds the actions detected until now.
3158 * Pointer to the modify action.
3159 * @param[in] item_flags
3160 * Holds the items detected.
3162 * Pointer to error structure.
3165 * 0 on success, a negative errno value otherwise and rte_errno is set.
3168 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3169 const struct rte_flow_action *action,
3170 const uint64_t item_flags,
3171 struct rte_flow_error *error)
3175 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3177 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3178 return rte_flow_error_set(error, EINVAL,
3179 RTE_FLOW_ERROR_TYPE_ACTION,
3181 "no ipv6 item in pattern");
3187 * Validate the modify-header TP actions.
3189 * @param[in] action_flags
3190 * Holds the actions detected until now.
3192 * Pointer to the modify action.
3193 * @param[in] item_flags
3194 * Holds the items detected.
3196 * Pointer to error structure.
3199 * 0 on success, a negative errno value otherwise and rte_errno is set.
3202 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3203 const struct rte_flow_action *action,
3204 const uint64_t item_flags,
3205 struct rte_flow_error *error)
3209 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3211 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3212 return rte_flow_error_set(error, EINVAL,
3213 RTE_FLOW_ERROR_TYPE_ACTION,
3214 NULL, "no transport layer "
3221 * Validate the modify-header actions of increment/decrement
3222 * TCP Sequence-number.
3224 * @param[in] action_flags
3225 * Holds the actions detected until now.
3227 * Pointer to the modify action.
3228 * @param[in] item_flags
3229 * Holds the items detected.
3231 * Pointer to error structure.
3234 * 0 on success, a negative errno value otherwise and rte_errno is set.
3237 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3238 const struct rte_flow_action *action,
3239 const uint64_t item_flags,
3240 struct rte_flow_error *error)
3244 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3246 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3247 return rte_flow_error_set(error, EINVAL,
3248 RTE_FLOW_ERROR_TYPE_ACTION,
3249 NULL, "no TCP item in"
3251 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3252 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3253 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3254 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3255 return rte_flow_error_set(error, EINVAL,
3256 RTE_FLOW_ERROR_TYPE_ACTION,
3258 "cannot decrease and increase"
3259 " TCP sequence number"
3260 " at the same time");
3266 * Validate the modify-header actions of increment/decrement
3267 * TCP Acknowledgment number.
3269 * @param[in] action_flags
3270 * Holds the actions detected until now.
3272 * Pointer to the modify action.
3273 * @param[in] item_flags
3274 * Holds the items detected.
3276 * Pointer to error structure.
3279 * 0 on success, a negative errno value otherwise and rte_errno is set.
3282 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3283 const struct rte_flow_action *action,
3284 const uint64_t item_flags,
3285 struct rte_flow_error *error)
3289 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3291 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3292 return rte_flow_error_set(error, EINVAL,
3293 RTE_FLOW_ERROR_TYPE_ACTION,
3294 NULL, "no TCP item in"
3296 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3297 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3298 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3299 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3300 return rte_flow_error_set(error, EINVAL,
3301 RTE_FLOW_ERROR_TYPE_ACTION,
3303 "cannot decrease and increase"
3304 " TCP acknowledgment number"
3305 " at the same time");
3311 * Validate the modify-header TTL actions.
3313 * @param[in] action_flags
3314 * Holds the actions detected until now.
3316 * Pointer to the modify action.
3317 * @param[in] item_flags
3318 * Holds the items detected.
3320 * Pointer to error structure.
3323 * 0 on success, a negative errno value otherwise and rte_errno is set.
3326 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3327 const struct rte_flow_action *action,
3328 const uint64_t item_flags,
3329 struct rte_flow_error *error)
3333 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3335 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3336 return rte_flow_error_set(error, EINVAL,
3337 RTE_FLOW_ERROR_TYPE_ACTION,
3339 "no IP protocol in pattern");
3345 * Validate jump action.
3348 * Pointer to the jump action.
3349 * @param[in] action_flags
3350 * Holds the actions detected until now.
3351 * @param[in] attributes
3352 * Pointer to flow attributes
3353 * @param[in] external
3354 * Action belongs to flow rule created by request external to PMD.
3356 * Pointer to error structure.
3359 * 0 on success, a negative errno value otherwise and rte_errno is set.
3362 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3363 uint64_t action_flags,
3364 const struct rte_flow_attr *attributes,
3365 bool external, struct rte_flow_error *error)
3367 uint32_t target_group, table;
3370 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3371 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3372 return rte_flow_error_set(error, EINVAL,
3373 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3374 "can't have 2 fate actions in"
3376 if (action_flags & MLX5_FLOW_ACTION_METER)
3377 return rte_flow_error_set(error, ENOTSUP,
3378 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3379 "jump with meter not support");
3381 return rte_flow_error_set(error, EINVAL,
3382 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3383 NULL, "action configuration not set");
3385 ((const struct rte_flow_action_jump *)action->conf)->group;
3386 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3390 if (attributes->group == target_group)
3391 return rte_flow_error_set(error, EINVAL,
3392 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3393 "target group must be other than"
3394 " the current flow group");
3399 * Validate the port_id action.
3402 * Pointer to rte_eth_dev structure.
3403 * @param[in] action_flags
3404 * Bit-fields that holds the actions detected until now.
3406 * Port_id RTE action structure.
3408 * Attributes of flow that includes this action.
3410 * Pointer to error structure.
3413 * 0 on success, a negative errno value otherwise and rte_errno is set.
3416 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3417 uint64_t action_flags,
3418 const struct rte_flow_action *action,
3419 const struct rte_flow_attr *attr,
3420 struct rte_flow_error *error)
3422 const struct rte_flow_action_port_id *port_id;
3423 struct mlx5_priv *act_priv;
3424 struct mlx5_priv *dev_priv;
3427 if (!attr->transfer)
3428 return rte_flow_error_set(error, ENOTSUP,
3429 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3431 "port id action is valid in transfer"
3433 if (!action || !action->conf)
3434 return rte_flow_error_set(error, ENOTSUP,
3435 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3437 "port id action parameters must be"
3439 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3440 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3441 return rte_flow_error_set(error, EINVAL,
3442 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3443 "can have only one fate actions in"
3445 dev_priv = mlx5_dev_to_eswitch_info(dev);
3447 return rte_flow_error_set(error, rte_errno,
3448 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3450 "failed to obtain E-Switch info");
3451 port_id = action->conf;
3452 port = port_id->original ? dev->data->port_id : port_id->id;
3453 act_priv = mlx5_port_to_eswitch_info(port, false);
3455 return rte_flow_error_set
3457 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3458 "failed to obtain E-Switch port id for port");
3459 if (act_priv->domain_id != dev_priv->domain_id)
3460 return rte_flow_error_set
3462 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3463 "port does not belong to"
3464 " E-Switch being configured");
3469 * Get the maximum number of modify header actions.
3472 * Pointer to rte_eth_dev structure.
3474 * Flags bits to check if root level.
3477 * Max number of modify header actions device can support.
3480 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3483 * There's no way to directly query the max cap. Although it has to be
3484 * acquried by iterative trial, it is a safe assumption that more
3485 * actions are supported by FW if extensive metadata register is
3486 * supported. (Only in the root table)
3488 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3489 return MLX5_MAX_MODIFY_NUM;
3491 return mlx5_flow_ext_mreg_supported(dev) ?
3492 MLX5_ROOT_TBL_MODIFY_NUM :
3493 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3497 * Validate the meter action.
3500 * Pointer to rte_eth_dev structure.
3501 * @param[in] action_flags
3502 * Bit-fields that holds the actions detected until now.
3504 * Pointer to the meter action.
3506 * Attributes of flow that includes this action.
3508 * Pointer to error structure.
3511 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3514 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3515 uint64_t action_flags,
3516 const struct rte_flow_action *action,
3517 const struct rte_flow_attr *attr,
3518 struct rte_flow_error *error)
3520 struct mlx5_priv *priv = dev->data->dev_private;
3521 const struct rte_flow_action_meter *am = action->conf;
3522 struct mlx5_flow_meter *fm;
3525 return rte_flow_error_set(error, EINVAL,
3526 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3527 "meter action conf is NULL");
3529 if (action_flags & MLX5_FLOW_ACTION_METER)
3530 return rte_flow_error_set(error, ENOTSUP,
3531 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3532 "meter chaining not support");
3533 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3534 return rte_flow_error_set(error, ENOTSUP,
3535 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3536 "meter with jump not support");
3538 return rte_flow_error_set(error, ENOTSUP,
3539 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3541 "meter action not supported");
3542 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3544 return rte_flow_error_set(error, EINVAL,
3545 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3547 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3548 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3549 (!fm->attr.egress && !attr->egress && attr->ingress))))
3550 return rte_flow_error_set(error, EINVAL,
3551 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3552 "Flow attributes are either invalid "
3553 "or have a conflict with current "
3554 "meter attributes");
3559 * Validate the modify-header IPv4 DSCP actions.
3561 * @param[in] action_flags
3562 * Holds the actions detected until now.
3564 * Pointer to the modify action.
3565 * @param[in] item_flags
3566 * Holds the items detected.
3568 * Pointer to error structure.
3571 * 0 on success, a negative errno value otherwise and rte_errno is set.
3574 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3575 const struct rte_flow_action *action,
3576 const uint64_t item_flags,
3577 struct rte_flow_error *error)
3581 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3583 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3584 return rte_flow_error_set(error, EINVAL,
3585 RTE_FLOW_ERROR_TYPE_ACTION,
3587 "no ipv4 item in pattern");
3593 * Validate the modify-header IPv6 DSCP actions.
3595 * @param[in] action_flags
3596 * Holds the actions detected until now.
3598 * Pointer to the modify action.
3599 * @param[in] item_flags
3600 * Holds the items detected.
3602 * Pointer to error structure.
3605 * 0 on success, a negative errno value otherwise and rte_errno is set.
3608 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3609 const struct rte_flow_action *action,
3610 const uint64_t item_flags,
3611 struct rte_flow_error *error)
3615 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3617 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3618 return rte_flow_error_set(error, EINVAL,
3619 RTE_FLOW_ERROR_TYPE_ACTION,
3621 "no ipv6 item in pattern");
3627 * Find existing modify-header resource or create and register a new one.
3629 * @param dev[in, out]
3630 * Pointer to rte_eth_dev structure.
3631 * @param[in, out] resource
3632 * Pointer to modify-header resource.
3633 * @parm[in, out] dev_flow
3634 * Pointer to the dev_flow.
3636 * pointer to error structure.
3639 * 0 on success otherwise -errno and errno is set.
3642 flow_dv_modify_hdr_resource_register
3643 (struct rte_eth_dev *dev,
3644 struct mlx5_flow_dv_modify_hdr_resource *resource,
3645 struct mlx5_flow *dev_flow,
3646 struct rte_flow_error *error)
3648 struct mlx5_priv *priv = dev->data->dev_private;
3649 struct mlx5_ibv_shared *sh = priv->sh;
3650 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3651 struct mlx5dv_dr_domain *ns;
3652 uint32_t actions_len;
3655 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3656 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3658 return rte_flow_error_set(error, EOVERFLOW,
3659 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3660 "too many modify header items");
3661 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3662 ns = sh->fdb_domain;
3663 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3667 /* Lookup a matching resource from cache. */
3668 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3669 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3670 if (resource->ft_type == cache_resource->ft_type &&
3671 resource->actions_num == cache_resource->actions_num &&
3672 resource->flags == cache_resource->flags &&
3673 !memcmp((const void *)resource->actions,
3674 (const void *)cache_resource->actions,
3676 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3677 (void *)cache_resource,
3678 rte_atomic32_read(&cache_resource->refcnt));
3679 rte_atomic32_inc(&cache_resource->refcnt);
3680 dev_flow->dv.modify_hdr = cache_resource;
3684 /* Register new modify-header resource. */
3685 cache_resource = rte_calloc(__func__, 1,
3686 sizeof(*cache_resource) + actions_len, 0);
3687 if (!cache_resource)
3688 return rte_flow_error_set(error, ENOMEM,
3689 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3690 "cannot allocate resource memory");
3691 *cache_resource = *resource;
3692 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3693 cache_resource->verbs_action =
3694 mlx5_glue->dv_create_flow_action_modify_header
3695 (sh->ctx, cache_resource->ft_type, ns,
3696 cache_resource->flags, actions_len,
3697 (uint64_t *)cache_resource->actions);
3698 if (!cache_resource->verbs_action) {
3699 rte_free(cache_resource);
3700 return rte_flow_error_set(error, ENOMEM,
3701 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3702 NULL, "cannot create action");
3704 rte_atomic32_init(&cache_resource->refcnt);
3705 rte_atomic32_inc(&cache_resource->refcnt);
3706 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3707 dev_flow->dv.modify_hdr = cache_resource;
3708 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3709 (void *)cache_resource,
3710 rte_atomic32_read(&cache_resource->refcnt));
3714 #define MLX5_CNT_CONTAINER_RESIZE 64
3717 * Get or create a flow counter.
3720 * Pointer to the Ethernet device structure.
3722 * Indicate if this counter is shared with other flows.
3724 * Counter identifier.
3727 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3729 static struct mlx5_flow_counter *
3730 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3733 struct mlx5_priv *priv = dev->data->dev_private;
3734 struct mlx5_flow_counter *cnt = NULL;
3735 struct mlx5_devx_obj *dcs = NULL;
3737 if (!priv->config.devx) {
3738 rte_errno = ENOTSUP;
3742 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3743 if (cnt->shared && cnt->id == id) {
3749 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3752 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3754 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3758 struct mlx5_flow_counter tmpl = {
3764 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3766 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3772 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3777 * Release a flow counter.
3780 * Pointer to the Ethernet device structure.
3781 * @param[in] counter
3782 * Pointer to the counter handler.
3785 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3786 struct mlx5_flow_counter *counter)
3788 struct mlx5_priv *priv = dev->data->dev_private;
3792 if (--counter->ref_cnt == 0) {
3793 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3794 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3800 * Query a devx flow counter.
3803 * Pointer to the Ethernet device structure.
3805 * Pointer to the flow counter.
3807 * The statistics value of packets.
3809 * The statistics value of bytes.
3812 * 0 on success, otherwise a negative errno value and rte_errno is set.
3815 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3816 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3819 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3824 * Get a pool by a counter.
3827 * Pointer to the counter.
3832 static struct mlx5_flow_counter_pool *
3833 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3836 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3837 return (struct mlx5_flow_counter_pool *)cnt - 1;
3843 * Get a pool by devx counter ID.
3846 * Pointer to the counter container.
3848 * The counter devx ID.
3851 * The counter pool pointer if exists, NULL otherwise,
3853 static struct mlx5_flow_counter_pool *
3854 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3856 struct mlx5_flow_counter_pool *pool;
3858 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3859 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3860 MLX5_COUNTERS_PER_POOL;
3862 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3869 * Allocate a new memory for the counter values wrapped by all the needed
3873 * Pointer to the Ethernet device structure.
3875 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3878 * The new memory management pointer on success, otherwise NULL and rte_errno
3881 static struct mlx5_counter_stats_mem_mng *
3882 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3884 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3885 (dev->data->dev_private))->sh;
3886 struct mlx5_devx_mkey_attr mkey_attr;
3887 struct mlx5_counter_stats_mem_mng *mem_mng;
3888 volatile struct flow_counter_stats *raw_data;
3889 int size = (sizeof(struct flow_counter_stats) *
3890 MLX5_COUNTERS_PER_POOL +
3891 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3892 sizeof(struct mlx5_counter_stats_mem_mng);
3893 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3900 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3901 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3902 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3903 IBV_ACCESS_LOCAL_WRITE);
3904 if (!mem_mng->umem) {
3909 mkey_attr.addr = (uintptr_t)mem;
3910 mkey_attr.size = size;
3911 mkey_attr.umem_id = mem_mng->umem->umem_id;
3912 mkey_attr.pd = sh->pdn;
3913 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3915 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3920 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3921 raw_data = (volatile struct flow_counter_stats *)mem;
3922 for (i = 0; i < raws_n; ++i) {
3923 mem_mng->raws[i].mem_mng = mem_mng;
3924 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3926 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3931 * Resize a counter container.
3934 * Pointer to the Ethernet device structure.
3936 * Whether the pool is for counter that was allocated by batch command.
3939 * The new container pointer on success, otherwise NULL and rte_errno is set.
3941 static struct mlx5_pools_container *
3942 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3944 struct mlx5_priv *priv = dev->data->dev_private;
3945 struct mlx5_pools_container *cont =
3946 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3947 struct mlx5_pools_container *new_cont =
3948 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3949 struct mlx5_counter_stats_mem_mng *mem_mng;
3950 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3951 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3954 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3955 /* The last resize still hasn't detected by the host thread. */
3959 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3960 if (!new_cont->pools) {
3965 memcpy(new_cont->pools, cont->pools, cont->n *
3966 sizeof(struct mlx5_flow_counter_pool *));
3967 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3968 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3970 rte_free(new_cont->pools);
3973 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3974 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3975 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3977 new_cont->n = resize;
3978 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3979 TAILQ_INIT(&new_cont->pool_list);
3980 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3981 new_cont->init_mem_mng = mem_mng;
3983 /* Flip the master container. */
3984 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3989 * Query a devx flow counter.
3992 * Pointer to the Ethernet device structure.
3994 * Pointer to the flow counter.
3996 * The statistics value of packets.
3998 * The statistics value of bytes.
4001 * 0 on success, otherwise a negative errno value and rte_errno is set.
4004 _flow_dv_query_count(struct rte_eth_dev *dev,
4005 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4008 struct mlx5_priv *priv = dev->data->dev_private;
4009 struct mlx5_flow_counter_pool *pool =
4010 flow_dv_counter_pool_get(cnt);
4011 int offset = cnt - &pool->counters_raw[0];
4013 if (priv->counter_fallback)
4014 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4016 rte_spinlock_lock(&pool->sl);
4018 * The single counters allocation may allocate smaller ID than the
4019 * current allocated in parallel to the host reading.
4020 * In this case the new counter values must be reported as 0.
4022 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4026 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4027 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4029 rte_spinlock_unlock(&pool->sl);
4034 * Create and initialize a new counter pool.
4037 * Pointer to the Ethernet device structure.
4039 * The devX counter handle.
4041 * Whether the pool is for counter that was allocated by batch command.
4044 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4046 static struct mlx5_flow_counter_pool *
4047 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4050 struct mlx5_priv *priv = dev->data->dev_private;
4051 struct mlx5_flow_counter_pool *pool;
4052 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4054 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4057 if (cont->n == n_valid) {
4058 cont = flow_dv_container_resize(dev, batch);
4062 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4063 sizeof(struct mlx5_flow_counter);
4064 pool = rte_calloc(__func__, 1, size, 0);
4069 pool->min_dcs = dcs;
4070 pool->raw = cont->init_mem_mng->raws + n_valid %
4071 MLX5_CNT_CONTAINER_RESIZE;
4072 pool->raw_hw = NULL;
4073 rte_spinlock_init(&pool->sl);
4075 * The generation of the new allocated counters in this pool is 0, 2 in
4076 * the pool generation makes all the counters valid for allocation.
4078 rte_atomic64_set(&pool->query_gen, 0x2);
4079 TAILQ_INIT(&pool->counters);
4080 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4081 cont->pools[n_valid] = pool;
4082 /* Pool initialization must be updated before host thread access. */
4084 rte_atomic16_add(&cont->n_valid, 1);
4089 * Prepare a new counter and/or a new counter pool.
4092 * Pointer to the Ethernet device structure.
4093 * @param[out] cnt_free
4094 * Where to put the pointer of a new counter.
4096 * Whether the pool is for counter that was allocated by batch command.
4099 * The free counter pool pointer and @p cnt_free is set on success,
4100 * NULL otherwise and rte_errno is set.
4102 static struct mlx5_flow_counter_pool *
4103 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4104 struct mlx5_flow_counter **cnt_free,
4107 struct mlx5_priv *priv = dev->data->dev_private;
4108 struct mlx5_flow_counter_pool *pool;
4109 struct mlx5_devx_obj *dcs = NULL;
4110 struct mlx5_flow_counter *cnt;
4114 /* bulk_bitmap must be 0 for single counter allocation. */
4115 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4118 pool = flow_dv_find_pool_by_id
4119 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4121 pool = flow_dv_pool_create(dev, dcs, batch);
4123 mlx5_devx_cmd_destroy(dcs);
4126 } else if (dcs->id < pool->min_dcs->id) {
4127 rte_atomic64_set(&pool->a64_dcs,
4128 (int64_t)(uintptr_t)dcs);
4130 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4131 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4136 /* bulk_bitmap is in 128 counters units. */
4137 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4138 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4140 rte_errno = ENODATA;
4143 pool = flow_dv_pool_create(dev, dcs, batch);
4145 mlx5_devx_cmd_destroy(dcs);
4148 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4149 cnt = &pool->counters_raw[i];
4151 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4153 *cnt_free = &pool->counters_raw[0];
4158 * Search for existed shared counter.
4161 * Pointer to the relevant counter pool container.
4163 * The shared counter ID to search.
4166 * NULL if not existed, otherwise pointer to the shared counter.
4168 static struct mlx5_flow_counter *
4169 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4172 static struct mlx5_flow_counter *cnt;
4173 struct mlx5_flow_counter_pool *pool;
4176 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4177 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4178 cnt = &pool->counters_raw[i];
4179 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4187 * Allocate a flow counter.
4190 * Pointer to the Ethernet device structure.
4192 * Indicate if this counter is shared with other flows.
4194 * Counter identifier.
4196 * Counter flow group.
4199 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4201 static struct mlx5_flow_counter *
4202 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4205 struct mlx5_priv *priv = dev->data->dev_private;
4206 struct mlx5_flow_counter_pool *pool = NULL;
4207 struct mlx5_flow_counter *cnt_free = NULL;
4209 * Currently group 0 flow counter cannot be assigned to a flow if it is
4210 * not the first one in the batch counter allocation, so it is better
4211 * to allocate counters one by one for these flows in a separate
4213 * A counter can be shared between different groups so need to take
4214 * shared counters from the single container.
4216 uint32_t batch = (group && !shared) ? 1 : 0;
4217 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4220 if (priv->counter_fallback)
4221 return flow_dv_counter_alloc_fallback(dev, shared, id);
4222 if (!priv->config.devx) {
4223 rte_errno = ENOTSUP;
4227 cnt_free = flow_dv_counter_shared_search(cont, id);
4229 if (cnt_free->ref_cnt + 1 == 0) {
4233 cnt_free->ref_cnt++;
4237 /* Pools which has a free counters are in the start. */
4238 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4240 * The free counter reset values must be updated between the
4241 * counter release to the counter allocation, so, at least one
4242 * query must be done in this time. ensure it by saving the
4243 * query generation in the release time.
4244 * The free list is sorted according to the generation - so if
4245 * the first one is not updated, all the others are not
4248 cnt_free = TAILQ_FIRST(&pool->counters);
4249 if (cnt_free && cnt_free->query_gen + 1 <
4250 rte_atomic64_read(&pool->query_gen))
4255 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4259 cnt_free->batch = batch;
4260 /* Create a DV counter action only in the first time usage. */
4261 if (!cnt_free->action) {
4263 struct mlx5_devx_obj *dcs;
4266 offset = cnt_free - &pool->counters_raw[0];
4267 dcs = pool->min_dcs;
4270 dcs = cnt_free->dcs;
4272 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4274 if (!cnt_free->action) {
4279 /* Update the counter reset values. */
4280 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4283 cnt_free->shared = shared;
4284 cnt_free->ref_cnt = 1;
4286 if (!priv->sh->cmng.query_thread_on)
4287 /* Start the asynchronous batch query by the host thread. */
4288 mlx5_set_query_alarm(priv->sh);
4289 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4290 if (TAILQ_EMPTY(&pool->counters)) {
4291 /* Move the pool to the end of the container pool list. */
4292 TAILQ_REMOVE(&cont->pool_list, pool, next);
4293 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4299 * Release a flow counter.
4302 * Pointer to the Ethernet device structure.
4303 * @param[in] counter
4304 * Pointer to the counter handler.
4307 flow_dv_counter_release(struct rte_eth_dev *dev,
4308 struct mlx5_flow_counter *counter)
4310 struct mlx5_priv *priv = dev->data->dev_private;
4314 if (priv->counter_fallback) {
4315 flow_dv_counter_release_fallback(dev, counter);
4318 if (--counter->ref_cnt == 0) {
4319 struct mlx5_flow_counter_pool *pool =
4320 flow_dv_counter_pool_get(counter);
4322 /* Put the counter in the end - the last updated one. */
4323 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4324 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4329 * Verify the @p attributes will be correctly understood by the NIC and store
4330 * them in the @p flow if everything is correct.
4333 * Pointer to dev struct.
4334 * @param[in] attributes
4335 * Pointer to flow attributes
4336 * @param[in] external
4337 * This flow rule is created by request external to PMD.
4339 * Pointer to error structure.
4342 * 0 on success, a negative errno value otherwise and rte_errno is set.
4345 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4346 const struct rte_flow_attr *attributes,
4347 bool external __rte_unused,
4348 struct rte_flow_error *error)
4350 struct mlx5_priv *priv = dev->data->dev_private;
4351 uint32_t priority_max = priv->config.flow_prio - 1;
4353 #ifndef HAVE_MLX5DV_DR
4354 if (attributes->group)
4355 return rte_flow_error_set(error, ENOTSUP,
4356 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4358 "groups are not supported");
4363 ret = mlx5_flow_group_to_table(attributes, external,
4369 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4370 attributes->priority >= priority_max)
4371 return rte_flow_error_set(error, ENOTSUP,
4372 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4374 "priority out of range");
4375 if (attributes->transfer) {
4376 if (!priv->config.dv_esw_en)
4377 return rte_flow_error_set
4379 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4380 "E-Switch dr is not supported");
4381 if (!(priv->representor || priv->master))
4382 return rte_flow_error_set
4383 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4384 NULL, "E-Switch configuration can only be"
4385 " done by a master or a representor device");
4386 if (attributes->egress)
4387 return rte_flow_error_set
4389 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4390 "egress is not supported");
4392 if (!(attributes->egress ^ attributes->ingress))
4393 return rte_flow_error_set(error, ENOTSUP,
4394 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4395 "must specify exactly one of "
4396 "ingress or egress");
4401 * Internal validation function. For validating both actions and items.
4404 * Pointer to the rte_eth_dev structure.
4406 * Pointer to the flow attributes.
4408 * Pointer to the list of items.
4409 * @param[in] actions
4410 * Pointer to the list of actions.
4411 * @param[in] external
4412 * This flow rule is created by request external to PMD.
4414 * Pointer to the error structure.
4417 * 0 on success, a negative errno value otherwise and rte_errno is set.
4420 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4421 const struct rte_flow_item items[],
4422 const struct rte_flow_action actions[],
4423 bool external, struct rte_flow_error *error)
4426 uint64_t action_flags = 0;
4427 uint64_t item_flags = 0;
4428 uint64_t last_item = 0;
4429 uint8_t next_protocol = 0xff;
4430 uint16_t ether_type = 0;
4432 const struct rte_flow_item *gre_item = NULL;
4433 struct rte_flow_item_tcp nic_tcp_mask = {
4436 .src_port = RTE_BE16(UINT16_MAX),
4437 .dst_port = RTE_BE16(UINT16_MAX),
4440 struct mlx5_priv *priv = dev->data->dev_private;
4441 struct mlx5_dev_config *dev_conf = &priv->config;
4445 ret = flow_dv_validate_attributes(dev, attr, external, error);
4448 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4449 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4450 int type = items->type;
4453 case RTE_FLOW_ITEM_TYPE_VOID:
4455 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4456 ret = flow_dv_validate_item_port_id
4457 (dev, items, attr, item_flags, error);
4460 last_item = MLX5_FLOW_ITEM_PORT_ID;
4462 case RTE_FLOW_ITEM_TYPE_ETH:
4463 ret = mlx5_flow_validate_item_eth(items, item_flags,
4467 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4468 MLX5_FLOW_LAYER_OUTER_L2;
4469 if (items->mask != NULL && items->spec != NULL) {
4471 ((const struct rte_flow_item_eth *)
4474 ((const struct rte_flow_item_eth *)
4476 ether_type = rte_be_to_cpu_16(ether_type);
4481 case RTE_FLOW_ITEM_TYPE_VLAN:
4482 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4486 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4487 MLX5_FLOW_LAYER_OUTER_VLAN;
4488 if (items->mask != NULL && items->spec != NULL) {
4490 ((const struct rte_flow_item_vlan *)
4491 items->spec)->inner_type;
4493 ((const struct rte_flow_item_vlan *)
4494 items->mask)->inner_type;
4495 ether_type = rte_be_to_cpu_16(ether_type);
4500 case RTE_FLOW_ITEM_TYPE_IPV4:
4501 mlx5_flow_tunnel_ip_check(items, next_protocol,
4502 &item_flags, &tunnel);
4503 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4509 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4510 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4511 if (items->mask != NULL &&
4512 ((const struct rte_flow_item_ipv4 *)
4513 items->mask)->hdr.next_proto_id) {
4515 ((const struct rte_flow_item_ipv4 *)
4516 (items->spec))->hdr.next_proto_id;
4518 ((const struct rte_flow_item_ipv4 *)
4519 (items->mask))->hdr.next_proto_id;
4521 /* Reset for inner layer. */
4522 next_protocol = 0xff;
4525 case RTE_FLOW_ITEM_TYPE_IPV6:
4526 mlx5_flow_tunnel_ip_check(items, next_protocol,
4527 &item_flags, &tunnel);
4528 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4534 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4535 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4536 if (items->mask != NULL &&
4537 ((const struct rte_flow_item_ipv6 *)
4538 items->mask)->hdr.proto) {
4540 ((const struct rte_flow_item_ipv6 *)
4541 items->spec)->hdr.proto;
4543 ((const struct rte_flow_item_ipv6 *)
4544 items->mask)->hdr.proto;
4546 /* Reset for inner layer. */
4547 next_protocol = 0xff;
4550 case RTE_FLOW_ITEM_TYPE_TCP:
4551 ret = mlx5_flow_validate_item_tcp
4558 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4559 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4561 case RTE_FLOW_ITEM_TYPE_UDP:
4562 ret = mlx5_flow_validate_item_udp(items, item_flags,
4567 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4568 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4570 case RTE_FLOW_ITEM_TYPE_GRE:
4571 ret = mlx5_flow_validate_item_gre(items, item_flags,
4572 next_protocol, error);
4576 last_item = MLX5_FLOW_LAYER_GRE;
4578 case RTE_FLOW_ITEM_TYPE_NVGRE:
4579 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4584 last_item = MLX5_FLOW_LAYER_NVGRE;
4586 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4587 ret = mlx5_flow_validate_item_gre_key
4588 (items, item_flags, gre_item, error);
4591 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4593 case RTE_FLOW_ITEM_TYPE_VXLAN:
4594 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4598 last_item = MLX5_FLOW_LAYER_VXLAN;
4600 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4601 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4606 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4608 case RTE_FLOW_ITEM_TYPE_GENEVE:
4609 ret = mlx5_flow_validate_item_geneve(items,
4614 last_item = MLX5_FLOW_LAYER_GENEVE;
4616 case RTE_FLOW_ITEM_TYPE_MPLS:
4617 ret = mlx5_flow_validate_item_mpls(dev, items,
4622 last_item = MLX5_FLOW_LAYER_MPLS;
4625 case RTE_FLOW_ITEM_TYPE_MARK:
4626 ret = flow_dv_validate_item_mark(dev, items, attr,
4630 last_item = MLX5_FLOW_ITEM_MARK;
4632 case RTE_FLOW_ITEM_TYPE_META:
4633 ret = flow_dv_validate_item_meta(dev, items, attr,
4637 last_item = MLX5_FLOW_ITEM_METADATA;
4639 case RTE_FLOW_ITEM_TYPE_ICMP:
4640 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4645 last_item = MLX5_FLOW_LAYER_ICMP;
4647 case RTE_FLOW_ITEM_TYPE_ICMP6:
4648 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4653 last_item = MLX5_FLOW_LAYER_ICMP6;
4655 case RTE_FLOW_ITEM_TYPE_TAG:
4656 ret = flow_dv_validate_item_tag(dev, items,
4660 last_item = MLX5_FLOW_ITEM_TAG;
4662 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4663 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4665 case RTE_FLOW_ITEM_TYPE_GTP:
4666 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4670 last_item = MLX5_FLOW_LAYER_GTP;
4673 return rte_flow_error_set(error, ENOTSUP,
4674 RTE_FLOW_ERROR_TYPE_ITEM,
4675 NULL, "item not supported");
4677 item_flags |= last_item;
4679 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4680 int type = actions->type;
4681 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4682 return rte_flow_error_set(error, ENOTSUP,
4683 RTE_FLOW_ERROR_TYPE_ACTION,
4684 actions, "too many actions");
4686 case RTE_FLOW_ACTION_TYPE_VOID:
4688 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4689 ret = flow_dv_validate_action_port_id(dev,
4696 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4699 case RTE_FLOW_ACTION_TYPE_FLAG:
4700 ret = flow_dv_validate_action_flag(dev, action_flags,
4704 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4705 /* Count all modify-header actions as one. */
4706 if (!(action_flags &
4707 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4709 action_flags |= MLX5_FLOW_ACTION_FLAG |
4710 MLX5_FLOW_ACTION_MARK_EXT;
4712 action_flags |= MLX5_FLOW_ACTION_FLAG;
4716 case RTE_FLOW_ACTION_TYPE_MARK:
4717 ret = flow_dv_validate_action_mark(dev, actions,
4722 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4723 /* Count all modify-header actions as one. */
4724 if (!(action_flags &
4725 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4727 action_flags |= MLX5_FLOW_ACTION_MARK |
4728 MLX5_FLOW_ACTION_MARK_EXT;
4730 action_flags |= MLX5_FLOW_ACTION_MARK;
4734 case RTE_FLOW_ACTION_TYPE_SET_META:
4735 ret = flow_dv_validate_action_set_meta(dev, actions,
4740 /* Count all modify-header actions as one action. */
4741 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4743 action_flags |= MLX5_FLOW_ACTION_SET_META;
4745 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4746 ret = flow_dv_validate_action_set_tag(dev, actions,
4751 /* Count all modify-header actions as one action. */
4752 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4754 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4756 case RTE_FLOW_ACTION_TYPE_DROP:
4757 ret = mlx5_flow_validate_action_drop(action_flags,
4761 action_flags |= MLX5_FLOW_ACTION_DROP;
4764 case RTE_FLOW_ACTION_TYPE_QUEUE:
4765 ret = mlx5_flow_validate_action_queue(actions,
4770 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4773 case RTE_FLOW_ACTION_TYPE_RSS:
4774 ret = mlx5_flow_validate_action_rss(actions,
4780 action_flags |= MLX5_FLOW_ACTION_RSS;
4783 case RTE_FLOW_ACTION_TYPE_COUNT:
4784 ret = flow_dv_validate_action_count(dev, error);
4787 action_flags |= MLX5_FLOW_ACTION_COUNT;
4790 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4791 if (flow_dv_validate_action_pop_vlan(dev,
4797 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4800 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4801 ret = flow_dv_validate_action_push_vlan(action_flags,
4807 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4810 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4811 ret = flow_dv_validate_action_set_vlan_pcp
4812 (action_flags, actions, error);
4815 /* Count PCP with push_vlan command. */
4816 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4818 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4819 ret = flow_dv_validate_action_set_vlan_vid
4820 (item_flags, action_flags,
4824 /* Count VID with push_vlan command. */
4825 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4827 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4828 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4829 ret = flow_dv_validate_action_l2_encap(action_flags,
4834 action_flags |= actions->type ==
4835 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4836 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4837 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4840 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4841 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4842 ret = flow_dv_validate_action_l2_decap(action_flags,
4846 action_flags |= actions->type ==
4847 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4848 MLX5_FLOW_ACTION_VXLAN_DECAP :
4849 MLX5_FLOW_ACTION_NVGRE_DECAP;
4852 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4853 ret = flow_dv_validate_action_raw_encap(action_flags,
4858 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4861 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4862 ret = flow_dv_validate_action_raw_decap(action_flags,
4867 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4870 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4871 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4872 ret = flow_dv_validate_action_modify_mac(action_flags,
4878 /* Count all modify-header actions as one action. */
4879 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4881 action_flags |= actions->type ==
4882 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4883 MLX5_FLOW_ACTION_SET_MAC_SRC :
4884 MLX5_FLOW_ACTION_SET_MAC_DST;
4887 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4888 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4889 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4895 /* Count all modify-header actions as one action. */
4896 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4898 action_flags |= actions->type ==
4899 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4900 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4901 MLX5_FLOW_ACTION_SET_IPV4_DST;
4903 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4904 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4905 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4911 /* Count all modify-header actions as one action. */
4912 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4914 action_flags |= actions->type ==
4915 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4916 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4917 MLX5_FLOW_ACTION_SET_IPV6_DST;
4919 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4920 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4921 ret = flow_dv_validate_action_modify_tp(action_flags,
4927 /* Count all modify-header actions as one action. */
4928 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4930 action_flags |= actions->type ==
4931 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4932 MLX5_FLOW_ACTION_SET_TP_SRC :
4933 MLX5_FLOW_ACTION_SET_TP_DST;
4935 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4936 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4937 ret = flow_dv_validate_action_modify_ttl(action_flags,
4943 /* Count all modify-header actions as one action. */
4944 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4946 action_flags |= actions->type ==
4947 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4948 MLX5_FLOW_ACTION_SET_TTL :
4949 MLX5_FLOW_ACTION_DEC_TTL;
4951 case RTE_FLOW_ACTION_TYPE_JUMP:
4952 ret = flow_dv_validate_action_jump(actions,
4959 action_flags |= MLX5_FLOW_ACTION_JUMP;
4961 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4962 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4963 ret = flow_dv_validate_action_modify_tcp_seq
4970 /* Count all modify-header actions as one action. */
4971 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4973 action_flags |= actions->type ==
4974 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4975 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4976 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4978 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4979 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4980 ret = flow_dv_validate_action_modify_tcp_ack
4987 /* Count all modify-header actions as one action. */
4988 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4990 action_flags |= actions->type ==
4991 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4992 MLX5_FLOW_ACTION_INC_TCP_ACK :
4993 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4995 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4996 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
4997 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4999 case RTE_FLOW_ACTION_TYPE_METER:
5000 ret = mlx5_flow_validate_action_meter(dev,
5006 action_flags |= MLX5_FLOW_ACTION_METER;
5009 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5010 ret = flow_dv_validate_action_modify_ipv4_dscp
5017 /* Count all modify-header actions as one action. */
5018 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5020 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5022 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5023 ret = flow_dv_validate_action_modify_ipv6_dscp
5030 /* Count all modify-header actions as one action. */
5031 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5033 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5036 return rte_flow_error_set(error, ENOTSUP,
5037 RTE_FLOW_ERROR_TYPE_ACTION,
5039 "action not supported");
5043 * Validate the drop action mutual exclusion with other actions.
5044 * Drop action is mutually-exclusive with any other action, except for
5047 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5048 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5049 return rte_flow_error_set(error, EINVAL,
5050 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5051 "Drop action is mutually-exclusive "
5052 "with any other action, except for "
5054 /* Eswitch has few restrictions on using items and actions */
5055 if (attr->transfer) {
5056 if (!mlx5_flow_ext_mreg_supported(dev) &&
5057 action_flags & MLX5_FLOW_ACTION_FLAG)
5058 return rte_flow_error_set(error, ENOTSUP,
5059 RTE_FLOW_ERROR_TYPE_ACTION,
5061 "unsupported action FLAG");
5062 if (!mlx5_flow_ext_mreg_supported(dev) &&
5063 action_flags & MLX5_FLOW_ACTION_MARK)
5064 return rte_flow_error_set(error, ENOTSUP,
5065 RTE_FLOW_ERROR_TYPE_ACTION,
5067 "unsupported action MARK");
5068 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5069 return rte_flow_error_set(error, ENOTSUP,
5070 RTE_FLOW_ERROR_TYPE_ACTION,
5072 "unsupported action QUEUE");
5073 if (action_flags & MLX5_FLOW_ACTION_RSS)
5074 return rte_flow_error_set(error, ENOTSUP,
5075 RTE_FLOW_ERROR_TYPE_ACTION,
5077 "unsupported action RSS");
5078 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5079 return rte_flow_error_set(error, EINVAL,
5080 RTE_FLOW_ERROR_TYPE_ACTION,
5082 "no fate action is found");
5084 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5085 return rte_flow_error_set(error, EINVAL,
5086 RTE_FLOW_ERROR_TYPE_ACTION,
5088 "no fate action is found");
5094 * Internal preparation function. Allocates the DV flow size,
5095 * this size is constant.
5098 * Pointer to the flow attributes.
5100 * Pointer to the list of items.
5101 * @param[in] actions
5102 * Pointer to the list of actions.
5104 * Pointer to the error structure.
5107 * Pointer to mlx5_flow object on success,
5108 * otherwise NULL and rte_errno is set.
5110 static struct mlx5_flow *
5111 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5112 const struct rte_flow_item items[] __rte_unused,
5113 const struct rte_flow_action actions[] __rte_unused,
5114 struct rte_flow_error *error)
5116 size_t size = sizeof(struct mlx5_flow);
5117 struct mlx5_flow *dev_flow;
5119 dev_flow = rte_calloc(__func__, 1, size, 0);
5121 rte_flow_error_set(error, ENOMEM,
5122 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5123 "not enough memory to create flow");
5126 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5127 dev_flow->ingress = attr->ingress;
5128 dev_flow->transfer = attr->transfer;
5134 * Sanity check for match mask and value. Similar to check_valid_spec() in
5135 * kernel driver. If unmasked bit is present in value, it returns failure.
5138 * pointer to match mask buffer.
5139 * @param match_value
5140 * pointer to match value buffer.
5143 * 0 if valid, -EINVAL otherwise.
5146 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5148 uint8_t *m = match_mask;
5149 uint8_t *v = match_value;
5152 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5155 "match_value differs from match_criteria"
5156 " %p[%u] != %p[%u]",
5157 match_value, i, match_mask, i);
5166 * Add Ethernet item to matcher and to the value.
5168 * @param[in, out] matcher
5170 * @param[in, out] key
5171 * Flow matcher value.
5173 * Flow pattern to translate.
5175 * Item is inner pattern.
5178 flow_dv_translate_item_eth(void *matcher, void *key,
5179 const struct rte_flow_item *item, int inner)
5181 const struct rte_flow_item_eth *eth_m = item->mask;
5182 const struct rte_flow_item_eth *eth_v = item->spec;
5183 const struct rte_flow_item_eth nic_mask = {
5184 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5185 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5186 .type = RTE_BE16(0xffff),
5198 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5200 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5202 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5204 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5206 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5207 ð_m->dst, sizeof(eth_m->dst));
5208 /* The value must be in the range of the mask. */
5209 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5210 for (i = 0; i < sizeof(eth_m->dst); ++i)
5211 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5212 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5213 ð_m->src, sizeof(eth_m->src));
5214 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5215 /* The value must be in the range of the mask. */
5216 for (i = 0; i < sizeof(eth_m->dst); ++i)
5217 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5218 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5219 rte_be_to_cpu_16(eth_m->type));
5220 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5221 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5225 * Add VLAN item to matcher and to the value.
5227 * @param[in, out] dev_flow
5229 * @param[in, out] matcher
5231 * @param[in, out] key
5232 * Flow matcher value.
5234 * Flow pattern to translate.
5236 * Item is inner pattern.
5239 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5240 void *matcher, void *key,
5241 const struct rte_flow_item *item,
5244 const struct rte_flow_item_vlan *vlan_m = item->mask;
5245 const struct rte_flow_item_vlan *vlan_v = item->spec;
5254 vlan_m = &rte_flow_item_vlan_mask;
5256 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5258 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5260 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5262 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5264 * This is workaround, masks are not supported,
5265 * and pre-validated.
5267 dev_flow->dv.vf_vlan.tag =
5268 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5270 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5271 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5272 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5273 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5274 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5275 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5276 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5277 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5278 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5279 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5280 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5281 rte_be_to_cpu_16(vlan_m->inner_type));
5282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5283 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5287 * Add IPV4 item to matcher and to the value.
5289 * @param[in, out] matcher
5291 * @param[in, out] key
5292 * Flow matcher value.
5294 * Flow pattern to translate.
5296 * Item is inner pattern.
5298 * The group to insert the rule.
5301 flow_dv_translate_item_ipv4(void *matcher, void *key,
5302 const struct rte_flow_item *item,
5303 int inner, uint32_t group)
5305 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5306 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5307 const struct rte_flow_item_ipv4 nic_mask = {
5309 .src_addr = RTE_BE32(0xffffffff),
5310 .dst_addr = RTE_BE32(0xffffffff),
5311 .type_of_service = 0xff,
5312 .next_proto_id = 0xff,
5322 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5324 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5326 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5328 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5331 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5333 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5334 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5339 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5340 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5341 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5342 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5343 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5344 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5345 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5346 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5347 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5348 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5349 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5350 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5351 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5352 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5353 ipv4_m->hdr.type_of_service);
5354 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5355 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5356 ipv4_m->hdr.type_of_service >> 2);
5357 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5358 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5359 ipv4_m->hdr.next_proto_id);
5360 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5361 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5365 * Add IPV6 item to matcher and to the value.
5367 * @param[in, out] matcher
5369 * @param[in, out] key
5370 * Flow matcher value.
5372 * Flow pattern to translate.
5374 * Item is inner pattern.
5376 * The group to insert the rule.
5379 flow_dv_translate_item_ipv6(void *matcher, void *key,
5380 const struct rte_flow_item *item,
5381 int inner, uint32_t group)
5383 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5384 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5385 const struct rte_flow_item_ipv6 nic_mask = {
5388 "\xff\xff\xff\xff\xff\xff\xff\xff"
5389 "\xff\xff\xff\xff\xff\xff\xff\xff",
5391 "\xff\xff\xff\xff\xff\xff\xff\xff"
5392 "\xff\xff\xff\xff\xff\xff\xff\xff",
5393 .vtc_flow = RTE_BE32(0xffffffff),
5400 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5401 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5410 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5412 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5414 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5416 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5419 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5421 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5422 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5427 size = sizeof(ipv6_m->hdr.dst_addr);
5428 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5429 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5430 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5431 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5432 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5433 for (i = 0; i < size; ++i)
5434 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5435 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5436 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5437 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5438 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5439 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5440 for (i = 0; i < size; ++i)
5441 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5443 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5444 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5445 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5446 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5447 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5448 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5451 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5453 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5456 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5458 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5462 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5464 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5465 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5469 * Add TCP item to matcher and to the value.
5471 * @param[in, out] matcher
5473 * @param[in, out] key
5474 * Flow matcher value.
5476 * Flow pattern to translate.
5478 * Item is inner pattern.
5481 flow_dv_translate_item_tcp(void *matcher, void *key,
5482 const struct rte_flow_item *item,
5485 const struct rte_flow_item_tcp *tcp_m = item->mask;
5486 const struct rte_flow_item_tcp *tcp_v = item->spec;
5491 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5493 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5495 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5497 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5499 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5504 tcp_m = &rte_flow_item_tcp_mask;
5505 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5506 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5508 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5509 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5510 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5512 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5513 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5514 tcp_m->hdr.tcp_flags);
5515 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5516 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5520 * Add UDP item to matcher and to the value.
5522 * @param[in, out] matcher
5524 * @param[in, out] key
5525 * Flow matcher value.
5527 * Flow pattern to translate.
5529 * Item is inner pattern.
5532 flow_dv_translate_item_udp(void *matcher, void *key,
5533 const struct rte_flow_item *item,
5536 const struct rte_flow_item_udp *udp_m = item->mask;
5537 const struct rte_flow_item_udp *udp_v = item->spec;
5542 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5544 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5546 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5548 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5550 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5551 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5555 udp_m = &rte_flow_item_udp_mask;
5556 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5557 rte_be_to_cpu_16(udp_m->hdr.src_port));
5558 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5559 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5560 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5561 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5562 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5563 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5567 * Add GRE optional Key item to matcher and to the value.
5569 * @param[in, out] matcher
5571 * @param[in, out] key
5572 * Flow matcher value.
5574 * Flow pattern to translate.
5576 * Item is inner pattern.
5579 flow_dv_translate_item_gre_key(void *matcher, void *key,
5580 const struct rte_flow_item *item)
5582 const rte_be32_t *key_m = item->mask;
5583 const rte_be32_t *key_v = item->spec;
5584 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5585 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5586 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5591 key_m = &gre_key_default_mask;
5592 /* GRE K bit must be on and should already be validated */
5593 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5594 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5595 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5596 rte_be_to_cpu_32(*key_m) >> 8);
5597 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5598 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5599 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5600 rte_be_to_cpu_32(*key_m) & 0xFF);
5601 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5602 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5606 * Add GRE item to matcher and to the value.
5608 * @param[in, out] matcher
5610 * @param[in, out] key
5611 * Flow matcher value.
5613 * Flow pattern to translate.
5615 * Item is inner pattern.
5618 flow_dv_translate_item_gre(void *matcher, void *key,
5619 const struct rte_flow_item *item,
5622 const struct rte_flow_item_gre *gre_m = item->mask;
5623 const struct rte_flow_item_gre *gre_v = item->spec;
5626 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5627 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5634 uint16_t s_present:1;
5635 uint16_t k_present:1;
5636 uint16_t rsvd_bit1:1;
5637 uint16_t c_present:1;
5641 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5644 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5646 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5648 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5650 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5652 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5653 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5657 gre_m = &rte_flow_item_gre_mask;
5658 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5659 rte_be_to_cpu_16(gre_m->protocol));
5660 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5661 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5662 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5663 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5664 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5665 gre_crks_rsvd0_ver_m.c_present);
5666 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5667 gre_crks_rsvd0_ver_v.c_present &
5668 gre_crks_rsvd0_ver_m.c_present);
5669 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5670 gre_crks_rsvd0_ver_m.k_present);
5671 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5672 gre_crks_rsvd0_ver_v.k_present &
5673 gre_crks_rsvd0_ver_m.k_present);
5674 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5675 gre_crks_rsvd0_ver_m.s_present);
5676 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5677 gre_crks_rsvd0_ver_v.s_present &
5678 gre_crks_rsvd0_ver_m.s_present);
5682 * Add NVGRE item to matcher and to the value.
5684 * @param[in, out] matcher
5686 * @param[in, out] key
5687 * Flow matcher value.
5689 * Flow pattern to translate.
5691 * Item is inner pattern.
5694 flow_dv_translate_item_nvgre(void *matcher, void *key,
5695 const struct rte_flow_item *item,
5698 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5699 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5700 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5701 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5702 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5703 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5709 /* For NVGRE, GRE header fields must be set with defined values. */
5710 const struct rte_flow_item_gre gre_spec = {
5711 .c_rsvd0_ver = RTE_BE16(0x2000),
5712 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5714 const struct rte_flow_item_gre gre_mask = {
5715 .c_rsvd0_ver = RTE_BE16(0xB000),
5716 .protocol = RTE_BE16(UINT16_MAX),
5718 const struct rte_flow_item gre_item = {
5723 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5727 nvgre_m = &rte_flow_item_nvgre_mask;
5728 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5729 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5730 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5731 memcpy(gre_key_m, tni_flow_id_m, size);
5732 for (i = 0; i < size; ++i)
5733 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5737 * Add VXLAN item to matcher and to the value.
5739 * @param[in, out] matcher
5741 * @param[in, out] key
5742 * Flow matcher value.
5744 * Flow pattern to translate.
5746 * Item is inner pattern.
5749 flow_dv_translate_item_vxlan(void *matcher, void *key,
5750 const struct rte_flow_item *item,
5753 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5754 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5757 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5758 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5766 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5768 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5770 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5772 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5774 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5775 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5776 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5777 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5778 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5783 vxlan_m = &rte_flow_item_vxlan_mask;
5784 size = sizeof(vxlan_m->vni);
5785 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5786 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5787 memcpy(vni_m, vxlan_m->vni, size);
5788 for (i = 0; i < size; ++i)
5789 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5793 * Add Geneve item to matcher and to the value.
5795 * @param[in, out] matcher
5797 * @param[in, out] key
5798 * Flow matcher value.
5800 * Flow pattern to translate.
5802 * Item is inner pattern.
5806 flow_dv_translate_item_geneve(void *matcher, void *key,
5807 const struct rte_flow_item *item, int inner)
5809 const struct rte_flow_item_geneve *geneve_m = item->mask;
5810 const struct rte_flow_item_geneve *geneve_v = item->spec;
5813 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5814 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5823 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5825 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5827 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5829 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5831 dport = MLX5_UDP_PORT_GENEVE;
5832 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5833 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5834 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5839 geneve_m = &rte_flow_item_geneve_mask;
5840 size = sizeof(geneve_m->vni);
5841 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5842 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5843 memcpy(vni_m, geneve_m->vni, size);
5844 for (i = 0; i < size; ++i)
5845 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5846 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5847 rte_be_to_cpu_16(geneve_m->protocol));
5848 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5849 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5850 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5851 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5852 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5853 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5854 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5855 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5856 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5857 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5858 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5859 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5860 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5864 * Add MPLS item to matcher and to the value.
5866 * @param[in, out] matcher
5868 * @param[in, out] key
5869 * Flow matcher value.
5871 * Flow pattern to translate.
5872 * @param[in] prev_layer
5873 * The protocol layer indicated in previous item.
5875 * Item is inner pattern.
5878 flow_dv_translate_item_mpls(void *matcher, void *key,
5879 const struct rte_flow_item *item,
5880 uint64_t prev_layer,
5883 const uint32_t *in_mpls_m = item->mask;
5884 const uint32_t *in_mpls_v = item->spec;
5885 uint32_t *out_mpls_m = 0;
5886 uint32_t *out_mpls_v = 0;
5887 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5888 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5889 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5891 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5892 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5893 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5895 switch (prev_layer) {
5896 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5897 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5898 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5899 MLX5_UDP_PORT_MPLS);
5901 case MLX5_FLOW_LAYER_GRE:
5902 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5903 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5904 RTE_ETHER_TYPE_MPLS);
5907 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5908 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5915 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5916 switch (prev_layer) {
5917 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5919 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5920 outer_first_mpls_over_udp);
5922 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5923 outer_first_mpls_over_udp);
5925 case MLX5_FLOW_LAYER_GRE:
5927 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5928 outer_first_mpls_over_gre);
5930 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5931 outer_first_mpls_over_gre);
5934 /* Inner MPLS not over GRE is not supported. */
5937 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5941 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5947 if (out_mpls_m && out_mpls_v) {
5948 *out_mpls_m = *in_mpls_m;
5949 *out_mpls_v = *in_mpls_v & *in_mpls_m;
5954 * Add metadata register item to matcher
5956 * @param[in, out] matcher
5958 * @param[in, out] key
5959 * Flow matcher value.
5960 * @param[in] reg_type
5961 * Type of device metadata register
5968 flow_dv_match_meta_reg(void *matcher, void *key,
5969 enum modify_reg reg_type,
5970 uint32_t data, uint32_t mask)
5973 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5975 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5981 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5982 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5985 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5986 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5990 * The metadata register C0 field might be divided into
5991 * source vport index and META item value, we should set
5992 * this field according to specified mask, not as whole one.
5994 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
5996 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
5997 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6000 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6003 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6004 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6007 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6008 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6011 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6012 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6015 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6016 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6019 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6020 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6023 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6024 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6027 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6028 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6037 * Add MARK item to matcher
6040 * The device to configure through.
6041 * @param[in, out] matcher
6043 * @param[in, out] key
6044 * Flow matcher value.
6046 * Flow pattern to translate.
6049 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6050 void *matcher, void *key,
6051 const struct rte_flow_item *item)
6053 struct mlx5_priv *priv = dev->data->dev_private;
6054 const struct rte_flow_item_mark *mark;
6058 mark = item->mask ? (const void *)item->mask :
6059 &rte_flow_item_mark_mask;
6060 mask = mark->id & priv->sh->dv_mark_mask;
6061 mark = (const void *)item->spec;
6063 value = mark->id & priv->sh->dv_mark_mask & mask;
6065 enum modify_reg reg;
6067 /* Get the metadata register index for the mark. */
6068 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6070 if (reg == REG_C_0) {
6071 struct mlx5_priv *priv = dev->data->dev_private;
6072 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6073 uint32_t shl_c0 = rte_bsf32(msk_c0);
6079 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6084 * Add META item to matcher
6087 * The devich to configure through.
6088 * @param[in, out] matcher
6090 * @param[in, out] key
6091 * Flow matcher value.
6093 * Attributes of flow that includes this item.
6095 * Flow pattern to translate.
6098 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6099 void *matcher, void *key,
6100 const struct rte_flow_attr *attr,
6101 const struct rte_flow_item *item)
6103 const struct rte_flow_item_meta *meta_m;
6104 const struct rte_flow_item_meta *meta_v;
6106 meta_m = (const void *)item->mask;
6108 meta_m = &rte_flow_item_meta_mask;
6109 meta_v = (const void *)item->spec;
6111 enum modify_reg reg;
6112 uint32_t value = meta_v->data;
6113 uint32_t mask = meta_m->data;
6115 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6119 * In datapath code there is no endianness
6120 * coversions for perfromance reasons, all
6121 * pattern conversions are done in rte_flow.
6123 value = rte_cpu_to_be_32(value);
6124 mask = rte_cpu_to_be_32(mask);
6125 if (reg == REG_C_0) {
6126 struct mlx5_priv *priv = dev->data->dev_private;
6127 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6128 uint32_t shl_c0 = rte_bsf32(msk_c0);
6129 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6130 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6138 assert(!(~msk_c0 & mask));
6140 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6145 * Add vport metadata Reg C0 item to matcher
6147 * @param[in, out] matcher
6149 * @param[in, out] key
6150 * Flow matcher value.
6152 * Flow pattern to translate.
6155 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6156 uint32_t value, uint32_t mask)
6158 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6162 * Add tag item to matcher
6165 * The devich to configure through.
6166 * @param[in, out] matcher
6168 * @param[in, out] key
6169 * Flow matcher value.
6171 * Flow pattern to translate.
6174 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6175 void *matcher, void *key,
6176 const struct rte_flow_item *item)
6178 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6179 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6180 uint32_t mask, value;
6183 value = tag_v->data;
6184 mask = tag_m ? tag_m->data : UINT32_MAX;
6185 if (tag_v->id == REG_C_0) {
6186 struct mlx5_priv *priv = dev->data->dev_private;
6187 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6188 uint32_t shl_c0 = rte_bsf32(msk_c0);
6194 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6198 * Add TAG item to matcher
6201 * The devich to configure through.
6202 * @param[in, out] matcher
6204 * @param[in, out] key
6205 * Flow matcher value.
6207 * Flow pattern to translate.
6210 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6211 void *matcher, void *key,
6212 const struct rte_flow_item *item)
6214 const struct rte_flow_item_tag *tag_v = item->spec;
6215 const struct rte_flow_item_tag *tag_m = item->mask;
6216 enum modify_reg reg;
6219 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6220 /* Get the metadata register index for the tag. */
6221 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6223 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6227 * Add source vport match to the specified matcher.
6229 * @param[in, out] matcher
6231 * @param[in, out] key
6232 * Flow matcher value.
6234 * Source vport value to match
6239 flow_dv_translate_item_source_vport(void *matcher, void *key,
6240 int16_t port, uint16_t mask)
6242 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6243 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6245 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6246 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6250 * Translate port-id item to eswitch match on port-id.
6253 * The devich to configure through.
6254 * @param[in, out] matcher
6256 * @param[in, out] key
6257 * Flow matcher value.
6259 * Flow pattern to translate.
6262 * 0 on success, a negative errno value otherwise.
6265 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6266 void *key, const struct rte_flow_item *item)
6268 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6269 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6270 struct mlx5_priv *priv;
6273 mask = pid_m ? pid_m->id : 0xffff;
6274 id = pid_v ? pid_v->id : dev->data->port_id;
6275 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6278 /* Translate to vport field or to metadata, depending on mode. */
6279 if (priv->vport_meta_mask)
6280 flow_dv_translate_item_meta_vport(matcher, key,
6281 priv->vport_meta_tag,
6282 priv->vport_meta_mask);
6284 flow_dv_translate_item_source_vport(matcher, key,
6285 priv->vport_id, mask);
6290 * Add ICMP6 item to matcher and to the value.
6292 * @param[in, out] matcher
6294 * @param[in, out] key
6295 * Flow matcher value.
6297 * Flow pattern to translate.
6299 * Item is inner pattern.
6302 flow_dv_translate_item_icmp6(void *matcher, void *key,
6303 const struct rte_flow_item *item,
6306 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6307 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6310 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6312 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6314 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6316 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6318 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6320 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6322 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6323 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6327 icmp6_m = &rte_flow_item_icmp6_mask;
6328 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6329 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6330 icmp6_v->type & icmp6_m->type);
6331 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6332 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6333 icmp6_v->code & icmp6_m->code);
6337 * Add ICMP item to matcher and to the value.
6339 * @param[in, out] matcher
6341 * @param[in, out] key
6342 * Flow matcher value.
6344 * Flow pattern to translate.
6346 * Item is inner pattern.
6349 flow_dv_translate_item_icmp(void *matcher, void *key,
6350 const struct rte_flow_item *item,
6353 const struct rte_flow_item_icmp *icmp_m = item->mask;
6354 const struct rte_flow_item_icmp *icmp_v = item->spec;
6357 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6359 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6361 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6363 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6365 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6367 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6369 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6370 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6374 icmp_m = &rte_flow_item_icmp_mask;
6375 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6376 icmp_m->hdr.icmp_type);
6377 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6378 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6379 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6380 icmp_m->hdr.icmp_code);
6381 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6382 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6386 * Add GTP item to matcher and to the value.
6388 * @param[in, out] matcher
6390 * @param[in, out] key
6391 * Flow matcher value.
6393 * Flow pattern to translate.
6395 * Item is inner pattern.
6398 flow_dv_translate_item_gtp(void *matcher, void *key,
6399 const struct rte_flow_item *item, int inner)
6401 const struct rte_flow_item_gtp *gtp_m = item->mask;
6402 const struct rte_flow_item_gtp *gtp_v = item->spec;
6405 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6407 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6408 uint16_t dport = RTE_GTPU_UDP_PORT;
6411 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6413 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6415 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6417 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6419 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6420 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6421 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6426 gtp_m = &rte_flow_item_gtp_mask;
6427 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6428 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6429 gtp_v->msg_type & gtp_m->msg_type);
6430 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6431 rte_be_to_cpu_32(gtp_m->teid));
6432 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6433 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6436 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6438 #define HEADER_IS_ZERO(match_criteria, headers) \
6439 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6440 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6443 * Calculate flow matcher enable bitmap.
6445 * @param match_criteria
6446 * Pointer to flow matcher criteria.
6449 * Bitmap of enabled fields.
6452 flow_dv_matcher_enable(uint32_t *match_criteria)
6454 uint8_t match_criteria_enable;
6456 match_criteria_enable =
6457 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6458 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6459 match_criteria_enable |=
6460 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6461 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6462 match_criteria_enable |=
6463 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6464 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6465 match_criteria_enable |=
6466 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6467 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6468 match_criteria_enable |=
6469 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6470 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6471 return match_criteria_enable;
6478 * @param[in, out] dev
6479 * Pointer to rte_eth_dev structure.
6480 * @param[in] table_id
6483 * Direction of the table.
6484 * @param[in] transfer
6485 * E-Switch or NIC flow.
6487 * pointer to error structure.
6490 * Returns tables resource based on the index, NULL in case of failed.
6492 static struct mlx5_flow_tbl_resource *
6493 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6494 uint32_t table_id, uint8_t egress,
6496 struct rte_flow_error *error)
6498 struct mlx5_priv *priv = dev->data->dev_private;
6499 struct mlx5_ibv_shared *sh = priv->sh;
6500 struct mlx5_flow_tbl_resource *tbl;
6501 union mlx5_flow_tbl_key table_key = {
6503 .table_id = table_id,
6505 .domain = !!transfer,
6506 .direction = !!egress,
6509 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6511 struct mlx5_flow_tbl_data_entry *tbl_data;
6516 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6518 tbl = &tbl_data->tbl;
6519 rte_atomic32_inc(&tbl->refcnt);
6522 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6524 rte_flow_error_set(error, ENOMEM,
6525 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6527 "cannot allocate flow table data entry");
6530 tbl = &tbl_data->tbl;
6531 pos = &tbl_data->entry;
6533 domain = sh->fdb_domain;
6535 domain = sh->tx_domain;
6537 domain = sh->rx_domain;
6538 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6540 rte_flow_error_set(error, ENOMEM,
6541 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6542 NULL, "cannot create flow table object");
6547 * No multi-threads now, but still better to initialize the reference
6548 * count before insert it into the hash list.
6550 rte_atomic32_init(&tbl->refcnt);
6551 /* Jump action reference count is initialized here. */
6552 rte_atomic32_init(&tbl_data->jump.refcnt);
6553 pos->key = table_key.v64;
6554 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6556 rte_flow_error_set(error, -ret,
6557 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6558 "cannot insert flow table data entry");
6559 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6562 rte_atomic32_inc(&tbl->refcnt);
6567 * Release a flow table.
6570 * Pointer to rte_eth_dev structure.
6572 * Table resource to be released.
6575 * Returns 0 if table was released, else return 1;
6578 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6579 struct mlx5_flow_tbl_resource *tbl)
6581 struct mlx5_priv *priv = dev->data->dev_private;
6582 struct mlx5_ibv_shared *sh = priv->sh;
6583 struct mlx5_flow_tbl_data_entry *tbl_data =
6584 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6588 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6589 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6591 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6593 /* remove the entry from the hash list and free memory. */
6594 mlx5_hlist_remove(sh->flow_tbls, pos);
6602 * Register the flow matcher.
6604 * @param[in, out] dev
6605 * Pointer to rte_eth_dev structure.
6606 * @param[in, out] matcher
6607 * Pointer to flow matcher.
6608 * @param[in, out] key
6609 * Pointer to flow table key.
6610 * @parm[in, out] dev_flow
6611 * Pointer to the dev_flow.
6613 * pointer to error structure.
6616 * 0 on success otherwise -errno and errno is set.
6619 flow_dv_matcher_register(struct rte_eth_dev *dev,
6620 struct mlx5_flow_dv_matcher *matcher,
6621 union mlx5_flow_tbl_key *key,
6622 struct mlx5_flow *dev_flow,
6623 struct rte_flow_error *error)
6625 struct mlx5_priv *priv = dev->data->dev_private;
6626 struct mlx5_ibv_shared *sh = priv->sh;
6627 struct mlx5_flow_dv_matcher *cache_matcher;
6628 struct mlx5dv_flow_matcher_attr dv_attr = {
6629 .type = IBV_FLOW_ATTR_NORMAL,
6630 .match_mask = (void *)&matcher->mask,
6632 struct mlx5_flow_tbl_resource *tbl;
6633 struct mlx5_flow_tbl_data_entry *tbl_data;
6635 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6636 key->domain, error);
6638 return -rte_errno; /* No need to refill the error info */
6639 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6640 /* Lookup from cache. */
6641 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6642 if (matcher->crc == cache_matcher->crc &&
6643 matcher->priority == cache_matcher->priority &&
6644 !memcmp((const void *)matcher->mask.buf,
6645 (const void *)cache_matcher->mask.buf,
6646 cache_matcher->mask.size)) {
6648 "%s group %u priority %hd use %s "
6649 "matcher %p: refcnt %d++",
6650 key->domain ? "FDB" : "NIC", key->table_id,
6651 cache_matcher->priority,
6652 key->direction ? "tx" : "rx",
6653 (void *)cache_matcher,
6654 rte_atomic32_read(&cache_matcher->refcnt));
6655 rte_atomic32_inc(&cache_matcher->refcnt);
6656 dev_flow->dv.matcher = cache_matcher;
6657 /* old matcher should not make the table ref++. */
6658 flow_dv_tbl_resource_release(dev, tbl);
6662 /* Register new matcher. */
6663 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6664 if (!cache_matcher) {
6665 flow_dv_tbl_resource_release(dev, tbl);
6666 return rte_flow_error_set(error, ENOMEM,
6667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6668 "cannot allocate matcher memory");
6670 *cache_matcher = *matcher;
6671 dv_attr.match_criteria_enable =
6672 flow_dv_matcher_enable(cache_matcher->mask.buf);
6673 dv_attr.priority = matcher->priority;
6675 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6676 cache_matcher->matcher_object =
6677 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6678 if (!cache_matcher->matcher_object) {
6679 rte_free(cache_matcher);
6680 #ifdef HAVE_MLX5DV_DR
6681 flow_dv_tbl_resource_release(dev, tbl);
6683 return rte_flow_error_set(error, ENOMEM,
6684 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6685 NULL, "cannot create matcher");
6687 /* Save the table information */
6688 cache_matcher->tbl = tbl;
6689 rte_atomic32_init(&cache_matcher->refcnt);
6690 /* only matcher ref++, table ref++ already done above in get API. */
6691 rte_atomic32_inc(&cache_matcher->refcnt);
6692 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6693 dev_flow->dv.matcher = cache_matcher;
6694 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6695 key->domain ? "FDB" : "NIC", key->table_id,
6696 cache_matcher->priority,
6697 key->direction ? "tx" : "rx", (void *)cache_matcher,
6698 rte_atomic32_read(&cache_matcher->refcnt));
6703 * Find existing tag resource or create and register a new one.
6705 * @param dev[in, out]
6706 * Pointer to rte_eth_dev structure.
6707 * @param[in, out] tag_be24
6708 * Tag value in big endian then R-shift 8.
6709 * @parm[in, out] dev_flow
6710 * Pointer to the dev_flow.
6712 * pointer to error structure.
6715 * 0 on success otherwise -errno and errno is set.
6718 flow_dv_tag_resource_register
6719 (struct rte_eth_dev *dev,
6721 struct mlx5_flow *dev_flow,
6722 struct rte_flow_error *error)
6724 struct mlx5_priv *priv = dev->data->dev_private;
6725 struct mlx5_ibv_shared *sh = priv->sh;
6726 struct mlx5_flow_dv_tag_resource *cache_resource;
6727 struct mlx5_hlist_entry *entry;
6729 /* Lookup a matching resource from cache. */
6730 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6732 cache_resource = container_of
6733 (entry, struct mlx5_flow_dv_tag_resource, entry);
6734 rte_atomic32_inc(&cache_resource->refcnt);
6735 dev_flow->dv.tag_resource = cache_resource;
6736 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6737 (void *)cache_resource,
6738 rte_atomic32_read(&cache_resource->refcnt));
6741 /* Register new resource. */
6742 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6743 if (!cache_resource)
6744 return rte_flow_error_set(error, ENOMEM,
6745 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6746 "cannot allocate resource memory");
6747 cache_resource->entry.key = (uint64_t)tag_be24;
6748 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6749 if (!cache_resource->action) {
6750 rte_free(cache_resource);
6751 return rte_flow_error_set(error, ENOMEM,
6752 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6753 NULL, "cannot create action");
6755 rte_atomic32_init(&cache_resource->refcnt);
6756 rte_atomic32_inc(&cache_resource->refcnt);
6757 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6758 mlx5_glue->destroy_flow_action(cache_resource->action);
6759 rte_free(cache_resource);
6760 return rte_flow_error_set(error, EEXIST,
6761 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6762 NULL, "cannot insert tag");
6764 dev_flow->dv.tag_resource = cache_resource;
6765 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6766 (void *)cache_resource,
6767 rte_atomic32_read(&cache_resource->refcnt));
6775 * Pointer to Ethernet device.
6777 * Pointer to mlx5_flow.
6780 * 1 while a reference on it exists, 0 when freed.
6783 flow_dv_tag_release(struct rte_eth_dev *dev,
6784 struct mlx5_flow_dv_tag_resource *tag)
6786 struct mlx5_priv *priv = dev->data->dev_private;
6787 struct mlx5_ibv_shared *sh = priv->sh;
6790 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6791 dev->data->port_id, (void *)tag,
6792 rte_atomic32_read(&tag->refcnt));
6793 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6794 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6795 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6796 DRV_LOG(DEBUG, "port %u tag %p: removed",
6797 dev->data->port_id, (void *)tag);
6805 * Translate port ID action to vport.
6808 * Pointer to rte_eth_dev structure.
6810 * Pointer to the port ID action.
6811 * @param[out] dst_port_id
6812 * The target port ID.
6814 * Pointer to the error structure.
6817 * 0 on success, a negative errno value otherwise and rte_errno is set.
6820 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6821 const struct rte_flow_action *action,
6822 uint32_t *dst_port_id,
6823 struct rte_flow_error *error)
6826 struct mlx5_priv *priv;
6827 const struct rte_flow_action_port_id *conf =
6828 (const struct rte_flow_action_port_id *)action->conf;
6830 port = conf->original ? dev->data->port_id : conf->id;
6831 priv = mlx5_port_to_eswitch_info(port, false);
6833 return rte_flow_error_set(error, -rte_errno,
6834 RTE_FLOW_ERROR_TYPE_ACTION,
6836 "No eswitch info was found for port");
6837 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6839 * This parameter is transferred to
6840 * mlx5dv_dr_action_create_dest_ib_port().
6842 *dst_port_id = priv->ibv_port;
6845 * Legacy mode, no LAG configurations is supported.
6846 * This parameter is transferred to
6847 * mlx5dv_dr_action_create_dest_vport().
6849 *dst_port_id = priv->vport_id;
6855 * Add Tx queue matcher
6858 * Pointer to the dev struct.
6859 * @param[in, out] matcher
6861 * @param[in, out] key
6862 * Flow matcher value.
6864 * Flow pattern to translate.
6866 * Item is inner pattern.
6869 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6870 void *matcher, void *key,
6871 const struct rte_flow_item *item)
6873 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6874 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6876 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6878 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6879 struct mlx5_txq_ctrl *txq;
6883 queue_m = (const void *)item->mask;
6886 queue_v = (const void *)item->spec;
6889 txq = mlx5_txq_get(dev, queue_v->queue);
6892 queue = txq->obj->sq->id;
6893 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6894 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6895 queue & queue_m->queue);
6896 mlx5_txq_release(dev, queue_v->queue);
6900 * Set the hash fields according to the @p flow information.
6902 * @param[in] dev_flow
6903 * Pointer to the mlx5_flow.
6906 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
6908 struct rte_flow *flow = dev_flow->flow;
6909 uint64_t items = dev_flow->layers;
6911 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
6913 dev_flow->hash_fields = 0;
6914 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
6915 if (flow->rss.level >= 2) {
6916 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
6920 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
6921 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
6922 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
6923 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6924 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
6925 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6926 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
6928 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
6930 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
6931 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
6932 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
6933 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6934 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
6935 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6936 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
6938 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
6941 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
6942 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
6943 if (rss_types & ETH_RSS_UDP) {
6944 if (rss_types & ETH_RSS_L4_SRC_ONLY)
6945 dev_flow->hash_fields |=
6946 IBV_RX_HASH_SRC_PORT_UDP;
6947 else if (rss_types & ETH_RSS_L4_DST_ONLY)
6948 dev_flow->hash_fields |=
6949 IBV_RX_HASH_DST_PORT_UDP;
6951 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
6953 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
6954 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
6955 if (rss_types & ETH_RSS_TCP) {
6956 if (rss_types & ETH_RSS_L4_SRC_ONLY)
6957 dev_flow->hash_fields |=
6958 IBV_RX_HASH_SRC_PORT_TCP;
6959 else if (rss_types & ETH_RSS_L4_DST_ONLY)
6960 dev_flow->hash_fields |=
6961 IBV_RX_HASH_DST_PORT_TCP;
6963 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
6969 * Fill the flow with DV spec, lock free
6970 * (mutex should be acquired by caller).
6973 * Pointer to rte_eth_dev structure.
6974 * @param[in, out] dev_flow
6975 * Pointer to the sub flow.
6977 * Pointer to the flow attributes.
6979 * Pointer to the list of items.
6980 * @param[in] actions
6981 * Pointer to the list of actions.
6983 * Pointer to the error structure.
6986 * 0 on success, a negative errno value otherwise and rte_errno is set.
6989 __flow_dv_translate(struct rte_eth_dev *dev,
6990 struct mlx5_flow *dev_flow,
6991 const struct rte_flow_attr *attr,
6992 const struct rte_flow_item items[],
6993 const struct rte_flow_action actions[],
6994 struct rte_flow_error *error)
6996 struct mlx5_priv *priv = dev->data->dev_private;
6997 struct mlx5_dev_config *dev_conf = &priv->config;
6998 struct rte_flow *flow = dev_flow->flow;
6999 uint64_t item_flags = 0;
7000 uint64_t last_item = 0;
7001 uint64_t action_flags = 0;
7002 uint64_t priority = attr->priority;
7003 struct mlx5_flow_dv_matcher matcher = {
7005 .size = sizeof(matcher.mask.buf),
7009 bool actions_end = false;
7011 struct mlx5_flow_dv_modify_hdr_resource res;
7012 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7013 sizeof(struct mlx5_modification_cmd) *
7014 (MLX5_MAX_MODIFY_NUM + 1)];
7016 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7017 union flow_dv_attr flow_attr = { .attr = 0 };
7019 union mlx5_flow_tbl_key tbl_key;
7020 uint32_t modify_action_position = UINT32_MAX;
7021 void *match_mask = matcher.mask.buf;
7022 void *match_value = dev_flow->dv.value.buf;
7023 uint8_t next_protocol = 0xff;
7024 struct rte_vlan_hdr vlan = { 0 };
7028 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7029 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7030 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7034 dev_flow->group = table;
7036 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7037 if (priority == MLX5_FLOW_PRIO_RSVD)
7038 priority = dev_conf->flow_prio - 1;
7039 /* number of actions must be set to 0 in case of dirty stack. */
7040 mhdr_res->actions_num = 0;
7041 for (; !actions_end ; actions++) {
7042 const struct rte_flow_action_queue *queue;
7043 const struct rte_flow_action_rss *rss;
7044 const struct rte_flow_action *action = actions;
7045 const struct rte_flow_action_count *count = action->conf;
7046 const uint8_t *rss_key;
7047 const struct rte_flow_action_jump *jump_data;
7048 const struct rte_flow_action_meter *mtr;
7049 struct mlx5_flow_tbl_resource *tbl;
7050 uint32_t port_id = 0;
7051 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7052 int action_type = actions->type;
7053 const struct rte_flow_action *found_action = NULL;
7055 switch (action_type) {
7056 case RTE_FLOW_ACTION_TYPE_VOID:
7058 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7059 if (flow_dv_translate_action_port_id(dev, action,
7062 port_id_resource.port_id = port_id;
7063 if (flow_dv_port_id_action_resource_register
7064 (dev, &port_id_resource, dev_flow, error))
7066 dev_flow->dv.actions[actions_n++] =
7067 dev_flow->dv.port_id_action->action;
7068 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7070 case RTE_FLOW_ACTION_TYPE_FLAG:
7071 action_flags |= MLX5_FLOW_ACTION_FLAG;
7072 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7073 struct rte_flow_action_mark mark = {
7074 .id = MLX5_FLOW_MARK_DEFAULT,
7077 if (flow_dv_convert_action_mark(dev, &mark,
7081 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7084 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7085 if (!dev_flow->dv.tag_resource)
7086 if (flow_dv_tag_resource_register
7087 (dev, tag_be, dev_flow, error))
7089 dev_flow->dv.actions[actions_n++] =
7090 dev_flow->dv.tag_resource->action;
7092 case RTE_FLOW_ACTION_TYPE_MARK:
7093 action_flags |= MLX5_FLOW_ACTION_MARK;
7094 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7095 const struct rte_flow_action_mark *mark =
7096 (const struct rte_flow_action_mark *)
7099 if (flow_dv_convert_action_mark(dev, mark,
7103 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7107 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7108 /* Legacy (non-extensive) MARK action. */
7109 tag_be = mlx5_flow_mark_set
7110 (((const struct rte_flow_action_mark *)
7111 (actions->conf))->id);
7112 if (!dev_flow->dv.tag_resource)
7113 if (flow_dv_tag_resource_register
7114 (dev, tag_be, dev_flow, error))
7116 dev_flow->dv.actions[actions_n++] =
7117 dev_flow->dv.tag_resource->action;
7119 case RTE_FLOW_ACTION_TYPE_SET_META:
7120 if (flow_dv_convert_action_set_meta
7121 (dev, mhdr_res, attr,
7122 (const struct rte_flow_action_set_meta *)
7123 actions->conf, error))
7125 action_flags |= MLX5_FLOW_ACTION_SET_META;
7127 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7128 if (flow_dv_convert_action_set_tag
7130 (const struct rte_flow_action_set_tag *)
7131 actions->conf, error))
7133 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7135 case RTE_FLOW_ACTION_TYPE_DROP:
7136 action_flags |= MLX5_FLOW_ACTION_DROP;
7138 case RTE_FLOW_ACTION_TYPE_QUEUE:
7139 assert(flow->rss.queue);
7140 queue = actions->conf;
7141 flow->rss.queue_num = 1;
7142 (*flow->rss.queue)[0] = queue->index;
7143 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7145 case RTE_FLOW_ACTION_TYPE_RSS:
7146 assert(flow->rss.queue);
7147 rss = actions->conf;
7148 if (flow->rss.queue)
7149 memcpy((*flow->rss.queue), rss->queue,
7150 rss->queue_num * sizeof(uint16_t));
7151 flow->rss.queue_num = rss->queue_num;
7152 /* NULL RSS key indicates default RSS key. */
7153 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7154 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7156 * rss->level and rss.types should be set in advance
7157 * when expanding items for RSS.
7159 action_flags |= MLX5_FLOW_ACTION_RSS;
7161 case RTE_FLOW_ACTION_TYPE_COUNT:
7162 if (!dev_conf->devx) {
7163 rte_errno = ENOTSUP;
7166 flow->counter = flow_dv_counter_alloc(dev,
7170 if (flow->counter == NULL)
7172 dev_flow->dv.actions[actions_n++] =
7173 flow->counter->action;
7174 action_flags |= MLX5_FLOW_ACTION_COUNT;
7177 if (rte_errno == ENOTSUP)
7178 return rte_flow_error_set
7180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7182 "count action not supported");
7184 return rte_flow_error_set
7186 RTE_FLOW_ERROR_TYPE_ACTION,
7188 "cannot create counter"
7191 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7192 dev_flow->dv.actions[actions_n++] =
7193 priv->sh->pop_vlan_action;
7194 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7196 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7197 flow_dev_get_vlan_info_from_items(items, &vlan);
7198 vlan.eth_proto = rte_be_to_cpu_16
7199 ((((const struct rte_flow_action_of_push_vlan *)
7200 actions->conf)->ethertype));
7201 found_action = mlx5_flow_find_action
7203 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7205 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7206 found_action = mlx5_flow_find_action
7208 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7210 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7211 if (flow_dv_create_action_push_vlan
7212 (dev, attr, &vlan, dev_flow, error))
7214 dev_flow->dv.actions[actions_n++] =
7215 dev_flow->dv.push_vlan_res->action;
7216 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7218 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7219 /* of_vlan_push action handled this action */
7220 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7222 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7223 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7225 flow_dev_get_vlan_info_from_items(items, &vlan);
7226 mlx5_update_vlan_vid_pcp(actions, &vlan);
7227 /* If no VLAN push - this is a modify header action */
7228 if (flow_dv_convert_action_modify_vlan_vid
7229 (mhdr_res, actions, error))
7231 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7233 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7234 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7235 if (flow_dv_create_action_l2_encap(dev, actions,
7240 dev_flow->dv.actions[actions_n++] =
7241 dev_flow->dv.encap_decap->verbs_action;
7242 action_flags |= actions->type ==
7243 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
7244 MLX5_FLOW_ACTION_VXLAN_ENCAP :
7245 MLX5_FLOW_ACTION_NVGRE_ENCAP;
7247 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7248 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7249 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7253 dev_flow->dv.actions[actions_n++] =
7254 dev_flow->dv.encap_decap->verbs_action;
7255 action_flags |= actions->type ==
7256 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7257 MLX5_FLOW_ACTION_VXLAN_DECAP :
7258 MLX5_FLOW_ACTION_NVGRE_DECAP;
7260 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7261 /* Handle encap with preceding decap. */
7262 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
7263 if (flow_dv_create_action_raw_encap
7264 (dev, actions, dev_flow, attr, error))
7266 dev_flow->dv.actions[actions_n++] =
7267 dev_flow->dv.encap_decap->verbs_action;
7269 /* Handle encap without preceding decap. */
7270 if (flow_dv_create_action_l2_encap
7271 (dev, actions, dev_flow, attr->transfer,
7274 dev_flow->dv.actions[actions_n++] =
7275 dev_flow->dv.encap_decap->verbs_action;
7277 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
7279 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7280 /* Check if this decap is followed by encap. */
7281 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
7282 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
7285 /* Handle decap only if it isn't followed by encap. */
7286 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7287 if (flow_dv_create_action_l2_decap
7288 (dev, dev_flow, attr->transfer, error))
7290 dev_flow->dv.actions[actions_n++] =
7291 dev_flow->dv.encap_decap->verbs_action;
7293 /* If decap is followed by encap, handle it at encap. */
7294 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
7296 case RTE_FLOW_ACTION_TYPE_JUMP:
7297 jump_data = action->conf;
7298 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7299 jump_data->group, &table,
7303 tbl = flow_dv_tbl_resource_get(dev, table,
7305 attr->transfer, error);
7307 return rte_flow_error_set
7309 RTE_FLOW_ERROR_TYPE_ACTION,
7311 "cannot create jump action.");
7312 if (flow_dv_jump_tbl_resource_register
7313 (dev, tbl, dev_flow, error)) {
7314 flow_dv_tbl_resource_release(dev, tbl);
7315 return rte_flow_error_set
7317 RTE_FLOW_ERROR_TYPE_ACTION,
7319 "cannot create jump action.");
7321 dev_flow->dv.actions[actions_n++] =
7322 dev_flow->dv.jump->action;
7323 action_flags |= MLX5_FLOW_ACTION_JUMP;
7325 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7326 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7327 if (flow_dv_convert_action_modify_mac
7328 (mhdr_res, actions, error))
7330 action_flags |= actions->type ==
7331 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7332 MLX5_FLOW_ACTION_SET_MAC_SRC :
7333 MLX5_FLOW_ACTION_SET_MAC_DST;
7335 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7336 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7337 if (flow_dv_convert_action_modify_ipv4
7338 (mhdr_res, actions, error))
7340 action_flags |= actions->type ==
7341 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7342 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7343 MLX5_FLOW_ACTION_SET_IPV4_DST;
7345 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7346 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7347 if (flow_dv_convert_action_modify_ipv6
7348 (mhdr_res, actions, error))
7350 action_flags |= actions->type ==
7351 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7352 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7353 MLX5_FLOW_ACTION_SET_IPV6_DST;
7355 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7356 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7357 if (flow_dv_convert_action_modify_tp
7358 (mhdr_res, actions, items,
7361 action_flags |= actions->type ==
7362 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7363 MLX5_FLOW_ACTION_SET_TP_SRC :
7364 MLX5_FLOW_ACTION_SET_TP_DST;
7366 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7367 if (flow_dv_convert_action_modify_dec_ttl
7368 (mhdr_res, items, &flow_attr, error))
7370 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7372 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7373 if (flow_dv_convert_action_modify_ttl
7374 (mhdr_res, actions, items,
7377 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7379 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7380 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7381 if (flow_dv_convert_action_modify_tcp_seq
7382 (mhdr_res, actions, error))
7384 action_flags |= actions->type ==
7385 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7386 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7387 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7390 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7391 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7392 if (flow_dv_convert_action_modify_tcp_ack
7393 (mhdr_res, actions, error))
7395 action_flags |= actions->type ==
7396 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7397 MLX5_FLOW_ACTION_INC_TCP_ACK :
7398 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7400 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7401 if (flow_dv_convert_action_set_reg
7402 (mhdr_res, actions, error))
7404 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7406 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7407 if (flow_dv_convert_action_copy_mreg
7408 (dev, mhdr_res, actions, error))
7410 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7412 case RTE_FLOW_ACTION_TYPE_METER:
7413 mtr = actions->conf;
7415 flow->meter = mlx5_flow_meter_attach(priv,
7419 return rte_flow_error_set(error,
7421 RTE_FLOW_ERROR_TYPE_ACTION,
7424 "or invalid parameters");
7426 /* Set the meter action. */
7427 dev_flow->dv.actions[actions_n++] =
7428 flow->meter->mfts->meter_action;
7429 action_flags |= MLX5_FLOW_ACTION_METER;
7431 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7432 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7435 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7437 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7438 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7441 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7443 case RTE_FLOW_ACTION_TYPE_END:
7445 if (mhdr_res->actions_num) {
7446 /* create modify action if needed. */
7447 if (flow_dv_modify_hdr_resource_register
7448 (dev, mhdr_res, dev_flow, error))
7450 dev_flow->dv.actions[modify_action_position] =
7451 dev_flow->dv.modify_hdr->verbs_action;
7457 if (mhdr_res->actions_num &&
7458 modify_action_position == UINT32_MAX)
7459 modify_action_position = actions_n++;
7461 dev_flow->dv.actions_n = actions_n;
7462 dev_flow->actions = action_flags;
7463 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7464 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7465 int item_type = items->type;
7467 switch (item_type) {
7468 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7469 flow_dv_translate_item_port_id(dev, match_mask,
7470 match_value, items);
7471 last_item = MLX5_FLOW_ITEM_PORT_ID;
7473 case RTE_FLOW_ITEM_TYPE_ETH:
7474 flow_dv_translate_item_eth(match_mask, match_value,
7476 matcher.priority = MLX5_PRIORITY_MAP_L2;
7477 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7478 MLX5_FLOW_LAYER_OUTER_L2;
7480 case RTE_FLOW_ITEM_TYPE_VLAN:
7481 flow_dv_translate_item_vlan(dev_flow,
7482 match_mask, match_value,
7484 matcher.priority = MLX5_PRIORITY_MAP_L2;
7485 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7486 MLX5_FLOW_LAYER_INNER_VLAN) :
7487 (MLX5_FLOW_LAYER_OUTER_L2 |
7488 MLX5_FLOW_LAYER_OUTER_VLAN);
7490 case RTE_FLOW_ITEM_TYPE_IPV4:
7491 mlx5_flow_tunnel_ip_check(items, next_protocol,
7492 &item_flags, &tunnel);
7493 flow_dv_translate_item_ipv4(match_mask, match_value,
7496 matcher.priority = MLX5_PRIORITY_MAP_L3;
7497 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7498 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7499 if (items->mask != NULL &&
7500 ((const struct rte_flow_item_ipv4 *)
7501 items->mask)->hdr.next_proto_id) {
7503 ((const struct rte_flow_item_ipv4 *)
7504 (items->spec))->hdr.next_proto_id;
7506 ((const struct rte_flow_item_ipv4 *)
7507 (items->mask))->hdr.next_proto_id;
7509 /* Reset for inner layer. */
7510 next_protocol = 0xff;
7513 case RTE_FLOW_ITEM_TYPE_IPV6:
7514 mlx5_flow_tunnel_ip_check(items, next_protocol,
7515 &item_flags, &tunnel);
7516 flow_dv_translate_item_ipv6(match_mask, match_value,
7519 matcher.priority = MLX5_PRIORITY_MAP_L3;
7520 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7521 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7522 if (items->mask != NULL &&
7523 ((const struct rte_flow_item_ipv6 *)
7524 items->mask)->hdr.proto) {
7526 ((const struct rte_flow_item_ipv6 *)
7527 items->spec)->hdr.proto;
7529 ((const struct rte_flow_item_ipv6 *)
7530 items->mask)->hdr.proto;
7532 /* Reset for inner layer. */
7533 next_protocol = 0xff;
7536 case RTE_FLOW_ITEM_TYPE_TCP:
7537 flow_dv_translate_item_tcp(match_mask, match_value,
7539 matcher.priority = MLX5_PRIORITY_MAP_L4;
7540 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7541 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7543 case RTE_FLOW_ITEM_TYPE_UDP:
7544 flow_dv_translate_item_udp(match_mask, match_value,
7546 matcher.priority = MLX5_PRIORITY_MAP_L4;
7547 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7548 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7550 case RTE_FLOW_ITEM_TYPE_GRE:
7551 flow_dv_translate_item_gre(match_mask, match_value,
7553 last_item = MLX5_FLOW_LAYER_GRE;
7555 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7556 flow_dv_translate_item_gre_key(match_mask,
7557 match_value, items);
7558 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7560 case RTE_FLOW_ITEM_TYPE_NVGRE:
7561 flow_dv_translate_item_nvgre(match_mask, match_value,
7563 last_item = MLX5_FLOW_LAYER_GRE;
7565 case RTE_FLOW_ITEM_TYPE_VXLAN:
7566 flow_dv_translate_item_vxlan(match_mask, match_value,
7568 last_item = MLX5_FLOW_LAYER_VXLAN;
7570 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7571 flow_dv_translate_item_vxlan(match_mask, match_value,
7573 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7575 case RTE_FLOW_ITEM_TYPE_GENEVE:
7576 flow_dv_translate_item_geneve(match_mask, match_value,
7578 last_item = MLX5_FLOW_LAYER_GENEVE;
7580 case RTE_FLOW_ITEM_TYPE_MPLS:
7581 flow_dv_translate_item_mpls(match_mask, match_value,
7582 items, last_item, tunnel);
7583 last_item = MLX5_FLOW_LAYER_MPLS;
7585 case RTE_FLOW_ITEM_TYPE_MARK:
7586 flow_dv_translate_item_mark(dev, match_mask,
7587 match_value, items);
7588 last_item = MLX5_FLOW_ITEM_MARK;
7590 case RTE_FLOW_ITEM_TYPE_META:
7591 flow_dv_translate_item_meta(dev, match_mask,
7592 match_value, attr, items);
7593 last_item = MLX5_FLOW_ITEM_METADATA;
7595 case RTE_FLOW_ITEM_TYPE_ICMP:
7596 flow_dv_translate_item_icmp(match_mask, match_value,
7598 last_item = MLX5_FLOW_LAYER_ICMP;
7600 case RTE_FLOW_ITEM_TYPE_ICMP6:
7601 flow_dv_translate_item_icmp6(match_mask, match_value,
7603 last_item = MLX5_FLOW_LAYER_ICMP6;
7605 case RTE_FLOW_ITEM_TYPE_TAG:
7606 flow_dv_translate_item_tag(dev, match_mask,
7607 match_value, items);
7608 last_item = MLX5_FLOW_ITEM_TAG;
7610 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7611 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7612 match_value, items);
7613 last_item = MLX5_FLOW_ITEM_TAG;
7615 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7616 flow_dv_translate_item_tx_queue(dev, match_mask,
7619 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7621 case RTE_FLOW_ITEM_TYPE_GTP:
7622 flow_dv_translate_item_gtp(match_mask, match_value,
7624 last_item = MLX5_FLOW_LAYER_GTP;
7629 item_flags |= last_item;
7632 * In case of ingress traffic when E-Switch mode is enabled,
7633 * we have two cases where we need to set the source port manually.
7634 * The first one, is in case of Nic steering rule, and the second is
7635 * E-Switch rule where no port_id item was found. In both cases
7636 * the source port is set according the current port in use.
7638 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
7639 (priv->representor || priv->master)) {
7640 if (flow_dv_translate_item_port_id(dev, match_mask,
7644 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
7645 dev_flow->dv.value.buf));
7646 dev_flow->layers = item_flags;
7647 if (action_flags & MLX5_FLOW_ACTION_RSS)
7648 flow_dv_hashfields_set(dev_flow);
7649 /* Register matcher. */
7650 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7652 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7654 /* reserved field no needs to be set to 0 here. */
7655 tbl_key.domain = attr->transfer;
7656 tbl_key.direction = attr->egress;
7657 tbl_key.table_id = dev_flow->group;
7658 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7664 * Apply the flow to the NIC, lock free,
7665 * (mutex should be acquired by caller).
7668 * Pointer to the Ethernet device structure.
7669 * @param[in, out] flow
7670 * Pointer to flow structure.
7672 * Pointer to error structure.
7675 * 0 on success, a negative errno value otherwise and rte_errno is set.
7678 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7679 struct rte_flow_error *error)
7681 struct mlx5_flow_dv *dv;
7682 struct mlx5_flow *dev_flow;
7683 struct mlx5_priv *priv = dev->data->dev_private;
7687 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7690 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7691 if (dev_flow->transfer) {
7692 dv->actions[n++] = priv->sh->esw_drop_action;
7694 dv->hrxq = mlx5_hrxq_drop_new(dev);
7698 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7700 "cannot get drop hash queue");
7703 dv->actions[n++] = dv->hrxq->action;
7705 } else if (dev_flow->actions &
7706 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7707 struct mlx5_hrxq *hrxq;
7709 assert(flow->rss.queue);
7710 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7711 MLX5_RSS_HASH_KEY_LEN,
7712 dev_flow->hash_fields,
7714 flow->rss.queue_num);
7716 hrxq = mlx5_hrxq_new
7717 (dev, flow->rss.key,
7718 MLX5_RSS_HASH_KEY_LEN,
7719 dev_flow->hash_fields,
7721 flow->rss.queue_num,
7722 !!(dev_flow->layers &
7723 MLX5_FLOW_LAYER_TUNNEL));
7728 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7729 "cannot get hash queue");
7733 dv->actions[n++] = dv->hrxq->action;
7736 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7737 (void *)&dv->value, n,
7740 rte_flow_error_set(error, errno,
7741 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7743 "hardware refuses to create flow");
7746 if (priv->vmwa_context &&
7747 dev_flow->dv.vf_vlan.tag &&
7748 !dev_flow->dv.vf_vlan.created) {
7750 * The rule contains the VLAN pattern.
7751 * For VF we are going to create VLAN
7752 * interface to make hypervisor set correct
7753 * e-Switch vport context.
7755 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7760 err = rte_errno; /* Save rte_errno before cleanup. */
7761 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7762 struct mlx5_flow_dv *dv = &dev_flow->dv;
7764 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7765 mlx5_hrxq_drop_release(dev);
7767 mlx5_hrxq_release(dev, dv->hrxq);
7770 if (dev_flow->dv.vf_vlan.tag &&
7771 dev_flow->dv.vf_vlan.created)
7772 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7774 rte_errno = err; /* Restore rte_errno. */
7779 * Release the flow matcher.
7782 * Pointer to Ethernet device.
7784 * Pointer to mlx5_flow.
7787 * 1 while a reference on it exists, 0 when freed.
7790 flow_dv_matcher_release(struct rte_eth_dev *dev,
7791 struct mlx5_flow *flow)
7793 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7795 assert(matcher->matcher_object);
7796 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7797 dev->data->port_id, (void *)matcher,
7798 rte_atomic32_read(&matcher->refcnt));
7799 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7800 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7801 (matcher->matcher_object));
7802 LIST_REMOVE(matcher, next);
7803 /* table ref-- in release interface. */
7804 flow_dv_tbl_resource_release(dev, matcher->tbl);
7806 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7807 dev->data->port_id, (void *)matcher);
7814 * Release an encap/decap resource.
7817 * Pointer to mlx5_flow.
7820 * 1 while a reference on it exists, 0 when freed.
7823 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7825 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7826 flow->dv.encap_decap;
7828 assert(cache_resource->verbs_action);
7829 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7830 (void *)cache_resource,
7831 rte_atomic32_read(&cache_resource->refcnt));
7832 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7833 claim_zero(mlx5_glue->destroy_flow_action
7834 (cache_resource->verbs_action));
7835 LIST_REMOVE(cache_resource, next);
7836 rte_free(cache_resource);
7837 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7838 (void *)cache_resource);
7845 * Release an jump to table action resource.
7848 * Pointer to Ethernet device.
7850 * Pointer to mlx5_flow.
7853 * 1 while a reference on it exists, 0 when freed.
7856 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7857 struct mlx5_flow *flow)
7859 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7860 struct mlx5_flow_tbl_data_entry *tbl_data =
7861 container_of(cache_resource,
7862 struct mlx5_flow_tbl_data_entry, jump);
7864 assert(cache_resource->action);
7865 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7866 (void *)cache_resource,
7867 rte_atomic32_read(&cache_resource->refcnt));
7868 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7869 claim_zero(mlx5_glue->destroy_flow_action
7870 (cache_resource->action));
7871 /* jump action memory free is inside the table release. */
7872 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7873 DRV_LOG(DEBUG, "jump table resource %p: removed",
7874 (void *)cache_resource);
7881 * Release a modify-header resource.
7884 * Pointer to mlx5_flow.
7887 * 1 while a reference on it exists, 0 when freed.
7890 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7892 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7893 flow->dv.modify_hdr;
7895 assert(cache_resource->verbs_action);
7896 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7897 (void *)cache_resource,
7898 rte_atomic32_read(&cache_resource->refcnt));
7899 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7900 claim_zero(mlx5_glue->destroy_flow_action
7901 (cache_resource->verbs_action));
7902 LIST_REMOVE(cache_resource, next);
7903 rte_free(cache_resource);
7904 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7905 (void *)cache_resource);
7912 * Release port ID action resource.
7915 * Pointer to mlx5_flow.
7918 * 1 while a reference on it exists, 0 when freed.
7921 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
7923 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
7924 flow->dv.port_id_action;
7926 assert(cache_resource->action);
7927 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
7928 (void *)cache_resource,
7929 rte_atomic32_read(&cache_resource->refcnt));
7930 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7931 claim_zero(mlx5_glue->destroy_flow_action
7932 (cache_resource->action));
7933 LIST_REMOVE(cache_resource, next);
7934 rte_free(cache_resource);
7935 DRV_LOG(DEBUG, "port id action resource %p: removed",
7936 (void *)cache_resource);
7943 * Release push vlan action resource.
7946 * Pointer to mlx5_flow.
7949 * 1 while a reference on it exists, 0 when freed.
7952 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
7954 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
7955 flow->dv.push_vlan_res;
7957 assert(cache_resource->action);
7958 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
7959 (void *)cache_resource,
7960 rte_atomic32_read(&cache_resource->refcnt));
7961 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7962 claim_zero(mlx5_glue->destroy_flow_action
7963 (cache_resource->action));
7964 LIST_REMOVE(cache_resource, next);
7965 rte_free(cache_resource);
7966 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
7967 (void *)cache_resource);
7974 * Remove the flow from the NIC but keeps it in memory.
7975 * Lock free, (mutex should be acquired by caller).
7978 * Pointer to Ethernet device.
7979 * @param[in, out] flow
7980 * Pointer to flow structure.
7983 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7985 struct mlx5_flow_dv *dv;
7986 struct mlx5_flow *dev_flow;
7990 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7993 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
7997 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7998 mlx5_hrxq_drop_release(dev);
8000 mlx5_hrxq_release(dev, dv->hrxq);
8003 if (dev_flow->dv.vf_vlan.tag &&
8004 dev_flow->dv.vf_vlan.created)
8005 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8010 * Remove the flow from the NIC and the memory.
8011 * Lock free, (mutex should be acquired by caller).
8014 * Pointer to the Ethernet device structure.
8015 * @param[in, out] flow
8016 * Pointer to flow structure.
8019 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8021 struct mlx5_flow *dev_flow;
8025 __flow_dv_remove(dev, flow);
8026 if (flow->counter) {
8027 flow_dv_counter_release(dev, flow->counter);
8028 flow->counter = NULL;
8031 mlx5_flow_meter_detach(flow->meter);
8034 while (!LIST_EMPTY(&flow->dev_flows)) {
8035 dev_flow = LIST_FIRST(&flow->dev_flows);
8036 LIST_REMOVE(dev_flow, next);
8037 if (dev_flow->dv.matcher)
8038 flow_dv_matcher_release(dev, dev_flow);
8039 if (dev_flow->dv.encap_decap)
8040 flow_dv_encap_decap_resource_release(dev_flow);
8041 if (dev_flow->dv.modify_hdr)
8042 flow_dv_modify_hdr_resource_release(dev_flow);
8043 if (dev_flow->dv.jump)
8044 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8045 if (dev_flow->dv.port_id_action)
8046 flow_dv_port_id_action_resource_release(dev_flow);
8047 if (dev_flow->dv.push_vlan_res)
8048 flow_dv_push_vlan_action_resource_release(dev_flow);
8049 if (dev_flow->dv.tag_resource)
8050 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8056 * Query a dv flow rule for its statistics via devx.
8059 * Pointer to Ethernet device.
8061 * Pointer to the sub flow.
8063 * data retrieved by the query.
8065 * Perform verbose error reporting if not NULL.
8068 * 0 on success, a negative errno value otherwise and rte_errno is set.
8071 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8072 void *data, struct rte_flow_error *error)
8074 struct mlx5_priv *priv = dev->data->dev_private;
8075 struct rte_flow_query_count *qc = data;
8077 if (!priv->config.devx)
8078 return rte_flow_error_set(error, ENOTSUP,
8079 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8081 "counters are not supported");
8082 if (flow->counter) {
8083 uint64_t pkts, bytes;
8084 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8088 return rte_flow_error_set(error, -err,
8089 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8090 NULL, "cannot read counters");
8093 qc->hits = pkts - flow->counter->hits;
8094 qc->bytes = bytes - flow->counter->bytes;
8096 flow->counter->hits = pkts;
8097 flow->counter->bytes = bytes;
8101 return rte_flow_error_set(error, EINVAL,
8102 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8104 "counters are not available");
8110 * @see rte_flow_query()
8114 flow_dv_query(struct rte_eth_dev *dev,
8115 struct rte_flow *flow __rte_unused,
8116 const struct rte_flow_action *actions __rte_unused,
8117 void *data __rte_unused,
8118 struct rte_flow_error *error __rte_unused)
8122 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8123 switch (actions->type) {
8124 case RTE_FLOW_ACTION_TYPE_VOID:
8126 case RTE_FLOW_ACTION_TYPE_COUNT:
8127 ret = flow_dv_query_count(dev, flow, data, error);
8130 return rte_flow_error_set(error, ENOTSUP,
8131 RTE_FLOW_ERROR_TYPE_ACTION,
8133 "action not supported");
8140 * Destroy the meter table set.
8141 * Lock free, (mutex should be acquired by caller).
8144 * Pointer to Ethernet device.
8146 * Pointer to the meter table set.
8152 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8153 struct mlx5_meter_domains_infos *tbl)
8155 struct mlx5_priv *priv = dev->data->dev_private;
8156 struct mlx5_meter_domains_infos *mtd =
8157 (struct mlx5_meter_domains_infos *)tbl;
8159 if (!mtd || !priv->config.dv_flow_en)
8161 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8162 claim_zero(mlx5_glue->dv_destroy_flow
8163 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8164 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8165 claim_zero(mlx5_glue->dv_destroy_flow
8166 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8167 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8168 claim_zero(mlx5_glue->dv_destroy_flow
8169 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8170 if (mtd->egress.color_matcher)
8171 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8172 (mtd->egress.color_matcher));
8173 if (mtd->egress.any_matcher)
8174 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8175 (mtd->egress.any_matcher));
8176 if (mtd->egress.tbl)
8177 claim_zero(flow_dv_tbl_resource_release(dev,
8179 if (mtd->ingress.color_matcher)
8180 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8181 (mtd->ingress.color_matcher));
8182 if (mtd->ingress.any_matcher)
8183 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8184 (mtd->ingress.any_matcher));
8185 if (mtd->ingress.tbl)
8186 claim_zero(flow_dv_tbl_resource_release(dev,
8188 if (mtd->transfer.color_matcher)
8189 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8190 (mtd->transfer.color_matcher));
8191 if (mtd->transfer.any_matcher)
8192 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8193 (mtd->transfer.any_matcher));
8194 if (mtd->transfer.tbl)
8195 claim_zero(flow_dv_tbl_resource_release(dev,
8196 mtd->transfer.tbl));
8198 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8203 /* Number of meter flow actions, count and jump or count and drop. */
8204 #define METER_ACTIONS 2
8207 * Create specify domain meter table and suffix table.
8210 * Pointer to Ethernet device.
8211 * @param[in,out] mtb
8212 * Pointer to DV meter table set.
8215 * @param[in] transfer
8217 * @param[in] color_reg_c_idx
8218 * Reg C index for color match.
8221 * 0 on success, -1 otherwise and rte_errno is set.
8224 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8225 struct mlx5_meter_domains_infos *mtb,
8226 uint8_t egress, uint8_t transfer,
8227 uint32_t color_reg_c_idx)
8229 struct mlx5_priv *priv = dev->data->dev_private;
8230 struct mlx5_ibv_shared *sh = priv->sh;
8231 struct mlx5_flow_dv_match_params mask = {
8232 .size = sizeof(mask.buf),
8234 struct mlx5_flow_dv_match_params value = {
8235 .size = sizeof(value.buf),
8237 struct mlx5dv_flow_matcher_attr dv_attr = {
8238 .type = IBV_FLOW_ATTR_NORMAL,
8240 .match_criteria_enable = 0,
8241 .match_mask = (void *)&mask,
8243 void *actions[METER_ACTIONS];
8244 struct mlx5_flow_tbl_resource **sfx_tbl;
8245 struct mlx5_meter_domain_info *dtb;
8246 struct rte_flow_error error;
8250 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8251 dtb = &mtb->transfer;
8252 } else if (egress) {
8253 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8256 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8257 dtb = &mtb->ingress;
8259 /* If the suffix table in missing, create it. */
8261 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8262 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8263 egress, transfer, &error);
8265 DRV_LOG(ERR, "Failed to create meter suffix table.");
8269 /* Create the meter table with METER level. */
8270 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8271 egress, transfer, &error);
8273 DRV_LOG(ERR, "Failed to create meter policer table.");
8276 /* Create matchers, Any and Color. */
8277 dv_attr.priority = 3;
8278 dv_attr.match_criteria_enable = 0;
8279 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8282 if (!dtb->any_matcher) {
8283 DRV_LOG(ERR, "Failed to create meter"
8284 " policer default matcher.");
8287 dv_attr.priority = 0;
8288 dv_attr.match_criteria_enable =
8289 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8290 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8291 rte_col_2_mlx5_col(RTE_COLORS), UINT32_MAX);
8292 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8295 if (!dtb->color_matcher) {
8296 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8299 if (mtb->count_actns[RTE_MTR_DROPPED])
8300 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8301 actions[i++] = mtb->drop_actn;
8302 /* Default rule: lowest priority, match any, actions: drop. */
8303 dtb->policer_rules[RTE_MTR_DROPPED] =
8304 mlx5_glue->dv_create_flow(dtb->any_matcher,
8305 (void *)&value, i, actions);
8306 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8307 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8316 * Create the needed meter and suffix tables.
8317 * Lock free, (mutex should be acquired by caller).
8320 * Pointer to Ethernet device.
8322 * Pointer to the flow meter.
8325 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8327 static struct mlx5_meter_domains_infos *
8328 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8329 const struct mlx5_flow_meter *fm)
8331 struct mlx5_priv *priv = dev->data->dev_private;
8332 struct mlx5_meter_domains_infos *mtb;
8336 if (!priv->mtr_en) {
8337 rte_errno = ENOTSUP;
8340 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8342 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8345 /* Create meter count actions */
8346 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8347 if (!fm->policer_stats.cnt[i])
8349 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8351 /* Create drop action. */
8352 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8353 if (!mtb->drop_actn) {
8354 DRV_LOG(ERR, "Failed to create drop action.");
8357 /* Egress meter table. */
8358 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8360 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8363 /* Ingress meter table. */
8364 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8366 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8369 /* FDB meter table. */
8370 if (priv->config.dv_esw_en) {
8371 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8372 priv->mtr_color_reg);
8374 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8380 flow_dv_destroy_mtr_tbl(dev, mtb);
8385 * Destroy domain policer rule.
8388 * Pointer to domain table.
8391 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8395 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8396 if (dt->policer_rules[i]) {
8397 claim_zero(mlx5_glue->dv_destroy_flow
8398 (dt->policer_rules[i]));
8399 dt->policer_rules[i] = NULL;
8402 if (dt->jump_actn) {
8403 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8404 dt->jump_actn = NULL;
8409 * Destroy policer rules.
8412 * Pointer to Ethernet device.
8414 * Pointer to flow meter structure.
8416 * Pointer to flow attributes.
8422 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8423 const struct mlx5_flow_meter *fm,
8424 const struct rte_flow_attr *attr)
8426 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8431 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8433 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8435 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8440 * Create specify domain meter policer rule.
8443 * Pointer to flow meter structure.
8445 * Pointer to DV meter table set.
8447 * Pointer to suffix table.
8448 * @param[in] mtr_reg_c
8449 * Color match REG_C.
8452 * 0 on success, -1 otherwise.
8455 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8456 struct mlx5_meter_domain_info *dtb,
8457 struct mlx5_flow_tbl_resource *sfx_tb,
8460 struct mlx5_flow_dv_match_params matcher = {
8461 .size = sizeof(matcher.buf),
8463 struct mlx5_flow_dv_match_params value = {
8464 .size = sizeof(value.buf),
8466 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8467 void *actions[METER_ACTIONS];
8470 /* Create jump action. */
8473 if (!dtb->jump_actn)
8475 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8477 if (!dtb->jump_actn) {
8478 DRV_LOG(ERR, "Failed to create policer jump action.");
8481 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8484 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8485 rte_col_2_mlx5_col(i), UINT32_MAX);
8486 if (mtb->count_actns[i])
8487 actions[j++] = mtb->count_actns[i];
8488 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8489 actions[j++] = mtb->drop_actn;
8491 actions[j++] = dtb->jump_actn;
8492 dtb->policer_rules[i] =
8493 mlx5_glue->dv_create_flow(dtb->color_matcher,
8496 if (!dtb->policer_rules[i]) {
8497 DRV_LOG(ERR, "Failed to create policer rule.");
8508 * Create policer rules.
8511 * Pointer to Ethernet device.
8513 * Pointer to flow meter structure.
8515 * Pointer to flow attributes.
8518 * 0 on success, -1 otherwise.
8521 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8522 struct mlx5_flow_meter *fm,
8523 const struct rte_flow_attr *attr)
8525 struct mlx5_priv *priv = dev->data->dev_private;
8526 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8530 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8531 priv->sh->tx_mtr_sfx_tbl,
8532 priv->mtr_color_reg);
8534 DRV_LOG(ERR, "Failed to create egress policer.");
8538 if (attr->ingress) {
8539 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8540 priv->sh->rx_mtr_sfx_tbl,
8541 priv->mtr_color_reg);
8543 DRV_LOG(ERR, "Failed to create ingress policer.");
8547 if (attr->transfer) {
8548 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8549 priv->sh->fdb_mtr_sfx_tbl,
8550 priv->mtr_color_reg);
8552 DRV_LOG(ERR, "Failed to create transfer policer.");
8558 flow_dv_destroy_policer_rules(dev, fm, attr);
8563 * Query a devx counter.
8566 * Pointer to the Ethernet device structure.
8568 * Pointer to the flow counter.
8570 * Set to clear the counter statistics.
8572 * The statistics value of packets.
8574 * The statistics value of bytes.
8577 * 0 on success, otherwise return -1.
8580 flow_dv_counter_query(struct rte_eth_dev *dev,
8581 struct mlx5_flow_counter *cnt, bool clear,
8582 uint64_t *pkts, uint64_t *bytes)
8584 struct mlx5_priv *priv = dev->data->dev_private;
8585 uint64_t inn_pkts, inn_bytes;
8588 if (!priv->config.devx)
8590 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8593 *pkts = inn_pkts - cnt->hits;
8594 *bytes = inn_bytes - cnt->bytes;
8596 cnt->hits = inn_pkts;
8597 cnt->bytes = inn_bytes;
8603 * Mutex-protected thunk to lock-free __flow_dv_translate().
8606 flow_dv_translate(struct rte_eth_dev *dev,
8607 struct mlx5_flow *dev_flow,
8608 const struct rte_flow_attr *attr,
8609 const struct rte_flow_item items[],
8610 const struct rte_flow_action actions[],
8611 struct rte_flow_error *error)
8615 flow_dv_shared_lock(dev);
8616 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8617 flow_dv_shared_unlock(dev);
8622 * Mutex-protected thunk to lock-free __flow_dv_apply().
8625 flow_dv_apply(struct rte_eth_dev *dev,
8626 struct rte_flow *flow,
8627 struct rte_flow_error *error)
8631 flow_dv_shared_lock(dev);
8632 ret = __flow_dv_apply(dev, flow, error);
8633 flow_dv_shared_unlock(dev);
8638 * Mutex-protected thunk to lock-free __flow_dv_remove().
8641 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8643 flow_dv_shared_lock(dev);
8644 __flow_dv_remove(dev, flow);
8645 flow_dv_shared_unlock(dev);
8649 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8652 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8654 flow_dv_shared_lock(dev);
8655 __flow_dv_destroy(dev, flow);
8656 flow_dv_shared_unlock(dev);
8660 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8662 static struct mlx5_flow_counter *
8663 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8665 struct mlx5_flow_counter *cnt;
8667 flow_dv_shared_lock(dev);
8668 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8669 flow_dv_shared_unlock(dev);
8674 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8677 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8679 flow_dv_shared_lock(dev);
8680 flow_dv_counter_release(dev, cnt);
8681 flow_dv_shared_unlock(dev);
8684 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8685 .validate = flow_dv_validate,
8686 .prepare = flow_dv_prepare,
8687 .translate = flow_dv_translate,
8688 .apply = flow_dv_apply,
8689 .remove = flow_dv_remove,
8690 .destroy = flow_dv_destroy,
8691 .query = flow_dv_query,
8692 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8693 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8694 .create_policer_rules = flow_dv_create_policer_rules,
8695 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8696 .counter_alloc = flow_dv_counter_allocate,
8697 .counter_free = flow_dv_counter_free,
8698 .counter_query = flow_dv_counter_query,
8701 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */