1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
31 #include "mlx5_defs.h"
32 #include "mlx5_glue.h"
33 #include "mlx5_flow.h"
35 #include "mlx5_rxtx.h"
37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
43 #ifndef HAVE_MLX5DV_DR_ESWITCH
44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
49 #ifndef HAVE_MLX5DV_DR
50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
66 * Initialize flow attributes structure according to flow items' types.
69 * Pointer to item specification.
71 * Pointer to flow attributes structure.
74 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
76 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
78 case RTE_FLOW_ITEM_TYPE_IPV4:
81 case RTE_FLOW_ITEM_TYPE_IPV6:
84 case RTE_FLOW_ITEM_TYPE_UDP:
87 case RTE_FLOW_ITEM_TYPE_TCP:
97 struct field_modify_info {
98 uint32_t size; /* Size of field in protocol header, in bytes. */
99 uint32_t offset; /* Offset of field in protocol header, in bytes. */
100 enum mlx5_modification_field id;
103 struct field_modify_info modify_eth[] = {
104 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
105 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
106 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
107 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
111 struct field_modify_info modify_ipv4[] = {
112 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
113 {4, 12, MLX5_MODI_OUT_SIPV4},
114 {4, 16, MLX5_MODI_OUT_DIPV4},
118 struct field_modify_info modify_ipv6[] = {
119 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
120 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
121 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
122 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
123 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
124 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
125 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
126 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
127 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
131 struct field_modify_info modify_udp[] = {
132 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
133 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
137 struct field_modify_info modify_tcp[] = {
138 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
139 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
140 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
141 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
146 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item, uint64_t *flags)
148 uint8_t next_protocol = 0xFF;
150 if (item->mask != NULL) {
151 switch (item->type) {
152 case RTE_FLOW_ITEM_TYPE_IPV4:
154 ((const struct rte_flow_item_ipv4 *)
155 (item->spec))->hdr.next_proto_id;
157 ((const struct rte_flow_item_ipv4 *)
158 (item->mask))->hdr.next_proto_id;
160 case RTE_FLOW_ITEM_TYPE_IPV6:
162 ((const struct rte_flow_item_ipv6 *)
163 (item->spec))->hdr.proto;
165 ((const struct rte_flow_item_ipv6 *)
166 (item->mask))->hdr.proto;
172 if (next_protocol == IPPROTO_IPIP)
173 *flags |= MLX5_FLOW_LAYER_IPIP;
174 if (next_protocol == IPPROTO_IPV6)
175 *flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
179 * Acquire the synchronizing object to protect multithreaded access
180 * to shared dv context. Lock occurs only if context is actually
181 * shared, i.e. we have multiport IB device and representors are
185 * Pointer to the rte_eth_dev structure.
188 flow_d_shared_lock(struct rte_eth_dev *dev)
190 struct mlx5_priv *priv = dev->data->dev_private;
191 struct mlx5_ibv_shared *sh = priv->sh;
193 if (sh->dv_refcnt > 1) {
196 ret = pthread_mutex_lock(&sh->dv_mutex);
203 flow_d_shared_unlock(struct rte_eth_dev *dev)
205 struct mlx5_priv *priv = dev->data->dev_private;
206 struct mlx5_ibv_shared *sh = priv->sh;
208 if (sh->dv_refcnt > 1) {
211 ret = pthread_mutex_unlock(&sh->dv_mutex);
218 * Convert modify-header action to DV specification.
221 * Pointer to item specification.
223 * Pointer to field modification information.
224 * @param[in,out] resource
225 * Pointer to the modify-header resource.
227 * Type of modification.
229 * Pointer to the error structure.
232 * 0 on success, a negative errno value otherwise and rte_errno is set.
235 flow_dv_convert_modify_action(struct rte_flow_item *item,
236 struct field_modify_info *field,
237 struct mlx5_flow_dv_modify_hdr_resource *resource,
239 struct rte_flow_error *error)
241 uint32_t i = resource->actions_num;
242 struct mlx5_modification_cmd *actions = resource->actions;
243 const uint8_t *spec = item->spec;
244 const uint8_t *mask = item->mask;
247 while (field->size) {
249 /* Generate modify command for each mask segment. */
250 memcpy(&set, &mask[field->offset], field->size);
252 if (i >= MLX5_MODIFY_NUM)
253 return rte_flow_error_set(error, EINVAL,
254 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
255 "too many items to modify");
256 actions[i].action_type = type;
257 actions[i].field = field->id;
258 actions[i].length = field->size ==
259 4 ? 0 : field->size * 8;
260 rte_memcpy(&actions[i].data[4 - field->size],
261 &spec[field->offset], field->size);
262 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
265 if (resource->actions_num != i)
266 resource->actions_num = i;
269 if (!resource->actions_num)
270 return rte_flow_error_set(error, EINVAL,
271 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
272 "invalid modification flow item");
277 * Convert modify-header set IPv4 address action to DV specification.
279 * @param[in,out] resource
280 * Pointer to the modify-header resource.
282 * Pointer to action specification.
284 * Pointer to the error structure.
287 * 0 on success, a negative errno value otherwise and rte_errno is set.
290 flow_dv_convert_action_modify_ipv4
291 (struct mlx5_flow_dv_modify_hdr_resource *resource,
292 const struct rte_flow_action *action,
293 struct rte_flow_error *error)
295 const struct rte_flow_action_set_ipv4 *conf =
296 (const struct rte_flow_action_set_ipv4 *)(action->conf);
297 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
298 struct rte_flow_item_ipv4 ipv4;
299 struct rte_flow_item_ipv4 ipv4_mask;
301 memset(&ipv4, 0, sizeof(ipv4));
302 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
303 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
304 ipv4.hdr.src_addr = conf->ipv4_addr;
305 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
307 ipv4.hdr.dst_addr = conf->ipv4_addr;
308 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
311 item.mask = &ipv4_mask;
312 return flow_dv_convert_modify_action(&item, modify_ipv4, resource,
313 MLX5_MODIFICATION_TYPE_SET, error);
317 * Convert modify-header set IPv6 address action to DV specification.
319 * @param[in,out] resource
320 * Pointer to the modify-header resource.
322 * Pointer to action specification.
324 * Pointer to the error structure.
327 * 0 on success, a negative errno value otherwise and rte_errno is set.
330 flow_dv_convert_action_modify_ipv6
331 (struct mlx5_flow_dv_modify_hdr_resource *resource,
332 const struct rte_flow_action *action,
333 struct rte_flow_error *error)
335 const struct rte_flow_action_set_ipv6 *conf =
336 (const struct rte_flow_action_set_ipv6 *)(action->conf);
337 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
338 struct rte_flow_item_ipv6 ipv6;
339 struct rte_flow_item_ipv6 ipv6_mask;
341 memset(&ipv6, 0, sizeof(ipv6));
342 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
343 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
344 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
345 sizeof(ipv6.hdr.src_addr));
346 memcpy(&ipv6_mask.hdr.src_addr,
347 &rte_flow_item_ipv6_mask.hdr.src_addr,
348 sizeof(ipv6.hdr.src_addr));
350 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
351 sizeof(ipv6.hdr.dst_addr));
352 memcpy(&ipv6_mask.hdr.dst_addr,
353 &rte_flow_item_ipv6_mask.hdr.dst_addr,
354 sizeof(ipv6.hdr.dst_addr));
357 item.mask = &ipv6_mask;
358 return flow_dv_convert_modify_action(&item, modify_ipv6, resource,
359 MLX5_MODIFICATION_TYPE_SET, error);
363 * Convert modify-header set MAC address action to DV specification.
365 * @param[in,out] resource
366 * Pointer to the modify-header resource.
368 * Pointer to action specification.
370 * Pointer to the error structure.
373 * 0 on success, a negative errno value otherwise and rte_errno is set.
376 flow_dv_convert_action_modify_mac
377 (struct mlx5_flow_dv_modify_hdr_resource *resource,
378 const struct rte_flow_action *action,
379 struct rte_flow_error *error)
381 const struct rte_flow_action_set_mac *conf =
382 (const struct rte_flow_action_set_mac *)(action->conf);
383 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
384 struct rte_flow_item_eth eth;
385 struct rte_flow_item_eth eth_mask;
387 memset(ð, 0, sizeof(eth));
388 memset(ð_mask, 0, sizeof(eth_mask));
389 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
390 memcpy(ð.src.addr_bytes, &conf->mac_addr,
391 sizeof(eth.src.addr_bytes));
392 memcpy(ð_mask.src.addr_bytes,
393 &rte_flow_item_eth_mask.src.addr_bytes,
394 sizeof(eth_mask.src.addr_bytes));
396 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
397 sizeof(eth.dst.addr_bytes));
398 memcpy(ð_mask.dst.addr_bytes,
399 &rte_flow_item_eth_mask.dst.addr_bytes,
400 sizeof(eth_mask.dst.addr_bytes));
403 item.mask = ð_mask;
404 return flow_dv_convert_modify_action(&item, modify_eth, resource,
405 MLX5_MODIFICATION_TYPE_SET, error);
409 * Convert modify-header set TP action to DV specification.
411 * @param[in,out] resource
412 * Pointer to the modify-header resource.
414 * Pointer to action specification.
416 * Pointer to rte_flow_item objects list.
418 * Pointer to flow attributes structure.
420 * Pointer to the error structure.
423 * 0 on success, a negative errno value otherwise and rte_errno is set.
426 flow_dv_convert_action_modify_tp
427 (struct mlx5_flow_dv_modify_hdr_resource *resource,
428 const struct rte_flow_action *action,
429 const struct rte_flow_item *items,
430 union flow_dv_attr *attr,
431 struct rte_flow_error *error)
433 const struct rte_flow_action_set_tp *conf =
434 (const struct rte_flow_action_set_tp *)(action->conf);
435 struct rte_flow_item item;
436 struct rte_flow_item_udp udp;
437 struct rte_flow_item_udp udp_mask;
438 struct rte_flow_item_tcp tcp;
439 struct rte_flow_item_tcp tcp_mask;
440 struct field_modify_info *field;
443 flow_dv_attr_init(items, attr);
445 memset(&udp, 0, sizeof(udp));
446 memset(&udp_mask, 0, sizeof(udp_mask));
447 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
448 udp.hdr.src_port = conf->port;
449 udp_mask.hdr.src_port =
450 rte_flow_item_udp_mask.hdr.src_port;
452 udp.hdr.dst_port = conf->port;
453 udp_mask.hdr.dst_port =
454 rte_flow_item_udp_mask.hdr.dst_port;
456 item.type = RTE_FLOW_ITEM_TYPE_UDP;
458 item.mask = &udp_mask;
462 memset(&tcp, 0, sizeof(tcp));
463 memset(&tcp_mask, 0, sizeof(tcp_mask));
464 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
465 tcp.hdr.src_port = conf->port;
466 tcp_mask.hdr.src_port =
467 rte_flow_item_tcp_mask.hdr.src_port;
469 tcp.hdr.dst_port = conf->port;
470 tcp_mask.hdr.dst_port =
471 rte_flow_item_tcp_mask.hdr.dst_port;
473 item.type = RTE_FLOW_ITEM_TYPE_TCP;
475 item.mask = &tcp_mask;
478 return flow_dv_convert_modify_action(&item, field, resource,
479 MLX5_MODIFICATION_TYPE_SET, error);
483 * Convert modify-header set TTL action to DV specification.
485 * @param[in,out] resource
486 * Pointer to the modify-header resource.
488 * Pointer to action specification.
490 * Pointer to rte_flow_item objects list.
492 * Pointer to flow attributes structure.
494 * Pointer to the error structure.
497 * 0 on success, a negative errno value otherwise and rte_errno is set.
500 flow_dv_convert_action_modify_ttl
501 (struct mlx5_flow_dv_modify_hdr_resource *resource,
502 const struct rte_flow_action *action,
503 const struct rte_flow_item *items,
504 union flow_dv_attr *attr,
505 struct rte_flow_error *error)
507 const struct rte_flow_action_set_ttl *conf =
508 (const struct rte_flow_action_set_ttl *)(action->conf);
509 struct rte_flow_item item;
510 struct rte_flow_item_ipv4 ipv4;
511 struct rte_flow_item_ipv4 ipv4_mask;
512 struct rte_flow_item_ipv6 ipv6;
513 struct rte_flow_item_ipv6 ipv6_mask;
514 struct field_modify_info *field;
517 flow_dv_attr_init(items, attr);
519 memset(&ipv4, 0, sizeof(ipv4));
520 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
521 ipv4.hdr.time_to_live = conf->ttl_value;
522 ipv4_mask.hdr.time_to_live = 0xFF;
523 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
525 item.mask = &ipv4_mask;
529 memset(&ipv6, 0, sizeof(ipv6));
530 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
531 ipv6.hdr.hop_limits = conf->ttl_value;
532 ipv6_mask.hdr.hop_limits = 0xFF;
533 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
535 item.mask = &ipv6_mask;
538 return flow_dv_convert_modify_action(&item, field, resource,
539 MLX5_MODIFICATION_TYPE_SET, error);
543 * Convert modify-header decrement TTL action to DV specification.
545 * @param[in,out] resource
546 * Pointer to the modify-header resource.
548 * Pointer to action specification.
550 * Pointer to rte_flow_item objects list.
552 * Pointer to flow attributes structure.
554 * Pointer to the error structure.
557 * 0 on success, a negative errno value otherwise and rte_errno is set.
560 flow_dv_convert_action_modify_dec_ttl
561 (struct mlx5_flow_dv_modify_hdr_resource *resource,
562 const struct rte_flow_item *items,
563 union flow_dv_attr *attr,
564 struct rte_flow_error *error)
566 struct rte_flow_item item;
567 struct rte_flow_item_ipv4 ipv4;
568 struct rte_flow_item_ipv4 ipv4_mask;
569 struct rte_flow_item_ipv6 ipv6;
570 struct rte_flow_item_ipv6 ipv6_mask;
571 struct field_modify_info *field;
574 flow_dv_attr_init(items, attr);
576 memset(&ipv4, 0, sizeof(ipv4));
577 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
578 ipv4.hdr.time_to_live = 0xFF;
579 ipv4_mask.hdr.time_to_live = 0xFF;
580 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
582 item.mask = &ipv4_mask;
586 memset(&ipv6, 0, sizeof(ipv6));
587 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
588 ipv6.hdr.hop_limits = 0xFF;
589 ipv6_mask.hdr.hop_limits = 0xFF;
590 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
592 item.mask = &ipv6_mask;
595 return flow_dv_convert_modify_action(&item, field, resource,
596 MLX5_MODIFICATION_TYPE_ADD, error);
600 * Convert modify-header increment/decrement TCP Sequence number
601 * to DV specification.
603 * @param[in,out] resource
604 * Pointer to the modify-header resource.
606 * Pointer to action specification.
608 * Pointer to the error structure.
611 * 0 on success, a negative errno value otherwise and rte_errno is set.
614 flow_dv_convert_action_modify_tcp_seq
615 (struct mlx5_flow_dv_modify_hdr_resource *resource,
616 const struct rte_flow_action *action,
617 struct rte_flow_error *error)
619 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
620 uint64_t value = rte_be_to_cpu_32(*conf);
621 struct rte_flow_item item;
622 struct rte_flow_item_tcp tcp;
623 struct rte_flow_item_tcp tcp_mask;
625 memset(&tcp, 0, sizeof(tcp));
626 memset(&tcp_mask, 0, sizeof(tcp_mask));
627 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
629 * The HW has no decrement operation, only increment operation.
630 * To simulate decrement X from Y using increment operation
631 * we need to add UINT32_MAX X times to Y.
632 * Each adding of UINT32_MAX decrements Y by 1.
635 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
636 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
637 item.type = RTE_FLOW_ITEM_TYPE_TCP;
639 item.mask = &tcp_mask;
640 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
641 MLX5_MODIFICATION_TYPE_ADD, error);
645 * Convert modify-header increment/decrement TCP Acknowledgment number
646 * to DV specification.
648 * @param[in,out] resource
649 * Pointer to the modify-header resource.
651 * Pointer to action specification.
653 * Pointer to the error structure.
656 * 0 on success, a negative errno value otherwise and rte_errno is set.
659 flow_dv_convert_action_modify_tcp_ack
660 (struct mlx5_flow_dv_modify_hdr_resource *resource,
661 const struct rte_flow_action *action,
662 struct rte_flow_error *error)
664 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
665 uint64_t value = rte_be_to_cpu_32(*conf);
666 struct rte_flow_item item;
667 struct rte_flow_item_tcp tcp;
668 struct rte_flow_item_tcp tcp_mask;
670 memset(&tcp, 0, sizeof(tcp));
671 memset(&tcp_mask, 0, sizeof(tcp_mask));
672 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
674 * The HW has no decrement operation, only increment operation.
675 * To simulate decrement X from Y using increment operation
676 * we need to add UINT32_MAX X times to Y.
677 * Each adding of UINT32_MAX decrements Y by 1.
680 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
681 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
682 item.type = RTE_FLOW_ITEM_TYPE_TCP;
684 item.mask = &tcp_mask;
685 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
686 MLX5_MODIFICATION_TYPE_ADD, error);
690 * Validate META item.
693 * Pointer to the rte_eth_dev structure.
695 * Item specification.
697 * Attributes of flow that includes this item.
699 * Pointer to error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
706 const struct rte_flow_item *item,
707 const struct rte_flow_attr *attr,
708 struct rte_flow_error *error)
710 const struct rte_flow_item_meta *spec = item->spec;
711 const struct rte_flow_item_meta *mask = item->mask;
712 const struct rte_flow_item_meta nic_mask = {
713 .data = RTE_BE32(UINT32_MAX)
716 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
718 if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
719 return rte_flow_error_set(error, EPERM,
720 RTE_FLOW_ERROR_TYPE_ITEM,
722 "match on metadata offload "
723 "configuration is off for this port");
725 return rte_flow_error_set(error, EINVAL,
726 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
728 "data cannot be empty");
730 return rte_flow_error_set(error, EINVAL,
731 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
733 "data cannot be zero");
735 mask = &rte_flow_item_meta_mask;
736 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
737 (const uint8_t *)&nic_mask,
738 sizeof(struct rte_flow_item_meta),
743 return rte_flow_error_set(error, ENOTSUP,
744 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
746 "pattern not supported for ingress");
751 * Validate vport item.
754 * Pointer to the rte_eth_dev structure.
756 * Item specification.
758 * Attributes of flow that includes this item.
759 * @param[in] item_flags
760 * Bit-fields that holds the items detected until now.
762 * Pointer to error structure.
765 * 0 on success, a negative errno value otherwise and rte_errno is set.
768 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
769 const struct rte_flow_item *item,
770 const struct rte_flow_attr *attr,
772 struct rte_flow_error *error)
774 const struct rte_flow_item_port_id *spec = item->spec;
775 const struct rte_flow_item_port_id *mask = item->mask;
776 const struct rte_flow_item_port_id switch_mask = {
779 uint16_t esw_domain_id;
780 uint16_t item_port_esw_domain_id;
784 return rte_flow_error_set(error, EINVAL,
785 RTE_FLOW_ERROR_TYPE_ITEM,
787 "match on port id is valid only"
788 " when transfer flag is enabled");
789 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
790 return rte_flow_error_set(error, ENOTSUP,
791 RTE_FLOW_ERROR_TYPE_ITEM, item,
792 "multiple source ports are not"
796 if (mask->id != 0xffffffff)
797 return rte_flow_error_set(error, ENOTSUP,
798 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
800 "no support for partial mask on"
802 ret = mlx5_flow_item_acceptable
803 (item, (const uint8_t *)mask,
804 (const uint8_t *)&rte_flow_item_port_id_mask,
805 sizeof(struct rte_flow_item_port_id),
811 ret = mlx5_port_to_eswitch_info(spec->id, &item_port_esw_domain_id,
814 return rte_flow_error_set(error, -ret,
815 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
816 "failed to obtain E-Switch info for"
818 ret = mlx5_port_to_eswitch_info(dev->data->port_id,
819 &esw_domain_id, NULL);
821 return rte_flow_error_set(error, -ret,
822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
824 "failed to obtain E-Switch info");
825 if (item_port_esw_domain_id != esw_domain_id)
826 return rte_flow_error_set(error, -ret,
827 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
828 "cannot match on a port from a"
829 " different E-Switch");
834 * Validate count action.
839 * Pointer to error structure.
842 * 0 on success, a negative errno value otherwise and rte_errno is set.
845 flow_dv_validate_action_count(struct rte_eth_dev *dev,
846 struct rte_flow_error *error)
848 struct mlx5_priv *priv = dev->data->dev_private;
850 if (!priv->config.devx)
852 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
856 return rte_flow_error_set
858 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
860 "count action not supported");
864 * Validate the L2 encap action.
866 * @param[in] action_flags
867 * Holds the actions detected until now.
869 * Pointer to the encap action.
871 * Pointer to flow attributes
873 * Pointer to error structure.
876 * 0 on success, a negative errno value otherwise and rte_errno is set.
879 flow_dv_validate_action_l2_encap(uint64_t action_flags,
880 const struct rte_flow_action *action,
881 const struct rte_flow_attr *attr,
882 struct rte_flow_error *error)
885 return rte_flow_error_set(error, EINVAL,
886 RTE_FLOW_ERROR_TYPE_ACTION, action,
887 "configuration cannot be null");
888 if (action_flags & MLX5_FLOW_ACTION_DROP)
889 return rte_flow_error_set(error, EINVAL,
890 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
891 "can't drop and encap in same flow");
892 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
893 return rte_flow_error_set(error, EINVAL,
894 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
895 "can only have a single encap or"
896 " decap action in a flow");
897 if (!attr->transfer && attr->ingress)
898 return rte_flow_error_set(error, ENOTSUP,
899 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
901 "encap action not supported for "
907 * Validate the L2 decap action.
909 * @param[in] action_flags
910 * Holds the actions detected until now.
912 * Pointer to flow attributes
914 * Pointer to error structure.
917 * 0 on success, a negative errno value otherwise and rte_errno is set.
920 flow_dv_validate_action_l2_decap(uint64_t action_flags,
921 const struct rte_flow_attr *attr,
922 struct rte_flow_error *error)
924 if (action_flags & MLX5_FLOW_ACTION_DROP)
925 return rte_flow_error_set(error, EINVAL,
926 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
927 "can't drop and decap in same flow");
928 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
929 return rte_flow_error_set(error, EINVAL,
930 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
931 "can only have a single encap or"
932 " decap action in a flow");
933 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
934 return rte_flow_error_set(error, EINVAL,
935 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
936 "can't have decap action after"
939 return rte_flow_error_set(error, ENOTSUP,
940 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
942 "decap action not supported for "
948 * Validate the raw encap action.
950 * @param[in] action_flags
951 * Holds the actions detected until now.
953 * Pointer to the encap action.
955 * Pointer to flow attributes
957 * Pointer to error structure.
960 * 0 on success, a negative errno value otherwise and rte_errno is set.
963 flow_dv_validate_action_raw_encap(uint64_t action_flags,
964 const struct rte_flow_action *action,
965 const struct rte_flow_attr *attr,
966 struct rte_flow_error *error)
969 return rte_flow_error_set(error, EINVAL,
970 RTE_FLOW_ERROR_TYPE_ACTION, action,
971 "configuration cannot be null");
972 if (action_flags & MLX5_FLOW_ACTION_DROP)
973 return rte_flow_error_set(error, EINVAL,
974 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
975 "can't drop and encap in same flow");
976 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
977 return rte_flow_error_set(error, EINVAL,
978 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
979 "can only have a single encap"
980 " action in a flow");
981 /* encap without preceding decap is not supported for ingress */
982 if (!attr->transfer && attr->ingress &&
983 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
984 return rte_flow_error_set(error, ENOTSUP,
985 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
987 "encap action not supported for "
993 * Validate the raw decap action.
995 * @param[in] action_flags
996 * Holds the actions detected until now.
998 * Pointer to the encap action.
1000 * Pointer to flow attributes
1002 * Pointer to error structure.
1005 * 0 on success, a negative errno value otherwise and rte_errno is set.
1008 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1009 const struct rte_flow_action *action,
1010 const struct rte_flow_attr *attr,
1011 struct rte_flow_error *error)
1013 if (action_flags & MLX5_FLOW_ACTION_DROP)
1014 return rte_flow_error_set(error, EINVAL,
1015 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1016 "can't drop and decap in same flow");
1017 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1018 return rte_flow_error_set(error, EINVAL,
1019 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1020 "can't have encap action before"
1022 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1023 return rte_flow_error_set(error, EINVAL,
1024 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1025 "can only have a single decap"
1026 " action in a flow");
1027 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1028 return rte_flow_error_set(error, EINVAL,
1029 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1030 "can't have decap action after"
1032 /* decap action is valid on egress only if it is followed by encap */
1034 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1035 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1038 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1039 return rte_flow_error_set
1041 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1042 NULL, "decap action not supported"
1049 * Find existing encap/decap resource or create and register a new one.
1051 * @param dev[in, out]
1052 * Pointer to rte_eth_dev structure.
1053 * @param[in, out] resource
1054 * Pointer to encap/decap resource.
1055 * @parm[in, out] dev_flow
1056 * Pointer to the dev_flow.
1058 * pointer to error structure.
1061 * 0 on success otherwise -errno and errno is set.
1064 flow_dv_encap_decap_resource_register
1065 (struct rte_eth_dev *dev,
1066 struct mlx5_flow_dv_encap_decap_resource *resource,
1067 struct mlx5_flow *dev_flow,
1068 struct rte_flow_error *error)
1070 struct mlx5_priv *priv = dev->data->dev_private;
1071 struct mlx5_ibv_shared *sh = priv->sh;
1072 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1073 struct rte_flow *flow = dev_flow->flow;
1074 struct mlx5dv_dr_domain *domain;
1076 resource->flags = flow->group ? 0 : 1;
1077 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1078 domain = sh->fdb_domain;
1079 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1080 domain = sh->rx_domain;
1082 domain = sh->tx_domain;
1084 /* Lookup a matching resource from cache. */
1085 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1086 if (resource->reformat_type == cache_resource->reformat_type &&
1087 resource->ft_type == cache_resource->ft_type &&
1088 resource->flags == cache_resource->flags &&
1089 resource->size == cache_resource->size &&
1090 !memcmp((const void *)resource->buf,
1091 (const void *)cache_resource->buf,
1093 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1094 (void *)cache_resource,
1095 rte_atomic32_read(&cache_resource->refcnt));
1096 rte_atomic32_inc(&cache_resource->refcnt);
1097 dev_flow->dv.encap_decap = cache_resource;
1101 /* Register new encap/decap resource. */
1102 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1103 if (!cache_resource)
1104 return rte_flow_error_set(error, ENOMEM,
1105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1106 "cannot allocate resource memory");
1107 *cache_resource = *resource;
1108 cache_resource->verbs_action =
1109 mlx5_glue->dv_create_flow_action_packet_reformat
1110 (sh->ctx, cache_resource->reformat_type,
1111 cache_resource->ft_type, domain, cache_resource->flags,
1112 cache_resource->size,
1113 (cache_resource->size ? cache_resource->buf : NULL));
1114 if (!cache_resource->verbs_action) {
1115 rte_free(cache_resource);
1116 return rte_flow_error_set(error, ENOMEM,
1117 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1118 NULL, "cannot create action");
1120 rte_atomic32_init(&cache_resource->refcnt);
1121 rte_atomic32_inc(&cache_resource->refcnt);
1122 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1123 dev_flow->dv.encap_decap = cache_resource;
1124 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1125 (void *)cache_resource,
1126 rte_atomic32_read(&cache_resource->refcnt));
1131 * Find existing table jump resource or create and register a new one.
1133 * @param dev[in, out]
1134 * Pointer to rte_eth_dev structure.
1135 * @param[in, out] resource
1136 * Pointer to jump table resource.
1137 * @parm[in, out] dev_flow
1138 * Pointer to the dev_flow.
1140 * pointer to error structure.
1143 * 0 on success otherwise -errno and errno is set.
1146 flow_dv_jump_tbl_resource_register
1147 (struct rte_eth_dev *dev,
1148 struct mlx5_flow_dv_jump_tbl_resource *resource,
1149 struct mlx5_flow *dev_flow,
1150 struct rte_flow_error *error)
1152 struct mlx5_priv *priv = dev->data->dev_private;
1153 struct mlx5_ibv_shared *sh = priv->sh;
1154 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1156 /* Lookup a matching resource from cache. */
1157 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1158 if (resource->tbl == cache_resource->tbl) {
1159 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1160 (void *)cache_resource,
1161 rte_atomic32_read(&cache_resource->refcnt));
1162 rte_atomic32_inc(&cache_resource->refcnt);
1163 dev_flow->dv.jump = cache_resource;
1167 /* Register new jump table resource. */
1168 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1169 if (!cache_resource)
1170 return rte_flow_error_set(error, ENOMEM,
1171 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1172 "cannot allocate resource memory");
1173 *cache_resource = *resource;
1174 cache_resource->action =
1175 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1176 (resource->tbl->obj);
1177 if (!cache_resource->action) {
1178 rte_free(cache_resource);
1179 return rte_flow_error_set(error, ENOMEM,
1180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1181 NULL, "cannot create action");
1183 rte_atomic32_init(&cache_resource->refcnt);
1184 rte_atomic32_inc(&cache_resource->refcnt);
1185 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1186 dev_flow->dv.jump = cache_resource;
1187 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1188 (void *)cache_resource,
1189 rte_atomic32_read(&cache_resource->refcnt));
1194 * Find existing table port ID resource or create and register a new one.
1196 * @param dev[in, out]
1197 * Pointer to rte_eth_dev structure.
1198 * @param[in, out] resource
1199 * Pointer to port ID action resource.
1200 * @parm[in, out] dev_flow
1201 * Pointer to the dev_flow.
1203 * pointer to error structure.
1206 * 0 on success otherwise -errno and errno is set.
1209 flow_dv_port_id_action_resource_register
1210 (struct rte_eth_dev *dev,
1211 struct mlx5_flow_dv_port_id_action_resource *resource,
1212 struct mlx5_flow *dev_flow,
1213 struct rte_flow_error *error)
1215 struct mlx5_priv *priv = dev->data->dev_private;
1216 struct mlx5_ibv_shared *sh = priv->sh;
1217 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1219 /* Lookup a matching resource from cache. */
1220 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1221 if (resource->port_id == cache_resource->port_id) {
1222 DRV_LOG(DEBUG, "port id action resource resource %p: "
1224 (void *)cache_resource,
1225 rte_atomic32_read(&cache_resource->refcnt));
1226 rte_atomic32_inc(&cache_resource->refcnt);
1227 dev_flow->dv.port_id_action = cache_resource;
1231 /* Register new port id action resource. */
1232 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1233 if (!cache_resource)
1234 return rte_flow_error_set(error, ENOMEM,
1235 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1236 "cannot allocate resource memory");
1237 *cache_resource = *resource;
1238 cache_resource->action =
1239 mlx5_glue->dr_create_flow_action_dest_vport
1240 (priv->sh->fdb_domain, resource->port_id);
1241 if (!cache_resource->action) {
1242 rte_free(cache_resource);
1243 return rte_flow_error_set(error, ENOMEM,
1244 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1245 NULL, "cannot create action");
1247 rte_atomic32_init(&cache_resource->refcnt);
1248 rte_atomic32_inc(&cache_resource->refcnt);
1249 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1250 dev_flow->dv.port_id_action = cache_resource;
1251 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1252 (void *)cache_resource,
1253 rte_atomic32_read(&cache_resource->refcnt));
1258 * Get the size of specific rte_flow_item_type
1260 * @param[in] item_type
1261 * Tested rte_flow_item_type.
1264 * sizeof struct item_type, 0 if void or irrelevant.
1267 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1271 switch (item_type) {
1272 case RTE_FLOW_ITEM_TYPE_ETH:
1273 retval = sizeof(struct rte_flow_item_eth);
1275 case RTE_FLOW_ITEM_TYPE_VLAN:
1276 retval = sizeof(struct rte_flow_item_vlan);
1278 case RTE_FLOW_ITEM_TYPE_IPV4:
1279 retval = sizeof(struct rte_flow_item_ipv4);
1281 case RTE_FLOW_ITEM_TYPE_IPV6:
1282 retval = sizeof(struct rte_flow_item_ipv6);
1284 case RTE_FLOW_ITEM_TYPE_UDP:
1285 retval = sizeof(struct rte_flow_item_udp);
1287 case RTE_FLOW_ITEM_TYPE_TCP:
1288 retval = sizeof(struct rte_flow_item_tcp);
1290 case RTE_FLOW_ITEM_TYPE_VXLAN:
1291 retval = sizeof(struct rte_flow_item_vxlan);
1293 case RTE_FLOW_ITEM_TYPE_GRE:
1294 retval = sizeof(struct rte_flow_item_gre);
1296 case RTE_FLOW_ITEM_TYPE_NVGRE:
1297 retval = sizeof(struct rte_flow_item_nvgre);
1299 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1300 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1302 case RTE_FLOW_ITEM_TYPE_MPLS:
1303 retval = sizeof(struct rte_flow_item_mpls);
1305 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1313 #define MLX5_ENCAP_IPV4_VERSION 0x40
1314 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1315 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1316 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1317 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1318 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1319 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1322 * Convert the encap action data from list of rte_flow_item to raw buffer
1325 * Pointer to rte_flow_item objects list.
1327 * Pointer to the output buffer.
1329 * Pointer to the output buffer size.
1331 * Pointer to the error structure.
1334 * 0 on success, a negative errno value otherwise and rte_errno is set.
1337 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1338 size_t *size, struct rte_flow_error *error)
1340 struct rte_ether_hdr *eth = NULL;
1341 struct rte_vlan_hdr *vlan = NULL;
1342 struct rte_ipv4_hdr *ipv4 = NULL;
1343 struct rte_ipv6_hdr *ipv6 = NULL;
1344 struct rte_udp_hdr *udp = NULL;
1345 struct rte_vxlan_hdr *vxlan = NULL;
1346 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1347 struct rte_gre_hdr *gre = NULL;
1349 size_t temp_size = 0;
1352 return rte_flow_error_set(error, EINVAL,
1353 RTE_FLOW_ERROR_TYPE_ACTION,
1354 NULL, "invalid empty data");
1355 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1356 len = flow_dv_get_item_len(items->type);
1357 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1358 return rte_flow_error_set(error, EINVAL,
1359 RTE_FLOW_ERROR_TYPE_ACTION,
1360 (void *)items->type,
1361 "items total size is too big"
1362 " for encap action");
1363 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1364 switch (items->type) {
1365 case RTE_FLOW_ITEM_TYPE_ETH:
1366 eth = (struct rte_ether_hdr *)&buf[temp_size];
1368 case RTE_FLOW_ITEM_TYPE_VLAN:
1369 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1371 return rte_flow_error_set(error, EINVAL,
1372 RTE_FLOW_ERROR_TYPE_ACTION,
1373 (void *)items->type,
1374 "eth header not found");
1375 if (!eth->ether_type)
1376 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1378 case RTE_FLOW_ITEM_TYPE_IPV4:
1379 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1381 return rte_flow_error_set(error, EINVAL,
1382 RTE_FLOW_ERROR_TYPE_ACTION,
1383 (void *)items->type,
1384 "neither eth nor vlan"
1386 if (vlan && !vlan->eth_proto)
1387 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1388 else if (eth && !eth->ether_type)
1389 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1390 if (!ipv4->version_ihl)
1391 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1392 MLX5_ENCAP_IPV4_IHL_MIN;
1393 if (!ipv4->time_to_live)
1394 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1396 case RTE_FLOW_ITEM_TYPE_IPV6:
1397 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1399 return rte_flow_error_set(error, EINVAL,
1400 RTE_FLOW_ERROR_TYPE_ACTION,
1401 (void *)items->type,
1402 "neither eth nor vlan"
1404 if (vlan && !vlan->eth_proto)
1405 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1406 else if (eth && !eth->ether_type)
1407 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1408 if (!ipv6->vtc_flow)
1410 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1411 if (!ipv6->hop_limits)
1412 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1414 case RTE_FLOW_ITEM_TYPE_UDP:
1415 udp = (struct rte_udp_hdr *)&buf[temp_size];
1417 return rte_flow_error_set(error, EINVAL,
1418 RTE_FLOW_ERROR_TYPE_ACTION,
1419 (void *)items->type,
1420 "ip header not found");
1421 if (ipv4 && !ipv4->next_proto_id)
1422 ipv4->next_proto_id = IPPROTO_UDP;
1423 else if (ipv6 && !ipv6->proto)
1424 ipv6->proto = IPPROTO_UDP;
1426 case RTE_FLOW_ITEM_TYPE_VXLAN:
1427 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1429 return rte_flow_error_set(error, EINVAL,
1430 RTE_FLOW_ERROR_TYPE_ACTION,
1431 (void *)items->type,
1432 "udp header not found");
1434 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1435 if (!vxlan->vx_flags)
1437 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1439 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1440 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1442 return rte_flow_error_set(error, EINVAL,
1443 RTE_FLOW_ERROR_TYPE_ACTION,
1444 (void *)items->type,
1445 "udp header not found");
1446 if (!vxlan_gpe->proto)
1447 return rte_flow_error_set(error, EINVAL,
1448 RTE_FLOW_ERROR_TYPE_ACTION,
1449 (void *)items->type,
1450 "next protocol not found");
1453 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1454 if (!vxlan_gpe->vx_flags)
1455 vxlan_gpe->vx_flags =
1456 MLX5_ENCAP_VXLAN_GPE_FLAGS;
1458 case RTE_FLOW_ITEM_TYPE_GRE:
1459 case RTE_FLOW_ITEM_TYPE_NVGRE:
1460 gre = (struct rte_gre_hdr *)&buf[temp_size];
1462 return rte_flow_error_set(error, EINVAL,
1463 RTE_FLOW_ERROR_TYPE_ACTION,
1464 (void *)items->type,
1465 "next protocol not found");
1467 return rte_flow_error_set(error, EINVAL,
1468 RTE_FLOW_ERROR_TYPE_ACTION,
1469 (void *)items->type,
1470 "ip header not found");
1471 if (ipv4 && !ipv4->next_proto_id)
1472 ipv4->next_proto_id = IPPROTO_GRE;
1473 else if (ipv6 && !ipv6->proto)
1474 ipv6->proto = IPPROTO_GRE;
1476 case RTE_FLOW_ITEM_TYPE_VOID:
1479 return rte_flow_error_set(error, EINVAL,
1480 RTE_FLOW_ERROR_TYPE_ACTION,
1481 (void *)items->type,
1482 "unsupported item type");
1492 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
1494 struct rte_ether_hdr *eth = NULL;
1495 struct rte_vlan_hdr *vlan = NULL;
1496 struct rte_ipv6_hdr *ipv6 = NULL;
1497 struct rte_udp_hdr *udp = NULL;
1501 eth = (struct rte_ether_hdr *)data;
1502 next_hdr = (char *)(eth + 1);
1503 proto = RTE_BE16(eth->ether_type);
1506 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
1507 next_hdr += sizeof(struct rte_vlan_hdr);
1508 vlan = (struct rte_vlan_hdr *)next_hdr;
1509 proto = RTE_BE16(vlan->eth_proto);
1512 /* HW calculates IPv4 csum. no need to proceed */
1513 if (proto == RTE_ETHER_TYPE_IPV4)
1516 /* non IPv4/IPv6 header. not supported */
1517 if (proto != RTE_ETHER_TYPE_IPV6) {
1518 return rte_flow_error_set(error, ENOTSUP,
1519 RTE_FLOW_ERROR_TYPE_ACTION,
1520 NULL, "Cannot offload non IPv4/IPv6");
1523 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
1525 /* ignore non UDP */
1526 if (ipv6->proto != IPPROTO_UDP)
1529 udp = (struct rte_udp_hdr *)(ipv6 + 1);
1530 udp->dgram_cksum = 0;
1536 * Convert L2 encap action to DV specification.
1539 * Pointer to rte_eth_dev structure.
1541 * Pointer to action structure.
1542 * @param[in, out] dev_flow
1543 * Pointer to the mlx5_flow.
1544 * @param[in] transfer
1545 * Mark if the flow is E-Switch flow.
1547 * Pointer to the error structure.
1550 * 0 on success, a negative errno value otherwise and rte_errno is set.
1553 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
1554 const struct rte_flow_action *action,
1555 struct mlx5_flow *dev_flow,
1557 struct rte_flow_error *error)
1559 const struct rte_flow_item *encap_data;
1560 const struct rte_flow_action_raw_encap *raw_encap_data;
1561 struct mlx5_flow_dv_encap_decap_resource res = {
1563 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
1564 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1565 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
1568 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1570 (const struct rte_flow_action_raw_encap *)action->conf;
1571 res.size = raw_encap_data->size;
1572 memcpy(res.buf, raw_encap_data->data, res.size);
1573 if (flow_dv_zero_encap_udp_csum(res.buf, error))
1576 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
1578 ((const struct rte_flow_action_vxlan_encap *)
1579 action->conf)->definition;
1582 ((const struct rte_flow_action_nvgre_encap *)
1583 action->conf)->definition;
1584 if (flow_dv_convert_encap_data(encap_data, res.buf,
1588 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1589 return rte_flow_error_set(error, EINVAL,
1590 RTE_FLOW_ERROR_TYPE_ACTION,
1591 NULL, "can't create L2 encap action");
1596 * Convert L2 decap action to DV specification.
1599 * Pointer to rte_eth_dev structure.
1600 * @param[in, out] dev_flow
1601 * Pointer to the mlx5_flow.
1602 * @param[in] transfer
1603 * Mark if the flow is E-Switch flow.
1605 * Pointer to the error structure.
1608 * 0 on success, a negative errno value otherwise and rte_errno is set.
1611 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
1612 struct mlx5_flow *dev_flow,
1614 struct rte_flow_error *error)
1616 struct mlx5_flow_dv_encap_decap_resource res = {
1619 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
1620 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1621 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
1624 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1625 return rte_flow_error_set(error, EINVAL,
1626 RTE_FLOW_ERROR_TYPE_ACTION,
1627 NULL, "can't create L2 decap action");
1632 * Convert raw decap/encap (L3 tunnel) action to DV specification.
1635 * Pointer to rte_eth_dev structure.
1637 * Pointer to action structure.
1638 * @param[in, out] dev_flow
1639 * Pointer to the mlx5_flow.
1641 * Pointer to the flow attributes.
1643 * Pointer to the error structure.
1646 * 0 on success, a negative errno value otherwise and rte_errno is set.
1649 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
1650 const struct rte_flow_action *action,
1651 struct mlx5_flow *dev_flow,
1652 const struct rte_flow_attr *attr,
1653 struct rte_flow_error *error)
1655 const struct rte_flow_action_raw_encap *encap_data;
1656 struct mlx5_flow_dv_encap_decap_resource res;
1658 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
1659 res.size = encap_data->size;
1660 memcpy(res.buf, encap_data->data, res.size);
1661 res.reformat_type = attr->egress ?
1662 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
1663 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
1665 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
1667 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
1668 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
1669 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1670 return rte_flow_error_set(error, EINVAL,
1671 RTE_FLOW_ERROR_TYPE_ACTION,
1672 NULL, "can't create encap action");
1677 * Validate the modify-header actions.
1679 * @param[in] action_flags
1680 * Holds the actions detected until now.
1682 * Pointer to the modify action.
1684 * Pointer to error structure.
1687 * 0 on success, a negative errno value otherwise and rte_errno is set.
1690 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
1691 const struct rte_flow_action *action,
1692 struct rte_flow_error *error)
1694 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
1695 return rte_flow_error_set(error, EINVAL,
1696 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1697 NULL, "action configuration not set");
1698 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1699 return rte_flow_error_set(error, EINVAL,
1700 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1701 "can't have encap action before"
1707 * Validate the modify-header MAC address actions.
1709 * @param[in] action_flags
1710 * Holds the actions detected until now.
1712 * Pointer to the modify action.
1713 * @param[in] item_flags
1714 * Holds the items detected.
1716 * Pointer to error structure.
1719 * 0 on success, a negative errno value otherwise and rte_errno is set.
1722 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
1723 const struct rte_flow_action *action,
1724 const uint64_t item_flags,
1725 struct rte_flow_error *error)
1729 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1731 if (!(item_flags & MLX5_FLOW_LAYER_L2))
1732 return rte_flow_error_set(error, EINVAL,
1733 RTE_FLOW_ERROR_TYPE_ACTION,
1735 "no L2 item in pattern");
1741 * Validate the modify-header IPv4 address actions.
1743 * @param[in] action_flags
1744 * Holds the actions detected until now.
1746 * Pointer to the modify action.
1747 * @param[in] item_flags
1748 * Holds the items detected.
1750 * Pointer to error structure.
1753 * 0 on success, a negative errno value otherwise and rte_errno is set.
1756 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
1757 const struct rte_flow_action *action,
1758 const uint64_t item_flags,
1759 struct rte_flow_error *error)
1763 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1765 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
1766 return rte_flow_error_set(error, EINVAL,
1767 RTE_FLOW_ERROR_TYPE_ACTION,
1769 "no ipv4 item in pattern");
1775 * Validate the modify-header IPv6 address actions.
1777 * @param[in] action_flags
1778 * Holds the actions detected until now.
1780 * Pointer to the modify action.
1781 * @param[in] item_flags
1782 * Holds the items detected.
1784 * Pointer to error structure.
1787 * 0 on success, a negative errno value otherwise and rte_errno is set.
1790 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
1791 const struct rte_flow_action *action,
1792 const uint64_t item_flags,
1793 struct rte_flow_error *error)
1797 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1799 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
1800 return rte_flow_error_set(error, EINVAL,
1801 RTE_FLOW_ERROR_TYPE_ACTION,
1803 "no ipv6 item in pattern");
1809 * Validate the modify-header TP actions.
1811 * @param[in] action_flags
1812 * Holds the actions detected until now.
1814 * Pointer to the modify action.
1815 * @param[in] item_flags
1816 * Holds the items detected.
1818 * Pointer to error structure.
1821 * 0 on success, a negative errno value otherwise and rte_errno is set.
1824 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
1825 const struct rte_flow_action *action,
1826 const uint64_t item_flags,
1827 struct rte_flow_error *error)
1831 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1833 if (!(item_flags & MLX5_FLOW_LAYER_L4))
1834 return rte_flow_error_set(error, EINVAL,
1835 RTE_FLOW_ERROR_TYPE_ACTION,
1836 NULL, "no transport layer "
1843 * Validate the modify-header actions of increment/decrement
1844 * TCP Sequence-number.
1846 * @param[in] action_flags
1847 * Holds the actions detected until now.
1849 * Pointer to the modify action.
1850 * @param[in] item_flags
1851 * Holds the items detected.
1853 * Pointer to error structure.
1856 * 0 on success, a negative errno value otherwise and rte_errno is set.
1859 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
1860 const struct rte_flow_action *action,
1861 const uint64_t item_flags,
1862 struct rte_flow_error *error)
1866 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1868 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
1869 return rte_flow_error_set(error, EINVAL,
1870 RTE_FLOW_ERROR_TYPE_ACTION,
1871 NULL, "no TCP item in"
1873 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
1874 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
1875 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
1876 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
1877 return rte_flow_error_set(error, EINVAL,
1878 RTE_FLOW_ERROR_TYPE_ACTION,
1880 "cannot decrease and increase"
1881 " TCP sequence number"
1882 " at the same time");
1888 * Validate the modify-header actions of increment/decrement
1889 * TCP Acknowledgment number.
1891 * @param[in] action_flags
1892 * Holds the actions detected until now.
1894 * Pointer to the modify action.
1895 * @param[in] item_flags
1896 * Holds the items detected.
1898 * Pointer to error structure.
1901 * 0 on success, a negative errno value otherwise and rte_errno is set.
1904 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
1905 const struct rte_flow_action *action,
1906 const uint64_t item_flags,
1907 struct rte_flow_error *error)
1911 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1913 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
1914 return rte_flow_error_set(error, EINVAL,
1915 RTE_FLOW_ERROR_TYPE_ACTION,
1916 NULL, "no TCP item in"
1918 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
1919 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
1920 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
1921 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
1922 return rte_flow_error_set(error, EINVAL,
1923 RTE_FLOW_ERROR_TYPE_ACTION,
1925 "cannot decrease and increase"
1926 " TCP acknowledgment number"
1927 " at the same time");
1933 * Validate the modify-header TTL actions.
1935 * @param[in] action_flags
1936 * Holds the actions detected until now.
1938 * Pointer to the modify action.
1939 * @param[in] item_flags
1940 * Holds the items detected.
1942 * Pointer to error structure.
1945 * 0 on success, a negative errno value otherwise and rte_errno is set.
1948 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
1949 const struct rte_flow_action *action,
1950 const uint64_t item_flags,
1951 struct rte_flow_error *error)
1955 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1957 if (!(item_flags & MLX5_FLOW_LAYER_L3))
1958 return rte_flow_error_set(error, EINVAL,
1959 RTE_FLOW_ERROR_TYPE_ACTION,
1961 "no IP protocol in pattern");
1967 * Validate jump action.
1970 * Pointer to the modify action.
1972 * The group of the current flow.
1974 * Pointer to error structure.
1977 * 0 on success, a negative errno value otherwise and rte_errno is set.
1980 flow_dv_validate_action_jump(const struct rte_flow_action *action,
1982 struct rte_flow_error *error)
1984 if (action->type != RTE_FLOW_ACTION_TYPE_JUMP && !action->conf)
1985 return rte_flow_error_set(error, EINVAL,
1986 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1987 NULL, "action configuration not set");
1988 if (group >= ((const struct rte_flow_action_jump *)action->conf)->group)
1989 return rte_flow_error_set(error, EINVAL,
1990 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1991 "target group must be higher then"
1992 " the current flow group");
1997 * Validate the port_id action.
2000 * Pointer to rte_eth_dev structure.
2001 * @param[in] action_flags
2002 * Bit-fields that holds the actions detected until now.
2004 * Port_id RTE action structure.
2006 * Attributes of flow that includes this action.
2008 * Pointer to error structure.
2011 * 0 on success, a negative errno value otherwise and rte_errno is set.
2014 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2015 uint64_t action_flags,
2016 const struct rte_flow_action *action,
2017 const struct rte_flow_attr *attr,
2018 struct rte_flow_error *error)
2020 const struct rte_flow_action_port_id *port_id;
2022 uint16_t esw_domain_id;
2023 uint16_t act_port_domain_id;
2026 if (!attr->transfer)
2027 return rte_flow_error_set(error, ENOTSUP,
2028 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2030 "port id action is valid in transfer"
2032 if (!action || !action->conf)
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2036 "port id action parameters must be"
2038 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2039 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2040 return rte_flow_error_set(error, EINVAL,
2041 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2042 "can have only one fate actions in"
2044 ret = mlx5_port_to_eswitch_info(dev->data->port_id,
2045 &esw_domain_id, NULL);
2047 return rte_flow_error_set(error, -ret,
2048 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2050 "failed to obtain E-Switch info");
2051 port_id = action->conf;
2052 port = port_id->original ? dev->data->port_id : port_id->id;
2053 ret = mlx5_port_to_eswitch_info(port, &act_port_domain_id, NULL);
2055 return rte_flow_error_set
2057 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2058 "failed to obtain E-Switch port id for port");
2059 if (act_port_domain_id != esw_domain_id)
2060 return rte_flow_error_set
2062 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2063 "port does not belong to"
2064 " E-Switch being configured");
2069 * Find existing modify-header resource or create and register a new one.
2071 * @param dev[in, out]
2072 * Pointer to rte_eth_dev structure.
2073 * @param[in, out] resource
2074 * Pointer to modify-header resource.
2075 * @parm[in, out] dev_flow
2076 * Pointer to the dev_flow.
2078 * pointer to error structure.
2081 * 0 on success otherwise -errno and errno is set.
2084 flow_dv_modify_hdr_resource_register
2085 (struct rte_eth_dev *dev,
2086 struct mlx5_flow_dv_modify_hdr_resource *resource,
2087 struct mlx5_flow *dev_flow,
2088 struct rte_flow_error *error)
2090 struct mlx5_priv *priv = dev->data->dev_private;
2091 struct mlx5_ibv_shared *sh = priv->sh;
2092 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2093 struct mlx5dv_dr_domain *ns;
2095 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2096 ns = sh->fdb_domain;
2097 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2102 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2103 /* Lookup a matching resource from cache. */
2104 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2105 if (resource->ft_type == cache_resource->ft_type &&
2106 resource->actions_num == cache_resource->actions_num &&
2107 resource->flags == cache_resource->flags &&
2108 !memcmp((const void *)resource->actions,
2109 (const void *)cache_resource->actions,
2110 (resource->actions_num *
2111 sizeof(resource->actions[0])))) {
2112 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2113 (void *)cache_resource,
2114 rte_atomic32_read(&cache_resource->refcnt));
2115 rte_atomic32_inc(&cache_resource->refcnt);
2116 dev_flow->dv.modify_hdr = cache_resource;
2120 /* Register new modify-header resource. */
2121 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2122 if (!cache_resource)
2123 return rte_flow_error_set(error, ENOMEM,
2124 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2125 "cannot allocate resource memory");
2126 *cache_resource = *resource;
2127 cache_resource->verbs_action =
2128 mlx5_glue->dv_create_flow_action_modify_header
2129 (sh->ctx, cache_resource->ft_type,
2130 ns, cache_resource->flags,
2131 cache_resource->actions_num *
2132 sizeof(cache_resource->actions[0]),
2133 (uint64_t *)cache_resource->actions);
2134 if (!cache_resource->verbs_action) {
2135 rte_free(cache_resource);
2136 return rte_flow_error_set(error, ENOMEM,
2137 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2138 NULL, "cannot create action");
2140 rte_atomic32_init(&cache_resource->refcnt);
2141 rte_atomic32_inc(&cache_resource->refcnt);
2142 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2143 dev_flow->dv.modify_hdr = cache_resource;
2144 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2145 (void *)cache_resource,
2146 rte_atomic32_read(&cache_resource->refcnt));
2150 #define MLX5_CNT_CONTAINER_RESIZE 64
2153 * Get or create a flow counter.
2156 * Pointer to the Ethernet device structure.
2158 * Indicate if this counter is shared with other flows.
2160 * Counter identifier.
2163 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2165 static struct mlx5_flow_counter *
2166 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2169 struct mlx5_priv *priv = dev->data->dev_private;
2170 struct mlx5_flow_counter *cnt = NULL;
2171 struct mlx5_devx_obj *dcs = NULL;
2173 if (!priv->config.devx) {
2174 rte_errno = ENOTSUP;
2178 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2179 if (cnt->shared && cnt->id == id) {
2185 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2188 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2190 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2194 struct mlx5_flow_counter tmpl = {
2200 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2202 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2208 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2213 * Release a flow counter.
2216 * Pointer to the Ethernet device structure.
2217 * @param[in] counter
2218 * Pointer to the counter handler.
2221 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2222 struct mlx5_flow_counter *counter)
2224 struct mlx5_priv *priv = dev->data->dev_private;
2228 if (--counter->ref_cnt == 0) {
2229 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2230 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2236 * Query a devx flow counter.
2239 * Pointer to the Ethernet device structure.
2241 * Pointer to the flow counter.
2243 * The statistics value of packets.
2245 * The statistics value of bytes.
2248 * 0 on success, otherwise a negative errno value and rte_errno is set.
2251 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2252 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2255 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2260 * Get a pool by a counter.
2263 * Pointer to the counter.
2268 static struct mlx5_flow_counter_pool *
2269 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2272 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2273 return (struct mlx5_flow_counter_pool *)cnt - 1;
2279 * Get a pool by devx counter ID.
2282 * Pointer to the counter container.
2284 * The counter devx ID.
2287 * The counter pool pointer if exists, NULL otherwise,
2289 static struct mlx5_flow_counter_pool *
2290 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2292 struct mlx5_flow_counter_pool *pool;
2294 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2295 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2296 MLX5_COUNTERS_PER_POOL;
2298 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2305 * Allocate a new memory for the counter values wrapped by all the needed
2309 * Pointer to the Ethernet device structure.
2311 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2314 * The new memory management pointer on success, otherwise NULL and rte_errno
2317 static struct mlx5_counter_stats_mem_mng *
2318 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2320 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2321 (dev->data->dev_private))->sh;
2322 struct mlx5_devx_mkey_attr mkey_attr;
2323 struct mlx5_counter_stats_mem_mng *mem_mng;
2324 volatile struct flow_counter_stats *raw_data;
2325 int size = (sizeof(struct flow_counter_stats) *
2326 MLX5_COUNTERS_PER_POOL +
2327 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2328 sizeof(struct mlx5_counter_stats_mem_mng);
2329 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2336 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2337 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2338 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2339 IBV_ACCESS_LOCAL_WRITE);
2340 if (!mem_mng->umem) {
2345 mkey_attr.addr = (uintptr_t)mem;
2346 mkey_attr.size = size;
2347 mkey_attr.umem_id = mem_mng->umem->umem_id;
2348 mkey_attr.pd = sh->pdn;
2349 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2351 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2356 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2357 raw_data = (volatile struct flow_counter_stats *)mem;
2358 for (i = 0; i < raws_n; ++i) {
2359 mem_mng->raws[i].mem_mng = mem_mng;
2360 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2362 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2367 * Resize a counter container.
2370 * Pointer to the Ethernet device structure.
2372 * Whether the pool is for counter that was allocated by batch command.
2375 * The new container pointer on success, otherwise NULL and rte_errno is set.
2377 static struct mlx5_pools_container *
2378 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2380 struct mlx5_priv *priv = dev->data->dev_private;
2381 struct mlx5_pools_container *cont =
2382 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2383 struct mlx5_pools_container *new_cont =
2384 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2385 struct mlx5_counter_stats_mem_mng *mem_mng;
2386 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2387 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2390 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2391 /* The last resize still hasn't detected by the host thread. */
2395 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
2396 if (!new_cont->pools) {
2401 memcpy(new_cont->pools, cont->pools, cont->n *
2402 sizeof(struct mlx5_flow_counter_pool *));
2403 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
2404 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
2406 rte_free(new_cont->pools);
2409 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
2410 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
2411 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
2413 new_cont->n = resize;
2414 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
2415 TAILQ_INIT(&new_cont->pool_list);
2416 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
2417 new_cont->init_mem_mng = mem_mng;
2419 /* Flip the master container. */
2420 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
2425 * Query a devx flow counter.
2428 * Pointer to the Ethernet device structure.
2430 * Pointer to the flow counter.
2432 * The statistics value of packets.
2434 * The statistics value of bytes.
2437 * 0 on success, otherwise a negative errno value and rte_errno is set.
2440 _flow_dv_query_count(struct rte_eth_dev *dev,
2441 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2444 struct mlx5_priv *priv = dev->data->dev_private;
2445 struct mlx5_flow_counter_pool *pool =
2446 flow_dv_counter_pool_get(cnt);
2447 int offset = cnt - &pool->counters_raw[0];
2449 if (priv->counter_fallback)
2450 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
2452 rte_spinlock_lock(&pool->sl);
2454 * The single counters allocation may allocate smaller ID than the
2455 * current allocated in parallel to the host reading.
2456 * In this case the new counter values must be reported as 0.
2458 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
2462 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
2463 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
2465 rte_spinlock_unlock(&pool->sl);
2470 * Create and initialize a new counter pool.
2473 * Pointer to the Ethernet device structure.
2475 * The devX counter handle.
2477 * Whether the pool is for counter that was allocated by batch command.
2480 * A new pool pointer on success, NULL otherwise and rte_errno is set.
2482 static struct mlx5_flow_counter_pool *
2483 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
2486 struct mlx5_priv *priv = dev->data->dev_private;
2487 struct mlx5_flow_counter_pool *pool;
2488 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
2490 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
2493 if (cont->n == n_valid) {
2494 cont = flow_dv_container_resize(dev, batch);
2498 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
2499 sizeof(struct mlx5_flow_counter);
2500 pool = rte_calloc(__func__, 1, size, 0);
2505 pool->min_dcs = dcs;
2506 pool->raw = cont->init_mem_mng->raws + n_valid %
2507 MLX5_CNT_CONTAINER_RESIZE;
2508 pool->raw_hw = NULL;
2509 rte_spinlock_init(&pool->sl);
2511 * The generation of the new allocated counters in this pool is 0, 2 in
2512 * the pool generation makes all the counters valid for allocation.
2514 rte_atomic64_set(&pool->query_gen, 0x2);
2515 TAILQ_INIT(&pool->counters);
2516 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
2517 cont->pools[n_valid] = pool;
2518 /* Pool initialization must be updated before host thread access. */
2520 rte_atomic16_add(&cont->n_valid, 1);
2525 * Prepare a new counter and/or a new counter pool.
2528 * Pointer to the Ethernet device structure.
2529 * @param[out] cnt_free
2530 * Where to put the pointer of a new counter.
2532 * Whether the pool is for counter that was allocated by batch command.
2535 * The free counter pool pointer and @p cnt_free is set on success,
2536 * NULL otherwise and rte_errno is set.
2538 static struct mlx5_flow_counter_pool *
2539 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
2540 struct mlx5_flow_counter **cnt_free,
2543 struct mlx5_priv *priv = dev->data->dev_private;
2544 struct mlx5_flow_counter_pool *pool;
2545 struct mlx5_devx_obj *dcs = NULL;
2546 struct mlx5_flow_counter *cnt;
2550 /* bulk_bitmap must be 0 for single counter allocation. */
2551 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2554 pool = flow_dv_find_pool_by_id
2555 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
2557 pool = flow_dv_pool_create(dev, dcs, batch);
2559 mlx5_devx_cmd_destroy(dcs);
2562 } else if (dcs->id < pool->min_dcs->id) {
2563 rte_atomic64_set(&pool->a64_dcs,
2564 (int64_t)(uintptr_t)dcs);
2566 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
2567 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
2572 /* bulk_bitmap is in 128 counters units. */
2573 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
2574 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
2576 rte_errno = ENODATA;
2579 pool = flow_dv_pool_create(dev, dcs, batch);
2581 mlx5_devx_cmd_destroy(dcs);
2584 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
2585 cnt = &pool->counters_raw[i];
2587 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
2589 *cnt_free = &pool->counters_raw[0];
2594 * Search for existed shared counter.
2597 * Pointer to the relevant counter pool container.
2599 * The shared counter ID to search.
2602 * NULL if not existed, otherwise pointer to the shared counter.
2604 static struct mlx5_flow_counter *
2605 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
2608 static struct mlx5_flow_counter *cnt;
2609 struct mlx5_flow_counter_pool *pool;
2612 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2613 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
2614 cnt = &pool->counters_raw[i];
2615 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
2623 * Allocate a flow counter.
2626 * Pointer to the Ethernet device structure.
2628 * Indicate if this counter is shared with other flows.
2630 * Counter identifier.
2632 * Counter flow group.
2635 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2637 static struct mlx5_flow_counter *
2638 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
2641 struct mlx5_priv *priv = dev->data->dev_private;
2642 struct mlx5_flow_counter_pool *pool = NULL;
2643 struct mlx5_flow_counter *cnt_free = NULL;
2645 * Currently group 0 flow counter cannot be assigned to a flow if it is
2646 * not the first one in the batch counter allocation, so it is better
2647 * to allocate counters one by one for these flows in a separate
2649 * A counter can be shared between different groups so need to take
2650 * shared counters from the single container.
2652 uint32_t batch = (group && !shared) ? 1 : 0;
2653 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
2656 if (priv->counter_fallback)
2657 return flow_dv_counter_alloc_fallback(dev, shared, id);
2658 if (!priv->config.devx) {
2659 rte_errno = ENOTSUP;
2663 cnt_free = flow_dv_counter_shared_search(cont, id);
2665 if (cnt_free->ref_cnt + 1 == 0) {
2669 cnt_free->ref_cnt++;
2673 /* Pools which has a free counters are in the start. */
2674 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2676 * The free counter reset values must be updated between the
2677 * counter release to the counter allocation, so, at least one
2678 * query must be done in this time. ensure it by saving the
2679 * query generation in the release time.
2680 * The free list is sorted according to the generation - so if
2681 * the first one is not updated, all the others are not
2684 cnt_free = TAILQ_FIRST(&pool->counters);
2685 if (cnt_free && cnt_free->query_gen + 1 <
2686 rte_atomic64_read(&pool->query_gen))
2691 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
2695 cnt_free->batch = batch;
2696 /* Create a DV counter action only in the first time usage. */
2697 if (!cnt_free->action) {
2699 struct mlx5_devx_obj *dcs;
2702 offset = cnt_free - &pool->counters_raw[0];
2703 dcs = pool->min_dcs;
2706 dcs = cnt_free->dcs;
2708 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
2710 if (!cnt_free->action) {
2715 /* Update the counter reset values. */
2716 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
2719 cnt_free->shared = shared;
2720 cnt_free->ref_cnt = 1;
2722 if (!priv->sh->cmng.query_thread_on)
2723 /* Start the asynchronous batch query by the host thread. */
2724 mlx5_set_query_alarm(priv->sh);
2725 TAILQ_REMOVE(&pool->counters, cnt_free, next);
2726 if (TAILQ_EMPTY(&pool->counters)) {
2727 /* Move the pool to the end of the container pool list. */
2728 TAILQ_REMOVE(&cont->pool_list, pool, next);
2729 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
2735 * Release a flow counter.
2738 * Pointer to the Ethernet device structure.
2739 * @param[in] counter
2740 * Pointer to the counter handler.
2743 flow_dv_counter_release(struct rte_eth_dev *dev,
2744 struct mlx5_flow_counter *counter)
2746 struct mlx5_priv *priv = dev->data->dev_private;
2750 if (priv->counter_fallback) {
2751 flow_dv_counter_release_fallback(dev, counter);
2754 if (--counter->ref_cnt == 0) {
2755 struct mlx5_flow_counter_pool *pool =
2756 flow_dv_counter_pool_get(counter);
2758 /* Put the counter in the end - the last updated one. */
2759 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
2760 counter->query_gen = rte_atomic64_read(&pool->query_gen);
2765 * Verify the @p attributes will be correctly understood by the NIC and store
2766 * them in the @p flow if everything is correct.
2769 * Pointer to dev struct.
2770 * @param[in] attributes
2771 * Pointer to flow attributes
2773 * Pointer to error structure.
2776 * 0 on success, a negative errno value otherwise and rte_errno is set.
2779 flow_dv_validate_attributes(struct rte_eth_dev *dev,
2780 const struct rte_flow_attr *attributes,
2781 struct rte_flow_error *error)
2783 struct mlx5_priv *priv = dev->data->dev_private;
2784 uint32_t priority_max = priv->config.flow_prio - 1;
2786 #ifndef HAVE_MLX5DV_DR
2787 if (attributes->group)
2788 return rte_flow_error_set(error, ENOTSUP,
2789 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
2791 "groups is not supported");
2793 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
2794 attributes->priority >= priority_max)
2795 return rte_flow_error_set(error, ENOTSUP,
2796 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
2798 "priority out of range");
2799 if (attributes->transfer) {
2800 if (!priv->config.dv_esw_en)
2801 return rte_flow_error_set
2803 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2804 "E-Switch dr is not supported");
2805 if (!(priv->representor || priv->master))
2806 return rte_flow_error_set
2807 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2808 NULL, "E-Switch configurationd can only be"
2809 " done by a master or a representor device");
2810 if (attributes->egress)
2811 return rte_flow_error_set
2813 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
2814 "egress is not supported");
2815 if (attributes->group >= MLX5_MAX_TABLES_FDB)
2816 return rte_flow_error_set
2818 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
2819 NULL, "group must be smaller than "
2820 RTE_STR(MLX5_MAX_FDB_TABLES));
2822 if (!(attributes->egress ^ attributes->ingress))
2823 return rte_flow_error_set(error, ENOTSUP,
2824 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
2825 "must specify exactly one of "
2826 "ingress or egress");
2831 * Internal validation function. For validating both actions and items.
2834 * Pointer to the rte_eth_dev structure.
2836 * Pointer to the flow attributes.
2838 * Pointer to the list of items.
2839 * @param[in] actions
2840 * Pointer to the list of actions.
2842 * Pointer to the error structure.
2845 * 0 on success, a negative errno value otherwise and rte_errno is set.
2848 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
2849 const struct rte_flow_item items[],
2850 const struct rte_flow_action actions[],
2851 struct rte_flow_error *error)
2854 uint64_t action_flags = 0;
2855 uint64_t item_flags = 0;
2856 uint64_t last_item = 0;
2857 uint8_t next_protocol = 0xff;
2859 const struct rte_flow_item *gre_item = NULL;
2860 struct rte_flow_item_tcp nic_tcp_mask = {
2863 .src_port = RTE_BE16(UINT16_MAX),
2864 .dst_port = RTE_BE16(UINT16_MAX),
2870 ret = flow_dv_validate_attributes(dev, attr, error);
2873 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2874 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2875 switch (items->type) {
2876 case RTE_FLOW_ITEM_TYPE_VOID:
2878 case RTE_FLOW_ITEM_TYPE_PORT_ID:
2879 ret = flow_dv_validate_item_port_id
2880 (dev, items, attr, item_flags, error);
2883 last_item = MLX5_FLOW_ITEM_PORT_ID;
2885 case RTE_FLOW_ITEM_TYPE_ETH:
2886 ret = mlx5_flow_validate_item_eth(items, item_flags,
2890 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
2891 MLX5_FLOW_LAYER_OUTER_L2;
2893 case RTE_FLOW_ITEM_TYPE_VLAN:
2894 ret = mlx5_flow_validate_item_vlan(items, item_flags,
2898 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2899 MLX5_FLOW_LAYER_OUTER_VLAN;
2901 case RTE_FLOW_ITEM_TYPE_IPV4:
2902 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
2906 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
2907 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
2908 if (items->mask != NULL &&
2909 ((const struct rte_flow_item_ipv4 *)
2910 items->mask)->hdr.next_proto_id) {
2912 ((const struct rte_flow_item_ipv4 *)
2913 (items->spec))->hdr.next_proto_id;
2915 ((const struct rte_flow_item_ipv4 *)
2916 (items->mask))->hdr.next_proto_id;
2918 /* Reset for inner layer. */
2919 next_protocol = 0xff;
2921 mlx5_flow_tunnel_ip_check(items, &last_item);
2923 case RTE_FLOW_ITEM_TYPE_IPV6:
2924 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
2928 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
2929 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
2930 if (items->mask != NULL &&
2931 ((const struct rte_flow_item_ipv6 *)
2932 items->mask)->hdr.proto) {
2934 ((const struct rte_flow_item_ipv6 *)
2935 items->spec)->hdr.proto;
2937 ((const struct rte_flow_item_ipv6 *)
2938 items->mask)->hdr.proto;
2940 /* Reset for inner layer. */
2941 next_protocol = 0xff;
2943 mlx5_flow_tunnel_ip_check(items, &last_item);
2945 case RTE_FLOW_ITEM_TYPE_TCP:
2946 ret = mlx5_flow_validate_item_tcp
2953 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
2954 MLX5_FLOW_LAYER_OUTER_L4_TCP;
2956 case RTE_FLOW_ITEM_TYPE_UDP:
2957 ret = mlx5_flow_validate_item_udp(items, item_flags,
2962 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
2963 MLX5_FLOW_LAYER_OUTER_L4_UDP;
2965 case RTE_FLOW_ITEM_TYPE_GRE:
2966 ret = mlx5_flow_validate_item_gre(items, item_flags,
2967 next_protocol, error);
2971 last_item = MLX5_FLOW_LAYER_GRE;
2973 case RTE_FLOW_ITEM_TYPE_NVGRE:
2974 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
2979 last_item = MLX5_FLOW_LAYER_NVGRE;
2981 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
2982 ret = mlx5_flow_validate_item_gre_key
2983 (items, item_flags, gre_item, error);
2986 last_item = MLX5_FLOW_LAYER_GRE_KEY;
2988 case RTE_FLOW_ITEM_TYPE_VXLAN:
2989 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
2993 last_item = MLX5_FLOW_LAYER_VXLAN;
2995 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2996 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3001 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3003 case RTE_FLOW_ITEM_TYPE_MPLS:
3004 ret = mlx5_flow_validate_item_mpls(dev, items,
3009 last_item = MLX5_FLOW_LAYER_MPLS;
3011 case RTE_FLOW_ITEM_TYPE_META:
3012 ret = flow_dv_validate_item_meta(dev, items, attr,
3016 last_item = MLX5_FLOW_ITEM_METADATA;
3018 case RTE_FLOW_ITEM_TYPE_ICMP:
3019 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3024 last_item = MLX5_FLOW_LAYER_ICMP;
3026 case RTE_FLOW_ITEM_TYPE_ICMP6:
3027 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3032 last_item = MLX5_FLOW_LAYER_ICMP6;
3035 return rte_flow_error_set(error, ENOTSUP,
3036 RTE_FLOW_ERROR_TYPE_ITEM,
3037 NULL, "item not supported");
3039 item_flags |= last_item;
3041 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3042 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3043 return rte_flow_error_set(error, ENOTSUP,
3044 RTE_FLOW_ERROR_TYPE_ACTION,
3045 actions, "too many actions");
3046 switch (actions->type) {
3047 case RTE_FLOW_ACTION_TYPE_VOID:
3049 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3050 ret = flow_dv_validate_action_port_id(dev,
3057 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3060 case RTE_FLOW_ACTION_TYPE_FLAG:
3061 ret = mlx5_flow_validate_action_flag(action_flags,
3065 action_flags |= MLX5_FLOW_ACTION_FLAG;
3068 case RTE_FLOW_ACTION_TYPE_MARK:
3069 ret = mlx5_flow_validate_action_mark(actions,
3074 action_flags |= MLX5_FLOW_ACTION_MARK;
3077 case RTE_FLOW_ACTION_TYPE_DROP:
3078 ret = mlx5_flow_validate_action_drop(action_flags,
3082 action_flags |= MLX5_FLOW_ACTION_DROP;
3085 case RTE_FLOW_ACTION_TYPE_QUEUE:
3086 ret = mlx5_flow_validate_action_queue(actions,
3091 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3094 case RTE_FLOW_ACTION_TYPE_RSS:
3095 ret = mlx5_flow_validate_action_rss(actions,
3101 action_flags |= MLX5_FLOW_ACTION_RSS;
3104 case RTE_FLOW_ACTION_TYPE_COUNT:
3105 ret = flow_dv_validate_action_count(dev, error);
3108 action_flags |= MLX5_FLOW_ACTION_COUNT;
3111 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3112 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3113 ret = flow_dv_validate_action_l2_encap(action_flags,
3118 action_flags |= actions->type ==
3119 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3120 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3121 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3124 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3125 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3126 ret = flow_dv_validate_action_l2_decap(action_flags,
3130 action_flags |= actions->type ==
3131 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3132 MLX5_FLOW_ACTION_VXLAN_DECAP :
3133 MLX5_FLOW_ACTION_NVGRE_DECAP;
3136 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3137 ret = flow_dv_validate_action_raw_encap(action_flags,
3142 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3145 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3146 ret = flow_dv_validate_action_raw_decap(action_flags,
3151 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3154 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3155 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3156 ret = flow_dv_validate_action_modify_mac(action_flags,
3162 /* Count all modify-header actions as one action. */
3163 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3165 action_flags |= actions->type ==
3166 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3167 MLX5_FLOW_ACTION_SET_MAC_SRC :
3168 MLX5_FLOW_ACTION_SET_MAC_DST;
3171 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3172 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3173 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3179 /* Count all modify-header actions as one action. */
3180 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3182 action_flags |= actions->type ==
3183 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3184 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3185 MLX5_FLOW_ACTION_SET_IPV4_DST;
3187 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3188 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3189 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3195 /* Count all modify-header actions as one action. */
3196 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3198 action_flags |= actions->type ==
3199 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3200 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3201 MLX5_FLOW_ACTION_SET_IPV6_DST;
3203 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3204 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3205 ret = flow_dv_validate_action_modify_tp(action_flags,
3211 /* Count all modify-header actions as one action. */
3212 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3214 action_flags |= actions->type ==
3215 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3216 MLX5_FLOW_ACTION_SET_TP_SRC :
3217 MLX5_FLOW_ACTION_SET_TP_DST;
3219 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3220 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3221 ret = flow_dv_validate_action_modify_ttl(action_flags,
3227 /* Count all modify-header actions as one action. */
3228 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3230 action_flags |= actions->type ==
3231 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3232 MLX5_FLOW_ACTION_SET_TTL :
3233 MLX5_FLOW_ACTION_DEC_TTL;
3235 case RTE_FLOW_ACTION_TYPE_JUMP:
3236 ret = flow_dv_validate_action_jump(actions,
3237 attr->group, error);
3241 action_flags |= MLX5_FLOW_ACTION_JUMP;
3243 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3244 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3245 ret = flow_dv_validate_action_modify_tcp_seq
3252 /* Count all modify-header actions as one action. */
3253 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3255 action_flags |= actions->type ==
3256 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3257 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3258 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3260 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3261 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3262 ret = flow_dv_validate_action_modify_tcp_ack
3269 /* Count all modify-header actions as one action. */
3270 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3272 action_flags |= actions->type ==
3273 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3274 MLX5_FLOW_ACTION_INC_TCP_ACK :
3275 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3278 return rte_flow_error_set(error, ENOTSUP,
3279 RTE_FLOW_ERROR_TYPE_ACTION,
3281 "action not supported");
3284 /* Eswitch has few restrictions on using items and actions */
3285 if (attr->transfer) {
3286 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3287 return rte_flow_error_set(error, ENOTSUP,
3288 RTE_FLOW_ERROR_TYPE_ACTION,
3290 "unsupported action FLAG");
3291 if (action_flags & MLX5_FLOW_ACTION_MARK)
3292 return rte_flow_error_set(error, ENOTSUP,
3293 RTE_FLOW_ERROR_TYPE_ACTION,
3295 "unsupported action MARK");
3296 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
3297 return rte_flow_error_set(error, ENOTSUP,
3298 RTE_FLOW_ERROR_TYPE_ACTION,
3300 "unsupported action QUEUE");
3301 if (action_flags & MLX5_FLOW_ACTION_RSS)
3302 return rte_flow_error_set(error, ENOTSUP,
3303 RTE_FLOW_ERROR_TYPE_ACTION,
3305 "unsupported action RSS");
3306 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3307 return rte_flow_error_set(error, EINVAL,
3308 RTE_FLOW_ERROR_TYPE_ACTION,
3310 "no fate action is found");
3312 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
3313 return rte_flow_error_set(error, EINVAL,
3314 RTE_FLOW_ERROR_TYPE_ACTION,
3316 "no fate action is found");
3322 * Internal preparation function. Allocates the DV flow size,
3323 * this size is constant.
3326 * Pointer to the flow attributes.
3328 * Pointer to the list of items.
3329 * @param[in] actions
3330 * Pointer to the list of actions.
3332 * Pointer to the error structure.
3335 * Pointer to mlx5_flow object on success,
3336 * otherwise NULL and rte_errno is set.
3338 static struct mlx5_flow *
3339 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
3340 const struct rte_flow_item items[] __rte_unused,
3341 const struct rte_flow_action actions[] __rte_unused,
3342 struct rte_flow_error *error)
3344 uint32_t size = sizeof(struct mlx5_flow);
3345 struct mlx5_flow *flow;
3347 flow = rte_calloc(__func__, 1, size, 0);
3349 rte_flow_error_set(error, ENOMEM,
3350 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3351 "not enough memory to create flow");
3354 flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
3360 * Sanity check for match mask and value. Similar to check_valid_spec() in
3361 * kernel driver. If unmasked bit is present in value, it returns failure.
3364 * pointer to match mask buffer.
3365 * @param match_value
3366 * pointer to match value buffer.
3369 * 0 if valid, -EINVAL otherwise.
3372 flow_dv_check_valid_spec(void *match_mask, void *match_value)
3374 uint8_t *m = match_mask;
3375 uint8_t *v = match_value;
3378 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
3381 "match_value differs from match_criteria"
3382 " %p[%u] != %p[%u]",
3383 match_value, i, match_mask, i);
3392 * Add Ethernet item to matcher and to the value.
3394 * @param[in, out] matcher
3396 * @param[in, out] key
3397 * Flow matcher value.
3399 * Flow pattern to translate.
3401 * Item is inner pattern.
3404 flow_dv_translate_item_eth(void *matcher, void *key,
3405 const struct rte_flow_item *item, int inner)
3407 const struct rte_flow_item_eth *eth_m = item->mask;
3408 const struct rte_flow_item_eth *eth_v = item->spec;
3409 const struct rte_flow_item_eth nic_mask = {
3410 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3411 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3412 .type = RTE_BE16(0xffff),
3424 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3426 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3428 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3430 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3432 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
3433 ð_m->dst, sizeof(eth_m->dst));
3434 /* The value must be in the range of the mask. */
3435 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
3436 for (i = 0; i < sizeof(eth_m->dst); ++i)
3437 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
3438 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
3439 ð_m->src, sizeof(eth_m->src));
3440 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
3441 /* The value must be in the range of the mask. */
3442 for (i = 0; i < sizeof(eth_m->dst); ++i)
3443 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
3444 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
3445 rte_be_to_cpu_16(eth_m->type));
3446 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
3447 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
3451 * Add VLAN item to matcher and to the value.
3453 * @param[in, out] matcher
3455 * @param[in, out] key
3456 * Flow matcher value.
3458 * Flow pattern to translate.
3460 * Item is inner pattern.
3463 flow_dv_translate_item_vlan(void *matcher, void *key,
3464 const struct rte_flow_item *item,
3467 const struct rte_flow_item_vlan *vlan_m = item->mask;
3468 const struct rte_flow_item_vlan *vlan_v = item->spec;
3469 const struct rte_flow_item_vlan nic_mask = {
3470 .tci = RTE_BE16(0x0fff),
3471 .inner_type = RTE_BE16(0xffff),
3483 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3485 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3487 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3489 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3491 tci_m = rte_be_to_cpu_16(vlan_m->tci);
3492 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
3493 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
3494 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
3495 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
3496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
3497 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
3498 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
3499 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
3500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
3504 * Add IPV4 item to matcher and to the value.
3506 * @param[in, out] matcher
3508 * @param[in, out] key
3509 * Flow matcher value.
3511 * Flow pattern to translate.
3513 * Item is inner pattern.
3515 * The group to insert the rule.
3518 flow_dv_translate_item_ipv4(void *matcher, void *key,
3519 const struct rte_flow_item *item,
3520 int inner, uint32_t group)
3522 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
3523 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
3524 const struct rte_flow_item_ipv4 nic_mask = {
3526 .src_addr = RTE_BE32(0xffffffff),
3527 .dst_addr = RTE_BE32(0xffffffff),
3528 .type_of_service = 0xff,
3529 .next_proto_id = 0xff,
3539 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3541 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3543 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3545 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3548 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
3550 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
3551 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
3556 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3557 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3558 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3559 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3560 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
3561 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
3562 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3563 src_ipv4_src_ipv6.ipv4_layout.ipv4);
3564 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3565 src_ipv4_src_ipv6.ipv4_layout.ipv4);
3566 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
3567 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
3568 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
3569 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
3570 ipv4_m->hdr.type_of_service);
3571 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
3572 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
3573 ipv4_m->hdr.type_of_service >> 2);
3574 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
3575 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
3576 ipv4_m->hdr.next_proto_id);
3577 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
3578 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
3582 * Add IPV6 item to matcher and to the value.
3584 * @param[in, out] matcher
3586 * @param[in, out] key
3587 * Flow matcher value.
3589 * Flow pattern to translate.
3591 * Item is inner pattern.
3593 * The group to insert the rule.
3596 flow_dv_translate_item_ipv6(void *matcher, void *key,
3597 const struct rte_flow_item *item,
3598 int inner, uint32_t group)
3600 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
3601 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
3602 const struct rte_flow_item_ipv6 nic_mask = {
3605 "\xff\xff\xff\xff\xff\xff\xff\xff"
3606 "\xff\xff\xff\xff\xff\xff\xff\xff",
3608 "\xff\xff\xff\xff\xff\xff\xff\xff"
3609 "\xff\xff\xff\xff\xff\xff\xff\xff",
3610 .vtc_flow = RTE_BE32(0xffffffff),
3617 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3618 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3627 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3629 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3631 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3633 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3636 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
3638 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
3639 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
3644 size = sizeof(ipv6_m->hdr.dst_addr);
3645 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3646 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
3647 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3648 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
3649 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
3650 for (i = 0; i < size; ++i)
3651 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
3652 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3653 src_ipv4_src_ipv6.ipv6_layout.ipv6);
3654 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3655 src_ipv4_src_ipv6.ipv6_layout.ipv6);
3656 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
3657 for (i = 0; i < size; ++i)
3658 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
3660 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
3661 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
3662 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
3663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
3664 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
3665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
3668 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
3670 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
3673 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
3675 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
3679 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
3681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
3682 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
3686 * Add TCP item to matcher and to the value.
3688 * @param[in, out] matcher
3690 * @param[in, out] key
3691 * Flow matcher value.
3693 * Flow pattern to translate.
3695 * Item is inner pattern.
3698 flow_dv_translate_item_tcp(void *matcher, void *key,
3699 const struct rte_flow_item *item,
3702 const struct rte_flow_item_tcp *tcp_m = item->mask;
3703 const struct rte_flow_item_tcp *tcp_v = item->spec;
3708 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3710 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3712 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3714 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3716 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
3717 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
3721 tcp_m = &rte_flow_item_tcp_mask;
3722 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
3723 rte_be_to_cpu_16(tcp_m->hdr.src_port));
3724 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
3725 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
3726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
3727 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
3728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
3729 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
3730 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
3731 tcp_m->hdr.tcp_flags);
3732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
3733 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
3737 * Add UDP item to matcher and to the value.
3739 * @param[in, out] matcher
3741 * @param[in, out] key
3742 * Flow matcher value.
3744 * Flow pattern to translate.
3746 * Item is inner pattern.
3749 flow_dv_translate_item_udp(void *matcher, void *key,
3750 const struct rte_flow_item *item,
3753 const struct rte_flow_item_udp *udp_m = item->mask;
3754 const struct rte_flow_item_udp *udp_v = item->spec;
3759 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3761 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3763 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3765 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3767 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
3768 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
3772 udp_m = &rte_flow_item_udp_mask;
3773 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
3774 rte_be_to_cpu_16(udp_m->hdr.src_port));
3775 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
3776 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
3777 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
3778 rte_be_to_cpu_16(udp_m->hdr.dst_port));
3779 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
3780 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
3784 * Add GRE optional Key item to matcher and to the value.
3786 * @param[in, out] matcher
3788 * @param[in, out] key
3789 * Flow matcher value.
3791 * Flow pattern to translate.
3793 * Item is inner pattern.
3796 flow_dv_translate_item_gre_key(void *matcher, void *key,
3797 const struct rte_flow_item *item)
3799 const rte_be32_t *key_m = item->mask;
3800 const rte_be32_t *key_v = item->spec;
3801 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3802 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3803 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
3808 key_m = &gre_key_default_mask;
3809 /* GRE K bit must be on and should already be validated */
3810 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
3811 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
3812 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
3813 rte_be_to_cpu_32(*key_m) >> 8);
3814 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
3815 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
3816 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
3817 rte_be_to_cpu_32(*key_m) & 0xFF);
3818 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
3819 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
3823 * Add GRE item to matcher and to the value.
3825 * @param[in, out] matcher
3827 * @param[in, out] key
3828 * Flow matcher value.
3830 * Flow pattern to translate.
3832 * Item is inner pattern.
3835 flow_dv_translate_item_gre(void *matcher, void *key,
3836 const struct rte_flow_item *item,
3839 const struct rte_flow_item_gre *gre_m = item->mask;
3840 const struct rte_flow_item_gre *gre_v = item->spec;
3843 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3844 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3851 uint16_t s_present:1;
3852 uint16_t k_present:1;
3853 uint16_t rsvd_bit1:1;
3854 uint16_t c_present:1;
3858 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
3861 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3863 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3865 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3867 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3869 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
3870 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
3874 gre_m = &rte_flow_item_gre_mask;
3875 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
3876 rte_be_to_cpu_16(gre_m->protocol));
3877 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
3878 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
3879 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
3880 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
3881 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
3882 gre_crks_rsvd0_ver_m.c_present);
3883 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
3884 gre_crks_rsvd0_ver_v.c_present &
3885 gre_crks_rsvd0_ver_m.c_present);
3886 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
3887 gre_crks_rsvd0_ver_m.k_present);
3888 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
3889 gre_crks_rsvd0_ver_v.k_present &
3890 gre_crks_rsvd0_ver_m.k_present);
3891 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
3892 gre_crks_rsvd0_ver_m.s_present);
3893 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
3894 gre_crks_rsvd0_ver_v.s_present &
3895 gre_crks_rsvd0_ver_m.s_present);
3899 * Add NVGRE item to matcher and to the value.
3901 * @param[in, out] matcher
3903 * @param[in, out] key
3904 * Flow matcher value.
3906 * Flow pattern to translate.
3908 * Item is inner pattern.
3911 flow_dv_translate_item_nvgre(void *matcher, void *key,
3912 const struct rte_flow_item *item,
3915 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
3916 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
3917 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3918 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3919 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
3920 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
3926 /* For NVGRE, GRE header fields must be set with defined values. */
3927 const struct rte_flow_item_gre gre_spec = {
3928 .c_rsvd0_ver = RTE_BE16(0x2000),
3929 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
3931 const struct rte_flow_item_gre gre_mask = {
3932 .c_rsvd0_ver = RTE_BE16(0xB000),
3933 .protocol = RTE_BE16(UINT16_MAX),
3935 const struct rte_flow_item gre_item = {
3940 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
3944 nvgre_m = &rte_flow_item_nvgre_mask;
3945 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
3946 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
3947 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
3948 memcpy(gre_key_m, tni_flow_id_m, size);
3949 for (i = 0; i < size; ++i)
3950 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
3954 * Add VXLAN item to matcher and to the value.
3956 * @param[in, out] matcher
3958 * @param[in, out] key
3959 * Flow matcher value.
3961 * Flow pattern to translate.
3963 * Item is inner pattern.
3966 flow_dv_translate_item_vxlan(void *matcher, void *key,
3967 const struct rte_flow_item *item,
3970 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
3971 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
3974 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3975 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3983 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3985 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3987 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3989 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3991 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
3992 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
3993 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
3994 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
3995 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4000 vxlan_m = &rte_flow_item_vxlan_mask;
4001 size = sizeof(vxlan_m->vni);
4002 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4003 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4004 memcpy(vni_m, vxlan_m->vni, size);
4005 for (i = 0; i < size; ++i)
4006 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4010 * Add MPLS item to matcher and to the value.
4012 * @param[in, out] matcher
4014 * @param[in, out] key
4015 * Flow matcher value.
4017 * Flow pattern to translate.
4018 * @param[in] prev_layer
4019 * The protocol layer indicated in previous item.
4021 * Item is inner pattern.
4024 flow_dv_translate_item_mpls(void *matcher, void *key,
4025 const struct rte_flow_item *item,
4026 uint64_t prev_layer,
4029 const uint32_t *in_mpls_m = item->mask;
4030 const uint32_t *in_mpls_v = item->spec;
4031 uint32_t *out_mpls_m = 0;
4032 uint32_t *out_mpls_v = 0;
4033 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4034 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4035 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4037 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4038 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4039 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4041 switch (prev_layer) {
4042 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4043 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4044 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4045 MLX5_UDP_PORT_MPLS);
4047 case MLX5_FLOW_LAYER_GRE:
4048 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4049 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4050 RTE_ETHER_TYPE_MPLS);
4053 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4054 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4061 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4062 switch (prev_layer) {
4063 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4065 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4066 outer_first_mpls_over_udp);
4068 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4069 outer_first_mpls_over_udp);
4071 case MLX5_FLOW_LAYER_GRE:
4073 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4074 outer_first_mpls_over_gre);
4076 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4077 outer_first_mpls_over_gre);
4080 /* Inner MPLS not over GRE is not supported. */
4083 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4087 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4093 if (out_mpls_m && out_mpls_v) {
4094 *out_mpls_m = *in_mpls_m;
4095 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4100 * Add META item to matcher
4102 * @param[in, out] matcher
4104 * @param[in, out] key
4105 * Flow matcher value.
4107 * Flow pattern to translate.
4109 * Item is inner pattern.
4112 flow_dv_translate_item_meta(void *matcher, void *key,
4113 const struct rte_flow_item *item)
4115 const struct rte_flow_item_meta *meta_m;
4116 const struct rte_flow_item_meta *meta_v;
4118 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4120 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4122 meta_m = (const void *)item->mask;
4124 meta_m = &rte_flow_item_meta_mask;
4125 meta_v = (const void *)item->spec;
4127 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4128 rte_be_to_cpu_32(meta_m->data));
4129 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4130 rte_be_to_cpu_32(meta_v->data & meta_m->data));
4135 * Add source vport match to the specified matcher.
4137 * @param[in, out] matcher
4139 * @param[in, out] key
4140 * Flow matcher value.
4142 * Source vport value to match
4147 flow_dv_translate_item_source_vport(void *matcher, void *key,
4148 int16_t port, uint16_t mask)
4150 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4151 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4153 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
4154 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
4158 * Translate port-id item to eswitch match on port-id.
4161 * The devich to configure through.
4162 * @param[in, out] matcher
4164 * @param[in, out] key
4165 * Flow matcher value.
4167 * Flow pattern to translate.
4170 * 0 on success, a negative errno value otherwise.
4173 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
4174 void *key, const struct rte_flow_item *item)
4176 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
4177 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
4178 uint16_t mask, val, id;
4181 mask = pid_m ? pid_m->id : 0xffff;
4182 id = pid_v ? pid_v->id : dev->data->port_id;
4183 ret = mlx5_port_to_eswitch_info(id, NULL, &val);
4186 flow_dv_translate_item_source_vport(matcher, key, val, mask);
4191 * Add ICMP6 item to matcher and to the value.
4193 * @param[in, out] matcher
4195 * @param[in, out] key
4196 * Flow matcher value.
4198 * Flow pattern to translate.
4200 * Item is inner pattern.
4203 flow_dv_translate_item_icmp6(void *matcher, void *key,
4204 const struct rte_flow_item *item,
4207 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
4208 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
4211 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4213 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4215 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4217 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4219 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4221 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4223 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4224 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
4228 icmp6_m = &rte_flow_item_icmp6_mask;
4229 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
4230 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
4231 icmp6_v->type & icmp6_m->type);
4232 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
4233 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
4234 icmp6_v->code & icmp6_m->code);
4238 * Add ICMP item to matcher and to the value.
4240 * @param[in, out] matcher
4242 * @param[in, out] key
4243 * Flow matcher value.
4245 * Flow pattern to translate.
4247 * Item is inner pattern.
4250 flow_dv_translate_item_icmp(void *matcher, void *key,
4251 const struct rte_flow_item *item,
4254 const struct rte_flow_item_icmp *icmp_m = item->mask;
4255 const struct rte_flow_item_icmp *icmp_v = item->spec;
4258 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4260 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4262 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4264 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4266 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4268 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4270 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4271 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
4275 icmp_m = &rte_flow_item_icmp_mask;
4276 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
4277 icmp_m->hdr.icmp_type);
4278 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
4279 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
4280 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
4281 icmp_m->hdr.icmp_code);
4282 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
4283 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
4286 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
4288 #define HEADER_IS_ZERO(match_criteria, headers) \
4289 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
4290 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
4293 * Calculate flow matcher enable bitmap.
4295 * @param match_criteria
4296 * Pointer to flow matcher criteria.
4299 * Bitmap of enabled fields.
4302 flow_dv_matcher_enable(uint32_t *match_criteria)
4304 uint8_t match_criteria_enable;
4306 match_criteria_enable =
4307 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
4308 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
4309 match_criteria_enable |=
4310 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
4311 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
4312 match_criteria_enable |=
4313 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
4314 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
4315 match_criteria_enable |=
4316 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
4317 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
4318 #ifdef HAVE_MLX5DV_DR
4319 match_criteria_enable |=
4320 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
4321 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
4323 return match_criteria_enable;
4330 * @param dev[in, out]
4331 * Pointer to rte_eth_dev structure.
4332 * @param[in] table_id
4335 * Direction of the table.
4336 * @param[in] transfer
4337 * E-Switch or NIC flow.
4339 * pointer to error structure.
4342 * Returns tables resource based on the index, NULL in case of failed.
4344 static struct mlx5_flow_tbl_resource *
4345 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
4346 uint32_t table_id, uint8_t egress,
4348 struct rte_flow_error *error)
4350 struct mlx5_priv *priv = dev->data->dev_private;
4351 struct mlx5_ibv_shared *sh = priv->sh;
4352 struct mlx5_flow_tbl_resource *tbl;
4354 #ifdef HAVE_MLX5DV_DR
4356 tbl = &sh->fdb_tbl[table_id];
4358 tbl->obj = mlx5_glue->dr_create_flow_tbl
4359 (sh->fdb_domain, table_id);
4360 } else if (egress) {
4361 tbl = &sh->tx_tbl[table_id];
4363 tbl->obj = mlx5_glue->dr_create_flow_tbl
4364 (sh->tx_domain, table_id);
4366 tbl = &sh->rx_tbl[table_id];
4368 tbl->obj = mlx5_glue->dr_create_flow_tbl
4369 (sh->rx_domain, table_id);
4372 rte_flow_error_set(error, ENOMEM,
4373 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4374 NULL, "cannot create table");
4377 rte_atomic32_inc(&tbl->refcnt);
4383 return &sh->fdb_tbl[table_id];
4385 return &sh->tx_tbl[table_id];
4387 return &sh->rx_tbl[table_id];
4392 * Release a flow table.
4395 * Table resource to be released.
4398 * Returns 0 if table was released, else return 1;
4401 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
4405 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
4406 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
4414 * Register the flow matcher.
4416 * @param dev[in, out]
4417 * Pointer to rte_eth_dev structure.
4418 * @param[in, out] matcher
4419 * Pointer to flow matcher.
4420 * @parm[in, out] dev_flow
4421 * Pointer to the dev_flow.
4423 * pointer to error structure.
4426 * 0 on success otherwise -errno and errno is set.
4429 flow_dv_matcher_register(struct rte_eth_dev *dev,
4430 struct mlx5_flow_dv_matcher *matcher,
4431 struct mlx5_flow *dev_flow,
4432 struct rte_flow_error *error)
4434 struct mlx5_priv *priv = dev->data->dev_private;
4435 struct mlx5_ibv_shared *sh = priv->sh;
4436 struct mlx5_flow_dv_matcher *cache_matcher;
4437 struct mlx5dv_flow_matcher_attr dv_attr = {
4438 .type = IBV_FLOW_ATTR_NORMAL,
4439 .match_mask = (void *)&matcher->mask,
4441 struct mlx5_flow_tbl_resource *tbl = NULL;
4443 /* Lookup from cache. */
4444 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
4445 if (matcher->crc == cache_matcher->crc &&
4446 matcher->priority == cache_matcher->priority &&
4447 matcher->egress == cache_matcher->egress &&
4448 matcher->group == cache_matcher->group &&
4449 matcher->transfer == cache_matcher->transfer &&
4450 !memcmp((const void *)matcher->mask.buf,
4451 (const void *)cache_matcher->mask.buf,
4452 cache_matcher->mask.size)) {
4454 "priority %hd use %s matcher %p: refcnt %d++",
4455 cache_matcher->priority,
4456 cache_matcher->egress ? "tx" : "rx",
4457 (void *)cache_matcher,
4458 rte_atomic32_read(&cache_matcher->refcnt));
4459 rte_atomic32_inc(&cache_matcher->refcnt);
4460 dev_flow->dv.matcher = cache_matcher;
4464 /* Register new matcher. */
4465 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
4467 return rte_flow_error_set(error, ENOMEM,
4468 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4469 "cannot allocate matcher memory");
4470 tbl = flow_dv_tbl_resource_get(dev, matcher->group * MLX5_GROUP_FACTOR,
4471 matcher->egress, matcher->transfer,
4474 rte_free(cache_matcher);
4475 return rte_flow_error_set(error, ENOMEM,
4476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4477 NULL, "cannot create table");
4479 *cache_matcher = *matcher;
4480 dv_attr.match_criteria_enable =
4481 flow_dv_matcher_enable(cache_matcher->mask.buf);
4482 dv_attr.priority = matcher->priority;
4483 if (matcher->egress)
4484 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
4485 cache_matcher->matcher_object =
4486 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
4487 if (!cache_matcher->matcher_object) {
4488 rte_free(cache_matcher);
4489 #ifdef HAVE_MLX5DV_DR
4490 flow_dv_tbl_resource_release(tbl);
4492 return rte_flow_error_set(error, ENOMEM,
4493 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4494 NULL, "cannot create matcher");
4496 rte_atomic32_inc(&cache_matcher->refcnt);
4497 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
4498 dev_flow->dv.matcher = cache_matcher;
4499 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
4500 cache_matcher->priority,
4501 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
4502 rte_atomic32_read(&cache_matcher->refcnt));
4503 rte_atomic32_inc(&tbl->refcnt);
4508 * Find existing tag resource or create and register a new one.
4510 * @param dev[in, out]
4511 * Pointer to rte_eth_dev structure.
4512 * @param[in, out] resource
4513 * Pointer to tag resource.
4514 * @parm[in, out] dev_flow
4515 * Pointer to the dev_flow.
4517 * pointer to error structure.
4520 * 0 on success otherwise -errno and errno is set.
4523 flow_dv_tag_resource_register
4524 (struct rte_eth_dev *dev,
4525 struct mlx5_flow_dv_tag_resource *resource,
4526 struct mlx5_flow *dev_flow,
4527 struct rte_flow_error *error)
4529 struct mlx5_priv *priv = dev->data->dev_private;
4530 struct mlx5_ibv_shared *sh = priv->sh;
4531 struct mlx5_flow_dv_tag_resource *cache_resource;
4533 /* Lookup a matching resource from cache. */
4534 LIST_FOREACH(cache_resource, &sh->tags, next) {
4535 if (resource->tag == cache_resource->tag) {
4536 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
4537 (void *)cache_resource,
4538 rte_atomic32_read(&cache_resource->refcnt));
4539 rte_atomic32_inc(&cache_resource->refcnt);
4540 dev_flow->flow->tag_resource = cache_resource;
4544 /* Register new resource. */
4545 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
4546 if (!cache_resource)
4547 return rte_flow_error_set(error, ENOMEM,
4548 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4549 "cannot allocate resource memory");
4550 *cache_resource = *resource;
4551 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
4553 if (!cache_resource->action) {
4554 rte_free(cache_resource);
4555 return rte_flow_error_set(error, ENOMEM,
4556 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4557 NULL, "cannot create action");
4559 rte_atomic32_init(&cache_resource->refcnt);
4560 rte_atomic32_inc(&cache_resource->refcnt);
4561 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
4562 dev_flow->flow->tag_resource = cache_resource;
4563 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
4564 (void *)cache_resource,
4565 rte_atomic32_read(&cache_resource->refcnt));
4573 * Pointer to Ethernet device.
4575 * Pointer to mlx5_flow.
4578 * 1 while a reference on it exists, 0 when freed.
4581 flow_dv_tag_release(struct rte_eth_dev *dev,
4582 struct mlx5_flow_dv_tag_resource *tag)
4585 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
4586 dev->data->port_id, (void *)tag,
4587 rte_atomic32_read(&tag->refcnt));
4588 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
4589 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
4590 LIST_REMOVE(tag, next);
4591 DRV_LOG(DEBUG, "port %u tag %p: removed",
4592 dev->data->port_id, (void *)tag);
4600 * Translate port ID action to vport.
4603 * Pointer to rte_eth_dev structure.
4605 * Pointer to the port ID action.
4606 * @param[out] dst_port_id
4607 * The target port ID.
4609 * Pointer to the error structure.
4612 * 0 on success, a negative errno value otherwise and rte_errno is set.
4615 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
4616 const struct rte_flow_action *action,
4617 uint32_t *dst_port_id,
4618 struct rte_flow_error *error)
4623 const struct rte_flow_action_port_id *conf =
4624 (const struct rte_flow_action_port_id *)action->conf;
4626 port = conf->original ? dev->data->port_id : conf->id;
4627 ret = mlx5_port_to_eswitch_info(port, NULL, &port_id);
4629 return rte_flow_error_set(error, -ret,
4630 RTE_FLOW_ERROR_TYPE_ACTION,
4632 "No eswitch info was found for port");
4633 *dst_port_id = port_id;
4638 * Fill the flow with DV spec.
4641 * Pointer to rte_eth_dev structure.
4642 * @param[in, out] dev_flow
4643 * Pointer to the sub flow.
4645 * Pointer to the flow attributes.
4647 * Pointer to the list of items.
4648 * @param[in] actions
4649 * Pointer to the list of actions.
4651 * Pointer to the error structure.
4654 * 0 on success, a negative errno value otherwise and rte_errno is set.
4657 flow_dv_translate(struct rte_eth_dev *dev,
4658 struct mlx5_flow *dev_flow,
4659 const struct rte_flow_attr *attr,
4660 const struct rte_flow_item items[],
4661 const struct rte_flow_action actions[],
4662 struct rte_flow_error *error)
4664 struct mlx5_priv *priv = dev->data->dev_private;
4665 struct rte_flow *flow = dev_flow->flow;
4666 uint64_t item_flags = 0;
4667 uint64_t last_item = 0;
4668 uint64_t action_flags = 0;
4669 uint64_t priority = attr->priority;
4670 struct mlx5_flow_dv_matcher matcher = {
4672 .size = sizeof(matcher.mask.buf),
4676 bool actions_end = false;
4677 struct mlx5_flow_dv_modify_hdr_resource res = {
4678 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4679 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
4681 union flow_dv_attr flow_attr = { .attr = 0 };
4682 struct mlx5_flow_dv_tag_resource tag_resource;
4683 uint32_t modify_action_position = UINT32_MAX;
4684 void *match_mask = matcher.mask.buf;
4685 void *match_value = dev_flow->dv.value.buf;
4687 flow->group = attr->group;
4689 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4690 if (priority == MLX5_FLOW_PRIO_RSVD)
4691 priority = priv->config.flow_prio - 1;
4692 for (; !actions_end ; actions++) {
4693 const struct rte_flow_action_queue *queue;
4694 const struct rte_flow_action_rss *rss;
4695 const struct rte_flow_action *action = actions;
4696 const struct rte_flow_action_count *count = action->conf;
4697 const uint8_t *rss_key;
4698 const struct rte_flow_action_jump *jump_data;
4699 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
4700 struct mlx5_flow_tbl_resource *tbl;
4701 uint32_t port_id = 0;
4702 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
4704 switch (actions->type) {
4705 case RTE_FLOW_ACTION_TYPE_VOID:
4707 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4708 if (flow_dv_translate_action_port_id(dev, action,
4711 port_id_resource.port_id = port_id;
4712 if (flow_dv_port_id_action_resource_register
4713 (dev, &port_id_resource, dev_flow, error))
4715 dev_flow->dv.actions[actions_n++] =
4716 dev_flow->dv.port_id_action->action;
4717 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4719 case RTE_FLOW_ACTION_TYPE_FLAG:
4721 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
4722 if (!flow->tag_resource)
4723 if (flow_dv_tag_resource_register
4724 (dev, &tag_resource, dev_flow, error))
4726 dev_flow->dv.actions[actions_n++] =
4727 flow->tag_resource->action;
4728 action_flags |= MLX5_FLOW_ACTION_FLAG;
4730 case RTE_FLOW_ACTION_TYPE_MARK:
4731 tag_resource.tag = mlx5_flow_mark_set
4732 (((const struct rte_flow_action_mark *)
4733 (actions->conf))->id);
4734 if (!flow->tag_resource)
4735 if (flow_dv_tag_resource_register
4736 (dev, &tag_resource, dev_flow, error))
4738 dev_flow->dv.actions[actions_n++] =
4739 flow->tag_resource->action;
4740 action_flags |= MLX5_FLOW_ACTION_MARK;
4742 case RTE_FLOW_ACTION_TYPE_DROP:
4743 action_flags |= MLX5_FLOW_ACTION_DROP;
4745 case RTE_FLOW_ACTION_TYPE_QUEUE:
4746 queue = actions->conf;
4747 flow->rss.queue_num = 1;
4748 (*flow->queue)[0] = queue->index;
4749 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4751 case RTE_FLOW_ACTION_TYPE_RSS:
4752 rss = actions->conf;
4754 memcpy((*flow->queue), rss->queue,
4755 rss->queue_num * sizeof(uint16_t));
4756 flow->rss.queue_num = rss->queue_num;
4757 /* NULL RSS key indicates default RSS key. */
4758 rss_key = !rss->key ? rss_hash_default_key : rss->key;
4759 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
4760 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
4761 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
4762 flow->rss.level = rss->level;
4763 action_flags |= MLX5_FLOW_ACTION_RSS;
4765 case RTE_FLOW_ACTION_TYPE_COUNT:
4766 if (!priv->config.devx) {
4767 rte_errno = ENOTSUP;
4770 flow->counter = flow_dv_counter_alloc(dev,
4774 if (flow->counter == NULL)
4776 dev_flow->dv.actions[actions_n++] =
4777 flow->counter->action;
4778 action_flags |= MLX5_FLOW_ACTION_COUNT;
4781 if (rte_errno == ENOTSUP)
4782 return rte_flow_error_set
4784 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4786 "count action not supported");
4788 return rte_flow_error_set
4790 RTE_FLOW_ERROR_TYPE_ACTION,
4792 "cannot create counter"
4794 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4795 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4796 if (flow_dv_create_action_l2_encap(dev, actions,
4801 dev_flow->dv.actions[actions_n++] =
4802 dev_flow->dv.encap_decap->verbs_action;
4803 action_flags |= actions->type ==
4804 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4805 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4806 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4808 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4809 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4810 if (flow_dv_create_action_l2_decap(dev, dev_flow,
4814 dev_flow->dv.actions[actions_n++] =
4815 dev_flow->dv.encap_decap->verbs_action;
4816 action_flags |= actions->type ==
4817 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4818 MLX5_FLOW_ACTION_VXLAN_DECAP :
4819 MLX5_FLOW_ACTION_NVGRE_DECAP;
4821 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4822 /* Handle encap with preceding decap. */
4823 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
4824 if (flow_dv_create_action_raw_encap
4825 (dev, actions, dev_flow, attr, error))
4827 dev_flow->dv.actions[actions_n++] =
4828 dev_flow->dv.encap_decap->verbs_action;
4830 /* Handle encap without preceding decap. */
4831 if (flow_dv_create_action_l2_encap
4832 (dev, actions, dev_flow, attr->transfer,
4835 dev_flow->dv.actions[actions_n++] =
4836 dev_flow->dv.encap_decap->verbs_action;
4838 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4840 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4841 /* Check if this decap is followed by encap. */
4842 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
4843 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
4846 /* Handle decap only if it isn't followed by encap. */
4847 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4848 if (flow_dv_create_action_l2_decap
4849 (dev, dev_flow, attr->transfer, error))
4851 dev_flow->dv.actions[actions_n++] =
4852 dev_flow->dv.encap_decap->verbs_action;
4854 /* If decap is followed by encap, handle it at encap. */
4855 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4857 case RTE_FLOW_ACTION_TYPE_JUMP:
4858 jump_data = action->conf;
4859 tbl = flow_dv_tbl_resource_get(dev, jump_data->group *
4862 attr->transfer, error);
4864 return rte_flow_error_set
4866 RTE_FLOW_ERROR_TYPE_ACTION,
4868 "cannot create jump action.");
4869 jump_tbl_resource.tbl = tbl;
4870 if (flow_dv_jump_tbl_resource_register
4871 (dev, &jump_tbl_resource, dev_flow, error)) {
4872 flow_dv_tbl_resource_release(tbl);
4873 return rte_flow_error_set
4875 RTE_FLOW_ERROR_TYPE_ACTION,
4877 "cannot create jump action.");
4879 dev_flow->dv.actions[actions_n++] =
4880 dev_flow->dv.jump->action;
4881 action_flags |= MLX5_FLOW_ACTION_JUMP;
4883 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4884 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4885 if (flow_dv_convert_action_modify_mac(&res, actions,
4888 action_flags |= actions->type ==
4889 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4890 MLX5_FLOW_ACTION_SET_MAC_SRC :
4891 MLX5_FLOW_ACTION_SET_MAC_DST;
4893 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4894 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4895 if (flow_dv_convert_action_modify_ipv4(&res, actions,
4898 action_flags |= actions->type ==
4899 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4900 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4901 MLX5_FLOW_ACTION_SET_IPV4_DST;
4903 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4904 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4905 if (flow_dv_convert_action_modify_ipv6(&res, actions,
4908 action_flags |= actions->type ==
4909 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4910 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4911 MLX5_FLOW_ACTION_SET_IPV6_DST;
4913 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4914 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4915 if (flow_dv_convert_action_modify_tp(&res, actions,
4919 action_flags |= actions->type ==
4920 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4921 MLX5_FLOW_ACTION_SET_TP_SRC :
4922 MLX5_FLOW_ACTION_SET_TP_DST;
4924 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4925 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
4929 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
4931 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4932 if (flow_dv_convert_action_modify_ttl(&res, actions,
4936 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
4938 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4939 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4940 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
4943 action_flags |= actions->type ==
4944 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4945 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4946 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4949 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4950 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4951 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
4954 action_flags |= actions->type ==
4955 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4956 MLX5_FLOW_ACTION_INC_TCP_ACK :
4957 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4959 case RTE_FLOW_ACTION_TYPE_END:
4961 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
4962 /* create modify action if needed. */
4963 if (flow_dv_modify_hdr_resource_register
4968 dev_flow->dv.actions[modify_action_position] =
4969 dev_flow->dv.modify_hdr->verbs_action;
4975 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
4976 modify_action_position == UINT32_MAX)
4977 modify_action_position = actions_n++;
4979 dev_flow->dv.actions_n = actions_n;
4980 flow->actions = action_flags;
4981 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4982 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4984 switch (items->type) {
4985 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4986 flow_dv_translate_item_port_id(dev, match_mask,
4987 match_value, items);
4988 last_item = MLX5_FLOW_ITEM_PORT_ID;
4990 case RTE_FLOW_ITEM_TYPE_ETH:
4991 flow_dv_translate_item_eth(match_mask, match_value,
4993 matcher.priority = MLX5_PRIORITY_MAP_L2;
4994 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4995 MLX5_FLOW_LAYER_OUTER_L2;
4997 case RTE_FLOW_ITEM_TYPE_VLAN:
4998 flow_dv_translate_item_vlan(match_mask, match_value,
5000 matcher.priority = MLX5_PRIORITY_MAP_L2;
5001 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
5002 MLX5_FLOW_LAYER_INNER_VLAN) :
5003 (MLX5_FLOW_LAYER_OUTER_L2 |
5004 MLX5_FLOW_LAYER_OUTER_VLAN);
5006 case RTE_FLOW_ITEM_TYPE_IPV4:
5007 flow_dv_translate_item_ipv4(match_mask, match_value,
5008 items, tunnel, attr->group);
5009 matcher.priority = MLX5_PRIORITY_MAP_L3;
5010 dev_flow->dv.hash_fields |=
5011 mlx5_flow_hashfields_adjust
5013 MLX5_IPV4_LAYER_TYPES,
5014 MLX5_IPV4_IBV_RX_HASH);
5015 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5016 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5017 mlx5_flow_tunnel_ip_check(items, &last_item);
5019 case RTE_FLOW_ITEM_TYPE_IPV6:
5020 flow_dv_translate_item_ipv6(match_mask, match_value,
5021 items, tunnel, attr->group);
5022 matcher.priority = MLX5_PRIORITY_MAP_L3;
5023 dev_flow->dv.hash_fields |=
5024 mlx5_flow_hashfields_adjust
5026 MLX5_IPV6_LAYER_TYPES,
5027 MLX5_IPV6_IBV_RX_HASH);
5028 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5029 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5030 mlx5_flow_tunnel_ip_check(items, &last_item);
5032 case RTE_FLOW_ITEM_TYPE_TCP:
5033 flow_dv_translate_item_tcp(match_mask, match_value,
5035 matcher.priority = MLX5_PRIORITY_MAP_L4;
5036 dev_flow->dv.hash_fields |=
5037 mlx5_flow_hashfields_adjust
5038 (dev_flow, tunnel, ETH_RSS_TCP,
5039 IBV_RX_HASH_SRC_PORT_TCP |
5040 IBV_RX_HASH_DST_PORT_TCP);
5041 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5042 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5044 case RTE_FLOW_ITEM_TYPE_UDP:
5045 flow_dv_translate_item_udp(match_mask, match_value,
5047 matcher.priority = MLX5_PRIORITY_MAP_L4;
5048 dev_flow->dv.hash_fields |=
5049 mlx5_flow_hashfields_adjust
5050 (dev_flow, tunnel, ETH_RSS_UDP,
5051 IBV_RX_HASH_SRC_PORT_UDP |
5052 IBV_RX_HASH_DST_PORT_UDP);
5053 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5054 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5056 case RTE_FLOW_ITEM_TYPE_GRE:
5057 flow_dv_translate_item_gre(match_mask, match_value,
5059 last_item = MLX5_FLOW_LAYER_GRE;
5061 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5062 flow_dv_translate_item_gre_key(match_mask,
5063 match_value, items);
5064 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5066 case RTE_FLOW_ITEM_TYPE_NVGRE:
5067 flow_dv_translate_item_nvgre(match_mask, match_value,
5069 last_item = MLX5_FLOW_LAYER_GRE;
5071 case RTE_FLOW_ITEM_TYPE_VXLAN:
5072 flow_dv_translate_item_vxlan(match_mask, match_value,
5074 last_item = MLX5_FLOW_LAYER_VXLAN;
5076 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5077 flow_dv_translate_item_vxlan(match_mask, match_value,
5079 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5081 case RTE_FLOW_ITEM_TYPE_MPLS:
5082 flow_dv_translate_item_mpls(match_mask, match_value,
5083 items, last_item, tunnel);
5084 last_item = MLX5_FLOW_LAYER_MPLS;
5086 case RTE_FLOW_ITEM_TYPE_META:
5087 flow_dv_translate_item_meta(match_mask, match_value,
5089 last_item = MLX5_FLOW_ITEM_METADATA;
5091 case RTE_FLOW_ITEM_TYPE_ICMP:
5092 flow_dv_translate_item_icmp(match_mask, match_value,
5094 last_item = MLX5_FLOW_LAYER_ICMP;
5096 case RTE_FLOW_ITEM_TYPE_ICMP6:
5097 flow_dv_translate_item_icmp6(match_mask, match_value,
5099 last_item = MLX5_FLOW_LAYER_ICMP6;
5104 item_flags |= last_item;
5107 * In case of ingress traffic when E-Switch mode is enabled,
5108 * we have two cases where we need to set the source port manually.
5109 * The first one, is in case of Nic steering rule, and the second is
5110 * E-Switch rule where no port_id item was found. In both cases
5111 * the source port is set according the current port in use.
5113 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
5114 (priv->representor || priv->master)) {
5115 if (flow_dv_translate_item_port_id(dev, match_mask,
5119 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
5120 dev_flow->dv.value.buf));
5121 dev_flow->layers = item_flags;
5122 /* Register matcher. */
5123 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
5125 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
5127 matcher.egress = attr->egress;
5128 matcher.group = attr->group;
5129 matcher.transfer = attr->transfer;
5130 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
5136 * Apply the flow to the NIC.
5139 * Pointer to the Ethernet device structure.
5140 * @param[in, out] flow
5141 * Pointer to flow structure.
5143 * Pointer to error structure.
5146 * 0 on success, a negative errno value otherwise and rte_errno is set.
5149 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
5150 struct rte_flow_error *error)
5152 struct mlx5_flow_dv *dv;
5153 struct mlx5_flow *dev_flow;
5154 struct mlx5_priv *priv = dev->data->dev_private;
5158 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5161 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
5162 if (flow->transfer) {
5163 dv->actions[n++] = priv->sh->esw_drop_action;
5165 dv->hrxq = mlx5_hrxq_drop_new(dev);
5169 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5171 "cannot get drop hash queue");
5174 dv->actions[n++] = dv->hrxq->action;
5176 } else if (flow->actions &
5177 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
5178 struct mlx5_hrxq *hrxq;
5180 hrxq = mlx5_hrxq_get(dev, flow->key,
5181 MLX5_RSS_HASH_KEY_LEN,
5184 flow->rss.queue_num);
5186 hrxq = mlx5_hrxq_new
5187 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
5188 dv->hash_fields, (*flow->queue),
5189 flow->rss.queue_num,
5190 !!(dev_flow->layers &
5191 MLX5_FLOW_LAYER_TUNNEL));
5196 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5197 "cannot get hash queue");
5201 dv->actions[n++] = dv->hrxq->action;
5204 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
5205 (void *)&dv->value, n,
5208 rte_flow_error_set(error, errno,
5209 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5211 "hardware refuses to create flow");
5217 err = rte_errno; /* Save rte_errno before cleanup. */
5218 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5219 struct mlx5_flow_dv *dv = &dev_flow->dv;
5221 if (flow->actions & MLX5_FLOW_ACTION_DROP)
5222 mlx5_hrxq_drop_release(dev);
5224 mlx5_hrxq_release(dev, dv->hrxq);
5228 rte_errno = err; /* Restore rte_errno. */
5233 * Release the flow matcher.
5236 * Pointer to Ethernet device.
5238 * Pointer to mlx5_flow.
5241 * 1 while a reference on it exists, 0 when freed.
5244 flow_dv_matcher_release(struct rte_eth_dev *dev,
5245 struct mlx5_flow *flow)
5247 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
5248 struct mlx5_priv *priv = dev->data->dev_private;
5249 struct mlx5_ibv_shared *sh = priv->sh;
5250 struct mlx5_flow_tbl_resource *tbl;
5252 assert(matcher->matcher_object);
5253 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
5254 dev->data->port_id, (void *)matcher,
5255 rte_atomic32_read(&matcher->refcnt));
5256 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
5257 claim_zero(mlx5_glue->dv_destroy_flow_matcher
5258 (matcher->matcher_object));
5259 LIST_REMOVE(matcher, next);
5260 if (matcher->egress)
5261 tbl = &sh->tx_tbl[matcher->group];
5263 tbl = &sh->rx_tbl[matcher->group];
5264 flow_dv_tbl_resource_release(tbl);
5266 DRV_LOG(DEBUG, "port %u matcher %p: removed",
5267 dev->data->port_id, (void *)matcher);
5274 * Release an encap/decap resource.
5277 * Pointer to mlx5_flow.
5280 * 1 while a reference on it exists, 0 when freed.
5283 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
5285 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
5286 flow->dv.encap_decap;
5288 assert(cache_resource->verbs_action);
5289 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
5290 (void *)cache_resource,
5291 rte_atomic32_read(&cache_resource->refcnt));
5292 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5293 claim_zero(mlx5_glue->destroy_flow_action
5294 (cache_resource->verbs_action));
5295 LIST_REMOVE(cache_resource, next);
5296 rte_free(cache_resource);
5297 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
5298 (void *)cache_resource);
5305 * Release an jump to table action resource.
5308 * Pointer to mlx5_flow.
5311 * 1 while a reference on it exists, 0 when freed.
5314 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
5316 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
5319 assert(cache_resource->action);
5320 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
5321 (void *)cache_resource,
5322 rte_atomic32_read(&cache_resource->refcnt));
5323 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5324 claim_zero(mlx5_glue->destroy_flow_action
5325 (cache_resource->action));
5326 LIST_REMOVE(cache_resource, next);
5327 flow_dv_tbl_resource_release(cache_resource->tbl);
5328 rte_free(cache_resource);
5329 DRV_LOG(DEBUG, "jump table resource %p: removed",
5330 (void *)cache_resource);
5337 * Release a modify-header resource.
5340 * Pointer to mlx5_flow.
5343 * 1 while a reference on it exists, 0 when freed.
5346 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
5348 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
5349 flow->dv.modify_hdr;
5351 assert(cache_resource->verbs_action);
5352 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
5353 (void *)cache_resource,
5354 rte_atomic32_read(&cache_resource->refcnt));
5355 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5356 claim_zero(mlx5_glue->destroy_flow_action
5357 (cache_resource->verbs_action));
5358 LIST_REMOVE(cache_resource, next);
5359 rte_free(cache_resource);
5360 DRV_LOG(DEBUG, "modify-header resource %p: removed",
5361 (void *)cache_resource);
5368 * Release port ID action resource.
5371 * Pointer to mlx5_flow.
5374 * 1 while a reference on it exists, 0 when freed.
5377 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
5379 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
5380 flow->dv.port_id_action;
5382 assert(cache_resource->action);
5383 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
5384 (void *)cache_resource,
5385 rte_atomic32_read(&cache_resource->refcnt));
5386 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5387 claim_zero(mlx5_glue->destroy_flow_action
5388 (cache_resource->action));
5389 LIST_REMOVE(cache_resource, next);
5390 rte_free(cache_resource);
5391 DRV_LOG(DEBUG, "port id action resource %p: removed",
5392 (void *)cache_resource);
5399 * Remove the flow from the NIC but keeps it in memory.
5402 * Pointer to Ethernet device.
5403 * @param[in, out] flow
5404 * Pointer to flow structure.
5407 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
5409 struct mlx5_flow_dv *dv;
5410 struct mlx5_flow *dev_flow;
5414 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5417 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
5421 if (flow->actions & MLX5_FLOW_ACTION_DROP)
5422 mlx5_hrxq_drop_release(dev);
5424 mlx5_hrxq_release(dev, dv->hrxq);
5431 * Remove the flow from the NIC and the memory.
5434 * Pointer to the Ethernet device structure.
5435 * @param[in, out] flow
5436 * Pointer to flow structure.
5439 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
5441 struct mlx5_flow *dev_flow;
5445 flow_dv_remove(dev, flow);
5446 if (flow->counter) {
5447 flow_dv_counter_release(dev, flow->counter);
5448 flow->counter = NULL;
5450 if (flow->tag_resource) {
5451 flow_dv_tag_release(dev, flow->tag_resource);
5452 flow->tag_resource = NULL;
5454 while (!LIST_EMPTY(&flow->dev_flows)) {
5455 dev_flow = LIST_FIRST(&flow->dev_flows);
5456 LIST_REMOVE(dev_flow, next);
5457 if (dev_flow->dv.matcher)
5458 flow_dv_matcher_release(dev, dev_flow);
5459 if (dev_flow->dv.encap_decap)
5460 flow_dv_encap_decap_resource_release(dev_flow);
5461 if (dev_flow->dv.modify_hdr)
5462 flow_dv_modify_hdr_resource_release(dev_flow);
5463 if (dev_flow->dv.jump)
5464 flow_dv_jump_tbl_resource_release(dev_flow);
5465 if (dev_flow->dv.port_id_action)
5466 flow_dv_port_id_action_resource_release(dev_flow);
5472 * Query a dv flow rule for its statistics via devx.
5475 * Pointer to Ethernet device.
5477 * Pointer to the sub flow.
5479 * data retrieved by the query.
5481 * Perform verbose error reporting if not NULL.
5484 * 0 on success, a negative errno value otherwise and rte_errno is set.
5487 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
5488 void *data, struct rte_flow_error *error)
5490 struct mlx5_priv *priv = dev->data->dev_private;
5491 struct rte_flow_query_count *qc = data;
5493 if (!priv->config.devx)
5494 return rte_flow_error_set(error, ENOTSUP,
5495 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5497 "counters are not supported");
5498 if (flow->counter) {
5499 uint64_t pkts, bytes;
5500 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
5504 return rte_flow_error_set(error, -err,
5505 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5506 NULL, "cannot read counters");
5509 qc->hits = pkts - flow->counter->hits;
5510 qc->bytes = bytes - flow->counter->bytes;
5512 flow->counter->hits = pkts;
5513 flow->counter->bytes = bytes;
5517 return rte_flow_error_set(error, EINVAL,
5518 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5520 "counters are not available");
5526 * @see rte_flow_query()
5530 flow_dv_query(struct rte_eth_dev *dev,
5531 struct rte_flow *flow __rte_unused,
5532 const struct rte_flow_action *actions __rte_unused,
5533 void *data __rte_unused,
5534 struct rte_flow_error *error __rte_unused)
5538 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5539 switch (actions->type) {
5540 case RTE_FLOW_ACTION_TYPE_VOID:
5542 case RTE_FLOW_ACTION_TYPE_COUNT:
5543 ret = flow_dv_query_count(dev, flow, data, error);
5546 return rte_flow_error_set(error, ENOTSUP,
5547 RTE_FLOW_ERROR_TYPE_ACTION,
5549 "action not supported");
5556 * Mutex-protected thunk to flow_dv_translate().
5559 flow_d_translate(struct rte_eth_dev *dev,
5560 struct mlx5_flow *dev_flow,
5561 const struct rte_flow_attr *attr,
5562 const struct rte_flow_item items[],
5563 const struct rte_flow_action actions[],
5564 struct rte_flow_error *error)
5568 flow_d_shared_lock(dev);
5569 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
5570 flow_d_shared_unlock(dev);
5575 * Mutex-protected thunk to flow_dv_apply().
5578 flow_d_apply(struct rte_eth_dev *dev,
5579 struct rte_flow *flow,
5580 struct rte_flow_error *error)
5584 flow_d_shared_lock(dev);
5585 ret = flow_dv_apply(dev, flow, error);
5586 flow_d_shared_unlock(dev);
5591 * Mutex-protected thunk to flow_dv_remove().
5594 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
5596 flow_d_shared_lock(dev);
5597 flow_dv_remove(dev, flow);
5598 flow_d_shared_unlock(dev);
5602 * Mutex-protected thunk to flow_dv_destroy().
5605 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
5607 flow_d_shared_lock(dev);
5608 flow_dv_destroy(dev, flow);
5609 flow_d_shared_unlock(dev);
5612 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
5613 .validate = flow_dv_validate,
5614 .prepare = flow_dv_prepare,
5615 .translate = flow_d_translate,
5616 .apply = flow_d_apply,
5617 .remove = flow_d_remove,
5618 .destroy = flow_d_destroy,
5619 .query = flow_dv_query,
5622 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */