1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_dv_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_dv_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_NONE] = MLX5_MODI_OUT_NONE,
836 [REG_A] = MLX5_MODI_META_DATA_REG_A,
837 [REG_B] = MLX5_MODI_META_DATA_REG_B,
838 [REG_C_0] = MLX5_MODI_META_REG_C_0,
839 [REG_C_1] = MLX5_MODI_META_REG_C_1,
840 [REG_C_2] = MLX5_MODI_META_REG_C_2,
841 [REG_C_3] = MLX5_MODI_META_REG_C_3,
842 [REG_C_4] = MLX5_MODI_META_REG_C_4,
843 [REG_C_5] = MLX5_MODI_META_REG_C_5,
844 [REG_C_6] = MLX5_MODI_META_REG_C_6,
845 [REG_C_7] = MLX5_MODI_META_REG_C_7,
849 * Convert register set to DV specification.
851 * @param[in,out] resource
852 * Pointer to the modify-header resource.
854 * Pointer to action specification.
856 * Pointer to the error structure.
859 * 0 on success, a negative errno value otherwise and rte_errno is set.
862 flow_dv_convert_action_set_reg
863 (struct mlx5_flow_dv_modify_hdr_resource *resource,
864 const struct rte_flow_action *action,
865 struct rte_flow_error *error)
867 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
868 struct mlx5_modification_cmd *actions = resource->actions;
869 uint32_t i = resource->actions_num;
871 if (i >= MLX5_MODIFY_NUM)
872 return rte_flow_error_set(error, EINVAL,
873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
874 "too many items to modify");
875 assert(conf->id != REG_NONE);
876 assert(conf->id < RTE_DIM(reg_to_field));
877 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
878 actions[i].field = reg_to_field[conf->id];
879 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
880 actions[i].data1 = rte_cpu_to_be_32(conf->data);
882 resource->actions_num = i;
883 if (!resource->actions_num)
884 return rte_flow_error_set(error, EINVAL,
885 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
886 "invalid modification flow item");
891 * Convert SET_TAG action to DV specification.
894 * Pointer to the rte_eth_dev structure.
895 * @param[in,out] resource
896 * Pointer to the modify-header resource.
898 * Pointer to action specification.
900 * Pointer to the error structure.
903 * 0 on success, a negative errno value otherwise and rte_errno is set.
906 flow_dv_convert_action_set_tag
907 (struct rte_eth_dev *dev,
908 struct mlx5_flow_dv_modify_hdr_resource *resource,
909 const struct rte_flow_action_set_tag *conf,
910 struct rte_flow_error *error)
912 rte_be32_t data = rte_cpu_to_be_32(conf->data);
913 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
914 struct rte_flow_item item = {
918 struct field_modify_info reg_c_x[] = {
921 enum mlx5_modification_field reg_type;
924 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
927 assert(ret != REG_NONE);
928 assert((unsigned int)ret < RTE_DIM(reg_to_field));
929 reg_type = reg_to_field[ret];
930 assert(reg_type > 0);
931 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
932 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
933 MLX5_MODIFICATION_TYPE_SET, error);
937 * Convert internal COPY_REG action to DV specification.
940 * Pointer to the rte_eth_dev structure.
942 * Pointer to the modify-header resource.
944 * Pointer to action specification.
946 * Pointer to the error structure.
949 * 0 on success, a negative errno value otherwise and rte_errno is set.
952 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
953 struct mlx5_flow_dv_modify_hdr_resource *res,
954 const struct rte_flow_action *action,
955 struct rte_flow_error *error)
957 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
958 rte_be32_t mask = RTE_BE32(UINT32_MAX);
959 struct rte_flow_item item = {
963 struct field_modify_info reg_src[] = {
964 {4, 0, reg_to_field[conf->src]},
967 struct field_modify_info reg_dst = {
969 .id = reg_to_field[conf->dst],
971 /* Adjust reg_c[0] usage according to reported mask. */
972 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
973 struct mlx5_priv *priv = dev->data->dev_private;
974 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
977 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
978 if (conf->dst == REG_C_0) {
979 /* Copy to reg_c[0], within mask only. */
980 reg_dst.offset = rte_bsf32(reg_c0);
982 * Mask is ignoring the enianness, because
983 * there is no conversion in datapath.
985 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
986 /* Copy from destination lower bits to reg_c[0]. */
987 mask = reg_c0 >> reg_dst.offset;
989 /* Copy from destination upper bits to reg_c[0]. */
990 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
991 rte_fls_u32(reg_c0));
994 mask = rte_cpu_to_be_32(reg_c0);
995 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
996 /* Copy from reg_c[0] to destination lower bits. */
999 /* Copy from reg_c[0] to destination upper bits. */
1000 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1001 (rte_fls_u32(reg_c0) -
1006 return flow_dv_convert_modify_action(&item,
1007 reg_src, ®_dst, res,
1008 MLX5_MODIFICATION_TYPE_COPY,
1013 * Convert MARK action to DV specification. This routine is used
1014 * in extensive metadata only and requires metadata register to be
1015 * handled. In legacy mode hardware tag resource is engaged.
1018 * Pointer to the rte_eth_dev structure.
1020 * Pointer to MARK action specification.
1021 * @param[in,out] resource
1022 * Pointer to the modify-header resource.
1024 * Pointer to the error structure.
1027 * 0 on success, a negative errno value otherwise and rte_errno is set.
1030 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1031 const struct rte_flow_action_mark *conf,
1032 struct mlx5_flow_dv_modify_hdr_resource *resource,
1033 struct rte_flow_error *error)
1035 struct mlx5_priv *priv = dev->data->dev_private;
1036 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1037 priv->sh->dv_mark_mask);
1038 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1039 struct rte_flow_item item = {
1043 struct field_modify_info reg_c_x[] = {
1044 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1047 enum modify_reg reg;
1050 return rte_flow_error_set(error, EINVAL,
1051 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1052 NULL, "zero mark action mask");
1053 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1057 reg_c_x[0].id = reg_to_field[reg];
1058 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1059 MLX5_MODIFICATION_TYPE_SET, error);
1063 * Validate MARK item.
1066 * Pointer to the rte_eth_dev structure.
1068 * Item specification.
1070 * Attributes of flow that includes this item.
1072 * Pointer to error structure.
1075 * 0 on success, a negative errno value otherwise and rte_errno is set.
1078 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1079 const struct rte_flow_item *item,
1080 const struct rte_flow_attr *attr __rte_unused,
1081 struct rte_flow_error *error)
1083 struct mlx5_priv *priv = dev->data->dev_private;
1084 struct mlx5_dev_config *config = &priv->config;
1085 const struct rte_flow_item_mark *spec = item->spec;
1086 const struct rte_flow_item_mark *mask = item->mask;
1087 const struct rte_flow_item_mark nic_mask = {
1088 .id = priv->sh->dv_mark_mask,
1092 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1093 return rte_flow_error_set(error, ENOTSUP,
1094 RTE_FLOW_ERROR_TYPE_ITEM, item,
1095 "extended metadata feature"
1097 if (!mlx5_flow_ext_mreg_supported(dev))
1098 return rte_flow_error_set(error, ENOTSUP,
1099 RTE_FLOW_ERROR_TYPE_ITEM, item,
1100 "extended metadata register"
1101 " isn't supported");
1103 return rte_flow_error_set(error, ENOTSUP,
1104 RTE_FLOW_ERROR_TYPE_ITEM, item,
1105 "extended metadata register"
1106 " isn't available");
1107 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1111 return rte_flow_error_set(error, EINVAL,
1112 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1114 "data cannot be empty");
1115 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1116 return rte_flow_error_set(error, EINVAL,
1117 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1119 "mark id exceeds the limit");
1122 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1123 (const uint8_t *)&nic_mask,
1124 sizeof(struct rte_flow_item_mark),
1132 * Validate META item.
1135 * Pointer to the rte_eth_dev structure.
1137 * Item specification.
1139 * Attributes of flow that includes this item.
1141 * Pointer to error structure.
1144 * 0 on success, a negative errno value otherwise and rte_errno is set.
1147 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1148 const struct rte_flow_item *item,
1149 const struct rte_flow_attr *attr,
1150 struct rte_flow_error *error)
1152 const struct rte_flow_item_meta *spec = item->spec;
1153 const struct rte_flow_item_meta *mask = item->mask;
1154 const struct rte_flow_item_meta nic_mask = {
1160 return rte_flow_error_set(error, EINVAL,
1161 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1163 "data cannot be empty");
1165 return rte_flow_error_set(error, EINVAL,
1166 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1168 "data cannot be zero");
1170 mask = &rte_flow_item_meta_mask;
1171 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1172 (const uint8_t *)&nic_mask,
1173 sizeof(struct rte_flow_item_meta),
1178 return rte_flow_error_set(error, ENOTSUP,
1179 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1181 "pattern not supported for ingress");
1186 * Validate TAG item.
1189 * Pointer to the rte_eth_dev structure.
1191 * Item specification.
1193 * Attributes of flow that includes this item.
1195 * Pointer to error structure.
1198 * 0 on success, a negative errno value otherwise and rte_errno is set.
1201 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1202 const struct rte_flow_item *item,
1203 const struct rte_flow_attr *attr __rte_unused,
1204 struct rte_flow_error *error)
1206 const struct rte_flow_item_tag *spec = item->spec;
1207 const struct rte_flow_item_tag *mask = item->mask;
1208 const struct rte_flow_item_tag nic_mask = {
1209 .data = RTE_BE32(UINT32_MAX),
1214 if (!mlx5_flow_ext_mreg_supported(dev))
1215 return rte_flow_error_set(error, ENOTSUP,
1216 RTE_FLOW_ERROR_TYPE_ITEM, item,
1217 "extensive metadata register"
1218 " isn't supported");
1220 return rte_flow_error_set(error, EINVAL,
1221 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1223 "data cannot be empty");
1225 mask = &rte_flow_item_tag_mask;
1226 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1227 (const uint8_t *)&nic_mask,
1228 sizeof(struct rte_flow_item_tag),
1232 if (mask->index != 0xff)
1233 return rte_flow_error_set(error, EINVAL,
1234 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1235 "partial mask for tag index"
1236 " is not supported");
1237 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1240 assert(ret != REG_NONE);
1245 * Validate vport item.
1248 * Pointer to the rte_eth_dev structure.
1250 * Item specification.
1252 * Attributes of flow that includes this item.
1253 * @param[in] item_flags
1254 * Bit-fields that holds the items detected until now.
1256 * Pointer to error structure.
1259 * 0 on success, a negative errno value otherwise and rte_errno is set.
1262 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1263 const struct rte_flow_item *item,
1264 const struct rte_flow_attr *attr,
1265 uint64_t item_flags,
1266 struct rte_flow_error *error)
1268 const struct rte_flow_item_port_id *spec = item->spec;
1269 const struct rte_flow_item_port_id *mask = item->mask;
1270 const struct rte_flow_item_port_id switch_mask = {
1273 struct mlx5_priv *esw_priv;
1274 struct mlx5_priv *dev_priv;
1277 if (!attr->transfer)
1278 return rte_flow_error_set(error, EINVAL,
1279 RTE_FLOW_ERROR_TYPE_ITEM,
1281 "match on port id is valid only"
1282 " when transfer flag is enabled");
1283 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1284 return rte_flow_error_set(error, ENOTSUP,
1285 RTE_FLOW_ERROR_TYPE_ITEM, item,
1286 "multiple source ports are not"
1289 mask = &switch_mask;
1290 if (mask->id != 0xffffffff)
1291 return rte_flow_error_set(error, ENOTSUP,
1292 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1294 "no support for partial mask on"
1296 ret = mlx5_flow_item_acceptable
1297 (item, (const uint8_t *)mask,
1298 (const uint8_t *)&rte_flow_item_port_id_mask,
1299 sizeof(struct rte_flow_item_port_id),
1305 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1307 return rte_flow_error_set(error, rte_errno,
1308 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1309 "failed to obtain E-Switch info for"
1311 dev_priv = mlx5_dev_to_eswitch_info(dev);
1313 return rte_flow_error_set(error, rte_errno,
1314 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1316 "failed to obtain E-Switch info");
1317 if (esw_priv->domain_id != dev_priv->domain_id)
1318 return rte_flow_error_set(error, EINVAL,
1319 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1320 "cannot match on a port from a"
1321 " different E-Switch");
1326 * Validate the pop VLAN action.
1329 * Pointer to the rte_eth_dev structure.
1330 * @param[in] action_flags
1331 * Holds the actions detected until now.
1333 * Pointer to the pop vlan action.
1334 * @param[in] item_flags
1335 * The items found in this flow rule.
1337 * Pointer to flow attributes.
1339 * Pointer to error structure.
1342 * 0 on success, a negative errno value otherwise and rte_errno is set.
1345 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1346 uint64_t action_flags,
1347 const struct rte_flow_action *action,
1348 uint64_t item_flags,
1349 const struct rte_flow_attr *attr,
1350 struct rte_flow_error *error)
1352 struct mlx5_priv *priv = dev->data->dev_private;
1356 if (!priv->sh->pop_vlan_action)
1357 return rte_flow_error_set(error, ENOTSUP,
1358 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1360 "pop vlan action is not supported");
1362 * Check for inconsistencies:
1363 * fail strip_vlan in a flow that matches packets without VLAN tags.
1364 * fail strip_vlan in a flow that matches packets without explicitly a
1365 * matching on VLAN tag ?
1367 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1368 return rte_flow_error_set(error, ENOTSUP,
1369 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1371 "no support for multiple vlan pop "
1373 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1374 return rte_flow_error_set(error, ENOTSUP,
1375 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1377 "cannot pop vlan without a "
1378 "match on (outer) vlan in the flow");
1379 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1380 return rte_flow_error_set(error, EINVAL,
1381 RTE_FLOW_ERROR_TYPE_ACTION, action,
1382 "wrong action order, port_id should "
1383 "be after pop VLAN action");
1388 * Get VLAN default info from vlan match info.
1391 * Pointer to the rte_eth_dev structure.
1393 * the list of item specifications.
1395 * pointer VLAN info to fill to.
1397 * Pointer to error structure.
1400 * 0 on success, a negative errno value otherwise and rte_errno is set.
1403 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1404 struct rte_vlan_hdr *vlan)
1406 const struct rte_flow_item_vlan nic_mask = {
1407 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1408 MLX5DV_FLOW_VLAN_VID_MASK),
1409 .inner_type = RTE_BE16(0xffff),
1414 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1415 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1417 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1418 const struct rte_flow_item_vlan *vlan_m = items->mask;
1419 const struct rte_flow_item_vlan *vlan_v = items->spec;
1423 /* Only full match values are accepted */
1424 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1425 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1426 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1428 rte_be_to_cpu_16(vlan_v->tci &
1429 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1431 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1432 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1433 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1435 rte_be_to_cpu_16(vlan_v->tci &
1436 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1438 if (vlan_m->inner_type == nic_mask.inner_type)
1439 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1440 vlan_m->inner_type);
1445 * Validate the push VLAN action.
1447 * @param[in] action_flags
1448 * Holds the actions detected until now.
1450 * Pointer to the encap action.
1452 * Pointer to flow attributes
1454 * Pointer to error structure.
1457 * 0 on success, a negative errno value otherwise and rte_errno is set.
1460 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1461 uint64_t item_flags,
1462 const struct rte_flow_action *action,
1463 const struct rte_flow_attr *attr,
1464 struct rte_flow_error *error)
1466 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1468 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1469 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1470 return rte_flow_error_set(error, EINVAL,
1471 RTE_FLOW_ERROR_TYPE_ACTION, action,
1472 "invalid vlan ethertype");
1474 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1475 return rte_flow_error_set(error, ENOTSUP,
1476 RTE_FLOW_ERROR_TYPE_ACTION, action,
1477 "no support for multiple VLAN "
1479 if (!mlx5_flow_find_action
1480 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1481 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1482 return rte_flow_error_set(error, ENOTSUP,
1483 RTE_FLOW_ERROR_TYPE_ACTION, action,
1484 "push VLAN needs to match on VLAN in order to "
1485 "get VLAN VID information because there is "
1486 "no followed set VLAN VID action");
1487 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1488 return rte_flow_error_set(error, EINVAL,
1489 RTE_FLOW_ERROR_TYPE_ACTION, action,
1490 "wrong action order, port_id should "
1491 "be after push VLAN");
1497 * Validate the set VLAN PCP.
1499 * @param[in] action_flags
1500 * Holds the actions detected until now.
1501 * @param[in] actions
1502 * Pointer to the list of actions remaining in the flow rule.
1504 * Pointer to flow attributes
1506 * Pointer to error structure.
1509 * 0 on success, a negative errno value otherwise and rte_errno is set.
1512 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1513 const struct rte_flow_action actions[],
1514 struct rte_flow_error *error)
1516 const struct rte_flow_action *action = actions;
1517 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1519 if (conf->vlan_pcp > 7)
1520 return rte_flow_error_set(error, EINVAL,
1521 RTE_FLOW_ERROR_TYPE_ACTION, action,
1522 "VLAN PCP value is too big");
1523 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1524 return rte_flow_error_set(error, ENOTSUP,
1525 RTE_FLOW_ERROR_TYPE_ACTION, action,
1526 "set VLAN PCP action must follow "
1527 "the push VLAN action");
1528 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1529 return rte_flow_error_set(error, ENOTSUP,
1530 RTE_FLOW_ERROR_TYPE_ACTION, action,
1531 "Multiple VLAN PCP modification are "
1533 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1534 return rte_flow_error_set(error, EINVAL,
1535 RTE_FLOW_ERROR_TYPE_ACTION, action,
1536 "wrong action order, port_id should "
1537 "be after set VLAN PCP");
1542 * Validate the set VLAN VID.
1544 * @param[in] item_flags
1545 * Holds the items detected in this rule.
1546 * @param[in] actions
1547 * Pointer to the list of actions remaining in the flow rule.
1549 * Pointer to flow attributes
1551 * Pointer to error structure.
1554 * 0 on success, a negative errno value otherwise and rte_errno is set.
1557 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1558 uint64_t action_flags,
1559 const struct rte_flow_action actions[],
1560 struct rte_flow_error *error)
1562 const struct rte_flow_action *action = actions;
1563 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1565 if (conf->vlan_vid > RTE_BE16(0xFFE))
1566 return rte_flow_error_set(error, EINVAL,
1567 RTE_FLOW_ERROR_TYPE_ACTION, action,
1568 "VLAN VID value is too big");
1569 /* there is an of_push_vlan action before us */
1570 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1571 if (mlx5_flow_find_action(actions + 1,
1572 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1573 return rte_flow_error_set(error, ENOTSUP,
1574 RTE_FLOW_ERROR_TYPE_ACTION, action,
1575 "Multiple VLAN VID modifications are "
1582 * Action is on an existing VLAN header:
1583 * Need to verify this is a single modify CID action.
1584 * Rule mast include a match on outer VLAN.
1586 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1587 return rte_flow_error_set(error, ENOTSUP,
1588 RTE_FLOW_ERROR_TYPE_ACTION, action,
1589 "Multiple VLAN VID modifications are "
1591 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1592 return rte_flow_error_set(error, EINVAL,
1593 RTE_FLOW_ERROR_TYPE_ACTION, action,
1594 "match on VLAN is required in order "
1596 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1597 return rte_flow_error_set(error, EINVAL,
1598 RTE_FLOW_ERROR_TYPE_ACTION, action,
1599 "wrong action order, port_id should "
1600 "be after set VLAN VID");
1605 * Validate the FLAG action.
1608 * Pointer to the rte_eth_dev structure.
1609 * @param[in] action_flags
1610 * Holds the actions detected until now.
1612 * Pointer to flow attributes
1614 * Pointer to error structure.
1617 * 0 on success, a negative errno value otherwise and rte_errno is set.
1620 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1621 uint64_t action_flags,
1622 const struct rte_flow_attr *attr,
1623 struct rte_flow_error *error)
1625 struct mlx5_priv *priv = dev->data->dev_private;
1626 struct mlx5_dev_config *config = &priv->config;
1629 /* Fall back if no extended metadata register support. */
1630 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1631 return mlx5_flow_validate_action_flag(action_flags, attr,
1633 /* Extensive metadata mode requires registers. */
1634 if (!mlx5_flow_ext_mreg_supported(dev))
1635 return rte_flow_error_set(error, ENOTSUP,
1636 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1637 "no metadata registers "
1638 "to support flag action");
1639 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1640 return rte_flow_error_set(error, ENOTSUP,
1641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1642 "extended metadata register"
1643 " isn't available");
1644 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1648 if (action_flags & MLX5_FLOW_ACTION_DROP)
1649 return rte_flow_error_set(error, EINVAL,
1650 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1651 "can't drop and flag in same flow");
1652 if (action_flags & MLX5_FLOW_ACTION_MARK)
1653 return rte_flow_error_set(error, EINVAL,
1654 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1655 "can't mark and flag in same flow");
1656 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1657 return rte_flow_error_set(error, EINVAL,
1658 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1660 " actions in same flow");
1665 * Validate MARK action.
1668 * Pointer to the rte_eth_dev structure.
1670 * Pointer to action.
1671 * @param[in] action_flags
1672 * Holds the actions detected until now.
1674 * Pointer to flow attributes
1676 * Pointer to error structure.
1679 * 0 on success, a negative errno value otherwise and rte_errno is set.
1682 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1683 const struct rte_flow_action *action,
1684 uint64_t action_flags,
1685 const struct rte_flow_attr *attr,
1686 struct rte_flow_error *error)
1688 struct mlx5_priv *priv = dev->data->dev_private;
1689 struct mlx5_dev_config *config = &priv->config;
1690 const struct rte_flow_action_mark *mark = action->conf;
1693 /* Fall back if no extended metadata register support. */
1694 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1695 return mlx5_flow_validate_action_mark(action, action_flags,
1697 /* Extensive metadata mode requires registers. */
1698 if (!mlx5_flow_ext_mreg_supported(dev))
1699 return rte_flow_error_set(error, ENOTSUP,
1700 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1701 "no metadata registers "
1702 "to support mark action");
1703 if (!priv->sh->dv_mark_mask)
1704 return rte_flow_error_set(error, ENOTSUP,
1705 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1706 "extended metadata register"
1707 " isn't available");
1708 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1713 return rte_flow_error_set(error, EINVAL,
1714 RTE_FLOW_ERROR_TYPE_ACTION, action,
1715 "configuration cannot be null");
1716 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1717 return rte_flow_error_set(error, EINVAL,
1718 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1720 "mark id exceeds the limit");
1721 if (action_flags & MLX5_FLOW_ACTION_DROP)
1722 return rte_flow_error_set(error, EINVAL,
1723 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1724 "can't drop and mark in same flow");
1725 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1726 return rte_flow_error_set(error, EINVAL,
1727 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1728 "can't flag and mark in same flow");
1729 if (action_flags & MLX5_FLOW_ACTION_MARK)
1730 return rte_flow_error_set(error, EINVAL,
1731 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1732 "can't have 2 mark actions in same"
1738 * Validate SET_TAG action.
1741 * Pointer to the rte_eth_dev structure.
1743 * Pointer to the encap action.
1744 * @param[in] action_flags
1745 * Holds the actions detected until now.
1747 * Pointer to flow attributes
1749 * Pointer to error structure.
1752 * 0 on success, a negative errno value otherwise and rte_errno is set.
1755 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
1756 const struct rte_flow_action *action,
1757 uint64_t action_flags,
1758 const struct rte_flow_attr *attr,
1759 struct rte_flow_error *error)
1761 const struct rte_flow_action_set_tag *conf;
1762 const uint64_t terminal_action_flags =
1763 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
1764 MLX5_FLOW_ACTION_RSS;
1767 if (!mlx5_flow_ext_mreg_supported(dev))
1768 return rte_flow_error_set(error, ENOTSUP,
1769 RTE_FLOW_ERROR_TYPE_ACTION, action,
1770 "extensive metadata register"
1771 " isn't supported");
1772 if (!(action->conf))
1773 return rte_flow_error_set(error, EINVAL,
1774 RTE_FLOW_ERROR_TYPE_ACTION, action,
1775 "configuration cannot be null");
1776 conf = (const struct rte_flow_action_set_tag *)action->conf;
1778 return rte_flow_error_set(error, EINVAL,
1779 RTE_FLOW_ERROR_TYPE_ACTION, action,
1780 "zero mask doesn't have any effect");
1781 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1784 if (!attr->transfer && attr->ingress &&
1785 (action_flags & terminal_action_flags))
1786 return rte_flow_error_set(error, EINVAL,
1787 RTE_FLOW_ERROR_TYPE_ACTION, action,
1788 "set_tag has no effect"
1789 " with terminal actions");
1794 * Validate count action.
1799 * Pointer to error structure.
1802 * 0 on success, a negative errno value otherwise and rte_errno is set.
1805 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1806 struct rte_flow_error *error)
1808 struct mlx5_priv *priv = dev->data->dev_private;
1810 if (!priv->config.devx)
1812 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1816 return rte_flow_error_set
1818 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1820 "count action not supported");
1824 * Validate the L2 encap action.
1826 * @param[in] action_flags
1827 * Holds the actions detected until now.
1829 * Pointer to the encap action.
1831 * Pointer to flow attributes
1833 * Pointer to error structure.
1836 * 0 on success, a negative errno value otherwise and rte_errno is set.
1839 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1840 const struct rte_flow_action *action,
1841 const struct rte_flow_attr *attr,
1842 struct rte_flow_error *error)
1844 if (!(action->conf))
1845 return rte_flow_error_set(error, EINVAL,
1846 RTE_FLOW_ERROR_TYPE_ACTION, action,
1847 "configuration cannot be null");
1848 if (action_flags & MLX5_FLOW_ACTION_DROP)
1849 return rte_flow_error_set(error, EINVAL,
1850 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1851 "can't drop and encap in same flow");
1852 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1853 return rte_flow_error_set(error, EINVAL,
1854 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1855 "can only have a single encap or"
1856 " decap action in a flow");
1857 if (!attr->transfer && attr->ingress)
1858 return rte_flow_error_set(error, ENOTSUP,
1859 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1861 "encap action not supported for "
1867 * Validate the L2 decap action.
1869 * @param[in] action_flags
1870 * Holds the actions detected until now.
1872 * Pointer to flow attributes
1874 * Pointer to error structure.
1877 * 0 on success, a negative errno value otherwise and rte_errno is set.
1880 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1881 const struct rte_flow_attr *attr,
1882 struct rte_flow_error *error)
1884 if (action_flags & MLX5_FLOW_ACTION_DROP)
1885 return rte_flow_error_set(error, EINVAL,
1886 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1887 "can't drop and decap in same flow");
1888 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1889 return rte_flow_error_set(error, EINVAL,
1890 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1891 "can only have a single encap or"
1892 " decap action in a flow");
1893 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1894 return rte_flow_error_set(error, EINVAL,
1895 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1896 "can't have decap action after"
1899 return rte_flow_error_set(error, ENOTSUP,
1900 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1902 "decap action not supported for "
1908 * Validate the raw encap action.
1910 * @param[in] action_flags
1911 * Holds the actions detected until now.
1913 * Pointer to the encap action.
1915 * Pointer to flow attributes
1917 * Pointer to error structure.
1920 * 0 on success, a negative errno value otherwise and rte_errno is set.
1923 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1924 const struct rte_flow_action *action,
1925 const struct rte_flow_attr *attr,
1926 struct rte_flow_error *error)
1928 const struct rte_flow_action_raw_encap *raw_encap =
1929 (const struct rte_flow_action_raw_encap *)action->conf;
1930 if (!(action->conf))
1931 return rte_flow_error_set(error, EINVAL,
1932 RTE_FLOW_ERROR_TYPE_ACTION, action,
1933 "configuration cannot be null");
1934 if (action_flags & MLX5_FLOW_ACTION_DROP)
1935 return rte_flow_error_set(error, EINVAL,
1936 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1937 "can't drop and encap in same flow");
1938 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1939 return rte_flow_error_set(error, EINVAL,
1940 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1941 "can only have a single encap"
1942 " action in a flow");
1943 /* encap without preceding decap is not supported for ingress */
1944 if (!attr->transfer && attr->ingress &&
1945 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1946 return rte_flow_error_set(error, ENOTSUP,
1947 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1949 "encap action not supported for "
1951 if (!raw_encap->size || !raw_encap->data)
1952 return rte_flow_error_set(error, EINVAL,
1953 RTE_FLOW_ERROR_TYPE_ACTION, action,
1954 "raw encap data cannot be empty");
1959 * Validate the raw decap action.
1961 * @param[in] action_flags
1962 * Holds the actions detected until now.
1964 * Pointer to the encap action.
1966 * Pointer to flow attributes
1968 * Pointer to error structure.
1971 * 0 on success, a negative errno value otherwise and rte_errno is set.
1974 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1975 const struct rte_flow_action *action,
1976 const struct rte_flow_attr *attr,
1977 struct rte_flow_error *error)
1979 if (action_flags & MLX5_FLOW_ACTION_DROP)
1980 return rte_flow_error_set(error, EINVAL,
1981 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1982 "can't drop and decap in same flow");
1983 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1984 return rte_flow_error_set(error, EINVAL,
1985 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1986 "can't have encap action before"
1988 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1989 return rte_flow_error_set(error, EINVAL,
1990 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1991 "can only have a single decap"
1992 " action in a flow");
1993 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1994 return rte_flow_error_set(error, EINVAL,
1995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1996 "can't have decap action after"
1998 /* decap action is valid on egress only if it is followed by encap */
2000 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
2001 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
2004 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
2005 return rte_flow_error_set
2007 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2008 NULL, "decap action not supported"
2015 * Find existing encap/decap resource or create and register a new one.
2017 * @param dev[in, out]
2018 * Pointer to rte_eth_dev structure.
2019 * @param[in, out] resource
2020 * Pointer to encap/decap resource.
2021 * @parm[in, out] dev_flow
2022 * Pointer to the dev_flow.
2024 * pointer to error structure.
2027 * 0 on success otherwise -errno and errno is set.
2030 flow_dv_encap_decap_resource_register
2031 (struct rte_eth_dev *dev,
2032 struct mlx5_flow_dv_encap_decap_resource *resource,
2033 struct mlx5_flow *dev_flow,
2034 struct rte_flow_error *error)
2036 struct mlx5_priv *priv = dev->data->dev_private;
2037 struct mlx5_ibv_shared *sh = priv->sh;
2038 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2039 struct mlx5dv_dr_domain *domain;
2041 resource->flags = dev_flow->group ? 0 : 1;
2042 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2043 domain = sh->fdb_domain;
2044 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2045 domain = sh->rx_domain;
2047 domain = sh->tx_domain;
2049 /* Lookup a matching resource from cache. */
2050 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2051 if (resource->reformat_type == cache_resource->reformat_type &&
2052 resource->ft_type == cache_resource->ft_type &&
2053 resource->flags == cache_resource->flags &&
2054 resource->size == cache_resource->size &&
2055 !memcmp((const void *)resource->buf,
2056 (const void *)cache_resource->buf,
2058 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2059 (void *)cache_resource,
2060 rte_atomic32_read(&cache_resource->refcnt));
2061 rte_atomic32_inc(&cache_resource->refcnt);
2062 dev_flow->dv.encap_decap = cache_resource;
2066 /* Register new encap/decap resource. */
2067 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2068 if (!cache_resource)
2069 return rte_flow_error_set(error, ENOMEM,
2070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2071 "cannot allocate resource memory");
2072 *cache_resource = *resource;
2073 cache_resource->verbs_action =
2074 mlx5_glue->dv_create_flow_action_packet_reformat
2075 (sh->ctx, cache_resource->reformat_type,
2076 cache_resource->ft_type, domain, cache_resource->flags,
2077 cache_resource->size,
2078 (cache_resource->size ? cache_resource->buf : NULL));
2079 if (!cache_resource->verbs_action) {
2080 rte_free(cache_resource);
2081 return rte_flow_error_set(error, ENOMEM,
2082 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2083 NULL, "cannot create action");
2085 rte_atomic32_init(&cache_resource->refcnt);
2086 rte_atomic32_inc(&cache_resource->refcnt);
2087 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2088 dev_flow->dv.encap_decap = cache_resource;
2089 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2090 (void *)cache_resource,
2091 rte_atomic32_read(&cache_resource->refcnt));
2096 * Find existing table jump resource or create and register a new one.
2098 * @param dev[in, out]
2099 * Pointer to rte_eth_dev structure.
2100 * @param[in, out] resource
2101 * Pointer to jump table resource.
2102 * @parm[in, out] dev_flow
2103 * Pointer to the dev_flow.
2105 * pointer to error structure.
2108 * 0 on success otherwise -errno and errno is set.
2111 flow_dv_jump_tbl_resource_register
2112 (struct rte_eth_dev *dev,
2113 struct mlx5_flow_dv_jump_tbl_resource *resource,
2114 struct mlx5_flow *dev_flow,
2115 struct rte_flow_error *error)
2117 struct mlx5_priv *priv = dev->data->dev_private;
2118 struct mlx5_ibv_shared *sh = priv->sh;
2119 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
2121 /* Lookup a matching resource from cache. */
2122 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
2123 if (resource->tbl == cache_resource->tbl) {
2124 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
2125 (void *)cache_resource,
2126 rte_atomic32_read(&cache_resource->refcnt));
2127 rte_atomic32_inc(&cache_resource->refcnt);
2128 dev_flow->dv.jump = cache_resource;
2132 /* Register new jump table resource. */
2133 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2134 if (!cache_resource)
2135 return rte_flow_error_set(error, ENOMEM,
2136 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2137 "cannot allocate resource memory");
2138 *cache_resource = *resource;
2139 cache_resource->action =
2140 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2141 (resource->tbl->obj);
2142 if (!cache_resource->action) {
2143 rte_free(cache_resource);
2144 return rte_flow_error_set(error, ENOMEM,
2145 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2146 NULL, "cannot create action");
2148 rte_atomic32_init(&cache_resource->refcnt);
2149 rte_atomic32_inc(&cache_resource->refcnt);
2150 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
2151 dev_flow->dv.jump = cache_resource;
2152 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2153 (void *)cache_resource,
2154 rte_atomic32_read(&cache_resource->refcnt));
2159 * Find existing table port ID resource or create and register a new one.
2161 * @param dev[in, out]
2162 * Pointer to rte_eth_dev structure.
2163 * @param[in, out] resource
2164 * Pointer to port ID action resource.
2165 * @parm[in, out] dev_flow
2166 * Pointer to the dev_flow.
2168 * pointer to error structure.
2171 * 0 on success otherwise -errno and errno is set.
2174 flow_dv_port_id_action_resource_register
2175 (struct rte_eth_dev *dev,
2176 struct mlx5_flow_dv_port_id_action_resource *resource,
2177 struct mlx5_flow *dev_flow,
2178 struct rte_flow_error *error)
2180 struct mlx5_priv *priv = dev->data->dev_private;
2181 struct mlx5_ibv_shared *sh = priv->sh;
2182 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2184 /* Lookup a matching resource from cache. */
2185 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2186 if (resource->port_id == cache_resource->port_id) {
2187 DRV_LOG(DEBUG, "port id action resource resource %p: "
2189 (void *)cache_resource,
2190 rte_atomic32_read(&cache_resource->refcnt));
2191 rte_atomic32_inc(&cache_resource->refcnt);
2192 dev_flow->dv.port_id_action = cache_resource;
2196 /* Register new port id action resource. */
2197 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2198 if (!cache_resource)
2199 return rte_flow_error_set(error, ENOMEM,
2200 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2201 "cannot allocate resource memory");
2202 *cache_resource = *resource;
2203 cache_resource->action =
2204 mlx5_glue->dr_create_flow_action_dest_vport
2205 (priv->sh->fdb_domain, resource->port_id);
2206 if (!cache_resource->action) {
2207 rte_free(cache_resource);
2208 return rte_flow_error_set(error, ENOMEM,
2209 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2210 NULL, "cannot create action");
2212 rte_atomic32_init(&cache_resource->refcnt);
2213 rte_atomic32_inc(&cache_resource->refcnt);
2214 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2215 dev_flow->dv.port_id_action = cache_resource;
2216 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2217 (void *)cache_resource,
2218 rte_atomic32_read(&cache_resource->refcnt));
2223 * Find existing push vlan resource or create and register a new one.
2225 * @param dev[in, out]
2226 * Pointer to rte_eth_dev structure.
2227 * @param[in, out] resource
2228 * Pointer to port ID action resource.
2229 * @parm[in, out] dev_flow
2230 * Pointer to the dev_flow.
2232 * pointer to error structure.
2235 * 0 on success otherwise -errno and errno is set.
2238 flow_dv_push_vlan_action_resource_register
2239 (struct rte_eth_dev *dev,
2240 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2241 struct mlx5_flow *dev_flow,
2242 struct rte_flow_error *error)
2244 struct mlx5_priv *priv = dev->data->dev_private;
2245 struct mlx5_ibv_shared *sh = priv->sh;
2246 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2247 struct mlx5dv_dr_domain *domain;
2249 /* Lookup a matching resource from cache. */
2250 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2251 if (resource->vlan_tag == cache_resource->vlan_tag &&
2252 resource->ft_type == cache_resource->ft_type) {
2253 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2255 (void *)cache_resource,
2256 rte_atomic32_read(&cache_resource->refcnt));
2257 rte_atomic32_inc(&cache_resource->refcnt);
2258 dev_flow->dv.push_vlan_res = cache_resource;
2262 /* Register new push_vlan action resource. */
2263 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2264 if (!cache_resource)
2265 return rte_flow_error_set(error, ENOMEM,
2266 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2267 "cannot allocate resource memory");
2268 *cache_resource = *resource;
2269 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2270 domain = sh->fdb_domain;
2271 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2272 domain = sh->rx_domain;
2274 domain = sh->tx_domain;
2275 cache_resource->action =
2276 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2277 resource->vlan_tag);
2278 if (!cache_resource->action) {
2279 rte_free(cache_resource);
2280 return rte_flow_error_set(error, ENOMEM,
2281 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2282 NULL, "cannot create action");
2284 rte_atomic32_init(&cache_resource->refcnt);
2285 rte_atomic32_inc(&cache_resource->refcnt);
2286 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2287 dev_flow->dv.push_vlan_res = cache_resource;
2288 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2289 (void *)cache_resource,
2290 rte_atomic32_read(&cache_resource->refcnt));
2294 * Get the size of specific rte_flow_item_type
2296 * @param[in] item_type
2297 * Tested rte_flow_item_type.
2300 * sizeof struct item_type, 0 if void or irrelevant.
2303 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2307 switch (item_type) {
2308 case RTE_FLOW_ITEM_TYPE_ETH:
2309 retval = sizeof(struct rte_flow_item_eth);
2311 case RTE_FLOW_ITEM_TYPE_VLAN:
2312 retval = sizeof(struct rte_flow_item_vlan);
2314 case RTE_FLOW_ITEM_TYPE_IPV4:
2315 retval = sizeof(struct rte_flow_item_ipv4);
2317 case RTE_FLOW_ITEM_TYPE_IPV6:
2318 retval = sizeof(struct rte_flow_item_ipv6);
2320 case RTE_FLOW_ITEM_TYPE_UDP:
2321 retval = sizeof(struct rte_flow_item_udp);
2323 case RTE_FLOW_ITEM_TYPE_TCP:
2324 retval = sizeof(struct rte_flow_item_tcp);
2326 case RTE_FLOW_ITEM_TYPE_VXLAN:
2327 retval = sizeof(struct rte_flow_item_vxlan);
2329 case RTE_FLOW_ITEM_TYPE_GRE:
2330 retval = sizeof(struct rte_flow_item_gre);
2332 case RTE_FLOW_ITEM_TYPE_NVGRE:
2333 retval = sizeof(struct rte_flow_item_nvgre);
2335 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2336 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2338 case RTE_FLOW_ITEM_TYPE_MPLS:
2339 retval = sizeof(struct rte_flow_item_mpls);
2341 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2349 #define MLX5_ENCAP_IPV4_VERSION 0x40
2350 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2351 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2352 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2353 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2354 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2355 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2358 * Convert the encap action data from list of rte_flow_item to raw buffer
2361 * Pointer to rte_flow_item objects list.
2363 * Pointer to the output buffer.
2365 * Pointer to the output buffer size.
2367 * Pointer to the error structure.
2370 * 0 on success, a negative errno value otherwise and rte_errno is set.
2373 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2374 size_t *size, struct rte_flow_error *error)
2376 struct rte_ether_hdr *eth = NULL;
2377 struct rte_vlan_hdr *vlan = NULL;
2378 struct rte_ipv4_hdr *ipv4 = NULL;
2379 struct rte_ipv6_hdr *ipv6 = NULL;
2380 struct rte_udp_hdr *udp = NULL;
2381 struct rte_vxlan_hdr *vxlan = NULL;
2382 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2383 struct rte_gre_hdr *gre = NULL;
2385 size_t temp_size = 0;
2388 return rte_flow_error_set(error, EINVAL,
2389 RTE_FLOW_ERROR_TYPE_ACTION,
2390 NULL, "invalid empty data");
2391 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2392 len = flow_dv_get_item_len(items->type);
2393 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2394 return rte_flow_error_set(error, EINVAL,
2395 RTE_FLOW_ERROR_TYPE_ACTION,
2396 (void *)items->type,
2397 "items total size is too big"
2398 " for encap action");
2399 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2400 switch (items->type) {
2401 case RTE_FLOW_ITEM_TYPE_ETH:
2402 eth = (struct rte_ether_hdr *)&buf[temp_size];
2404 case RTE_FLOW_ITEM_TYPE_VLAN:
2405 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2407 return rte_flow_error_set(error, EINVAL,
2408 RTE_FLOW_ERROR_TYPE_ACTION,
2409 (void *)items->type,
2410 "eth header not found");
2411 if (!eth->ether_type)
2412 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2414 case RTE_FLOW_ITEM_TYPE_IPV4:
2415 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2417 return rte_flow_error_set(error, EINVAL,
2418 RTE_FLOW_ERROR_TYPE_ACTION,
2419 (void *)items->type,
2420 "neither eth nor vlan"
2422 if (vlan && !vlan->eth_proto)
2423 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2424 else if (eth && !eth->ether_type)
2425 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2426 if (!ipv4->version_ihl)
2427 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2428 MLX5_ENCAP_IPV4_IHL_MIN;
2429 if (!ipv4->time_to_live)
2430 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2432 case RTE_FLOW_ITEM_TYPE_IPV6:
2433 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2435 return rte_flow_error_set(error, EINVAL,
2436 RTE_FLOW_ERROR_TYPE_ACTION,
2437 (void *)items->type,
2438 "neither eth nor vlan"
2440 if (vlan && !vlan->eth_proto)
2441 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2442 else if (eth && !eth->ether_type)
2443 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2444 if (!ipv6->vtc_flow)
2446 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2447 if (!ipv6->hop_limits)
2448 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2450 case RTE_FLOW_ITEM_TYPE_UDP:
2451 udp = (struct rte_udp_hdr *)&buf[temp_size];
2453 return rte_flow_error_set(error, EINVAL,
2454 RTE_FLOW_ERROR_TYPE_ACTION,
2455 (void *)items->type,
2456 "ip header not found");
2457 if (ipv4 && !ipv4->next_proto_id)
2458 ipv4->next_proto_id = IPPROTO_UDP;
2459 else if (ipv6 && !ipv6->proto)
2460 ipv6->proto = IPPROTO_UDP;
2462 case RTE_FLOW_ITEM_TYPE_VXLAN:
2463 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2465 return rte_flow_error_set(error, EINVAL,
2466 RTE_FLOW_ERROR_TYPE_ACTION,
2467 (void *)items->type,
2468 "udp header not found");
2470 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2471 if (!vxlan->vx_flags)
2473 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2475 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2476 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2478 return rte_flow_error_set(error, EINVAL,
2479 RTE_FLOW_ERROR_TYPE_ACTION,
2480 (void *)items->type,
2481 "udp header not found");
2482 if (!vxlan_gpe->proto)
2483 return rte_flow_error_set(error, EINVAL,
2484 RTE_FLOW_ERROR_TYPE_ACTION,
2485 (void *)items->type,
2486 "next protocol not found");
2489 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2490 if (!vxlan_gpe->vx_flags)
2491 vxlan_gpe->vx_flags =
2492 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2494 case RTE_FLOW_ITEM_TYPE_GRE:
2495 case RTE_FLOW_ITEM_TYPE_NVGRE:
2496 gre = (struct rte_gre_hdr *)&buf[temp_size];
2498 return rte_flow_error_set(error, EINVAL,
2499 RTE_FLOW_ERROR_TYPE_ACTION,
2500 (void *)items->type,
2501 "next protocol not found");
2503 return rte_flow_error_set(error, EINVAL,
2504 RTE_FLOW_ERROR_TYPE_ACTION,
2505 (void *)items->type,
2506 "ip header not found");
2507 if (ipv4 && !ipv4->next_proto_id)
2508 ipv4->next_proto_id = IPPROTO_GRE;
2509 else if (ipv6 && !ipv6->proto)
2510 ipv6->proto = IPPROTO_GRE;
2512 case RTE_FLOW_ITEM_TYPE_VOID:
2515 return rte_flow_error_set(error, EINVAL,
2516 RTE_FLOW_ERROR_TYPE_ACTION,
2517 (void *)items->type,
2518 "unsupported item type");
2528 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2530 struct rte_ether_hdr *eth = NULL;
2531 struct rte_vlan_hdr *vlan = NULL;
2532 struct rte_ipv6_hdr *ipv6 = NULL;
2533 struct rte_udp_hdr *udp = NULL;
2537 eth = (struct rte_ether_hdr *)data;
2538 next_hdr = (char *)(eth + 1);
2539 proto = RTE_BE16(eth->ether_type);
2542 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2543 vlan = (struct rte_vlan_hdr *)next_hdr;
2544 proto = RTE_BE16(vlan->eth_proto);
2545 next_hdr += sizeof(struct rte_vlan_hdr);
2548 /* HW calculates IPv4 csum. no need to proceed */
2549 if (proto == RTE_ETHER_TYPE_IPV4)
2552 /* non IPv4/IPv6 header. not supported */
2553 if (proto != RTE_ETHER_TYPE_IPV6) {
2554 return rte_flow_error_set(error, ENOTSUP,
2555 RTE_FLOW_ERROR_TYPE_ACTION,
2556 NULL, "Cannot offload non IPv4/IPv6");
2559 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2561 /* ignore non UDP */
2562 if (ipv6->proto != IPPROTO_UDP)
2565 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2566 udp->dgram_cksum = 0;
2572 * Convert L2 encap action to DV specification.
2575 * Pointer to rte_eth_dev structure.
2577 * Pointer to action structure.
2578 * @param[in, out] dev_flow
2579 * Pointer to the mlx5_flow.
2580 * @param[in] transfer
2581 * Mark if the flow is E-Switch flow.
2583 * Pointer to the error structure.
2586 * 0 on success, a negative errno value otherwise and rte_errno is set.
2589 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2590 const struct rte_flow_action *action,
2591 struct mlx5_flow *dev_flow,
2593 struct rte_flow_error *error)
2595 const struct rte_flow_item *encap_data;
2596 const struct rte_flow_action_raw_encap *raw_encap_data;
2597 struct mlx5_flow_dv_encap_decap_resource res = {
2599 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2600 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2601 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2604 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2606 (const struct rte_flow_action_raw_encap *)action->conf;
2607 res.size = raw_encap_data->size;
2608 memcpy(res.buf, raw_encap_data->data, res.size);
2609 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2612 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2614 ((const struct rte_flow_action_vxlan_encap *)
2615 action->conf)->definition;
2618 ((const struct rte_flow_action_nvgre_encap *)
2619 action->conf)->definition;
2620 if (flow_dv_convert_encap_data(encap_data, res.buf,
2624 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2625 return rte_flow_error_set(error, EINVAL,
2626 RTE_FLOW_ERROR_TYPE_ACTION,
2627 NULL, "can't create L2 encap action");
2632 * Convert L2 decap action to DV specification.
2635 * Pointer to rte_eth_dev structure.
2636 * @param[in, out] dev_flow
2637 * Pointer to the mlx5_flow.
2638 * @param[in] transfer
2639 * Mark if the flow is E-Switch flow.
2641 * Pointer to the error structure.
2644 * 0 on success, a negative errno value otherwise and rte_errno is set.
2647 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2648 struct mlx5_flow *dev_flow,
2650 struct rte_flow_error *error)
2652 struct mlx5_flow_dv_encap_decap_resource res = {
2655 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2656 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2657 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2660 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2661 return rte_flow_error_set(error, EINVAL,
2662 RTE_FLOW_ERROR_TYPE_ACTION,
2663 NULL, "can't create L2 decap action");
2668 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2671 * Pointer to rte_eth_dev structure.
2673 * Pointer to action structure.
2674 * @param[in, out] dev_flow
2675 * Pointer to the mlx5_flow.
2677 * Pointer to the flow attributes.
2679 * Pointer to the error structure.
2682 * 0 on success, a negative errno value otherwise and rte_errno is set.
2685 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2686 const struct rte_flow_action *action,
2687 struct mlx5_flow *dev_flow,
2688 const struct rte_flow_attr *attr,
2689 struct rte_flow_error *error)
2691 const struct rte_flow_action_raw_encap *encap_data;
2692 struct mlx5_flow_dv_encap_decap_resource res;
2694 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2695 res.size = encap_data->size;
2696 memcpy(res.buf, encap_data->data, res.size);
2697 res.reformat_type = attr->egress ?
2698 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2699 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2701 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2703 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2704 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2705 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2706 return rte_flow_error_set(error, EINVAL,
2707 RTE_FLOW_ERROR_TYPE_ACTION,
2708 NULL, "can't create encap action");
2713 * Create action push VLAN.
2716 * Pointer to rte_eth_dev structure.
2717 * @param[in] vlan_tag
2718 * the vlan tag to push to the Ethernet header.
2719 * @param[in, out] dev_flow
2720 * Pointer to the mlx5_flow.
2722 * Pointer to the flow attributes.
2724 * Pointer to the error structure.
2727 * 0 on success, a negative errno value otherwise and rte_errno is set.
2730 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2731 const struct rte_flow_attr *attr,
2732 const struct rte_vlan_hdr *vlan,
2733 struct mlx5_flow *dev_flow,
2734 struct rte_flow_error *error)
2736 struct mlx5_flow_dv_push_vlan_action_resource res;
2739 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2742 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2744 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2745 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2746 return flow_dv_push_vlan_action_resource_register
2747 (dev, &res, dev_flow, error);
2751 * Validate the modify-header actions.
2753 * @param[in] action_flags
2754 * Holds the actions detected until now.
2756 * Pointer to the modify action.
2758 * Pointer to error structure.
2761 * 0 on success, a negative errno value otherwise and rte_errno is set.
2764 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2765 const struct rte_flow_action *action,
2766 struct rte_flow_error *error)
2768 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2769 return rte_flow_error_set(error, EINVAL,
2770 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2771 NULL, "action configuration not set");
2772 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2773 return rte_flow_error_set(error, EINVAL,
2774 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2775 "can't have encap action before"
2781 * Validate the modify-header MAC address actions.
2783 * @param[in] action_flags
2784 * Holds the actions detected until now.
2786 * Pointer to the modify action.
2787 * @param[in] item_flags
2788 * Holds the items detected.
2790 * Pointer to error structure.
2793 * 0 on success, a negative errno value otherwise and rte_errno is set.
2796 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2797 const struct rte_flow_action *action,
2798 const uint64_t item_flags,
2799 struct rte_flow_error *error)
2803 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2805 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2806 return rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ACTION,
2809 "no L2 item in pattern");
2815 * Validate the modify-header IPv4 address actions.
2817 * @param[in] action_flags
2818 * Holds the actions detected until now.
2820 * Pointer to the modify action.
2821 * @param[in] item_flags
2822 * Holds the items detected.
2824 * Pointer to error structure.
2827 * 0 on success, a negative errno value otherwise and rte_errno is set.
2830 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2831 const struct rte_flow_action *action,
2832 const uint64_t item_flags,
2833 struct rte_flow_error *error)
2837 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2839 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2840 return rte_flow_error_set(error, EINVAL,
2841 RTE_FLOW_ERROR_TYPE_ACTION,
2843 "no ipv4 item in pattern");
2849 * Validate the modify-header IPv6 address actions.
2851 * @param[in] action_flags
2852 * Holds the actions detected until now.
2854 * Pointer to the modify action.
2855 * @param[in] item_flags
2856 * Holds the items detected.
2858 * Pointer to error structure.
2861 * 0 on success, a negative errno value otherwise and rte_errno is set.
2864 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2865 const struct rte_flow_action *action,
2866 const uint64_t item_flags,
2867 struct rte_flow_error *error)
2871 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2873 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2874 return rte_flow_error_set(error, EINVAL,
2875 RTE_FLOW_ERROR_TYPE_ACTION,
2877 "no ipv6 item in pattern");
2883 * Validate the modify-header TP actions.
2885 * @param[in] action_flags
2886 * Holds the actions detected until now.
2888 * Pointer to the modify action.
2889 * @param[in] item_flags
2890 * Holds the items detected.
2892 * Pointer to error structure.
2895 * 0 on success, a negative errno value otherwise and rte_errno is set.
2898 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2899 const struct rte_flow_action *action,
2900 const uint64_t item_flags,
2901 struct rte_flow_error *error)
2905 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2907 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2908 return rte_flow_error_set(error, EINVAL,
2909 RTE_FLOW_ERROR_TYPE_ACTION,
2910 NULL, "no transport layer "
2917 * Validate the modify-header actions of increment/decrement
2918 * TCP Sequence-number.
2920 * @param[in] action_flags
2921 * Holds the actions detected until now.
2923 * Pointer to the modify action.
2924 * @param[in] item_flags
2925 * Holds the items detected.
2927 * Pointer to error structure.
2930 * 0 on success, a negative errno value otherwise and rte_errno is set.
2933 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2934 const struct rte_flow_action *action,
2935 const uint64_t item_flags,
2936 struct rte_flow_error *error)
2940 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2942 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2943 return rte_flow_error_set(error, EINVAL,
2944 RTE_FLOW_ERROR_TYPE_ACTION,
2945 NULL, "no TCP item in"
2947 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2948 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2949 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2950 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2951 return rte_flow_error_set(error, EINVAL,
2952 RTE_FLOW_ERROR_TYPE_ACTION,
2954 "cannot decrease and increase"
2955 " TCP sequence number"
2956 " at the same time");
2962 * Validate the modify-header actions of increment/decrement
2963 * TCP Acknowledgment number.
2965 * @param[in] action_flags
2966 * Holds the actions detected until now.
2968 * Pointer to the modify action.
2969 * @param[in] item_flags
2970 * Holds the items detected.
2972 * Pointer to error structure.
2975 * 0 on success, a negative errno value otherwise and rte_errno is set.
2978 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2979 const struct rte_flow_action *action,
2980 const uint64_t item_flags,
2981 struct rte_flow_error *error)
2985 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2987 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2988 return rte_flow_error_set(error, EINVAL,
2989 RTE_FLOW_ERROR_TYPE_ACTION,
2990 NULL, "no TCP item in"
2992 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2993 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2994 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2995 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2996 return rte_flow_error_set(error, EINVAL,
2997 RTE_FLOW_ERROR_TYPE_ACTION,
2999 "cannot decrease and increase"
3000 " TCP acknowledgment number"
3001 " at the same time");
3007 * Validate the modify-header TTL actions.
3009 * @param[in] action_flags
3010 * Holds the actions detected until now.
3012 * Pointer to the modify action.
3013 * @param[in] item_flags
3014 * Holds the items detected.
3016 * Pointer to error structure.
3019 * 0 on success, a negative errno value otherwise and rte_errno is set.
3022 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3023 const struct rte_flow_action *action,
3024 const uint64_t item_flags,
3025 struct rte_flow_error *error)
3029 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3031 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3032 return rte_flow_error_set(error, EINVAL,
3033 RTE_FLOW_ERROR_TYPE_ACTION,
3035 "no IP protocol in pattern");
3041 * Validate jump action.
3044 * Pointer to the jump action.
3045 * @param[in] action_flags
3046 * Holds the actions detected until now.
3047 * @param[in] attributes
3048 * Pointer to flow attributes
3049 * @param[in] external
3050 * Action belongs to flow rule created by request external to PMD.
3052 * Pointer to error structure.
3055 * 0 on success, a negative errno value otherwise and rte_errno is set.
3058 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3059 uint64_t action_flags,
3060 const struct rte_flow_attr *attributes,
3061 bool external, struct rte_flow_error *error)
3063 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3065 uint32_t target_group, table;
3068 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3069 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3070 return rte_flow_error_set(error, EINVAL,
3071 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3072 "can't have 2 fate actions in"
3075 return rte_flow_error_set(error, EINVAL,
3076 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3077 NULL, "action configuration not set");
3079 ((const struct rte_flow_action_jump *)action->conf)->group;
3080 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3084 if (table >= max_group)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3087 "target group index out of range");
3088 if (attributes->group >= target_group)
3089 return rte_flow_error_set(error, EINVAL,
3090 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3091 "target group must be higher than"
3092 " the current flow group");
3097 * Validate the port_id action.
3100 * Pointer to rte_eth_dev structure.
3101 * @param[in] action_flags
3102 * Bit-fields that holds the actions detected until now.
3104 * Port_id RTE action structure.
3106 * Attributes of flow that includes this action.
3108 * Pointer to error structure.
3111 * 0 on success, a negative errno value otherwise and rte_errno is set.
3114 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3115 uint64_t action_flags,
3116 const struct rte_flow_action *action,
3117 const struct rte_flow_attr *attr,
3118 struct rte_flow_error *error)
3120 const struct rte_flow_action_port_id *port_id;
3121 struct mlx5_priv *act_priv;
3122 struct mlx5_priv *dev_priv;
3125 if (!attr->transfer)
3126 return rte_flow_error_set(error, ENOTSUP,
3127 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3129 "port id action is valid in transfer"
3131 if (!action || !action->conf)
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3135 "port id action parameters must be"
3137 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3138 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3139 return rte_flow_error_set(error, EINVAL,
3140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3141 "can have only one fate actions in"
3143 dev_priv = mlx5_dev_to_eswitch_info(dev);
3145 return rte_flow_error_set(error, rte_errno,
3146 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3148 "failed to obtain E-Switch info");
3149 port_id = action->conf;
3150 port = port_id->original ? dev->data->port_id : port_id->id;
3151 act_priv = mlx5_port_to_eswitch_info(port, false);
3153 return rte_flow_error_set
3155 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3156 "failed to obtain E-Switch port id for port");
3157 if (act_priv->domain_id != dev_priv->domain_id)
3158 return rte_flow_error_set
3160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3161 "port does not belong to"
3162 " E-Switch being configured");
3167 * Get the maximum number of modify header actions.
3170 * Pointer to rte_eth_dev structure.
3173 * Max number of modify header actions device can support.
3176 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev)
3179 * There's no way to directly query the max cap. Although it has to be
3180 * acquried by iterative trial, it is a safe assumption that more
3181 * actions are supported by FW if extensive metadata register is
3184 return mlx5_flow_ext_mreg_supported(dev) ? MLX5_MODIFY_NUM :
3185 MLX5_MODIFY_NUM_NO_MREG;
3188 * Find existing modify-header resource or create and register a new one.
3190 * @param dev[in, out]
3191 * Pointer to rte_eth_dev structure.
3192 * @param[in, out] resource
3193 * Pointer to modify-header resource.
3194 * @parm[in, out] dev_flow
3195 * Pointer to the dev_flow.
3197 * pointer to error structure.
3200 * 0 on success otherwise -errno and errno is set.
3203 flow_dv_modify_hdr_resource_register
3204 (struct rte_eth_dev *dev,
3205 struct mlx5_flow_dv_modify_hdr_resource *resource,
3206 struct mlx5_flow *dev_flow,
3207 struct rte_flow_error *error)
3209 struct mlx5_priv *priv = dev->data->dev_private;
3210 struct mlx5_ibv_shared *sh = priv->sh;
3211 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3212 struct mlx5dv_dr_domain *ns;
3214 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev))
3215 return rte_flow_error_set(error, EOVERFLOW,
3216 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3217 "too many modify header items");
3218 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3219 ns = sh->fdb_domain;
3220 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3225 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3226 /* Lookup a matching resource from cache. */
3227 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3228 if (resource->ft_type == cache_resource->ft_type &&
3229 resource->actions_num == cache_resource->actions_num &&
3230 resource->flags == cache_resource->flags &&
3231 !memcmp((const void *)resource->actions,
3232 (const void *)cache_resource->actions,
3233 (resource->actions_num *
3234 sizeof(resource->actions[0])))) {
3235 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3236 (void *)cache_resource,
3237 rte_atomic32_read(&cache_resource->refcnt));
3238 rte_atomic32_inc(&cache_resource->refcnt);
3239 dev_flow->dv.modify_hdr = cache_resource;
3243 /* Register new modify-header resource. */
3244 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
3245 if (!cache_resource)
3246 return rte_flow_error_set(error, ENOMEM,
3247 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3248 "cannot allocate resource memory");
3249 *cache_resource = *resource;
3250 cache_resource->verbs_action =
3251 mlx5_glue->dv_create_flow_action_modify_header
3252 (sh->ctx, cache_resource->ft_type,
3253 ns, cache_resource->flags,
3254 cache_resource->actions_num *
3255 sizeof(cache_resource->actions[0]),
3256 (uint64_t *)cache_resource->actions);
3257 if (!cache_resource->verbs_action) {
3258 rte_free(cache_resource);
3259 return rte_flow_error_set(error, ENOMEM,
3260 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3261 NULL, "cannot create action");
3263 rte_atomic32_init(&cache_resource->refcnt);
3264 rte_atomic32_inc(&cache_resource->refcnt);
3265 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3266 dev_flow->dv.modify_hdr = cache_resource;
3267 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3268 (void *)cache_resource,
3269 rte_atomic32_read(&cache_resource->refcnt));
3273 #define MLX5_CNT_CONTAINER_RESIZE 64
3276 * Get or create a flow counter.
3279 * Pointer to the Ethernet device structure.
3281 * Indicate if this counter is shared with other flows.
3283 * Counter identifier.
3286 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3288 static struct mlx5_flow_counter *
3289 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3292 struct mlx5_priv *priv = dev->data->dev_private;
3293 struct mlx5_flow_counter *cnt = NULL;
3294 struct mlx5_devx_obj *dcs = NULL;
3296 if (!priv->config.devx) {
3297 rte_errno = ENOTSUP;
3301 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3302 if (cnt->shared && cnt->id == id) {
3308 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3311 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3313 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3317 struct mlx5_flow_counter tmpl = {
3323 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3325 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3331 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3336 * Release a flow counter.
3339 * Pointer to the Ethernet device structure.
3340 * @param[in] counter
3341 * Pointer to the counter handler.
3344 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3345 struct mlx5_flow_counter *counter)
3347 struct mlx5_priv *priv = dev->data->dev_private;
3351 if (--counter->ref_cnt == 0) {
3352 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3353 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3359 * Query a devx flow counter.
3362 * Pointer to the Ethernet device structure.
3364 * Pointer to the flow counter.
3366 * The statistics value of packets.
3368 * The statistics value of bytes.
3371 * 0 on success, otherwise a negative errno value and rte_errno is set.
3374 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3375 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3378 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3383 * Get a pool by a counter.
3386 * Pointer to the counter.
3391 static struct mlx5_flow_counter_pool *
3392 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3395 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3396 return (struct mlx5_flow_counter_pool *)cnt - 1;
3402 * Get a pool by devx counter ID.
3405 * Pointer to the counter container.
3407 * The counter devx ID.
3410 * The counter pool pointer if exists, NULL otherwise,
3412 static struct mlx5_flow_counter_pool *
3413 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3415 struct mlx5_flow_counter_pool *pool;
3417 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3418 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3419 MLX5_COUNTERS_PER_POOL;
3421 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3428 * Allocate a new memory for the counter values wrapped by all the needed
3432 * Pointer to the Ethernet device structure.
3434 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3437 * The new memory management pointer on success, otherwise NULL and rte_errno
3440 static struct mlx5_counter_stats_mem_mng *
3441 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3443 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3444 (dev->data->dev_private))->sh;
3445 struct mlx5_devx_mkey_attr mkey_attr;
3446 struct mlx5_counter_stats_mem_mng *mem_mng;
3447 volatile struct flow_counter_stats *raw_data;
3448 int size = (sizeof(struct flow_counter_stats) *
3449 MLX5_COUNTERS_PER_POOL +
3450 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3451 sizeof(struct mlx5_counter_stats_mem_mng);
3452 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3459 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3460 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3461 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3462 IBV_ACCESS_LOCAL_WRITE);
3463 if (!mem_mng->umem) {
3468 mkey_attr.addr = (uintptr_t)mem;
3469 mkey_attr.size = size;
3470 mkey_attr.umem_id = mem_mng->umem->umem_id;
3471 mkey_attr.pd = sh->pdn;
3472 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3474 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3479 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3480 raw_data = (volatile struct flow_counter_stats *)mem;
3481 for (i = 0; i < raws_n; ++i) {
3482 mem_mng->raws[i].mem_mng = mem_mng;
3483 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3485 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3490 * Resize a counter container.
3493 * Pointer to the Ethernet device structure.
3495 * Whether the pool is for counter that was allocated by batch command.
3498 * The new container pointer on success, otherwise NULL and rte_errno is set.
3500 static struct mlx5_pools_container *
3501 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3503 struct mlx5_priv *priv = dev->data->dev_private;
3504 struct mlx5_pools_container *cont =
3505 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3506 struct mlx5_pools_container *new_cont =
3507 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3508 struct mlx5_counter_stats_mem_mng *mem_mng;
3509 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3510 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3513 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3514 /* The last resize still hasn't detected by the host thread. */
3518 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3519 if (!new_cont->pools) {
3524 memcpy(new_cont->pools, cont->pools, cont->n *
3525 sizeof(struct mlx5_flow_counter_pool *));
3526 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3527 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3529 rte_free(new_cont->pools);
3532 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3533 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3534 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3536 new_cont->n = resize;
3537 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3538 TAILQ_INIT(&new_cont->pool_list);
3539 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3540 new_cont->init_mem_mng = mem_mng;
3542 /* Flip the master container. */
3543 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3548 * Query a devx flow counter.
3551 * Pointer to the Ethernet device structure.
3553 * Pointer to the flow counter.
3555 * The statistics value of packets.
3557 * The statistics value of bytes.
3560 * 0 on success, otherwise a negative errno value and rte_errno is set.
3563 _flow_dv_query_count(struct rte_eth_dev *dev,
3564 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3567 struct mlx5_priv *priv = dev->data->dev_private;
3568 struct mlx5_flow_counter_pool *pool =
3569 flow_dv_counter_pool_get(cnt);
3570 int offset = cnt - &pool->counters_raw[0];
3572 if (priv->counter_fallback)
3573 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3575 rte_spinlock_lock(&pool->sl);
3577 * The single counters allocation may allocate smaller ID than the
3578 * current allocated in parallel to the host reading.
3579 * In this case the new counter values must be reported as 0.
3581 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3585 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3586 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3588 rte_spinlock_unlock(&pool->sl);
3593 * Create and initialize a new counter pool.
3596 * Pointer to the Ethernet device structure.
3598 * The devX counter handle.
3600 * Whether the pool is for counter that was allocated by batch command.
3603 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3605 static struct mlx5_flow_counter_pool *
3606 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3609 struct mlx5_priv *priv = dev->data->dev_private;
3610 struct mlx5_flow_counter_pool *pool;
3611 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3613 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3616 if (cont->n == n_valid) {
3617 cont = flow_dv_container_resize(dev, batch);
3621 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3622 sizeof(struct mlx5_flow_counter);
3623 pool = rte_calloc(__func__, 1, size, 0);
3628 pool->min_dcs = dcs;
3629 pool->raw = cont->init_mem_mng->raws + n_valid %
3630 MLX5_CNT_CONTAINER_RESIZE;
3631 pool->raw_hw = NULL;
3632 rte_spinlock_init(&pool->sl);
3634 * The generation of the new allocated counters in this pool is 0, 2 in
3635 * the pool generation makes all the counters valid for allocation.
3637 rte_atomic64_set(&pool->query_gen, 0x2);
3638 TAILQ_INIT(&pool->counters);
3639 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3640 cont->pools[n_valid] = pool;
3641 /* Pool initialization must be updated before host thread access. */
3643 rte_atomic16_add(&cont->n_valid, 1);
3648 * Prepare a new counter and/or a new counter pool.
3651 * Pointer to the Ethernet device structure.
3652 * @param[out] cnt_free
3653 * Where to put the pointer of a new counter.
3655 * Whether the pool is for counter that was allocated by batch command.
3658 * The free counter pool pointer and @p cnt_free is set on success,
3659 * NULL otherwise and rte_errno is set.
3661 static struct mlx5_flow_counter_pool *
3662 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3663 struct mlx5_flow_counter **cnt_free,
3666 struct mlx5_priv *priv = dev->data->dev_private;
3667 struct mlx5_flow_counter_pool *pool;
3668 struct mlx5_devx_obj *dcs = NULL;
3669 struct mlx5_flow_counter *cnt;
3673 /* bulk_bitmap must be 0 for single counter allocation. */
3674 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3677 pool = flow_dv_find_pool_by_id
3678 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3680 pool = flow_dv_pool_create(dev, dcs, batch);
3682 mlx5_devx_cmd_destroy(dcs);
3685 } else if (dcs->id < pool->min_dcs->id) {
3686 rte_atomic64_set(&pool->a64_dcs,
3687 (int64_t)(uintptr_t)dcs);
3689 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3690 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3695 /* bulk_bitmap is in 128 counters units. */
3696 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3697 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3699 rte_errno = ENODATA;
3702 pool = flow_dv_pool_create(dev, dcs, batch);
3704 mlx5_devx_cmd_destroy(dcs);
3707 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3708 cnt = &pool->counters_raw[i];
3710 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3712 *cnt_free = &pool->counters_raw[0];
3717 * Search for existed shared counter.
3720 * Pointer to the relevant counter pool container.
3722 * The shared counter ID to search.
3725 * NULL if not existed, otherwise pointer to the shared counter.
3727 static struct mlx5_flow_counter *
3728 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3731 static struct mlx5_flow_counter *cnt;
3732 struct mlx5_flow_counter_pool *pool;
3735 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3736 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3737 cnt = &pool->counters_raw[i];
3738 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3746 * Allocate a flow counter.
3749 * Pointer to the Ethernet device structure.
3751 * Indicate if this counter is shared with other flows.
3753 * Counter identifier.
3755 * Counter flow group.
3758 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3760 static struct mlx5_flow_counter *
3761 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3764 struct mlx5_priv *priv = dev->data->dev_private;
3765 struct mlx5_flow_counter_pool *pool = NULL;
3766 struct mlx5_flow_counter *cnt_free = NULL;
3768 * Currently group 0 flow counter cannot be assigned to a flow if it is
3769 * not the first one in the batch counter allocation, so it is better
3770 * to allocate counters one by one for these flows in a separate
3772 * A counter can be shared between different groups so need to take
3773 * shared counters from the single container.
3775 uint32_t batch = (group && !shared) ? 1 : 0;
3776 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3779 if (priv->counter_fallback)
3780 return flow_dv_counter_alloc_fallback(dev, shared, id);
3781 if (!priv->config.devx) {
3782 rte_errno = ENOTSUP;
3786 cnt_free = flow_dv_counter_shared_search(cont, id);
3788 if (cnt_free->ref_cnt + 1 == 0) {
3792 cnt_free->ref_cnt++;
3796 /* Pools which has a free counters are in the start. */
3797 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3799 * The free counter reset values must be updated between the
3800 * counter release to the counter allocation, so, at least one
3801 * query must be done in this time. ensure it by saving the
3802 * query generation in the release time.
3803 * The free list is sorted according to the generation - so if
3804 * the first one is not updated, all the others are not
3807 cnt_free = TAILQ_FIRST(&pool->counters);
3808 if (cnt_free && cnt_free->query_gen + 1 <
3809 rte_atomic64_read(&pool->query_gen))
3814 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3818 cnt_free->batch = batch;
3819 /* Create a DV counter action only in the first time usage. */
3820 if (!cnt_free->action) {
3822 struct mlx5_devx_obj *dcs;
3825 offset = cnt_free - &pool->counters_raw[0];
3826 dcs = pool->min_dcs;
3829 dcs = cnt_free->dcs;
3831 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3833 if (!cnt_free->action) {
3838 /* Update the counter reset values. */
3839 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3842 cnt_free->shared = shared;
3843 cnt_free->ref_cnt = 1;
3845 if (!priv->sh->cmng.query_thread_on)
3846 /* Start the asynchronous batch query by the host thread. */
3847 mlx5_set_query_alarm(priv->sh);
3848 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3849 if (TAILQ_EMPTY(&pool->counters)) {
3850 /* Move the pool to the end of the container pool list. */
3851 TAILQ_REMOVE(&cont->pool_list, pool, next);
3852 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3858 * Release a flow counter.
3861 * Pointer to the Ethernet device structure.
3862 * @param[in] counter
3863 * Pointer to the counter handler.
3866 flow_dv_counter_release(struct rte_eth_dev *dev,
3867 struct mlx5_flow_counter *counter)
3869 struct mlx5_priv *priv = dev->data->dev_private;
3873 if (priv->counter_fallback) {
3874 flow_dv_counter_release_fallback(dev, counter);
3877 if (--counter->ref_cnt == 0) {
3878 struct mlx5_flow_counter_pool *pool =
3879 flow_dv_counter_pool_get(counter);
3881 /* Put the counter in the end - the last updated one. */
3882 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3883 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3888 * Verify the @p attributes will be correctly understood by the NIC and store
3889 * them in the @p flow if everything is correct.
3892 * Pointer to dev struct.
3893 * @param[in] attributes
3894 * Pointer to flow attributes
3895 * @param[in] external
3896 * This flow rule is created by request external to PMD.
3898 * Pointer to error structure.
3901 * 0 on success, a negative errno value otherwise and rte_errno is set.
3904 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3905 const struct rte_flow_attr *attributes,
3906 bool external __rte_unused,
3907 struct rte_flow_error *error)
3909 struct mlx5_priv *priv = dev->data->dev_private;
3910 uint32_t priority_max = priv->config.flow_prio - 1;
3912 #ifndef HAVE_MLX5DV_DR
3913 if (attributes->group)
3914 return rte_flow_error_set(error, ENOTSUP,
3915 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3917 "groups are not supported");
3919 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3924 ret = mlx5_flow_group_to_table(attributes, external,
3929 if (table >= max_group)
3930 return rte_flow_error_set(error, EINVAL,
3931 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3932 "group index out of range");
3934 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3935 attributes->priority >= priority_max)
3936 return rte_flow_error_set(error, ENOTSUP,
3937 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3939 "priority out of range");
3940 if (attributes->transfer) {
3941 if (!priv->config.dv_esw_en)
3942 return rte_flow_error_set
3944 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3945 "E-Switch dr is not supported");
3946 if (!(priv->representor || priv->master))
3947 return rte_flow_error_set
3948 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3949 NULL, "E-Switch configuration can only be"
3950 " done by a master or a representor device");
3951 if (attributes->egress)
3952 return rte_flow_error_set
3954 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3955 "egress is not supported");
3957 if (!(attributes->egress ^ attributes->ingress))
3958 return rte_flow_error_set(error, ENOTSUP,
3959 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3960 "must specify exactly one of "
3961 "ingress or egress");
3966 * Internal validation function. For validating both actions and items.
3969 * Pointer to the rte_eth_dev structure.
3971 * Pointer to the flow attributes.
3973 * Pointer to the list of items.
3974 * @param[in] actions
3975 * Pointer to the list of actions.
3976 * @param[in] external
3977 * This flow rule is created by request external to PMD.
3979 * Pointer to the error structure.
3982 * 0 on success, a negative errno value otherwise and rte_errno is set.
3985 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3986 const struct rte_flow_item items[],
3987 const struct rte_flow_action actions[],
3988 bool external, struct rte_flow_error *error)
3991 uint64_t action_flags = 0;
3992 uint64_t item_flags = 0;
3993 uint64_t last_item = 0;
3994 uint8_t next_protocol = 0xff;
3995 uint16_t ether_type = 0;
3997 const struct rte_flow_item *gre_item = NULL;
3998 struct rte_flow_item_tcp nic_tcp_mask = {
4001 .src_port = RTE_BE16(UINT16_MAX),
4002 .dst_port = RTE_BE16(UINT16_MAX),
4005 struct mlx5_priv *priv = dev->data->dev_private;
4006 struct mlx5_dev_config *dev_conf = &priv->config;
4010 ret = flow_dv_validate_attributes(dev, attr, external, error);
4013 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4014 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4015 int type = items->type;
4018 case RTE_FLOW_ITEM_TYPE_VOID:
4020 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4021 ret = flow_dv_validate_item_port_id
4022 (dev, items, attr, item_flags, error);
4025 last_item = MLX5_FLOW_ITEM_PORT_ID;
4027 case RTE_FLOW_ITEM_TYPE_ETH:
4028 ret = mlx5_flow_validate_item_eth(items, item_flags,
4032 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4033 MLX5_FLOW_LAYER_OUTER_L2;
4034 if (items->mask != NULL && items->spec != NULL) {
4036 ((const struct rte_flow_item_eth *)
4039 ((const struct rte_flow_item_eth *)
4041 ether_type = rte_be_to_cpu_16(ether_type);
4046 case RTE_FLOW_ITEM_TYPE_VLAN:
4047 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4051 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4052 MLX5_FLOW_LAYER_OUTER_VLAN;
4053 if (items->mask != NULL && items->spec != NULL) {
4055 ((const struct rte_flow_item_vlan *)
4056 items->spec)->inner_type;
4058 ((const struct rte_flow_item_vlan *)
4059 items->mask)->inner_type;
4060 ether_type = rte_be_to_cpu_16(ether_type);
4065 case RTE_FLOW_ITEM_TYPE_IPV4:
4066 mlx5_flow_tunnel_ip_check(items, next_protocol,
4067 &item_flags, &tunnel);
4068 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4074 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4075 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4076 if (items->mask != NULL &&
4077 ((const struct rte_flow_item_ipv4 *)
4078 items->mask)->hdr.next_proto_id) {
4080 ((const struct rte_flow_item_ipv4 *)
4081 (items->spec))->hdr.next_proto_id;
4083 ((const struct rte_flow_item_ipv4 *)
4084 (items->mask))->hdr.next_proto_id;
4086 /* Reset for inner layer. */
4087 next_protocol = 0xff;
4090 case RTE_FLOW_ITEM_TYPE_IPV6:
4091 mlx5_flow_tunnel_ip_check(items, next_protocol,
4092 &item_flags, &tunnel);
4093 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4099 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4100 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4101 if (items->mask != NULL &&
4102 ((const struct rte_flow_item_ipv6 *)
4103 items->mask)->hdr.proto) {
4105 ((const struct rte_flow_item_ipv6 *)
4106 items->spec)->hdr.proto;
4108 ((const struct rte_flow_item_ipv6 *)
4109 items->mask)->hdr.proto;
4111 /* Reset for inner layer. */
4112 next_protocol = 0xff;
4115 case RTE_FLOW_ITEM_TYPE_TCP:
4116 ret = mlx5_flow_validate_item_tcp
4123 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4124 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4126 case RTE_FLOW_ITEM_TYPE_UDP:
4127 ret = mlx5_flow_validate_item_udp(items, item_flags,
4132 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4133 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4135 case RTE_FLOW_ITEM_TYPE_GRE:
4136 ret = mlx5_flow_validate_item_gre(items, item_flags,
4137 next_protocol, error);
4141 last_item = MLX5_FLOW_LAYER_GRE;
4143 case RTE_FLOW_ITEM_TYPE_NVGRE:
4144 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4149 last_item = MLX5_FLOW_LAYER_NVGRE;
4151 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4152 ret = mlx5_flow_validate_item_gre_key
4153 (items, item_flags, gre_item, error);
4156 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4158 case RTE_FLOW_ITEM_TYPE_VXLAN:
4159 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4163 last_item = MLX5_FLOW_LAYER_VXLAN;
4165 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4166 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4171 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4173 case RTE_FLOW_ITEM_TYPE_GENEVE:
4174 ret = mlx5_flow_validate_item_geneve(items,
4179 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4181 case RTE_FLOW_ITEM_TYPE_MPLS:
4182 ret = mlx5_flow_validate_item_mpls(dev, items,
4187 last_item = MLX5_FLOW_LAYER_MPLS;
4190 case RTE_FLOW_ITEM_TYPE_MARK:
4191 ret = flow_dv_validate_item_mark(dev, items, attr,
4195 last_item = MLX5_FLOW_ITEM_MARK;
4197 case RTE_FLOW_ITEM_TYPE_META:
4198 ret = flow_dv_validate_item_meta(dev, items, attr,
4202 last_item = MLX5_FLOW_ITEM_METADATA;
4204 case RTE_FLOW_ITEM_TYPE_ICMP:
4205 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4210 last_item = MLX5_FLOW_LAYER_ICMP;
4212 case RTE_FLOW_ITEM_TYPE_ICMP6:
4213 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4218 last_item = MLX5_FLOW_LAYER_ICMP6;
4220 case RTE_FLOW_ITEM_TYPE_TAG:
4221 ret = flow_dv_validate_item_tag(dev, items,
4225 last_item = MLX5_FLOW_ITEM_TAG;
4227 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4228 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4231 return rte_flow_error_set(error, ENOTSUP,
4232 RTE_FLOW_ERROR_TYPE_ITEM,
4233 NULL, "item not supported");
4235 item_flags |= last_item;
4237 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4238 int type = actions->type;
4239 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4240 return rte_flow_error_set(error, ENOTSUP,
4241 RTE_FLOW_ERROR_TYPE_ACTION,
4242 actions, "too many actions");
4244 case RTE_FLOW_ACTION_TYPE_VOID:
4246 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4247 ret = flow_dv_validate_action_port_id(dev,
4254 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4257 case RTE_FLOW_ACTION_TYPE_FLAG:
4258 ret = flow_dv_validate_action_flag(dev, action_flags,
4262 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4263 /* Count all modify-header actions as one. */
4264 if (!(action_flags &
4265 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4267 action_flags |= MLX5_FLOW_ACTION_FLAG |
4268 MLX5_FLOW_ACTION_MARK_EXT;
4270 action_flags |= MLX5_FLOW_ACTION_FLAG;
4274 case RTE_FLOW_ACTION_TYPE_MARK:
4275 ret = flow_dv_validate_action_mark(dev, actions,
4280 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4281 /* Count all modify-header actions as one. */
4282 if (!(action_flags &
4283 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4285 action_flags |= MLX5_FLOW_ACTION_MARK |
4286 MLX5_FLOW_ACTION_MARK_EXT;
4288 action_flags |= MLX5_FLOW_ACTION_MARK;
4292 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4293 ret = flow_dv_validate_action_set_tag(dev, actions,
4298 /* Count all modify-header actions as one action. */
4299 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4301 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4303 case RTE_FLOW_ACTION_TYPE_DROP:
4304 ret = mlx5_flow_validate_action_drop(action_flags,
4308 action_flags |= MLX5_FLOW_ACTION_DROP;
4311 case RTE_FLOW_ACTION_TYPE_QUEUE:
4312 ret = mlx5_flow_validate_action_queue(actions,
4317 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4320 case RTE_FLOW_ACTION_TYPE_RSS:
4321 ret = mlx5_flow_validate_action_rss(actions,
4327 action_flags |= MLX5_FLOW_ACTION_RSS;
4330 case RTE_FLOW_ACTION_TYPE_COUNT:
4331 ret = flow_dv_validate_action_count(dev, error);
4334 action_flags |= MLX5_FLOW_ACTION_COUNT;
4337 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4338 if (flow_dv_validate_action_pop_vlan(dev,
4344 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4347 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4348 ret = flow_dv_validate_action_push_vlan(action_flags,
4354 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4357 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4358 ret = flow_dv_validate_action_set_vlan_pcp
4359 (action_flags, actions, error);
4362 /* Count PCP with push_vlan command. */
4363 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4365 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4366 ret = flow_dv_validate_action_set_vlan_vid
4367 (item_flags, action_flags,
4371 /* Count VID with push_vlan command. */
4372 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4374 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4375 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4376 ret = flow_dv_validate_action_l2_encap(action_flags,
4381 action_flags |= actions->type ==
4382 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4383 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4384 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4387 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4388 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4389 ret = flow_dv_validate_action_l2_decap(action_flags,
4393 action_flags |= actions->type ==
4394 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4395 MLX5_FLOW_ACTION_VXLAN_DECAP :
4396 MLX5_FLOW_ACTION_NVGRE_DECAP;
4399 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4400 ret = flow_dv_validate_action_raw_encap(action_flags,
4405 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4408 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4409 ret = flow_dv_validate_action_raw_decap(action_flags,
4414 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4417 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4418 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4419 ret = flow_dv_validate_action_modify_mac(action_flags,
4425 /* Count all modify-header actions as one action. */
4426 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4428 action_flags |= actions->type ==
4429 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4430 MLX5_FLOW_ACTION_SET_MAC_SRC :
4431 MLX5_FLOW_ACTION_SET_MAC_DST;
4434 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4435 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4436 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4442 /* Count all modify-header actions as one action. */
4443 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4445 action_flags |= actions->type ==
4446 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4447 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4448 MLX5_FLOW_ACTION_SET_IPV4_DST;
4450 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4451 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4452 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4458 /* Count all modify-header actions as one action. */
4459 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4461 action_flags |= actions->type ==
4462 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4463 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4464 MLX5_FLOW_ACTION_SET_IPV6_DST;
4466 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4467 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4468 ret = flow_dv_validate_action_modify_tp(action_flags,
4474 /* Count all modify-header actions as one action. */
4475 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4477 action_flags |= actions->type ==
4478 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4479 MLX5_FLOW_ACTION_SET_TP_SRC :
4480 MLX5_FLOW_ACTION_SET_TP_DST;
4482 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4483 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4484 ret = flow_dv_validate_action_modify_ttl(action_flags,
4490 /* Count all modify-header actions as one action. */
4491 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4493 action_flags |= actions->type ==
4494 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4495 MLX5_FLOW_ACTION_SET_TTL :
4496 MLX5_FLOW_ACTION_DEC_TTL;
4498 case RTE_FLOW_ACTION_TYPE_JUMP:
4499 ret = flow_dv_validate_action_jump(actions,
4506 action_flags |= MLX5_FLOW_ACTION_JUMP;
4508 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4509 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4510 ret = flow_dv_validate_action_modify_tcp_seq
4517 /* Count all modify-header actions as one action. */
4518 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4520 action_flags |= actions->type ==
4521 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4522 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4523 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4525 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4526 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4527 ret = flow_dv_validate_action_modify_tcp_ack
4534 /* Count all modify-header actions as one action. */
4535 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4537 action_flags |= actions->type ==
4538 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4539 MLX5_FLOW_ACTION_INC_TCP_ACK :
4540 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4542 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4543 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4546 return rte_flow_error_set(error, ENOTSUP,
4547 RTE_FLOW_ERROR_TYPE_ACTION,
4549 "action not supported");
4552 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4553 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4554 return rte_flow_error_set(error, ENOTSUP,
4555 RTE_FLOW_ERROR_TYPE_ACTION,
4557 "can't have vxlan and vlan"
4558 " actions in the same rule");
4559 /* Eswitch has few restrictions on using items and actions */
4560 if (attr->transfer) {
4561 if (!mlx5_flow_ext_mreg_supported(dev) &&
4562 action_flags & MLX5_FLOW_ACTION_FLAG)
4563 return rte_flow_error_set(error, ENOTSUP,
4564 RTE_FLOW_ERROR_TYPE_ACTION,
4566 "unsupported action FLAG");
4567 if (!mlx5_flow_ext_mreg_supported(dev) &&
4568 action_flags & MLX5_FLOW_ACTION_MARK)
4569 return rte_flow_error_set(error, ENOTSUP,
4570 RTE_FLOW_ERROR_TYPE_ACTION,
4572 "unsupported action MARK");
4573 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4574 return rte_flow_error_set(error, ENOTSUP,
4575 RTE_FLOW_ERROR_TYPE_ACTION,
4577 "unsupported action QUEUE");
4578 if (action_flags & MLX5_FLOW_ACTION_RSS)
4579 return rte_flow_error_set(error, ENOTSUP,
4580 RTE_FLOW_ERROR_TYPE_ACTION,
4582 "unsupported action RSS");
4583 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4584 return rte_flow_error_set(error, EINVAL,
4585 RTE_FLOW_ERROR_TYPE_ACTION,
4587 "no fate action is found");
4589 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4590 return rte_flow_error_set(error, EINVAL,
4591 RTE_FLOW_ERROR_TYPE_ACTION,
4593 "no fate action is found");
4599 * Internal preparation function. Allocates the DV flow size,
4600 * this size is constant.
4603 * Pointer to the flow attributes.
4605 * Pointer to the list of items.
4606 * @param[in] actions
4607 * Pointer to the list of actions.
4609 * Pointer to the error structure.
4612 * Pointer to mlx5_flow object on success,
4613 * otherwise NULL and rte_errno is set.
4615 static struct mlx5_flow *
4616 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4617 const struct rte_flow_item items[] __rte_unused,
4618 const struct rte_flow_action actions[] __rte_unused,
4619 struct rte_flow_error *error)
4621 size_t size = sizeof(struct mlx5_flow);
4622 struct mlx5_flow *dev_flow;
4624 dev_flow = rte_calloc(__func__, 1, size, 0);
4626 rte_flow_error_set(error, ENOMEM,
4627 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4628 "not enough memory to create flow");
4631 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4632 dev_flow->ingress = attr->ingress;
4633 dev_flow->transfer = attr->transfer;
4639 * Sanity check for match mask and value. Similar to check_valid_spec() in
4640 * kernel driver. If unmasked bit is present in value, it returns failure.
4643 * pointer to match mask buffer.
4644 * @param match_value
4645 * pointer to match value buffer.
4648 * 0 if valid, -EINVAL otherwise.
4651 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4653 uint8_t *m = match_mask;
4654 uint8_t *v = match_value;
4657 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4660 "match_value differs from match_criteria"
4661 " %p[%u] != %p[%u]",
4662 match_value, i, match_mask, i);
4671 * Add Ethernet item to matcher and to the value.
4673 * @param[in, out] matcher
4675 * @param[in, out] key
4676 * Flow matcher value.
4678 * Flow pattern to translate.
4680 * Item is inner pattern.
4683 flow_dv_translate_item_eth(void *matcher, void *key,
4684 const struct rte_flow_item *item, int inner)
4686 const struct rte_flow_item_eth *eth_m = item->mask;
4687 const struct rte_flow_item_eth *eth_v = item->spec;
4688 const struct rte_flow_item_eth nic_mask = {
4689 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4690 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4691 .type = RTE_BE16(0xffff),
4703 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4705 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4707 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4709 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4711 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4712 ð_m->dst, sizeof(eth_m->dst));
4713 /* The value must be in the range of the mask. */
4714 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4715 for (i = 0; i < sizeof(eth_m->dst); ++i)
4716 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4717 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4718 ð_m->src, sizeof(eth_m->src));
4719 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4720 /* The value must be in the range of the mask. */
4721 for (i = 0; i < sizeof(eth_m->dst); ++i)
4722 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4723 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4724 rte_be_to_cpu_16(eth_m->type));
4725 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4726 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4730 * Add VLAN item to matcher and to the value.
4732 * @param[in, out] dev_flow
4734 * @param[in, out] matcher
4736 * @param[in, out] key
4737 * Flow matcher value.
4739 * Flow pattern to translate.
4741 * Item is inner pattern.
4744 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4745 void *matcher, void *key,
4746 const struct rte_flow_item *item,
4749 const struct rte_flow_item_vlan *vlan_m = item->mask;
4750 const struct rte_flow_item_vlan *vlan_v = item->spec;
4759 vlan_m = &rte_flow_item_vlan_mask;
4761 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4763 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4765 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4767 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4769 * This is workaround, masks are not supported,
4770 * and pre-validated.
4772 dev_flow->dv.vf_vlan.tag =
4773 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4775 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4776 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4777 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4778 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4779 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4780 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4781 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4782 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4783 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4784 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4785 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4786 rte_be_to_cpu_16(vlan_m->inner_type));
4787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4788 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4792 * Add IPV4 item to matcher and to the value.
4794 * @param[in, out] matcher
4796 * @param[in, out] key
4797 * Flow matcher value.
4799 * Flow pattern to translate.
4801 * Item is inner pattern.
4803 * The group to insert the rule.
4806 flow_dv_translate_item_ipv4(void *matcher, void *key,
4807 const struct rte_flow_item *item,
4808 int inner, uint32_t group)
4810 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4811 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4812 const struct rte_flow_item_ipv4 nic_mask = {
4814 .src_addr = RTE_BE32(0xffffffff),
4815 .dst_addr = RTE_BE32(0xffffffff),
4816 .type_of_service = 0xff,
4817 .next_proto_id = 0xff,
4827 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4829 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4831 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4833 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4836 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4838 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4839 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4844 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4845 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4846 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4847 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4848 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4849 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4850 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4851 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4852 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4853 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4854 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4855 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4856 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4857 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4858 ipv4_m->hdr.type_of_service);
4859 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4860 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4861 ipv4_m->hdr.type_of_service >> 2);
4862 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4863 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4864 ipv4_m->hdr.next_proto_id);
4865 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4866 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4870 * Add IPV6 item to matcher and to the value.
4872 * @param[in, out] matcher
4874 * @param[in, out] key
4875 * Flow matcher value.
4877 * Flow pattern to translate.
4879 * Item is inner pattern.
4881 * The group to insert the rule.
4884 flow_dv_translate_item_ipv6(void *matcher, void *key,
4885 const struct rte_flow_item *item,
4886 int inner, uint32_t group)
4888 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4889 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4890 const struct rte_flow_item_ipv6 nic_mask = {
4893 "\xff\xff\xff\xff\xff\xff\xff\xff"
4894 "\xff\xff\xff\xff\xff\xff\xff\xff",
4896 "\xff\xff\xff\xff\xff\xff\xff\xff"
4897 "\xff\xff\xff\xff\xff\xff\xff\xff",
4898 .vtc_flow = RTE_BE32(0xffffffff),
4905 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4906 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4915 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4917 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4919 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4921 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4924 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4926 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4927 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4932 size = sizeof(ipv6_m->hdr.dst_addr);
4933 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4934 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4935 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4936 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4937 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4938 for (i = 0; i < size; ++i)
4939 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4940 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4941 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4942 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4943 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4944 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4945 for (i = 0; i < size; ++i)
4946 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4948 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4949 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4950 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4951 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4952 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4953 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4956 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4958 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4961 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4963 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4967 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4969 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4970 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4974 * Add TCP item to matcher and to the value.
4976 * @param[in, out] matcher
4978 * @param[in, out] key
4979 * Flow matcher value.
4981 * Flow pattern to translate.
4983 * Item is inner pattern.
4986 flow_dv_translate_item_tcp(void *matcher, void *key,
4987 const struct rte_flow_item *item,
4990 const struct rte_flow_item_tcp *tcp_m = item->mask;
4991 const struct rte_flow_item_tcp *tcp_v = item->spec;
4996 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4998 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5000 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5002 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5004 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5005 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5009 tcp_m = &rte_flow_item_tcp_mask;
5010 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5011 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5012 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5013 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5014 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5015 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5016 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5017 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5018 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5019 tcp_m->hdr.tcp_flags);
5020 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5021 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5025 * Add UDP item to matcher and to the value.
5027 * @param[in, out] matcher
5029 * @param[in, out] key
5030 * Flow matcher value.
5032 * Flow pattern to translate.
5034 * Item is inner pattern.
5037 flow_dv_translate_item_udp(void *matcher, void *key,
5038 const struct rte_flow_item *item,
5041 const struct rte_flow_item_udp *udp_m = item->mask;
5042 const struct rte_flow_item_udp *udp_v = item->spec;
5047 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5049 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5051 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5053 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5055 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5056 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5060 udp_m = &rte_flow_item_udp_mask;
5061 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5062 rte_be_to_cpu_16(udp_m->hdr.src_port));
5063 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5064 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5065 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5066 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5067 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5068 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5072 * Add GRE optional Key item to matcher and to the value.
5074 * @param[in, out] matcher
5076 * @param[in, out] key
5077 * Flow matcher value.
5079 * Flow pattern to translate.
5081 * Item is inner pattern.
5084 flow_dv_translate_item_gre_key(void *matcher, void *key,
5085 const struct rte_flow_item *item)
5087 const rte_be32_t *key_m = item->mask;
5088 const rte_be32_t *key_v = item->spec;
5089 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5090 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5091 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5096 key_m = &gre_key_default_mask;
5097 /* GRE K bit must be on and should already be validated */
5098 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5099 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5100 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5101 rte_be_to_cpu_32(*key_m) >> 8);
5102 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5103 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5104 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5105 rte_be_to_cpu_32(*key_m) & 0xFF);
5106 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5107 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5111 * Add GRE item to matcher and to the value.
5113 * @param[in, out] matcher
5115 * @param[in, out] key
5116 * Flow matcher value.
5118 * Flow pattern to translate.
5120 * Item is inner pattern.
5123 flow_dv_translate_item_gre(void *matcher, void *key,
5124 const struct rte_flow_item *item,
5127 const struct rte_flow_item_gre *gre_m = item->mask;
5128 const struct rte_flow_item_gre *gre_v = item->spec;
5131 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5132 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5139 uint16_t s_present:1;
5140 uint16_t k_present:1;
5141 uint16_t rsvd_bit1:1;
5142 uint16_t c_present:1;
5146 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5149 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5151 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5153 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5155 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5157 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5158 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5162 gre_m = &rte_flow_item_gre_mask;
5163 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5164 rte_be_to_cpu_16(gre_m->protocol));
5165 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5166 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5167 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5168 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5169 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5170 gre_crks_rsvd0_ver_m.c_present);
5171 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5172 gre_crks_rsvd0_ver_v.c_present &
5173 gre_crks_rsvd0_ver_m.c_present);
5174 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5175 gre_crks_rsvd0_ver_m.k_present);
5176 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5177 gre_crks_rsvd0_ver_v.k_present &
5178 gre_crks_rsvd0_ver_m.k_present);
5179 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5180 gre_crks_rsvd0_ver_m.s_present);
5181 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5182 gre_crks_rsvd0_ver_v.s_present &
5183 gre_crks_rsvd0_ver_m.s_present);
5187 * Add NVGRE item to matcher and to the value.
5189 * @param[in, out] matcher
5191 * @param[in, out] key
5192 * Flow matcher value.
5194 * Flow pattern to translate.
5196 * Item is inner pattern.
5199 flow_dv_translate_item_nvgre(void *matcher, void *key,
5200 const struct rte_flow_item *item,
5203 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5204 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5205 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5206 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5207 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5208 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5214 /* For NVGRE, GRE header fields must be set with defined values. */
5215 const struct rte_flow_item_gre gre_spec = {
5216 .c_rsvd0_ver = RTE_BE16(0x2000),
5217 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5219 const struct rte_flow_item_gre gre_mask = {
5220 .c_rsvd0_ver = RTE_BE16(0xB000),
5221 .protocol = RTE_BE16(UINT16_MAX),
5223 const struct rte_flow_item gre_item = {
5228 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5232 nvgre_m = &rte_flow_item_nvgre_mask;
5233 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5234 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5235 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5236 memcpy(gre_key_m, tni_flow_id_m, size);
5237 for (i = 0; i < size; ++i)
5238 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5242 * Add VXLAN item to matcher and to the value.
5244 * @param[in, out] matcher
5246 * @param[in, out] key
5247 * Flow matcher value.
5249 * Flow pattern to translate.
5251 * Item is inner pattern.
5254 flow_dv_translate_item_vxlan(void *matcher, void *key,
5255 const struct rte_flow_item *item,
5258 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5259 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5262 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5263 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5271 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5273 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5275 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5277 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5279 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5280 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5281 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5282 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5283 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5288 vxlan_m = &rte_flow_item_vxlan_mask;
5289 size = sizeof(vxlan_m->vni);
5290 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5291 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5292 memcpy(vni_m, vxlan_m->vni, size);
5293 for (i = 0; i < size; ++i)
5294 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5298 * Add Geneve item to matcher and to the value.
5300 * @param[in, out] matcher
5302 * @param[in, out] key
5303 * Flow matcher value.
5305 * Flow pattern to translate.
5307 * Item is inner pattern.
5311 flow_dv_translate_item_geneve(void *matcher, void *key,
5312 const struct rte_flow_item *item, int inner)
5314 const struct rte_flow_item_geneve *geneve_m = item->mask;
5315 const struct rte_flow_item_geneve *geneve_v = item->spec;
5318 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5319 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5328 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5330 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5332 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5334 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5336 dport = MLX5_UDP_PORT_GENEVE;
5337 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5338 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5339 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5344 geneve_m = &rte_flow_item_geneve_mask;
5345 size = sizeof(geneve_m->vni);
5346 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5347 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5348 memcpy(vni_m, geneve_m->vni, size);
5349 for (i = 0; i < size; ++i)
5350 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5351 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5352 rte_be_to_cpu_16(geneve_m->protocol));
5353 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5354 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5355 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5356 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5357 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5358 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5359 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5360 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5361 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5362 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5363 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5364 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5365 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5369 * Add MPLS item to matcher and to the value.
5371 * @param[in, out] matcher
5373 * @param[in, out] key
5374 * Flow matcher value.
5376 * Flow pattern to translate.
5377 * @param[in] prev_layer
5378 * The protocol layer indicated in previous item.
5380 * Item is inner pattern.
5383 flow_dv_translate_item_mpls(void *matcher, void *key,
5384 const struct rte_flow_item *item,
5385 uint64_t prev_layer,
5388 const uint32_t *in_mpls_m = item->mask;
5389 const uint32_t *in_mpls_v = item->spec;
5390 uint32_t *out_mpls_m = 0;
5391 uint32_t *out_mpls_v = 0;
5392 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5393 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5394 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5396 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5397 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5398 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5400 switch (prev_layer) {
5401 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5402 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5404 MLX5_UDP_PORT_MPLS);
5406 case MLX5_FLOW_LAYER_GRE:
5407 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5408 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5409 RTE_ETHER_TYPE_MPLS);
5412 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5413 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5420 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5421 switch (prev_layer) {
5422 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5424 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5425 outer_first_mpls_over_udp);
5427 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5428 outer_first_mpls_over_udp);
5430 case MLX5_FLOW_LAYER_GRE:
5432 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5433 outer_first_mpls_over_gre);
5435 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5436 outer_first_mpls_over_gre);
5439 /* Inner MPLS not over GRE is not supported. */
5442 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5446 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5452 if (out_mpls_m && out_mpls_v) {
5453 *out_mpls_m = *in_mpls_m;
5454 *out_mpls_v = *in_mpls_v & *in_mpls_m;
5459 * Add metadata register item to matcher
5461 * @param[in, out] matcher
5463 * @param[in, out] key
5464 * Flow matcher value.
5465 * @param[in] reg_type
5466 * Type of device metadata register
5473 flow_dv_match_meta_reg(void *matcher, void *key,
5474 enum modify_reg reg_type,
5475 uint32_t data, uint32_t mask)
5478 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5480 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5485 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5486 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5489 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5490 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5493 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
5494 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
5497 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5498 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5501 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5502 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5505 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5506 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5509 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5510 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
5513 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
5514 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
5517 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
5518 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
5521 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
5522 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5531 * Add MARK item to matcher
5534 * The device to configure through.
5535 * @param[in, out] matcher
5537 * @param[in, out] key
5538 * Flow matcher value.
5540 * Flow pattern to translate.
5543 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
5544 void *matcher, void *key,
5545 const struct rte_flow_item *item)
5547 struct mlx5_priv *priv = dev->data->dev_private;
5548 const struct rte_flow_item_mark *mark;
5552 mark = item->mask ? (const void *)item->mask :
5553 &rte_flow_item_mark_mask;
5554 mask = mark->id & priv->sh->dv_mark_mask;
5555 mark = (const void *)item->spec;
5557 value = mark->id & priv->sh->dv_mark_mask & mask;
5559 enum modify_reg reg;
5561 /* Get the metadata register index for the mark. */
5562 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
5564 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
5569 * Add META item to matcher
5571 * @param[in, out] matcher
5573 * @param[in, out] key
5574 * Flow matcher value.
5576 * Flow pattern to translate.
5579 flow_dv_translate_item_meta(void *matcher, void *key,
5580 const struct rte_flow_item *item)
5582 const struct rte_flow_item_meta *meta_m;
5583 const struct rte_flow_item_meta *meta_v;
5585 meta_m = (const void *)item->mask;
5587 meta_m = &rte_flow_item_meta_mask;
5588 meta_v = (const void *)item->spec;
5590 flow_dv_match_meta_reg(matcher, key, REG_A,
5591 rte_cpu_to_be_32(meta_v->data),
5592 rte_cpu_to_be_32(meta_m->data));
5596 * Add vport metadata Reg C0 item to matcher
5598 * @param[in, out] matcher
5600 * @param[in, out] key
5601 * Flow matcher value.
5603 * Flow pattern to translate.
5606 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5607 uint32_t value, uint32_t mask)
5609 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5613 * Add tag item to matcher
5615 * @param[in, out] matcher
5617 * @param[in, out] key
5618 * Flow matcher value.
5620 * Flow pattern to translate.
5623 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5624 const struct rte_flow_item *item)
5626 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5627 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5630 flow_dv_match_meta_reg(matcher, key, tag_v->id, tag_v->data,
5631 tag_m ? tag_m->data : UINT32_MAX);
5635 * Add TAG item to matcher
5638 * The devich to configure through.
5639 * @param[in, out] matcher
5641 * @param[in, out] key
5642 * Flow matcher value.
5644 * Flow pattern to translate.
5647 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
5648 void *matcher, void *key,
5649 const struct rte_flow_item *item)
5651 const struct rte_flow_item_tag *tag_v = item->spec;
5652 const struct rte_flow_item_tag *tag_m = item->mask;
5653 enum modify_reg reg;
5656 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
5657 /* Get the metadata register index for the tag. */
5658 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
5660 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5664 * Add source vport match to the specified matcher.
5666 * @param[in, out] matcher
5668 * @param[in, out] key
5669 * Flow matcher value.
5671 * Source vport value to match
5676 flow_dv_translate_item_source_vport(void *matcher, void *key,
5677 int16_t port, uint16_t mask)
5679 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5680 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5682 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5683 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5687 * Translate port-id item to eswitch match on port-id.
5690 * The devich to configure through.
5691 * @param[in, out] matcher
5693 * @param[in, out] key
5694 * Flow matcher value.
5696 * Flow pattern to translate.
5699 * 0 on success, a negative errno value otherwise.
5702 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5703 void *key, const struct rte_flow_item *item)
5705 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5706 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5707 struct mlx5_priv *priv;
5710 mask = pid_m ? pid_m->id : 0xffff;
5711 id = pid_v ? pid_v->id : dev->data->port_id;
5712 priv = mlx5_port_to_eswitch_info(id, item == NULL);
5715 /* Translate to vport field or to metadata, depending on mode. */
5716 if (priv->vport_meta_mask)
5717 flow_dv_translate_item_meta_vport(matcher, key,
5718 priv->vport_meta_tag,
5719 priv->vport_meta_mask);
5721 flow_dv_translate_item_source_vport(matcher, key,
5722 priv->vport_id, mask);
5727 * Add ICMP6 item to matcher and to the value.
5729 * @param[in, out] matcher
5731 * @param[in, out] key
5732 * Flow matcher value.
5734 * Flow pattern to translate.
5736 * Item is inner pattern.
5739 flow_dv_translate_item_icmp6(void *matcher, void *key,
5740 const struct rte_flow_item *item,
5743 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5744 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5747 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5749 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5751 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5753 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5755 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5757 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5759 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5760 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5764 icmp6_m = &rte_flow_item_icmp6_mask;
5765 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5766 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5767 icmp6_v->type & icmp6_m->type);
5768 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5769 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5770 icmp6_v->code & icmp6_m->code);
5774 * Add ICMP item to matcher and to the value.
5776 * @param[in, out] matcher
5778 * @param[in, out] key
5779 * Flow matcher value.
5781 * Flow pattern to translate.
5783 * Item is inner pattern.
5786 flow_dv_translate_item_icmp(void *matcher, void *key,
5787 const struct rte_flow_item *item,
5790 const struct rte_flow_item_icmp *icmp_m = item->mask;
5791 const struct rte_flow_item_icmp *icmp_v = item->spec;
5794 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5796 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5798 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5800 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5802 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5804 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5806 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5807 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5811 icmp_m = &rte_flow_item_icmp_mask;
5812 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5813 icmp_m->hdr.icmp_type);
5814 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5815 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5816 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5817 icmp_m->hdr.icmp_code);
5818 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5819 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5822 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5824 #define HEADER_IS_ZERO(match_criteria, headers) \
5825 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5826 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5829 * Calculate flow matcher enable bitmap.
5831 * @param match_criteria
5832 * Pointer to flow matcher criteria.
5835 * Bitmap of enabled fields.
5838 flow_dv_matcher_enable(uint32_t *match_criteria)
5840 uint8_t match_criteria_enable;
5842 match_criteria_enable =
5843 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5844 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5845 match_criteria_enable |=
5846 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5847 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5848 match_criteria_enable |=
5849 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5850 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5851 match_criteria_enable |=
5852 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5853 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5854 match_criteria_enable |=
5855 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5856 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5857 return match_criteria_enable;
5864 * @param dev[in, out]
5865 * Pointer to rte_eth_dev structure.
5866 * @param[in] table_id
5869 * Direction of the table.
5870 * @param[in] transfer
5871 * E-Switch or NIC flow.
5873 * pointer to error structure.
5876 * Returns tables resource based on the index, NULL in case of failed.
5878 static struct mlx5_flow_tbl_resource *
5879 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5880 uint32_t table_id, uint8_t egress,
5882 struct rte_flow_error *error)
5884 struct mlx5_priv *priv = dev->data->dev_private;
5885 struct mlx5_ibv_shared *sh = priv->sh;
5886 struct mlx5_flow_tbl_resource *tbl;
5888 #ifdef HAVE_MLX5DV_DR
5890 tbl = &sh->fdb_tbl[table_id];
5892 tbl->obj = mlx5_glue->dr_create_flow_tbl
5893 (sh->fdb_domain, table_id);
5894 } else if (egress) {
5895 tbl = &sh->tx_tbl[table_id];
5897 tbl->obj = mlx5_glue->dr_create_flow_tbl
5898 (sh->tx_domain, table_id);
5900 tbl = &sh->rx_tbl[table_id];
5902 tbl->obj = mlx5_glue->dr_create_flow_tbl
5903 (sh->rx_domain, table_id);
5906 rte_flow_error_set(error, ENOMEM,
5907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5908 NULL, "cannot create table");
5911 rte_atomic32_inc(&tbl->refcnt);
5917 return &sh->fdb_tbl[table_id];
5919 return &sh->tx_tbl[table_id];
5921 return &sh->rx_tbl[table_id];
5926 * Release a flow table.
5929 * Table resource to be released.
5932 * Returns 0 if table was released, else return 1;
5935 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5939 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5940 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5948 * Register the flow matcher.
5950 * @param dev[in, out]
5951 * Pointer to rte_eth_dev structure.
5952 * @param[in, out] matcher
5953 * Pointer to flow matcher.
5954 * @parm[in, out] dev_flow
5955 * Pointer to the dev_flow.
5957 * pointer to error structure.
5960 * 0 on success otherwise -errno and errno is set.
5963 flow_dv_matcher_register(struct rte_eth_dev *dev,
5964 struct mlx5_flow_dv_matcher *matcher,
5965 struct mlx5_flow *dev_flow,
5966 struct rte_flow_error *error)
5968 struct mlx5_priv *priv = dev->data->dev_private;
5969 struct mlx5_ibv_shared *sh = priv->sh;
5970 struct mlx5_flow_dv_matcher *cache_matcher;
5971 struct mlx5dv_flow_matcher_attr dv_attr = {
5972 .type = IBV_FLOW_ATTR_NORMAL,
5973 .match_mask = (void *)&matcher->mask,
5975 struct mlx5_flow_tbl_resource *tbl = NULL;
5977 /* Lookup from cache. */
5978 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5979 if (matcher->crc == cache_matcher->crc &&
5980 matcher->priority == cache_matcher->priority &&
5981 matcher->egress == cache_matcher->egress &&
5982 matcher->group == cache_matcher->group &&
5983 matcher->transfer == cache_matcher->transfer &&
5984 !memcmp((const void *)matcher->mask.buf,
5985 (const void *)cache_matcher->mask.buf,
5986 cache_matcher->mask.size)) {
5988 "priority %hd use %s matcher %p: refcnt %d++",
5989 cache_matcher->priority,
5990 cache_matcher->egress ? "tx" : "rx",
5991 (void *)cache_matcher,
5992 rte_atomic32_read(&cache_matcher->refcnt));
5993 rte_atomic32_inc(&cache_matcher->refcnt);
5994 dev_flow->dv.matcher = cache_matcher;
5998 /* Register new matcher. */
5999 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6001 return rte_flow_error_set(error, ENOMEM,
6002 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6003 "cannot allocate matcher memory");
6004 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
6005 matcher->egress, matcher->transfer,
6008 rte_free(cache_matcher);
6009 return rte_flow_error_set(error, ENOMEM,
6010 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6011 NULL, "cannot create table");
6013 *cache_matcher = *matcher;
6014 dv_attr.match_criteria_enable =
6015 flow_dv_matcher_enable(cache_matcher->mask.buf);
6016 dv_attr.priority = matcher->priority;
6017 if (matcher->egress)
6018 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6019 cache_matcher->matcher_object =
6020 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6021 if (!cache_matcher->matcher_object) {
6022 rte_free(cache_matcher);
6023 #ifdef HAVE_MLX5DV_DR
6024 flow_dv_tbl_resource_release(tbl);
6026 return rte_flow_error_set(error, ENOMEM,
6027 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6028 NULL, "cannot create matcher");
6030 rte_atomic32_inc(&cache_matcher->refcnt);
6031 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
6032 dev_flow->dv.matcher = cache_matcher;
6033 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
6034 cache_matcher->priority,
6035 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
6036 rte_atomic32_read(&cache_matcher->refcnt));
6037 rte_atomic32_inc(&tbl->refcnt);
6042 * Find existing tag resource or create and register a new one.
6044 * @param dev[in, out]
6045 * Pointer to rte_eth_dev structure.
6046 * @param[in, out] resource
6047 * Pointer to tag resource.
6048 * @parm[in, out] dev_flow
6049 * Pointer to the dev_flow.
6051 * pointer to error structure.
6054 * 0 on success otherwise -errno and errno is set.
6057 flow_dv_tag_resource_register
6058 (struct rte_eth_dev *dev,
6059 struct mlx5_flow_dv_tag_resource *resource,
6060 struct mlx5_flow *dev_flow,
6061 struct rte_flow_error *error)
6063 struct mlx5_priv *priv = dev->data->dev_private;
6064 struct mlx5_ibv_shared *sh = priv->sh;
6065 struct mlx5_flow_dv_tag_resource *cache_resource;
6067 /* Lookup a matching resource from cache. */
6068 LIST_FOREACH(cache_resource, &sh->tags, next) {
6069 if (resource->tag == cache_resource->tag) {
6070 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
6071 (void *)cache_resource,
6072 rte_atomic32_read(&cache_resource->refcnt));
6073 rte_atomic32_inc(&cache_resource->refcnt);
6074 dev_flow->dv.tag_resource = cache_resource;
6078 /* Register new resource. */
6079 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6080 if (!cache_resource)
6081 return rte_flow_error_set(error, ENOMEM,
6082 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6083 "cannot allocate resource memory");
6084 *cache_resource = *resource;
6085 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
6087 if (!cache_resource->action) {
6088 rte_free(cache_resource);
6089 return rte_flow_error_set(error, ENOMEM,
6090 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6091 NULL, "cannot create action");
6093 rte_atomic32_init(&cache_resource->refcnt);
6094 rte_atomic32_inc(&cache_resource->refcnt);
6095 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
6096 dev_flow->dv.tag_resource = cache_resource;
6097 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
6098 (void *)cache_resource,
6099 rte_atomic32_read(&cache_resource->refcnt));
6107 * Pointer to Ethernet device.
6109 * Pointer to mlx5_flow.
6112 * 1 while a reference on it exists, 0 when freed.
6115 flow_dv_tag_release(struct rte_eth_dev *dev,
6116 struct mlx5_flow_dv_tag_resource *tag)
6119 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6120 dev->data->port_id, (void *)tag,
6121 rte_atomic32_read(&tag->refcnt));
6122 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6123 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6124 LIST_REMOVE(tag, next);
6125 DRV_LOG(DEBUG, "port %u tag %p: removed",
6126 dev->data->port_id, (void *)tag);
6134 * Translate port ID action to vport.
6137 * Pointer to rte_eth_dev structure.
6139 * Pointer to the port ID action.
6140 * @param[out] dst_port_id
6141 * The target port ID.
6143 * Pointer to the error structure.
6146 * 0 on success, a negative errno value otherwise and rte_errno is set.
6149 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6150 const struct rte_flow_action *action,
6151 uint32_t *dst_port_id,
6152 struct rte_flow_error *error)
6155 struct mlx5_priv *priv;
6156 const struct rte_flow_action_port_id *conf =
6157 (const struct rte_flow_action_port_id *)action->conf;
6159 port = conf->original ? dev->data->port_id : conf->id;
6160 priv = mlx5_port_to_eswitch_info(port, false);
6162 return rte_flow_error_set(error, -rte_errno,
6163 RTE_FLOW_ERROR_TYPE_ACTION,
6165 "No eswitch info was found for port");
6166 if (priv->vport_meta_mask)
6167 *dst_port_id = priv->vport_meta_tag;
6169 *dst_port_id = priv->vport_id;
6174 * Add Tx queue matcher
6177 * Pointer to the dev struct.
6178 * @param[in, out] matcher
6180 * @param[in, out] key
6181 * Flow matcher value.
6183 * Flow pattern to translate.
6185 * Item is inner pattern.
6188 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6189 void *matcher, void *key,
6190 const struct rte_flow_item *item)
6192 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6193 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6195 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6197 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6198 struct mlx5_txq_ctrl *txq;
6202 queue_m = (const void *)item->mask;
6205 queue_v = (const void *)item->spec;
6208 txq = mlx5_txq_get(dev, queue_v->queue);
6211 queue = txq->obj->sq->id;
6212 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6213 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6214 queue & queue_m->queue);
6215 mlx5_txq_release(dev, queue_v->queue);
6219 * Fill the flow with DV spec, lock free
6220 * (mutex should be acquired by caller).
6223 * Pointer to rte_eth_dev structure.
6224 * @param[in, out] dev_flow
6225 * Pointer to the sub flow.
6227 * Pointer to the flow attributes.
6229 * Pointer to the list of items.
6230 * @param[in] actions
6231 * Pointer to the list of actions.
6233 * Pointer to the error structure.
6236 * 0 on success, a negative errno value otherwise and rte_errno is set.
6239 __flow_dv_translate(struct rte_eth_dev *dev,
6240 struct mlx5_flow *dev_flow,
6241 const struct rte_flow_attr *attr,
6242 const struct rte_flow_item items[],
6243 const struct rte_flow_action actions[],
6244 struct rte_flow_error *error)
6246 struct mlx5_priv *priv = dev->data->dev_private;
6247 struct mlx5_dev_config *dev_conf = &priv->config;
6248 struct rte_flow *flow = dev_flow->flow;
6249 uint64_t item_flags = 0;
6250 uint64_t last_item = 0;
6251 uint64_t action_flags = 0;
6252 uint64_t priority = attr->priority;
6253 struct mlx5_flow_dv_matcher matcher = {
6255 .size = sizeof(matcher.mask.buf),
6259 bool actions_end = false;
6260 struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
6261 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
6262 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
6264 union flow_dv_attr flow_attr = { .attr = 0 };
6265 struct mlx5_flow_dv_tag_resource tag_resource;
6266 uint32_t modify_action_position = UINT32_MAX;
6267 void *match_mask = matcher.mask.buf;
6268 void *match_value = dev_flow->dv.value.buf;
6269 uint8_t next_protocol = 0xff;
6270 struct rte_vlan_hdr vlan = { 0 };
6274 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
6278 dev_flow->group = table;
6280 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
6281 if (priority == MLX5_FLOW_PRIO_RSVD)
6282 priority = dev_conf->flow_prio - 1;
6283 for (; !actions_end ; actions++) {
6284 const struct rte_flow_action_queue *queue;
6285 const struct rte_flow_action_rss *rss;
6286 const struct rte_flow_action *action = actions;
6287 const struct rte_flow_action_count *count = action->conf;
6288 const uint8_t *rss_key;
6289 const struct rte_flow_action_jump *jump_data;
6290 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
6291 struct mlx5_flow_tbl_resource *tbl;
6292 uint32_t port_id = 0;
6293 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
6294 int action_type = actions->type;
6295 const struct rte_flow_action *found_action = NULL;
6297 switch (action_type) {
6298 case RTE_FLOW_ACTION_TYPE_VOID:
6300 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6301 if (flow_dv_translate_action_port_id(dev, action,
6304 port_id_resource.port_id = port_id;
6305 if (flow_dv_port_id_action_resource_register
6306 (dev, &port_id_resource, dev_flow, error))
6308 dev_flow->dv.actions[actions_n++] =
6309 dev_flow->dv.port_id_action->action;
6310 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6312 case RTE_FLOW_ACTION_TYPE_FLAG:
6313 action_flags |= MLX5_FLOW_ACTION_FLAG;
6314 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6315 struct rte_flow_action_mark mark = {
6316 .id = MLX5_FLOW_MARK_DEFAULT,
6319 if (flow_dv_convert_action_mark(dev, &mark,
6323 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
6327 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
6328 if (!dev_flow->dv.tag_resource)
6329 if (flow_dv_tag_resource_register
6330 (dev, &tag_resource, dev_flow, error))
6332 dev_flow->dv.actions[actions_n++] =
6333 dev_flow->dv.tag_resource->action;
6335 case RTE_FLOW_ACTION_TYPE_MARK:
6336 action_flags |= MLX5_FLOW_ACTION_MARK;
6337 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6338 const struct rte_flow_action_mark *mark =
6339 (const struct rte_flow_action_mark *)
6342 if (flow_dv_convert_action_mark(dev, mark,
6346 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
6349 /* Legacy (non-extensive) MARK action. */
6350 tag_resource.tag = mlx5_flow_mark_set
6351 (((const struct rte_flow_action_mark *)
6352 (actions->conf))->id);
6353 if (!dev_flow->dv.tag_resource)
6354 if (flow_dv_tag_resource_register
6355 (dev, &tag_resource, dev_flow, error))
6357 dev_flow->dv.actions[actions_n++] =
6358 dev_flow->dv.tag_resource->action;
6360 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6361 if (flow_dv_convert_action_set_tag
6363 (const struct rte_flow_action_set_tag *)
6364 actions->conf, error))
6366 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6368 case RTE_FLOW_ACTION_TYPE_DROP:
6369 action_flags |= MLX5_FLOW_ACTION_DROP;
6371 case RTE_FLOW_ACTION_TYPE_QUEUE:
6372 assert(flow->rss.queue);
6373 queue = actions->conf;
6374 flow->rss.queue_num = 1;
6375 (*flow->rss.queue)[0] = queue->index;
6376 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6378 case RTE_FLOW_ACTION_TYPE_RSS:
6379 assert(flow->rss.queue);
6380 rss = actions->conf;
6381 if (flow->rss.queue)
6382 memcpy((*flow->rss.queue), rss->queue,
6383 rss->queue_num * sizeof(uint16_t));
6384 flow->rss.queue_num = rss->queue_num;
6385 /* NULL RSS key indicates default RSS key. */
6386 rss_key = !rss->key ? rss_hash_default_key : rss->key;
6387 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
6389 * rss->level and rss.types should be set in advance
6390 * when expanding items for RSS.
6392 action_flags |= MLX5_FLOW_ACTION_RSS;
6394 case RTE_FLOW_ACTION_TYPE_COUNT:
6395 if (!dev_conf->devx) {
6396 rte_errno = ENOTSUP;
6399 flow->counter = flow_dv_counter_alloc(dev,
6403 if (flow->counter == NULL)
6405 dev_flow->dv.actions[actions_n++] =
6406 flow->counter->action;
6407 action_flags |= MLX5_FLOW_ACTION_COUNT;
6410 if (rte_errno == ENOTSUP)
6411 return rte_flow_error_set
6413 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6415 "count action not supported");
6417 return rte_flow_error_set
6419 RTE_FLOW_ERROR_TYPE_ACTION,
6421 "cannot create counter"
6424 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6425 dev_flow->dv.actions[actions_n++] =
6426 priv->sh->pop_vlan_action;
6427 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6429 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6430 flow_dev_get_vlan_info_from_items(items, &vlan);
6431 vlan.eth_proto = rte_be_to_cpu_16
6432 ((((const struct rte_flow_action_of_push_vlan *)
6433 actions->conf)->ethertype));
6434 found_action = mlx5_flow_find_action
6436 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
6438 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6439 found_action = mlx5_flow_find_action
6441 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
6443 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6444 if (flow_dv_create_action_push_vlan
6445 (dev, attr, &vlan, dev_flow, error))
6447 dev_flow->dv.actions[actions_n++] =
6448 dev_flow->dv.push_vlan_res->action;
6449 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6451 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6452 /* of_vlan_push action handled this action */
6453 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
6455 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6456 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6458 flow_dev_get_vlan_info_from_items(items, &vlan);
6459 mlx5_update_vlan_vid_pcp(actions, &vlan);
6460 /* If no VLAN push - this is a modify header action */
6461 if (flow_dv_convert_action_modify_vlan_vid
6462 (&mhdr_res, actions, error))
6464 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6466 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6467 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6468 if (flow_dv_create_action_l2_encap(dev, actions,
6473 dev_flow->dv.actions[actions_n++] =
6474 dev_flow->dv.encap_decap->verbs_action;
6475 action_flags |= actions->type ==
6476 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
6477 MLX5_FLOW_ACTION_VXLAN_ENCAP :
6478 MLX5_FLOW_ACTION_NVGRE_ENCAP;
6480 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6481 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6482 if (flow_dv_create_action_l2_decap(dev, dev_flow,
6486 dev_flow->dv.actions[actions_n++] =
6487 dev_flow->dv.encap_decap->verbs_action;
6488 action_flags |= actions->type ==
6489 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
6490 MLX5_FLOW_ACTION_VXLAN_DECAP :
6491 MLX5_FLOW_ACTION_NVGRE_DECAP;
6493 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6494 /* Handle encap with preceding decap. */
6495 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
6496 if (flow_dv_create_action_raw_encap
6497 (dev, actions, dev_flow, attr, error))
6499 dev_flow->dv.actions[actions_n++] =
6500 dev_flow->dv.encap_decap->verbs_action;
6502 /* Handle encap without preceding decap. */
6503 if (flow_dv_create_action_l2_encap
6504 (dev, actions, dev_flow, attr->transfer,
6507 dev_flow->dv.actions[actions_n++] =
6508 dev_flow->dv.encap_decap->verbs_action;
6510 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
6512 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6513 /* Check if this decap is followed by encap. */
6514 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
6515 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
6518 /* Handle decap only if it isn't followed by encap. */
6519 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6520 if (flow_dv_create_action_l2_decap
6521 (dev, dev_flow, attr->transfer, error))
6523 dev_flow->dv.actions[actions_n++] =
6524 dev_flow->dv.encap_decap->verbs_action;
6526 /* If decap is followed by encap, handle it at encap. */
6527 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
6529 case RTE_FLOW_ACTION_TYPE_JUMP:
6530 jump_data = action->conf;
6531 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
6532 jump_data->group, &table,
6536 tbl = flow_dv_tbl_resource_get(dev, table,
6538 attr->transfer, error);
6540 return rte_flow_error_set
6542 RTE_FLOW_ERROR_TYPE_ACTION,
6544 "cannot create jump action.");
6545 jump_tbl_resource.tbl = tbl;
6546 if (flow_dv_jump_tbl_resource_register
6547 (dev, &jump_tbl_resource, dev_flow, error)) {
6548 flow_dv_tbl_resource_release(tbl);
6549 return rte_flow_error_set
6551 RTE_FLOW_ERROR_TYPE_ACTION,
6553 "cannot create jump action.");
6555 dev_flow->dv.actions[actions_n++] =
6556 dev_flow->dv.jump->action;
6557 action_flags |= MLX5_FLOW_ACTION_JUMP;
6559 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6560 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6561 if (flow_dv_convert_action_modify_mac
6562 (&mhdr_res, actions, error))
6564 action_flags |= actions->type ==
6565 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6566 MLX5_FLOW_ACTION_SET_MAC_SRC :
6567 MLX5_FLOW_ACTION_SET_MAC_DST;
6569 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6570 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6571 if (flow_dv_convert_action_modify_ipv4
6572 (&mhdr_res, actions, error))
6574 action_flags |= actions->type ==
6575 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6576 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6577 MLX5_FLOW_ACTION_SET_IPV4_DST;
6579 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6580 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6581 if (flow_dv_convert_action_modify_ipv6
6582 (&mhdr_res, actions, error))
6584 action_flags |= actions->type ==
6585 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6586 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6587 MLX5_FLOW_ACTION_SET_IPV6_DST;
6589 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6590 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6591 if (flow_dv_convert_action_modify_tp
6592 (&mhdr_res, actions, items,
6595 action_flags |= actions->type ==
6596 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6597 MLX5_FLOW_ACTION_SET_TP_SRC :
6598 MLX5_FLOW_ACTION_SET_TP_DST;
6600 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6601 if (flow_dv_convert_action_modify_dec_ttl
6602 (&mhdr_res, items, &flow_attr, error))
6604 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
6606 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6607 if (flow_dv_convert_action_modify_ttl
6608 (&mhdr_res, actions, items,
6611 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
6613 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6614 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6615 if (flow_dv_convert_action_modify_tcp_seq
6616 (&mhdr_res, actions, error))
6618 action_flags |= actions->type ==
6619 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6620 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6621 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6624 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6625 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6626 if (flow_dv_convert_action_modify_tcp_ack
6627 (&mhdr_res, actions, error))
6629 action_flags |= actions->type ==
6630 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6631 MLX5_FLOW_ACTION_INC_TCP_ACK :
6632 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6634 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6635 if (flow_dv_convert_action_set_reg
6636 (&mhdr_res, actions, error))
6638 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6640 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6641 if (flow_dv_convert_action_copy_mreg
6642 (dev, &mhdr_res, actions, error))
6644 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6646 case RTE_FLOW_ACTION_TYPE_END:
6648 if (mhdr_res.actions_num) {
6649 /* create modify action if needed. */
6650 if (flow_dv_modify_hdr_resource_register
6651 (dev, &mhdr_res, dev_flow, error))
6653 dev_flow->dv.actions[modify_action_position] =
6654 dev_flow->dv.modify_hdr->verbs_action;
6660 if (mhdr_res.actions_num &&
6661 modify_action_position == UINT32_MAX)
6662 modify_action_position = actions_n++;
6664 dev_flow->dv.actions_n = actions_n;
6665 dev_flow->actions = action_flags;
6666 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6667 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6668 int item_type = items->type;
6670 switch (item_type) {
6671 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6672 flow_dv_translate_item_port_id(dev, match_mask,
6673 match_value, items);
6674 last_item = MLX5_FLOW_ITEM_PORT_ID;
6676 case RTE_FLOW_ITEM_TYPE_ETH:
6677 flow_dv_translate_item_eth(match_mask, match_value,
6679 matcher.priority = MLX5_PRIORITY_MAP_L2;
6680 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6681 MLX5_FLOW_LAYER_OUTER_L2;
6683 case RTE_FLOW_ITEM_TYPE_VLAN:
6684 flow_dv_translate_item_vlan(dev_flow,
6685 match_mask, match_value,
6687 matcher.priority = MLX5_PRIORITY_MAP_L2;
6688 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6689 MLX5_FLOW_LAYER_INNER_VLAN) :
6690 (MLX5_FLOW_LAYER_OUTER_L2 |
6691 MLX5_FLOW_LAYER_OUTER_VLAN);
6693 case RTE_FLOW_ITEM_TYPE_IPV4:
6694 mlx5_flow_tunnel_ip_check(items, next_protocol,
6695 &item_flags, &tunnel);
6696 flow_dv_translate_item_ipv4(match_mask, match_value,
6699 matcher.priority = MLX5_PRIORITY_MAP_L3;
6700 dev_flow->hash_fields |=
6701 mlx5_flow_hashfields_adjust
6703 MLX5_IPV4_LAYER_TYPES,
6704 MLX5_IPV4_IBV_RX_HASH);
6705 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6706 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6707 if (items->mask != NULL &&
6708 ((const struct rte_flow_item_ipv4 *)
6709 items->mask)->hdr.next_proto_id) {
6711 ((const struct rte_flow_item_ipv4 *)
6712 (items->spec))->hdr.next_proto_id;
6714 ((const struct rte_flow_item_ipv4 *)
6715 (items->mask))->hdr.next_proto_id;
6717 /* Reset for inner layer. */
6718 next_protocol = 0xff;
6721 case RTE_FLOW_ITEM_TYPE_IPV6:
6722 mlx5_flow_tunnel_ip_check(items, next_protocol,
6723 &item_flags, &tunnel);
6724 flow_dv_translate_item_ipv6(match_mask, match_value,
6727 matcher.priority = MLX5_PRIORITY_MAP_L3;
6728 dev_flow->hash_fields |=
6729 mlx5_flow_hashfields_adjust
6731 MLX5_IPV6_LAYER_TYPES,
6732 MLX5_IPV6_IBV_RX_HASH);
6733 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6734 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6735 if (items->mask != NULL &&
6736 ((const struct rte_flow_item_ipv6 *)
6737 items->mask)->hdr.proto) {
6739 ((const struct rte_flow_item_ipv6 *)
6740 items->spec)->hdr.proto;
6742 ((const struct rte_flow_item_ipv6 *)
6743 items->mask)->hdr.proto;
6745 /* Reset for inner layer. */
6746 next_protocol = 0xff;
6749 case RTE_FLOW_ITEM_TYPE_TCP:
6750 flow_dv_translate_item_tcp(match_mask, match_value,
6752 matcher.priority = MLX5_PRIORITY_MAP_L4;
6753 dev_flow->hash_fields |=
6754 mlx5_flow_hashfields_adjust
6755 (dev_flow, tunnel, ETH_RSS_TCP,
6756 IBV_RX_HASH_SRC_PORT_TCP |
6757 IBV_RX_HASH_DST_PORT_TCP);
6758 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6759 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6761 case RTE_FLOW_ITEM_TYPE_UDP:
6762 flow_dv_translate_item_udp(match_mask, match_value,
6764 matcher.priority = MLX5_PRIORITY_MAP_L4;
6765 dev_flow->hash_fields |=
6766 mlx5_flow_hashfields_adjust
6767 (dev_flow, tunnel, ETH_RSS_UDP,
6768 IBV_RX_HASH_SRC_PORT_UDP |
6769 IBV_RX_HASH_DST_PORT_UDP);
6770 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6771 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6773 case RTE_FLOW_ITEM_TYPE_GRE:
6774 flow_dv_translate_item_gre(match_mask, match_value,
6776 last_item = MLX5_FLOW_LAYER_GRE;
6778 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6779 flow_dv_translate_item_gre_key(match_mask,
6780 match_value, items);
6781 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6783 case RTE_FLOW_ITEM_TYPE_NVGRE:
6784 flow_dv_translate_item_nvgre(match_mask, match_value,
6786 last_item = MLX5_FLOW_LAYER_GRE;
6788 case RTE_FLOW_ITEM_TYPE_VXLAN:
6789 flow_dv_translate_item_vxlan(match_mask, match_value,
6791 last_item = MLX5_FLOW_LAYER_VXLAN;
6793 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6794 flow_dv_translate_item_vxlan(match_mask, match_value,
6796 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6798 case RTE_FLOW_ITEM_TYPE_GENEVE:
6799 flow_dv_translate_item_geneve(match_mask, match_value,
6801 last_item = MLX5_FLOW_LAYER_GENEVE;
6803 case RTE_FLOW_ITEM_TYPE_MPLS:
6804 flow_dv_translate_item_mpls(match_mask, match_value,
6805 items, last_item, tunnel);
6806 last_item = MLX5_FLOW_LAYER_MPLS;
6808 case RTE_FLOW_ITEM_TYPE_MARK:
6809 flow_dv_translate_item_mark(dev, match_mask,
6810 match_value, items);
6811 last_item = MLX5_FLOW_ITEM_MARK;
6813 case RTE_FLOW_ITEM_TYPE_META:
6814 flow_dv_translate_item_meta(match_mask, match_value,
6816 last_item = MLX5_FLOW_ITEM_METADATA;
6818 case RTE_FLOW_ITEM_TYPE_ICMP:
6819 flow_dv_translate_item_icmp(match_mask, match_value,
6821 last_item = MLX5_FLOW_LAYER_ICMP;
6823 case RTE_FLOW_ITEM_TYPE_ICMP6:
6824 flow_dv_translate_item_icmp6(match_mask, match_value,
6826 last_item = MLX5_FLOW_LAYER_ICMP6;
6828 case RTE_FLOW_ITEM_TYPE_TAG:
6829 flow_dv_translate_item_tag(dev, match_mask,
6830 match_value, items);
6831 last_item = MLX5_FLOW_ITEM_TAG;
6833 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6834 flow_dv_translate_mlx5_item_tag(match_mask,
6835 match_value, items);
6836 last_item = MLX5_FLOW_ITEM_TAG;
6838 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6839 flow_dv_translate_item_tx_queue(dev, match_mask,
6842 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6847 item_flags |= last_item;
6850 * In case of ingress traffic when E-Switch mode is enabled,
6851 * we have two cases where we need to set the source port manually.
6852 * The first one, is in case of Nic steering rule, and the second is
6853 * E-Switch rule where no port_id item was found. In both cases
6854 * the source port is set according the current port in use.
6856 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6857 (priv->representor || priv->master)) {
6858 if (flow_dv_translate_item_port_id(dev, match_mask,
6862 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6863 dev_flow->dv.value.buf));
6864 dev_flow->layers = item_flags;
6865 /* Register matcher. */
6866 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6868 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6870 matcher.egress = attr->egress;
6871 matcher.group = dev_flow->group;
6872 matcher.transfer = attr->transfer;
6873 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6879 * Apply the flow to the NIC, lock free,
6880 * (mutex should be acquired by caller).
6883 * Pointer to the Ethernet device structure.
6884 * @param[in, out] flow
6885 * Pointer to flow structure.
6887 * Pointer to error structure.
6890 * 0 on success, a negative errno value otherwise and rte_errno is set.
6893 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6894 struct rte_flow_error *error)
6896 struct mlx5_flow_dv *dv;
6897 struct mlx5_flow *dev_flow;
6898 struct mlx5_priv *priv = dev->data->dev_private;
6902 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6905 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6906 if (dev_flow->transfer) {
6907 dv->actions[n++] = priv->sh->esw_drop_action;
6909 dv->hrxq = mlx5_hrxq_drop_new(dev);
6913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6915 "cannot get drop hash queue");
6918 dv->actions[n++] = dv->hrxq->action;
6920 } else if (dev_flow->actions &
6921 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6922 struct mlx5_hrxq *hrxq;
6924 assert(flow->rss.queue);
6925 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
6926 MLX5_RSS_HASH_KEY_LEN,
6927 dev_flow->hash_fields,
6929 flow->rss.queue_num);
6931 hrxq = mlx5_hrxq_new
6932 (dev, flow->rss.key,
6933 MLX5_RSS_HASH_KEY_LEN,
6934 dev_flow->hash_fields,
6936 flow->rss.queue_num,
6937 !!(dev_flow->layers &
6938 MLX5_FLOW_LAYER_TUNNEL));
6943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6944 "cannot get hash queue");
6948 dv->actions[n++] = dv->hrxq->action;
6951 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6952 (void *)&dv->value, n,
6955 rte_flow_error_set(error, errno,
6956 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6958 "hardware refuses to create flow");
6961 if (priv->vmwa_context &&
6962 dev_flow->dv.vf_vlan.tag &&
6963 !dev_flow->dv.vf_vlan.created) {
6965 * The rule contains the VLAN pattern.
6966 * For VF we are going to create VLAN
6967 * interface to make hypervisor set correct
6968 * e-Switch vport context.
6970 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6975 err = rte_errno; /* Save rte_errno before cleanup. */
6976 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6977 struct mlx5_flow_dv *dv = &dev_flow->dv;
6979 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6980 mlx5_hrxq_drop_release(dev);
6982 mlx5_hrxq_release(dev, dv->hrxq);
6985 if (dev_flow->dv.vf_vlan.tag &&
6986 dev_flow->dv.vf_vlan.created)
6987 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6989 rte_errno = err; /* Restore rte_errno. */
6994 * Release the flow matcher.
6997 * Pointer to Ethernet device.
6999 * Pointer to mlx5_flow.
7002 * 1 while a reference on it exists, 0 when freed.
7005 flow_dv_matcher_release(struct rte_eth_dev *dev,
7006 struct mlx5_flow *flow)
7008 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7009 struct mlx5_priv *priv = dev->data->dev_private;
7010 struct mlx5_ibv_shared *sh = priv->sh;
7011 struct mlx5_flow_tbl_resource *tbl;
7013 assert(matcher->matcher_object);
7014 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7015 dev->data->port_id, (void *)matcher,
7016 rte_atomic32_read(&matcher->refcnt));
7017 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7018 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7019 (matcher->matcher_object));
7020 LIST_REMOVE(matcher, next);
7021 if (matcher->egress)
7022 tbl = &sh->tx_tbl[matcher->group];
7024 tbl = &sh->rx_tbl[matcher->group];
7025 flow_dv_tbl_resource_release(tbl);
7027 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7028 dev->data->port_id, (void *)matcher);
7035 * Release an encap/decap resource.
7038 * Pointer to mlx5_flow.
7041 * 1 while a reference on it exists, 0 when freed.
7044 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7046 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7047 flow->dv.encap_decap;
7049 assert(cache_resource->verbs_action);
7050 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7051 (void *)cache_resource,
7052 rte_atomic32_read(&cache_resource->refcnt));
7053 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7054 claim_zero(mlx5_glue->destroy_flow_action
7055 (cache_resource->verbs_action));
7056 LIST_REMOVE(cache_resource, next);
7057 rte_free(cache_resource);
7058 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7059 (void *)cache_resource);
7066 * Release an jump to table action resource.
7069 * Pointer to mlx5_flow.
7072 * 1 while a reference on it exists, 0 when freed.
7075 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
7077 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
7080 assert(cache_resource->action);
7081 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7082 (void *)cache_resource,
7083 rte_atomic32_read(&cache_resource->refcnt));
7084 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7085 claim_zero(mlx5_glue->destroy_flow_action
7086 (cache_resource->action));
7087 LIST_REMOVE(cache_resource, next);
7088 flow_dv_tbl_resource_release(cache_resource->tbl);
7089 rte_free(cache_resource);
7090 DRV_LOG(DEBUG, "jump table resource %p: removed",
7091 (void *)cache_resource);
7098 * Release a modify-header resource.
7101 * Pointer to mlx5_flow.
7104 * 1 while a reference on it exists, 0 when freed.
7107 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7109 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7110 flow->dv.modify_hdr;
7112 assert(cache_resource->verbs_action);
7113 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7114 (void *)cache_resource,
7115 rte_atomic32_read(&cache_resource->refcnt));
7116 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7117 claim_zero(mlx5_glue->destroy_flow_action
7118 (cache_resource->verbs_action));
7119 LIST_REMOVE(cache_resource, next);
7120 rte_free(cache_resource);
7121 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7122 (void *)cache_resource);
7129 * Release port ID action resource.
7132 * Pointer to mlx5_flow.
7135 * 1 while a reference on it exists, 0 when freed.
7138 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
7140 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
7141 flow->dv.port_id_action;
7143 assert(cache_resource->action);
7144 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
7145 (void *)cache_resource,
7146 rte_atomic32_read(&cache_resource->refcnt));
7147 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7148 claim_zero(mlx5_glue->destroy_flow_action
7149 (cache_resource->action));
7150 LIST_REMOVE(cache_resource, next);
7151 rte_free(cache_resource);
7152 DRV_LOG(DEBUG, "port id action resource %p: removed",
7153 (void *)cache_resource);
7160 * Release push vlan action resource.
7163 * Pointer to mlx5_flow.
7166 * 1 while a reference on it exists, 0 when freed.
7169 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
7171 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
7172 flow->dv.push_vlan_res;
7174 assert(cache_resource->action);
7175 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
7176 (void *)cache_resource,
7177 rte_atomic32_read(&cache_resource->refcnt));
7178 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7179 claim_zero(mlx5_glue->destroy_flow_action
7180 (cache_resource->action));
7181 LIST_REMOVE(cache_resource, next);
7182 rte_free(cache_resource);
7183 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
7184 (void *)cache_resource);
7191 * Remove the flow from the NIC but keeps it in memory.
7192 * Lock free, (mutex should be acquired by caller).
7195 * Pointer to Ethernet device.
7196 * @param[in, out] flow
7197 * Pointer to flow structure.
7200 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7202 struct mlx5_flow_dv *dv;
7203 struct mlx5_flow *dev_flow;
7207 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7210 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
7214 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7215 mlx5_hrxq_drop_release(dev);
7217 mlx5_hrxq_release(dev, dv->hrxq);
7220 if (dev_flow->dv.vf_vlan.tag &&
7221 dev_flow->dv.vf_vlan.created)
7222 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7227 * Remove the flow from the NIC and the memory.
7228 * Lock free, (mutex should be acquired by caller).
7231 * Pointer to the Ethernet device structure.
7232 * @param[in, out] flow
7233 * Pointer to flow structure.
7236 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
7238 struct mlx5_flow *dev_flow;
7242 __flow_dv_remove(dev, flow);
7243 if (flow->counter) {
7244 flow_dv_counter_release(dev, flow->counter);
7245 flow->counter = NULL;
7247 while (!LIST_EMPTY(&flow->dev_flows)) {
7248 dev_flow = LIST_FIRST(&flow->dev_flows);
7249 LIST_REMOVE(dev_flow, next);
7250 if (dev_flow->dv.matcher)
7251 flow_dv_matcher_release(dev, dev_flow);
7252 if (dev_flow->dv.encap_decap)
7253 flow_dv_encap_decap_resource_release(dev_flow);
7254 if (dev_flow->dv.modify_hdr)
7255 flow_dv_modify_hdr_resource_release(dev_flow);
7256 if (dev_flow->dv.jump)
7257 flow_dv_jump_tbl_resource_release(dev_flow);
7258 if (dev_flow->dv.port_id_action)
7259 flow_dv_port_id_action_resource_release(dev_flow);
7260 if (dev_flow->dv.push_vlan_res)
7261 flow_dv_push_vlan_action_resource_release(dev_flow);
7262 if (dev_flow->dv.tag_resource)
7263 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
7269 * Query a dv flow rule for its statistics via devx.
7272 * Pointer to Ethernet device.
7274 * Pointer to the sub flow.
7276 * data retrieved by the query.
7278 * Perform verbose error reporting if not NULL.
7281 * 0 on success, a negative errno value otherwise and rte_errno is set.
7284 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
7285 void *data, struct rte_flow_error *error)
7287 struct mlx5_priv *priv = dev->data->dev_private;
7288 struct rte_flow_query_count *qc = data;
7290 if (!priv->config.devx)
7291 return rte_flow_error_set(error, ENOTSUP,
7292 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7294 "counters are not supported");
7295 if (flow->counter) {
7296 uint64_t pkts, bytes;
7297 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
7301 return rte_flow_error_set(error, -err,
7302 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7303 NULL, "cannot read counters");
7306 qc->hits = pkts - flow->counter->hits;
7307 qc->bytes = bytes - flow->counter->bytes;
7309 flow->counter->hits = pkts;
7310 flow->counter->bytes = bytes;
7314 return rte_flow_error_set(error, EINVAL,
7315 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7317 "counters are not available");
7323 * @see rte_flow_query()
7327 flow_dv_query(struct rte_eth_dev *dev,
7328 struct rte_flow *flow __rte_unused,
7329 const struct rte_flow_action *actions __rte_unused,
7330 void *data __rte_unused,
7331 struct rte_flow_error *error __rte_unused)
7335 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7336 switch (actions->type) {
7337 case RTE_FLOW_ACTION_TYPE_VOID:
7339 case RTE_FLOW_ACTION_TYPE_COUNT:
7340 ret = flow_dv_query_count(dev, flow, data, error);
7343 return rte_flow_error_set(error, ENOTSUP,
7344 RTE_FLOW_ERROR_TYPE_ACTION,
7346 "action not supported");
7353 * Mutex-protected thunk to lock-free __flow_dv_translate().
7356 flow_dv_translate(struct rte_eth_dev *dev,
7357 struct mlx5_flow *dev_flow,
7358 const struct rte_flow_attr *attr,
7359 const struct rte_flow_item items[],
7360 const struct rte_flow_action actions[],
7361 struct rte_flow_error *error)
7365 flow_dv_shared_lock(dev);
7366 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
7367 flow_dv_shared_unlock(dev);
7372 * Mutex-protected thunk to lock-free __flow_dv_apply().
7375 flow_dv_apply(struct rte_eth_dev *dev,
7376 struct rte_flow *flow,
7377 struct rte_flow_error *error)
7381 flow_dv_shared_lock(dev);
7382 ret = __flow_dv_apply(dev, flow, error);
7383 flow_dv_shared_unlock(dev);
7388 * Mutex-protected thunk to lock-free __flow_dv_remove().
7391 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7393 flow_dv_shared_lock(dev);
7394 __flow_dv_remove(dev, flow);
7395 flow_dv_shared_unlock(dev);
7399 * Mutex-protected thunk to lock-free __flow_dv_destroy().
7402 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
7404 flow_dv_shared_lock(dev);
7405 __flow_dv_destroy(dev, flow);
7406 flow_dv_shared_unlock(dev);
7409 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
7410 .validate = flow_dv_validate,
7411 .prepare = flow_dv_prepare,
7412 .translate = flow_dv_translate,
7413 .apply = flow_dv_apply,
7414 .remove = flow_dv_remove,
7415 .destroy = flow_dv_destroy,
7416 .query = flow_dv_query,
7419 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */