1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_dv_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_dv_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_NONE] = MLX5_MODI_OUT_NONE,
836 [REG_A] = MLX5_MODI_META_DATA_REG_A,
837 [REG_B] = MLX5_MODI_META_DATA_REG_B,
838 [REG_C_0] = MLX5_MODI_META_REG_C_0,
839 [REG_C_1] = MLX5_MODI_META_REG_C_1,
840 [REG_C_2] = MLX5_MODI_META_REG_C_2,
841 [REG_C_3] = MLX5_MODI_META_REG_C_3,
842 [REG_C_4] = MLX5_MODI_META_REG_C_4,
843 [REG_C_5] = MLX5_MODI_META_REG_C_5,
844 [REG_C_6] = MLX5_MODI_META_REG_C_6,
845 [REG_C_7] = MLX5_MODI_META_REG_C_7,
849 * Convert register set to DV specification.
851 * @param[in,out] resource
852 * Pointer to the modify-header resource.
854 * Pointer to action specification.
856 * Pointer to the error structure.
859 * 0 on success, a negative errno value otherwise and rte_errno is set.
862 flow_dv_convert_action_set_reg
863 (struct mlx5_flow_dv_modify_hdr_resource *resource,
864 const struct rte_flow_action *action,
865 struct rte_flow_error *error)
867 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
868 struct mlx5_modification_cmd *actions = resource->actions;
869 uint32_t i = resource->actions_num;
871 if (i >= MLX5_MODIFY_NUM)
872 return rte_flow_error_set(error, EINVAL,
873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
874 "too many items to modify");
875 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
876 actions[i].field = reg_to_field[conf->id];
877 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
878 actions[i].data1 = conf->data;
880 resource->actions_num = i;
881 if (!resource->actions_num)
882 return rte_flow_error_set(error, EINVAL,
883 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
884 "invalid modification flow item");
889 * Convert internal COPY_REG action to DV specification.
892 * Pointer to the rte_eth_dev structure.
894 * Pointer to the modify-header resource.
896 * Pointer to action specification.
898 * Pointer to the error structure.
901 * 0 on success, a negative errno value otherwise and rte_errno is set.
904 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev __rte_unused,
905 struct mlx5_flow_dv_modify_hdr_resource *res,
906 const struct rte_flow_action *action,
907 struct rte_flow_error *error)
909 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
910 uint32_t mask = RTE_BE32(UINT32_MAX);
911 struct rte_flow_item item = {
915 struct field_modify_info reg_src[] = {
916 {4, 0, reg_to_field[conf->src]},
919 struct field_modify_info reg_dst = {
920 .offset = (uint32_t)-1, /* Same as src. */
921 .id = reg_to_field[conf->dst],
923 return flow_dv_convert_modify_action(&item,
924 reg_src, ®_dst, res,
925 MLX5_MODIFICATION_TYPE_COPY,
930 * Validate META item.
933 * Pointer to the rte_eth_dev structure.
935 * Item specification.
937 * Attributes of flow that includes this item.
939 * Pointer to error structure.
942 * 0 on success, a negative errno value otherwise and rte_errno is set.
945 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
946 const struct rte_flow_item *item,
947 const struct rte_flow_attr *attr,
948 struct rte_flow_error *error)
950 const struct rte_flow_item_meta *spec = item->spec;
951 const struct rte_flow_item_meta *mask = item->mask;
952 const struct rte_flow_item_meta nic_mask = {
958 return rte_flow_error_set(error, EINVAL,
959 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
961 "data cannot be empty");
963 return rte_flow_error_set(error, EINVAL,
964 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
966 "data cannot be zero");
968 mask = &rte_flow_item_meta_mask;
969 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
970 (const uint8_t *)&nic_mask,
971 sizeof(struct rte_flow_item_meta),
976 return rte_flow_error_set(error, ENOTSUP,
977 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
979 "pattern not supported for ingress");
984 * Validate vport item.
987 * Pointer to the rte_eth_dev structure.
989 * Item specification.
991 * Attributes of flow that includes this item.
992 * @param[in] item_flags
993 * Bit-fields that holds the items detected until now.
995 * Pointer to error structure.
998 * 0 on success, a negative errno value otherwise and rte_errno is set.
1001 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1002 const struct rte_flow_item *item,
1003 const struct rte_flow_attr *attr,
1004 uint64_t item_flags,
1005 struct rte_flow_error *error)
1007 const struct rte_flow_item_port_id *spec = item->spec;
1008 const struct rte_flow_item_port_id *mask = item->mask;
1009 const struct rte_flow_item_port_id switch_mask = {
1012 struct mlx5_priv *esw_priv;
1013 struct mlx5_priv *dev_priv;
1016 if (!attr->transfer)
1017 return rte_flow_error_set(error, EINVAL,
1018 RTE_FLOW_ERROR_TYPE_ITEM,
1020 "match on port id is valid only"
1021 " when transfer flag is enabled");
1022 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1023 return rte_flow_error_set(error, ENOTSUP,
1024 RTE_FLOW_ERROR_TYPE_ITEM, item,
1025 "multiple source ports are not"
1028 mask = &switch_mask;
1029 if (mask->id != 0xffffffff)
1030 return rte_flow_error_set(error, ENOTSUP,
1031 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1033 "no support for partial mask on"
1035 ret = mlx5_flow_item_acceptable
1036 (item, (const uint8_t *)mask,
1037 (const uint8_t *)&rte_flow_item_port_id_mask,
1038 sizeof(struct rte_flow_item_port_id),
1044 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1046 return rte_flow_error_set(error, rte_errno,
1047 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1048 "failed to obtain E-Switch info for"
1050 dev_priv = mlx5_dev_to_eswitch_info(dev);
1052 return rte_flow_error_set(error, rte_errno,
1053 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1055 "failed to obtain E-Switch info");
1056 if (esw_priv->domain_id != dev_priv->domain_id)
1057 return rte_flow_error_set(error, EINVAL,
1058 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1059 "cannot match on a port from a"
1060 " different E-Switch");
1065 * Validate the pop VLAN action.
1068 * Pointer to the rte_eth_dev structure.
1069 * @param[in] action_flags
1070 * Holds the actions detected until now.
1072 * Pointer to the pop vlan action.
1073 * @param[in] item_flags
1074 * The items found in this flow rule.
1076 * Pointer to flow attributes.
1078 * Pointer to error structure.
1081 * 0 on success, a negative errno value otherwise and rte_errno is set.
1084 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1085 uint64_t action_flags,
1086 const struct rte_flow_action *action,
1087 uint64_t item_flags,
1088 const struct rte_flow_attr *attr,
1089 struct rte_flow_error *error)
1091 struct mlx5_priv *priv = dev->data->dev_private;
1095 if (!priv->sh->pop_vlan_action)
1096 return rte_flow_error_set(error, ENOTSUP,
1097 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1099 "pop vlan action is not supported");
1101 * Check for inconsistencies:
1102 * fail strip_vlan in a flow that matches packets without VLAN tags.
1103 * fail strip_vlan in a flow that matches packets without explicitly a
1104 * matching on VLAN tag ?
1106 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1107 return rte_flow_error_set(error, ENOTSUP,
1108 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1110 "no support for multiple vlan pop "
1112 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1113 return rte_flow_error_set(error, ENOTSUP,
1114 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1116 "cannot pop vlan without a "
1117 "match on (outer) vlan in the flow");
1118 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1119 return rte_flow_error_set(error, EINVAL,
1120 RTE_FLOW_ERROR_TYPE_ACTION, action,
1121 "wrong action order, port_id should "
1122 "be after pop VLAN action");
1127 * Get VLAN default info from vlan match info.
1130 * Pointer to the rte_eth_dev structure.
1132 * the list of item specifications.
1134 * pointer VLAN info to fill to.
1136 * Pointer to error structure.
1139 * 0 on success, a negative errno value otherwise and rte_errno is set.
1142 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1143 struct rte_vlan_hdr *vlan)
1145 const struct rte_flow_item_vlan nic_mask = {
1146 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1147 MLX5DV_FLOW_VLAN_VID_MASK),
1148 .inner_type = RTE_BE16(0xffff),
1153 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1154 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1156 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1157 const struct rte_flow_item_vlan *vlan_m = items->mask;
1158 const struct rte_flow_item_vlan *vlan_v = items->spec;
1162 /* Only full match values are accepted */
1163 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1164 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1165 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1167 rte_be_to_cpu_16(vlan_v->tci &
1168 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1170 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1171 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1172 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1174 rte_be_to_cpu_16(vlan_v->tci &
1175 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1177 if (vlan_m->inner_type == nic_mask.inner_type)
1178 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1179 vlan_m->inner_type);
1184 * Validate the push VLAN action.
1186 * @param[in] action_flags
1187 * Holds the actions detected until now.
1189 * Pointer to the encap action.
1191 * Pointer to flow attributes
1193 * Pointer to error structure.
1196 * 0 on success, a negative errno value otherwise and rte_errno is set.
1199 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1200 uint64_t item_flags,
1201 const struct rte_flow_action *action,
1202 const struct rte_flow_attr *attr,
1203 struct rte_flow_error *error)
1205 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1207 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1208 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1209 return rte_flow_error_set(error, EINVAL,
1210 RTE_FLOW_ERROR_TYPE_ACTION, action,
1211 "invalid vlan ethertype");
1213 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1214 return rte_flow_error_set(error, ENOTSUP,
1215 RTE_FLOW_ERROR_TYPE_ACTION, action,
1216 "no support for multiple VLAN "
1218 if (!mlx5_flow_find_action
1219 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1220 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1221 return rte_flow_error_set(error, ENOTSUP,
1222 RTE_FLOW_ERROR_TYPE_ACTION, action,
1223 "push VLAN needs to match on VLAN in order to "
1224 "get VLAN VID information because there is "
1225 "no followed set VLAN VID action");
1226 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1227 return rte_flow_error_set(error, EINVAL,
1228 RTE_FLOW_ERROR_TYPE_ACTION, action,
1229 "wrong action order, port_id should "
1230 "be after push VLAN");
1236 * Validate the set VLAN PCP.
1238 * @param[in] action_flags
1239 * Holds the actions detected until now.
1240 * @param[in] actions
1241 * Pointer to the list of actions remaining in the flow rule.
1243 * Pointer to flow attributes
1245 * Pointer to error structure.
1248 * 0 on success, a negative errno value otherwise and rte_errno is set.
1251 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1252 const struct rte_flow_action actions[],
1253 struct rte_flow_error *error)
1255 const struct rte_flow_action *action = actions;
1256 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1258 if (conf->vlan_pcp > 7)
1259 return rte_flow_error_set(error, EINVAL,
1260 RTE_FLOW_ERROR_TYPE_ACTION, action,
1261 "VLAN PCP value is too big");
1262 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1263 return rte_flow_error_set(error, ENOTSUP,
1264 RTE_FLOW_ERROR_TYPE_ACTION, action,
1265 "set VLAN PCP action must follow "
1266 "the push VLAN action");
1267 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1268 return rte_flow_error_set(error, ENOTSUP,
1269 RTE_FLOW_ERROR_TYPE_ACTION, action,
1270 "Multiple VLAN PCP modification are "
1272 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1273 return rte_flow_error_set(error, EINVAL,
1274 RTE_FLOW_ERROR_TYPE_ACTION, action,
1275 "wrong action order, port_id should "
1276 "be after set VLAN PCP");
1281 * Validate the set VLAN VID.
1283 * @param[in] item_flags
1284 * Holds the items detected in this rule.
1285 * @param[in] actions
1286 * Pointer to the list of actions remaining in the flow rule.
1288 * Pointer to flow attributes
1290 * Pointer to error structure.
1293 * 0 on success, a negative errno value otherwise and rte_errno is set.
1296 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1297 uint64_t action_flags,
1298 const struct rte_flow_action actions[],
1299 struct rte_flow_error *error)
1301 const struct rte_flow_action *action = actions;
1302 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1304 if (conf->vlan_vid > RTE_BE16(0xFFE))
1305 return rte_flow_error_set(error, EINVAL,
1306 RTE_FLOW_ERROR_TYPE_ACTION, action,
1307 "VLAN VID value is too big");
1308 /* there is an of_push_vlan action before us */
1309 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1310 if (mlx5_flow_find_action(actions + 1,
1311 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1312 return rte_flow_error_set(error, ENOTSUP,
1313 RTE_FLOW_ERROR_TYPE_ACTION, action,
1314 "Multiple VLAN VID modifications are "
1321 * Action is on an existing VLAN header:
1322 * Need to verify this is a single modify CID action.
1323 * Rule mast include a match on outer VLAN.
1325 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1326 return rte_flow_error_set(error, ENOTSUP,
1327 RTE_FLOW_ERROR_TYPE_ACTION, action,
1328 "Multiple VLAN VID modifications are "
1330 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1331 return rte_flow_error_set(error, EINVAL,
1332 RTE_FLOW_ERROR_TYPE_ACTION, action,
1333 "match on VLAN is required in order "
1335 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1336 return rte_flow_error_set(error, EINVAL,
1337 RTE_FLOW_ERROR_TYPE_ACTION, action,
1338 "wrong action order, port_id should "
1339 "be after set VLAN VID");
1344 * Validate count action.
1349 * Pointer to error structure.
1352 * 0 on success, a negative errno value otherwise and rte_errno is set.
1355 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1356 struct rte_flow_error *error)
1358 struct mlx5_priv *priv = dev->data->dev_private;
1360 if (!priv->config.devx)
1362 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1366 return rte_flow_error_set
1368 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1370 "count action not supported");
1374 * Validate the L2 encap action.
1376 * @param[in] action_flags
1377 * Holds the actions detected until now.
1379 * Pointer to the encap action.
1381 * Pointer to flow attributes
1383 * Pointer to error structure.
1386 * 0 on success, a negative errno value otherwise and rte_errno is set.
1389 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1390 const struct rte_flow_action *action,
1391 const struct rte_flow_attr *attr,
1392 struct rte_flow_error *error)
1394 if (!(action->conf))
1395 return rte_flow_error_set(error, EINVAL,
1396 RTE_FLOW_ERROR_TYPE_ACTION, action,
1397 "configuration cannot be null");
1398 if (action_flags & MLX5_FLOW_ACTION_DROP)
1399 return rte_flow_error_set(error, EINVAL,
1400 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1401 "can't drop and encap in same flow");
1402 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1403 return rte_flow_error_set(error, EINVAL,
1404 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1405 "can only have a single encap or"
1406 " decap action in a flow");
1407 if (!attr->transfer && attr->ingress)
1408 return rte_flow_error_set(error, ENOTSUP,
1409 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1411 "encap action not supported for "
1417 * Validate the L2 decap action.
1419 * @param[in] action_flags
1420 * Holds the actions detected until now.
1422 * Pointer to flow attributes
1424 * Pointer to error structure.
1427 * 0 on success, a negative errno value otherwise and rte_errno is set.
1430 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1431 const struct rte_flow_attr *attr,
1432 struct rte_flow_error *error)
1434 if (action_flags & MLX5_FLOW_ACTION_DROP)
1435 return rte_flow_error_set(error, EINVAL,
1436 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1437 "can't drop and decap in same flow");
1438 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1439 return rte_flow_error_set(error, EINVAL,
1440 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1441 "can only have a single encap or"
1442 " decap action in a flow");
1443 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1444 return rte_flow_error_set(error, EINVAL,
1445 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1446 "can't have decap action after"
1449 return rte_flow_error_set(error, ENOTSUP,
1450 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1452 "decap action not supported for "
1458 * Validate the raw encap action.
1460 * @param[in] action_flags
1461 * Holds the actions detected until now.
1463 * Pointer to the encap action.
1465 * Pointer to flow attributes
1467 * Pointer to error structure.
1470 * 0 on success, a negative errno value otherwise and rte_errno is set.
1473 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1474 const struct rte_flow_action *action,
1475 const struct rte_flow_attr *attr,
1476 struct rte_flow_error *error)
1478 const struct rte_flow_action_raw_encap *raw_encap =
1479 (const struct rte_flow_action_raw_encap *)action->conf;
1480 if (!(action->conf))
1481 return rte_flow_error_set(error, EINVAL,
1482 RTE_FLOW_ERROR_TYPE_ACTION, action,
1483 "configuration cannot be null");
1484 if (action_flags & MLX5_FLOW_ACTION_DROP)
1485 return rte_flow_error_set(error, EINVAL,
1486 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1487 "can't drop and encap in same flow");
1488 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1489 return rte_flow_error_set(error, EINVAL,
1490 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1491 "can only have a single encap"
1492 " action in a flow");
1493 /* encap without preceding decap is not supported for ingress */
1494 if (!attr->transfer && attr->ingress &&
1495 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1496 return rte_flow_error_set(error, ENOTSUP,
1497 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1499 "encap action not supported for "
1501 if (!raw_encap->size || !raw_encap->data)
1502 return rte_flow_error_set(error, EINVAL,
1503 RTE_FLOW_ERROR_TYPE_ACTION, action,
1504 "raw encap data cannot be empty");
1509 * Validate the raw decap action.
1511 * @param[in] action_flags
1512 * Holds the actions detected until now.
1514 * Pointer to the encap action.
1516 * Pointer to flow attributes
1518 * Pointer to error structure.
1521 * 0 on success, a negative errno value otherwise and rte_errno is set.
1524 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1525 const struct rte_flow_action *action,
1526 const struct rte_flow_attr *attr,
1527 struct rte_flow_error *error)
1529 if (action_flags & MLX5_FLOW_ACTION_DROP)
1530 return rte_flow_error_set(error, EINVAL,
1531 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1532 "can't drop and decap in same flow");
1533 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1534 return rte_flow_error_set(error, EINVAL,
1535 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1536 "can't have encap action before"
1538 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1539 return rte_flow_error_set(error, EINVAL,
1540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1541 "can only have a single decap"
1542 " action in a flow");
1543 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1546 "can't have decap action after"
1548 /* decap action is valid on egress only if it is followed by encap */
1550 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1551 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1554 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1555 return rte_flow_error_set
1557 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1558 NULL, "decap action not supported"
1565 * Find existing encap/decap resource or create and register a new one.
1567 * @param dev[in, out]
1568 * Pointer to rte_eth_dev structure.
1569 * @param[in, out] resource
1570 * Pointer to encap/decap resource.
1571 * @parm[in, out] dev_flow
1572 * Pointer to the dev_flow.
1574 * pointer to error structure.
1577 * 0 on success otherwise -errno and errno is set.
1580 flow_dv_encap_decap_resource_register
1581 (struct rte_eth_dev *dev,
1582 struct mlx5_flow_dv_encap_decap_resource *resource,
1583 struct mlx5_flow *dev_flow,
1584 struct rte_flow_error *error)
1586 struct mlx5_priv *priv = dev->data->dev_private;
1587 struct mlx5_ibv_shared *sh = priv->sh;
1588 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1589 struct mlx5dv_dr_domain *domain;
1591 resource->flags = dev_flow->group ? 0 : 1;
1592 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1593 domain = sh->fdb_domain;
1594 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1595 domain = sh->rx_domain;
1597 domain = sh->tx_domain;
1599 /* Lookup a matching resource from cache. */
1600 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1601 if (resource->reformat_type == cache_resource->reformat_type &&
1602 resource->ft_type == cache_resource->ft_type &&
1603 resource->flags == cache_resource->flags &&
1604 resource->size == cache_resource->size &&
1605 !memcmp((const void *)resource->buf,
1606 (const void *)cache_resource->buf,
1608 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1609 (void *)cache_resource,
1610 rte_atomic32_read(&cache_resource->refcnt));
1611 rte_atomic32_inc(&cache_resource->refcnt);
1612 dev_flow->dv.encap_decap = cache_resource;
1616 /* Register new encap/decap resource. */
1617 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1618 if (!cache_resource)
1619 return rte_flow_error_set(error, ENOMEM,
1620 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1621 "cannot allocate resource memory");
1622 *cache_resource = *resource;
1623 cache_resource->verbs_action =
1624 mlx5_glue->dv_create_flow_action_packet_reformat
1625 (sh->ctx, cache_resource->reformat_type,
1626 cache_resource->ft_type, domain, cache_resource->flags,
1627 cache_resource->size,
1628 (cache_resource->size ? cache_resource->buf : NULL));
1629 if (!cache_resource->verbs_action) {
1630 rte_free(cache_resource);
1631 return rte_flow_error_set(error, ENOMEM,
1632 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1633 NULL, "cannot create action");
1635 rte_atomic32_init(&cache_resource->refcnt);
1636 rte_atomic32_inc(&cache_resource->refcnt);
1637 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1638 dev_flow->dv.encap_decap = cache_resource;
1639 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1640 (void *)cache_resource,
1641 rte_atomic32_read(&cache_resource->refcnt));
1646 * Find existing table jump resource or create and register a new one.
1648 * @param dev[in, out]
1649 * Pointer to rte_eth_dev structure.
1650 * @param[in, out] resource
1651 * Pointer to jump table resource.
1652 * @parm[in, out] dev_flow
1653 * Pointer to the dev_flow.
1655 * pointer to error structure.
1658 * 0 on success otherwise -errno and errno is set.
1661 flow_dv_jump_tbl_resource_register
1662 (struct rte_eth_dev *dev,
1663 struct mlx5_flow_dv_jump_tbl_resource *resource,
1664 struct mlx5_flow *dev_flow,
1665 struct rte_flow_error *error)
1667 struct mlx5_priv *priv = dev->data->dev_private;
1668 struct mlx5_ibv_shared *sh = priv->sh;
1669 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1671 /* Lookup a matching resource from cache. */
1672 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1673 if (resource->tbl == cache_resource->tbl) {
1674 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1675 (void *)cache_resource,
1676 rte_atomic32_read(&cache_resource->refcnt));
1677 rte_atomic32_inc(&cache_resource->refcnt);
1678 dev_flow->dv.jump = cache_resource;
1682 /* Register new jump table resource. */
1683 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1684 if (!cache_resource)
1685 return rte_flow_error_set(error, ENOMEM,
1686 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1687 "cannot allocate resource memory");
1688 *cache_resource = *resource;
1689 cache_resource->action =
1690 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1691 (resource->tbl->obj);
1692 if (!cache_resource->action) {
1693 rte_free(cache_resource);
1694 return rte_flow_error_set(error, ENOMEM,
1695 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1696 NULL, "cannot create action");
1698 rte_atomic32_init(&cache_resource->refcnt);
1699 rte_atomic32_inc(&cache_resource->refcnt);
1700 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1701 dev_flow->dv.jump = cache_resource;
1702 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1703 (void *)cache_resource,
1704 rte_atomic32_read(&cache_resource->refcnt));
1709 * Find existing table port ID resource or create and register a new one.
1711 * @param dev[in, out]
1712 * Pointer to rte_eth_dev structure.
1713 * @param[in, out] resource
1714 * Pointer to port ID action resource.
1715 * @parm[in, out] dev_flow
1716 * Pointer to the dev_flow.
1718 * pointer to error structure.
1721 * 0 on success otherwise -errno and errno is set.
1724 flow_dv_port_id_action_resource_register
1725 (struct rte_eth_dev *dev,
1726 struct mlx5_flow_dv_port_id_action_resource *resource,
1727 struct mlx5_flow *dev_flow,
1728 struct rte_flow_error *error)
1730 struct mlx5_priv *priv = dev->data->dev_private;
1731 struct mlx5_ibv_shared *sh = priv->sh;
1732 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1734 /* Lookup a matching resource from cache. */
1735 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1736 if (resource->port_id == cache_resource->port_id) {
1737 DRV_LOG(DEBUG, "port id action resource resource %p: "
1739 (void *)cache_resource,
1740 rte_atomic32_read(&cache_resource->refcnt));
1741 rte_atomic32_inc(&cache_resource->refcnt);
1742 dev_flow->dv.port_id_action = cache_resource;
1746 /* Register new port id action resource. */
1747 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1748 if (!cache_resource)
1749 return rte_flow_error_set(error, ENOMEM,
1750 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1751 "cannot allocate resource memory");
1752 *cache_resource = *resource;
1753 cache_resource->action =
1754 mlx5_glue->dr_create_flow_action_dest_vport
1755 (priv->sh->fdb_domain, resource->port_id);
1756 if (!cache_resource->action) {
1757 rte_free(cache_resource);
1758 return rte_flow_error_set(error, ENOMEM,
1759 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1760 NULL, "cannot create action");
1762 rte_atomic32_init(&cache_resource->refcnt);
1763 rte_atomic32_inc(&cache_resource->refcnt);
1764 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1765 dev_flow->dv.port_id_action = cache_resource;
1766 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1767 (void *)cache_resource,
1768 rte_atomic32_read(&cache_resource->refcnt));
1773 * Find existing push vlan resource or create and register a new one.
1775 * @param dev[in, out]
1776 * Pointer to rte_eth_dev structure.
1777 * @param[in, out] resource
1778 * Pointer to port ID action resource.
1779 * @parm[in, out] dev_flow
1780 * Pointer to the dev_flow.
1782 * pointer to error structure.
1785 * 0 on success otherwise -errno and errno is set.
1788 flow_dv_push_vlan_action_resource_register
1789 (struct rte_eth_dev *dev,
1790 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1791 struct mlx5_flow *dev_flow,
1792 struct rte_flow_error *error)
1794 struct mlx5_priv *priv = dev->data->dev_private;
1795 struct mlx5_ibv_shared *sh = priv->sh;
1796 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1797 struct mlx5dv_dr_domain *domain;
1799 /* Lookup a matching resource from cache. */
1800 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1801 if (resource->vlan_tag == cache_resource->vlan_tag &&
1802 resource->ft_type == cache_resource->ft_type) {
1803 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1805 (void *)cache_resource,
1806 rte_atomic32_read(&cache_resource->refcnt));
1807 rte_atomic32_inc(&cache_resource->refcnt);
1808 dev_flow->dv.push_vlan_res = cache_resource;
1812 /* Register new push_vlan action resource. */
1813 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1814 if (!cache_resource)
1815 return rte_flow_error_set(error, ENOMEM,
1816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1817 "cannot allocate resource memory");
1818 *cache_resource = *resource;
1819 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1820 domain = sh->fdb_domain;
1821 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1822 domain = sh->rx_domain;
1824 domain = sh->tx_domain;
1825 cache_resource->action =
1826 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1827 resource->vlan_tag);
1828 if (!cache_resource->action) {
1829 rte_free(cache_resource);
1830 return rte_flow_error_set(error, ENOMEM,
1831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1832 NULL, "cannot create action");
1834 rte_atomic32_init(&cache_resource->refcnt);
1835 rte_atomic32_inc(&cache_resource->refcnt);
1836 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1837 dev_flow->dv.push_vlan_res = cache_resource;
1838 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1839 (void *)cache_resource,
1840 rte_atomic32_read(&cache_resource->refcnt));
1844 * Get the size of specific rte_flow_item_type
1846 * @param[in] item_type
1847 * Tested rte_flow_item_type.
1850 * sizeof struct item_type, 0 if void or irrelevant.
1853 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1857 switch (item_type) {
1858 case RTE_FLOW_ITEM_TYPE_ETH:
1859 retval = sizeof(struct rte_flow_item_eth);
1861 case RTE_FLOW_ITEM_TYPE_VLAN:
1862 retval = sizeof(struct rte_flow_item_vlan);
1864 case RTE_FLOW_ITEM_TYPE_IPV4:
1865 retval = sizeof(struct rte_flow_item_ipv4);
1867 case RTE_FLOW_ITEM_TYPE_IPV6:
1868 retval = sizeof(struct rte_flow_item_ipv6);
1870 case RTE_FLOW_ITEM_TYPE_UDP:
1871 retval = sizeof(struct rte_flow_item_udp);
1873 case RTE_FLOW_ITEM_TYPE_TCP:
1874 retval = sizeof(struct rte_flow_item_tcp);
1876 case RTE_FLOW_ITEM_TYPE_VXLAN:
1877 retval = sizeof(struct rte_flow_item_vxlan);
1879 case RTE_FLOW_ITEM_TYPE_GRE:
1880 retval = sizeof(struct rte_flow_item_gre);
1882 case RTE_FLOW_ITEM_TYPE_NVGRE:
1883 retval = sizeof(struct rte_flow_item_nvgre);
1885 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1886 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1888 case RTE_FLOW_ITEM_TYPE_MPLS:
1889 retval = sizeof(struct rte_flow_item_mpls);
1891 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1899 #define MLX5_ENCAP_IPV4_VERSION 0x40
1900 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1901 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1902 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1903 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1904 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1905 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1908 * Convert the encap action data from list of rte_flow_item to raw buffer
1911 * Pointer to rte_flow_item objects list.
1913 * Pointer to the output buffer.
1915 * Pointer to the output buffer size.
1917 * Pointer to the error structure.
1920 * 0 on success, a negative errno value otherwise and rte_errno is set.
1923 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1924 size_t *size, struct rte_flow_error *error)
1926 struct rte_ether_hdr *eth = NULL;
1927 struct rte_vlan_hdr *vlan = NULL;
1928 struct rte_ipv4_hdr *ipv4 = NULL;
1929 struct rte_ipv6_hdr *ipv6 = NULL;
1930 struct rte_udp_hdr *udp = NULL;
1931 struct rte_vxlan_hdr *vxlan = NULL;
1932 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1933 struct rte_gre_hdr *gre = NULL;
1935 size_t temp_size = 0;
1938 return rte_flow_error_set(error, EINVAL,
1939 RTE_FLOW_ERROR_TYPE_ACTION,
1940 NULL, "invalid empty data");
1941 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1942 len = flow_dv_get_item_len(items->type);
1943 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1944 return rte_flow_error_set(error, EINVAL,
1945 RTE_FLOW_ERROR_TYPE_ACTION,
1946 (void *)items->type,
1947 "items total size is too big"
1948 " for encap action");
1949 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1950 switch (items->type) {
1951 case RTE_FLOW_ITEM_TYPE_ETH:
1952 eth = (struct rte_ether_hdr *)&buf[temp_size];
1954 case RTE_FLOW_ITEM_TYPE_VLAN:
1955 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1957 return rte_flow_error_set(error, EINVAL,
1958 RTE_FLOW_ERROR_TYPE_ACTION,
1959 (void *)items->type,
1960 "eth header not found");
1961 if (!eth->ether_type)
1962 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1964 case RTE_FLOW_ITEM_TYPE_IPV4:
1965 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION,
1969 (void *)items->type,
1970 "neither eth nor vlan"
1972 if (vlan && !vlan->eth_proto)
1973 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1974 else if (eth && !eth->ether_type)
1975 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1976 if (!ipv4->version_ihl)
1977 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1978 MLX5_ENCAP_IPV4_IHL_MIN;
1979 if (!ipv4->time_to_live)
1980 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1982 case RTE_FLOW_ITEM_TYPE_IPV6:
1983 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1985 return rte_flow_error_set(error, EINVAL,
1986 RTE_FLOW_ERROR_TYPE_ACTION,
1987 (void *)items->type,
1988 "neither eth nor vlan"
1990 if (vlan && !vlan->eth_proto)
1991 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1992 else if (eth && !eth->ether_type)
1993 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1994 if (!ipv6->vtc_flow)
1996 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1997 if (!ipv6->hop_limits)
1998 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2000 case RTE_FLOW_ITEM_TYPE_UDP:
2001 udp = (struct rte_udp_hdr *)&buf[temp_size];
2003 return rte_flow_error_set(error, EINVAL,
2004 RTE_FLOW_ERROR_TYPE_ACTION,
2005 (void *)items->type,
2006 "ip header not found");
2007 if (ipv4 && !ipv4->next_proto_id)
2008 ipv4->next_proto_id = IPPROTO_UDP;
2009 else if (ipv6 && !ipv6->proto)
2010 ipv6->proto = IPPROTO_UDP;
2012 case RTE_FLOW_ITEM_TYPE_VXLAN:
2013 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2015 return rte_flow_error_set(error, EINVAL,
2016 RTE_FLOW_ERROR_TYPE_ACTION,
2017 (void *)items->type,
2018 "udp header not found");
2020 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2021 if (!vxlan->vx_flags)
2023 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2025 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2026 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2028 return rte_flow_error_set(error, EINVAL,
2029 RTE_FLOW_ERROR_TYPE_ACTION,
2030 (void *)items->type,
2031 "udp header not found");
2032 if (!vxlan_gpe->proto)
2033 return rte_flow_error_set(error, EINVAL,
2034 RTE_FLOW_ERROR_TYPE_ACTION,
2035 (void *)items->type,
2036 "next protocol not found");
2039 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2040 if (!vxlan_gpe->vx_flags)
2041 vxlan_gpe->vx_flags =
2042 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2044 case RTE_FLOW_ITEM_TYPE_GRE:
2045 case RTE_FLOW_ITEM_TYPE_NVGRE:
2046 gre = (struct rte_gre_hdr *)&buf[temp_size];
2048 return rte_flow_error_set(error, EINVAL,
2049 RTE_FLOW_ERROR_TYPE_ACTION,
2050 (void *)items->type,
2051 "next protocol not found");
2053 return rte_flow_error_set(error, EINVAL,
2054 RTE_FLOW_ERROR_TYPE_ACTION,
2055 (void *)items->type,
2056 "ip header not found");
2057 if (ipv4 && !ipv4->next_proto_id)
2058 ipv4->next_proto_id = IPPROTO_GRE;
2059 else if (ipv6 && !ipv6->proto)
2060 ipv6->proto = IPPROTO_GRE;
2062 case RTE_FLOW_ITEM_TYPE_VOID:
2065 return rte_flow_error_set(error, EINVAL,
2066 RTE_FLOW_ERROR_TYPE_ACTION,
2067 (void *)items->type,
2068 "unsupported item type");
2078 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2080 struct rte_ether_hdr *eth = NULL;
2081 struct rte_vlan_hdr *vlan = NULL;
2082 struct rte_ipv6_hdr *ipv6 = NULL;
2083 struct rte_udp_hdr *udp = NULL;
2087 eth = (struct rte_ether_hdr *)data;
2088 next_hdr = (char *)(eth + 1);
2089 proto = RTE_BE16(eth->ether_type);
2092 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2093 vlan = (struct rte_vlan_hdr *)next_hdr;
2094 proto = RTE_BE16(vlan->eth_proto);
2095 next_hdr += sizeof(struct rte_vlan_hdr);
2098 /* HW calculates IPv4 csum. no need to proceed */
2099 if (proto == RTE_ETHER_TYPE_IPV4)
2102 /* non IPv4/IPv6 header. not supported */
2103 if (proto != RTE_ETHER_TYPE_IPV6) {
2104 return rte_flow_error_set(error, ENOTSUP,
2105 RTE_FLOW_ERROR_TYPE_ACTION,
2106 NULL, "Cannot offload non IPv4/IPv6");
2109 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2111 /* ignore non UDP */
2112 if (ipv6->proto != IPPROTO_UDP)
2115 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2116 udp->dgram_cksum = 0;
2122 * Convert L2 encap action to DV specification.
2125 * Pointer to rte_eth_dev structure.
2127 * Pointer to action structure.
2128 * @param[in, out] dev_flow
2129 * Pointer to the mlx5_flow.
2130 * @param[in] transfer
2131 * Mark if the flow is E-Switch flow.
2133 * Pointer to the error structure.
2136 * 0 on success, a negative errno value otherwise and rte_errno is set.
2139 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2140 const struct rte_flow_action *action,
2141 struct mlx5_flow *dev_flow,
2143 struct rte_flow_error *error)
2145 const struct rte_flow_item *encap_data;
2146 const struct rte_flow_action_raw_encap *raw_encap_data;
2147 struct mlx5_flow_dv_encap_decap_resource res = {
2149 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2150 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2151 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2154 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2156 (const struct rte_flow_action_raw_encap *)action->conf;
2157 res.size = raw_encap_data->size;
2158 memcpy(res.buf, raw_encap_data->data, res.size);
2159 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2162 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2164 ((const struct rte_flow_action_vxlan_encap *)
2165 action->conf)->definition;
2168 ((const struct rte_flow_action_nvgre_encap *)
2169 action->conf)->definition;
2170 if (flow_dv_convert_encap_data(encap_data, res.buf,
2174 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2175 return rte_flow_error_set(error, EINVAL,
2176 RTE_FLOW_ERROR_TYPE_ACTION,
2177 NULL, "can't create L2 encap action");
2182 * Convert L2 decap action to DV specification.
2185 * Pointer to rte_eth_dev structure.
2186 * @param[in, out] dev_flow
2187 * Pointer to the mlx5_flow.
2188 * @param[in] transfer
2189 * Mark if the flow is E-Switch flow.
2191 * Pointer to the error structure.
2194 * 0 on success, a negative errno value otherwise and rte_errno is set.
2197 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2198 struct mlx5_flow *dev_flow,
2200 struct rte_flow_error *error)
2202 struct mlx5_flow_dv_encap_decap_resource res = {
2205 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2206 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2207 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2210 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2211 return rte_flow_error_set(error, EINVAL,
2212 RTE_FLOW_ERROR_TYPE_ACTION,
2213 NULL, "can't create L2 decap action");
2218 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2221 * Pointer to rte_eth_dev structure.
2223 * Pointer to action structure.
2224 * @param[in, out] dev_flow
2225 * Pointer to the mlx5_flow.
2227 * Pointer to the flow attributes.
2229 * Pointer to the error structure.
2232 * 0 on success, a negative errno value otherwise and rte_errno is set.
2235 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2236 const struct rte_flow_action *action,
2237 struct mlx5_flow *dev_flow,
2238 const struct rte_flow_attr *attr,
2239 struct rte_flow_error *error)
2241 const struct rte_flow_action_raw_encap *encap_data;
2242 struct mlx5_flow_dv_encap_decap_resource res;
2244 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2245 res.size = encap_data->size;
2246 memcpy(res.buf, encap_data->data, res.size);
2247 res.reformat_type = attr->egress ?
2248 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2249 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2251 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2253 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2254 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2255 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2256 return rte_flow_error_set(error, EINVAL,
2257 RTE_FLOW_ERROR_TYPE_ACTION,
2258 NULL, "can't create encap action");
2263 * Create action push VLAN.
2266 * Pointer to rte_eth_dev structure.
2267 * @param[in] vlan_tag
2268 * the vlan tag to push to the Ethernet header.
2269 * @param[in, out] dev_flow
2270 * Pointer to the mlx5_flow.
2272 * Pointer to the flow attributes.
2274 * Pointer to the error structure.
2277 * 0 on success, a negative errno value otherwise and rte_errno is set.
2280 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2281 const struct rte_flow_attr *attr,
2282 const struct rte_vlan_hdr *vlan,
2283 struct mlx5_flow *dev_flow,
2284 struct rte_flow_error *error)
2286 struct mlx5_flow_dv_push_vlan_action_resource res;
2289 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2292 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2294 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2295 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2296 return flow_dv_push_vlan_action_resource_register
2297 (dev, &res, dev_flow, error);
2301 * Validate the modify-header actions.
2303 * @param[in] action_flags
2304 * Holds the actions detected until now.
2306 * Pointer to the modify action.
2308 * Pointer to error structure.
2311 * 0 on success, a negative errno value otherwise and rte_errno is set.
2314 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2315 const struct rte_flow_action *action,
2316 struct rte_flow_error *error)
2318 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2319 return rte_flow_error_set(error, EINVAL,
2320 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2321 NULL, "action configuration not set");
2322 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2323 return rte_flow_error_set(error, EINVAL,
2324 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2325 "can't have encap action before"
2331 * Validate the modify-header MAC address actions.
2333 * @param[in] action_flags
2334 * Holds the actions detected until now.
2336 * Pointer to the modify action.
2337 * @param[in] item_flags
2338 * Holds the items detected.
2340 * Pointer to error structure.
2343 * 0 on success, a negative errno value otherwise and rte_errno is set.
2346 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2347 const struct rte_flow_action *action,
2348 const uint64_t item_flags,
2349 struct rte_flow_error *error)
2353 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2355 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2356 return rte_flow_error_set(error, EINVAL,
2357 RTE_FLOW_ERROR_TYPE_ACTION,
2359 "no L2 item in pattern");
2365 * Validate the modify-header IPv4 address actions.
2367 * @param[in] action_flags
2368 * Holds the actions detected until now.
2370 * Pointer to the modify action.
2371 * @param[in] item_flags
2372 * Holds the items detected.
2374 * Pointer to error structure.
2377 * 0 on success, a negative errno value otherwise and rte_errno is set.
2380 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2381 const struct rte_flow_action *action,
2382 const uint64_t item_flags,
2383 struct rte_flow_error *error)
2387 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2389 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2390 return rte_flow_error_set(error, EINVAL,
2391 RTE_FLOW_ERROR_TYPE_ACTION,
2393 "no ipv4 item in pattern");
2399 * Validate the modify-header IPv6 address actions.
2401 * @param[in] action_flags
2402 * Holds the actions detected until now.
2404 * Pointer to the modify action.
2405 * @param[in] item_flags
2406 * Holds the items detected.
2408 * Pointer to error structure.
2411 * 0 on success, a negative errno value otherwise and rte_errno is set.
2414 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2415 const struct rte_flow_action *action,
2416 const uint64_t item_flags,
2417 struct rte_flow_error *error)
2421 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2423 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2424 return rte_flow_error_set(error, EINVAL,
2425 RTE_FLOW_ERROR_TYPE_ACTION,
2427 "no ipv6 item in pattern");
2433 * Validate the modify-header TP actions.
2435 * @param[in] action_flags
2436 * Holds the actions detected until now.
2438 * Pointer to the modify action.
2439 * @param[in] item_flags
2440 * Holds the items detected.
2442 * Pointer to error structure.
2445 * 0 on success, a negative errno value otherwise and rte_errno is set.
2448 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2449 const struct rte_flow_action *action,
2450 const uint64_t item_flags,
2451 struct rte_flow_error *error)
2455 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2457 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2458 return rte_flow_error_set(error, EINVAL,
2459 RTE_FLOW_ERROR_TYPE_ACTION,
2460 NULL, "no transport layer "
2467 * Validate the modify-header actions of increment/decrement
2468 * TCP Sequence-number.
2470 * @param[in] action_flags
2471 * Holds the actions detected until now.
2473 * Pointer to the modify action.
2474 * @param[in] item_flags
2475 * Holds the items detected.
2477 * Pointer to error structure.
2480 * 0 on success, a negative errno value otherwise and rte_errno is set.
2483 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2484 const struct rte_flow_action *action,
2485 const uint64_t item_flags,
2486 struct rte_flow_error *error)
2490 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2492 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2493 return rte_flow_error_set(error, EINVAL,
2494 RTE_FLOW_ERROR_TYPE_ACTION,
2495 NULL, "no TCP item in"
2497 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2498 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2499 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2500 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2501 return rte_flow_error_set(error, EINVAL,
2502 RTE_FLOW_ERROR_TYPE_ACTION,
2504 "cannot decrease and increase"
2505 " TCP sequence number"
2506 " at the same time");
2512 * Validate the modify-header actions of increment/decrement
2513 * TCP Acknowledgment number.
2515 * @param[in] action_flags
2516 * Holds the actions detected until now.
2518 * Pointer to the modify action.
2519 * @param[in] item_flags
2520 * Holds the items detected.
2522 * Pointer to error structure.
2525 * 0 on success, a negative errno value otherwise and rte_errno is set.
2528 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2529 const struct rte_flow_action *action,
2530 const uint64_t item_flags,
2531 struct rte_flow_error *error)
2535 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2537 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2538 return rte_flow_error_set(error, EINVAL,
2539 RTE_FLOW_ERROR_TYPE_ACTION,
2540 NULL, "no TCP item in"
2542 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2543 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2544 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2545 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2546 return rte_flow_error_set(error, EINVAL,
2547 RTE_FLOW_ERROR_TYPE_ACTION,
2549 "cannot decrease and increase"
2550 " TCP acknowledgment number"
2551 " at the same time");
2557 * Validate the modify-header TTL actions.
2559 * @param[in] action_flags
2560 * Holds the actions detected until now.
2562 * Pointer to the modify action.
2563 * @param[in] item_flags
2564 * Holds the items detected.
2566 * Pointer to error structure.
2569 * 0 on success, a negative errno value otherwise and rte_errno is set.
2572 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2573 const struct rte_flow_action *action,
2574 const uint64_t item_flags,
2575 struct rte_flow_error *error)
2579 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2581 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2582 return rte_flow_error_set(error, EINVAL,
2583 RTE_FLOW_ERROR_TYPE_ACTION,
2585 "no IP protocol in pattern");
2591 * Validate jump action.
2594 * Pointer to the jump action.
2595 * @param[in] action_flags
2596 * Holds the actions detected until now.
2597 * @param[in] attributes
2598 * Pointer to flow attributes
2599 * @param[in] external
2600 * Action belongs to flow rule created by request external to PMD.
2602 * Pointer to error structure.
2605 * 0 on success, a negative errno value otherwise and rte_errno is set.
2608 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2609 uint64_t action_flags,
2610 const struct rte_flow_attr *attributes,
2611 bool external, struct rte_flow_error *error)
2613 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2615 uint32_t target_group, table;
2618 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2619 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2620 return rte_flow_error_set(error, EINVAL,
2621 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2622 "can't have 2 fate actions in"
2625 return rte_flow_error_set(error, EINVAL,
2626 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2627 NULL, "action configuration not set");
2629 ((const struct rte_flow_action_jump *)action->conf)->group;
2630 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2634 if (table >= max_group)
2635 return rte_flow_error_set(error, EINVAL,
2636 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2637 "target group index out of range");
2638 if (attributes->group >= target_group)
2639 return rte_flow_error_set(error, EINVAL,
2640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2641 "target group must be higher than"
2642 " the current flow group");
2647 * Validate the port_id action.
2650 * Pointer to rte_eth_dev structure.
2651 * @param[in] action_flags
2652 * Bit-fields that holds the actions detected until now.
2654 * Port_id RTE action structure.
2656 * Attributes of flow that includes this action.
2658 * Pointer to error structure.
2661 * 0 on success, a negative errno value otherwise and rte_errno is set.
2664 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2665 uint64_t action_flags,
2666 const struct rte_flow_action *action,
2667 const struct rte_flow_attr *attr,
2668 struct rte_flow_error *error)
2670 const struct rte_flow_action_port_id *port_id;
2671 struct mlx5_priv *act_priv;
2672 struct mlx5_priv *dev_priv;
2675 if (!attr->transfer)
2676 return rte_flow_error_set(error, ENOTSUP,
2677 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2679 "port id action is valid in transfer"
2681 if (!action || !action->conf)
2682 return rte_flow_error_set(error, ENOTSUP,
2683 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2685 "port id action parameters must be"
2687 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2688 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2689 return rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2691 "can have only one fate actions in"
2693 dev_priv = mlx5_dev_to_eswitch_info(dev);
2695 return rte_flow_error_set(error, rte_errno,
2696 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2698 "failed to obtain E-Switch info");
2699 port_id = action->conf;
2700 port = port_id->original ? dev->data->port_id : port_id->id;
2701 act_priv = mlx5_port_to_eswitch_info(port, false);
2703 return rte_flow_error_set
2705 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2706 "failed to obtain E-Switch port id for port");
2707 if (act_priv->domain_id != dev_priv->domain_id)
2708 return rte_flow_error_set
2710 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2711 "port does not belong to"
2712 " E-Switch being configured");
2717 * Find existing modify-header resource or create and register a new one.
2719 * @param dev[in, out]
2720 * Pointer to rte_eth_dev structure.
2721 * @param[in, out] resource
2722 * Pointer to modify-header resource.
2723 * @parm[in, out] dev_flow
2724 * Pointer to the dev_flow.
2726 * pointer to error structure.
2729 * 0 on success otherwise -errno and errno is set.
2732 flow_dv_modify_hdr_resource_register
2733 (struct rte_eth_dev *dev,
2734 struct mlx5_flow_dv_modify_hdr_resource *resource,
2735 struct mlx5_flow *dev_flow,
2736 struct rte_flow_error *error)
2738 struct mlx5_priv *priv = dev->data->dev_private;
2739 struct mlx5_ibv_shared *sh = priv->sh;
2740 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2741 struct mlx5dv_dr_domain *ns;
2743 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2744 ns = sh->fdb_domain;
2745 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2750 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2751 /* Lookup a matching resource from cache. */
2752 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2753 if (resource->ft_type == cache_resource->ft_type &&
2754 resource->actions_num == cache_resource->actions_num &&
2755 resource->flags == cache_resource->flags &&
2756 !memcmp((const void *)resource->actions,
2757 (const void *)cache_resource->actions,
2758 (resource->actions_num *
2759 sizeof(resource->actions[0])))) {
2760 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2761 (void *)cache_resource,
2762 rte_atomic32_read(&cache_resource->refcnt));
2763 rte_atomic32_inc(&cache_resource->refcnt);
2764 dev_flow->dv.modify_hdr = cache_resource;
2768 /* Register new modify-header resource. */
2769 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2770 if (!cache_resource)
2771 return rte_flow_error_set(error, ENOMEM,
2772 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2773 "cannot allocate resource memory");
2774 *cache_resource = *resource;
2775 cache_resource->verbs_action =
2776 mlx5_glue->dv_create_flow_action_modify_header
2777 (sh->ctx, cache_resource->ft_type,
2778 ns, cache_resource->flags,
2779 cache_resource->actions_num *
2780 sizeof(cache_resource->actions[0]),
2781 (uint64_t *)cache_resource->actions);
2782 if (!cache_resource->verbs_action) {
2783 rte_free(cache_resource);
2784 return rte_flow_error_set(error, ENOMEM,
2785 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2786 NULL, "cannot create action");
2788 rte_atomic32_init(&cache_resource->refcnt);
2789 rte_atomic32_inc(&cache_resource->refcnt);
2790 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2791 dev_flow->dv.modify_hdr = cache_resource;
2792 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2793 (void *)cache_resource,
2794 rte_atomic32_read(&cache_resource->refcnt));
2798 #define MLX5_CNT_CONTAINER_RESIZE 64
2801 * Get or create a flow counter.
2804 * Pointer to the Ethernet device structure.
2806 * Indicate if this counter is shared with other flows.
2808 * Counter identifier.
2811 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2813 static struct mlx5_flow_counter *
2814 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2817 struct mlx5_priv *priv = dev->data->dev_private;
2818 struct mlx5_flow_counter *cnt = NULL;
2819 struct mlx5_devx_obj *dcs = NULL;
2821 if (!priv->config.devx) {
2822 rte_errno = ENOTSUP;
2826 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2827 if (cnt->shared && cnt->id == id) {
2833 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2836 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2838 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2842 struct mlx5_flow_counter tmpl = {
2848 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2850 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2856 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2861 * Release a flow counter.
2864 * Pointer to the Ethernet device structure.
2865 * @param[in] counter
2866 * Pointer to the counter handler.
2869 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2870 struct mlx5_flow_counter *counter)
2872 struct mlx5_priv *priv = dev->data->dev_private;
2876 if (--counter->ref_cnt == 0) {
2877 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2878 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2884 * Query a devx flow counter.
2887 * Pointer to the Ethernet device structure.
2889 * Pointer to the flow counter.
2891 * The statistics value of packets.
2893 * The statistics value of bytes.
2896 * 0 on success, otherwise a negative errno value and rte_errno is set.
2899 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2900 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2903 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2908 * Get a pool by a counter.
2911 * Pointer to the counter.
2916 static struct mlx5_flow_counter_pool *
2917 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2920 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2921 return (struct mlx5_flow_counter_pool *)cnt - 1;
2927 * Get a pool by devx counter ID.
2930 * Pointer to the counter container.
2932 * The counter devx ID.
2935 * The counter pool pointer if exists, NULL otherwise,
2937 static struct mlx5_flow_counter_pool *
2938 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2940 struct mlx5_flow_counter_pool *pool;
2942 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2943 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2944 MLX5_COUNTERS_PER_POOL;
2946 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2953 * Allocate a new memory for the counter values wrapped by all the needed
2957 * Pointer to the Ethernet device structure.
2959 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2962 * The new memory management pointer on success, otherwise NULL and rte_errno
2965 static struct mlx5_counter_stats_mem_mng *
2966 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2968 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2969 (dev->data->dev_private))->sh;
2970 struct mlx5_devx_mkey_attr mkey_attr;
2971 struct mlx5_counter_stats_mem_mng *mem_mng;
2972 volatile struct flow_counter_stats *raw_data;
2973 int size = (sizeof(struct flow_counter_stats) *
2974 MLX5_COUNTERS_PER_POOL +
2975 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2976 sizeof(struct mlx5_counter_stats_mem_mng);
2977 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2984 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2985 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2986 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2987 IBV_ACCESS_LOCAL_WRITE);
2988 if (!mem_mng->umem) {
2993 mkey_attr.addr = (uintptr_t)mem;
2994 mkey_attr.size = size;
2995 mkey_attr.umem_id = mem_mng->umem->umem_id;
2996 mkey_attr.pd = sh->pdn;
2997 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2999 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3004 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3005 raw_data = (volatile struct flow_counter_stats *)mem;
3006 for (i = 0; i < raws_n; ++i) {
3007 mem_mng->raws[i].mem_mng = mem_mng;
3008 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3010 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3015 * Resize a counter container.
3018 * Pointer to the Ethernet device structure.
3020 * Whether the pool is for counter that was allocated by batch command.
3023 * The new container pointer on success, otherwise NULL and rte_errno is set.
3025 static struct mlx5_pools_container *
3026 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3028 struct mlx5_priv *priv = dev->data->dev_private;
3029 struct mlx5_pools_container *cont =
3030 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3031 struct mlx5_pools_container *new_cont =
3032 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3033 struct mlx5_counter_stats_mem_mng *mem_mng;
3034 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3035 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3038 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3039 /* The last resize still hasn't detected by the host thread. */
3043 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3044 if (!new_cont->pools) {
3049 memcpy(new_cont->pools, cont->pools, cont->n *
3050 sizeof(struct mlx5_flow_counter_pool *));
3051 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3052 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3054 rte_free(new_cont->pools);
3057 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3058 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3059 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3061 new_cont->n = resize;
3062 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3063 TAILQ_INIT(&new_cont->pool_list);
3064 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3065 new_cont->init_mem_mng = mem_mng;
3067 /* Flip the master container. */
3068 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3073 * Query a devx flow counter.
3076 * Pointer to the Ethernet device structure.
3078 * Pointer to the flow counter.
3080 * The statistics value of packets.
3082 * The statistics value of bytes.
3085 * 0 on success, otherwise a negative errno value and rte_errno is set.
3088 _flow_dv_query_count(struct rte_eth_dev *dev,
3089 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3092 struct mlx5_priv *priv = dev->data->dev_private;
3093 struct mlx5_flow_counter_pool *pool =
3094 flow_dv_counter_pool_get(cnt);
3095 int offset = cnt - &pool->counters_raw[0];
3097 if (priv->counter_fallback)
3098 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3100 rte_spinlock_lock(&pool->sl);
3102 * The single counters allocation may allocate smaller ID than the
3103 * current allocated in parallel to the host reading.
3104 * In this case the new counter values must be reported as 0.
3106 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3110 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3111 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3113 rte_spinlock_unlock(&pool->sl);
3118 * Create and initialize a new counter pool.
3121 * Pointer to the Ethernet device structure.
3123 * The devX counter handle.
3125 * Whether the pool is for counter that was allocated by batch command.
3128 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3130 static struct mlx5_flow_counter_pool *
3131 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3134 struct mlx5_priv *priv = dev->data->dev_private;
3135 struct mlx5_flow_counter_pool *pool;
3136 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3138 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3141 if (cont->n == n_valid) {
3142 cont = flow_dv_container_resize(dev, batch);
3146 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3147 sizeof(struct mlx5_flow_counter);
3148 pool = rte_calloc(__func__, 1, size, 0);
3153 pool->min_dcs = dcs;
3154 pool->raw = cont->init_mem_mng->raws + n_valid %
3155 MLX5_CNT_CONTAINER_RESIZE;
3156 pool->raw_hw = NULL;
3157 rte_spinlock_init(&pool->sl);
3159 * The generation of the new allocated counters in this pool is 0, 2 in
3160 * the pool generation makes all the counters valid for allocation.
3162 rte_atomic64_set(&pool->query_gen, 0x2);
3163 TAILQ_INIT(&pool->counters);
3164 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3165 cont->pools[n_valid] = pool;
3166 /* Pool initialization must be updated before host thread access. */
3168 rte_atomic16_add(&cont->n_valid, 1);
3173 * Prepare a new counter and/or a new counter pool.
3176 * Pointer to the Ethernet device structure.
3177 * @param[out] cnt_free
3178 * Where to put the pointer of a new counter.
3180 * Whether the pool is for counter that was allocated by batch command.
3183 * The free counter pool pointer and @p cnt_free is set on success,
3184 * NULL otherwise and rte_errno is set.
3186 static struct mlx5_flow_counter_pool *
3187 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3188 struct mlx5_flow_counter **cnt_free,
3191 struct mlx5_priv *priv = dev->data->dev_private;
3192 struct mlx5_flow_counter_pool *pool;
3193 struct mlx5_devx_obj *dcs = NULL;
3194 struct mlx5_flow_counter *cnt;
3198 /* bulk_bitmap must be 0 for single counter allocation. */
3199 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3202 pool = flow_dv_find_pool_by_id
3203 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3205 pool = flow_dv_pool_create(dev, dcs, batch);
3207 mlx5_devx_cmd_destroy(dcs);
3210 } else if (dcs->id < pool->min_dcs->id) {
3211 rte_atomic64_set(&pool->a64_dcs,
3212 (int64_t)(uintptr_t)dcs);
3214 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3215 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3220 /* bulk_bitmap is in 128 counters units. */
3221 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3222 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3224 rte_errno = ENODATA;
3227 pool = flow_dv_pool_create(dev, dcs, batch);
3229 mlx5_devx_cmd_destroy(dcs);
3232 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3233 cnt = &pool->counters_raw[i];
3235 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3237 *cnt_free = &pool->counters_raw[0];
3242 * Search for existed shared counter.
3245 * Pointer to the relevant counter pool container.
3247 * The shared counter ID to search.
3250 * NULL if not existed, otherwise pointer to the shared counter.
3252 static struct mlx5_flow_counter *
3253 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3256 static struct mlx5_flow_counter *cnt;
3257 struct mlx5_flow_counter_pool *pool;
3260 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3261 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3262 cnt = &pool->counters_raw[i];
3263 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3271 * Allocate a flow counter.
3274 * Pointer to the Ethernet device structure.
3276 * Indicate if this counter is shared with other flows.
3278 * Counter identifier.
3280 * Counter flow group.
3283 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3285 static struct mlx5_flow_counter *
3286 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3289 struct mlx5_priv *priv = dev->data->dev_private;
3290 struct mlx5_flow_counter_pool *pool = NULL;
3291 struct mlx5_flow_counter *cnt_free = NULL;
3293 * Currently group 0 flow counter cannot be assigned to a flow if it is
3294 * not the first one in the batch counter allocation, so it is better
3295 * to allocate counters one by one for these flows in a separate
3297 * A counter can be shared between different groups so need to take
3298 * shared counters from the single container.
3300 uint32_t batch = (group && !shared) ? 1 : 0;
3301 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3304 if (priv->counter_fallback)
3305 return flow_dv_counter_alloc_fallback(dev, shared, id);
3306 if (!priv->config.devx) {
3307 rte_errno = ENOTSUP;
3311 cnt_free = flow_dv_counter_shared_search(cont, id);
3313 if (cnt_free->ref_cnt + 1 == 0) {
3317 cnt_free->ref_cnt++;
3321 /* Pools which has a free counters are in the start. */
3322 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3324 * The free counter reset values must be updated between the
3325 * counter release to the counter allocation, so, at least one
3326 * query must be done in this time. ensure it by saving the
3327 * query generation in the release time.
3328 * The free list is sorted according to the generation - so if
3329 * the first one is not updated, all the others are not
3332 cnt_free = TAILQ_FIRST(&pool->counters);
3333 if (cnt_free && cnt_free->query_gen + 1 <
3334 rte_atomic64_read(&pool->query_gen))
3339 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3343 cnt_free->batch = batch;
3344 /* Create a DV counter action only in the first time usage. */
3345 if (!cnt_free->action) {
3347 struct mlx5_devx_obj *dcs;
3350 offset = cnt_free - &pool->counters_raw[0];
3351 dcs = pool->min_dcs;
3354 dcs = cnt_free->dcs;
3356 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3358 if (!cnt_free->action) {
3363 /* Update the counter reset values. */
3364 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3367 cnt_free->shared = shared;
3368 cnt_free->ref_cnt = 1;
3370 if (!priv->sh->cmng.query_thread_on)
3371 /* Start the asynchronous batch query by the host thread. */
3372 mlx5_set_query_alarm(priv->sh);
3373 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3374 if (TAILQ_EMPTY(&pool->counters)) {
3375 /* Move the pool to the end of the container pool list. */
3376 TAILQ_REMOVE(&cont->pool_list, pool, next);
3377 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3383 * Release a flow counter.
3386 * Pointer to the Ethernet device structure.
3387 * @param[in] counter
3388 * Pointer to the counter handler.
3391 flow_dv_counter_release(struct rte_eth_dev *dev,
3392 struct mlx5_flow_counter *counter)
3394 struct mlx5_priv *priv = dev->data->dev_private;
3398 if (priv->counter_fallback) {
3399 flow_dv_counter_release_fallback(dev, counter);
3402 if (--counter->ref_cnt == 0) {
3403 struct mlx5_flow_counter_pool *pool =
3404 flow_dv_counter_pool_get(counter);
3406 /* Put the counter in the end - the last updated one. */
3407 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3408 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3413 * Verify the @p attributes will be correctly understood by the NIC and store
3414 * them in the @p flow if everything is correct.
3417 * Pointer to dev struct.
3418 * @param[in] attributes
3419 * Pointer to flow attributes
3420 * @param[in] external
3421 * This flow rule is created by request external to PMD.
3423 * Pointer to error structure.
3426 * 0 on success, a negative errno value otherwise and rte_errno is set.
3429 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3430 const struct rte_flow_attr *attributes,
3431 bool external __rte_unused,
3432 struct rte_flow_error *error)
3434 struct mlx5_priv *priv = dev->data->dev_private;
3435 uint32_t priority_max = priv->config.flow_prio - 1;
3437 #ifndef HAVE_MLX5DV_DR
3438 if (attributes->group)
3439 return rte_flow_error_set(error, ENOTSUP,
3440 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3442 "groups are not supported");
3444 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3449 ret = mlx5_flow_group_to_table(attributes, external,
3454 if (table >= max_group)
3455 return rte_flow_error_set(error, EINVAL,
3456 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3457 "group index out of range");
3459 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3460 attributes->priority >= priority_max)
3461 return rte_flow_error_set(error, ENOTSUP,
3462 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3464 "priority out of range");
3465 if (attributes->transfer) {
3466 if (!priv->config.dv_esw_en)
3467 return rte_flow_error_set
3469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3470 "E-Switch dr is not supported");
3471 if (!(priv->representor || priv->master))
3472 return rte_flow_error_set
3473 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3474 NULL, "E-Switch configuration can only be"
3475 " done by a master or a representor device");
3476 if (attributes->egress)
3477 return rte_flow_error_set
3479 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3480 "egress is not supported");
3482 if (!(attributes->egress ^ attributes->ingress))
3483 return rte_flow_error_set(error, ENOTSUP,
3484 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3485 "must specify exactly one of "
3486 "ingress or egress");
3491 * Internal validation function. For validating both actions and items.
3494 * Pointer to the rte_eth_dev structure.
3496 * Pointer to the flow attributes.
3498 * Pointer to the list of items.
3499 * @param[in] actions
3500 * Pointer to the list of actions.
3501 * @param[in] external
3502 * This flow rule is created by request external to PMD.
3504 * Pointer to the error structure.
3507 * 0 on success, a negative errno value otherwise and rte_errno is set.
3510 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3511 const struct rte_flow_item items[],
3512 const struct rte_flow_action actions[],
3513 bool external, struct rte_flow_error *error)
3516 uint64_t action_flags = 0;
3517 uint64_t item_flags = 0;
3518 uint64_t last_item = 0;
3519 uint8_t next_protocol = 0xff;
3520 uint16_t ether_type = 0;
3522 const struct rte_flow_item *gre_item = NULL;
3523 struct rte_flow_item_tcp nic_tcp_mask = {
3526 .src_port = RTE_BE16(UINT16_MAX),
3527 .dst_port = RTE_BE16(UINT16_MAX),
3533 ret = flow_dv_validate_attributes(dev, attr, external, error);
3536 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3537 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3538 int type = items->type;
3541 case RTE_FLOW_ITEM_TYPE_VOID:
3543 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3544 ret = flow_dv_validate_item_port_id
3545 (dev, items, attr, item_flags, error);
3548 last_item = MLX5_FLOW_ITEM_PORT_ID;
3550 case RTE_FLOW_ITEM_TYPE_ETH:
3551 ret = mlx5_flow_validate_item_eth(items, item_flags,
3555 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3556 MLX5_FLOW_LAYER_OUTER_L2;
3557 if (items->mask != NULL && items->spec != NULL) {
3559 ((const struct rte_flow_item_eth *)
3562 ((const struct rte_flow_item_eth *)
3564 ether_type = rte_be_to_cpu_16(ether_type);
3569 case RTE_FLOW_ITEM_TYPE_VLAN:
3570 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3574 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3575 MLX5_FLOW_LAYER_OUTER_VLAN;
3576 if (items->mask != NULL && items->spec != NULL) {
3578 ((const struct rte_flow_item_vlan *)
3579 items->spec)->inner_type;
3581 ((const struct rte_flow_item_vlan *)
3582 items->mask)->inner_type;
3583 ether_type = rte_be_to_cpu_16(ether_type);
3588 case RTE_FLOW_ITEM_TYPE_IPV4:
3589 mlx5_flow_tunnel_ip_check(items, next_protocol,
3590 &item_flags, &tunnel);
3591 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3597 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3598 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3599 if (items->mask != NULL &&
3600 ((const struct rte_flow_item_ipv4 *)
3601 items->mask)->hdr.next_proto_id) {
3603 ((const struct rte_flow_item_ipv4 *)
3604 (items->spec))->hdr.next_proto_id;
3606 ((const struct rte_flow_item_ipv4 *)
3607 (items->mask))->hdr.next_proto_id;
3609 /* Reset for inner layer. */
3610 next_protocol = 0xff;
3613 case RTE_FLOW_ITEM_TYPE_IPV6:
3614 mlx5_flow_tunnel_ip_check(items, next_protocol,
3615 &item_flags, &tunnel);
3616 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3622 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3623 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3624 if (items->mask != NULL &&
3625 ((const struct rte_flow_item_ipv6 *)
3626 items->mask)->hdr.proto) {
3628 ((const struct rte_flow_item_ipv6 *)
3629 items->spec)->hdr.proto;
3631 ((const struct rte_flow_item_ipv6 *)
3632 items->mask)->hdr.proto;
3634 /* Reset for inner layer. */
3635 next_protocol = 0xff;
3638 case RTE_FLOW_ITEM_TYPE_TCP:
3639 ret = mlx5_flow_validate_item_tcp
3646 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3647 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3649 case RTE_FLOW_ITEM_TYPE_UDP:
3650 ret = mlx5_flow_validate_item_udp(items, item_flags,
3655 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3656 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3658 case RTE_FLOW_ITEM_TYPE_GRE:
3659 ret = mlx5_flow_validate_item_gre(items, item_flags,
3660 next_protocol, error);
3664 last_item = MLX5_FLOW_LAYER_GRE;
3666 case RTE_FLOW_ITEM_TYPE_NVGRE:
3667 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3672 last_item = MLX5_FLOW_LAYER_NVGRE;
3674 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3675 ret = mlx5_flow_validate_item_gre_key
3676 (items, item_flags, gre_item, error);
3679 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3681 case RTE_FLOW_ITEM_TYPE_VXLAN:
3682 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3686 last_item = MLX5_FLOW_LAYER_VXLAN;
3688 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3689 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3694 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3696 case RTE_FLOW_ITEM_TYPE_GENEVE:
3697 ret = mlx5_flow_validate_item_geneve(items,
3702 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3704 case RTE_FLOW_ITEM_TYPE_MPLS:
3705 ret = mlx5_flow_validate_item_mpls(dev, items,
3710 last_item = MLX5_FLOW_LAYER_MPLS;
3712 case RTE_FLOW_ITEM_TYPE_META:
3713 ret = flow_dv_validate_item_meta(dev, items, attr,
3717 last_item = MLX5_FLOW_ITEM_METADATA;
3719 case RTE_FLOW_ITEM_TYPE_ICMP:
3720 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3725 last_item = MLX5_FLOW_LAYER_ICMP;
3727 case RTE_FLOW_ITEM_TYPE_ICMP6:
3728 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3733 last_item = MLX5_FLOW_LAYER_ICMP6;
3735 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3736 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3739 return rte_flow_error_set(error, ENOTSUP,
3740 RTE_FLOW_ERROR_TYPE_ITEM,
3741 NULL, "item not supported");
3743 item_flags |= last_item;
3745 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3746 int type = actions->type;
3747 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3748 return rte_flow_error_set(error, ENOTSUP,
3749 RTE_FLOW_ERROR_TYPE_ACTION,
3750 actions, "too many actions");
3752 case RTE_FLOW_ACTION_TYPE_VOID:
3754 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3755 ret = flow_dv_validate_action_port_id(dev,
3762 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3765 case RTE_FLOW_ACTION_TYPE_FLAG:
3766 ret = mlx5_flow_validate_action_flag(action_flags,
3770 action_flags |= MLX5_FLOW_ACTION_FLAG;
3773 case RTE_FLOW_ACTION_TYPE_MARK:
3774 ret = mlx5_flow_validate_action_mark(actions,
3779 action_flags |= MLX5_FLOW_ACTION_MARK;
3782 case RTE_FLOW_ACTION_TYPE_DROP:
3783 ret = mlx5_flow_validate_action_drop(action_flags,
3787 action_flags |= MLX5_FLOW_ACTION_DROP;
3790 case RTE_FLOW_ACTION_TYPE_QUEUE:
3791 ret = mlx5_flow_validate_action_queue(actions,
3796 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3799 case RTE_FLOW_ACTION_TYPE_RSS:
3800 ret = mlx5_flow_validate_action_rss(actions,
3806 action_flags |= MLX5_FLOW_ACTION_RSS;
3809 case RTE_FLOW_ACTION_TYPE_COUNT:
3810 ret = flow_dv_validate_action_count(dev, error);
3813 action_flags |= MLX5_FLOW_ACTION_COUNT;
3816 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3817 if (flow_dv_validate_action_pop_vlan(dev,
3823 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3826 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3827 ret = flow_dv_validate_action_push_vlan(action_flags,
3833 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3836 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3837 ret = flow_dv_validate_action_set_vlan_pcp
3838 (action_flags, actions, error);
3841 /* Count PCP with push_vlan command. */
3842 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3844 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3845 ret = flow_dv_validate_action_set_vlan_vid
3846 (item_flags, action_flags,
3850 /* Count VID with push_vlan command. */
3851 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3853 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3854 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3855 ret = flow_dv_validate_action_l2_encap(action_flags,
3860 action_flags |= actions->type ==
3861 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3862 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3863 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3866 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3867 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3868 ret = flow_dv_validate_action_l2_decap(action_flags,
3872 action_flags |= actions->type ==
3873 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3874 MLX5_FLOW_ACTION_VXLAN_DECAP :
3875 MLX5_FLOW_ACTION_NVGRE_DECAP;
3878 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3879 ret = flow_dv_validate_action_raw_encap(action_flags,
3884 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3887 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3888 ret = flow_dv_validate_action_raw_decap(action_flags,
3893 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3896 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3897 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3898 ret = flow_dv_validate_action_modify_mac(action_flags,
3904 /* Count all modify-header actions as one action. */
3905 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3907 action_flags |= actions->type ==
3908 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3909 MLX5_FLOW_ACTION_SET_MAC_SRC :
3910 MLX5_FLOW_ACTION_SET_MAC_DST;
3913 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3914 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3915 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3921 /* Count all modify-header actions as one action. */
3922 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3924 action_flags |= actions->type ==
3925 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3926 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3927 MLX5_FLOW_ACTION_SET_IPV4_DST;
3929 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3930 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3931 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3937 /* Count all modify-header actions as one action. */
3938 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3940 action_flags |= actions->type ==
3941 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3942 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3943 MLX5_FLOW_ACTION_SET_IPV6_DST;
3945 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3946 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3947 ret = flow_dv_validate_action_modify_tp(action_flags,
3953 /* Count all modify-header actions as one action. */
3954 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3956 action_flags |= actions->type ==
3957 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3958 MLX5_FLOW_ACTION_SET_TP_SRC :
3959 MLX5_FLOW_ACTION_SET_TP_DST;
3961 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3962 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3963 ret = flow_dv_validate_action_modify_ttl(action_flags,
3969 /* Count all modify-header actions as one action. */
3970 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3972 action_flags |= actions->type ==
3973 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3974 MLX5_FLOW_ACTION_SET_TTL :
3975 MLX5_FLOW_ACTION_DEC_TTL;
3977 case RTE_FLOW_ACTION_TYPE_JUMP:
3978 ret = flow_dv_validate_action_jump(actions,
3985 action_flags |= MLX5_FLOW_ACTION_JUMP;
3987 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3988 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3989 ret = flow_dv_validate_action_modify_tcp_seq
3996 /* Count all modify-header actions as one action. */
3997 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3999 action_flags |= actions->type ==
4000 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4001 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4002 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4004 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4005 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4006 ret = flow_dv_validate_action_modify_tcp_ack
4013 /* Count all modify-header actions as one action. */
4014 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4016 action_flags |= actions->type ==
4017 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4018 MLX5_FLOW_ACTION_INC_TCP_ACK :
4019 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4021 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4022 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4025 return rte_flow_error_set(error, ENOTSUP,
4026 RTE_FLOW_ERROR_TYPE_ACTION,
4028 "action not supported");
4031 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4032 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4033 return rte_flow_error_set(error, ENOTSUP,
4034 RTE_FLOW_ERROR_TYPE_ACTION,
4036 "can't have vxlan and vlan"
4037 " actions in the same rule");
4038 /* Eswitch has few restrictions on using items and actions */
4039 if (attr->transfer) {
4040 if (action_flags & MLX5_FLOW_ACTION_FLAG)
4041 return rte_flow_error_set(error, ENOTSUP,
4042 RTE_FLOW_ERROR_TYPE_ACTION,
4044 "unsupported action FLAG");
4045 if (action_flags & MLX5_FLOW_ACTION_MARK)
4046 return rte_flow_error_set(error, ENOTSUP,
4047 RTE_FLOW_ERROR_TYPE_ACTION,
4049 "unsupported action MARK");
4050 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4051 return rte_flow_error_set(error, ENOTSUP,
4052 RTE_FLOW_ERROR_TYPE_ACTION,
4054 "unsupported action QUEUE");
4055 if (action_flags & MLX5_FLOW_ACTION_RSS)
4056 return rte_flow_error_set(error, ENOTSUP,
4057 RTE_FLOW_ERROR_TYPE_ACTION,
4059 "unsupported action RSS");
4060 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4061 return rte_flow_error_set(error, EINVAL,
4062 RTE_FLOW_ERROR_TYPE_ACTION,
4064 "no fate action is found");
4066 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4067 return rte_flow_error_set(error, EINVAL,
4068 RTE_FLOW_ERROR_TYPE_ACTION,
4070 "no fate action is found");
4076 * Internal preparation function. Allocates the DV flow size,
4077 * this size is constant.
4080 * Pointer to the flow attributes.
4082 * Pointer to the list of items.
4083 * @param[in] actions
4084 * Pointer to the list of actions.
4086 * Pointer to the error structure.
4089 * Pointer to mlx5_flow object on success,
4090 * otherwise NULL and rte_errno is set.
4092 static struct mlx5_flow *
4093 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4094 const struct rte_flow_item items[] __rte_unused,
4095 const struct rte_flow_action actions[] __rte_unused,
4096 struct rte_flow_error *error)
4098 size_t size = sizeof(struct mlx5_flow);
4099 struct mlx5_flow *dev_flow;
4101 dev_flow = rte_calloc(__func__, 1, size, 0);
4103 rte_flow_error_set(error, ENOMEM,
4104 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4105 "not enough memory to create flow");
4108 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4109 dev_flow->ingress = attr->ingress;
4110 dev_flow->transfer = attr->transfer;
4116 * Sanity check for match mask and value. Similar to check_valid_spec() in
4117 * kernel driver. If unmasked bit is present in value, it returns failure.
4120 * pointer to match mask buffer.
4121 * @param match_value
4122 * pointer to match value buffer.
4125 * 0 if valid, -EINVAL otherwise.
4128 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4130 uint8_t *m = match_mask;
4131 uint8_t *v = match_value;
4134 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4137 "match_value differs from match_criteria"
4138 " %p[%u] != %p[%u]",
4139 match_value, i, match_mask, i);
4148 * Add Ethernet item to matcher and to the value.
4150 * @param[in, out] matcher
4152 * @param[in, out] key
4153 * Flow matcher value.
4155 * Flow pattern to translate.
4157 * Item is inner pattern.
4160 flow_dv_translate_item_eth(void *matcher, void *key,
4161 const struct rte_flow_item *item, int inner)
4163 const struct rte_flow_item_eth *eth_m = item->mask;
4164 const struct rte_flow_item_eth *eth_v = item->spec;
4165 const struct rte_flow_item_eth nic_mask = {
4166 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4167 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4168 .type = RTE_BE16(0xffff),
4180 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4182 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4184 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4186 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4188 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4189 ð_m->dst, sizeof(eth_m->dst));
4190 /* The value must be in the range of the mask. */
4191 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4192 for (i = 0; i < sizeof(eth_m->dst); ++i)
4193 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4194 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4195 ð_m->src, sizeof(eth_m->src));
4196 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4197 /* The value must be in the range of the mask. */
4198 for (i = 0; i < sizeof(eth_m->dst); ++i)
4199 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4200 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4201 rte_be_to_cpu_16(eth_m->type));
4202 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4203 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4207 * Add VLAN item to matcher and to the value.
4209 * @param[in, out] dev_flow
4211 * @param[in, out] matcher
4213 * @param[in, out] key
4214 * Flow matcher value.
4216 * Flow pattern to translate.
4218 * Item is inner pattern.
4221 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4222 void *matcher, void *key,
4223 const struct rte_flow_item *item,
4226 const struct rte_flow_item_vlan *vlan_m = item->mask;
4227 const struct rte_flow_item_vlan *vlan_v = item->spec;
4236 vlan_m = &rte_flow_item_vlan_mask;
4238 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4240 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4242 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4244 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4246 * This is workaround, masks are not supported,
4247 * and pre-validated.
4249 dev_flow->dv.vf_vlan.tag =
4250 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4252 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4253 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4254 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4255 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4256 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4257 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4258 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4259 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4260 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4261 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4262 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4263 rte_be_to_cpu_16(vlan_m->inner_type));
4264 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4265 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4269 * Add IPV4 item to matcher and to the value.
4271 * @param[in, out] matcher
4273 * @param[in, out] key
4274 * Flow matcher value.
4276 * Flow pattern to translate.
4278 * Item is inner pattern.
4280 * The group to insert the rule.
4283 flow_dv_translate_item_ipv4(void *matcher, void *key,
4284 const struct rte_flow_item *item,
4285 int inner, uint32_t group)
4287 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4288 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4289 const struct rte_flow_item_ipv4 nic_mask = {
4291 .src_addr = RTE_BE32(0xffffffff),
4292 .dst_addr = RTE_BE32(0xffffffff),
4293 .type_of_service = 0xff,
4294 .next_proto_id = 0xff,
4304 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4306 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4308 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4310 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4313 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4315 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4316 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4321 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4322 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4323 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4324 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4325 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4326 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4327 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4328 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4329 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4330 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4331 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4332 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4333 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4334 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4335 ipv4_m->hdr.type_of_service);
4336 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4337 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4338 ipv4_m->hdr.type_of_service >> 2);
4339 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4340 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4341 ipv4_m->hdr.next_proto_id);
4342 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4343 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4347 * Add IPV6 item to matcher and to the value.
4349 * @param[in, out] matcher
4351 * @param[in, out] key
4352 * Flow matcher value.
4354 * Flow pattern to translate.
4356 * Item is inner pattern.
4358 * The group to insert the rule.
4361 flow_dv_translate_item_ipv6(void *matcher, void *key,
4362 const struct rte_flow_item *item,
4363 int inner, uint32_t group)
4365 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4366 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4367 const struct rte_flow_item_ipv6 nic_mask = {
4370 "\xff\xff\xff\xff\xff\xff\xff\xff"
4371 "\xff\xff\xff\xff\xff\xff\xff\xff",
4373 "\xff\xff\xff\xff\xff\xff\xff\xff"
4374 "\xff\xff\xff\xff\xff\xff\xff\xff",
4375 .vtc_flow = RTE_BE32(0xffffffff),
4382 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4383 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4392 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4394 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4396 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4398 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4401 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4403 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4404 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4409 size = sizeof(ipv6_m->hdr.dst_addr);
4410 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4411 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4412 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4413 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4414 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4415 for (i = 0; i < size; ++i)
4416 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4417 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4418 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4419 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4420 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4421 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4422 for (i = 0; i < size; ++i)
4423 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4425 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4426 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4427 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4428 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4429 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4433 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4435 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4438 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4440 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4444 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4446 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4447 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4451 * Add TCP item to matcher and to the value.
4453 * @param[in, out] matcher
4455 * @param[in, out] key
4456 * Flow matcher value.
4458 * Flow pattern to translate.
4460 * Item is inner pattern.
4463 flow_dv_translate_item_tcp(void *matcher, void *key,
4464 const struct rte_flow_item *item,
4467 const struct rte_flow_item_tcp *tcp_m = item->mask;
4468 const struct rte_flow_item_tcp *tcp_v = item->spec;
4473 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4475 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4477 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4479 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4481 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4482 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4486 tcp_m = &rte_flow_item_tcp_mask;
4487 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4488 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4490 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4491 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4492 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4494 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4495 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4496 tcp_m->hdr.tcp_flags);
4497 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4498 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4502 * Add UDP item to matcher and to the value.
4504 * @param[in, out] matcher
4506 * @param[in, out] key
4507 * Flow matcher value.
4509 * Flow pattern to translate.
4511 * Item is inner pattern.
4514 flow_dv_translate_item_udp(void *matcher, void *key,
4515 const struct rte_flow_item *item,
4518 const struct rte_flow_item_udp *udp_m = item->mask;
4519 const struct rte_flow_item_udp *udp_v = item->spec;
4524 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4526 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4528 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4530 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4532 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4533 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4537 udp_m = &rte_flow_item_udp_mask;
4538 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4539 rte_be_to_cpu_16(udp_m->hdr.src_port));
4540 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4541 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4542 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4543 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4544 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4545 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4549 * Add GRE optional Key item to matcher and to the value.
4551 * @param[in, out] matcher
4553 * @param[in, out] key
4554 * Flow matcher value.
4556 * Flow pattern to translate.
4558 * Item is inner pattern.
4561 flow_dv_translate_item_gre_key(void *matcher, void *key,
4562 const struct rte_flow_item *item)
4564 const rte_be32_t *key_m = item->mask;
4565 const rte_be32_t *key_v = item->spec;
4566 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4567 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4568 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4573 key_m = &gre_key_default_mask;
4574 /* GRE K bit must be on and should already be validated */
4575 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4576 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4577 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4578 rte_be_to_cpu_32(*key_m) >> 8);
4579 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4580 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4581 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4582 rte_be_to_cpu_32(*key_m) & 0xFF);
4583 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4584 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4588 * Add GRE item to matcher and to the value.
4590 * @param[in, out] matcher
4592 * @param[in, out] key
4593 * Flow matcher value.
4595 * Flow pattern to translate.
4597 * Item is inner pattern.
4600 flow_dv_translate_item_gre(void *matcher, void *key,
4601 const struct rte_flow_item *item,
4604 const struct rte_flow_item_gre *gre_m = item->mask;
4605 const struct rte_flow_item_gre *gre_v = item->spec;
4608 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4609 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4616 uint16_t s_present:1;
4617 uint16_t k_present:1;
4618 uint16_t rsvd_bit1:1;
4619 uint16_t c_present:1;
4623 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4626 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4628 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4630 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4632 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4634 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4635 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4639 gre_m = &rte_flow_item_gre_mask;
4640 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4641 rte_be_to_cpu_16(gre_m->protocol));
4642 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4643 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4644 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4645 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4646 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4647 gre_crks_rsvd0_ver_m.c_present);
4648 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4649 gre_crks_rsvd0_ver_v.c_present &
4650 gre_crks_rsvd0_ver_m.c_present);
4651 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4652 gre_crks_rsvd0_ver_m.k_present);
4653 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4654 gre_crks_rsvd0_ver_v.k_present &
4655 gre_crks_rsvd0_ver_m.k_present);
4656 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4657 gre_crks_rsvd0_ver_m.s_present);
4658 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4659 gre_crks_rsvd0_ver_v.s_present &
4660 gre_crks_rsvd0_ver_m.s_present);
4664 * Add NVGRE item to matcher and to the value.
4666 * @param[in, out] matcher
4668 * @param[in, out] key
4669 * Flow matcher value.
4671 * Flow pattern to translate.
4673 * Item is inner pattern.
4676 flow_dv_translate_item_nvgre(void *matcher, void *key,
4677 const struct rte_flow_item *item,
4680 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4681 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4682 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4683 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4684 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4685 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4691 /* For NVGRE, GRE header fields must be set with defined values. */
4692 const struct rte_flow_item_gre gre_spec = {
4693 .c_rsvd0_ver = RTE_BE16(0x2000),
4694 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4696 const struct rte_flow_item_gre gre_mask = {
4697 .c_rsvd0_ver = RTE_BE16(0xB000),
4698 .protocol = RTE_BE16(UINT16_MAX),
4700 const struct rte_flow_item gre_item = {
4705 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4709 nvgre_m = &rte_flow_item_nvgre_mask;
4710 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4711 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4712 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4713 memcpy(gre_key_m, tni_flow_id_m, size);
4714 for (i = 0; i < size; ++i)
4715 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4719 * Add VXLAN item to matcher and to the value.
4721 * @param[in, out] matcher
4723 * @param[in, out] key
4724 * Flow matcher value.
4726 * Flow pattern to translate.
4728 * Item is inner pattern.
4731 flow_dv_translate_item_vxlan(void *matcher, void *key,
4732 const struct rte_flow_item *item,
4735 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4736 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4739 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4740 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4748 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4750 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4752 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4754 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4756 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4757 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4758 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4759 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4760 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4765 vxlan_m = &rte_flow_item_vxlan_mask;
4766 size = sizeof(vxlan_m->vni);
4767 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4768 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4769 memcpy(vni_m, vxlan_m->vni, size);
4770 for (i = 0; i < size; ++i)
4771 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4775 * Add Geneve item to matcher and to the value.
4777 * @param[in, out] matcher
4779 * @param[in, out] key
4780 * Flow matcher value.
4782 * Flow pattern to translate.
4784 * Item is inner pattern.
4788 flow_dv_translate_item_geneve(void *matcher, void *key,
4789 const struct rte_flow_item *item, int inner)
4791 const struct rte_flow_item_geneve *geneve_m = item->mask;
4792 const struct rte_flow_item_geneve *geneve_v = item->spec;
4795 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4796 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4805 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4807 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4809 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4811 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4813 dport = MLX5_UDP_PORT_GENEVE;
4814 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4815 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4816 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4821 geneve_m = &rte_flow_item_geneve_mask;
4822 size = sizeof(geneve_m->vni);
4823 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4824 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4825 memcpy(vni_m, geneve_m->vni, size);
4826 for (i = 0; i < size; ++i)
4827 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4828 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4829 rte_be_to_cpu_16(geneve_m->protocol));
4830 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4831 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4832 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4833 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4834 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4835 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4836 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4837 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4838 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4839 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4840 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4841 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4842 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4846 * Add MPLS item to matcher and to the value.
4848 * @param[in, out] matcher
4850 * @param[in, out] key
4851 * Flow matcher value.
4853 * Flow pattern to translate.
4854 * @param[in] prev_layer
4855 * The protocol layer indicated in previous item.
4857 * Item is inner pattern.
4860 flow_dv_translate_item_mpls(void *matcher, void *key,
4861 const struct rte_flow_item *item,
4862 uint64_t prev_layer,
4865 const uint32_t *in_mpls_m = item->mask;
4866 const uint32_t *in_mpls_v = item->spec;
4867 uint32_t *out_mpls_m = 0;
4868 uint32_t *out_mpls_v = 0;
4869 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4870 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4871 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4873 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4874 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4875 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4877 switch (prev_layer) {
4878 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4879 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4880 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4881 MLX5_UDP_PORT_MPLS);
4883 case MLX5_FLOW_LAYER_GRE:
4884 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4885 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4886 RTE_ETHER_TYPE_MPLS);
4889 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4890 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4897 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4898 switch (prev_layer) {
4899 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4901 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4902 outer_first_mpls_over_udp);
4904 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4905 outer_first_mpls_over_udp);
4907 case MLX5_FLOW_LAYER_GRE:
4909 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4910 outer_first_mpls_over_gre);
4912 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4913 outer_first_mpls_over_gre);
4916 /* Inner MPLS not over GRE is not supported. */
4919 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4923 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4929 if (out_mpls_m && out_mpls_v) {
4930 *out_mpls_m = *in_mpls_m;
4931 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4936 * Add metadata register item to matcher
4938 * @param[in, out] matcher
4940 * @param[in, out] key
4941 * Flow matcher value.
4942 * @param[in] reg_type
4943 * Type of device metadata register
4950 flow_dv_match_meta_reg(void *matcher, void *key,
4951 enum modify_reg reg_type,
4952 uint32_t data, uint32_t mask)
4955 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4957 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4962 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
4963 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
4966 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
4967 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
4970 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4971 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
4974 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
4975 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
4978 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
4979 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
4982 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
4983 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
4986 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
4987 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
4990 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
4991 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
4994 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
4995 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
4998 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
4999 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5008 * Add META item to matcher
5010 * @param[in, out] matcher
5012 * @param[in, out] key
5013 * Flow matcher value.
5015 * Flow pattern to translate.
5017 * Item is inner pattern.
5020 flow_dv_translate_item_meta(void *matcher, void *key,
5021 const struct rte_flow_item *item)
5023 const struct rte_flow_item_meta *meta_m;
5024 const struct rte_flow_item_meta *meta_v;
5026 meta_m = (const void *)item->mask;
5028 meta_m = &rte_flow_item_meta_mask;
5029 meta_v = (const void *)item->spec;
5031 flow_dv_match_meta_reg(matcher, key, REG_A,
5032 rte_cpu_to_be_32(meta_v->data),
5033 rte_cpu_to_be_32(meta_m->data));
5037 * Add vport metadata Reg C0 item to matcher
5039 * @param[in, out] matcher
5041 * @param[in, out] key
5042 * Flow matcher value.
5044 * Flow pattern to translate.
5047 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5048 uint32_t value, uint32_t mask)
5050 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5054 * Add tag item to matcher
5056 * @param[in, out] matcher
5058 * @param[in, out] key
5059 * Flow matcher value.
5061 * Flow pattern to translate.
5064 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5065 const struct rte_flow_item *item)
5067 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5068 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5069 enum modify_reg reg = tag_v->id;
5071 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5075 * Add source vport match to the specified matcher.
5077 * @param[in, out] matcher
5079 * @param[in, out] key
5080 * Flow matcher value.
5082 * Source vport value to match
5087 flow_dv_translate_item_source_vport(void *matcher, void *key,
5088 int16_t port, uint16_t mask)
5090 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5091 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5093 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5094 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5098 * Translate port-id item to eswitch match on port-id.
5101 * The devich to configure through.
5102 * @param[in, out] matcher
5104 * @param[in, out] key
5105 * Flow matcher value.
5107 * Flow pattern to translate.
5110 * 0 on success, a negative errno value otherwise.
5113 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5114 void *key, const struct rte_flow_item *item)
5116 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5117 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5118 struct mlx5_priv *priv;
5121 mask = pid_m ? pid_m->id : 0xffff;
5122 id = pid_v ? pid_v->id : dev->data->port_id;
5123 priv = mlx5_port_to_eswitch_info(id, item == NULL);
5126 /* Translate to vport field or to metadata, depending on mode. */
5127 if (priv->vport_meta_mask)
5128 flow_dv_translate_item_meta_vport(matcher, key,
5129 priv->vport_meta_tag,
5130 priv->vport_meta_mask);
5132 flow_dv_translate_item_source_vport(matcher, key,
5133 priv->vport_id, mask);
5138 * Add ICMP6 item to matcher and to the value.
5140 * @param[in, out] matcher
5142 * @param[in, out] key
5143 * Flow matcher value.
5145 * Flow pattern to translate.
5147 * Item is inner pattern.
5150 flow_dv_translate_item_icmp6(void *matcher, void *key,
5151 const struct rte_flow_item *item,
5154 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5155 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5158 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5160 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5162 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5164 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5166 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5168 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5170 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5171 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5175 icmp6_m = &rte_flow_item_icmp6_mask;
5176 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5177 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5178 icmp6_v->type & icmp6_m->type);
5179 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5180 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5181 icmp6_v->code & icmp6_m->code);
5185 * Add ICMP item to matcher and to the value.
5187 * @param[in, out] matcher
5189 * @param[in, out] key
5190 * Flow matcher value.
5192 * Flow pattern to translate.
5194 * Item is inner pattern.
5197 flow_dv_translate_item_icmp(void *matcher, void *key,
5198 const struct rte_flow_item *item,
5201 const struct rte_flow_item_icmp *icmp_m = item->mask;
5202 const struct rte_flow_item_icmp *icmp_v = item->spec;
5205 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5207 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5209 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5211 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5213 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5215 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5217 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5218 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5222 icmp_m = &rte_flow_item_icmp_mask;
5223 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5224 icmp_m->hdr.icmp_type);
5225 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5226 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5227 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5228 icmp_m->hdr.icmp_code);
5229 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5230 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5233 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5235 #define HEADER_IS_ZERO(match_criteria, headers) \
5236 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5237 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5240 * Calculate flow matcher enable bitmap.
5242 * @param match_criteria
5243 * Pointer to flow matcher criteria.
5246 * Bitmap of enabled fields.
5249 flow_dv_matcher_enable(uint32_t *match_criteria)
5251 uint8_t match_criteria_enable;
5253 match_criteria_enable =
5254 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5255 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5256 match_criteria_enable |=
5257 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5258 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5259 match_criteria_enable |=
5260 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5261 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5262 match_criteria_enable |=
5263 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5264 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5265 match_criteria_enable |=
5266 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5267 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5268 return match_criteria_enable;
5275 * @param dev[in, out]
5276 * Pointer to rte_eth_dev structure.
5277 * @param[in] table_id
5280 * Direction of the table.
5281 * @param[in] transfer
5282 * E-Switch or NIC flow.
5284 * pointer to error structure.
5287 * Returns tables resource based on the index, NULL in case of failed.
5289 static struct mlx5_flow_tbl_resource *
5290 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5291 uint32_t table_id, uint8_t egress,
5293 struct rte_flow_error *error)
5295 struct mlx5_priv *priv = dev->data->dev_private;
5296 struct mlx5_ibv_shared *sh = priv->sh;
5297 struct mlx5_flow_tbl_resource *tbl;
5299 #ifdef HAVE_MLX5DV_DR
5301 tbl = &sh->fdb_tbl[table_id];
5303 tbl->obj = mlx5_glue->dr_create_flow_tbl
5304 (sh->fdb_domain, table_id);
5305 } else if (egress) {
5306 tbl = &sh->tx_tbl[table_id];
5308 tbl->obj = mlx5_glue->dr_create_flow_tbl
5309 (sh->tx_domain, table_id);
5311 tbl = &sh->rx_tbl[table_id];
5313 tbl->obj = mlx5_glue->dr_create_flow_tbl
5314 (sh->rx_domain, table_id);
5317 rte_flow_error_set(error, ENOMEM,
5318 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5319 NULL, "cannot create table");
5322 rte_atomic32_inc(&tbl->refcnt);
5328 return &sh->fdb_tbl[table_id];
5330 return &sh->tx_tbl[table_id];
5332 return &sh->rx_tbl[table_id];
5337 * Release a flow table.
5340 * Table resource to be released.
5343 * Returns 0 if table was released, else return 1;
5346 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5350 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5351 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5359 * Register the flow matcher.
5361 * @param dev[in, out]
5362 * Pointer to rte_eth_dev structure.
5363 * @param[in, out] matcher
5364 * Pointer to flow matcher.
5365 * @parm[in, out] dev_flow
5366 * Pointer to the dev_flow.
5368 * pointer to error structure.
5371 * 0 on success otherwise -errno and errno is set.
5374 flow_dv_matcher_register(struct rte_eth_dev *dev,
5375 struct mlx5_flow_dv_matcher *matcher,
5376 struct mlx5_flow *dev_flow,
5377 struct rte_flow_error *error)
5379 struct mlx5_priv *priv = dev->data->dev_private;
5380 struct mlx5_ibv_shared *sh = priv->sh;
5381 struct mlx5_flow_dv_matcher *cache_matcher;
5382 struct mlx5dv_flow_matcher_attr dv_attr = {
5383 .type = IBV_FLOW_ATTR_NORMAL,
5384 .match_mask = (void *)&matcher->mask,
5386 struct mlx5_flow_tbl_resource *tbl = NULL;
5388 /* Lookup from cache. */
5389 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5390 if (matcher->crc == cache_matcher->crc &&
5391 matcher->priority == cache_matcher->priority &&
5392 matcher->egress == cache_matcher->egress &&
5393 matcher->group == cache_matcher->group &&
5394 matcher->transfer == cache_matcher->transfer &&
5395 !memcmp((const void *)matcher->mask.buf,
5396 (const void *)cache_matcher->mask.buf,
5397 cache_matcher->mask.size)) {
5399 "priority %hd use %s matcher %p: refcnt %d++",
5400 cache_matcher->priority,
5401 cache_matcher->egress ? "tx" : "rx",
5402 (void *)cache_matcher,
5403 rte_atomic32_read(&cache_matcher->refcnt));
5404 rte_atomic32_inc(&cache_matcher->refcnt);
5405 dev_flow->dv.matcher = cache_matcher;
5409 /* Register new matcher. */
5410 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5412 return rte_flow_error_set(error, ENOMEM,
5413 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5414 "cannot allocate matcher memory");
5415 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5416 matcher->egress, matcher->transfer,
5419 rte_free(cache_matcher);
5420 return rte_flow_error_set(error, ENOMEM,
5421 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5422 NULL, "cannot create table");
5424 *cache_matcher = *matcher;
5425 dv_attr.match_criteria_enable =
5426 flow_dv_matcher_enable(cache_matcher->mask.buf);
5427 dv_attr.priority = matcher->priority;
5428 if (matcher->egress)
5429 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5430 cache_matcher->matcher_object =
5431 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5432 if (!cache_matcher->matcher_object) {
5433 rte_free(cache_matcher);
5434 #ifdef HAVE_MLX5DV_DR
5435 flow_dv_tbl_resource_release(tbl);
5437 return rte_flow_error_set(error, ENOMEM,
5438 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5439 NULL, "cannot create matcher");
5441 rte_atomic32_inc(&cache_matcher->refcnt);
5442 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5443 dev_flow->dv.matcher = cache_matcher;
5444 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5445 cache_matcher->priority,
5446 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5447 rte_atomic32_read(&cache_matcher->refcnt));
5448 rte_atomic32_inc(&tbl->refcnt);
5453 * Find existing tag resource or create and register a new one.
5455 * @param dev[in, out]
5456 * Pointer to rte_eth_dev structure.
5457 * @param[in, out] resource
5458 * Pointer to tag resource.
5459 * @parm[in, out] dev_flow
5460 * Pointer to the dev_flow.
5462 * pointer to error structure.
5465 * 0 on success otherwise -errno and errno is set.
5468 flow_dv_tag_resource_register
5469 (struct rte_eth_dev *dev,
5470 struct mlx5_flow_dv_tag_resource *resource,
5471 struct mlx5_flow *dev_flow,
5472 struct rte_flow_error *error)
5474 struct mlx5_priv *priv = dev->data->dev_private;
5475 struct mlx5_ibv_shared *sh = priv->sh;
5476 struct mlx5_flow_dv_tag_resource *cache_resource;
5478 /* Lookup a matching resource from cache. */
5479 LIST_FOREACH(cache_resource, &sh->tags, next) {
5480 if (resource->tag == cache_resource->tag) {
5481 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5482 (void *)cache_resource,
5483 rte_atomic32_read(&cache_resource->refcnt));
5484 rte_atomic32_inc(&cache_resource->refcnt);
5485 dev_flow->dv.tag_resource = cache_resource;
5489 /* Register new resource. */
5490 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5491 if (!cache_resource)
5492 return rte_flow_error_set(error, ENOMEM,
5493 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5494 "cannot allocate resource memory");
5495 *cache_resource = *resource;
5496 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5498 if (!cache_resource->action) {
5499 rte_free(cache_resource);
5500 return rte_flow_error_set(error, ENOMEM,
5501 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5502 NULL, "cannot create action");
5504 rte_atomic32_init(&cache_resource->refcnt);
5505 rte_atomic32_inc(&cache_resource->refcnt);
5506 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5507 dev_flow->dv.tag_resource = cache_resource;
5508 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5509 (void *)cache_resource,
5510 rte_atomic32_read(&cache_resource->refcnt));
5518 * Pointer to Ethernet device.
5520 * Pointer to mlx5_flow.
5523 * 1 while a reference on it exists, 0 when freed.
5526 flow_dv_tag_release(struct rte_eth_dev *dev,
5527 struct mlx5_flow_dv_tag_resource *tag)
5530 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5531 dev->data->port_id, (void *)tag,
5532 rte_atomic32_read(&tag->refcnt));
5533 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5534 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5535 LIST_REMOVE(tag, next);
5536 DRV_LOG(DEBUG, "port %u tag %p: removed",
5537 dev->data->port_id, (void *)tag);
5545 * Translate port ID action to vport.
5548 * Pointer to rte_eth_dev structure.
5550 * Pointer to the port ID action.
5551 * @param[out] dst_port_id
5552 * The target port ID.
5554 * Pointer to the error structure.
5557 * 0 on success, a negative errno value otherwise and rte_errno is set.
5560 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5561 const struct rte_flow_action *action,
5562 uint32_t *dst_port_id,
5563 struct rte_flow_error *error)
5566 struct mlx5_priv *priv;
5567 const struct rte_flow_action_port_id *conf =
5568 (const struct rte_flow_action_port_id *)action->conf;
5570 port = conf->original ? dev->data->port_id : conf->id;
5571 priv = mlx5_port_to_eswitch_info(port, false);
5573 return rte_flow_error_set(error, -rte_errno,
5574 RTE_FLOW_ERROR_TYPE_ACTION,
5576 "No eswitch info was found for port");
5577 if (priv->vport_meta_mask)
5578 *dst_port_id = priv->vport_meta_tag;
5580 *dst_port_id = priv->vport_id;
5585 * Add Tx queue matcher
5588 * Pointer to the dev struct.
5589 * @param[in, out] matcher
5591 * @param[in, out] key
5592 * Flow matcher value.
5594 * Flow pattern to translate.
5596 * Item is inner pattern.
5599 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5600 void *matcher, void *key,
5601 const struct rte_flow_item *item)
5603 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5604 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5606 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5608 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5609 struct mlx5_txq_ctrl *txq;
5613 queue_m = (const void *)item->mask;
5616 queue_v = (const void *)item->spec;
5619 txq = mlx5_txq_get(dev, queue_v->queue);
5622 queue = txq->obj->sq->id;
5623 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5624 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5625 queue & queue_m->queue);
5626 mlx5_txq_release(dev, queue_v->queue);
5630 * Fill the flow with DV spec, lock free
5631 * (mutex should be acquired by caller).
5634 * Pointer to rte_eth_dev structure.
5635 * @param[in, out] dev_flow
5636 * Pointer to the sub flow.
5638 * Pointer to the flow attributes.
5640 * Pointer to the list of items.
5641 * @param[in] actions
5642 * Pointer to the list of actions.
5644 * Pointer to the error structure.
5647 * 0 on success, a negative errno value otherwise and rte_errno is set.
5650 __flow_dv_translate(struct rte_eth_dev *dev,
5651 struct mlx5_flow *dev_flow,
5652 const struct rte_flow_attr *attr,
5653 const struct rte_flow_item items[],
5654 const struct rte_flow_action actions[],
5655 struct rte_flow_error *error)
5657 struct mlx5_priv *priv = dev->data->dev_private;
5658 struct rte_flow *flow = dev_flow->flow;
5659 uint64_t item_flags = 0;
5660 uint64_t last_item = 0;
5661 uint64_t action_flags = 0;
5662 uint64_t priority = attr->priority;
5663 struct mlx5_flow_dv_matcher matcher = {
5665 .size = sizeof(matcher.mask.buf),
5669 bool actions_end = false;
5670 struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
5671 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5672 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5674 union flow_dv_attr flow_attr = { .attr = 0 };
5675 struct mlx5_flow_dv_tag_resource tag_resource;
5676 uint32_t modify_action_position = UINT32_MAX;
5677 void *match_mask = matcher.mask.buf;
5678 void *match_value = dev_flow->dv.value.buf;
5679 uint8_t next_protocol = 0xff;
5680 struct rte_vlan_hdr vlan = { 0 };
5684 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5688 dev_flow->group = table;
5690 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5691 if (priority == MLX5_FLOW_PRIO_RSVD)
5692 priority = priv->config.flow_prio - 1;
5693 for (; !actions_end ; actions++) {
5694 const struct rte_flow_action_queue *queue;
5695 const struct rte_flow_action_rss *rss;
5696 const struct rte_flow_action *action = actions;
5697 const struct rte_flow_action_count *count = action->conf;
5698 const uint8_t *rss_key;
5699 const struct rte_flow_action_jump *jump_data;
5700 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5701 struct mlx5_flow_tbl_resource *tbl;
5702 uint32_t port_id = 0;
5703 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5704 int action_type = actions->type;
5705 const struct rte_flow_action *found_action = NULL;
5707 switch (action_type) {
5708 case RTE_FLOW_ACTION_TYPE_VOID:
5710 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5711 if (flow_dv_translate_action_port_id(dev, action,
5714 port_id_resource.port_id = port_id;
5715 if (flow_dv_port_id_action_resource_register
5716 (dev, &port_id_resource, dev_flow, error))
5718 dev_flow->dv.actions[actions_n++] =
5719 dev_flow->dv.port_id_action->action;
5720 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5722 case RTE_FLOW_ACTION_TYPE_FLAG:
5724 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5725 if (!dev_flow->dv.tag_resource)
5726 if (flow_dv_tag_resource_register
5727 (dev, &tag_resource, dev_flow, error))
5729 dev_flow->dv.actions[actions_n++] =
5730 dev_flow->dv.tag_resource->action;
5731 action_flags |= MLX5_FLOW_ACTION_FLAG;
5733 case RTE_FLOW_ACTION_TYPE_MARK:
5734 tag_resource.tag = mlx5_flow_mark_set
5735 (((const struct rte_flow_action_mark *)
5736 (actions->conf))->id);
5737 if (!dev_flow->dv.tag_resource)
5738 if (flow_dv_tag_resource_register
5739 (dev, &tag_resource, dev_flow, error))
5741 dev_flow->dv.actions[actions_n++] =
5742 dev_flow->dv.tag_resource->action;
5743 action_flags |= MLX5_FLOW_ACTION_MARK;
5745 case RTE_FLOW_ACTION_TYPE_DROP:
5746 action_flags |= MLX5_FLOW_ACTION_DROP;
5748 case RTE_FLOW_ACTION_TYPE_QUEUE:
5749 assert(flow->rss.queue);
5750 queue = actions->conf;
5751 flow->rss.queue_num = 1;
5752 (*flow->rss.queue)[0] = queue->index;
5753 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5755 case RTE_FLOW_ACTION_TYPE_RSS:
5756 assert(flow->rss.queue);
5757 rss = actions->conf;
5758 if (flow->rss.queue)
5759 memcpy((*flow->rss.queue), rss->queue,
5760 rss->queue_num * sizeof(uint16_t));
5761 flow->rss.queue_num = rss->queue_num;
5762 /* NULL RSS key indicates default RSS key. */
5763 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5764 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5766 * rss->level and rss.types should be set in advance
5767 * when expanding items for RSS.
5769 action_flags |= MLX5_FLOW_ACTION_RSS;
5771 case RTE_FLOW_ACTION_TYPE_COUNT:
5772 if (!priv->config.devx) {
5773 rte_errno = ENOTSUP;
5776 flow->counter = flow_dv_counter_alloc(dev,
5780 if (flow->counter == NULL)
5782 dev_flow->dv.actions[actions_n++] =
5783 flow->counter->action;
5784 action_flags |= MLX5_FLOW_ACTION_COUNT;
5787 if (rte_errno == ENOTSUP)
5788 return rte_flow_error_set
5790 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5792 "count action not supported");
5794 return rte_flow_error_set
5796 RTE_FLOW_ERROR_TYPE_ACTION,
5798 "cannot create counter"
5801 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5802 dev_flow->dv.actions[actions_n++] =
5803 priv->sh->pop_vlan_action;
5804 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5806 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5807 flow_dev_get_vlan_info_from_items(items, &vlan);
5808 vlan.eth_proto = rte_be_to_cpu_16
5809 ((((const struct rte_flow_action_of_push_vlan *)
5810 actions->conf)->ethertype));
5811 found_action = mlx5_flow_find_action
5813 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5815 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5816 found_action = mlx5_flow_find_action
5818 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5820 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5821 if (flow_dv_create_action_push_vlan
5822 (dev, attr, &vlan, dev_flow, error))
5824 dev_flow->dv.actions[actions_n++] =
5825 dev_flow->dv.push_vlan_res->action;
5826 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5828 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5829 /* of_vlan_push action handled this action */
5830 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5832 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5833 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5835 flow_dev_get_vlan_info_from_items(items, &vlan);
5836 mlx5_update_vlan_vid_pcp(actions, &vlan);
5837 /* If no VLAN push - this is a modify header action */
5838 if (flow_dv_convert_action_modify_vlan_vid
5839 (&mhdr_res, actions, error))
5841 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5843 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5844 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5845 if (flow_dv_create_action_l2_encap(dev, actions,
5850 dev_flow->dv.actions[actions_n++] =
5851 dev_flow->dv.encap_decap->verbs_action;
5852 action_flags |= actions->type ==
5853 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5854 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5855 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5857 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5858 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5859 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5863 dev_flow->dv.actions[actions_n++] =
5864 dev_flow->dv.encap_decap->verbs_action;
5865 action_flags |= actions->type ==
5866 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5867 MLX5_FLOW_ACTION_VXLAN_DECAP :
5868 MLX5_FLOW_ACTION_NVGRE_DECAP;
5870 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5871 /* Handle encap with preceding decap. */
5872 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5873 if (flow_dv_create_action_raw_encap
5874 (dev, actions, dev_flow, attr, error))
5876 dev_flow->dv.actions[actions_n++] =
5877 dev_flow->dv.encap_decap->verbs_action;
5879 /* Handle encap without preceding decap. */
5880 if (flow_dv_create_action_l2_encap
5881 (dev, actions, dev_flow, attr->transfer,
5884 dev_flow->dv.actions[actions_n++] =
5885 dev_flow->dv.encap_decap->verbs_action;
5887 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5889 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5890 /* Check if this decap is followed by encap. */
5891 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5892 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5895 /* Handle decap only if it isn't followed by encap. */
5896 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5897 if (flow_dv_create_action_l2_decap
5898 (dev, dev_flow, attr->transfer, error))
5900 dev_flow->dv.actions[actions_n++] =
5901 dev_flow->dv.encap_decap->verbs_action;
5903 /* If decap is followed by encap, handle it at encap. */
5904 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5906 case RTE_FLOW_ACTION_TYPE_JUMP:
5907 jump_data = action->conf;
5908 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5909 jump_data->group, &table,
5913 tbl = flow_dv_tbl_resource_get(dev, table,
5915 attr->transfer, error);
5917 return rte_flow_error_set
5919 RTE_FLOW_ERROR_TYPE_ACTION,
5921 "cannot create jump action.");
5922 jump_tbl_resource.tbl = tbl;
5923 if (flow_dv_jump_tbl_resource_register
5924 (dev, &jump_tbl_resource, dev_flow, error)) {
5925 flow_dv_tbl_resource_release(tbl);
5926 return rte_flow_error_set
5928 RTE_FLOW_ERROR_TYPE_ACTION,
5930 "cannot create jump action.");
5932 dev_flow->dv.actions[actions_n++] =
5933 dev_flow->dv.jump->action;
5934 action_flags |= MLX5_FLOW_ACTION_JUMP;
5936 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5937 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5938 if (flow_dv_convert_action_modify_mac
5939 (&mhdr_res, actions, error))
5941 action_flags |= actions->type ==
5942 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5943 MLX5_FLOW_ACTION_SET_MAC_SRC :
5944 MLX5_FLOW_ACTION_SET_MAC_DST;
5946 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5947 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5948 if (flow_dv_convert_action_modify_ipv4
5949 (&mhdr_res, actions, error))
5951 action_flags |= actions->type ==
5952 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5953 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5954 MLX5_FLOW_ACTION_SET_IPV4_DST;
5956 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5957 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5958 if (flow_dv_convert_action_modify_ipv6
5959 (&mhdr_res, actions, error))
5961 action_flags |= actions->type ==
5962 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5963 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5964 MLX5_FLOW_ACTION_SET_IPV6_DST;
5966 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5967 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5968 if (flow_dv_convert_action_modify_tp
5969 (&mhdr_res, actions, items,
5972 action_flags |= actions->type ==
5973 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5974 MLX5_FLOW_ACTION_SET_TP_SRC :
5975 MLX5_FLOW_ACTION_SET_TP_DST;
5977 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5978 if (flow_dv_convert_action_modify_dec_ttl
5979 (&mhdr_res, items, &flow_attr, error))
5981 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5983 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5984 if (flow_dv_convert_action_modify_ttl
5985 (&mhdr_res, actions, items,
5988 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5990 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5991 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5992 if (flow_dv_convert_action_modify_tcp_seq
5993 (&mhdr_res, actions, error))
5995 action_flags |= actions->type ==
5996 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5997 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5998 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6001 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6002 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6003 if (flow_dv_convert_action_modify_tcp_ack
6004 (&mhdr_res, actions, error))
6006 action_flags |= actions->type ==
6007 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6008 MLX5_FLOW_ACTION_INC_TCP_ACK :
6009 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6011 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6012 if (flow_dv_convert_action_set_reg
6013 (&mhdr_res, actions, error))
6015 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6017 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6018 if (flow_dv_convert_action_copy_mreg
6019 (dev, &mhdr_res, actions, error))
6021 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6023 case RTE_FLOW_ACTION_TYPE_END:
6025 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
6026 /* create modify action if needed. */
6027 if (flow_dv_modify_hdr_resource_register
6028 (dev, &mhdr_res, dev_flow, error))
6030 dev_flow->dv.actions[modify_action_position] =
6031 dev_flow->dv.modify_hdr->verbs_action;
6037 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
6038 modify_action_position == UINT32_MAX)
6039 modify_action_position = actions_n++;
6041 dev_flow->dv.actions_n = actions_n;
6042 dev_flow->actions = action_flags;
6043 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6044 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6045 int item_type = items->type;
6047 switch (item_type) {
6048 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6049 flow_dv_translate_item_port_id(dev, match_mask,
6050 match_value, items);
6051 last_item = MLX5_FLOW_ITEM_PORT_ID;
6053 case RTE_FLOW_ITEM_TYPE_ETH:
6054 flow_dv_translate_item_eth(match_mask, match_value,
6056 matcher.priority = MLX5_PRIORITY_MAP_L2;
6057 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6058 MLX5_FLOW_LAYER_OUTER_L2;
6060 case RTE_FLOW_ITEM_TYPE_VLAN:
6061 flow_dv_translate_item_vlan(dev_flow,
6062 match_mask, match_value,
6064 matcher.priority = MLX5_PRIORITY_MAP_L2;
6065 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6066 MLX5_FLOW_LAYER_INNER_VLAN) :
6067 (MLX5_FLOW_LAYER_OUTER_L2 |
6068 MLX5_FLOW_LAYER_OUTER_VLAN);
6070 case RTE_FLOW_ITEM_TYPE_IPV4:
6071 mlx5_flow_tunnel_ip_check(items, next_protocol,
6072 &item_flags, &tunnel);
6073 flow_dv_translate_item_ipv4(match_mask, match_value,
6076 matcher.priority = MLX5_PRIORITY_MAP_L3;
6077 dev_flow->hash_fields |=
6078 mlx5_flow_hashfields_adjust
6080 MLX5_IPV4_LAYER_TYPES,
6081 MLX5_IPV4_IBV_RX_HASH);
6082 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6083 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6084 if (items->mask != NULL &&
6085 ((const struct rte_flow_item_ipv4 *)
6086 items->mask)->hdr.next_proto_id) {
6088 ((const struct rte_flow_item_ipv4 *)
6089 (items->spec))->hdr.next_proto_id;
6091 ((const struct rte_flow_item_ipv4 *)
6092 (items->mask))->hdr.next_proto_id;
6094 /* Reset for inner layer. */
6095 next_protocol = 0xff;
6098 case RTE_FLOW_ITEM_TYPE_IPV6:
6099 mlx5_flow_tunnel_ip_check(items, next_protocol,
6100 &item_flags, &tunnel);
6101 flow_dv_translate_item_ipv6(match_mask, match_value,
6104 matcher.priority = MLX5_PRIORITY_MAP_L3;
6105 dev_flow->hash_fields |=
6106 mlx5_flow_hashfields_adjust
6108 MLX5_IPV6_LAYER_TYPES,
6109 MLX5_IPV6_IBV_RX_HASH);
6110 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6111 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6112 if (items->mask != NULL &&
6113 ((const struct rte_flow_item_ipv6 *)
6114 items->mask)->hdr.proto) {
6116 ((const struct rte_flow_item_ipv6 *)
6117 items->spec)->hdr.proto;
6119 ((const struct rte_flow_item_ipv6 *)
6120 items->mask)->hdr.proto;
6122 /* Reset for inner layer. */
6123 next_protocol = 0xff;
6126 case RTE_FLOW_ITEM_TYPE_TCP:
6127 flow_dv_translate_item_tcp(match_mask, match_value,
6129 matcher.priority = MLX5_PRIORITY_MAP_L4;
6130 dev_flow->hash_fields |=
6131 mlx5_flow_hashfields_adjust
6132 (dev_flow, tunnel, ETH_RSS_TCP,
6133 IBV_RX_HASH_SRC_PORT_TCP |
6134 IBV_RX_HASH_DST_PORT_TCP);
6135 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6136 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6138 case RTE_FLOW_ITEM_TYPE_UDP:
6139 flow_dv_translate_item_udp(match_mask, match_value,
6141 matcher.priority = MLX5_PRIORITY_MAP_L4;
6142 dev_flow->hash_fields |=
6143 mlx5_flow_hashfields_adjust
6144 (dev_flow, tunnel, ETH_RSS_UDP,
6145 IBV_RX_HASH_SRC_PORT_UDP |
6146 IBV_RX_HASH_DST_PORT_UDP);
6147 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6148 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6150 case RTE_FLOW_ITEM_TYPE_GRE:
6151 flow_dv_translate_item_gre(match_mask, match_value,
6153 last_item = MLX5_FLOW_LAYER_GRE;
6155 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6156 flow_dv_translate_item_gre_key(match_mask,
6157 match_value, items);
6158 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6160 case RTE_FLOW_ITEM_TYPE_NVGRE:
6161 flow_dv_translate_item_nvgre(match_mask, match_value,
6163 last_item = MLX5_FLOW_LAYER_GRE;
6165 case RTE_FLOW_ITEM_TYPE_VXLAN:
6166 flow_dv_translate_item_vxlan(match_mask, match_value,
6168 last_item = MLX5_FLOW_LAYER_VXLAN;
6170 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6171 flow_dv_translate_item_vxlan(match_mask, match_value,
6173 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6175 case RTE_FLOW_ITEM_TYPE_GENEVE:
6176 flow_dv_translate_item_geneve(match_mask, match_value,
6178 last_item = MLX5_FLOW_LAYER_GENEVE;
6180 case RTE_FLOW_ITEM_TYPE_MPLS:
6181 flow_dv_translate_item_mpls(match_mask, match_value,
6182 items, last_item, tunnel);
6183 last_item = MLX5_FLOW_LAYER_MPLS;
6185 case RTE_FLOW_ITEM_TYPE_META:
6186 flow_dv_translate_item_meta(match_mask, match_value,
6188 last_item = MLX5_FLOW_ITEM_METADATA;
6190 case RTE_FLOW_ITEM_TYPE_ICMP:
6191 flow_dv_translate_item_icmp(match_mask, match_value,
6193 last_item = MLX5_FLOW_LAYER_ICMP;
6195 case RTE_FLOW_ITEM_TYPE_ICMP6:
6196 flow_dv_translate_item_icmp6(match_mask, match_value,
6198 last_item = MLX5_FLOW_LAYER_ICMP6;
6200 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6201 flow_dv_translate_mlx5_item_tag(match_mask,
6202 match_value, items);
6203 last_item = MLX5_FLOW_ITEM_TAG;
6205 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6206 flow_dv_translate_item_tx_queue(dev, match_mask,
6209 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6214 item_flags |= last_item;
6217 * In case of ingress traffic when E-Switch mode is enabled,
6218 * we have two cases where we need to set the source port manually.
6219 * The first one, is in case of Nic steering rule, and the second is
6220 * E-Switch rule where no port_id item was found. In both cases
6221 * the source port is set according the current port in use.
6223 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6224 (priv->representor || priv->master)) {
6225 if (flow_dv_translate_item_port_id(dev, match_mask,
6229 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6230 dev_flow->dv.value.buf));
6231 dev_flow->layers = item_flags;
6232 /* Register matcher. */
6233 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6235 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6237 matcher.egress = attr->egress;
6238 matcher.group = dev_flow->group;
6239 matcher.transfer = attr->transfer;
6240 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6246 * Apply the flow to the NIC, lock free,
6247 * (mutex should be acquired by caller).
6250 * Pointer to the Ethernet device structure.
6251 * @param[in, out] flow
6252 * Pointer to flow structure.
6254 * Pointer to error structure.
6257 * 0 on success, a negative errno value otherwise and rte_errno is set.
6260 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6261 struct rte_flow_error *error)
6263 struct mlx5_flow_dv *dv;
6264 struct mlx5_flow *dev_flow;
6265 struct mlx5_priv *priv = dev->data->dev_private;
6269 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6272 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6273 if (dev_flow->transfer) {
6274 dv->actions[n++] = priv->sh->esw_drop_action;
6276 dv->hrxq = mlx5_hrxq_drop_new(dev);
6280 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6282 "cannot get drop hash queue");
6285 dv->actions[n++] = dv->hrxq->action;
6287 } else if (dev_flow->actions &
6288 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6289 struct mlx5_hrxq *hrxq;
6291 assert(flow->rss.queue);
6292 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
6293 MLX5_RSS_HASH_KEY_LEN,
6294 dev_flow->hash_fields,
6296 flow->rss.queue_num);
6298 hrxq = mlx5_hrxq_new
6299 (dev, flow->rss.key,
6300 MLX5_RSS_HASH_KEY_LEN,
6301 dev_flow->hash_fields,
6303 flow->rss.queue_num,
6304 !!(dev_flow->layers &
6305 MLX5_FLOW_LAYER_TUNNEL));
6310 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6311 "cannot get hash queue");
6315 dv->actions[n++] = dv->hrxq->action;
6318 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6319 (void *)&dv->value, n,
6322 rte_flow_error_set(error, errno,
6323 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6325 "hardware refuses to create flow");
6328 if (priv->vmwa_context &&
6329 dev_flow->dv.vf_vlan.tag &&
6330 !dev_flow->dv.vf_vlan.created) {
6332 * The rule contains the VLAN pattern.
6333 * For VF we are going to create VLAN
6334 * interface to make hypervisor set correct
6335 * e-Switch vport context.
6337 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6342 err = rte_errno; /* Save rte_errno before cleanup. */
6343 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6344 struct mlx5_flow_dv *dv = &dev_flow->dv;
6346 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6347 mlx5_hrxq_drop_release(dev);
6349 mlx5_hrxq_release(dev, dv->hrxq);
6352 if (dev_flow->dv.vf_vlan.tag &&
6353 dev_flow->dv.vf_vlan.created)
6354 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6356 rte_errno = err; /* Restore rte_errno. */
6361 * Release the flow matcher.
6364 * Pointer to Ethernet device.
6366 * Pointer to mlx5_flow.
6369 * 1 while a reference on it exists, 0 when freed.
6372 flow_dv_matcher_release(struct rte_eth_dev *dev,
6373 struct mlx5_flow *flow)
6375 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6376 struct mlx5_priv *priv = dev->data->dev_private;
6377 struct mlx5_ibv_shared *sh = priv->sh;
6378 struct mlx5_flow_tbl_resource *tbl;
6380 assert(matcher->matcher_object);
6381 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6382 dev->data->port_id, (void *)matcher,
6383 rte_atomic32_read(&matcher->refcnt));
6384 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6385 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6386 (matcher->matcher_object));
6387 LIST_REMOVE(matcher, next);
6388 if (matcher->egress)
6389 tbl = &sh->tx_tbl[matcher->group];
6391 tbl = &sh->rx_tbl[matcher->group];
6392 flow_dv_tbl_resource_release(tbl);
6394 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6395 dev->data->port_id, (void *)matcher);
6402 * Release an encap/decap resource.
6405 * Pointer to mlx5_flow.
6408 * 1 while a reference on it exists, 0 when freed.
6411 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6413 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6414 flow->dv.encap_decap;
6416 assert(cache_resource->verbs_action);
6417 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6418 (void *)cache_resource,
6419 rte_atomic32_read(&cache_resource->refcnt));
6420 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6421 claim_zero(mlx5_glue->destroy_flow_action
6422 (cache_resource->verbs_action));
6423 LIST_REMOVE(cache_resource, next);
6424 rte_free(cache_resource);
6425 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6426 (void *)cache_resource);
6433 * Release an jump to table action resource.
6436 * Pointer to mlx5_flow.
6439 * 1 while a reference on it exists, 0 when freed.
6442 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6444 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6447 assert(cache_resource->action);
6448 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6449 (void *)cache_resource,
6450 rte_atomic32_read(&cache_resource->refcnt));
6451 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6452 claim_zero(mlx5_glue->destroy_flow_action
6453 (cache_resource->action));
6454 LIST_REMOVE(cache_resource, next);
6455 flow_dv_tbl_resource_release(cache_resource->tbl);
6456 rte_free(cache_resource);
6457 DRV_LOG(DEBUG, "jump table resource %p: removed",
6458 (void *)cache_resource);
6465 * Release a modify-header resource.
6468 * Pointer to mlx5_flow.
6471 * 1 while a reference on it exists, 0 when freed.
6474 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6476 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6477 flow->dv.modify_hdr;
6479 assert(cache_resource->verbs_action);
6480 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6481 (void *)cache_resource,
6482 rte_atomic32_read(&cache_resource->refcnt));
6483 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6484 claim_zero(mlx5_glue->destroy_flow_action
6485 (cache_resource->verbs_action));
6486 LIST_REMOVE(cache_resource, next);
6487 rte_free(cache_resource);
6488 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6489 (void *)cache_resource);
6496 * Release port ID action resource.
6499 * Pointer to mlx5_flow.
6502 * 1 while a reference on it exists, 0 when freed.
6505 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6507 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6508 flow->dv.port_id_action;
6510 assert(cache_resource->action);
6511 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6512 (void *)cache_resource,
6513 rte_atomic32_read(&cache_resource->refcnt));
6514 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6515 claim_zero(mlx5_glue->destroy_flow_action
6516 (cache_resource->action));
6517 LIST_REMOVE(cache_resource, next);
6518 rte_free(cache_resource);
6519 DRV_LOG(DEBUG, "port id action resource %p: removed",
6520 (void *)cache_resource);
6527 * Release push vlan action resource.
6530 * Pointer to mlx5_flow.
6533 * 1 while a reference on it exists, 0 when freed.
6536 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6538 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6539 flow->dv.push_vlan_res;
6541 assert(cache_resource->action);
6542 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6543 (void *)cache_resource,
6544 rte_atomic32_read(&cache_resource->refcnt));
6545 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6546 claim_zero(mlx5_glue->destroy_flow_action
6547 (cache_resource->action));
6548 LIST_REMOVE(cache_resource, next);
6549 rte_free(cache_resource);
6550 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6551 (void *)cache_resource);
6558 * Remove the flow from the NIC but keeps it in memory.
6559 * Lock free, (mutex should be acquired by caller).
6562 * Pointer to Ethernet device.
6563 * @param[in, out] flow
6564 * Pointer to flow structure.
6567 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6569 struct mlx5_flow_dv *dv;
6570 struct mlx5_flow *dev_flow;
6574 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6577 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6581 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6582 mlx5_hrxq_drop_release(dev);
6584 mlx5_hrxq_release(dev, dv->hrxq);
6587 if (dev_flow->dv.vf_vlan.tag &&
6588 dev_flow->dv.vf_vlan.created)
6589 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6594 * Remove the flow from the NIC and the memory.
6595 * Lock free, (mutex should be acquired by caller).
6598 * Pointer to the Ethernet device structure.
6599 * @param[in, out] flow
6600 * Pointer to flow structure.
6603 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6605 struct mlx5_flow *dev_flow;
6609 __flow_dv_remove(dev, flow);
6610 if (flow->counter) {
6611 flow_dv_counter_release(dev, flow->counter);
6612 flow->counter = NULL;
6614 while (!LIST_EMPTY(&flow->dev_flows)) {
6615 dev_flow = LIST_FIRST(&flow->dev_flows);
6616 LIST_REMOVE(dev_flow, next);
6617 if (dev_flow->dv.matcher)
6618 flow_dv_matcher_release(dev, dev_flow);
6619 if (dev_flow->dv.encap_decap)
6620 flow_dv_encap_decap_resource_release(dev_flow);
6621 if (dev_flow->dv.modify_hdr)
6622 flow_dv_modify_hdr_resource_release(dev_flow);
6623 if (dev_flow->dv.jump)
6624 flow_dv_jump_tbl_resource_release(dev_flow);
6625 if (dev_flow->dv.port_id_action)
6626 flow_dv_port_id_action_resource_release(dev_flow);
6627 if (dev_flow->dv.push_vlan_res)
6628 flow_dv_push_vlan_action_resource_release(dev_flow);
6629 if (dev_flow->dv.tag_resource)
6630 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
6636 * Query a dv flow rule for its statistics via devx.
6639 * Pointer to Ethernet device.
6641 * Pointer to the sub flow.
6643 * data retrieved by the query.
6645 * Perform verbose error reporting if not NULL.
6648 * 0 on success, a negative errno value otherwise and rte_errno is set.
6651 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6652 void *data, struct rte_flow_error *error)
6654 struct mlx5_priv *priv = dev->data->dev_private;
6655 struct rte_flow_query_count *qc = data;
6657 if (!priv->config.devx)
6658 return rte_flow_error_set(error, ENOTSUP,
6659 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6661 "counters are not supported");
6662 if (flow->counter) {
6663 uint64_t pkts, bytes;
6664 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6668 return rte_flow_error_set(error, -err,
6669 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6670 NULL, "cannot read counters");
6673 qc->hits = pkts - flow->counter->hits;
6674 qc->bytes = bytes - flow->counter->bytes;
6676 flow->counter->hits = pkts;
6677 flow->counter->bytes = bytes;
6681 return rte_flow_error_set(error, EINVAL,
6682 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6684 "counters are not available");
6690 * @see rte_flow_query()
6694 flow_dv_query(struct rte_eth_dev *dev,
6695 struct rte_flow *flow __rte_unused,
6696 const struct rte_flow_action *actions __rte_unused,
6697 void *data __rte_unused,
6698 struct rte_flow_error *error __rte_unused)
6702 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6703 switch (actions->type) {
6704 case RTE_FLOW_ACTION_TYPE_VOID:
6706 case RTE_FLOW_ACTION_TYPE_COUNT:
6707 ret = flow_dv_query_count(dev, flow, data, error);
6710 return rte_flow_error_set(error, ENOTSUP,
6711 RTE_FLOW_ERROR_TYPE_ACTION,
6713 "action not supported");
6720 * Mutex-protected thunk to lock-free __flow_dv_translate().
6723 flow_dv_translate(struct rte_eth_dev *dev,
6724 struct mlx5_flow *dev_flow,
6725 const struct rte_flow_attr *attr,
6726 const struct rte_flow_item items[],
6727 const struct rte_flow_action actions[],
6728 struct rte_flow_error *error)
6732 flow_dv_shared_lock(dev);
6733 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6734 flow_dv_shared_unlock(dev);
6739 * Mutex-protected thunk to lock-free __flow_dv_apply().
6742 flow_dv_apply(struct rte_eth_dev *dev,
6743 struct rte_flow *flow,
6744 struct rte_flow_error *error)
6748 flow_dv_shared_lock(dev);
6749 ret = __flow_dv_apply(dev, flow, error);
6750 flow_dv_shared_unlock(dev);
6755 * Mutex-protected thunk to lock-free __flow_dv_remove().
6758 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6760 flow_dv_shared_lock(dev);
6761 __flow_dv_remove(dev, flow);
6762 flow_dv_shared_unlock(dev);
6766 * Mutex-protected thunk to lock-free __flow_dv_destroy().
6769 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6771 flow_dv_shared_lock(dev);
6772 __flow_dv_destroy(dev, flow);
6773 flow_dv_shared_unlock(dev);
6776 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6777 .validate = flow_dv_validate,
6778 .prepare = flow_dv_prepare,
6779 .translate = flow_dv_translate,
6780 .apply = flow_dv_apply,
6781 .remove = flow_dv_remove,
6782 .destroy = flow_dv_destroy,
6783 .query = flow_dv_query,
6786 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */