1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_d_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_d_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_A] = MLX5_MODI_META_DATA_REG_A,
836 [REG_B] = MLX5_MODI_META_DATA_REG_B,
837 [REG_C_0] = MLX5_MODI_META_REG_C_0,
838 [REG_C_1] = MLX5_MODI_META_REG_C_1,
839 [REG_C_2] = MLX5_MODI_META_REG_C_2,
840 [REG_C_3] = MLX5_MODI_META_REG_C_3,
841 [REG_C_4] = MLX5_MODI_META_REG_C_4,
842 [REG_C_5] = MLX5_MODI_META_REG_C_5,
843 [REG_C_6] = MLX5_MODI_META_REG_C_6,
844 [REG_C_7] = MLX5_MODI_META_REG_C_7,
848 * Convert register set to DV specification.
850 * @param[in,out] resource
851 * Pointer to the modify-header resource.
853 * Pointer to action specification.
855 * Pointer to the error structure.
858 * 0 on success, a negative errno value otherwise and rte_errno is set.
861 flow_dv_convert_action_set_reg
862 (struct mlx5_flow_dv_modify_hdr_resource *resource,
863 const struct rte_flow_action *action,
864 struct rte_flow_error *error)
866 const struct mlx5_rte_flow_action_set_tag *conf = (action->conf);
867 struct mlx5_modification_cmd *actions = resource->actions;
868 uint32_t i = resource->actions_num;
870 if (i >= MLX5_MODIFY_NUM)
871 return rte_flow_error_set(error, EINVAL,
872 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
873 "too many items to modify");
874 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
875 actions[i].field = reg_to_field[conf->id];
876 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
877 actions[i].data1 = conf->data;
879 resource->actions_num = i;
880 if (!resource->actions_num)
881 return rte_flow_error_set(error, EINVAL,
882 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
883 "invalid modification flow item");
888 * Validate META item.
891 * Pointer to the rte_eth_dev structure.
893 * Item specification.
895 * Attributes of flow that includes this item.
897 * Pointer to error structure.
900 * 0 on success, a negative errno value otherwise and rte_errno is set.
903 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
904 const struct rte_flow_item *item,
905 const struct rte_flow_attr *attr,
906 struct rte_flow_error *error)
908 const struct rte_flow_item_meta *spec = item->spec;
909 const struct rte_flow_item_meta *mask = item->mask;
910 const struct rte_flow_item_meta nic_mask = {
916 return rte_flow_error_set(error, EINVAL,
917 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
919 "data cannot be empty");
921 return rte_flow_error_set(error, EINVAL,
922 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
924 "data cannot be zero");
926 mask = &rte_flow_item_meta_mask;
927 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
928 (const uint8_t *)&nic_mask,
929 sizeof(struct rte_flow_item_meta),
934 return rte_flow_error_set(error, ENOTSUP,
935 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
937 "pattern not supported for ingress");
942 * Validate vport item.
945 * Pointer to the rte_eth_dev structure.
947 * Item specification.
949 * Attributes of flow that includes this item.
950 * @param[in] item_flags
951 * Bit-fields that holds the items detected until now.
953 * Pointer to error structure.
956 * 0 on success, a negative errno value otherwise and rte_errno is set.
959 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
960 const struct rte_flow_item *item,
961 const struct rte_flow_attr *attr,
963 struct rte_flow_error *error)
965 const struct rte_flow_item_port_id *spec = item->spec;
966 const struct rte_flow_item_port_id *mask = item->mask;
967 const struct rte_flow_item_port_id switch_mask = {
970 struct mlx5_priv *esw_priv;
971 struct mlx5_priv *dev_priv;
975 return rte_flow_error_set(error, EINVAL,
976 RTE_FLOW_ERROR_TYPE_ITEM,
978 "match on port id is valid only"
979 " when transfer flag is enabled");
980 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
981 return rte_flow_error_set(error, ENOTSUP,
982 RTE_FLOW_ERROR_TYPE_ITEM, item,
983 "multiple source ports are not"
987 if (mask->id != 0xffffffff)
988 return rte_flow_error_set(error, ENOTSUP,
989 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
991 "no support for partial mask on"
993 ret = mlx5_flow_item_acceptable
994 (item, (const uint8_t *)mask,
995 (const uint8_t *)&rte_flow_item_port_id_mask,
996 sizeof(struct rte_flow_item_port_id),
1002 esw_priv = mlx5_port_to_eswitch_info(spec->id);
1004 return rte_flow_error_set(error, rte_errno,
1005 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1006 "failed to obtain E-Switch info for"
1008 dev_priv = mlx5_dev_to_eswitch_info(dev);
1010 return rte_flow_error_set(error, rte_errno,
1011 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1013 "failed to obtain E-Switch info");
1014 if (esw_priv->domain_id != dev_priv->domain_id)
1015 return rte_flow_error_set(error, EINVAL,
1016 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1017 "cannot match on a port from a"
1018 " different E-Switch");
1023 * Validate the pop VLAN action.
1026 * Pointer to the rte_eth_dev structure.
1027 * @param[in] action_flags
1028 * Holds the actions detected until now.
1030 * Pointer to the pop vlan action.
1031 * @param[in] item_flags
1032 * The items found in this flow rule.
1034 * Pointer to flow attributes.
1036 * Pointer to error structure.
1039 * 0 on success, a negative errno value otherwise and rte_errno is set.
1042 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1043 uint64_t action_flags,
1044 const struct rte_flow_action *action,
1045 uint64_t item_flags,
1046 const struct rte_flow_attr *attr,
1047 struct rte_flow_error *error)
1049 struct mlx5_priv *priv = dev->data->dev_private;
1053 if (!priv->sh->pop_vlan_action)
1054 return rte_flow_error_set(error, ENOTSUP,
1055 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1057 "pop vlan action is not supported");
1059 * Check for inconsistencies:
1060 * fail strip_vlan in a flow that matches packets without VLAN tags.
1061 * fail strip_vlan in a flow that matches packets without explicitly a
1062 * matching on VLAN tag ?
1064 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1065 return rte_flow_error_set(error, ENOTSUP,
1066 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1068 "no support for multiple vlan pop "
1070 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1071 return rte_flow_error_set(error, ENOTSUP,
1072 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1074 "cannot pop vlan without a "
1075 "match on (outer) vlan in the flow");
1076 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1077 return rte_flow_error_set(error, EINVAL,
1078 RTE_FLOW_ERROR_TYPE_ACTION, action,
1079 "wrong action order, port_id should "
1080 "be after pop VLAN action");
1085 * Get VLAN default info from vlan match info.
1088 * Pointer to the rte_eth_dev structure.
1090 * the list of item specifications.
1092 * pointer VLAN info to fill to.
1094 * Pointer to error structure.
1097 * 0 on success, a negative errno value otherwise and rte_errno is set.
1100 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1101 struct rte_vlan_hdr *vlan)
1103 const struct rte_flow_item_vlan nic_mask = {
1104 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1105 MLX5DV_FLOW_VLAN_VID_MASK),
1106 .inner_type = RTE_BE16(0xffff),
1111 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1112 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1114 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1115 const struct rte_flow_item_vlan *vlan_m = items->mask;
1116 const struct rte_flow_item_vlan *vlan_v = items->spec;
1120 /* Only full match values are accepted */
1121 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1122 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1123 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1125 rte_be_to_cpu_16(vlan_v->tci &
1126 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1128 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1129 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1130 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1132 rte_be_to_cpu_16(vlan_v->tci &
1133 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1135 if (vlan_m->inner_type == nic_mask.inner_type)
1136 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1137 vlan_m->inner_type);
1142 * Validate the push VLAN action.
1144 * @param[in] action_flags
1145 * Holds the actions detected until now.
1147 * Pointer to the encap action.
1149 * Pointer to flow attributes
1151 * Pointer to error structure.
1154 * 0 on success, a negative errno value otherwise and rte_errno is set.
1157 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1158 uint64_t item_flags,
1159 const struct rte_flow_action *action,
1160 const struct rte_flow_attr *attr,
1161 struct rte_flow_error *error)
1163 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1165 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1166 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1167 return rte_flow_error_set(error, EINVAL,
1168 RTE_FLOW_ERROR_TYPE_ACTION, action,
1169 "invalid vlan ethertype");
1171 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1172 return rte_flow_error_set(error, ENOTSUP,
1173 RTE_FLOW_ERROR_TYPE_ACTION, action,
1174 "no support for multiple VLAN "
1176 if (!mlx5_flow_find_action
1177 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1178 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1179 return rte_flow_error_set(error, ENOTSUP,
1180 RTE_FLOW_ERROR_TYPE_ACTION, action,
1181 "push VLAN needs to match on VLAN in order to "
1182 "get VLAN VID information because there is "
1183 "no followed set VLAN VID action");
1184 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1185 return rte_flow_error_set(error, EINVAL,
1186 RTE_FLOW_ERROR_TYPE_ACTION, action,
1187 "wrong action order, port_id should "
1188 "be after push VLAN");
1194 * Validate the set VLAN PCP.
1196 * @param[in] action_flags
1197 * Holds the actions detected until now.
1198 * @param[in] actions
1199 * Pointer to the list of actions remaining in the flow rule.
1201 * Pointer to flow attributes
1203 * Pointer to error structure.
1206 * 0 on success, a negative errno value otherwise and rte_errno is set.
1209 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1210 const struct rte_flow_action actions[],
1211 struct rte_flow_error *error)
1213 const struct rte_flow_action *action = actions;
1214 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1216 if (conf->vlan_pcp > 7)
1217 return rte_flow_error_set(error, EINVAL,
1218 RTE_FLOW_ERROR_TYPE_ACTION, action,
1219 "VLAN PCP value is too big");
1220 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1221 return rte_flow_error_set(error, ENOTSUP,
1222 RTE_FLOW_ERROR_TYPE_ACTION, action,
1223 "set VLAN PCP action must follow "
1224 "the push VLAN action");
1225 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1226 return rte_flow_error_set(error, ENOTSUP,
1227 RTE_FLOW_ERROR_TYPE_ACTION, action,
1228 "Multiple VLAN PCP modification are "
1230 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1231 return rte_flow_error_set(error, EINVAL,
1232 RTE_FLOW_ERROR_TYPE_ACTION, action,
1233 "wrong action order, port_id should "
1234 "be after set VLAN PCP");
1239 * Validate the set VLAN VID.
1241 * @param[in] item_flags
1242 * Holds the items detected in this rule.
1243 * @param[in] actions
1244 * Pointer to the list of actions remaining in the flow rule.
1246 * Pointer to flow attributes
1248 * Pointer to error structure.
1251 * 0 on success, a negative errno value otherwise and rte_errno is set.
1254 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1255 uint64_t action_flags,
1256 const struct rte_flow_action actions[],
1257 struct rte_flow_error *error)
1259 const struct rte_flow_action *action = actions;
1260 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1262 if (conf->vlan_vid > RTE_BE16(0xFFE))
1263 return rte_flow_error_set(error, EINVAL,
1264 RTE_FLOW_ERROR_TYPE_ACTION, action,
1265 "VLAN VID value is too big");
1266 /* there is an of_push_vlan action before us */
1267 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1268 if (mlx5_flow_find_action(actions + 1,
1269 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1270 return rte_flow_error_set(error, ENOTSUP,
1271 RTE_FLOW_ERROR_TYPE_ACTION, action,
1272 "Multiple VLAN VID modifications are "
1279 * Action is on an existing VLAN header:
1280 * Need to verify this is a single modify CID action.
1281 * Rule mast include a match on outer VLAN.
1283 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1284 return rte_flow_error_set(error, ENOTSUP,
1285 RTE_FLOW_ERROR_TYPE_ACTION, action,
1286 "Multiple VLAN VID modifications are "
1288 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1289 return rte_flow_error_set(error, EINVAL,
1290 RTE_FLOW_ERROR_TYPE_ACTION, action,
1291 "match on VLAN is required in order "
1293 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1294 return rte_flow_error_set(error, EINVAL,
1295 RTE_FLOW_ERROR_TYPE_ACTION, action,
1296 "wrong action order, port_id should "
1297 "be after set VLAN VID");
1302 * Validate count action.
1307 * Pointer to error structure.
1310 * 0 on success, a negative errno value otherwise and rte_errno is set.
1313 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1314 struct rte_flow_error *error)
1316 struct mlx5_priv *priv = dev->data->dev_private;
1318 if (!priv->config.devx)
1320 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1324 return rte_flow_error_set
1326 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1328 "count action not supported");
1332 * Validate the L2 encap action.
1334 * @param[in] action_flags
1335 * Holds the actions detected until now.
1337 * Pointer to the encap action.
1339 * Pointer to flow attributes
1341 * Pointer to error structure.
1344 * 0 on success, a negative errno value otherwise and rte_errno is set.
1347 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1348 const struct rte_flow_action *action,
1349 const struct rte_flow_attr *attr,
1350 struct rte_flow_error *error)
1352 if (!(action->conf))
1353 return rte_flow_error_set(error, EINVAL,
1354 RTE_FLOW_ERROR_TYPE_ACTION, action,
1355 "configuration cannot be null");
1356 if (action_flags & MLX5_FLOW_ACTION_DROP)
1357 return rte_flow_error_set(error, EINVAL,
1358 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1359 "can't drop and encap in same flow");
1360 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1361 return rte_flow_error_set(error, EINVAL,
1362 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1363 "can only have a single encap or"
1364 " decap action in a flow");
1365 if (!attr->transfer && attr->ingress)
1366 return rte_flow_error_set(error, ENOTSUP,
1367 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1369 "encap action not supported for "
1375 * Validate the L2 decap action.
1377 * @param[in] action_flags
1378 * Holds the actions detected until now.
1380 * Pointer to flow attributes
1382 * Pointer to error structure.
1385 * 0 on success, a negative errno value otherwise and rte_errno is set.
1388 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1389 const struct rte_flow_attr *attr,
1390 struct rte_flow_error *error)
1392 if (action_flags & MLX5_FLOW_ACTION_DROP)
1393 return rte_flow_error_set(error, EINVAL,
1394 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1395 "can't drop and decap in same flow");
1396 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1397 return rte_flow_error_set(error, EINVAL,
1398 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1399 "can only have a single encap or"
1400 " decap action in a flow");
1401 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1402 return rte_flow_error_set(error, EINVAL,
1403 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1404 "can't have decap action after"
1407 return rte_flow_error_set(error, ENOTSUP,
1408 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1410 "decap action not supported for "
1416 * Validate the raw encap action.
1418 * @param[in] action_flags
1419 * Holds the actions detected until now.
1421 * Pointer to the encap action.
1423 * Pointer to flow attributes
1425 * Pointer to error structure.
1428 * 0 on success, a negative errno value otherwise and rte_errno is set.
1431 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1432 const struct rte_flow_action *action,
1433 const struct rte_flow_attr *attr,
1434 struct rte_flow_error *error)
1436 const struct rte_flow_action_raw_encap *raw_encap =
1437 (const struct rte_flow_action_raw_encap *)action->conf;
1438 if (!(action->conf))
1439 return rte_flow_error_set(error, EINVAL,
1440 RTE_FLOW_ERROR_TYPE_ACTION, action,
1441 "configuration cannot be null");
1442 if (action_flags & MLX5_FLOW_ACTION_DROP)
1443 return rte_flow_error_set(error, EINVAL,
1444 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1445 "can't drop and encap in same flow");
1446 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1447 return rte_flow_error_set(error, EINVAL,
1448 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1449 "can only have a single encap"
1450 " action in a flow");
1451 /* encap without preceding decap is not supported for ingress */
1452 if (!attr->transfer && attr->ingress &&
1453 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1454 return rte_flow_error_set(error, ENOTSUP,
1455 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1457 "encap action not supported for "
1459 if (!raw_encap->size || !raw_encap->data)
1460 return rte_flow_error_set(error, EINVAL,
1461 RTE_FLOW_ERROR_TYPE_ACTION, action,
1462 "raw encap data cannot be empty");
1467 * Validate the raw decap action.
1469 * @param[in] action_flags
1470 * Holds the actions detected until now.
1472 * Pointer to the encap action.
1474 * Pointer to flow attributes
1476 * Pointer to error structure.
1479 * 0 on success, a negative errno value otherwise and rte_errno is set.
1482 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1483 const struct rte_flow_action *action,
1484 const struct rte_flow_attr *attr,
1485 struct rte_flow_error *error)
1487 if (action_flags & MLX5_FLOW_ACTION_DROP)
1488 return rte_flow_error_set(error, EINVAL,
1489 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1490 "can't drop and decap in same flow");
1491 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1492 return rte_flow_error_set(error, EINVAL,
1493 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1494 "can't have encap action before"
1496 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1497 return rte_flow_error_set(error, EINVAL,
1498 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1499 "can only have a single decap"
1500 " action in a flow");
1501 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1502 return rte_flow_error_set(error, EINVAL,
1503 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1504 "can't have decap action after"
1506 /* decap action is valid on egress only if it is followed by encap */
1508 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1509 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1512 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1513 return rte_flow_error_set
1515 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1516 NULL, "decap action not supported"
1523 * Find existing encap/decap resource or create and register a new one.
1525 * @param dev[in, out]
1526 * Pointer to rte_eth_dev structure.
1527 * @param[in, out] resource
1528 * Pointer to encap/decap resource.
1529 * @parm[in, out] dev_flow
1530 * Pointer to the dev_flow.
1532 * pointer to error structure.
1535 * 0 on success otherwise -errno and errno is set.
1538 flow_dv_encap_decap_resource_register
1539 (struct rte_eth_dev *dev,
1540 struct mlx5_flow_dv_encap_decap_resource *resource,
1541 struct mlx5_flow *dev_flow,
1542 struct rte_flow_error *error)
1544 struct mlx5_priv *priv = dev->data->dev_private;
1545 struct mlx5_ibv_shared *sh = priv->sh;
1546 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1547 struct rte_flow *flow = dev_flow->flow;
1548 struct mlx5dv_dr_domain *domain;
1550 resource->flags = flow->group ? 0 : 1;
1551 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1552 domain = sh->fdb_domain;
1553 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1554 domain = sh->rx_domain;
1556 domain = sh->tx_domain;
1558 /* Lookup a matching resource from cache. */
1559 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1560 if (resource->reformat_type == cache_resource->reformat_type &&
1561 resource->ft_type == cache_resource->ft_type &&
1562 resource->flags == cache_resource->flags &&
1563 resource->size == cache_resource->size &&
1564 !memcmp((const void *)resource->buf,
1565 (const void *)cache_resource->buf,
1567 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1568 (void *)cache_resource,
1569 rte_atomic32_read(&cache_resource->refcnt));
1570 rte_atomic32_inc(&cache_resource->refcnt);
1571 dev_flow->dv.encap_decap = cache_resource;
1575 /* Register new encap/decap resource. */
1576 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1577 if (!cache_resource)
1578 return rte_flow_error_set(error, ENOMEM,
1579 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1580 "cannot allocate resource memory");
1581 *cache_resource = *resource;
1582 cache_resource->verbs_action =
1583 mlx5_glue->dv_create_flow_action_packet_reformat
1584 (sh->ctx, cache_resource->reformat_type,
1585 cache_resource->ft_type, domain, cache_resource->flags,
1586 cache_resource->size,
1587 (cache_resource->size ? cache_resource->buf : NULL));
1588 if (!cache_resource->verbs_action) {
1589 rte_free(cache_resource);
1590 return rte_flow_error_set(error, ENOMEM,
1591 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1592 NULL, "cannot create action");
1594 rte_atomic32_init(&cache_resource->refcnt);
1595 rte_atomic32_inc(&cache_resource->refcnt);
1596 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1597 dev_flow->dv.encap_decap = cache_resource;
1598 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1599 (void *)cache_resource,
1600 rte_atomic32_read(&cache_resource->refcnt));
1605 * Find existing table jump resource or create and register a new one.
1607 * @param dev[in, out]
1608 * Pointer to rte_eth_dev structure.
1609 * @param[in, out] resource
1610 * Pointer to jump table resource.
1611 * @parm[in, out] dev_flow
1612 * Pointer to the dev_flow.
1614 * pointer to error structure.
1617 * 0 on success otherwise -errno and errno is set.
1620 flow_dv_jump_tbl_resource_register
1621 (struct rte_eth_dev *dev,
1622 struct mlx5_flow_dv_jump_tbl_resource *resource,
1623 struct mlx5_flow *dev_flow,
1624 struct rte_flow_error *error)
1626 struct mlx5_priv *priv = dev->data->dev_private;
1627 struct mlx5_ibv_shared *sh = priv->sh;
1628 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1630 /* Lookup a matching resource from cache. */
1631 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1632 if (resource->tbl == cache_resource->tbl) {
1633 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1634 (void *)cache_resource,
1635 rte_atomic32_read(&cache_resource->refcnt));
1636 rte_atomic32_inc(&cache_resource->refcnt);
1637 dev_flow->dv.jump = cache_resource;
1641 /* Register new jump table resource. */
1642 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1643 if (!cache_resource)
1644 return rte_flow_error_set(error, ENOMEM,
1645 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1646 "cannot allocate resource memory");
1647 *cache_resource = *resource;
1648 cache_resource->action =
1649 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1650 (resource->tbl->obj);
1651 if (!cache_resource->action) {
1652 rte_free(cache_resource);
1653 return rte_flow_error_set(error, ENOMEM,
1654 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1655 NULL, "cannot create action");
1657 rte_atomic32_init(&cache_resource->refcnt);
1658 rte_atomic32_inc(&cache_resource->refcnt);
1659 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1660 dev_flow->dv.jump = cache_resource;
1661 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1662 (void *)cache_resource,
1663 rte_atomic32_read(&cache_resource->refcnt));
1668 * Find existing table port ID resource or create and register a new one.
1670 * @param dev[in, out]
1671 * Pointer to rte_eth_dev structure.
1672 * @param[in, out] resource
1673 * Pointer to port ID action resource.
1674 * @parm[in, out] dev_flow
1675 * Pointer to the dev_flow.
1677 * pointer to error structure.
1680 * 0 on success otherwise -errno and errno is set.
1683 flow_dv_port_id_action_resource_register
1684 (struct rte_eth_dev *dev,
1685 struct mlx5_flow_dv_port_id_action_resource *resource,
1686 struct mlx5_flow *dev_flow,
1687 struct rte_flow_error *error)
1689 struct mlx5_priv *priv = dev->data->dev_private;
1690 struct mlx5_ibv_shared *sh = priv->sh;
1691 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1693 /* Lookup a matching resource from cache. */
1694 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1695 if (resource->port_id == cache_resource->port_id) {
1696 DRV_LOG(DEBUG, "port id action resource resource %p: "
1698 (void *)cache_resource,
1699 rte_atomic32_read(&cache_resource->refcnt));
1700 rte_atomic32_inc(&cache_resource->refcnt);
1701 dev_flow->dv.port_id_action = cache_resource;
1705 /* Register new port id action resource. */
1706 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1707 if (!cache_resource)
1708 return rte_flow_error_set(error, ENOMEM,
1709 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1710 "cannot allocate resource memory");
1711 *cache_resource = *resource;
1712 cache_resource->action =
1713 mlx5_glue->dr_create_flow_action_dest_vport
1714 (priv->sh->fdb_domain, resource->port_id);
1715 if (!cache_resource->action) {
1716 rte_free(cache_resource);
1717 return rte_flow_error_set(error, ENOMEM,
1718 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1719 NULL, "cannot create action");
1721 rte_atomic32_init(&cache_resource->refcnt);
1722 rte_atomic32_inc(&cache_resource->refcnt);
1723 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1724 dev_flow->dv.port_id_action = cache_resource;
1725 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1726 (void *)cache_resource,
1727 rte_atomic32_read(&cache_resource->refcnt));
1732 * Find existing push vlan resource or create and register a new one.
1734 * @param dev[in, out]
1735 * Pointer to rte_eth_dev structure.
1736 * @param[in, out] resource
1737 * Pointer to port ID action resource.
1738 * @parm[in, out] dev_flow
1739 * Pointer to the dev_flow.
1741 * pointer to error structure.
1744 * 0 on success otherwise -errno and errno is set.
1747 flow_dv_push_vlan_action_resource_register
1748 (struct rte_eth_dev *dev,
1749 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1750 struct mlx5_flow *dev_flow,
1751 struct rte_flow_error *error)
1753 struct mlx5_priv *priv = dev->data->dev_private;
1754 struct mlx5_ibv_shared *sh = priv->sh;
1755 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1756 struct mlx5dv_dr_domain *domain;
1758 /* Lookup a matching resource from cache. */
1759 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1760 if (resource->vlan_tag == cache_resource->vlan_tag &&
1761 resource->ft_type == cache_resource->ft_type) {
1762 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1764 (void *)cache_resource,
1765 rte_atomic32_read(&cache_resource->refcnt));
1766 rte_atomic32_inc(&cache_resource->refcnt);
1767 dev_flow->dv.push_vlan_res = cache_resource;
1771 /* Register new push_vlan action resource. */
1772 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1773 if (!cache_resource)
1774 return rte_flow_error_set(error, ENOMEM,
1775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1776 "cannot allocate resource memory");
1777 *cache_resource = *resource;
1778 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1779 domain = sh->fdb_domain;
1780 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1781 domain = sh->rx_domain;
1783 domain = sh->tx_domain;
1784 cache_resource->action =
1785 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1786 resource->vlan_tag);
1787 if (!cache_resource->action) {
1788 rte_free(cache_resource);
1789 return rte_flow_error_set(error, ENOMEM,
1790 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1791 NULL, "cannot create action");
1793 rte_atomic32_init(&cache_resource->refcnt);
1794 rte_atomic32_inc(&cache_resource->refcnt);
1795 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1796 dev_flow->dv.push_vlan_res = cache_resource;
1797 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1798 (void *)cache_resource,
1799 rte_atomic32_read(&cache_resource->refcnt));
1803 * Get the size of specific rte_flow_item_type
1805 * @param[in] item_type
1806 * Tested rte_flow_item_type.
1809 * sizeof struct item_type, 0 if void or irrelevant.
1812 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1816 switch (item_type) {
1817 case RTE_FLOW_ITEM_TYPE_ETH:
1818 retval = sizeof(struct rte_flow_item_eth);
1820 case RTE_FLOW_ITEM_TYPE_VLAN:
1821 retval = sizeof(struct rte_flow_item_vlan);
1823 case RTE_FLOW_ITEM_TYPE_IPV4:
1824 retval = sizeof(struct rte_flow_item_ipv4);
1826 case RTE_FLOW_ITEM_TYPE_IPV6:
1827 retval = sizeof(struct rte_flow_item_ipv6);
1829 case RTE_FLOW_ITEM_TYPE_UDP:
1830 retval = sizeof(struct rte_flow_item_udp);
1832 case RTE_FLOW_ITEM_TYPE_TCP:
1833 retval = sizeof(struct rte_flow_item_tcp);
1835 case RTE_FLOW_ITEM_TYPE_VXLAN:
1836 retval = sizeof(struct rte_flow_item_vxlan);
1838 case RTE_FLOW_ITEM_TYPE_GRE:
1839 retval = sizeof(struct rte_flow_item_gre);
1841 case RTE_FLOW_ITEM_TYPE_NVGRE:
1842 retval = sizeof(struct rte_flow_item_nvgre);
1844 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1845 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1847 case RTE_FLOW_ITEM_TYPE_MPLS:
1848 retval = sizeof(struct rte_flow_item_mpls);
1850 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1858 #define MLX5_ENCAP_IPV4_VERSION 0x40
1859 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1860 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1861 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1862 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1863 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1864 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1867 * Convert the encap action data from list of rte_flow_item to raw buffer
1870 * Pointer to rte_flow_item objects list.
1872 * Pointer to the output buffer.
1874 * Pointer to the output buffer size.
1876 * Pointer to the error structure.
1879 * 0 on success, a negative errno value otherwise and rte_errno is set.
1882 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1883 size_t *size, struct rte_flow_error *error)
1885 struct rte_ether_hdr *eth = NULL;
1886 struct rte_vlan_hdr *vlan = NULL;
1887 struct rte_ipv4_hdr *ipv4 = NULL;
1888 struct rte_ipv6_hdr *ipv6 = NULL;
1889 struct rte_udp_hdr *udp = NULL;
1890 struct rte_vxlan_hdr *vxlan = NULL;
1891 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1892 struct rte_gre_hdr *gre = NULL;
1894 size_t temp_size = 0;
1897 return rte_flow_error_set(error, EINVAL,
1898 RTE_FLOW_ERROR_TYPE_ACTION,
1899 NULL, "invalid empty data");
1900 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1901 len = flow_dv_get_item_len(items->type);
1902 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1903 return rte_flow_error_set(error, EINVAL,
1904 RTE_FLOW_ERROR_TYPE_ACTION,
1905 (void *)items->type,
1906 "items total size is too big"
1907 " for encap action");
1908 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1909 switch (items->type) {
1910 case RTE_FLOW_ITEM_TYPE_ETH:
1911 eth = (struct rte_ether_hdr *)&buf[temp_size];
1913 case RTE_FLOW_ITEM_TYPE_VLAN:
1914 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1916 return rte_flow_error_set(error, EINVAL,
1917 RTE_FLOW_ERROR_TYPE_ACTION,
1918 (void *)items->type,
1919 "eth header not found");
1920 if (!eth->ether_type)
1921 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1923 case RTE_FLOW_ITEM_TYPE_IPV4:
1924 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1926 return rte_flow_error_set(error, EINVAL,
1927 RTE_FLOW_ERROR_TYPE_ACTION,
1928 (void *)items->type,
1929 "neither eth nor vlan"
1931 if (vlan && !vlan->eth_proto)
1932 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1933 else if (eth && !eth->ether_type)
1934 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1935 if (!ipv4->version_ihl)
1936 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1937 MLX5_ENCAP_IPV4_IHL_MIN;
1938 if (!ipv4->time_to_live)
1939 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1941 case RTE_FLOW_ITEM_TYPE_IPV6:
1942 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1944 return rte_flow_error_set(error, EINVAL,
1945 RTE_FLOW_ERROR_TYPE_ACTION,
1946 (void *)items->type,
1947 "neither eth nor vlan"
1949 if (vlan && !vlan->eth_proto)
1950 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1951 else if (eth && !eth->ether_type)
1952 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1953 if (!ipv6->vtc_flow)
1955 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1956 if (!ipv6->hop_limits)
1957 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1959 case RTE_FLOW_ITEM_TYPE_UDP:
1960 udp = (struct rte_udp_hdr *)&buf[temp_size];
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ACTION,
1964 (void *)items->type,
1965 "ip header not found");
1966 if (ipv4 && !ipv4->next_proto_id)
1967 ipv4->next_proto_id = IPPROTO_UDP;
1968 else if (ipv6 && !ipv6->proto)
1969 ipv6->proto = IPPROTO_UDP;
1971 case RTE_FLOW_ITEM_TYPE_VXLAN:
1972 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1974 return rte_flow_error_set(error, EINVAL,
1975 RTE_FLOW_ERROR_TYPE_ACTION,
1976 (void *)items->type,
1977 "udp header not found");
1979 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1980 if (!vxlan->vx_flags)
1982 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1984 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1985 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1987 return rte_flow_error_set(error, EINVAL,
1988 RTE_FLOW_ERROR_TYPE_ACTION,
1989 (void *)items->type,
1990 "udp header not found");
1991 if (!vxlan_gpe->proto)
1992 return rte_flow_error_set(error, EINVAL,
1993 RTE_FLOW_ERROR_TYPE_ACTION,
1994 (void *)items->type,
1995 "next protocol not found");
1998 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1999 if (!vxlan_gpe->vx_flags)
2000 vxlan_gpe->vx_flags =
2001 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2003 case RTE_FLOW_ITEM_TYPE_GRE:
2004 case RTE_FLOW_ITEM_TYPE_NVGRE:
2005 gre = (struct rte_gre_hdr *)&buf[temp_size];
2007 return rte_flow_error_set(error, EINVAL,
2008 RTE_FLOW_ERROR_TYPE_ACTION,
2009 (void *)items->type,
2010 "next protocol not found");
2012 return rte_flow_error_set(error, EINVAL,
2013 RTE_FLOW_ERROR_TYPE_ACTION,
2014 (void *)items->type,
2015 "ip header not found");
2016 if (ipv4 && !ipv4->next_proto_id)
2017 ipv4->next_proto_id = IPPROTO_GRE;
2018 else if (ipv6 && !ipv6->proto)
2019 ipv6->proto = IPPROTO_GRE;
2021 case RTE_FLOW_ITEM_TYPE_VOID:
2024 return rte_flow_error_set(error, EINVAL,
2025 RTE_FLOW_ERROR_TYPE_ACTION,
2026 (void *)items->type,
2027 "unsupported item type");
2037 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2039 struct rte_ether_hdr *eth = NULL;
2040 struct rte_vlan_hdr *vlan = NULL;
2041 struct rte_ipv6_hdr *ipv6 = NULL;
2042 struct rte_udp_hdr *udp = NULL;
2046 eth = (struct rte_ether_hdr *)data;
2047 next_hdr = (char *)(eth + 1);
2048 proto = RTE_BE16(eth->ether_type);
2051 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2052 vlan = (struct rte_vlan_hdr *)next_hdr;
2053 proto = RTE_BE16(vlan->eth_proto);
2054 next_hdr += sizeof(struct rte_vlan_hdr);
2057 /* HW calculates IPv4 csum. no need to proceed */
2058 if (proto == RTE_ETHER_TYPE_IPV4)
2061 /* non IPv4/IPv6 header. not supported */
2062 if (proto != RTE_ETHER_TYPE_IPV6) {
2063 return rte_flow_error_set(error, ENOTSUP,
2064 RTE_FLOW_ERROR_TYPE_ACTION,
2065 NULL, "Cannot offload non IPv4/IPv6");
2068 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2070 /* ignore non UDP */
2071 if (ipv6->proto != IPPROTO_UDP)
2074 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2075 udp->dgram_cksum = 0;
2081 * Convert L2 encap action to DV specification.
2084 * Pointer to rte_eth_dev structure.
2086 * Pointer to action structure.
2087 * @param[in, out] dev_flow
2088 * Pointer to the mlx5_flow.
2089 * @param[in] transfer
2090 * Mark if the flow is E-Switch flow.
2092 * Pointer to the error structure.
2095 * 0 on success, a negative errno value otherwise and rte_errno is set.
2098 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2099 const struct rte_flow_action *action,
2100 struct mlx5_flow *dev_flow,
2102 struct rte_flow_error *error)
2104 const struct rte_flow_item *encap_data;
2105 const struct rte_flow_action_raw_encap *raw_encap_data;
2106 struct mlx5_flow_dv_encap_decap_resource res = {
2108 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2109 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2110 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2113 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2115 (const struct rte_flow_action_raw_encap *)action->conf;
2116 res.size = raw_encap_data->size;
2117 memcpy(res.buf, raw_encap_data->data, res.size);
2118 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2121 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2123 ((const struct rte_flow_action_vxlan_encap *)
2124 action->conf)->definition;
2127 ((const struct rte_flow_action_nvgre_encap *)
2128 action->conf)->definition;
2129 if (flow_dv_convert_encap_data(encap_data, res.buf,
2133 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2134 return rte_flow_error_set(error, EINVAL,
2135 RTE_FLOW_ERROR_TYPE_ACTION,
2136 NULL, "can't create L2 encap action");
2141 * Convert L2 decap action to DV specification.
2144 * Pointer to rte_eth_dev structure.
2145 * @param[in, out] dev_flow
2146 * Pointer to the mlx5_flow.
2147 * @param[in] transfer
2148 * Mark if the flow is E-Switch flow.
2150 * Pointer to the error structure.
2153 * 0 on success, a negative errno value otherwise and rte_errno is set.
2156 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2157 struct mlx5_flow *dev_flow,
2159 struct rte_flow_error *error)
2161 struct mlx5_flow_dv_encap_decap_resource res = {
2164 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2165 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2166 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2169 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2170 return rte_flow_error_set(error, EINVAL,
2171 RTE_FLOW_ERROR_TYPE_ACTION,
2172 NULL, "can't create L2 decap action");
2177 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2180 * Pointer to rte_eth_dev structure.
2182 * Pointer to action structure.
2183 * @param[in, out] dev_flow
2184 * Pointer to the mlx5_flow.
2186 * Pointer to the flow attributes.
2188 * Pointer to the error structure.
2191 * 0 on success, a negative errno value otherwise and rte_errno is set.
2194 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2195 const struct rte_flow_action *action,
2196 struct mlx5_flow *dev_flow,
2197 const struct rte_flow_attr *attr,
2198 struct rte_flow_error *error)
2200 const struct rte_flow_action_raw_encap *encap_data;
2201 struct mlx5_flow_dv_encap_decap_resource res;
2203 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2204 res.size = encap_data->size;
2205 memcpy(res.buf, encap_data->data, res.size);
2206 res.reformat_type = attr->egress ?
2207 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2208 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2210 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2212 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2213 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2214 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2215 return rte_flow_error_set(error, EINVAL,
2216 RTE_FLOW_ERROR_TYPE_ACTION,
2217 NULL, "can't create encap action");
2222 * Create action push VLAN.
2225 * Pointer to rte_eth_dev structure.
2226 * @param[in] vlan_tag
2227 * the vlan tag to push to the Ethernet header.
2228 * @param[in, out] dev_flow
2229 * Pointer to the mlx5_flow.
2231 * Pointer to the flow attributes.
2233 * Pointer to the error structure.
2236 * 0 on success, a negative errno value otherwise and rte_errno is set.
2239 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2240 const struct rte_flow_attr *attr,
2241 const struct rte_vlan_hdr *vlan,
2242 struct mlx5_flow *dev_flow,
2243 struct rte_flow_error *error)
2245 struct mlx5_flow_dv_push_vlan_action_resource res;
2248 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2251 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2253 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2254 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2255 return flow_dv_push_vlan_action_resource_register
2256 (dev, &res, dev_flow, error);
2260 * Validate the modify-header actions.
2262 * @param[in] action_flags
2263 * Holds the actions detected until now.
2265 * Pointer to the modify action.
2267 * Pointer to error structure.
2270 * 0 on success, a negative errno value otherwise and rte_errno is set.
2273 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2274 const struct rte_flow_action *action,
2275 struct rte_flow_error *error)
2277 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2278 return rte_flow_error_set(error, EINVAL,
2279 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2280 NULL, "action configuration not set");
2281 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2284 "can't have encap action before"
2290 * Validate the modify-header MAC address actions.
2292 * @param[in] action_flags
2293 * Holds the actions detected until now.
2295 * Pointer to the modify action.
2296 * @param[in] item_flags
2297 * Holds the items detected.
2299 * Pointer to error structure.
2302 * 0 on success, a negative errno value otherwise and rte_errno is set.
2305 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2306 const struct rte_flow_action *action,
2307 const uint64_t item_flags,
2308 struct rte_flow_error *error)
2312 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2314 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2315 return rte_flow_error_set(error, EINVAL,
2316 RTE_FLOW_ERROR_TYPE_ACTION,
2318 "no L2 item in pattern");
2324 * Validate the modify-header IPv4 address actions.
2326 * @param[in] action_flags
2327 * Holds the actions detected until now.
2329 * Pointer to the modify action.
2330 * @param[in] item_flags
2331 * Holds the items detected.
2333 * Pointer to error structure.
2336 * 0 on success, a negative errno value otherwise and rte_errno is set.
2339 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2340 const struct rte_flow_action *action,
2341 const uint64_t item_flags,
2342 struct rte_flow_error *error)
2346 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2348 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2349 return rte_flow_error_set(error, EINVAL,
2350 RTE_FLOW_ERROR_TYPE_ACTION,
2352 "no ipv4 item in pattern");
2358 * Validate the modify-header IPv6 address actions.
2360 * @param[in] action_flags
2361 * Holds the actions detected until now.
2363 * Pointer to the modify action.
2364 * @param[in] item_flags
2365 * Holds the items detected.
2367 * Pointer to error structure.
2370 * 0 on success, a negative errno value otherwise and rte_errno is set.
2373 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2374 const struct rte_flow_action *action,
2375 const uint64_t item_flags,
2376 struct rte_flow_error *error)
2380 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2382 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2383 return rte_flow_error_set(error, EINVAL,
2384 RTE_FLOW_ERROR_TYPE_ACTION,
2386 "no ipv6 item in pattern");
2392 * Validate the modify-header TP actions.
2394 * @param[in] action_flags
2395 * Holds the actions detected until now.
2397 * Pointer to the modify action.
2398 * @param[in] item_flags
2399 * Holds the items detected.
2401 * Pointer to error structure.
2404 * 0 on success, a negative errno value otherwise and rte_errno is set.
2407 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2408 const struct rte_flow_action *action,
2409 const uint64_t item_flags,
2410 struct rte_flow_error *error)
2414 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2416 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2417 return rte_flow_error_set(error, EINVAL,
2418 RTE_FLOW_ERROR_TYPE_ACTION,
2419 NULL, "no transport layer "
2426 * Validate the modify-header actions of increment/decrement
2427 * TCP Sequence-number.
2429 * @param[in] action_flags
2430 * Holds the actions detected until now.
2432 * Pointer to the modify action.
2433 * @param[in] item_flags
2434 * Holds the items detected.
2436 * Pointer to error structure.
2439 * 0 on success, a negative errno value otherwise and rte_errno is set.
2442 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2443 const struct rte_flow_action *action,
2444 const uint64_t item_flags,
2445 struct rte_flow_error *error)
2449 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2451 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2452 return rte_flow_error_set(error, EINVAL,
2453 RTE_FLOW_ERROR_TYPE_ACTION,
2454 NULL, "no TCP item in"
2456 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2457 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2458 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2459 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2460 return rte_flow_error_set(error, EINVAL,
2461 RTE_FLOW_ERROR_TYPE_ACTION,
2463 "cannot decrease and increase"
2464 " TCP sequence number"
2465 " at the same time");
2471 * Validate the modify-header actions of increment/decrement
2472 * TCP Acknowledgment number.
2474 * @param[in] action_flags
2475 * Holds the actions detected until now.
2477 * Pointer to the modify action.
2478 * @param[in] item_flags
2479 * Holds the items detected.
2481 * Pointer to error structure.
2484 * 0 on success, a negative errno value otherwise and rte_errno is set.
2487 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2488 const struct rte_flow_action *action,
2489 const uint64_t item_flags,
2490 struct rte_flow_error *error)
2494 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2496 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2497 return rte_flow_error_set(error, EINVAL,
2498 RTE_FLOW_ERROR_TYPE_ACTION,
2499 NULL, "no TCP item in"
2501 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2502 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2503 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2504 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2505 return rte_flow_error_set(error, EINVAL,
2506 RTE_FLOW_ERROR_TYPE_ACTION,
2508 "cannot decrease and increase"
2509 " TCP acknowledgment number"
2510 " at the same time");
2516 * Validate the modify-header TTL actions.
2518 * @param[in] action_flags
2519 * Holds the actions detected until now.
2521 * Pointer to the modify action.
2522 * @param[in] item_flags
2523 * Holds the items detected.
2525 * Pointer to error structure.
2528 * 0 on success, a negative errno value otherwise and rte_errno is set.
2531 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2532 const struct rte_flow_action *action,
2533 const uint64_t item_flags,
2534 struct rte_flow_error *error)
2538 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2540 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2541 return rte_flow_error_set(error, EINVAL,
2542 RTE_FLOW_ERROR_TYPE_ACTION,
2544 "no IP protocol in pattern");
2550 * Validate jump action.
2553 * Pointer to the jump action.
2554 * @param[in] action_flags
2555 * Holds the actions detected until now.
2556 * @param[in] attributes
2557 * Pointer to flow attributes
2558 * @param[in] external
2559 * Action belongs to flow rule created by request external to PMD.
2561 * Pointer to error structure.
2564 * 0 on success, a negative errno value otherwise and rte_errno is set.
2567 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2568 uint64_t action_flags,
2569 const struct rte_flow_attr *attributes,
2570 bool external, struct rte_flow_error *error)
2572 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2574 uint32_t target_group, table;
2577 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2578 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2579 return rte_flow_error_set(error, EINVAL,
2580 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2581 "can't have 2 fate actions in"
2584 return rte_flow_error_set(error, EINVAL,
2585 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2586 NULL, "action configuration not set");
2588 ((const struct rte_flow_action_jump *)action->conf)->group;
2589 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2593 if (table >= max_group)
2594 return rte_flow_error_set(error, EINVAL,
2595 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2596 "target group index out of range");
2597 if (attributes->group >= target_group)
2598 return rte_flow_error_set(error, EINVAL,
2599 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2600 "target group must be higher than"
2601 " the current flow group");
2606 * Validate the port_id action.
2609 * Pointer to rte_eth_dev structure.
2610 * @param[in] action_flags
2611 * Bit-fields that holds the actions detected until now.
2613 * Port_id RTE action structure.
2615 * Attributes of flow that includes this action.
2617 * Pointer to error structure.
2620 * 0 on success, a negative errno value otherwise and rte_errno is set.
2623 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2624 uint64_t action_flags,
2625 const struct rte_flow_action *action,
2626 const struct rte_flow_attr *attr,
2627 struct rte_flow_error *error)
2629 const struct rte_flow_action_port_id *port_id;
2630 struct mlx5_priv *act_priv;
2631 struct mlx5_priv *dev_priv;
2634 if (!attr->transfer)
2635 return rte_flow_error_set(error, ENOTSUP,
2636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2638 "port id action is valid in transfer"
2640 if (!action || !action->conf)
2641 return rte_flow_error_set(error, ENOTSUP,
2642 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2644 "port id action parameters must be"
2646 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2647 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2648 return rte_flow_error_set(error, EINVAL,
2649 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2650 "can have only one fate actions in"
2652 dev_priv = mlx5_dev_to_eswitch_info(dev);
2654 return rte_flow_error_set(error, rte_errno,
2655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2657 "failed to obtain E-Switch info");
2658 port_id = action->conf;
2659 port = port_id->original ? dev->data->port_id : port_id->id;
2660 act_priv = mlx5_port_to_eswitch_info(port);
2662 return rte_flow_error_set
2664 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2665 "failed to obtain E-Switch port id for port");
2666 if (act_priv->domain_id != dev_priv->domain_id)
2667 return rte_flow_error_set
2669 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2670 "port does not belong to"
2671 " E-Switch being configured");
2676 * Find existing modify-header resource or create and register a new one.
2678 * @param dev[in, out]
2679 * Pointer to rte_eth_dev structure.
2680 * @param[in, out] resource
2681 * Pointer to modify-header resource.
2682 * @parm[in, out] dev_flow
2683 * Pointer to the dev_flow.
2685 * pointer to error structure.
2688 * 0 on success otherwise -errno and errno is set.
2691 flow_dv_modify_hdr_resource_register
2692 (struct rte_eth_dev *dev,
2693 struct mlx5_flow_dv_modify_hdr_resource *resource,
2694 struct mlx5_flow *dev_flow,
2695 struct rte_flow_error *error)
2697 struct mlx5_priv *priv = dev->data->dev_private;
2698 struct mlx5_ibv_shared *sh = priv->sh;
2699 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2700 struct mlx5dv_dr_domain *ns;
2702 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2703 ns = sh->fdb_domain;
2704 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2709 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2710 /* Lookup a matching resource from cache. */
2711 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2712 if (resource->ft_type == cache_resource->ft_type &&
2713 resource->actions_num == cache_resource->actions_num &&
2714 resource->flags == cache_resource->flags &&
2715 !memcmp((const void *)resource->actions,
2716 (const void *)cache_resource->actions,
2717 (resource->actions_num *
2718 sizeof(resource->actions[0])))) {
2719 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2720 (void *)cache_resource,
2721 rte_atomic32_read(&cache_resource->refcnt));
2722 rte_atomic32_inc(&cache_resource->refcnt);
2723 dev_flow->dv.modify_hdr = cache_resource;
2727 /* Register new modify-header resource. */
2728 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2729 if (!cache_resource)
2730 return rte_flow_error_set(error, ENOMEM,
2731 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2732 "cannot allocate resource memory");
2733 *cache_resource = *resource;
2734 cache_resource->verbs_action =
2735 mlx5_glue->dv_create_flow_action_modify_header
2736 (sh->ctx, cache_resource->ft_type,
2737 ns, cache_resource->flags,
2738 cache_resource->actions_num *
2739 sizeof(cache_resource->actions[0]),
2740 (uint64_t *)cache_resource->actions);
2741 if (!cache_resource->verbs_action) {
2742 rte_free(cache_resource);
2743 return rte_flow_error_set(error, ENOMEM,
2744 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2745 NULL, "cannot create action");
2747 rte_atomic32_init(&cache_resource->refcnt);
2748 rte_atomic32_inc(&cache_resource->refcnt);
2749 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2750 dev_flow->dv.modify_hdr = cache_resource;
2751 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2752 (void *)cache_resource,
2753 rte_atomic32_read(&cache_resource->refcnt));
2757 #define MLX5_CNT_CONTAINER_RESIZE 64
2760 * Get or create a flow counter.
2763 * Pointer to the Ethernet device structure.
2765 * Indicate if this counter is shared with other flows.
2767 * Counter identifier.
2770 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2772 static struct mlx5_flow_counter *
2773 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2776 struct mlx5_priv *priv = dev->data->dev_private;
2777 struct mlx5_flow_counter *cnt = NULL;
2778 struct mlx5_devx_obj *dcs = NULL;
2780 if (!priv->config.devx) {
2781 rte_errno = ENOTSUP;
2785 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2786 if (cnt->shared && cnt->id == id) {
2792 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2795 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2797 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2801 struct mlx5_flow_counter tmpl = {
2807 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2809 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2815 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2820 * Release a flow counter.
2823 * Pointer to the Ethernet device structure.
2824 * @param[in] counter
2825 * Pointer to the counter handler.
2828 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2829 struct mlx5_flow_counter *counter)
2831 struct mlx5_priv *priv = dev->data->dev_private;
2835 if (--counter->ref_cnt == 0) {
2836 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2837 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2843 * Query a devx flow counter.
2846 * Pointer to the Ethernet device structure.
2848 * Pointer to the flow counter.
2850 * The statistics value of packets.
2852 * The statistics value of bytes.
2855 * 0 on success, otherwise a negative errno value and rte_errno is set.
2858 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2859 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2862 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2867 * Get a pool by a counter.
2870 * Pointer to the counter.
2875 static struct mlx5_flow_counter_pool *
2876 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2879 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2880 return (struct mlx5_flow_counter_pool *)cnt - 1;
2886 * Get a pool by devx counter ID.
2889 * Pointer to the counter container.
2891 * The counter devx ID.
2894 * The counter pool pointer if exists, NULL otherwise,
2896 static struct mlx5_flow_counter_pool *
2897 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2899 struct mlx5_flow_counter_pool *pool;
2901 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2902 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2903 MLX5_COUNTERS_PER_POOL;
2905 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2912 * Allocate a new memory for the counter values wrapped by all the needed
2916 * Pointer to the Ethernet device structure.
2918 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2921 * The new memory management pointer on success, otherwise NULL and rte_errno
2924 static struct mlx5_counter_stats_mem_mng *
2925 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2927 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2928 (dev->data->dev_private))->sh;
2929 struct mlx5_devx_mkey_attr mkey_attr;
2930 struct mlx5_counter_stats_mem_mng *mem_mng;
2931 volatile struct flow_counter_stats *raw_data;
2932 int size = (sizeof(struct flow_counter_stats) *
2933 MLX5_COUNTERS_PER_POOL +
2934 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2935 sizeof(struct mlx5_counter_stats_mem_mng);
2936 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2943 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2944 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2945 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2946 IBV_ACCESS_LOCAL_WRITE);
2947 if (!mem_mng->umem) {
2952 mkey_attr.addr = (uintptr_t)mem;
2953 mkey_attr.size = size;
2954 mkey_attr.umem_id = mem_mng->umem->umem_id;
2955 mkey_attr.pd = sh->pdn;
2956 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2958 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2963 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2964 raw_data = (volatile struct flow_counter_stats *)mem;
2965 for (i = 0; i < raws_n; ++i) {
2966 mem_mng->raws[i].mem_mng = mem_mng;
2967 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2969 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2974 * Resize a counter container.
2977 * Pointer to the Ethernet device structure.
2979 * Whether the pool is for counter that was allocated by batch command.
2982 * The new container pointer on success, otherwise NULL and rte_errno is set.
2984 static struct mlx5_pools_container *
2985 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2987 struct mlx5_priv *priv = dev->data->dev_private;
2988 struct mlx5_pools_container *cont =
2989 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2990 struct mlx5_pools_container *new_cont =
2991 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2992 struct mlx5_counter_stats_mem_mng *mem_mng;
2993 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2994 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2997 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2998 /* The last resize still hasn't detected by the host thread. */
3002 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3003 if (!new_cont->pools) {
3008 memcpy(new_cont->pools, cont->pools, cont->n *
3009 sizeof(struct mlx5_flow_counter_pool *));
3010 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3011 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3013 rte_free(new_cont->pools);
3016 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3017 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3018 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3020 new_cont->n = resize;
3021 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3022 TAILQ_INIT(&new_cont->pool_list);
3023 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3024 new_cont->init_mem_mng = mem_mng;
3026 /* Flip the master container. */
3027 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3032 * Query a devx flow counter.
3035 * Pointer to the Ethernet device structure.
3037 * Pointer to the flow counter.
3039 * The statistics value of packets.
3041 * The statistics value of bytes.
3044 * 0 on success, otherwise a negative errno value and rte_errno is set.
3047 _flow_dv_query_count(struct rte_eth_dev *dev,
3048 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3051 struct mlx5_priv *priv = dev->data->dev_private;
3052 struct mlx5_flow_counter_pool *pool =
3053 flow_dv_counter_pool_get(cnt);
3054 int offset = cnt - &pool->counters_raw[0];
3056 if (priv->counter_fallback)
3057 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3059 rte_spinlock_lock(&pool->sl);
3061 * The single counters allocation may allocate smaller ID than the
3062 * current allocated in parallel to the host reading.
3063 * In this case the new counter values must be reported as 0.
3065 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3069 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3070 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3072 rte_spinlock_unlock(&pool->sl);
3077 * Create and initialize a new counter pool.
3080 * Pointer to the Ethernet device structure.
3082 * The devX counter handle.
3084 * Whether the pool is for counter that was allocated by batch command.
3087 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3089 static struct mlx5_flow_counter_pool *
3090 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3093 struct mlx5_priv *priv = dev->data->dev_private;
3094 struct mlx5_flow_counter_pool *pool;
3095 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3097 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3100 if (cont->n == n_valid) {
3101 cont = flow_dv_container_resize(dev, batch);
3105 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3106 sizeof(struct mlx5_flow_counter);
3107 pool = rte_calloc(__func__, 1, size, 0);
3112 pool->min_dcs = dcs;
3113 pool->raw = cont->init_mem_mng->raws + n_valid %
3114 MLX5_CNT_CONTAINER_RESIZE;
3115 pool->raw_hw = NULL;
3116 rte_spinlock_init(&pool->sl);
3118 * The generation of the new allocated counters in this pool is 0, 2 in
3119 * the pool generation makes all the counters valid for allocation.
3121 rte_atomic64_set(&pool->query_gen, 0x2);
3122 TAILQ_INIT(&pool->counters);
3123 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3124 cont->pools[n_valid] = pool;
3125 /* Pool initialization must be updated before host thread access. */
3127 rte_atomic16_add(&cont->n_valid, 1);
3132 * Prepare a new counter and/or a new counter pool.
3135 * Pointer to the Ethernet device structure.
3136 * @param[out] cnt_free
3137 * Where to put the pointer of a new counter.
3139 * Whether the pool is for counter that was allocated by batch command.
3142 * The free counter pool pointer and @p cnt_free is set on success,
3143 * NULL otherwise and rte_errno is set.
3145 static struct mlx5_flow_counter_pool *
3146 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3147 struct mlx5_flow_counter **cnt_free,
3150 struct mlx5_priv *priv = dev->data->dev_private;
3151 struct mlx5_flow_counter_pool *pool;
3152 struct mlx5_devx_obj *dcs = NULL;
3153 struct mlx5_flow_counter *cnt;
3157 /* bulk_bitmap must be 0 for single counter allocation. */
3158 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3161 pool = flow_dv_find_pool_by_id
3162 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3164 pool = flow_dv_pool_create(dev, dcs, batch);
3166 mlx5_devx_cmd_destroy(dcs);
3169 } else if (dcs->id < pool->min_dcs->id) {
3170 rte_atomic64_set(&pool->a64_dcs,
3171 (int64_t)(uintptr_t)dcs);
3173 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3174 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3179 /* bulk_bitmap is in 128 counters units. */
3180 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3181 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3183 rte_errno = ENODATA;
3186 pool = flow_dv_pool_create(dev, dcs, batch);
3188 mlx5_devx_cmd_destroy(dcs);
3191 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3192 cnt = &pool->counters_raw[i];
3194 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3196 *cnt_free = &pool->counters_raw[0];
3201 * Search for existed shared counter.
3204 * Pointer to the relevant counter pool container.
3206 * The shared counter ID to search.
3209 * NULL if not existed, otherwise pointer to the shared counter.
3211 static struct mlx5_flow_counter *
3212 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3215 static struct mlx5_flow_counter *cnt;
3216 struct mlx5_flow_counter_pool *pool;
3219 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3220 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3221 cnt = &pool->counters_raw[i];
3222 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3230 * Allocate a flow counter.
3233 * Pointer to the Ethernet device structure.
3235 * Indicate if this counter is shared with other flows.
3237 * Counter identifier.
3239 * Counter flow group.
3242 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3244 static struct mlx5_flow_counter *
3245 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3248 struct mlx5_priv *priv = dev->data->dev_private;
3249 struct mlx5_flow_counter_pool *pool = NULL;
3250 struct mlx5_flow_counter *cnt_free = NULL;
3252 * Currently group 0 flow counter cannot be assigned to a flow if it is
3253 * not the first one in the batch counter allocation, so it is better
3254 * to allocate counters one by one for these flows in a separate
3256 * A counter can be shared between different groups so need to take
3257 * shared counters from the single container.
3259 uint32_t batch = (group && !shared) ? 1 : 0;
3260 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3263 if (priv->counter_fallback)
3264 return flow_dv_counter_alloc_fallback(dev, shared, id);
3265 if (!priv->config.devx) {
3266 rte_errno = ENOTSUP;
3270 cnt_free = flow_dv_counter_shared_search(cont, id);
3272 if (cnt_free->ref_cnt + 1 == 0) {
3276 cnt_free->ref_cnt++;
3280 /* Pools which has a free counters are in the start. */
3281 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3283 * The free counter reset values must be updated between the
3284 * counter release to the counter allocation, so, at least one
3285 * query must be done in this time. ensure it by saving the
3286 * query generation in the release time.
3287 * The free list is sorted according to the generation - so if
3288 * the first one is not updated, all the others are not
3291 cnt_free = TAILQ_FIRST(&pool->counters);
3292 if (cnt_free && cnt_free->query_gen + 1 <
3293 rte_atomic64_read(&pool->query_gen))
3298 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3302 cnt_free->batch = batch;
3303 /* Create a DV counter action only in the first time usage. */
3304 if (!cnt_free->action) {
3306 struct mlx5_devx_obj *dcs;
3309 offset = cnt_free - &pool->counters_raw[0];
3310 dcs = pool->min_dcs;
3313 dcs = cnt_free->dcs;
3315 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3317 if (!cnt_free->action) {
3322 /* Update the counter reset values. */
3323 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3326 cnt_free->shared = shared;
3327 cnt_free->ref_cnt = 1;
3329 if (!priv->sh->cmng.query_thread_on)
3330 /* Start the asynchronous batch query by the host thread. */
3331 mlx5_set_query_alarm(priv->sh);
3332 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3333 if (TAILQ_EMPTY(&pool->counters)) {
3334 /* Move the pool to the end of the container pool list. */
3335 TAILQ_REMOVE(&cont->pool_list, pool, next);
3336 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3342 * Release a flow counter.
3345 * Pointer to the Ethernet device structure.
3346 * @param[in] counter
3347 * Pointer to the counter handler.
3350 flow_dv_counter_release(struct rte_eth_dev *dev,
3351 struct mlx5_flow_counter *counter)
3353 struct mlx5_priv *priv = dev->data->dev_private;
3357 if (priv->counter_fallback) {
3358 flow_dv_counter_release_fallback(dev, counter);
3361 if (--counter->ref_cnt == 0) {
3362 struct mlx5_flow_counter_pool *pool =
3363 flow_dv_counter_pool_get(counter);
3365 /* Put the counter in the end - the last updated one. */
3366 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3367 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3372 * Verify the @p attributes will be correctly understood by the NIC and store
3373 * them in the @p flow if everything is correct.
3376 * Pointer to dev struct.
3377 * @param[in] attributes
3378 * Pointer to flow attributes
3379 * @param[in] external
3380 * This flow rule is created by request external to PMD.
3382 * Pointer to error structure.
3385 * 0 on success, a negative errno value otherwise and rte_errno is set.
3388 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3389 const struct rte_flow_attr *attributes,
3390 bool external __rte_unused,
3391 struct rte_flow_error *error)
3393 struct mlx5_priv *priv = dev->data->dev_private;
3394 uint32_t priority_max = priv->config.flow_prio - 1;
3396 #ifndef HAVE_MLX5DV_DR
3397 if (attributes->group)
3398 return rte_flow_error_set(error, ENOTSUP,
3399 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3401 "groups are not supported");
3403 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3408 ret = mlx5_flow_group_to_table(attributes, external,
3413 if (table >= max_group)
3414 return rte_flow_error_set(error, EINVAL,
3415 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3416 "group index out of range");
3418 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3419 attributes->priority >= priority_max)
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3423 "priority out of range");
3424 if (attributes->transfer) {
3425 if (!priv->config.dv_esw_en)
3426 return rte_flow_error_set
3428 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3429 "E-Switch dr is not supported");
3430 if (!(priv->representor || priv->master))
3431 return rte_flow_error_set
3432 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3433 NULL, "E-Switch configuration can only be"
3434 " done by a master or a representor device");
3435 if (attributes->egress)
3436 return rte_flow_error_set
3438 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3439 "egress is not supported");
3441 if (!(attributes->egress ^ attributes->ingress))
3442 return rte_flow_error_set(error, ENOTSUP,
3443 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3444 "must specify exactly one of "
3445 "ingress or egress");
3450 * Internal validation function. For validating both actions and items.
3453 * Pointer to the rte_eth_dev structure.
3455 * Pointer to the flow attributes.
3457 * Pointer to the list of items.
3458 * @param[in] actions
3459 * Pointer to the list of actions.
3460 * @param[in] external
3461 * This flow rule is created by request external to PMD.
3463 * Pointer to the error structure.
3466 * 0 on success, a negative errno value otherwise and rte_errno is set.
3469 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3470 const struct rte_flow_item items[],
3471 const struct rte_flow_action actions[],
3472 bool external, struct rte_flow_error *error)
3475 uint64_t action_flags = 0;
3476 uint64_t item_flags = 0;
3477 uint64_t last_item = 0;
3478 uint8_t next_protocol = 0xff;
3479 uint16_t ether_type = 0;
3481 const struct rte_flow_item *gre_item = NULL;
3482 struct rte_flow_item_tcp nic_tcp_mask = {
3485 .src_port = RTE_BE16(UINT16_MAX),
3486 .dst_port = RTE_BE16(UINT16_MAX),
3492 ret = flow_dv_validate_attributes(dev, attr, external, error);
3495 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3496 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3497 int type = items->type;
3500 case RTE_FLOW_ITEM_TYPE_VOID:
3502 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3503 ret = flow_dv_validate_item_port_id
3504 (dev, items, attr, item_flags, error);
3507 last_item = MLX5_FLOW_ITEM_PORT_ID;
3509 case RTE_FLOW_ITEM_TYPE_ETH:
3510 ret = mlx5_flow_validate_item_eth(items, item_flags,
3514 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3515 MLX5_FLOW_LAYER_OUTER_L2;
3516 if (items->mask != NULL && items->spec != NULL) {
3518 ((const struct rte_flow_item_eth *)
3521 ((const struct rte_flow_item_eth *)
3523 ether_type = rte_be_to_cpu_16(ether_type);
3528 case RTE_FLOW_ITEM_TYPE_VLAN:
3529 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3533 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3534 MLX5_FLOW_LAYER_OUTER_VLAN;
3535 if (items->mask != NULL && items->spec != NULL) {
3537 ((const struct rte_flow_item_vlan *)
3538 items->spec)->inner_type;
3540 ((const struct rte_flow_item_vlan *)
3541 items->mask)->inner_type;
3542 ether_type = rte_be_to_cpu_16(ether_type);
3547 case RTE_FLOW_ITEM_TYPE_IPV4:
3548 mlx5_flow_tunnel_ip_check(items, next_protocol,
3549 &item_flags, &tunnel);
3550 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3556 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3557 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3558 if (items->mask != NULL &&
3559 ((const struct rte_flow_item_ipv4 *)
3560 items->mask)->hdr.next_proto_id) {
3562 ((const struct rte_flow_item_ipv4 *)
3563 (items->spec))->hdr.next_proto_id;
3565 ((const struct rte_flow_item_ipv4 *)
3566 (items->mask))->hdr.next_proto_id;
3568 /* Reset for inner layer. */
3569 next_protocol = 0xff;
3572 case RTE_FLOW_ITEM_TYPE_IPV6:
3573 mlx5_flow_tunnel_ip_check(items, next_protocol,
3574 &item_flags, &tunnel);
3575 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3581 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3582 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3583 if (items->mask != NULL &&
3584 ((const struct rte_flow_item_ipv6 *)
3585 items->mask)->hdr.proto) {
3587 ((const struct rte_flow_item_ipv6 *)
3588 items->spec)->hdr.proto;
3590 ((const struct rte_flow_item_ipv6 *)
3591 items->mask)->hdr.proto;
3593 /* Reset for inner layer. */
3594 next_protocol = 0xff;
3597 case RTE_FLOW_ITEM_TYPE_TCP:
3598 ret = mlx5_flow_validate_item_tcp
3605 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3606 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3608 case RTE_FLOW_ITEM_TYPE_UDP:
3609 ret = mlx5_flow_validate_item_udp(items, item_flags,
3614 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3615 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3617 case RTE_FLOW_ITEM_TYPE_GRE:
3618 ret = mlx5_flow_validate_item_gre(items, item_flags,
3619 next_protocol, error);
3623 last_item = MLX5_FLOW_LAYER_GRE;
3625 case RTE_FLOW_ITEM_TYPE_NVGRE:
3626 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3631 last_item = MLX5_FLOW_LAYER_NVGRE;
3633 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3634 ret = mlx5_flow_validate_item_gre_key
3635 (items, item_flags, gre_item, error);
3638 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3640 case RTE_FLOW_ITEM_TYPE_VXLAN:
3641 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3645 last_item = MLX5_FLOW_LAYER_VXLAN;
3647 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3648 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3653 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3655 case RTE_FLOW_ITEM_TYPE_GENEVE:
3656 ret = mlx5_flow_validate_item_geneve(items,
3661 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3663 case RTE_FLOW_ITEM_TYPE_MPLS:
3664 ret = mlx5_flow_validate_item_mpls(dev, items,
3669 last_item = MLX5_FLOW_LAYER_MPLS;
3671 case RTE_FLOW_ITEM_TYPE_META:
3672 ret = flow_dv_validate_item_meta(dev, items, attr,
3676 last_item = MLX5_FLOW_ITEM_METADATA;
3678 case RTE_FLOW_ITEM_TYPE_ICMP:
3679 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3684 last_item = MLX5_FLOW_LAYER_ICMP;
3686 case RTE_FLOW_ITEM_TYPE_ICMP6:
3687 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3692 last_item = MLX5_FLOW_LAYER_ICMP6;
3694 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3695 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3698 return rte_flow_error_set(error, ENOTSUP,
3699 RTE_FLOW_ERROR_TYPE_ITEM,
3700 NULL, "item not supported");
3702 item_flags |= last_item;
3704 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3705 int type = actions->type;
3706 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3707 return rte_flow_error_set(error, ENOTSUP,
3708 RTE_FLOW_ERROR_TYPE_ACTION,
3709 actions, "too many actions");
3711 case RTE_FLOW_ACTION_TYPE_VOID:
3713 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3714 ret = flow_dv_validate_action_port_id(dev,
3721 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3724 case RTE_FLOW_ACTION_TYPE_FLAG:
3725 ret = mlx5_flow_validate_action_flag(action_flags,
3729 action_flags |= MLX5_FLOW_ACTION_FLAG;
3732 case RTE_FLOW_ACTION_TYPE_MARK:
3733 ret = mlx5_flow_validate_action_mark(actions,
3738 action_flags |= MLX5_FLOW_ACTION_MARK;
3741 case RTE_FLOW_ACTION_TYPE_DROP:
3742 ret = mlx5_flow_validate_action_drop(action_flags,
3746 action_flags |= MLX5_FLOW_ACTION_DROP;
3749 case RTE_FLOW_ACTION_TYPE_QUEUE:
3750 ret = mlx5_flow_validate_action_queue(actions,
3755 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3758 case RTE_FLOW_ACTION_TYPE_RSS:
3759 ret = mlx5_flow_validate_action_rss(actions,
3765 action_flags |= MLX5_FLOW_ACTION_RSS;
3768 case RTE_FLOW_ACTION_TYPE_COUNT:
3769 ret = flow_dv_validate_action_count(dev, error);
3772 action_flags |= MLX5_FLOW_ACTION_COUNT;
3775 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3776 if (flow_dv_validate_action_pop_vlan(dev,
3782 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3785 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3786 ret = flow_dv_validate_action_push_vlan(action_flags,
3792 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3795 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3796 ret = flow_dv_validate_action_set_vlan_pcp
3797 (action_flags, actions, error);
3800 /* Count PCP with push_vlan command. */
3801 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3803 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3804 ret = flow_dv_validate_action_set_vlan_vid
3805 (item_flags, action_flags,
3809 /* Count VID with push_vlan command. */
3810 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3812 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3813 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3814 ret = flow_dv_validate_action_l2_encap(action_flags,
3819 action_flags |= actions->type ==
3820 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3821 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3822 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3825 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3826 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3827 ret = flow_dv_validate_action_l2_decap(action_flags,
3831 action_flags |= actions->type ==
3832 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3833 MLX5_FLOW_ACTION_VXLAN_DECAP :
3834 MLX5_FLOW_ACTION_NVGRE_DECAP;
3837 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3838 ret = flow_dv_validate_action_raw_encap(action_flags,
3843 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3846 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3847 ret = flow_dv_validate_action_raw_decap(action_flags,
3852 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3855 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3856 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3857 ret = flow_dv_validate_action_modify_mac(action_flags,
3863 /* Count all modify-header actions as one action. */
3864 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3866 action_flags |= actions->type ==
3867 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3868 MLX5_FLOW_ACTION_SET_MAC_SRC :
3869 MLX5_FLOW_ACTION_SET_MAC_DST;
3872 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3873 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3874 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3880 /* Count all modify-header actions as one action. */
3881 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3883 action_flags |= actions->type ==
3884 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3885 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3886 MLX5_FLOW_ACTION_SET_IPV4_DST;
3888 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3889 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3890 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3896 /* Count all modify-header actions as one action. */
3897 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3899 action_flags |= actions->type ==
3900 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3901 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3902 MLX5_FLOW_ACTION_SET_IPV6_DST;
3904 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3905 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3906 ret = flow_dv_validate_action_modify_tp(action_flags,
3912 /* Count all modify-header actions as one action. */
3913 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3915 action_flags |= actions->type ==
3916 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3917 MLX5_FLOW_ACTION_SET_TP_SRC :
3918 MLX5_FLOW_ACTION_SET_TP_DST;
3920 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3921 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3922 ret = flow_dv_validate_action_modify_ttl(action_flags,
3928 /* Count all modify-header actions as one action. */
3929 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3931 action_flags |= actions->type ==
3932 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3933 MLX5_FLOW_ACTION_SET_TTL :
3934 MLX5_FLOW_ACTION_DEC_TTL;
3936 case RTE_FLOW_ACTION_TYPE_JUMP:
3937 ret = flow_dv_validate_action_jump(actions,
3944 action_flags |= MLX5_FLOW_ACTION_JUMP;
3946 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3947 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3948 ret = flow_dv_validate_action_modify_tcp_seq
3955 /* Count all modify-header actions as one action. */
3956 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3958 action_flags |= actions->type ==
3959 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3960 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3961 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3963 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3964 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3965 ret = flow_dv_validate_action_modify_tcp_ack
3972 /* Count all modify-header actions as one action. */
3973 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3975 action_flags |= actions->type ==
3976 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3977 MLX5_FLOW_ACTION_INC_TCP_ACK :
3978 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3980 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
3983 return rte_flow_error_set(error, ENOTSUP,
3984 RTE_FLOW_ERROR_TYPE_ACTION,
3986 "action not supported");
3989 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
3990 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
3991 return rte_flow_error_set(error, ENOTSUP,
3992 RTE_FLOW_ERROR_TYPE_ACTION,
3994 "can't have vxlan and vlan"
3995 " actions in the same rule");
3996 /* Eswitch has few restrictions on using items and actions */
3997 if (attr->transfer) {
3998 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3999 return rte_flow_error_set(error, ENOTSUP,
4000 RTE_FLOW_ERROR_TYPE_ACTION,
4002 "unsupported action FLAG");
4003 if (action_flags & MLX5_FLOW_ACTION_MARK)
4004 return rte_flow_error_set(error, ENOTSUP,
4005 RTE_FLOW_ERROR_TYPE_ACTION,
4007 "unsupported action MARK");
4008 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4009 return rte_flow_error_set(error, ENOTSUP,
4010 RTE_FLOW_ERROR_TYPE_ACTION,
4012 "unsupported action QUEUE");
4013 if (action_flags & MLX5_FLOW_ACTION_RSS)
4014 return rte_flow_error_set(error, ENOTSUP,
4015 RTE_FLOW_ERROR_TYPE_ACTION,
4017 "unsupported action RSS");
4018 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4019 return rte_flow_error_set(error, EINVAL,
4020 RTE_FLOW_ERROR_TYPE_ACTION,
4022 "no fate action is found");
4024 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4025 return rte_flow_error_set(error, EINVAL,
4026 RTE_FLOW_ERROR_TYPE_ACTION,
4028 "no fate action is found");
4034 * Internal preparation function. Allocates the DV flow size,
4035 * this size is constant.
4038 * Pointer to the flow attributes.
4040 * Pointer to the list of items.
4041 * @param[in] actions
4042 * Pointer to the list of actions.
4044 * Pointer to the error structure.
4047 * Pointer to mlx5_flow object on success,
4048 * otherwise NULL and rte_errno is set.
4050 static struct mlx5_flow *
4051 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4052 const struct rte_flow_item items[] __rte_unused,
4053 const struct rte_flow_action actions[] __rte_unused,
4054 struct rte_flow_error *error)
4056 uint32_t size = sizeof(struct mlx5_flow);
4057 struct mlx5_flow *flow;
4059 flow = rte_calloc(__func__, 1, size, 0);
4061 rte_flow_error_set(error, ENOMEM,
4062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4063 "not enough memory to create flow");
4066 flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4072 * Sanity check for match mask and value. Similar to check_valid_spec() in
4073 * kernel driver. If unmasked bit is present in value, it returns failure.
4076 * pointer to match mask buffer.
4077 * @param match_value
4078 * pointer to match value buffer.
4081 * 0 if valid, -EINVAL otherwise.
4084 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4086 uint8_t *m = match_mask;
4087 uint8_t *v = match_value;
4090 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4093 "match_value differs from match_criteria"
4094 " %p[%u] != %p[%u]",
4095 match_value, i, match_mask, i);
4104 * Add Ethernet item to matcher and to the value.
4106 * @param[in, out] matcher
4108 * @param[in, out] key
4109 * Flow matcher value.
4111 * Flow pattern to translate.
4113 * Item is inner pattern.
4116 flow_dv_translate_item_eth(void *matcher, void *key,
4117 const struct rte_flow_item *item, int inner)
4119 const struct rte_flow_item_eth *eth_m = item->mask;
4120 const struct rte_flow_item_eth *eth_v = item->spec;
4121 const struct rte_flow_item_eth nic_mask = {
4122 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4123 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4124 .type = RTE_BE16(0xffff),
4136 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4138 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4140 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4142 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4144 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4145 ð_m->dst, sizeof(eth_m->dst));
4146 /* The value must be in the range of the mask. */
4147 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4148 for (i = 0; i < sizeof(eth_m->dst); ++i)
4149 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4150 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4151 ð_m->src, sizeof(eth_m->src));
4152 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4153 /* The value must be in the range of the mask. */
4154 for (i = 0; i < sizeof(eth_m->dst); ++i)
4155 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4156 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4157 rte_be_to_cpu_16(eth_m->type));
4158 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4159 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4163 * Add VLAN item to matcher and to the value.
4165 * @param[in, out] dev_flow
4167 * @param[in, out] matcher
4169 * @param[in, out] key
4170 * Flow matcher value.
4172 * Flow pattern to translate.
4174 * Item is inner pattern.
4177 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4178 void *matcher, void *key,
4179 const struct rte_flow_item *item,
4182 const struct rte_flow_item_vlan *vlan_m = item->mask;
4183 const struct rte_flow_item_vlan *vlan_v = item->spec;
4192 vlan_m = &rte_flow_item_vlan_mask;
4194 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4196 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4198 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4200 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4202 * This is workaround, masks are not supported,
4203 * and pre-validated.
4205 dev_flow->dv.vf_vlan.tag =
4206 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4208 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4209 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4210 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4211 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4212 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4213 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4214 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4215 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4218 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4219 rte_be_to_cpu_16(vlan_m->inner_type));
4220 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4221 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4225 * Add IPV4 item to matcher and to the value.
4227 * @param[in, out] matcher
4229 * @param[in, out] key
4230 * Flow matcher value.
4232 * Flow pattern to translate.
4234 * Item is inner pattern.
4236 * The group to insert the rule.
4239 flow_dv_translate_item_ipv4(void *matcher, void *key,
4240 const struct rte_flow_item *item,
4241 int inner, uint32_t group)
4243 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4244 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4245 const struct rte_flow_item_ipv4 nic_mask = {
4247 .src_addr = RTE_BE32(0xffffffff),
4248 .dst_addr = RTE_BE32(0xffffffff),
4249 .type_of_service = 0xff,
4250 .next_proto_id = 0xff,
4260 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4262 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4264 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4266 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4269 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4271 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4272 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4277 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4278 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4279 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4280 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4281 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4282 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4283 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4284 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4285 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4286 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4287 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4288 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4289 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4290 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4291 ipv4_m->hdr.type_of_service);
4292 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4293 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4294 ipv4_m->hdr.type_of_service >> 2);
4295 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4296 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4297 ipv4_m->hdr.next_proto_id);
4298 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4299 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4303 * Add IPV6 item to matcher and to the value.
4305 * @param[in, out] matcher
4307 * @param[in, out] key
4308 * Flow matcher value.
4310 * Flow pattern to translate.
4312 * Item is inner pattern.
4314 * The group to insert the rule.
4317 flow_dv_translate_item_ipv6(void *matcher, void *key,
4318 const struct rte_flow_item *item,
4319 int inner, uint32_t group)
4321 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4322 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4323 const struct rte_flow_item_ipv6 nic_mask = {
4326 "\xff\xff\xff\xff\xff\xff\xff\xff"
4327 "\xff\xff\xff\xff\xff\xff\xff\xff",
4329 "\xff\xff\xff\xff\xff\xff\xff\xff"
4330 "\xff\xff\xff\xff\xff\xff\xff\xff",
4331 .vtc_flow = RTE_BE32(0xffffffff),
4338 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4339 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4348 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4350 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4352 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4354 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4357 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4359 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4360 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4365 size = sizeof(ipv6_m->hdr.dst_addr);
4366 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4367 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4368 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4369 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4370 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4371 for (i = 0; i < size; ++i)
4372 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4373 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4374 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4375 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4376 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4377 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4378 for (i = 0; i < size; ++i)
4379 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4381 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4382 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4383 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4384 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4385 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4386 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4389 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4391 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4394 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4396 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4400 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4402 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4403 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4407 * Add TCP item to matcher and to the value.
4409 * @param[in, out] matcher
4411 * @param[in, out] key
4412 * Flow matcher value.
4414 * Flow pattern to translate.
4416 * Item is inner pattern.
4419 flow_dv_translate_item_tcp(void *matcher, void *key,
4420 const struct rte_flow_item *item,
4423 const struct rte_flow_item_tcp *tcp_m = item->mask;
4424 const struct rte_flow_item_tcp *tcp_v = item->spec;
4429 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4431 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4433 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4435 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4437 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4438 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4442 tcp_m = &rte_flow_item_tcp_mask;
4443 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4444 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4445 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4446 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4447 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4448 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4449 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4450 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4451 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4452 tcp_m->hdr.tcp_flags);
4453 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4454 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4458 * Add UDP item to matcher and to the value.
4460 * @param[in, out] matcher
4462 * @param[in, out] key
4463 * Flow matcher value.
4465 * Flow pattern to translate.
4467 * Item is inner pattern.
4470 flow_dv_translate_item_udp(void *matcher, void *key,
4471 const struct rte_flow_item *item,
4474 const struct rte_flow_item_udp *udp_m = item->mask;
4475 const struct rte_flow_item_udp *udp_v = item->spec;
4480 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4482 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4484 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4486 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4488 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4493 udp_m = &rte_flow_item_udp_mask;
4494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4495 rte_be_to_cpu_16(udp_m->hdr.src_port));
4496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4497 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4498 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4499 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4501 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4505 * Add GRE optional Key item to matcher and to the value.
4507 * @param[in, out] matcher
4509 * @param[in, out] key
4510 * Flow matcher value.
4512 * Flow pattern to translate.
4514 * Item is inner pattern.
4517 flow_dv_translate_item_gre_key(void *matcher, void *key,
4518 const struct rte_flow_item *item)
4520 const rte_be32_t *key_m = item->mask;
4521 const rte_be32_t *key_v = item->spec;
4522 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4523 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4524 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4529 key_m = &gre_key_default_mask;
4530 /* GRE K bit must be on and should already be validated */
4531 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4532 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4533 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4534 rte_be_to_cpu_32(*key_m) >> 8);
4535 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4536 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4537 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4538 rte_be_to_cpu_32(*key_m) & 0xFF);
4539 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4540 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4544 * Add GRE item to matcher and to the value.
4546 * @param[in, out] matcher
4548 * @param[in, out] key
4549 * Flow matcher value.
4551 * Flow pattern to translate.
4553 * Item is inner pattern.
4556 flow_dv_translate_item_gre(void *matcher, void *key,
4557 const struct rte_flow_item *item,
4560 const struct rte_flow_item_gre *gre_m = item->mask;
4561 const struct rte_flow_item_gre *gre_v = item->spec;
4564 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4565 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4572 uint16_t s_present:1;
4573 uint16_t k_present:1;
4574 uint16_t rsvd_bit1:1;
4575 uint16_t c_present:1;
4579 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4582 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4584 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4586 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4588 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4590 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4591 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4595 gre_m = &rte_flow_item_gre_mask;
4596 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4597 rte_be_to_cpu_16(gre_m->protocol));
4598 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4599 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4600 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4601 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4602 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4603 gre_crks_rsvd0_ver_m.c_present);
4604 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4605 gre_crks_rsvd0_ver_v.c_present &
4606 gre_crks_rsvd0_ver_m.c_present);
4607 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4608 gre_crks_rsvd0_ver_m.k_present);
4609 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4610 gre_crks_rsvd0_ver_v.k_present &
4611 gre_crks_rsvd0_ver_m.k_present);
4612 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4613 gre_crks_rsvd0_ver_m.s_present);
4614 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4615 gre_crks_rsvd0_ver_v.s_present &
4616 gre_crks_rsvd0_ver_m.s_present);
4620 * Add NVGRE item to matcher and to the value.
4622 * @param[in, out] matcher
4624 * @param[in, out] key
4625 * Flow matcher value.
4627 * Flow pattern to translate.
4629 * Item is inner pattern.
4632 flow_dv_translate_item_nvgre(void *matcher, void *key,
4633 const struct rte_flow_item *item,
4636 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4637 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4638 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4639 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4640 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4641 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4647 /* For NVGRE, GRE header fields must be set with defined values. */
4648 const struct rte_flow_item_gre gre_spec = {
4649 .c_rsvd0_ver = RTE_BE16(0x2000),
4650 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4652 const struct rte_flow_item_gre gre_mask = {
4653 .c_rsvd0_ver = RTE_BE16(0xB000),
4654 .protocol = RTE_BE16(UINT16_MAX),
4656 const struct rte_flow_item gre_item = {
4661 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4665 nvgre_m = &rte_flow_item_nvgre_mask;
4666 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4667 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4668 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4669 memcpy(gre_key_m, tni_flow_id_m, size);
4670 for (i = 0; i < size; ++i)
4671 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4675 * Add VXLAN item to matcher and to the value.
4677 * @param[in, out] matcher
4679 * @param[in, out] key
4680 * Flow matcher value.
4682 * Flow pattern to translate.
4684 * Item is inner pattern.
4687 flow_dv_translate_item_vxlan(void *matcher, void *key,
4688 const struct rte_flow_item *item,
4691 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4692 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4695 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4696 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4704 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4706 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4708 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4710 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4712 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4713 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4714 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4715 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4716 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4721 vxlan_m = &rte_flow_item_vxlan_mask;
4722 size = sizeof(vxlan_m->vni);
4723 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4724 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4725 memcpy(vni_m, vxlan_m->vni, size);
4726 for (i = 0; i < size; ++i)
4727 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4731 * Add Geneve item to matcher and to the value.
4733 * @param[in, out] matcher
4735 * @param[in, out] key
4736 * Flow matcher value.
4738 * Flow pattern to translate.
4740 * Item is inner pattern.
4744 flow_dv_translate_item_geneve(void *matcher, void *key,
4745 const struct rte_flow_item *item, int inner)
4747 const struct rte_flow_item_geneve *geneve_m = item->mask;
4748 const struct rte_flow_item_geneve *geneve_v = item->spec;
4751 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4752 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4761 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4763 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4765 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4767 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4769 dport = MLX5_UDP_PORT_GENEVE;
4770 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4771 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4772 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4777 geneve_m = &rte_flow_item_geneve_mask;
4778 size = sizeof(geneve_m->vni);
4779 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4780 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4781 memcpy(vni_m, geneve_m->vni, size);
4782 for (i = 0; i < size; ++i)
4783 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4784 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4785 rte_be_to_cpu_16(geneve_m->protocol));
4786 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4787 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4788 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4789 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4790 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4791 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4792 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4793 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4794 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4795 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4796 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4797 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4798 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4802 * Add MPLS item to matcher and to the value.
4804 * @param[in, out] matcher
4806 * @param[in, out] key
4807 * Flow matcher value.
4809 * Flow pattern to translate.
4810 * @param[in] prev_layer
4811 * The protocol layer indicated in previous item.
4813 * Item is inner pattern.
4816 flow_dv_translate_item_mpls(void *matcher, void *key,
4817 const struct rte_flow_item *item,
4818 uint64_t prev_layer,
4821 const uint32_t *in_mpls_m = item->mask;
4822 const uint32_t *in_mpls_v = item->spec;
4823 uint32_t *out_mpls_m = 0;
4824 uint32_t *out_mpls_v = 0;
4825 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4826 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4827 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4829 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4830 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4831 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4833 switch (prev_layer) {
4834 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4835 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4836 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4837 MLX5_UDP_PORT_MPLS);
4839 case MLX5_FLOW_LAYER_GRE:
4840 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4841 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4842 RTE_ETHER_TYPE_MPLS);
4845 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4846 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4853 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4854 switch (prev_layer) {
4855 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4857 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4858 outer_first_mpls_over_udp);
4860 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4861 outer_first_mpls_over_udp);
4863 case MLX5_FLOW_LAYER_GRE:
4865 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4866 outer_first_mpls_over_gre);
4868 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4869 outer_first_mpls_over_gre);
4872 /* Inner MPLS not over GRE is not supported. */
4875 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4879 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4885 if (out_mpls_m && out_mpls_v) {
4886 *out_mpls_m = *in_mpls_m;
4887 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4892 * Add META item to matcher
4894 * @param[in, out] matcher
4896 * @param[in, out] key
4897 * Flow matcher value.
4899 * Flow pattern to translate.
4901 * Item is inner pattern.
4904 flow_dv_translate_item_meta(void *matcher, void *key,
4905 const struct rte_flow_item *item)
4907 const struct rte_flow_item_meta *meta_m;
4908 const struct rte_flow_item_meta *meta_v;
4910 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4912 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4914 meta_m = (const void *)item->mask;
4916 meta_m = &rte_flow_item_meta_mask;
4917 meta_v = (const void *)item->spec;
4919 MLX5_SET(fte_match_set_misc2, misc2_m,
4920 metadata_reg_a, meta_m->data);
4921 MLX5_SET(fte_match_set_misc2, misc2_v,
4922 metadata_reg_a, meta_v->data & meta_m->data);
4927 * Add vport metadata Reg C0 item to matcher
4929 * @param[in, out] matcher
4931 * @param[in, out] key
4932 * Flow matcher value.
4934 * Flow pattern to translate.
4937 flow_dv_translate_item_meta_vport(void *matcher, void *key,
4938 uint32_t value, uint32_t mask)
4941 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4943 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4945 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4946 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);
4950 * Add tag item to matcher
4952 * @param[in, out] matcher
4954 * @param[in, out] key
4955 * Flow matcher value.
4957 * Flow pattern to translate.
4960 flow_dv_translate_item_tag(void *matcher, void *key,
4961 const struct rte_flow_item *item)
4964 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4966 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4967 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
4968 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
4969 enum modify_reg reg = tag_v->id;
4970 rte_be32_t value = tag_v->data;
4971 rte_be32_t mask = tag_m->data;
4975 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4976 rte_be_to_cpu_32(mask));
4977 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4978 rte_be_to_cpu_32(value));
4981 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,
4982 rte_be_to_cpu_32(mask));
4983 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,
4984 rte_be_to_cpu_32(value));
4987 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,
4988 rte_be_to_cpu_32(mask));
4989 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,
4990 rte_be_to_cpu_32(value));
4993 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,
4994 rte_be_to_cpu_32(mask));
4995 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,
4996 rte_be_to_cpu_32(value));
4999 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,
5000 rte_be_to_cpu_32(mask));
5001 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,
5002 rte_be_to_cpu_32(value));
5005 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,
5006 rte_be_to_cpu_32(mask));
5007 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,
5008 rte_be_to_cpu_32(value));
5011 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,
5012 rte_be_to_cpu_32(mask));
5013 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,
5014 rte_be_to_cpu_32(value));
5017 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,
5018 rte_be_to_cpu_32(mask));
5019 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,
5020 rte_be_to_cpu_32(value));
5023 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,
5024 rte_be_to_cpu_32(mask));
5025 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,
5026 rte_be_to_cpu_32(value));
5029 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,
5030 rte_be_to_cpu_32(mask));
5031 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,
5032 rte_be_to_cpu_32(value));
5038 * Add source vport match to the specified matcher.
5040 * @param[in, out] matcher
5042 * @param[in, out] key
5043 * Flow matcher value.
5045 * Source vport value to match
5050 flow_dv_translate_item_source_vport(void *matcher, void *key,
5051 int16_t port, uint16_t mask)
5053 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5054 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5056 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5057 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5061 * Translate port-id item to eswitch match on port-id.
5064 * The devich to configure through.
5065 * @param[in, out] matcher
5067 * @param[in, out] key
5068 * Flow matcher value.
5070 * Flow pattern to translate.
5073 * 0 on success, a negative errno value otherwise.
5076 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5077 void *key, const struct rte_flow_item *item)
5079 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5080 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5081 struct mlx5_priv *priv;
5084 mask = pid_m ? pid_m->id : 0xffff;
5085 id = pid_v ? pid_v->id : dev->data->port_id;
5086 priv = mlx5_port_to_eswitch_info(id);
5089 /* Translate to vport field or to metadata, depending on mode. */
5090 if (priv->vport_meta_mask)
5091 flow_dv_translate_item_meta_vport(matcher, key,
5092 priv->vport_meta_tag,
5093 priv->vport_meta_mask);
5095 flow_dv_translate_item_source_vport(matcher, key,
5096 priv->vport_id, mask);
5101 * Add ICMP6 item to matcher and to the value.
5103 * @param[in, out] matcher
5105 * @param[in, out] key
5106 * Flow matcher value.
5108 * Flow pattern to translate.
5110 * Item is inner pattern.
5113 flow_dv_translate_item_icmp6(void *matcher, void *key,
5114 const struct rte_flow_item *item,
5117 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5118 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5121 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5123 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5125 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5127 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5129 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5131 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5133 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5134 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5138 icmp6_m = &rte_flow_item_icmp6_mask;
5139 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5140 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5141 icmp6_v->type & icmp6_m->type);
5142 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5143 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5144 icmp6_v->code & icmp6_m->code);
5148 * Add ICMP item to matcher and to the value.
5150 * @param[in, out] matcher
5152 * @param[in, out] key
5153 * Flow matcher value.
5155 * Flow pattern to translate.
5157 * Item is inner pattern.
5160 flow_dv_translate_item_icmp(void *matcher, void *key,
5161 const struct rte_flow_item *item,
5164 const struct rte_flow_item_icmp *icmp_m = item->mask;
5165 const struct rte_flow_item_icmp *icmp_v = item->spec;
5168 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5170 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5172 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5174 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5176 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5178 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5180 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5185 icmp_m = &rte_flow_item_icmp_mask;
5186 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5187 icmp_m->hdr.icmp_type);
5188 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5189 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5190 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5191 icmp_m->hdr.icmp_code);
5192 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5193 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5196 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5198 #define HEADER_IS_ZERO(match_criteria, headers) \
5199 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5200 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5203 * Calculate flow matcher enable bitmap.
5205 * @param match_criteria
5206 * Pointer to flow matcher criteria.
5209 * Bitmap of enabled fields.
5212 flow_dv_matcher_enable(uint32_t *match_criteria)
5214 uint8_t match_criteria_enable;
5216 match_criteria_enable =
5217 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5218 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5219 match_criteria_enable |=
5220 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5221 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5222 match_criteria_enable |=
5223 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5224 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5225 match_criteria_enable |=
5226 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5227 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5228 match_criteria_enable |=
5229 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5230 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5231 return match_criteria_enable;
5238 * @param dev[in, out]
5239 * Pointer to rte_eth_dev structure.
5240 * @param[in] table_id
5243 * Direction of the table.
5244 * @param[in] transfer
5245 * E-Switch or NIC flow.
5247 * pointer to error structure.
5250 * Returns tables resource based on the index, NULL in case of failed.
5252 static struct mlx5_flow_tbl_resource *
5253 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5254 uint32_t table_id, uint8_t egress,
5256 struct rte_flow_error *error)
5258 struct mlx5_priv *priv = dev->data->dev_private;
5259 struct mlx5_ibv_shared *sh = priv->sh;
5260 struct mlx5_flow_tbl_resource *tbl;
5262 #ifdef HAVE_MLX5DV_DR
5264 tbl = &sh->fdb_tbl[table_id];
5266 tbl->obj = mlx5_glue->dr_create_flow_tbl
5267 (sh->fdb_domain, table_id);
5268 } else if (egress) {
5269 tbl = &sh->tx_tbl[table_id];
5271 tbl->obj = mlx5_glue->dr_create_flow_tbl
5272 (sh->tx_domain, table_id);
5274 tbl = &sh->rx_tbl[table_id];
5276 tbl->obj = mlx5_glue->dr_create_flow_tbl
5277 (sh->rx_domain, table_id);
5280 rte_flow_error_set(error, ENOMEM,
5281 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5282 NULL, "cannot create table");
5285 rte_atomic32_inc(&tbl->refcnt);
5291 return &sh->fdb_tbl[table_id];
5293 return &sh->tx_tbl[table_id];
5295 return &sh->rx_tbl[table_id];
5300 * Release a flow table.
5303 * Table resource to be released.
5306 * Returns 0 if table was released, else return 1;
5309 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5313 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5314 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5322 * Register the flow matcher.
5324 * @param dev[in, out]
5325 * Pointer to rte_eth_dev structure.
5326 * @param[in, out] matcher
5327 * Pointer to flow matcher.
5328 * @parm[in, out] dev_flow
5329 * Pointer to the dev_flow.
5331 * pointer to error structure.
5334 * 0 on success otherwise -errno and errno is set.
5337 flow_dv_matcher_register(struct rte_eth_dev *dev,
5338 struct mlx5_flow_dv_matcher *matcher,
5339 struct mlx5_flow *dev_flow,
5340 struct rte_flow_error *error)
5342 struct mlx5_priv *priv = dev->data->dev_private;
5343 struct mlx5_ibv_shared *sh = priv->sh;
5344 struct mlx5_flow_dv_matcher *cache_matcher;
5345 struct mlx5dv_flow_matcher_attr dv_attr = {
5346 .type = IBV_FLOW_ATTR_NORMAL,
5347 .match_mask = (void *)&matcher->mask,
5349 struct mlx5_flow_tbl_resource *tbl = NULL;
5351 /* Lookup from cache. */
5352 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5353 if (matcher->crc == cache_matcher->crc &&
5354 matcher->priority == cache_matcher->priority &&
5355 matcher->egress == cache_matcher->egress &&
5356 matcher->group == cache_matcher->group &&
5357 matcher->transfer == cache_matcher->transfer &&
5358 !memcmp((const void *)matcher->mask.buf,
5359 (const void *)cache_matcher->mask.buf,
5360 cache_matcher->mask.size)) {
5362 "priority %hd use %s matcher %p: refcnt %d++",
5363 cache_matcher->priority,
5364 cache_matcher->egress ? "tx" : "rx",
5365 (void *)cache_matcher,
5366 rte_atomic32_read(&cache_matcher->refcnt));
5367 rte_atomic32_inc(&cache_matcher->refcnt);
5368 dev_flow->dv.matcher = cache_matcher;
5372 /* Register new matcher. */
5373 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5375 return rte_flow_error_set(error, ENOMEM,
5376 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5377 "cannot allocate matcher memory");
5378 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5379 matcher->egress, matcher->transfer,
5382 rte_free(cache_matcher);
5383 return rte_flow_error_set(error, ENOMEM,
5384 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5385 NULL, "cannot create table");
5387 *cache_matcher = *matcher;
5388 dv_attr.match_criteria_enable =
5389 flow_dv_matcher_enable(cache_matcher->mask.buf);
5390 dv_attr.priority = matcher->priority;
5391 if (matcher->egress)
5392 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5393 cache_matcher->matcher_object =
5394 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5395 if (!cache_matcher->matcher_object) {
5396 rte_free(cache_matcher);
5397 #ifdef HAVE_MLX5DV_DR
5398 flow_dv_tbl_resource_release(tbl);
5400 return rte_flow_error_set(error, ENOMEM,
5401 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5402 NULL, "cannot create matcher");
5404 rte_atomic32_inc(&cache_matcher->refcnt);
5405 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5406 dev_flow->dv.matcher = cache_matcher;
5407 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5408 cache_matcher->priority,
5409 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5410 rte_atomic32_read(&cache_matcher->refcnt));
5411 rte_atomic32_inc(&tbl->refcnt);
5416 * Find existing tag resource or create and register a new one.
5418 * @param dev[in, out]
5419 * Pointer to rte_eth_dev structure.
5420 * @param[in, out] resource
5421 * Pointer to tag resource.
5422 * @parm[in, out] dev_flow
5423 * Pointer to the dev_flow.
5425 * pointer to error structure.
5428 * 0 on success otherwise -errno and errno is set.
5431 flow_dv_tag_resource_register
5432 (struct rte_eth_dev *dev,
5433 struct mlx5_flow_dv_tag_resource *resource,
5434 struct mlx5_flow *dev_flow,
5435 struct rte_flow_error *error)
5437 struct mlx5_priv *priv = dev->data->dev_private;
5438 struct mlx5_ibv_shared *sh = priv->sh;
5439 struct mlx5_flow_dv_tag_resource *cache_resource;
5441 /* Lookup a matching resource from cache. */
5442 LIST_FOREACH(cache_resource, &sh->tags, next) {
5443 if (resource->tag == cache_resource->tag) {
5444 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5445 (void *)cache_resource,
5446 rte_atomic32_read(&cache_resource->refcnt));
5447 rte_atomic32_inc(&cache_resource->refcnt);
5448 dev_flow->flow->tag_resource = cache_resource;
5452 /* Register new resource. */
5453 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5454 if (!cache_resource)
5455 return rte_flow_error_set(error, ENOMEM,
5456 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5457 "cannot allocate resource memory");
5458 *cache_resource = *resource;
5459 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5461 if (!cache_resource->action) {
5462 rte_free(cache_resource);
5463 return rte_flow_error_set(error, ENOMEM,
5464 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5465 NULL, "cannot create action");
5467 rte_atomic32_init(&cache_resource->refcnt);
5468 rte_atomic32_inc(&cache_resource->refcnt);
5469 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5470 dev_flow->flow->tag_resource = cache_resource;
5471 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5472 (void *)cache_resource,
5473 rte_atomic32_read(&cache_resource->refcnt));
5481 * Pointer to Ethernet device.
5483 * Pointer to mlx5_flow.
5486 * 1 while a reference on it exists, 0 when freed.
5489 flow_dv_tag_release(struct rte_eth_dev *dev,
5490 struct mlx5_flow_dv_tag_resource *tag)
5493 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5494 dev->data->port_id, (void *)tag,
5495 rte_atomic32_read(&tag->refcnt));
5496 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5497 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5498 LIST_REMOVE(tag, next);
5499 DRV_LOG(DEBUG, "port %u tag %p: removed",
5500 dev->data->port_id, (void *)tag);
5508 * Translate port ID action to vport.
5511 * Pointer to rte_eth_dev structure.
5513 * Pointer to the port ID action.
5514 * @param[out] dst_port_id
5515 * The target port ID.
5517 * Pointer to the error structure.
5520 * 0 on success, a negative errno value otherwise and rte_errno is set.
5523 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5524 const struct rte_flow_action *action,
5525 uint32_t *dst_port_id,
5526 struct rte_flow_error *error)
5529 struct mlx5_priv *priv;
5530 const struct rte_flow_action_port_id *conf =
5531 (const struct rte_flow_action_port_id *)action->conf;
5533 port = conf->original ? dev->data->port_id : conf->id;
5534 priv = mlx5_port_to_eswitch_info(port);
5536 return rte_flow_error_set(error, -rte_errno,
5537 RTE_FLOW_ERROR_TYPE_ACTION,
5539 "No eswitch info was found for port");
5540 if (priv->vport_meta_mask)
5541 *dst_port_id = priv->vport_meta_tag;
5543 *dst_port_id = priv->vport_id;
5548 * Add Tx queue matcher
5551 * Pointer to the dev struct.
5552 * @param[in, out] matcher
5554 * @param[in, out] key
5555 * Flow matcher value.
5557 * Flow pattern to translate.
5559 * Item is inner pattern.
5562 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5563 void *matcher, void *key,
5564 const struct rte_flow_item *item)
5566 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5567 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5569 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5571 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5572 struct mlx5_txq_ctrl *txq;
5576 queue_m = (const void *)item->mask;
5579 queue_v = (const void *)item->spec;
5582 txq = mlx5_txq_get(dev, queue_v->queue);
5585 queue = txq->obj->sq->id;
5586 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5587 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5588 queue & queue_m->queue);
5589 mlx5_txq_release(dev, queue_v->queue);
5593 * Fill the flow with DV spec.
5596 * Pointer to rte_eth_dev structure.
5597 * @param[in, out] dev_flow
5598 * Pointer to the sub flow.
5600 * Pointer to the flow attributes.
5602 * Pointer to the list of items.
5603 * @param[in] actions
5604 * Pointer to the list of actions.
5606 * Pointer to the error structure.
5609 * 0 on success, a negative errno value otherwise and rte_errno is set.
5612 flow_dv_translate(struct rte_eth_dev *dev,
5613 struct mlx5_flow *dev_flow,
5614 const struct rte_flow_attr *attr,
5615 const struct rte_flow_item items[],
5616 const struct rte_flow_action actions[],
5617 struct rte_flow_error *error)
5619 struct mlx5_priv *priv = dev->data->dev_private;
5620 struct rte_flow *flow = dev_flow->flow;
5621 uint64_t item_flags = 0;
5622 uint64_t last_item = 0;
5623 uint64_t action_flags = 0;
5624 uint64_t priority = attr->priority;
5625 struct mlx5_flow_dv_matcher matcher = {
5627 .size = sizeof(matcher.mask.buf),
5631 bool actions_end = false;
5632 struct mlx5_flow_dv_modify_hdr_resource res = {
5633 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5634 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5636 union flow_dv_attr flow_attr = { .attr = 0 };
5637 struct mlx5_flow_dv_tag_resource tag_resource;
5638 uint32_t modify_action_position = UINT32_MAX;
5639 void *match_mask = matcher.mask.buf;
5640 void *match_value = dev_flow->dv.value.buf;
5641 uint8_t next_protocol = 0xff;
5642 struct rte_vlan_hdr vlan = { 0 };
5646 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5650 flow->group = table;
5652 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5653 if (priority == MLX5_FLOW_PRIO_RSVD)
5654 priority = priv->config.flow_prio - 1;
5655 for (; !actions_end ; actions++) {
5656 const struct rte_flow_action_queue *queue;
5657 const struct rte_flow_action_rss *rss;
5658 const struct rte_flow_action *action = actions;
5659 const struct rte_flow_action_count *count = action->conf;
5660 const uint8_t *rss_key;
5661 const struct rte_flow_action_jump *jump_data;
5662 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5663 struct mlx5_flow_tbl_resource *tbl;
5664 uint32_t port_id = 0;
5665 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5666 int action_type = actions->type;
5667 const struct rte_flow_action *found_action = NULL;
5669 switch (action_type) {
5670 case RTE_FLOW_ACTION_TYPE_VOID:
5672 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5673 if (flow_dv_translate_action_port_id(dev, action,
5676 port_id_resource.port_id = port_id;
5677 if (flow_dv_port_id_action_resource_register
5678 (dev, &port_id_resource, dev_flow, error))
5680 dev_flow->dv.actions[actions_n++] =
5681 dev_flow->dv.port_id_action->action;
5682 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5684 case RTE_FLOW_ACTION_TYPE_FLAG:
5686 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5687 if (!flow->tag_resource)
5688 if (flow_dv_tag_resource_register
5689 (dev, &tag_resource, dev_flow, error))
5691 dev_flow->dv.actions[actions_n++] =
5692 flow->tag_resource->action;
5693 action_flags |= MLX5_FLOW_ACTION_FLAG;
5695 case RTE_FLOW_ACTION_TYPE_MARK:
5696 tag_resource.tag = mlx5_flow_mark_set
5697 (((const struct rte_flow_action_mark *)
5698 (actions->conf))->id);
5699 if (!flow->tag_resource)
5700 if (flow_dv_tag_resource_register
5701 (dev, &tag_resource, dev_flow, error))
5703 dev_flow->dv.actions[actions_n++] =
5704 flow->tag_resource->action;
5705 action_flags |= MLX5_FLOW_ACTION_MARK;
5707 case RTE_FLOW_ACTION_TYPE_DROP:
5708 action_flags |= MLX5_FLOW_ACTION_DROP;
5710 case RTE_FLOW_ACTION_TYPE_QUEUE:
5711 queue = actions->conf;
5712 flow->rss.queue_num = 1;
5713 (*flow->queue)[0] = queue->index;
5714 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5716 case RTE_FLOW_ACTION_TYPE_RSS:
5717 rss = actions->conf;
5719 memcpy((*flow->queue), rss->queue,
5720 rss->queue_num * sizeof(uint16_t));
5721 flow->rss.queue_num = rss->queue_num;
5722 /* NULL RSS key indicates default RSS key. */
5723 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5724 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5725 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
5726 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
5727 flow->rss.level = rss->level;
5728 action_flags |= MLX5_FLOW_ACTION_RSS;
5730 case RTE_FLOW_ACTION_TYPE_COUNT:
5731 if (!priv->config.devx) {
5732 rte_errno = ENOTSUP;
5735 flow->counter = flow_dv_counter_alloc(dev,
5739 if (flow->counter == NULL)
5741 dev_flow->dv.actions[actions_n++] =
5742 flow->counter->action;
5743 action_flags |= MLX5_FLOW_ACTION_COUNT;
5746 if (rte_errno == ENOTSUP)
5747 return rte_flow_error_set
5749 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5751 "count action not supported");
5753 return rte_flow_error_set
5755 RTE_FLOW_ERROR_TYPE_ACTION,
5757 "cannot create counter"
5760 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5761 dev_flow->dv.actions[actions_n++] =
5762 priv->sh->pop_vlan_action;
5763 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5765 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5766 flow_dev_get_vlan_info_from_items(items, &vlan);
5767 vlan.eth_proto = rte_be_to_cpu_16
5768 ((((const struct rte_flow_action_of_push_vlan *)
5769 actions->conf)->ethertype));
5770 found_action = mlx5_flow_find_action
5772 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5774 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5775 found_action = mlx5_flow_find_action
5777 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5779 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5780 if (flow_dv_create_action_push_vlan
5781 (dev, attr, &vlan, dev_flow, error))
5783 dev_flow->dv.actions[actions_n++] =
5784 dev_flow->dv.push_vlan_res->action;
5785 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5787 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5788 /* of_vlan_push action handled this action */
5789 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5791 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5792 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5794 flow_dev_get_vlan_info_from_items(items, &vlan);
5795 mlx5_update_vlan_vid_pcp(actions, &vlan);
5796 /* If no VLAN push - this is a modify header action */
5797 if (flow_dv_convert_action_modify_vlan_vid
5798 (&res, actions, error))
5800 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5802 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5803 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5804 if (flow_dv_create_action_l2_encap(dev, actions,
5809 dev_flow->dv.actions[actions_n++] =
5810 dev_flow->dv.encap_decap->verbs_action;
5811 action_flags |= actions->type ==
5812 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5813 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5814 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5816 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5817 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5818 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5822 dev_flow->dv.actions[actions_n++] =
5823 dev_flow->dv.encap_decap->verbs_action;
5824 action_flags |= actions->type ==
5825 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5826 MLX5_FLOW_ACTION_VXLAN_DECAP :
5827 MLX5_FLOW_ACTION_NVGRE_DECAP;
5829 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5830 /* Handle encap with preceding decap. */
5831 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5832 if (flow_dv_create_action_raw_encap
5833 (dev, actions, dev_flow, attr, error))
5835 dev_flow->dv.actions[actions_n++] =
5836 dev_flow->dv.encap_decap->verbs_action;
5838 /* Handle encap without preceding decap. */
5839 if (flow_dv_create_action_l2_encap
5840 (dev, actions, dev_flow, attr->transfer,
5843 dev_flow->dv.actions[actions_n++] =
5844 dev_flow->dv.encap_decap->verbs_action;
5846 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5848 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5849 /* Check if this decap is followed by encap. */
5850 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5851 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5854 /* Handle decap only if it isn't followed by encap. */
5855 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5856 if (flow_dv_create_action_l2_decap
5857 (dev, dev_flow, attr->transfer, error))
5859 dev_flow->dv.actions[actions_n++] =
5860 dev_flow->dv.encap_decap->verbs_action;
5862 /* If decap is followed by encap, handle it at encap. */
5863 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5865 case RTE_FLOW_ACTION_TYPE_JUMP:
5866 jump_data = action->conf;
5867 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5868 jump_data->group, &table,
5872 tbl = flow_dv_tbl_resource_get(dev, table,
5874 attr->transfer, error);
5876 return rte_flow_error_set
5878 RTE_FLOW_ERROR_TYPE_ACTION,
5880 "cannot create jump action.");
5881 jump_tbl_resource.tbl = tbl;
5882 if (flow_dv_jump_tbl_resource_register
5883 (dev, &jump_tbl_resource, dev_flow, error)) {
5884 flow_dv_tbl_resource_release(tbl);
5885 return rte_flow_error_set
5887 RTE_FLOW_ERROR_TYPE_ACTION,
5889 "cannot create jump action.");
5891 dev_flow->dv.actions[actions_n++] =
5892 dev_flow->dv.jump->action;
5893 action_flags |= MLX5_FLOW_ACTION_JUMP;
5895 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5896 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5897 if (flow_dv_convert_action_modify_mac(&res, actions,
5900 action_flags |= actions->type ==
5901 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5902 MLX5_FLOW_ACTION_SET_MAC_SRC :
5903 MLX5_FLOW_ACTION_SET_MAC_DST;
5905 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5906 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5907 if (flow_dv_convert_action_modify_ipv4(&res, actions,
5910 action_flags |= actions->type ==
5911 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5912 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5913 MLX5_FLOW_ACTION_SET_IPV4_DST;
5915 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5916 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5917 if (flow_dv_convert_action_modify_ipv6(&res, actions,
5920 action_flags |= actions->type ==
5921 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5922 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5923 MLX5_FLOW_ACTION_SET_IPV6_DST;
5925 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5926 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5927 if (flow_dv_convert_action_modify_tp(&res, actions,
5931 action_flags |= actions->type ==
5932 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5933 MLX5_FLOW_ACTION_SET_TP_SRC :
5934 MLX5_FLOW_ACTION_SET_TP_DST;
5936 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5937 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5941 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5943 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5944 if (flow_dv_convert_action_modify_ttl(&res, actions,
5948 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5950 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5951 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5952 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5955 action_flags |= actions->type ==
5956 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5957 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5958 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5961 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5962 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5963 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
5966 action_flags |= actions->type ==
5967 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5968 MLX5_FLOW_ACTION_INC_TCP_ACK :
5969 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5971 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5972 if (flow_dv_convert_action_set_reg(&res, actions,
5975 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5977 case RTE_FLOW_ACTION_TYPE_END:
5979 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
5980 /* create modify action if needed. */
5981 if (flow_dv_modify_hdr_resource_register
5986 dev_flow->dv.actions[modify_action_position] =
5987 dev_flow->dv.modify_hdr->verbs_action;
5993 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
5994 modify_action_position == UINT32_MAX)
5995 modify_action_position = actions_n++;
5997 dev_flow->dv.actions_n = actions_n;
5998 dev_flow->actions = action_flags;
5999 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6000 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6001 int item_type = items->type;
6003 switch (item_type) {
6004 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6005 flow_dv_translate_item_port_id(dev, match_mask,
6006 match_value, items);
6007 last_item = MLX5_FLOW_ITEM_PORT_ID;
6009 case RTE_FLOW_ITEM_TYPE_ETH:
6010 flow_dv_translate_item_eth(match_mask, match_value,
6012 matcher.priority = MLX5_PRIORITY_MAP_L2;
6013 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6014 MLX5_FLOW_LAYER_OUTER_L2;
6016 case RTE_FLOW_ITEM_TYPE_VLAN:
6017 flow_dv_translate_item_vlan(dev_flow,
6018 match_mask, match_value,
6020 matcher.priority = MLX5_PRIORITY_MAP_L2;
6021 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6022 MLX5_FLOW_LAYER_INNER_VLAN) :
6023 (MLX5_FLOW_LAYER_OUTER_L2 |
6024 MLX5_FLOW_LAYER_OUTER_VLAN);
6026 case RTE_FLOW_ITEM_TYPE_IPV4:
6027 mlx5_flow_tunnel_ip_check(items, next_protocol,
6028 &item_flags, &tunnel);
6029 flow_dv_translate_item_ipv4(match_mask, match_value,
6030 items, tunnel, flow->group);
6031 matcher.priority = MLX5_PRIORITY_MAP_L3;
6032 dev_flow->dv.hash_fields |=
6033 mlx5_flow_hashfields_adjust
6035 MLX5_IPV4_LAYER_TYPES,
6036 MLX5_IPV4_IBV_RX_HASH);
6037 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6038 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6039 if (items->mask != NULL &&
6040 ((const struct rte_flow_item_ipv4 *)
6041 items->mask)->hdr.next_proto_id) {
6043 ((const struct rte_flow_item_ipv4 *)
6044 (items->spec))->hdr.next_proto_id;
6046 ((const struct rte_flow_item_ipv4 *)
6047 (items->mask))->hdr.next_proto_id;
6049 /* Reset for inner layer. */
6050 next_protocol = 0xff;
6053 case RTE_FLOW_ITEM_TYPE_IPV6:
6054 mlx5_flow_tunnel_ip_check(items, next_protocol,
6055 &item_flags, &tunnel);
6056 flow_dv_translate_item_ipv6(match_mask, match_value,
6057 items, tunnel, flow->group);
6058 matcher.priority = MLX5_PRIORITY_MAP_L3;
6059 dev_flow->dv.hash_fields |=
6060 mlx5_flow_hashfields_adjust
6062 MLX5_IPV6_LAYER_TYPES,
6063 MLX5_IPV6_IBV_RX_HASH);
6064 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6065 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6066 if (items->mask != NULL &&
6067 ((const struct rte_flow_item_ipv6 *)
6068 items->mask)->hdr.proto) {
6070 ((const struct rte_flow_item_ipv6 *)
6071 items->spec)->hdr.proto;
6073 ((const struct rte_flow_item_ipv6 *)
6074 items->mask)->hdr.proto;
6076 /* Reset for inner layer. */
6077 next_protocol = 0xff;
6080 case RTE_FLOW_ITEM_TYPE_TCP:
6081 flow_dv_translate_item_tcp(match_mask, match_value,
6083 matcher.priority = MLX5_PRIORITY_MAP_L4;
6084 dev_flow->dv.hash_fields |=
6085 mlx5_flow_hashfields_adjust
6086 (dev_flow, tunnel, ETH_RSS_TCP,
6087 IBV_RX_HASH_SRC_PORT_TCP |
6088 IBV_RX_HASH_DST_PORT_TCP);
6089 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6090 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6092 case RTE_FLOW_ITEM_TYPE_UDP:
6093 flow_dv_translate_item_udp(match_mask, match_value,
6095 matcher.priority = MLX5_PRIORITY_MAP_L4;
6096 dev_flow->dv.hash_fields |=
6097 mlx5_flow_hashfields_adjust
6098 (dev_flow, tunnel, ETH_RSS_UDP,
6099 IBV_RX_HASH_SRC_PORT_UDP |
6100 IBV_RX_HASH_DST_PORT_UDP);
6101 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6102 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6104 case RTE_FLOW_ITEM_TYPE_GRE:
6105 flow_dv_translate_item_gre(match_mask, match_value,
6107 last_item = MLX5_FLOW_LAYER_GRE;
6109 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6110 flow_dv_translate_item_gre_key(match_mask,
6111 match_value, items);
6112 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6114 case RTE_FLOW_ITEM_TYPE_NVGRE:
6115 flow_dv_translate_item_nvgre(match_mask, match_value,
6117 last_item = MLX5_FLOW_LAYER_GRE;
6119 case RTE_FLOW_ITEM_TYPE_VXLAN:
6120 flow_dv_translate_item_vxlan(match_mask, match_value,
6122 last_item = MLX5_FLOW_LAYER_VXLAN;
6124 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6125 flow_dv_translate_item_vxlan(match_mask, match_value,
6127 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6129 case RTE_FLOW_ITEM_TYPE_GENEVE:
6130 flow_dv_translate_item_geneve(match_mask, match_value,
6132 last_item = MLX5_FLOW_LAYER_GENEVE;
6134 case RTE_FLOW_ITEM_TYPE_MPLS:
6135 flow_dv_translate_item_mpls(match_mask, match_value,
6136 items, last_item, tunnel);
6137 last_item = MLX5_FLOW_LAYER_MPLS;
6139 case RTE_FLOW_ITEM_TYPE_META:
6140 flow_dv_translate_item_meta(match_mask, match_value,
6142 last_item = MLX5_FLOW_ITEM_METADATA;
6144 case RTE_FLOW_ITEM_TYPE_ICMP:
6145 flow_dv_translate_item_icmp(match_mask, match_value,
6147 last_item = MLX5_FLOW_LAYER_ICMP;
6149 case RTE_FLOW_ITEM_TYPE_ICMP6:
6150 flow_dv_translate_item_icmp6(match_mask, match_value,
6152 last_item = MLX5_FLOW_LAYER_ICMP6;
6154 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6155 flow_dv_translate_item_tag(match_mask, match_value,
6157 last_item = MLX5_FLOW_ITEM_TAG;
6159 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6160 flow_dv_translate_item_tx_queue(dev, match_mask,
6163 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6168 item_flags |= last_item;
6171 * In case of ingress traffic when E-Switch mode is enabled,
6172 * we have two cases where we need to set the source port manually.
6173 * The first one, is in case of Nic steering rule, and the second is
6174 * E-Switch rule where no port_id item was found. In both cases
6175 * the source port is set according the current port in use.
6177 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6178 (priv->representor || priv->master)) {
6179 if (flow_dv_translate_item_port_id(dev, match_mask,
6183 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6184 dev_flow->dv.value.buf));
6185 dev_flow->layers = item_flags;
6186 /* Register matcher. */
6187 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6189 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6191 matcher.egress = attr->egress;
6192 matcher.group = flow->group;
6193 matcher.transfer = attr->transfer;
6194 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6200 * Apply the flow to the NIC.
6203 * Pointer to the Ethernet device structure.
6204 * @param[in, out] flow
6205 * Pointer to flow structure.
6207 * Pointer to error structure.
6210 * 0 on success, a negative errno value otherwise and rte_errno is set.
6213 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6214 struct rte_flow_error *error)
6216 struct mlx5_flow_dv *dv;
6217 struct mlx5_flow *dev_flow;
6218 struct mlx5_priv *priv = dev->data->dev_private;
6222 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6225 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6226 if (flow->transfer) {
6227 dv->actions[n++] = priv->sh->esw_drop_action;
6229 dv->hrxq = mlx5_hrxq_drop_new(dev);
6233 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6235 "cannot get drop hash queue");
6238 dv->actions[n++] = dv->hrxq->action;
6240 } else if (dev_flow->actions &
6241 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6242 struct mlx5_hrxq *hrxq;
6244 hrxq = mlx5_hrxq_get(dev, flow->key,
6245 MLX5_RSS_HASH_KEY_LEN,
6248 flow->rss.queue_num);
6250 hrxq = mlx5_hrxq_new
6251 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
6252 dv->hash_fields, (*flow->queue),
6253 flow->rss.queue_num,
6254 !!(dev_flow->layers &
6255 MLX5_FLOW_LAYER_TUNNEL));
6260 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6261 "cannot get hash queue");
6265 dv->actions[n++] = dv->hrxq->action;
6268 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6269 (void *)&dv->value, n,
6272 rte_flow_error_set(error, errno,
6273 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6275 "hardware refuses to create flow");
6278 if (priv->vmwa_context &&
6279 dev_flow->dv.vf_vlan.tag &&
6280 !dev_flow->dv.vf_vlan.created) {
6282 * The rule contains the VLAN pattern.
6283 * For VF we are going to create VLAN
6284 * interface to make hypervisor set correct
6285 * e-Switch vport context.
6287 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6292 err = rte_errno; /* Save rte_errno before cleanup. */
6293 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6294 struct mlx5_flow_dv *dv = &dev_flow->dv;
6296 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6297 mlx5_hrxq_drop_release(dev);
6299 mlx5_hrxq_release(dev, dv->hrxq);
6302 if (dev_flow->dv.vf_vlan.tag &&
6303 dev_flow->dv.vf_vlan.created)
6304 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6306 rte_errno = err; /* Restore rte_errno. */
6311 * Release the flow matcher.
6314 * Pointer to Ethernet device.
6316 * Pointer to mlx5_flow.
6319 * 1 while a reference on it exists, 0 when freed.
6322 flow_dv_matcher_release(struct rte_eth_dev *dev,
6323 struct mlx5_flow *flow)
6325 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6326 struct mlx5_priv *priv = dev->data->dev_private;
6327 struct mlx5_ibv_shared *sh = priv->sh;
6328 struct mlx5_flow_tbl_resource *tbl;
6330 assert(matcher->matcher_object);
6331 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6332 dev->data->port_id, (void *)matcher,
6333 rte_atomic32_read(&matcher->refcnt));
6334 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6335 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6336 (matcher->matcher_object));
6337 LIST_REMOVE(matcher, next);
6338 if (matcher->egress)
6339 tbl = &sh->tx_tbl[matcher->group];
6341 tbl = &sh->rx_tbl[matcher->group];
6342 flow_dv_tbl_resource_release(tbl);
6344 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6345 dev->data->port_id, (void *)matcher);
6352 * Release an encap/decap resource.
6355 * Pointer to mlx5_flow.
6358 * 1 while a reference on it exists, 0 when freed.
6361 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6363 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6364 flow->dv.encap_decap;
6366 assert(cache_resource->verbs_action);
6367 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6368 (void *)cache_resource,
6369 rte_atomic32_read(&cache_resource->refcnt));
6370 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6371 claim_zero(mlx5_glue->destroy_flow_action
6372 (cache_resource->verbs_action));
6373 LIST_REMOVE(cache_resource, next);
6374 rte_free(cache_resource);
6375 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6376 (void *)cache_resource);
6383 * Release an jump to table action resource.
6386 * Pointer to mlx5_flow.
6389 * 1 while a reference on it exists, 0 when freed.
6392 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6394 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6397 assert(cache_resource->action);
6398 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6399 (void *)cache_resource,
6400 rte_atomic32_read(&cache_resource->refcnt));
6401 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6402 claim_zero(mlx5_glue->destroy_flow_action
6403 (cache_resource->action));
6404 LIST_REMOVE(cache_resource, next);
6405 flow_dv_tbl_resource_release(cache_resource->tbl);
6406 rte_free(cache_resource);
6407 DRV_LOG(DEBUG, "jump table resource %p: removed",
6408 (void *)cache_resource);
6415 * Release a modify-header resource.
6418 * Pointer to mlx5_flow.
6421 * 1 while a reference on it exists, 0 when freed.
6424 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6426 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6427 flow->dv.modify_hdr;
6429 assert(cache_resource->verbs_action);
6430 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6431 (void *)cache_resource,
6432 rte_atomic32_read(&cache_resource->refcnt));
6433 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6434 claim_zero(mlx5_glue->destroy_flow_action
6435 (cache_resource->verbs_action));
6436 LIST_REMOVE(cache_resource, next);
6437 rte_free(cache_resource);
6438 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6439 (void *)cache_resource);
6446 * Release port ID action resource.
6449 * Pointer to mlx5_flow.
6452 * 1 while a reference on it exists, 0 when freed.
6455 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6457 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6458 flow->dv.port_id_action;
6460 assert(cache_resource->action);
6461 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6462 (void *)cache_resource,
6463 rte_atomic32_read(&cache_resource->refcnt));
6464 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6465 claim_zero(mlx5_glue->destroy_flow_action
6466 (cache_resource->action));
6467 LIST_REMOVE(cache_resource, next);
6468 rte_free(cache_resource);
6469 DRV_LOG(DEBUG, "port id action resource %p: removed",
6470 (void *)cache_resource);
6477 * Release push vlan action resource.
6480 * Pointer to mlx5_flow.
6483 * 1 while a reference on it exists, 0 when freed.
6486 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6488 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6489 flow->dv.push_vlan_res;
6491 assert(cache_resource->action);
6492 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6493 (void *)cache_resource,
6494 rte_atomic32_read(&cache_resource->refcnt));
6495 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6496 claim_zero(mlx5_glue->destroy_flow_action
6497 (cache_resource->action));
6498 LIST_REMOVE(cache_resource, next);
6499 rte_free(cache_resource);
6500 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6501 (void *)cache_resource);
6508 * Remove the flow from the NIC but keeps it in memory.
6511 * Pointer to Ethernet device.
6512 * @param[in, out] flow
6513 * Pointer to flow structure.
6516 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6518 struct mlx5_flow_dv *dv;
6519 struct mlx5_flow *dev_flow;
6523 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6526 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6530 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6531 mlx5_hrxq_drop_release(dev);
6533 mlx5_hrxq_release(dev, dv->hrxq);
6536 if (dev_flow->dv.vf_vlan.tag &&
6537 dev_flow->dv.vf_vlan.created)
6538 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6543 * Remove the flow from the NIC and the memory.
6546 * Pointer to the Ethernet device structure.
6547 * @param[in, out] flow
6548 * Pointer to flow structure.
6551 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6553 struct mlx5_flow *dev_flow;
6557 flow_dv_remove(dev, flow);
6558 if (flow->counter) {
6559 flow_dv_counter_release(dev, flow->counter);
6560 flow->counter = NULL;
6562 if (flow->tag_resource) {
6563 flow_dv_tag_release(dev, flow->tag_resource);
6564 flow->tag_resource = NULL;
6566 while (!LIST_EMPTY(&flow->dev_flows)) {
6567 dev_flow = LIST_FIRST(&flow->dev_flows);
6568 LIST_REMOVE(dev_flow, next);
6569 if (dev_flow->dv.matcher)
6570 flow_dv_matcher_release(dev, dev_flow);
6571 if (dev_flow->dv.encap_decap)
6572 flow_dv_encap_decap_resource_release(dev_flow);
6573 if (dev_flow->dv.modify_hdr)
6574 flow_dv_modify_hdr_resource_release(dev_flow);
6575 if (dev_flow->dv.jump)
6576 flow_dv_jump_tbl_resource_release(dev_flow);
6577 if (dev_flow->dv.port_id_action)
6578 flow_dv_port_id_action_resource_release(dev_flow);
6579 if (dev_flow->dv.push_vlan_res)
6580 flow_dv_push_vlan_action_resource_release(dev_flow);
6586 * Query a dv flow rule for its statistics via devx.
6589 * Pointer to Ethernet device.
6591 * Pointer to the sub flow.
6593 * data retrieved by the query.
6595 * Perform verbose error reporting if not NULL.
6598 * 0 on success, a negative errno value otherwise and rte_errno is set.
6601 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6602 void *data, struct rte_flow_error *error)
6604 struct mlx5_priv *priv = dev->data->dev_private;
6605 struct rte_flow_query_count *qc = data;
6607 if (!priv->config.devx)
6608 return rte_flow_error_set(error, ENOTSUP,
6609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6611 "counters are not supported");
6612 if (flow->counter) {
6613 uint64_t pkts, bytes;
6614 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6618 return rte_flow_error_set(error, -err,
6619 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6620 NULL, "cannot read counters");
6623 qc->hits = pkts - flow->counter->hits;
6624 qc->bytes = bytes - flow->counter->bytes;
6626 flow->counter->hits = pkts;
6627 flow->counter->bytes = bytes;
6631 return rte_flow_error_set(error, EINVAL,
6632 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6634 "counters are not available");
6640 * @see rte_flow_query()
6644 flow_dv_query(struct rte_eth_dev *dev,
6645 struct rte_flow *flow __rte_unused,
6646 const struct rte_flow_action *actions __rte_unused,
6647 void *data __rte_unused,
6648 struct rte_flow_error *error __rte_unused)
6652 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6653 switch (actions->type) {
6654 case RTE_FLOW_ACTION_TYPE_VOID:
6656 case RTE_FLOW_ACTION_TYPE_COUNT:
6657 ret = flow_dv_query_count(dev, flow, data, error);
6660 return rte_flow_error_set(error, ENOTSUP,
6661 RTE_FLOW_ERROR_TYPE_ACTION,
6663 "action not supported");
6670 * Mutex-protected thunk to flow_dv_translate().
6673 flow_d_translate(struct rte_eth_dev *dev,
6674 struct mlx5_flow *dev_flow,
6675 const struct rte_flow_attr *attr,
6676 const struct rte_flow_item items[],
6677 const struct rte_flow_action actions[],
6678 struct rte_flow_error *error)
6682 flow_d_shared_lock(dev);
6683 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6684 flow_d_shared_unlock(dev);
6689 * Mutex-protected thunk to flow_dv_apply().
6692 flow_d_apply(struct rte_eth_dev *dev,
6693 struct rte_flow *flow,
6694 struct rte_flow_error *error)
6698 flow_d_shared_lock(dev);
6699 ret = flow_dv_apply(dev, flow, error);
6700 flow_d_shared_unlock(dev);
6705 * Mutex-protected thunk to flow_dv_remove().
6708 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6710 flow_d_shared_lock(dev);
6711 flow_dv_remove(dev, flow);
6712 flow_d_shared_unlock(dev);
6716 * Mutex-protected thunk to flow_dv_destroy().
6719 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6721 flow_d_shared_lock(dev);
6722 flow_dv_destroy(dev, flow);
6723 flow_d_shared_unlock(dev);
6726 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6727 .validate = flow_dv_validate,
6728 .prepare = flow_dv_prepare,
6729 .translate = flow_d_translate,
6730 .apply = flow_d_apply,
6731 .remove = flow_d_remove,
6732 .destroy = flow_d_destroy,
6733 .query = flow_dv_query,
6736 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */