1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
33 #include "mlx5_defs.h"
34 #include "mlx5_glue.h"
35 #include "mlx5_flow.h"
37 #include "mlx5_rxtx.h"
39 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
45 #ifndef HAVE_MLX5DV_DR_ESWITCH
46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
51 #ifndef HAVE_MLX5DV_DR
52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
55 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
56 sizeof(struct rte_flow_item_ipv4))
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
88 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
90 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
92 case RTE_FLOW_ITEM_TYPE_IPV4:
96 case RTE_FLOW_ITEM_TYPE_IPV6:
100 case RTE_FLOW_ITEM_TYPE_UDP:
104 case RTE_FLOW_ITEM_TYPE_TCP:
116 * Convert rte_mtr_color to mlx5 color.
125 rte_col_2_mlx5_col(enum rte_color rcol)
128 case RTE_COLOR_GREEN:
129 return MLX5_FLOW_COLOR_GREEN;
130 case RTE_COLOR_YELLOW:
131 return MLX5_FLOW_COLOR_YELLOW;
133 return MLX5_FLOW_COLOR_RED;
137 return MLX5_FLOW_COLOR_UNDEFINED;
140 struct field_modify_info {
141 uint32_t size; /* Size of field in protocol header, in bytes. */
142 uint32_t offset; /* Offset of field in protocol header, in bytes. */
143 enum mlx5_modification_field id;
146 struct field_modify_info modify_eth[] = {
147 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
148 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
149 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
150 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
154 struct field_modify_info modify_vlan_out_first_vid[] = {
155 /* Size in bits !!! */
156 {12, 0, MLX5_MODI_OUT_FIRST_VID},
160 struct field_modify_info modify_ipv4[] = {
161 {1, 1, MLX5_MODI_OUT_IP_DSCP},
162 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
163 {4, 12, MLX5_MODI_OUT_SIPV4},
164 {4, 16, MLX5_MODI_OUT_DIPV4},
168 struct field_modify_info modify_ipv6[] = {
169 {1, 0, MLX5_MODI_OUT_IP_DSCP},
170 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
171 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
172 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
173 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
174 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
175 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
176 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
177 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
178 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
182 struct field_modify_info modify_udp[] = {
183 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
184 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
188 struct field_modify_info modify_tcp[] = {
189 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
190 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
191 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
192 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
197 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
198 uint8_t next_protocol, uint64_t *item_flags,
201 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
202 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
203 if (next_protocol == IPPROTO_IPIP) {
204 *item_flags |= MLX5_FLOW_LAYER_IPIP;
207 if (next_protocol == IPPROTO_IPV6) {
208 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
214 * Acquire the synchronizing object to protect multithreaded access
215 * to shared dv context. Lock occurs only if context is actually
216 * shared, i.e. we have multiport IB device and representors are
220 * Pointer to the rte_eth_dev structure.
223 flow_dv_shared_lock(struct rte_eth_dev *dev)
225 struct mlx5_priv *priv = dev->data->dev_private;
226 struct mlx5_ibv_shared *sh = priv->sh;
228 if (sh->dv_refcnt > 1) {
231 ret = pthread_mutex_lock(&sh->dv_mutex);
238 flow_dv_shared_unlock(struct rte_eth_dev *dev)
240 struct mlx5_priv *priv = dev->data->dev_private;
241 struct mlx5_ibv_shared *sh = priv->sh;
243 if (sh->dv_refcnt > 1) {
246 ret = pthread_mutex_unlock(&sh->dv_mutex);
252 /* Update VLAN's VID/PCP based on input rte_flow_action.
255 * Pointer to struct rte_flow_action.
257 * Pointer to struct rte_vlan_hdr.
260 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
261 struct rte_vlan_hdr *vlan)
264 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
266 ((const struct rte_flow_action_of_set_vlan_pcp *)
267 action->conf)->vlan_pcp;
268 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
269 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
270 vlan->vlan_tci |= vlan_tci;
271 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
272 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
273 vlan->vlan_tci |= rte_be_to_cpu_16
274 (((const struct rte_flow_action_of_set_vlan_vid *)
275 action->conf)->vlan_vid);
280 * Fetch 1, 2, 3 or 4 byte field from the byte array
281 * and return as unsigned integer in host-endian format.
284 * Pointer to data array.
286 * Size of field to extract.
289 * converted field in host endian format.
291 static inline uint32_t
292 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
301 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
304 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
305 ret = (ret << 8) | *(data + sizeof(uint16_t));
308 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
319 * Convert modify-header action to DV specification.
321 * Data length of each action is determined by provided field description
322 * and the item mask. Data bit offset and width of each action is determined
323 * by provided item mask.
326 * Pointer to item specification.
328 * Pointer to field modification information.
329 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
330 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
331 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
333 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
334 * Negative offset value sets the same offset as source offset.
335 * size field is ignored, value is taken from source field.
336 * @param[in,out] resource
337 * Pointer to the modify-header resource.
339 * Type of modification.
341 * Pointer to the error structure.
344 * 0 on success, a negative errno value otherwise and rte_errno is set.
347 flow_dv_convert_modify_action(struct rte_flow_item *item,
348 struct field_modify_info *field,
349 struct field_modify_info *dcopy,
350 struct mlx5_flow_dv_modify_hdr_resource *resource,
351 uint32_t type, struct rte_flow_error *error)
353 uint32_t i = resource->actions_num;
354 struct mlx5_modification_cmd *actions = resource->actions;
357 * The item and mask are provided in big-endian format.
358 * The fields should be presented as in big-endian format either.
359 * Mask must be always present, it defines the actual field width.
369 if (i >= MLX5_MAX_MODIFY_NUM)
370 return rte_flow_error_set(error, EINVAL,
371 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
372 "too many items to modify");
373 /* Fetch variable byte size mask from the array. */
374 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
375 field->offset, field->size);
380 /* Deduce actual data width in bits from mask value. */
381 off_b = rte_bsf32(mask);
382 size_b = sizeof(uint32_t) * CHAR_BIT -
383 off_b - __builtin_clz(mask);
385 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
386 actions[i].action_type = type;
387 actions[i].field = field->id;
388 actions[i].offset = off_b;
389 actions[i].length = size_b;
390 /* Convert entire record to expected big-endian format. */
391 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
392 if (type == MLX5_MODIFICATION_TYPE_COPY) {
394 actions[i].dst_field = dcopy->id;
395 actions[i].dst_offset =
396 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
397 /* Convert entire record to big-endian format. */
398 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
401 data = flow_dv_fetch_field((const uint8_t *)item->spec +
402 field->offset, field->size);
403 /* Shift out the trailing masked bits from data. */
404 data = (data & mask) >> off_b;
405 actions[i].data1 = rte_cpu_to_be_32(data);
409 } while (field->size);
410 if (resource->actions_num == i)
411 return rte_flow_error_set(error, EINVAL,
412 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
413 "invalid modification flow item");
414 resource->actions_num = i;
419 * Convert modify-header set IPv4 address action to DV specification.
421 * @param[in,out] resource
422 * Pointer to the modify-header resource.
424 * Pointer to action specification.
426 * Pointer to the error structure.
429 * 0 on success, a negative errno value otherwise and rte_errno is set.
432 flow_dv_convert_action_modify_ipv4
433 (struct mlx5_flow_dv_modify_hdr_resource *resource,
434 const struct rte_flow_action *action,
435 struct rte_flow_error *error)
437 const struct rte_flow_action_set_ipv4 *conf =
438 (const struct rte_flow_action_set_ipv4 *)(action->conf);
439 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
440 struct rte_flow_item_ipv4 ipv4;
441 struct rte_flow_item_ipv4 ipv4_mask;
443 memset(&ipv4, 0, sizeof(ipv4));
444 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
445 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
446 ipv4.hdr.src_addr = conf->ipv4_addr;
447 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
449 ipv4.hdr.dst_addr = conf->ipv4_addr;
450 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
453 item.mask = &ipv4_mask;
454 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
455 MLX5_MODIFICATION_TYPE_SET, error);
459 * Convert modify-header set IPv6 address action to DV specification.
461 * @param[in,out] resource
462 * Pointer to the modify-header resource.
464 * Pointer to action specification.
466 * Pointer to the error structure.
469 * 0 on success, a negative errno value otherwise and rte_errno is set.
472 flow_dv_convert_action_modify_ipv6
473 (struct mlx5_flow_dv_modify_hdr_resource *resource,
474 const struct rte_flow_action *action,
475 struct rte_flow_error *error)
477 const struct rte_flow_action_set_ipv6 *conf =
478 (const struct rte_flow_action_set_ipv6 *)(action->conf);
479 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
480 struct rte_flow_item_ipv6 ipv6;
481 struct rte_flow_item_ipv6 ipv6_mask;
483 memset(&ipv6, 0, sizeof(ipv6));
484 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
485 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
486 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
487 sizeof(ipv6.hdr.src_addr));
488 memcpy(&ipv6_mask.hdr.src_addr,
489 &rte_flow_item_ipv6_mask.hdr.src_addr,
490 sizeof(ipv6.hdr.src_addr));
492 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
493 sizeof(ipv6.hdr.dst_addr));
494 memcpy(&ipv6_mask.hdr.dst_addr,
495 &rte_flow_item_ipv6_mask.hdr.dst_addr,
496 sizeof(ipv6.hdr.dst_addr));
499 item.mask = &ipv6_mask;
500 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
501 MLX5_MODIFICATION_TYPE_SET, error);
505 * Convert modify-header set MAC address action to DV specification.
507 * @param[in,out] resource
508 * Pointer to the modify-header resource.
510 * Pointer to action specification.
512 * Pointer to the error structure.
515 * 0 on success, a negative errno value otherwise and rte_errno is set.
518 flow_dv_convert_action_modify_mac
519 (struct mlx5_flow_dv_modify_hdr_resource *resource,
520 const struct rte_flow_action *action,
521 struct rte_flow_error *error)
523 const struct rte_flow_action_set_mac *conf =
524 (const struct rte_flow_action_set_mac *)(action->conf);
525 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
526 struct rte_flow_item_eth eth;
527 struct rte_flow_item_eth eth_mask;
529 memset(ð, 0, sizeof(eth));
530 memset(ð_mask, 0, sizeof(eth_mask));
531 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
532 memcpy(ð.src.addr_bytes, &conf->mac_addr,
533 sizeof(eth.src.addr_bytes));
534 memcpy(ð_mask.src.addr_bytes,
535 &rte_flow_item_eth_mask.src.addr_bytes,
536 sizeof(eth_mask.src.addr_bytes));
538 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
539 sizeof(eth.dst.addr_bytes));
540 memcpy(ð_mask.dst.addr_bytes,
541 &rte_flow_item_eth_mask.dst.addr_bytes,
542 sizeof(eth_mask.dst.addr_bytes));
545 item.mask = ð_mask;
546 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
547 MLX5_MODIFICATION_TYPE_SET, error);
551 * Convert modify-header set VLAN VID action to DV specification.
553 * @param[in,out] resource
554 * Pointer to the modify-header resource.
556 * Pointer to action specification.
558 * Pointer to the error structure.
561 * 0 on success, a negative errno value otherwise and rte_errno is set.
564 flow_dv_convert_action_modify_vlan_vid
565 (struct mlx5_flow_dv_modify_hdr_resource *resource,
566 const struct rte_flow_action *action,
567 struct rte_flow_error *error)
569 const struct rte_flow_action_of_set_vlan_vid *conf =
570 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
571 int i = resource->actions_num;
572 struct mlx5_modification_cmd *actions = &resource->actions[i];
573 struct field_modify_info *field = modify_vlan_out_first_vid;
575 if (i >= MLX5_MAX_MODIFY_NUM)
576 return rte_flow_error_set(error, EINVAL,
577 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
578 "too many items to modify");
579 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
580 actions[i].field = field->id;
581 actions[i].length = field->size;
582 actions[i].offset = field->offset;
583 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
584 actions[i].data1 = conf->vlan_vid;
585 actions[i].data1 = actions[i].data1 << 16;
586 resource->actions_num = ++i;
591 * Convert modify-header set TP action to DV specification.
593 * @param[in,out] resource
594 * Pointer to the modify-header resource.
596 * Pointer to action specification.
598 * Pointer to rte_flow_item objects list.
600 * Pointer to flow attributes structure.
602 * Pointer to the error structure.
605 * 0 on success, a negative errno value otherwise and rte_errno is set.
608 flow_dv_convert_action_modify_tp
609 (struct mlx5_flow_dv_modify_hdr_resource *resource,
610 const struct rte_flow_action *action,
611 const struct rte_flow_item *items,
612 union flow_dv_attr *attr,
613 struct rte_flow_error *error)
615 const struct rte_flow_action_set_tp *conf =
616 (const struct rte_flow_action_set_tp *)(action->conf);
617 struct rte_flow_item item;
618 struct rte_flow_item_udp udp;
619 struct rte_flow_item_udp udp_mask;
620 struct rte_flow_item_tcp tcp;
621 struct rte_flow_item_tcp tcp_mask;
622 struct field_modify_info *field;
625 flow_dv_attr_init(items, attr);
627 memset(&udp, 0, sizeof(udp));
628 memset(&udp_mask, 0, sizeof(udp_mask));
629 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
630 udp.hdr.src_port = conf->port;
631 udp_mask.hdr.src_port =
632 rte_flow_item_udp_mask.hdr.src_port;
634 udp.hdr.dst_port = conf->port;
635 udp_mask.hdr.dst_port =
636 rte_flow_item_udp_mask.hdr.dst_port;
638 item.type = RTE_FLOW_ITEM_TYPE_UDP;
640 item.mask = &udp_mask;
644 memset(&tcp, 0, sizeof(tcp));
645 memset(&tcp_mask, 0, sizeof(tcp_mask));
646 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
647 tcp.hdr.src_port = conf->port;
648 tcp_mask.hdr.src_port =
649 rte_flow_item_tcp_mask.hdr.src_port;
651 tcp.hdr.dst_port = conf->port;
652 tcp_mask.hdr.dst_port =
653 rte_flow_item_tcp_mask.hdr.dst_port;
655 item.type = RTE_FLOW_ITEM_TYPE_TCP;
657 item.mask = &tcp_mask;
660 return flow_dv_convert_modify_action(&item, field, NULL, resource,
661 MLX5_MODIFICATION_TYPE_SET, error);
665 * Convert modify-header set TTL action to DV specification.
667 * @param[in,out] resource
668 * Pointer to the modify-header resource.
670 * Pointer to action specification.
672 * Pointer to rte_flow_item objects list.
674 * Pointer to flow attributes structure.
676 * Pointer to the error structure.
679 * 0 on success, a negative errno value otherwise and rte_errno is set.
682 flow_dv_convert_action_modify_ttl
683 (struct mlx5_flow_dv_modify_hdr_resource *resource,
684 const struct rte_flow_action *action,
685 const struct rte_flow_item *items,
686 union flow_dv_attr *attr,
687 struct rte_flow_error *error)
689 const struct rte_flow_action_set_ttl *conf =
690 (const struct rte_flow_action_set_ttl *)(action->conf);
691 struct rte_flow_item item;
692 struct rte_flow_item_ipv4 ipv4;
693 struct rte_flow_item_ipv4 ipv4_mask;
694 struct rte_flow_item_ipv6 ipv6;
695 struct rte_flow_item_ipv6 ipv6_mask;
696 struct field_modify_info *field;
699 flow_dv_attr_init(items, attr);
701 memset(&ipv4, 0, sizeof(ipv4));
702 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
703 ipv4.hdr.time_to_live = conf->ttl_value;
704 ipv4_mask.hdr.time_to_live = 0xFF;
705 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
707 item.mask = &ipv4_mask;
711 memset(&ipv6, 0, sizeof(ipv6));
712 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
713 ipv6.hdr.hop_limits = conf->ttl_value;
714 ipv6_mask.hdr.hop_limits = 0xFF;
715 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
717 item.mask = &ipv6_mask;
720 return flow_dv_convert_modify_action(&item, field, NULL, resource,
721 MLX5_MODIFICATION_TYPE_SET, error);
725 * Convert modify-header decrement TTL action to DV specification.
727 * @param[in,out] resource
728 * Pointer to the modify-header resource.
730 * Pointer to action specification.
732 * Pointer to rte_flow_item objects list.
734 * Pointer to flow attributes structure.
736 * Pointer to the error structure.
739 * 0 on success, a negative errno value otherwise and rte_errno is set.
742 flow_dv_convert_action_modify_dec_ttl
743 (struct mlx5_flow_dv_modify_hdr_resource *resource,
744 const struct rte_flow_item *items,
745 union flow_dv_attr *attr,
746 struct rte_flow_error *error)
748 struct rte_flow_item item;
749 struct rte_flow_item_ipv4 ipv4;
750 struct rte_flow_item_ipv4 ipv4_mask;
751 struct rte_flow_item_ipv6 ipv6;
752 struct rte_flow_item_ipv6 ipv6_mask;
753 struct field_modify_info *field;
756 flow_dv_attr_init(items, attr);
758 memset(&ipv4, 0, sizeof(ipv4));
759 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
760 ipv4.hdr.time_to_live = 0xFF;
761 ipv4_mask.hdr.time_to_live = 0xFF;
762 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
764 item.mask = &ipv4_mask;
768 memset(&ipv6, 0, sizeof(ipv6));
769 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
770 ipv6.hdr.hop_limits = 0xFF;
771 ipv6_mask.hdr.hop_limits = 0xFF;
772 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
774 item.mask = &ipv6_mask;
777 return flow_dv_convert_modify_action(&item, field, NULL, resource,
778 MLX5_MODIFICATION_TYPE_ADD, error);
782 * Convert modify-header increment/decrement TCP Sequence number
783 * to DV specification.
785 * @param[in,out] resource
786 * Pointer to the modify-header resource.
788 * Pointer to action specification.
790 * Pointer to the error structure.
793 * 0 on success, a negative errno value otherwise and rte_errno is set.
796 flow_dv_convert_action_modify_tcp_seq
797 (struct mlx5_flow_dv_modify_hdr_resource *resource,
798 const struct rte_flow_action *action,
799 struct rte_flow_error *error)
801 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
802 uint64_t value = rte_be_to_cpu_32(*conf);
803 struct rte_flow_item item;
804 struct rte_flow_item_tcp tcp;
805 struct rte_flow_item_tcp tcp_mask;
807 memset(&tcp, 0, sizeof(tcp));
808 memset(&tcp_mask, 0, sizeof(tcp_mask));
809 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
811 * The HW has no decrement operation, only increment operation.
812 * To simulate decrement X from Y using increment operation
813 * we need to add UINT32_MAX X times to Y.
814 * Each adding of UINT32_MAX decrements Y by 1.
817 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
818 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
819 item.type = RTE_FLOW_ITEM_TYPE_TCP;
821 item.mask = &tcp_mask;
822 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
823 MLX5_MODIFICATION_TYPE_ADD, error);
827 * Convert modify-header increment/decrement TCP Acknowledgment number
828 * to DV specification.
830 * @param[in,out] resource
831 * Pointer to the modify-header resource.
833 * Pointer to action specification.
835 * Pointer to the error structure.
838 * 0 on success, a negative errno value otherwise and rte_errno is set.
841 flow_dv_convert_action_modify_tcp_ack
842 (struct mlx5_flow_dv_modify_hdr_resource *resource,
843 const struct rte_flow_action *action,
844 struct rte_flow_error *error)
846 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
847 uint64_t value = rte_be_to_cpu_32(*conf);
848 struct rte_flow_item item;
849 struct rte_flow_item_tcp tcp;
850 struct rte_flow_item_tcp tcp_mask;
852 memset(&tcp, 0, sizeof(tcp));
853 memset(&tcp_mask, 0, sizeof(tcp_mask));
854 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
856 * The HW has no decrement operation, only increment operation.
857 * To simulate decrement X from Y using increment operation
858 * we need to add UINT32_MAX X times to Y.
859 * Each adding of UINT32_MAX decrements Y by 1.
862 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
863 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
864 item.type = RTE_FLOW_ITEM_TYPE_TCP;
866 item.mask = &tcp_mask;
867 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
868 MLX5_MODIFICATION_TYPE_ADD, error);
871 static enum mlx5_modification_field reg_to_field[] = {
872 [REG_NONE] = MLX5_MODI_OUT_NONE,
873 [REG_A] = MLX5_MODI_META_DATA_REG_A,
874 [REG_B] = MLX5_MODI_META_DATA_REG_B,
875 [REG_C_0] = MLX5_MODI_META_REG_C_0,
876 [REG_C_1] = MLX5_MODI_META_REG_C_1,
877 [REG_C_2] = MLX5_MODI_META_REG_C_2,
878 [REG_C_3] = MLX5_MODI_META_REG_C_3,
879 [REG_C_4] = MLX5_MODI_META_REG_C_4,
880 [REG_C_5] = MLX5_MODI_META_REG_C_5,
881 [REG_C_6] = MLX5_MODI_META_REG_C_6,
882 [REG_C_7] = MLX5_MODI_META_REG_C_7,
886 * Convert register set to DV specification.
888 * @param[in,out] resource
889 * Pointer to the modify-header resource.
891 * Pointer to action specification.
893 * Pointer to the error structure.
896 * 0 on success, a negative errno value otherwise and rte_errno is set.
899 flow_dv_convert_action_set_reg
900 (struct mlx5_flow_dv_modify_hdr_resource *resource,
901 const struct rte_flow_action *action,
902 struct rte_flow_error *error)
904 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
905 struct mlx5_modification_cmd *actions = resource->actions;
906 uint32_t i = resource->actions_num;
908 if (i >= MLX5_MAX_MODIFY_NUM)
909 return rte_flow_error_set(error, EINVAL,
910 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
911 "too many items to modify");
912 assert(conf->id != REG_NONE);
913 assert(conf->id < RTE_DIM(reg_to_field));
914 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
915 actions[i].field = reg_to_field[conf->id];
916 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
917 actions[i].data1 = rte_cpu_to_be_32(conf->data);
919 resource->actions_num = i;
924 * Convert SET_TAG action to DV specification.
927 * Pointer to the rte_eth_dev structure.
928 * @param[in,out] resource
929 * Pointer to the modify-header resource.
931 * Pointer to action specification.
933 * Pointer to the error structure.
936 * 0 on success, a negative errno value otherwise and rte_errno is set.
939 flow_dv_convert_action_set_tag
940 (struct rte_eth_dev *dev,
941 struct mlx5_flow_dv_modify_hdr_resource *resource,
942 const struct rte_flow_action_set_tag *conf,
943 struct rte_flow_error *error)
945 rte_be32_t data = rte_cpu_to_be_32(conf->data);
946 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
947 struct rte_flow_item item = {
951 struct field_modify_info reg_c_x[] = {
954 enum mlx5_modification_field reg_type;
957 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
960 assert(ret != REG_NONE);
961 assert((unsigned int)ret < RTE_DIM(reg_to_field));
962 reg_type = reg_to_field[ret];
963 assert(reg_type > 0);
964 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
965 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
966 MLX5_MODIFICATION_TYPE_SET, error);
970 * Convert internal COPY_REG action to DV specification.
973 * Pointer to the rte_eth_dev structure.
975 * Pointer to the modify-header resource.
977 * Pointer to action specification.
979 * Pointer to the error structure.
982 * 0 on success, a negative errno value otherwise and rte_errno is set.
985 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
986 struct mlx5_flow_dv_modify_hdr_resource *res,
987 const struct rte_flow_action *action,
988 struct rte_flow_error *error)
990 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
991 rte_be32_t mask = RTE_BE32(UINT32_MAX);
992 struct rte_flow_item item = {
996 struct field_modify_info reg_src[] = {
997 {4, 0, reg_to_field[conf->src]},
1000 struct field_modify_info reg_dst = {
1002 .id = reg_to_field[conf->dst],
1004 /* Adjust reg_c[0] usage according to reported mask. */
1005 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1006 struct mlx5_priv *priv = dev->data->dev_private;
1007 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1010 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1011 if (conf->dst == REG_C_0) {
1012 /* Copy to reg_c[0], within mask only. */
1013 reg_dst.offset = rte_bsf32(reg_c0);
1015 * Mask is ignoring the enianness, because
1016 * there is no conversion in datapath.
1018 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1019 /* Copy from destination lower bits to reg_c[0]. */
1020 mask = reg_c0 >> reg_dst.offset;
1022 /* Copy from destination upper bits to reg_c[0]. */
1023 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1024 rte_fls_u32(reg_c0));
1027 mask = rte_cpu_to_be_32(reg_c0);
1028 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1029 /* Copy from reg_c[0] to destination lower bits. */
1032 /* Copy from reg_c[0] to destination upper bits. */
1033 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1034 (rte_fls_u32(reg_c0) -
1039 return flow_dv_convert_modify_action(&item,
1040 reg_src, ®_dst, res,
1041 MLX5_MODIFICATION_TYPE_COPY,
1046 * Convert MARK action to DV specification. This routine is used
1047 * in extensive metadata only and requires metadata register to be
1048 * handled. In legacy mode hardware tag resource is engaged.
1051 * Pointer to the rte_eth_dev structure.
1053 * Pointer to MARK action specification.
1054 * @param[in,out] resource
1055 * Pointer to the modify-header resource.
1057 * Pointer to the error structure.
1060 * 0 on success, a negative errno value otherwise and rte_errno is set.
1063 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1064 const struct rte_flow_action_mark *conf,
1065 struct mlx5_flow_dv_modify_hdr_resource *resource,
1066 struct rte_flow_error *error)
1068 struct mlx5_priv *priv = dev->data->dev_private;
1069 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1070 priv->sh->dv_mark_mask);
1071 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1072 struct rte_flow_item item = {
1076 struct field_modify_info reg_c_x[] = {
1077 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1080 enum modify_reg reg;
1083 return rte_flow_error_set(error, EINVAL,
1084 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1085 NULL, "zero mark action mask");
1086 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1090 if (reg == REG_C_0) {
1091 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1092 uint32_t shl_c0 = rte_bsf32(msk_c0);
1094 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1095 mask = rte_cpu_to_be_32(mask) & msk_c0;
1096 mask = rte_cpu_to_be_32(mask << shl_c0);
1098 reg_c_x[0].id = reg_to_field[reg];
1099 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1100 MLX5_MODIFICATION_TYPE_SET, error);
1104 * Get metadata register index for specified steering domain.
1107 * Pointer to the rte_eth_dev structure.
1109 * Attributes of flow to determine steering domain.
1111 * Pointer to the error structure.
1114 * positive index on success, a negative errno value otherwise
1115 * and rte_errno is set.
1117 static enum modify_reg
1118 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1119 const struct rte_flow_attr *attr,
1120 struct rte_flow_error *error)
1122 enum modify_reg reg =
1123 mlx5_flow_get_reg_id(dev, attr->transfer ?
1127 MLX5_METADATA_RX, 0, error);
1129 return rte_flow_error_set(error,
1130 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1131 NULL, "unavailable "
1132 "metadata register");
1137 * Convert SET_META action to DV specification.
1140 * Pointer to the rte_eth_dev structure.
1141 * @param[in,out] resource
1142 * Pointer to the modify-header resource.
1144 * Attributes of flow that includes this item.
1146 * Pointer to action specification.
1148 * Pointer to the error structure.
1151 * 0 on success, a negative errno value otherwise and rte_errno is set.
1154 flow_dv_convert_action_set_meta
1155 (struct rte_eth_dev *dev,
1156 struct mlx5_flow_dv_modify_hdr_resource *resource,
1157 const struct rte_flow_attr *attr,
1158 const struct rte_flow_action_set_meta *conf,
1159 struct rte_flow_error *error)
1161 uint32_t data = conf->data;
1162 uint32_t mask = conf->mask;
1163 struct rte_flow_item item = {
1167 struct field_modify_info reg_c_x[] = {
1170 enum modify_reg reg = flow_dv_get_metadata_reg(dev, attr, error);
1175 * In datapath code there is no endianness
1176 * coversions for perfromance reasons, all
1177 * pattern conversions are done in rte_flow.
1179 if (reg == REG_C_0) {
1180 struct mlx5_priv *priv = dev->data->dev_private;
1181 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1185 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1186 shl_c0 = rte_bsf32(msk_c0);
1188 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1192 assert(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1194 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1195 /* The routine expects parameters in memory as big-endian ones. */
1196 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1197 MLX5_MODIFICATION_TYPE_SET, error);
1201 * Convert modify-header set IPv4 DSCP action to DV specification.
1203 * @param[in,out] resource
1204 * Pointer to the modify-header resource.
1206 * Pointer to action specification.
1208 * Pointer to the error structure.
1211 * 0 on success, a negative errno value otherwise and rte_errno is set.
1214 flow_dv_convert_action_modify_ipv4_dscp
1215 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1216 const struct rte_flow_action *action,
1217 struct rte_flow_error *error)
1219 const struct rte_flow_action_set_dscp *conf =
1220 (const struct rte_flow_action_set_dscp *)(action->conf);
1221 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1222 struct rte_flow_item_ipv4 ipv4;
1223 struct rte_flow_item_ipv4 ipv4_mask;
1225 memset(&ipv4, 0, sizeof(ipv4));
1226 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1227 ipv4.hdr.type_of_service = conf->dscp;
1228 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1230 item.mask = &ipv4_mask;
1231 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1232 MLX5_MODIFICATION_TYPE_SET, error);
1236 * Convert modify-header set IPv6 DSCP action to DV specification.
1238 * @param[in,out] resource
1239 * Pointer to the modify-header resource.
1241 * Pointer to action specification.
1243 * Pointer to the error structure.
1246 * 0 on success, a negative errno value otherwise and rte_errno is set.
1249 flow_dv_convert_action_modify_ipv6_dscp
1250 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1251 const struct rte_flow_action *action,
1252 struct rte_flow_error *error)
1254 const struct rte_flow_action_set_dscp *conf =
1255 (const struct rte_flow_action_set_dscp *)(action->conf);
1256 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1257 struct rte_flow_item_ipv6 ipv6;
1258 struct rte_flow_item_ipv6 ipv6_mask;
1260 memset(&ipv6, 0, sizeof(ipv6));
1261 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1263 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1264 * rdma-core only accept the DSCP bits byte aligned start from
1265 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1266 * bits in IPv6 case as rdma-core requires byte aligned value.
1268 ipv6.hdr.vtc_flow = conf->dscp;
1269 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1271 item.mask = &ipv6_mask;
1272 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1273 MLX5_MODIFICATION_TYPE_SET, error);
1277 * Validate MARK item.
1280 * Pointer to the rte_eth_dev structure.
1282 * Item specification.
1284 * Attributes of flow that includes this item.
1286 * Pointer to error structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1293 const struct rte_flow_item *item,
1294 const struct rte_flow_attr *attr __rte_unused,
1295 struct rte_flow_error *error)
1297 struct mlx5_priv *priv = dev->data->dev_private;
1298 struct mlx5_dev_config *config = &priv->config;
1299 const struct rte_flow_item_mark *spec = item->spec;
1300 const struct rte_flow_item_mark *mask = item->mask;
1301 const struct rte_flow_item_mark nic_mask = {
1302 .id = priv->sh->dv_mark_mask,
1306 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1307 return rte_flow_error_set(error, ENOTSUP,
1308 RTE_FLOW_ERROR_TYPE_ITEM, item,
1309 "extended metadata feature"
1311 if (!mlx5_flow_ext_mreg_supported(dev))
1312 return rte_flow_error_set(error, ENOTSUP,
1313 RTE_FLOW_ERROR_TYPE_ITEM, item,
1314 "extended metadata register"
1315 " isn't supported");
1317 return rte_flow_error_set(error, ENOTSUP,
1318 RTE_FLOW_ERROR_TYPE_ITEM, item,
1319 "extended metadata register"
1320 " isn't available");
1321 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1325 return rte_flow_error_set(error, EINVAL,
1326 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1328 "data cannot be empty");
1329 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1330 return rte_flow_error_set(error, EINVAL,
1331 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1333 "mark id exceeds the limit");
1336 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1337 (const uint8_t *)&nic_mask,
1338 sizeof(struct rte_flow_item_mark),
1346 * Validate META item.
1349 * Pointer to the rte_eth_dev structure.
1351 * Item specification.
1353 * Attributes of flow that includes this item.
1355 * Pointer to error structure.
1358 * 0 on success, a negative errno value otherwise and rte_errno is set.
1361 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1362 const struct rte_flow_item *item,
1363 const struct rte_flow_attr *attr,
1364 struct rte_flow_error *error)
1366 struct mlx5_priv *priv = dev->data->dev_private;
1367 struct mlx5_dev_config *config = &priv->config;
1368 const struct rte_flow_item_meta *spec = item->spec;
1369 const struct rte_flow_item_meta *mask = item->mask;
1370 struct rte_flow_item_meta nic_mask = {
1373 enum modify_reg reg;
1377 return rte_flow_error_set(error, EINVAL,
1378 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1380 "data cannot be empty");
1382 return rte_flow_error_set(error, EINVAL,
1383 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1384 "data cannot be zero");
1385 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1386 if (!mlx5_flow_ext_mreg_supported(dev))
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata register"
1390 " isn't supported");
1391 reg = flow_dv_get_metadata_reg(dev, attr, error);
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1400 nic_mask.data = priv->sh->dv_meta_mask;
1403 mask = &rte_flow_item_meta_mask;
1404 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1405 (const uint8_t *)&nic_mask,
1406 sizeof(struct rte_flow_item_meta),
1412 * Validate TAG item.
1415 * Pointer to the rte_eth_dev structure.
1417 * Item specification.
1419 * Attributes of flow that includes this item.
1421 * Pointer to error structure.
1424 * 0 on success, a negative errno value otherwise and rte_errno is set.
1427 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1428 const struct rte_flow_item *item,
1429 const struct rte_flow_attr *attr __rte_unused,
1430 struct rte_flow_error *error)
1432 const struct rte_flow_item_tag *spec = item->spec;
1433 const struct rte_flow_item_tag *mask = item->mask;
1434 const struct rte_flow_item_tag nic_mask = {
1435 .data = RTE_BE32(UINT32_MAX),
1440 if (!mlx5_flow_ext_mreg_supported(dev))
1441 return rte_flow_error_set(error, ENOTSUP,
1442 RTE_FLOW_ERROR_TYPE_ITEM, item,
1443 "extensive metadata register"
1444 " isn't supported");
1446 return rte_flow_error_set(error, EINVAL,
1447 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1449 "data cannot be empty");
1451 mask = &rte_flow_item_tag_mask;
1452 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1453 (const uint8_t *)&nic_mask,
1454 sizeof(struct rte_flow_item_tag),
1458 if (mask->index != 0xff)
1459 return rte_flow_error_set(error, EINVAL,
1460 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1461 "partial mask for tag index"
1462 " is not supported");
1463 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1466 assert(ret != REG_NONE);
1471 * Validate vport item.
1474 * Pointer to the rte_eth_dev structure.
1476 * Item specification.
1478 * Attributes of flow that includes this item.
1479 * @param[in] item_flags
1480 * Bit-fields that holds the items detected until now.
1482 * Pointer to error structure.
1485 * 0 on success, a negative errno value otherwise and rte_errno is set.
1488 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1489 const struct rte_flow_item *item,
1490 const struct rte_flow_attr *attr,
1491 uint64_t item_flags,
1492 struct rte_flow_error *error)
1494 const struct rte_flow_item_port_id *spec = item->spec;
1495 const struct rte_flow_item_port_id *mask = item->mask;
1496 const struct rte_flow_item_port_id switch_mask = {
1499 struct mlx5_priv *esw_priv;
1500 struct mlx5_priv *dev_priv;
1503 if (!attr->transfer)
1504 return rte_flow_error_set(error, EINVAL,
1505 RTE_FLOW_ERROR_TYPE_ITEM,
1507 "match on port id is valid only"
1508 " when transfer flag is enabled");
1509 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1510 return rte_flow_error_set(error, ENOTSUP,
1511 RTE_FLOW_ERROR_TYPE_ITEM, item,
1512 "multiple source ports are not"
1515 mask = &switch_mask;
1516 if (mask->id != 0xffffffff)
1517 return rte_flow_error_set(error, ENOTSUP,
1518 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1520 "no support for partial mask on"
1522 ret = mlx5_flow_item_acceptable
1523 (item, (const uint8_t *)mask,
1524 (const uint8_t *)&rte_flow_item_port_id_mask,
1525 sizeof(struct rte_flow_item_port_id),
1531 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1533 return rte_flow_error_set(error, rte_errno,
1534 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1535 "failed to obtain E-Switch info for"
1537 dev_priv = mlx5_dev_to_eswitch_info(dev);
1539 return rte_flow_error_set(error, rte_errno,
1540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1542 "failed to obtain E-Switch info");
1543 if (esw_priv->domain_id != dev_priv->domain_id)
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1546 "cannot match on a port from a"
1547 " different E-Switch");
1552 * Validate GTP item.
1555 * Pointer to the rte_eth_dev structure.
1557 * Item specification.
1558 * @param[in] item_flags
1559 * Bit-fields that holds the items detected until now.
1561 * Pointer to error structure.
1564 * 0 on success, a negative errno value otherwise and rte_errno is set.
1567 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1568 const struct rte_flow_item *item,
1569 uint64_t item_flags,
1570 struct rte_flow_error *error)
1572 struct mlx5_priv *priv = dev->data->dev_private;
1573 const struct rte_flow_item_gtp *mask = item->mask;
1574 const struct rte_flow_item_gtp nic_mask = {
1576 .teid = RTE_BE32(0xffffffff),
1579 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1580 return rte_flow_error_set(error, ENOTSUP,
1581 RTE_FLOW_ERROR_TYPE_ITEM, item,
1582 "GTP support is not enabled");
1583 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1584 return rte_flow_error_set(error, ENOTSUP,
1585 RTE_FLOW_ERROR_TYPE_ITEM, item,
1586 "multiple tunnel layers not"
1588 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1589 return rte_flow_error_set(error, EINVAL,
1590 RTE_FLOW_ERROR_TYPE_ITEM, item,
1591 "no outer UDP layer found");
1593 mask = &rte_flow_item_gtp_mask;
1594 return mlx5_flow_item_acceptable
1595 (item, (const uint8_t *)mask,
1596 (const uint8_t *)&nic_mask,
1597 sizeof(struct rte_flow_item_gtp),
1602 * Validate the pop VLAN action.
1605 * Pointer to the rte_eth_dev structure.
1606 * @param[in] action_flags
1607 * Holds the actions detected until now.
1609 * Pointer to the pop vlan action.
1610 * @param[in] item_flags
1611 * The items found in this flow rule.
1613 * Pointer to flow attributes.
1615 * Pointer to error structure.
1618 * 0 on success, a negative errno value otherwise and rte_errno is set.
1621 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1622 uint64_t action_flags,
1623 const struct rte_flow_action *action,
1624 uint64_t item_flags,
1625 const struct rte_flow_attr *attr,
1626 struct rte_flow_error *error)
1628 struct mlx5_priv *priv = dev->data->dev_private;
1632 if (!priv->sh->pop_vlan_action)
1633 return rte_flow_error_set(error, ENOTSUP,
1634 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1636 "pop vlan action is not supported");
1638 * Check for inconsistencies:
1639 * fail strip_vlan in a flow that matches packets without VLAN tags.
1640 * fail strip_vlan in a flow that matches packets without explicitly a
1641 * matching on VLAN tag ?
1643 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1644 return rte_flow_error_set(error, ENOTSUP,
1645 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1647 "no support for multiple vlan pop "
1649 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1650 return rte_flow_error_set(error, ENOTSUP,
1651 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1653 "cannot pop vlan without a "
1654 "match on (outer) vlan in the flow");
1655 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1656 return rte_flow_error_set(error, EINVAL,
1657 RTE_FLOW_ERROR_TYPE_ACTION, action,
1658 "wrong action order, port_id should "
1659 "be after pop VLAN action");
1664 * Get VLAN default info from vlan match info.
1667 * Pointer to the rte_eth_dev structure.
1669 * the list of item specifications.
1671 * pointer VLAN info to fill to.
1673 * Pointer to error structure.
1676 * 0 on success, a negative errno value otherwise and rte_errno is set.
1679 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1680 struct rte_vlan_hdr *vlan)
1682 const struct rte_flow_item_vlan nic_mask = {
1683 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1684 MLX5DV_FLOW_VLAN_VID_MASK),
1685 .inner_type = RTE_BE16(0xffff),
1690 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1691 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1693 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1694 const struct rte_flow_item_vlan *vlan_m = items->mask;
1695 const struct rte_flow_item_vlan *vlan_v = items->spec;
1699 /* Only full match values are accepted */
1700 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1701 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1702 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1704 rte_be_to_cpu_16(vlan_v->tci &
1705 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1707 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1708 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1709 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1711 rte_be_to_cpu_16(vlan_v->tci &
1712 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1714 if (vlan_m->inner_type == nic_mask.inner_type)
1715 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1716 vlan_m->inner_type);
1721 * Validate the push VLAN action.
1723 * @param[in] action_flags
1724 * Holds the actions detected until now.
1726 * Pointer to the encap action.
1728 * Pointer to flow attributes
1730 * Pointer to error structure.
1733 * 0 on success, a negative errno value otherwise and rte_errno is set.
1736 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1737 uint64_t item_flags,
1738 const struct rte_flow_action *action,
1739 const struct rte_flow_attr *attr,
1740 struct rte_flow_error *error)
1742 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1744 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1745 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1746 return rte_flow_error_set(error, EINVAL,
1747 RTE_FLOW_ERROR_TYPE_ACTION, action,
1748 "invalid vlan ethertype");
1750 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1751 return rte_flow_error_set(error, ENOTSUP,
1752 RTE_FLOW_ERROR_TYPE_ACTION, action,
1753 "no support for multiple VLAN "
1755 if (!mlx5_flow_find_action
1756 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1757 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1758 return rte_flow_error_set(error, ENOTSUP,
1759 RTE_FLOW_ERROR_TYPE_ACTION, action,
1760 "push VLAN needs to match on VLAN in order to "
1761 "get VLAN VID information because there is "
1762 "no followed set VLAN VID action");
1763 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1764 return rte_flow_error_set(error, EINVAL,
1765 RTE_FLOW_ERROR_TYPE_ACTION, action,
1766 "wrong action order, port_id should "
1767 "be after push VLAN");
1773 * Validate the set VLAN PCP.
1775 * @param[in] action_flags
1776 * Holds the actions detected until now.
1777 * @param[in] actions
1778 * Pointer to the list of actions remaining in the flow rule.
1780 * Pointer to flow attributes
1782 * Pointer to error structure.
1785 * 0 on success, a negative errno value otherwise and rte_errno is set.
1788 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1789 const struct rte_flow_action actions[],
1790 struct rte_flow_error *error)
1792 const struct rte_flow_action *action = actions;
1793 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1795 if (conf->vlan_pcp > 7)
1796 return rte_flow_error_set(error, EINVAL,
1797 RTE_FLOW_ERROR_TYPE_ACTION, action,
1798 "VLAN PCP value is too big");
1799 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1800 return rte_flow_error_set(error, ENOTSUP,
1801 RTE_FLOW_ERROR_TYPE_ACTION, action,
1802 "set VLAN PCP action must follow "
1803 "the push VLAN action");
1804 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1805 return rte_flow_error_set(error, ENOTSUP,
1806 RTE_FLOW_ERROR_TYPE_ACTION, action,
1807 "Multiple VLAN PCP modification are "
1809 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1810 return rte_flow_error_set(error, EINVAL,
1811 RTE_FLOW_ERROR_TYPE_ACTION, action,
1812 "wrong action order, port_id should "
1813 "be after set VLAN PCP");
1818 * Validate the set VLAN VID.
1820 * @param[in] item_flags
1821 * Holds the items detected in this rule.
1822 * @param[in] actions
1823 * Pointer to the list of actions remaining in the flow rule.
1825 * Pointer to flow attributes
1827 * Pointer to error structure.
1830 * 0 on success, a negative errno value otherwise and rte_errno is set.
1833 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1834 uint64_t action_flags,
1835 const struct rte_flow_action actions[],
1836 struct rte_flow_error *error)
1838 const struct rte_flow_action *action = actions;
1839 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1841 if (conf->vlan_vid > RTE_BE16(0xFFE))
1842 return rte_flow_error_set(error, EINVAL,
1843 RTE_FLOW_ERROR_TYPE_ACTION, action,
1844 "VLAN VID value is too big");
1845 /* there is an of_push_vlan action before us */
1846 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1847 if (mlx5_flow_find_action(actions + 1,
1848 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1849 return rte_flow_error_set(error, ENOTSUP,
1850 RTE_FLOW_ERROR_TYPE_ACTION, action,
1851 "Multiple VLAN VID modifications are "
1858 * Action is on an existing VLAN header:
1859 * Need to verify this is a single modify CID action.
1860 * Rule mast include a match on outer VLAN.
1862 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1863 return rte_flow_error_set(error, ENOTSUP,
1864 RTE_FLOW_ERROR_TYPE_ACTION, action,
1865 "Multiple VLAN VID modifications are "
1867 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1868 return rte_flow_error_set(error, EINVAL,
1869 RTE_FLOW_ERROR_TYPE_ACTION, action,
1870 "match on VLAN is required in order "
1872 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1873 return rte_flow_error_set(error, EINVAL,
1874 RTE_FLOW_ERROR_TYPE_ACTION, action,
1875 "wrong action order, port_id should "
1876 "be after set VLAN VID");
1881 * Validate the FLAG action.
1884 * Pointer to the rte_eth_dev structure.
1885 * @param[in] action_flags
1886 * Holds the actions detected until now.
1888 * Pointer to flow attributes
1890 * Pointer to error structure.
1893 * 0 on success, a negative errno value otherwise and rte_errno is set.
1896 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1897 uint64_t action_flags,
1898 const struct rte_flow_attr *attr,
1899 struct rte_flow_error *error)
1901 struct mlx5_priv *priv = dev->data->dev_private;
1902 struct mlx5_dev_config *config = &priv->config;
1905 /* Fall back if no extended metadata register support. */
1906 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1907 return mlx5_flow_validate_action_flag(action_flags, attr,
1909 /* Extensive metadata mode requires registers. */
1910 if (!mlx5_flow_ext_mreg_supported(dev))
1911 return rte_flow_error_set(error, ENOTSUP,
1912 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1913 "no metadata registers "
1914 "to support flag action");
1915 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1916 return rte_flow_error_set(error, ENOTSUP,
1917 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1918 "extended metadata register"
1919 " isn't available");
1920 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1924 if (action_flags & MLX5_FLOW_ACTION_DROP)
1925 return rte_flow_error_set(error, EINVAL,
1926 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1927 "can't drop and flag in same flow");
1928 if (action_flags & MLX5_FLOW_ACTION_MARK)
1929 return rte_flow_error_set(error, EINVAL,
1930 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1931 "can't mark and flag in same flow");
1932 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1933 return rte_flow_error_set(error, EINVAL,
1934 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1936 " actions in same flow");
1941 * Validate MARK action.
1944 * Pointer to the rte_eth_dev structure.
1946 * Pointer to action.
1947 * @param[in] action_flags
1948 * Holds the actions detected until now.
1950 * Pointer to flow attributes
1952 * Pointer to error structure.
1955 * 0 on success, a negative errno value otherwise and rte_errno is set.
1958 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1959 const struct rte_flow_action *action,
1960 uint64_t action_flags,
1961 const struct rte_flow_attr *attr,
1962 struct rte_flow_error *error)
1964 struct mlx5_priv *priv = dev->data->dev_private;
1965 struct mlx5_dev_config *config = &priv->config;
1966 const struct rte_flow_action_mark *mark = action->conf;
1969 /* Fall back if no extended metadata register support. */
1970 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1971 return mlx5_flow_validate_action_mark(action, action_flags,
1973 /* Extensive metadata mode requires registers. */
1974 if (!mlx5_flow_ext_mreg_supported(dev))
1975 return rte_flow_error_set(error, ENOTSUP,
1976 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1977 "no metadata registers "
1978 "to support mark action");
1979 if (!priv->sh->dv_mark_mask)
1980 return rte_flow_error_set(error, ENOTSUP,
1981 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1982 "extended metadata register"
1983 " isn't available");
1984 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1989 return rte_flow_error_set(error, EINVAL,
1990 RTE_FLOW_ERROR_TYPE_ACTION, action,
1991 "configuration cannot be null");
1992 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1993 return rte_flow_error_set(error, EINVAL,
1994 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1996 "mark id exceeds the limit");
1997 if (action_flags & MLX5_FLOW_ACTION_DROP)
1998 return rte_flow_error_set(error, EINVAL,
1999 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2000 "can't drop and mark in same flow");
2001 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2002 return rte_flow_error_set(error, EINVAL,
2003 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2004 "can't flag and mark in same flow");
2005 if (action_flags & MLX5_FLOW_ACTION_MARK)
2006 return rte_flow_error_set(error, EINVAL,
2007 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2008 "can't have 2 mark actions in same"
2014 * Validate SET_META action.
2017 * Pointer to the rte_eth_dev structure.
2019 * Pointer to the encap action.
2020 * @param[in] action_flags
2021 * Holds the actions detected until now.
2023 * Pointer to flow attributes
2025 * Pointer to error structure.
2028 * 0 on success, a negative errno value otherwise and rte_errno is set.
2031 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2032 const struct rte_flow_action *action,
2033 uint64_t action_flags __rte_unused,
2034 const struct rte_flow_attr *attr,
2035 struct rte_flow_error *error)
2037 const struct rte_flow_action_set_meta *conf;
2038 uint32_t nic_mask = UINT32_MAX;
2039 enum modify_reg reg;
2041 if (!mlx5_flow_ext_mreg_supported(dev))
2042 return rte_flow_error_set(error, ENOTSUP,
2043 RTE_FLOW_ERROR_TYPE_ACTION, action,
2044 "extended metadata register"
2045 " isn't supported");
2046 reg = flow_dv_get_metadata_reg(dev, attr, error);
2049 if (reg != REG_A && reg != REG_B) {
2050 struct mlx5_priv *priv = dev->data->dev_private;
2052 nic_mask = priv->sh->dv_meta_mask;
2054 if (!(action->conf))
2055 return rte_flow_error_set(error, EINVAL,
2056 RTE_FLOW_ERROR_TYPE_ACTION, action,
2057 "configuration cannot be null");
2058 conf = (const struct rte_flow_action_set_meta *)action->conf;
2060 return rte_flow_error_set(error, EINVAL,
2061 RTE_FLOW_ERROR_TYPE_ACTION, action,
2062 "zero mask doesn't have any effect");
2063 if (conf->mask & ~nic_mask)
2064 return rte_flow_error_set(error, EINVAL,
2065 RTE_FLOW_ERROR_TYPE_ACTION, action,
2066 "meta data must be within reg C0");
2067 if (!(conf->data & conf->mask))
2068 return rte_flow_error_set(error, EINVAL,
2069 RTE_FLOW_ERROR_TYPE_ACTION, action,
2070 "zero value has no effect");
2075 * Validate SET_TAG action.
2078 * Pointer to the rte_eth_dev structure.
2080 * Pointer to the encap action.
2081 * @param[in] action_flags
2082 * Holds the actions detected until now.
2084 * Pointer to flow attributes
2086 * Pointer to error structure.
2089 * 0 on success, a negative errno value otherwise and rte_errno is set.
2092 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2093 const struct rte_flow_action *action,
2094 uint64_t action_flags,
2095 const struct rte_flow_attr *attr,
2096 struct rte_flow_error *error)
2098 const struct rte_flow_action_set_tag *conf;
2099 const uint64_t terminal_action_flags =
2100 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2101 MLX5_FLOW_ACTION_RSS;
2104 if (!mlx5_flow_ext_mreg_supported(dev))
2105 return rte_flow_error_set(error, ENOTSUP,
2106 RTE_FLOW_ERROR_TYPE_ACTION, action,
2107 "extensive metadata register"
2108 " isn't supported");
2109 if (!(action->conf))
2110 return rte_flow_error_set(error, EINVAL,
2111 RTE_FLOW_ERROR_TYPE_ACTION, action,
2112 "configuration cannot be null");
2113 conf = (const struct rte_flow_action_set_tag *)action->conf;
2115 return rte_flow_error_set(error, EINVAL,
2116 RTE_FLOW_ERROR_TYPE_ACTION, action,
2117 "zero mask doesn't have any effect");
2118 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2121 if (!attr->transfer && attr->ingress &&
2122 (action_flags & terminal_action_flags))
2123 return rte_flow_error_set(error, EINVAL,
2124 RTE_FLOW_ERROR_TYPE_ACTION, action,
2125 "set_tag has no effect"
2126 " with terminal actions");
2131 * Validate count action.
2136 * Pointer to error structure.
2139 * 0 on success, a negative errno value otherwise and rte_errno is set.
2142 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2143 struct rte_flow_error *error)
2145 struct mlx5_priv *priv = dev->data->dev_private;
2147 if (!priv->config.devx)
2149 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2153 return rte_flow_error_set
2155 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2157 "count action not supported");
2161 * Validate the L2 encap action.
2163 * @param[in] action_flags
2164 * Holds the actions detected until now.
2166 * Pointer to the encap action.
2168 * Pointer to flow attributes
2170 * Pointer to error structure.
2173 * 0 on success, a negative errno value otherwise and rte_errno is set.
2176 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2177 const struct rte_flow_action *action,
2178 const struct rte_flow_attr *attr,
2179 struct rte_flow_error *error)
2181 if (!(action->conf))
2182 return rte_flow_error_set(error, EINVAL,
2183 RTE_FLOW_ERROR_TYPE_ACTION, action,
2184 "configuration cannot be null");
2185 if (action_flags & MLX5_FLOW_ACTION_DROP)
2186 return rte_flow_error_set(error, EINVAL,
2187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 "can't drop and encap in same flow");
2189 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2190 return rte_flow_error_set(error, EINVAL,
2191 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2192 "can only have a single encap or"
2193 " decap action in a flow");
2194 if (!attr->transfer && attr->ingress)
2195 return rte_flow_error_set(error, ENOTSUP,
2196 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2198 "encap action not supported for "
2204 * Validate the L2 decap action.
2206 * @param[in] action_flags
2207 * Holds the actions detected until now.
2209 * Pointer to flow attributes
2211 * Pointer to error structure.
2214 * 0 on success, a negative errno value otherwise and rte_errno is set.
2217 flow_dv_validate_action_l2_decap(uint64_t action_flags,
2218 const struct rte_flow_attr *attr,
2219 struct rte_flow_error *error)
2221 if (action_flags & MLX5_FLOW_ACTION_DROP)
2222 return rte_flow_error_set(error, EINVAL,
2223 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2224 "can't drop and decap in same flow");
2225 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2226 return rte_flow_error_set(error, EINVAL,
2227 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2228 "can only have a single encap or"
2229 " decap action in a flow");
2230 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2231 return rte_flow_error_set(error, EINVAL,
2232 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2233 "can't have decap action after"
2236 return rte_flow_error_set(error, ENOTSUP,
2237 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2239 "decap action not supported for "
2245 * Validate the raw encap action.
2247 * @param[in] action_flags
2248 * Holds the actions detected until now.
2250 * Pointer to the encap action.
2252 * Pointer to flow attributes
2254 * Pointer to error structure.
2257 * 0 on success, a negative errno value otherwise and rte_errno is set.
2260 flow_dv_validate_action_raw_encap(uint64_t action_flags,
2261 const struct rte_flow_action *action,
2262 const struct rte_flow_attr *attr,
2263 struct rte_flow_error *error)
2265 const struct rte_flow_action_raw_encap *raw_encap =
2266 (const struct rte_flow_action_raw_encap *)action->conf;
2267 if (!(action->conf))
2268 return rte_flow_error_set(error, EINVAL,
2269 RTE_FLOW_ERROR_TYPE_ACTION, action,
2270 "configuration cannot be null");
2271 if (action_flags & MLX5_FLOW_ACTION_DROP)
2272 return rte_flow_error_set(error, EINVAL,
2273 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2274 "can't drop and encap in same flow");
2275 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2276 return rte_flow_error_set(error, EINVAL,
2277 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2278 "can only have a single encap"
2279 " action in a flow");
2280 /* encap without preceding decap is not supported for ingress */
2281 if (!attr->transfer && attr->ingress &&
2282 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
2283 return rte_flow_error_set(error, ENOTSUP,
2284 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2286 "encap action not supported for "
2288 if (!raw_encap->size || !raw_encap->data)
2289 return rte_flow_error_set(error, EINVAL,
2290 RTE_FLOW_ERROR_TYPE_ACTION, action,
2291 "raw encap data cannot be empty");
2296 * Validate the raw decap action.
2298 * @param[in] action_flags
2299 * Holds the actions detected until now.
2301 * Pointer to the encap action.
2303 * Pointer to flow attributes
2305 * Pointer to error structure.
2308 * 0 on success, a negative errno value otherwise and rte_errno is set.
2311 flow_dv_validate_action_raw_decap(uint64_t action_flags,
2312 const struct rte_flow_action *action,
2313 const struct rte_flow_attr *attr,
2314 struct rte_flow_error *error)
2316 const struct rte_flow_action_raw_decap *decap = action->conf;
2318 if (action_flags & MLX5_FLOW_ACTION_DROP)
2319 return rte_flow_error_set(error, EINVAL,
2320 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2321 "can't drop and decap in same flow");
2322 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2323 return rte_flow_error_set(error, EINVAL,
2324 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2325 "can't have encap action before"
2327 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
2328 return rte_flow_error_set(error, EINVAL,
2329 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2330 "can only have a single decap"
2331 " action in a flow");
2332 /* decap action is valid on egress only if it is followed by encap */
2333 if (attr->egress && decap &&
2334 decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) {
2335 return rte_flow_error_set(error, ENOTSUP,
2336 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2337 NULL, "decap action not supported"
2339 } else if (decap && decap->size > MLX5_ENCAPSULATION_DECISION_SIZE &&
2340 (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)) {
2341 return rte_flow_error_set(error, EINVAL,
2342 RTE_FLOW_ERROR_TYPE_ACTION,
2344 "can't have decap action "
2345 "after modify action");
2351 * Find existing encap/decap resource or create and register a new one.
2353 * @param[in, out] dev
2354 * Pointer to rte_eth_dev structure.
2355 * @param[in, out] resource
2356 * Pointer to encap/decap resource.
2357 * @parm[in, out] dev_flow
2358 * Pointer to the dev_flow.
2360 * pointer to error structure.
2363 * 0 on success otherwise -errno and errno is set.
2366 flow_dv_encap_decap_resource_register
2367 (struct rte_eth_dev *dev,
2368 struct mlx5_flow_dv_encap_decap_resource *resource,
2369 struct mlx5_flow *dev_flow,
2370 struct rte_flow_error *error)
2372 struct mlx5_priv *priv = dev->data->dev_private;
2373 struct mlx5_ibv_shared *sh = priv->sh;
2374 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2375 struct mlx5dv_dr_domain *domain;
2377 resource->flags = dev_flow->group ? 0 : 1;
2378 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2379 domain = sh->fdb_domain;
2380 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2381 domain = sh->rx_domain;
2383 domain = sh->tx_domain;
2384 /* Lookup a matching resource from cache. */
2385 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2386 if (resource->reformat_type == cache_resource->reformat_type &&
2387 resource->ft_type == cache_resource->ft_type &&
2388 resource->flags == cache_resource->flags &&
2389 resource->size == cache_resource->size &&
2390 !memcmp((const void *)resource->buf,
2391 (const void *)cache_resource->buf,
2393 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2394 (void *)cache_resource,
2395 rte_atomic32_read(&cache_resource->refcnt));
2396 rte_atomic32_inc(&cache_resource->refcnt);
2397 dev_flow->dv.encap_decap = cache_resource;
2401 /* Register new encap/decap resource. */
2402 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2403 if (!cache_resource)
2404 return rte_flow_error_set(error, ENOMEM,
2405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2406 "cannot allocate resource memory");
2407 *cache_resource = *resource;
2408 cache_resource->verbs_action =
2409 mlx5_glue->dv_create_flow_action_packet_reformat
2410 (sh->ctx, cache_resource->reformat_type,
2411 cache_resource->ft_type, domain, cache_resource->flags,
2412 cache_resource->size,
2413 (cache_resource->size ? cache_resource->buf : NULL));
2414 if (!cache_resource->verbs_action) {
2415 rte_free(cache_resource);
2416 return rte_flow_error_set(error, ENOMEM,
2417 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2418 NULL, "cannot create action");
2420 rte_atomic32_init(&cache_resource->refcnt);
2421 rte_atomic32_inc(&cache_resource->refcnt);
2422 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2423 dev_flow->dv.encap_decap = cache_resource;
2424 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2425 (void *)cache_resource,
2426 rte_atomic32_read(&cache_resource->refcnt));
2431 * Find existing table jump resource or create and register a new one.
2433 * @param[in, out] dev
2434 * Pointer to rte_eth_dev structure.
2435 * @param[in, out] tbl
2436 * Pointer to flow table resource.
2437 * @parm[in, out] dev_flow
2438 * Pointer to the dev_flow.
2440 * pointer to error structure.
2443 * 0 on success otherwise -errno and errno is set.
2446 flow_dv_jump_tbl_resource_register
2447 (struct rte_eth_dev *dev __rte_unused,
2448 struct mlx5_flow_tbl_resource *tbl,
2449 struct mlx5_flow *dev_flow,
2450 struct rte_flow_error *error)
2452 struct mlx5_flow_tbl_data_entry *tbl_data =
2453 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2457 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2459 tbl_data->jump.action =
2460 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2462 if (!tbl_data->jump.action)
2463 return rte_flow_error_set(error, ENOMEM,
2464 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2465 NULL, "cannot create jump action");
2466 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2467 (void *)&tbl_data->jump, cnt);
2469 assert(tbl_data->jump.action);
2470 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2471 (void *)&tbl_data->jump, cnt);
2473 rte_atomic32_inc(&tbl_data->jump.refcnt);
2474 dev_flow->dv.jump = &tbl_data->jump;
2479 * Find existing table port ID resource or create and register a new one.
2481 * @param[in, out] dev
2482 * Pointer to rte_eth_dev structure.
2483 * @param[in, out] resource
2484 * Pointer to port ID action resource.
2485 * @parm[in, out] dev_flow
2486 * Pointer to the dev_flow.
2488 * pointer to error structure.
2491 * 0 on success otherwise -errno and errno is set.
2494 flow_dv_port_id_action_resource_register
2495 (struct rte_eth_dev *dev,
2496 struct mlx5_flow_dv_port_id_action_resource *resource,
2497 struct mlx5_flow *dev_flow,
2498 struct rte_flow_error *error)
2500 struct mlx5_priv *priv = dev->data->dev_private;
2501 struct mlx5_ibv_shared *sh = priv->sh;
2502 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2504 /* Lookup a matching resource from cache. */
2505 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2506 if (resource->port_id == cache_resource->port_id) {
2507 DRV_LOG(DEBUG, "port id action resource resource %p: "
2509 (void *)cache_resource,
2510 rte_atomic32_read(&cache_resource->refcnt));
2511 rte_atomic32_inc(&cache_resource->refcnt);
2512 dev_flow->dv.port_id_action = cache_resource;
2516 /* Register new port id action resource. */
2517 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2518 if (!cache_resource)
2519 return rte_flow_error_set(error, ENOMEM,
2520 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2521 "cannot allocate resource memory");
2522 *cache_resource = *resource;
2524 * Depending on rdma_core version the glue routine calls
2525 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2526 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2528 cache_resource->action =
2529 mlx5_glue->dr_create_flow_action_dest_port
2530 (priv->sh->fdb_domain, resource->port_id);
2531 if (!cache_resource->action) {
2532 rte_free(cache_resource);
2533 return rte_flow_error_set(error, ENOMEM,
2534 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2535 NULL, "cannot create action");
2537 rte_atomic32_init(&cache_resource->refcnt);
2538 rte_atomic32_inc(&cache_resource->refcnt);
2539 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2540 dev_flow->dv.port_id_action = cache_resource;
2541 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2542 (void *)cache_resource,
2543 rte_atomic32_read(&cache_resource->refcnt));
2548 * Find existing push vlan resource or create and register a new one.
2550 * @param [in, out] dev
2551 * Pointer to rte_eth_dev structure.
2552 * @param[in, out] resource
2553 * Pointer to port ID action resource.
2554 * @parm[in, out] dev_flow
2555 * Pointer to the dev_flow.
2557 * pointer to error structure.
2560 * 0 on success otherwise -errno and errno is set.
2563 flow_dv_push_vlan_action_resource_register
2564 (struct rte_eth_dev *dev,
2565 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2566 struct mlx5_flow *dev_flow,
2567 struct rte_flow_error *error)
2569 struct mlx5_priv *priv = dev->data->dev_private;
2570 struct mlx5_ibv_shared *sh = priv->sh;
2571 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2572 struct mlx5dv_dr_domain *domain;
2574 /* Lookup a matching resource from cache. */
2575 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2576 if (resource->vlan_tag == cache_resource->vlan_tag &&
2577 resource->ft_type == cache_resource->ft_type) {
2578 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2580 (void *)cache_resource,
2581 rte_atomic32_read(&cache_resource->refcnt));
2582 rte_atomic32_inc(&cache_resource->refcnt);
2583 dev_flow->dv.push_vlan_res = cache_resource;
2587 /* Register new push_vlan action resource. */
2588 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2589 if (!cache_resource)
2590 return rte_flow_error_set(error, ENOMEM,
2591 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2592 "cannot allocate resource memory");
2593 *cache_resource = *resource;
2594 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2595 domain = sh->fdb_domain;
2596 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2597 domain = sh->rx_domain;
2599 domain = sh->tx_domain;
2600 cache_resource->action =
2601 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2602 resource->vlan_tag);
2603 if (!cache_resource->action) {
2604 rte_free(cache_resource);
2605 return rte_flow_error_set(error, ENOMEM,
2606 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2607 NULL, "cannot create action");
2609 rte_atomic32_init(&cache_resource->refcnt);
2610 rte_atomic32_inc(&cache_resource->refcnt);
2611 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2612 dev_flow->dv.push_vlan_res = cache_resource;
2613 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2614 (void *)cache_resource,
2615 rte_atomic32_read(&cache_resource->refcnt));
2619 * Get the size of specific rte_flow_item_type
2621 * @param[in] item_type
2622 * Tested rte_flow_item_type.
2625 * sizeof struct item_type, 0 if void or irrelevant.
2628 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2632 switch (item_type) {
2633 case RTE_FLOW_ITEM_TYPE_ETH:
2634 retval = sizeof(struct rte_flow_item_eth);
2636 case RTE_FLOW_ITEM_TYPE_VLAN:
2637 retval = sizeof(struct rte_flow_item_vlan);
2639 case RTE_FLOW_ITEM_TYPE_IPV4:
2640 retval = sizeof(struct rte_flow_item_ipv4);
2642 case RTE_FLOW_ITEM_TYPE_IPV6:
2643 retval = sizeof(struct rte_flow_item_ipv6);
2645 case RTE_FLOW_ITEM_TYPE_UDP:
2646 retval = sizeof(struct rte_flow_item_udp);
2648 case RTE_FLOW_ITEM_TYPE_TCP:
2649 retval = sizeof(struct rte_flow_item_tcp);
2651 case RTE_FLOW_ITEM_TYPE_VXLAN:
2652 retval = sizeof(struct rte_flow_item_vxlan);
2654 case RTE_FLOW_ITEM_TYPE_GRE:
2655 retval = sizeof(struct rte_flow_item_gre);
2657 case RTE_FLOW_ITEM_TYPE_NVGRE:
2658 retval = sizeof(struct rte_flow_item_nvgre);
2660 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2661 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2663 case RTE_FLOW_ITEM_TYPE_MPLS:
2664 retval = sizeof(struct rte_flow_item_mpls);
2666 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2674 #define MLX5_ENCAP_IPV4_VERSION 0x40
2675 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2676 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2677 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2678 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2679 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2680 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2683 * Convert the encap action data from list of rte_flow_item to raw buffer
2686 * Pointer to rte_flow_item objects list.
2688 * Pointer to the output buffer.
2690 * Pointer to the output buffer size.
2692 * Pointer to the error structure.
2695 * 0 on success, a negative errno value otherwise and rte_errno is set.
2698 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2699 size_t *size, struct rte_flow_error *error)
2701 struct rte_ether_hdr *eth = NULL;
2702 struct rte_vlan_hdr *vlan = NULL;
2703 struct rte_ipv4_hdr *ipv4 = NULL;
2704 struct rte_ipv6_hdr *ipv6 = NULL;
2705 struct rte_udp_hdr *udp = NULL;
2706 struct rte_vxlan_hdr *vxlan = NULL;
2707 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2708 struct rte_gre_hdr *gre = NULL;
2710 size_t temp_size = 0;
2713 return rte_flow_error_set(error, EINVAL,
2714 RTE_FLOW_ERROR_TYPE_ACTION,
2715 NULL, "invalid empty data");
2716 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2717 len = flow_dv_get_item_len(items->type);
2718 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2719 return rte_flow_error_set(error, EINVAL,
2720 RTE_FLOW_ERROR_TYPE_ACTION,
2721 (void *)items->type,
2722 "items total size is too big"
2723 " for encap action");
2724 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2725 switch (items->type) {
2726 case RTE_FLOW_ITEM_TYPE_ETH:
2727 eth = (struct rte_ether_hdr *)&buf[temp_size];
2729 case RTE_FLOW_ITEM_TYPE_VLAN:
2730 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2732 return rte_flow_error_set(error, EINVAL,
2733 RTE_FLOW_ERROR_TYPE_ACTION,
2734 (void *)items->type,
2735 "eth header not found");
2736 if (!eth->ether_type)
2737 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2739 case RTE_FLOW_ITEM_TYPE_IPV4:
2740 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2742 return rte_flow_error_set(error, EINVAL,
2743 RTE_FLOW_ERROR_TYPE_ACTION,
2744 (void *)items->type,
2745 "neither eth nor vlan"
2747 if (vlan && !vlan->eth_proto)
2748 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2749 else if (eth && !eth->ether_type)
2750 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2751 if (!ipv4->version_ihl)
2752 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2753 MLX5_ENCAP_IPV4_IHL_MIN;
2754 if (!ipv4->time_to_live)
2755 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2757 case RTE_FLOW_ITEM_TYPE_IPV6:
2758 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2760 return rte_flow_error_set(error, EINVAL,
2761 RTE_FLOW_ERROR_TYPE_ACTION,
2762 (void *)items->type,
2763 "neither eth nor vlan"
2765 if (vlan && !vlan->eth_proto)
2766 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2767 else if (eth && !eth->ether_type)
2768 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2769 if (!ipv6->vtc_flow)
2771 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2772 if (!ipv6->hop_limits)
2773 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2775 case RTE_FLOW_ITEM_TYPE_UDP:
2776 udp = (struct rte_udp_hdr *)&buf[temp_size];
2778 return rte_flow_error_set(error, EINVAL,
2779 RTE_FLOW_ERROR_TYPE_ACTION,
2780 (void *)items->type,
2781 "ip header not found");
2782 if (ipv4 && !ipv4->next_proto_id)
2783 ipv4->next_proto_id = IPPROTO_UDP;
2784 else if (ipv6 && !ipv6->proto)
2785 ipv6->proto = IPPROTO_UDP;
2787 case RTE_FLOW_ITEM_TYPE_VXLAN:
2788 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2790 return rte_flow_error_set(error, EINVAL,
2791 RTE_FLOW_ERROR_TYPE_ACTION,
2792 (void *)items->type,
2793 "udp header not found");
2795 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2796 if (!vxlan->vx_flags)
2798 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2800 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2801 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2803 return rte_flow_error_set(error, EINVAL,
2804 RTE_FLOW_ERROR_TYPE_ACTION,
2805 (void *)items->type,
2806 "udp header not found");
2807 if (!vxlan_gpe->proto)
2808 return rte_flow_error_set(error, EINVAL,
2809 RTE_FLOW_ERROR_TYPE_ACTION,
2810 (void *)items->type,
2811 "next protocol not found");
2814 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2815 if (!vxlan_gpe->vx_flags)
2816 vxlan_gpe->vx_flags =
2817 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2819 case RTE_FLOW_ITEM_TYPE_GRE:
2820 case RTE_FLOW_ITEM_TYPE_NVGRE:
2821 gre = (struct rte_gre_hdr *)&buf[temp_size];
2823 return rte_flow_error_set(error, EINVAL,
2824 RTE_FLOW_ERROR_TYPE_ACTION,
2825 (void *)items->type,
2826 "next protocol not found");
2828 return rte_flow_error_set(error, EINVAL,
2829 RTE_FLOW_ERROR_TYPE_ACTION,
2830 (void *)items->type,
2831 "ip header not found");
2832 if (ipv4 && !ipv4->next_proto_id)
2833 ipv4->next_proto_id = IPPROTO_GRE;
2834 else if (ipv6 && !ipv6->proto)
2835 ipv6->proto = IPPROTO_GRE;
2837 case RTE_FLOW_ITEM_TYPE_VOID:
2840 return rte_flow_error_set(error, EINVAL,
2841 RTE_FLOW_ERROR_TYPE_ACTION,
2842 (void *)items->type,
2843 "unsupported item type");
2853 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2855 struct rte_ether_hdr *eth = NULL;
2856 struct rte_vlan_hdr *vlan = NULL;
2857 struct rte_ipv6_hdr *ipv6 = NULL;
2858 struct rte_udp_hdr *udp = NULL;
2862 eth = (struct rte_ether_hdr *)data;
2863 next_hdr = (char *)(eth + 1);
2864 proto = RTE_BE16(eth->ether_type);
2867 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2868 vlan = (struct rte_vlan_hdr *)next_hdr;
2869 proto = RTE_BE16(vlan->eth_proto);
2870 next_hdr += sizeof(struct rte_vlan_hdr);
2873 /* HW calculates IPv4 csum. no need to proceed */
2874 if (proto == RTE_ETHER_TYPE_IPV4)
2877 /* non IPv4/IPv6 header. not supported */
2878 if (proto != RTE_ETHER_TYPE_IPV6) {
2879 return rte_flow_error_set(error, ENOTSUP,
2880 RTE_FLOW_ERROR_TYPE_ACTION,
2881 NULL, "Cannot offload non IPv4/IPv6");
2884 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2886 /* ignore non UDP */
2887 if (ipv6->proto != IPPROTO_UDP)
2890 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2891 udp->dgram_cksum = 0;
2897 * Convert L2 encap action to DV specification.
2900 * Pointer to rte_eth_dev structure.
2902 * Pointer to action structure.
2903 * @param[in, out] dev_flow
2904 * Pointer to the mlx5_flow.
2905 * @param[in] transfer
2906 * Mark if the flow is E-Switch flow.
2908 * Pointer to the error structure.
2911 * 0 on success, a negative errno value otherwise and rte_errno is set.
2914 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2915 const struct rte_flow_action *action,
2916 struct mlx5_flow *dev_flow,
2918 struct rte_flow_error *error)
2920 const struct rte_flow_item *encap_data;
2921 const struct rte_flow_action_raw_encap *raw_encap_data;
2922 struct mlx5_flow_dv_encap_decap_resource res = {
2924 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2925 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2926 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2929 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2931 (const struct rte_flow_action_raw_encap *)action->conf;
2932 res.size = raw_encap_data->size;
2933 memcpy(res.buf, raw_encap_data->data, res.size);
2934 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2937 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2939 ((const struct rte_flow_action_vxlan_encap *)
2940 action->conf)->definition;
2943 ((const struct rte_flow_action_nvgre_encap *)
2944 action->conf)->definition;
2945 if (flow_dv_convert_encap_data(encap_data, res.buf,
2949 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2950 return rte_flow_error_set(error, EINVAL,
2951 RTE_FLOW_ERROR_TYPE_ACTION,
2952 NULL, "can't create L2 encap action");
2957 * Convert L2 decap action to DV specification.
2960 * Pointer to rte_eth_dev structure.
2961 * @param[in, out] dev_flow
2962 * Pointer to the mlx5_flow.
2963 * @param[in] transfer
2964 * Mark if the flow is E-Switch flow.
2966 * Pointer to the error structure.
2969 * 0 on success, a negative errno value otherwise and rte_errno is set.
2972 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2973 struct mlx5_flow *dev_flow,
2975 struct rte_flow_error *error)
2977 struct mlx5_flow_dv_encap_decap_resource res = {
2980 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2981 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2982 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2985 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2986 return rte_flow_error_set(error, EINVAL,
2987 RTE_FLOW_ERROR_TYPE_ACTION,
2988 NULL, "can't create L2 decap action");
2993 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2996 * Pointer to rte_eth_dev structure.
2998 * Pointer to action structure.
2999 * @param[in, out] dev_flow
3000 * Pointer to the mlx5_flow.
3002 * Pointer to the flow attributes.
3004 * Pointer to the error structure.
3007 * 0 on success, a negative errno value otherwise and rte_errno is set.
3010 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3011 const struct rte_flow_action *action,
3012 struct mlx5_flow *dev_flow,
3013 const struct rte_flow_attr *attr,
3014 struct rte_flow_error *error)
3016 const struct rte_flow_action_raw_encap *encap_data;
3017 struct mlx5_flow_dv_encap_decap_resource res;
3019 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3020 res.size = encap_data->size;
3021 memcpy(res.buf, encap_data->data, res.size);
3022 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3023 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3024 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3026 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3028 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3029 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3030 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3031 return rte_flow_error_set(error, EINVAL,
3032 RTE_FLOW_ERROR_TYPE_ACTION,
3033 NULL, "can't create encap action");
3038 * Create action push VLAN.
3041 * Pointer to rte_eth_dev structure.
3042 * @param[in] vlan_tag
3043 * the vlan tag to push to the Ethernet header.
3044 * @param[in, out] dev_flow
3045 * Pointer to the mlx5_flow.
3047 * Pointer to the flow attributes.
3049 * Pointer to the error structure.
3052 * 0 on success, a negative errno value otherwise and rte_errno is set.
3055 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3056 const struct rte_flow_attr *attr,
3057 const struct rte_vlan_hdr *vlan,
3058 struct mlx5_flow *dev_flow,
3059 struct rte_flow_error *error)
3061 struct mlx5_flow_dv_push_vlan_action_resource res;
3064 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3067 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3069 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3070 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3071 return flow_dv_push_vlan_action_resource_register
3072 (dev, &res, dev_flow, error);
3076 * Validate the modify-header actions.
3078 * @param[in] action_flags
3079 * Holds the actions detected until now.
3081 * Pointer to the modify action.
3083 * Pointer to error structure.
3086 * 0 on success, a negative errno value otherwise and rte_errno is set.
3089 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3090 const struct rte_flow_action *action,
3091 struct rte_flow_error *error)
3093 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3094 return rte_flow_error_set(error, EINVAL,
3095 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3096 NULL, "action configuration not set");
3097 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
3098 return rte_flow_error_set(error, EINVAL,
3099 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3100 "can't have encap action before"
3106 * Validate the modify-header MAC address actions.
3108 * @param[in] action_flags
3109 * Holds the actions detected until now.
3111 * Pointer to the modify action.
3112 * @param[in] item_flags
3113 * Holds the items detected.
3115 * Pointer to error structure.
3118 * 0 on success, a negative errno value otherwise and rte_errno is set.
3121 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3122 const struct rte_flow_action *action,
3123 const uint64_t item_flags,
3124 struct rte_flow_error *error)
3128 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3130 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3131 return rte_flow_error_set(error, EINVAL,
3132 RTE_FLOW_ERROR_TYPE_ACTION,
3134 "no L2 item in pattern");
3140 * Validate the modify-header IPv4 address actions.
3142 * @param[in] action_flags
3143 * Holds the actions detected until now.
3145 * Pointer to the modify action.
3146 * @param[in] item_flags
3147 * Holds the items detected.
3149 * Pointer to error structure.
3152 * 0 on success, a negative errno value otherwise and rte_errno is set.
3155 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3156 const struct rte_flow_action *action,
3157 const uint64_t item_flags,
3158 struct rte_flow_error *error)
3162 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3164 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3165 return rte_flow_error_set(error, EINVAL,
3166 RTE_FLOW_ERROR_TYPE_ACTION,
3168 "no ipv4 item in pattern");
3174 * Validate the modify-header IPv6 address actions.
3176 * @param[in] action_flags
3177 * Holds the actions detected until now.
3179 * Pointer to the modify action.
3180 * @param[in] item_flags
3181 * Holds the items detected.
3183 * Pointer to error structure.
3186 * 0 on success, a negative errno value otherwise and rte_errno is set.
3189 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3190 const struct rte_flow_action *action,
3191 const uint64_t item_flags,
3192 struct rte_flow_error *error)
3196 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3198 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3199 return rte_flow_error_set(error, EINVAL,
3200 RTE_FLOW_ERROR_TYPE_ACTION,
3202 "no ipv6 item in pattern");
3208 * Validate the modify-header TP actions.
3210 * @param[in] action_flags
3211 * Holds the actions detected until now.
3213 * Pointer to the modify action.
3214 * @param[in] item_flags
3215 * Holds the items detected.
3217 * Pointer to error structure.
3220 * 0 on success, a negative errno value otherwise and rte_errno is set.
3223 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3224 const struct rte_flow_action *action,
3225 const uint64_t item_flags,
3226 struct rte_flow_error *error)
3230 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3232 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3233 return rte_flow_error_set(error, EINVAL,
3234 RTE_FLOW_ERROR_TYPE_ACTION,
3235 NULL, "no transport layer "
3242 * Validate the modify-header actions of increment/decrement
3243 * TCP Sequence-number.
3245 * @param[in] action_flags
3246 * Holds the actions detected until now.
3248 * Pointer to the modify action.
3249 * @param[in] item_flags
3250 * Holds the items detected.
3252 * Pointer to error structure.
3255 * 0 on success, a negative errno value otherwise and rte_errno is set.
3258 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3259 const struct rte_flow_action *action,
3260 const uint64_t item_flags,
3261 struct rte_flow_error *error)
3265 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3267 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3268 return rte_flow_error_set(error, EINVAL,
3269 RTE_FLOW_ERROR_TYPE_ACTION,
3270 NULL, "no TCP item in"
3272 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3273 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3274 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3275 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3276 return rte_flow_error_set(error, EINVAL,
3277 RTE_FLOW_ERROR_TYPE_ACTION,
3279 "cannot decrease and increase"
3280 " TCP sequence number"
3281 " at the same time");
3287 * Validate the modify-header actions of increment/decrement
3288 * TCP Acknowledgment number.
3290 * @param[in] action_flags
3291 * Holds the actions detected until now.
3293 * Pointer to the modify action.
3294 * @param[in] item_flags
3295 * Holds the items detected.
3297 * Pointer to error structure.
3300 * 0 on success, a negative errno value otherwise and rte_errno is set.
3303 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3304 const struct rte_flow_action *action,
3305 const uint64_t item_flags,
3306 struct rte_flow_error *error)
3310 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3312 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3313 return rte_flow_error_set(error, EINVAL,
3314 RTE_FLOW_ERROR_TYPE_ACTION,
3315 NULL, "no TCP item in"
3317 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3318 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3319 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3320 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3321 return rte_flow_error_set(error, EINVAL,
3322 RTE_FLOW_ERROR_TYPE_ACTION,
3324 "cannot decrease and increase"
3325 " TCP acknowledgment number"
3326 " at the same time");
3332 * Validate the modify-header TTL actions.
3334 * @param[in] action_flags
3335 * Holds the actions detected until now.
3337 * Pointer to the modify action.
3338 * @param[in] item_flags
3339 * Holds the items detected.
3341 * Pointer to error structure.
3344 * 0 on success, a negative errno value otherwise and rte_errno is set.
3347 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3348 const struct rte_flow_action *action,
3349 const uint64_t item_flags,
3350 struct rte_flow_error *error)
3354 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3356 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3357 return rte_flow_error_set(error, EINVAL,
3358 RTE_FLOW_ERROR_TYPE_ACTION,
3360 "no IP protocol in pattern");
3366 * Validate jump action.
3369 * Pointer to the jump action.
3370 * @param[in] action_flags
3371 * Holds the actions detected until now.
3372 * @param[in] attributes
3373 * Pointer to flow attributes
3374 * @param[in] external
3375 * Action belongs to flow rule created by request external to PMD.
3377 * Pointer to error structure.
3380 * 0 on success, a negative errno value otherwise and rte_errno is set.
3383 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3384 uint64_t action_flags,
3385 const struct rte_flow_attr *attributes,
3386 bool external, struct rte_flow_error *error)
3388 uint32_t target_group, table;
3391 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3392 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3393 return rte_flow_error_set(error, EINVAL,
3394 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3395 "can't have 2 fate actions in"
3397 if (action_flags & MLX5_FLOW_ACTION_METER)
3398 return rte_flow_error_set(error, ENOTSUP,
3399 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3400 "jump with meter not support");
3402 return rte_flow_error_set(error, EINVAL,
3403 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3404 NULL, "action configuration not set");
3406 ((const struct rte_flow_action_jump *)action->conf)->group;
3407 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3411 if (attributes->group == target_group)
3412 return rte_flow_error_set(error, EINVAL,
3413 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3414 "target group must be other than"
3415 " the current flow group");
3420 * Validate the port_id action.
3423 * Pointer to rte_eth_dev structure.
3424 * @param[in] action_flags
3425 * Bit-fields that holds the actions detected until now.
3427 * Port_id RTE action structure.
3429 * Attributes of flow that includes this action.
3431 * Pointer to error structure.
3434 * 0 on success, a negative errno value otherwise and rte_errno is set.
3437 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3438 uint64_t action_flags,
3439 const struct rte_flow_action *action,
3440 const struct rte_flow_attr *attr,
3441 struct rte_flow_error *error)
3443 const struct rte_flow_action_port_id *port_id;
3444 struct mlx5_priv *act_priv;
3445 struct mlx5_priv *dev_priv;
3448 if (!attr->transfer)
3449 return rte_flow_error_set(error, ENOTSUP,
3450 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3452 "port id action is valid in transfer"
3454 if (!action || !action->conf)
3455 return rte_flow_error_set(error, ENOTSUP,
3456 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3458 "port id action parameters must be"
3460 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3461 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3462 return rte_flow_error_set(error, EINVAL,
3463 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3464 "can have only one fate actions in"
3466 dev_priv = mlx5_dev_to_eswitch_info(dev);
3468 return rte_flow_error_set(error, rte_errno,
3469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3471 "failed to obtain E-Switch info");
3472 port_id = action->conf;
3473 port = port_id->original ? dev->data->port_id : port_id->id;
3474 act_priv = mlx5_port_to_eswitch_info(port, false);
3476 return rte_flow_error_set
3478 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3479 "failed to obtain E-Switch port id for port");
3480 if (act_priv->domain_id != dev_priv->domain_id)
3481 return rte_flow_error_set
3483 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3484 "port does not belong to"
3485 " E-Switch being configured");
3490 * Get the maximum number of modify header actions.
3493 * Pointer to rte_eth_dev structure.
3495 * Flags bits to check if root level.
3498 * Max number of modify header actions device can support.
3501 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3504 * There's no way to directly query the max cap. Although it has to be
3505 * acquried by iterative trial, it is a safe assumption that more
3506 * actions are supported by FW if extensive metadata register is
3507 * supported. (Only in the root table)
3509 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3510 return MLX5_MAX_MODIFY_NUM;
3512 return mlx5_flow_ext_mreg_supported(dev) ?
3513 MLX5_ROOT_TBL_MODIFY_NUM :
3514 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3518 * Validate the meter action.
3521 * Pointer to rte_eth_dev structure.
3522 * @param[in] action_flags
3523 * Bit-fields that holds the actions detected until now.
3525 * Pointer to the meter action.
3527 * Attributes of flow that includes this action.
3529 * Pointer to error structure.
3532 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3535 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3536 uint64_t action_flags,
3537 const struct rte_flow_action *action,
3538 const struct rte_flow_attr *attr,
3539 struct rte_flow_error *error)
3541 struct mlx5_priv *priv = dev->data->dev_private;
3542 const struct rte_flow_action_meter *am = action->conf;
3543 struct mlx5_flow_meter *fm;
3546 return rte_flow_error_set(error, EINVAL,
3547 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3548 "meter action conf is NULL");
3550 if (action_flags & MLX5_FLOW_ACTION_METER)
3551 return rte_flow_error_set(error, ENOTSUP,
3552 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3553 "meter chaining not support");
3554 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3555 return rte_flow_error_set(error, ENOTSUP,
3556 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557 "meter with jump not support");
3559 return rte_flow_error_set(error, ENOTSUP,
3560 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3562 "meter action not supported");
3563 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3565 return rte_flow_error_set(error, EINVAL,
3566 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3568 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3569 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3570 (!fm->attr.egress && !attr->egress && attr->ingress))))
3571 return rte_flow_error_set(error, EINVAL,
3572 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3573 "Flow attributes are either invalid "
3574 "or have a conflict with current "
3575 "meter attributes");
3580 * Validate the modify-header IPv4 DSCP actions.
3582 * @param[in] action_flags
3583 * Holds the actions detected until now.
3585 * Pointer to the modify action.
3586 * @param[in] item_flags
3587 * Holds the items detected.
3589 * Pointer to error structure.
3592 * 0 on success, a negative errno value otherwise and rte_errno is set.
3595 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3596 const struct rte_flow_action *action,
3597 const uint64_t item_flags,
3598 struct rte_flow_error *error)
3602 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3604 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3605 return rte_flow_error_set(error, EINVAL,
3606 RTE_FLOW_ERROR_TYPE_ACTION,
3608 "no ipv4 item in pattern");
3614 * Validate the modify-header IPv6 DSCP actions.
3616 * @param[in] action_flags
3617 * Holds the actions detected until now.
3619 * Pointer to the modify action.
3620 * @param[in] item_flags
3621 * Holds the items detected.
3623 * Pointer to error structure.
3626 * 0 on success, a negative errno value otherwise and rte_errno is set.
3629 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3630 const struct rte_flow_action *action,
3631 const uint64_t item_flags,
3632 struct rte_flow_error *error)
3636 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3638 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3639 return rte_flow_error_set(error, EINVAL,
3640 RTE_FLOW_ERROR_TYPE_ACTION,
3642 "no ipv6 item in pattern");
3648 * Find existing modify-header resource or create and register a new one.
3650 * @param dev[in, out]
3651 * Pointer to rte_eth_dev structure.
3652 * @param[in, out] resource
3653 * Pointer to modify-header resource.
3654 * @parm[in, out] dev_flow
3655 * Pointer to the dev_flow.
3657 * pointer to error structure.
3660 * 0 on success otherwise -errno and errno is set.
3663 flow_dv_modify_hdr_resource_register
3664 (struct rte_eth_dev *dev,
3665 struct mlx5_flow_dv_modify_hdr_resource *resource,
3666 struct mlx5_flow *dev_flow,
3667 struct rte_flow_error *error)
3669 struct mlx5_priv *priv = dev->data->dev_private;
3670 struct mlx5_ibv_shared *sh = priv->sh;
3671 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3672 struct mlx5dv_dr_domain *ns;
3673 uint32_t actions_len;
3676 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3677 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3679 return rte_flow_error_set(error, EOVERFLOW,
3680 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3681 "too many modify header items");
3682 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3683 ns = sh->fdb_domain;
3684 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3688 /* Lookup a matching resource from cache. */
3689 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3690 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3691 if (resource->ft_type == cache_resource->ft_type &&
3692 resource->actions_num == cache_resource->actions_num &&
3693 resource->flags == cache_resource->flags &&
3694 !memcmp((const void *)resource->actions,
3695 (const void *)cache_resource->actions,
3697 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3698 (void *)cache_resource,
3699 rte_atomic32_read(&cache_resource->refcnt));
3700 rte_atomic32_inc(&cache_resource->refcnt);
3701 dev_flow->dv.modify_hdr = cache_resource;
3705 /* Register new modify-header resource. */
3706 cache_resource = rte_calloc(__func__, 1,
3707 sizeof(*cache_resource) + actions_len, 0);
3708 if (!cache_resource)
3709 return rte_flow_error_set(error, ENOMEM,
3710 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3711 "cannot allocate resource memory");
3712 *cache_resource = *resource;
3713 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3714 cache_resource->verbs_action =
3715 mlx5_glue->dv_create_flow_action_modify_header
3716 (sh->ctx, cache_resource->ft_type, ns,
3717 cache_resource->flags, actions_len,
3718 (uint64_t *)cache_resource->actions);
3719 if (!cache_resource->verbs_action) {
3720 rte_free(cache_resource);
3721 return rte_flow_error_set(error, ENOMEM,
3722 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3723 NULL, "cannot create action");
3725 rte_atomic32_init(&cache_resource->refcnt);
3726 rte_atomic32_inc(&cache_resource->refcnt);
3727 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3728 dev_flow->dv.modify_hdr = cache_resource;
3729 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3730 (void *)cache_resource,
3731 rte_atomic32_read(&cache_resource->refcnt));
3735 #define MLX5_CNT_CONTAINER_RESIZE 64
3738 * Get or create a flow counter.
3741 * Pointer to the Ethernet device structure.
3743 * Indicate if this counter is shared with other flows.
3745 * Counter identifier.
3748 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3750 static struct mlx5_flow_counter *
3751 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3754 struct mlx5_priv *priv = dev->data->dev_private;
3755 struct mlx5_flow_counter *cnt = NULL;
3756 struct mlx5_devx_obj *dcs = NULL;
3758 if (!priv->config.devx) {
3759 rte_errno = ENOTSUP;
3763 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3764 if (cnt->shared && cnt->id == id) {
3770 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3773 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3775 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3779 struct mlx5_flow_counter tmpl = {
3785 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3787 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3793 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3798 * Release a flow counter.
3801 * Pointer to the Ethernet device structure.
3802 * @param[in] counter
3803 * Pointer to the counter handler.
3806 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3807 struct mlx5_flow_counter *counter)
3809 struct mlx5_priv *priv = dev->data->dev_private;
3813 if (--counter->ref_cnt == 0) {
3814 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3815 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3821 * Query a devx flow counter.
3824 * Pointer to the Ethernet device structure.
3826 * Pointer to the flow counter.
3828 * The statistics value of packets.
3830 * The statistics value of bytes.
3833 * 0 on success, otherwise a negative errno value and rte_errno is set.
3836 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3837 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3840 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3845 * Get a pool by a counter.
3848 * Pointer to the counter.
3853 static struct mlx5_flow_counter_pool *
3854 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3857 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3858 return (struct mlx5_flow_counter_pool *)cnt - 1;
3864 * Get a pool by devx counter ID.
3867 * Pointer to the counter container.
3869 * The counter devx ID.
3872 * The counter pool pointer if exists, NULL otherwise,
3874 static struct mlx5_flow_counter_pool *
3875 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3877 struct mlx5_flow_counter_pool *pool;
3879 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3880 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3881 MLX5_COUNTERS_PER_POOL;
3883 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3890 * Allocate a new memory for the counter values wrapped by all the needed
3894 * Pointer to the Ethernet device structure.
3896 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3899 * The new memory management pointer on success, otherwise NULL and rte_errno
3902 static struct mlx5_counter_stats_mem_mng *
3903 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3905 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3906 (dev->data->dev_private))->sh;
3907 struct mlx5_devx_mkey_attr mkey_attr;
3908 struct mlx5_counter_stats_mem_mng *mem_mng;
3909 volatile struct flow_counter_stats *raw_data;
3910 int size = (sizeof(struct flow_counter_stats) *
3911 MLX5_COUNTERS_PER_POOL +
3912 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3913 sizeof(struct mlx5_counter_stats_mem_mng);
3914 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3921 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3922 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3923 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3924 IBV_ACCESS_LOCAL_WRITE);
3925 if (!mem_mng->umem) {
3930 mkey_attr.addr = (uintptr_t)mem;
3931 mkey_attr.size = size;
3932 mkey_attr.umem_id = mem_mng->umem->umem_id;
3933 mkey_attr.pd = sh->pdn;
3934 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3936 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3941 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3942 raw_data = (volatile struct flow_counter_stats *)mem;
3943 for (i = 0; i < raws_n; ++i) {
3944 mem_mng->raws[i].mem_mng = mem_mng;
3945 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3947 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3952 * Resize a counter container.
3955 * Pointer to the Ethernet device structure.
3957 * Whether the pool is for counter that was allocated by batch command.
3960 * The new container pointer on success, otherwise NULL and rte_errno is set.
3962 static struct mlx5_pools_container *
3963 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3965 struct mlx5_priv *priv = dev->data->dev_private;
3966 struct mlx5_pools_container *cont =
3967 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3968 struct mlx5_pools_container *new_cont =
3969 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3970 struct mlx5_counter_stats_mem_mng *mem_mng;
3971 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3972 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3975 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3976 /* The last resize still hasn't detected by the host thread. */
3980 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3981 if (!new_cont->pools) {
3986 memcpy(new_cont->pools, cont->pools, cont->n *
3987 sizeof(struct mlx5_flow_counter_pool *));
3988 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3989 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3991 rte_free(new_cont->pools);
3994 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3995 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3996 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3998 new_cont->n = resize;
3999 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4000 TAILQ_INIT(&new_cont->pool_list);
4001 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4002 new_cont->init_mem_mng = mem_mng;
4004 /* Flip the master container. */
4005 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4010 * Query a devx flow counter.
4013 * Pointer to the Ethernet device structure.
4015 * Pointer to the flow counter.
4017 * The statistics value of packets.
4019 * The statistics value of bytes.
4022 * 0 on success, otherwise a negative errno value and rte_errno is set.
4025 _flow_dv_query_count(struct rte_eth_dev *dev,
4026 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4029 struct mlx5_priv *priv = dev->data->dev_private;
4030 struct mlx5_flow_counter_pool *pool =
4031 flow_dv_counter_pool_get(cnt);
4032 int offset = cnt - &pool->counters_raw[0];
4034 if (priv->counter_fallback)
4035 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4037 rte_spinlock_lock(&pool->sl);
4039 * The single counters allocation may allocate smaller ID than the
4040 * current allocated in parallel to the host reading.
4041 * In this case the new counter values must be reported as 0.
4043 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4047 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4048 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4050 rte_spinlock_unlock(&pool->sl);
4055 * Create and initialize a new counter pool.
4058 * Pointer to the Ethernet device structure.
4060 * The devX counter handle.
4062 * Whether the pool is for counter that was allocated by batch command.
4065 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4067 static struct mlx5_flow_counter_pool *
4068 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4071 struct mlx5_priv *priv = dev->data->dev_private;
4072 struct mlx5_flow_counter_pool *pool;
4073 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4075 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4078 if (cont->n == n_valid) {
4079 cont = flow_dv_container_resize(dev, batch);
4083 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4084 sizeof(struct mlx5_flow_counter);
4085 pool = rte_calloc(__func__, 1, size, 0);
4090 pool->min_dcs = dcs;
4091 pool->raw = cont->init_mem_mng->raws + n_valid %
4092 MLX5_CNT_CONTAINER_RESIZE;
4093 pool->raw_hw = NULL;
4094 rte_spinlock_init(&pool->sl);
4096 * The generation of the new allocated counters in this pool is 0, 2 in
4097 * the pool generation makes all the counters valid for allocation.
4099 rte_atomic64_set(&pool->query_gen, 0x2);
4100 TAILQ_INIT(&pool->counters);
4101 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4102 cont->pools[n_valid] = pool;
4103 /* Pool initialization must be updated before host thread access. */
4105 rte_atomic16_add(&cont->n_valid, 1);
4110 * Prepare a new counter and/or a new counter pool.
4113 * Pointer to the Ethernet device structure.
4114 * @param[out] cnt_free
4115 * Where to put the pointer of a new counter.
4117 * Whether the pool is for counter that was allocated by batch command.
4120 * The free counter pool pointer and @p cnt_free is set on success,
4121 * NULL otherwise and rte_errno is set.
4123 static struct mlx5_flow_counter_pool *
4124 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4125 struct mlx5_flow_counter **cnt_free,
4128 struct mlx5_priv *priv = dev->data->dev_private;
4129 struct mlx5_flow_counter_pool *pool;
4130 struct mlx5_devx_obj *dcs = NULL;
4131 struct mlx5_flow_counter *cnt;
4135 /* bulk_bitmap must be 0 for single counter allocation. */
4136 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4139 pool = flow_dv_find_pool_by_id
4140 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4142 pool = flow_dv_pool_create(dev, dcs, batch);
4144 mlx5_devx_cmd_destroy(dcs);
4147 } else if (dcs->id < pool->min_dcs->id) {
4148 rte_atomic64_set(&pool->a64_dcs,
4149 (int64_t)(uintptr_t)dcs);
4151 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4152 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4157 /* bulk_bitmap is in 128 counters units. */
4158 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4159 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4161 rte_errno = ENODATA;
4164 pool = flow_dv_pool_create(dev, dcs, batch);
4166 mlx5_devx_cmd_destroy(dcs);
4169 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4170 cnt = &pool->counters_raw[i];
4172 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4174 *cnt_free = &pool->counters_raw[0];
4179 * Search for existed shared counter.
4182 * Pointer to the relevant counter pool container.
4184 * The shared counter ID to search.
4187 * NULL if not existed, otherwise pointer to the shared counter.
4189 static struct mlx5_flow_counter *
4190 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4193 static struct mlx5_flow_counter *cnt;
4194 struct mlx5_flow_counter_pool *pool;
4197 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4198 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4199 cnt = &pool->counters_raw[i];
4200 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4208 * Allocate a flow counter.
4211 * Pointer to the Ethernet device structure.
4213 * Indicate if this counter is shared with other flows.
4215 * Counter identifier.
4217 * Counter flow group.
4220 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4222 static struct mlx5_flow_counter *
4223 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4226 struct mlx5_priv *priv = dev->data->dev_private;
4227 struct mlx5_flow_counter_pool *pool = NULL;
4228 struct mlx5_flow_counter *cnt_free = NULL;
4230 * Currently group 0 flow counter cannot be assigned to a flow if it is
4231 * not the first one in the batch counter allocation, so it is better
4232 * to allocate counters one by one for these flows in a separate
4234 * A counter can be shared between different groups so need to take
4235 * shared counters from the single container.
4237 uint32_t batch = (group && !shared) ? 1 : 0;
4238 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4241 if (priv->counter_fallback)
4242 return flow_dv_counter_alloc_fallback(dev, shared, id);
4243 if (!priv->config.devx) {
4244 rte_errno = ENOTSUP;
4248 cnt_free = flow_dv_counter_shared_search(cont, id);
4250 if (cnt_free->ref_cnt + 1 == 0) {
4254 cnt_free->ref_cnt++;
4258 /* Pools which has a free counters are in the start. */
4259 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4261 * The free counter reset values must be updated between the
4262 * counter release to the counter allocation, so, at least one
4263 * query must be done in this time. ensure it by saving the
4264 * query generation in the release time.
4265 * The free list is sorted according to the generation - so if
4266 * the first one is not updated, all the others are not
4269 cnt_free = TAILQ_FIRST(&pool->counters);
4270 if (cnt_free && cnt_free->query_gen + 1 <
4271 rte_atomic64_read(&pool->query_gen))
4276 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4280 cnt_free->batch = batch;
4281 /* Create a DV counter action only in the first time usage. */
4282 if (!cnt_free->action) {
4284 struct mlx5_devx_obj *dcs;
4287 offset = cnt_free - &pool->counters_raw[0];
4288 dcs = pool->min_dcs;
4291 dcs = cnt_free->dcs;
4293 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4295 if (!cnt_free->action) {
4300 /* Update the counter reset values. */
4301 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4304 cnt_free->shared = shared;
4305 cnt_free->ref_cnt = 1;
4307 if (!priv->sh->cmng.query_thread_on)
4308 /* Start the asynchronous batch query by the host thread. */
4309 mlx5_set_query_alarm(priv->sh);
4310 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4311 if (TAILQ_EMPTY(&pool->counters)) {
4312 /* Move the pool to the end of the container pool list. */
4313 TAILQ_REMOVE(&cont->pool_list, pool, next);
4314 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4320 * Release a flow counter.
4323 * Pointer to the Ethernet device structure.
4324 * @param[in] counter
4325 * Pointer to the counter handler.
4328 flow_dv_counter_release(struct rte_eth_dev *dev,
4329 struct mlx5_flow_counter *counter)
4331 struct mlx5_priv *priv = dev->data->dev_private;
4335 if (priv->counter_fallback) {
4336 flow_dv_counter_release_fallback(dev, counter);
4339 if (--counter->ref_cnt == 0) {
4340 struct mlx5_flow_counter_pool *pool =
4341 flow_dv_counter_pool_get(counter);
4343 /* Put the counter in the end - the last updated one. */
4344 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4345 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4350 * Verify the @p attributes will be correctly understood by the NIC and store
4351 * them in the @p flow if everything is correct.
4354 * Pointer to dev struct.
4355 * @param[in] attributes
4356 * Pointer to flow attributes
4357 * @param[in] external
4358 * This flow rule is created by request external to PMD.
4360 * Pointer to error structure.
4363 * 0 on success, a negative errno value otherwise and rte_errno is set.
4366 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4367 const struct rte_flow_attr *attributes,
4368 bool external __rte_unused,
4369 struct rte_flow_error *error)
4371 struct mlx5_priv *priv = dev->data->dev_private;
4372 uint32_t priority_max = priv->config.flow_prio - 1;
4374 #ifndef HAVE_MLX5DV_DR
4375 if (attributes->group)
4376 return rte_flow_error_set(error, ENOTSUP,
4377 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4379 "groups are not supported");
4384 ret = mlx5_flow_group_to_table(attributes, external,
4390 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4391 attributes->priority >= priority_max)
4392 return rte_flow_error_set(error, ENOTSUP,
4393 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4395 "priority out of range");
4396 if (attributes->transfer) {
4397 if (!priv->config.dv_esw_en)
4398 return rte_flow_error_set
4400 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4401 "E-Switch dr is not supported");
4402 if (!(priv->representor || priv->master))
4403 return rte_flow_error_set
4404 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4405 NULL, "E-Switch configuration can only be"
4406 " done by a master or a representor device");
4407 if (attributes->egress)
4408 return rte_flow_error_set
4410 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4411 "egress is not supported");
4413 if (!(attributes->egress ^ attributes->ingress))
4414 return rte_flow_error_set(error, ENOTSUP,
4415 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4416 "must specify exactly one of "
4417 "ingress or egress");
4422 * Internal validation function. For validating both actions and items.
4425 * Pointer to the rte_eth_dev structure.
4427 * Pointer to the flow attributes.
4429 * Pointer to the list of items.
4430 * @param[in] actions
4431 * Pointer to the list of actions.
4432 * @param[in] external
4433 * This flow rule is created by request external to PMD.
4435 * Pointer to the error structure.
4438 * 0 on success, a negative errno value otherwise and rte_errno is set.
4441 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4442 const struct rte_flow_item items[],
4443 const struct rte_flow_action actions[],
4444 bool external, struct rte_flow_error *error)
4447 uint64_t action_flags = 0;
4448 uint64_t item_flags = 0;
4449 uint64_t last_item = 0;
4450 uint8_t next_protocol = 0xff;
4451 uint16_t ether_type = 0;
4453 const struct rte_flow_item *gre_item = NULL;
4454 struct rte_flow_item_tcp nic_tcp_mask = {
4457 .src_port = RTE_BE16(UINT16_MAX),
4458 .dst_port = RTE_BE16(UINT16_MAX),
4461 struct mlx5_priv *priv = dev->data->dev_private;
4462 struct mlx5_dev_config *dev_conf = &priv->config;
4466 ret = flow_dv_validate_attributes(dev, attr, external, error);
4469 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4470 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4471 int type = items->type;
4474 case RTE_FLOW_ITEM_TYPE_VOID:
4476 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4477 ret = flow_dv_validate_item_port_id
4478 (dev, items, attr, item_flags, error);
4481 last_item = MLX5_FLOW_ITEM_PORT_ID;
4483 case RTE_FLOW_ITEM_TYPE_ETH:
4484 ret = mlx5_flow_validate_item_eth(items, item_flags,
4488 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4489 MLX5_FLOW_LAYER_OUTER_L2;
4490 if (items->mask != NULL && items->spec != NULL) {
4492 ((const struct rte_flow_item_eth *)
4495 ((const struct rte_flow_item_eth *)
4497 ether_type = rte_be_to_cpu_16(ether_type);
4502 case RTE_FLOW_ITEM_TYPE_VLAN:
4503 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4507 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4508 MLX5_FLOW_LAYER_OUTER_VLAN;
4509 if (items->mask != NULL && items->spec != NULL) {
4511 ((const struct rte_flow_item_vlan *)
4512 items->spec)->inner_type;
4514 ((const struct rte_flow_item_vlan *)
4515 items->mask)->inner_type;
4516 ether_type = rte_be_to_cpu_16(ether_type);
4521 case RTE_FLOW_ITEM_TYPE_IPV4:
4522 mlx5_flow_tunnel_ip_check(items, next_protocol,
4523 &item_flags, &tunnel);
4524 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4530 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4531 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4532 if (items->mask != NULL &&
4533 ((const struct rte_flow_item_ipv4 *)
4534 items->mask)->hdr.next_proto_id) {
4536 ((const struct rte_flow_item_ipv4 *)
4537 (items->spec))->hdr.next_proto_id;
4539 ((const struct rte_flow_item_ipv4 *)
4540 (items->mask))->hdr.next_proto_id;
4542 /* Reset for inner layer. */
4543 next_protocol = 0xff;
4546 case RTE_FLOW_ITEM_TYPE_IPV6:
4547 mlx5_flow_tunnel_ip_check(items, next_protocol,
4548 &item_flags, &tunnel);
4549 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4555 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4556 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4557 if (items->mask != NULL &&
4558 ((const struct rte_flow_item_ipv6 *)
4559 items->mask)->hdr.proto) {
4561 ((const struct rte_flow_item_ipv6 *)
4562 items->spec)->hdr.proto;
4564 ((const struct rte_flow_item_ipv6 *)
4565 items->mask)->hdr.proto;
4567 /* Reset for inner layer. */
4568 next_protocol = 0xff;
4571 case RTE_FLOW_ITEM_TYPE_TCP:
4572 ret = mlx5_flow_validate_item_tcp
4579 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4580 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4582 case RTE_FLOW_ITEM_TYPE_UDP:
4583 ret = mlx5_flow_validate_item_udp(items, item_flags,
4588 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4589 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4591 case RTE_FLOW_ITEM_TYPE_GRE:
4592 ret = mlx5_flow_validate_item_gre(items, item_flags,
4593 next_protocol, error);
4597 last_item = MLX5_FLOW_LAYER_GRE;
4599 case RTE_FLOW_ITEM_TYPE_NVGRE:
4600 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4605 last_item = MLX5_FLOW_LAYER_NVGRE;
4607 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4608 ret = mlx5_flow_validate_item_gre_key
4609 (items, item_flags, gre_item, error);
4612 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4614 case RTE_FLOW_ITEM_TYPE_VXLAN:
4615 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4619 last_item = MLX5_FLOW_LAYER_VXLAN;
4621 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4622 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4627 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4629 case RTE_FLOW_ITEM_TYPE_GENEVE:
4630 ret = mlx5_flow_validate_item_geneve(items,
4635 last_item = MLX5_FLOW_LAYER_GENEVE;
4637 case RTE_FLOW_ITEM_TYPE_MPLS:
4638 ret = mlx5_flow_validate_item_mpls(dev, items,
4643 last_item = MLX5_FLOW_LAYER_MPLS;
4646 case RTE_FLOW_ITEM_TYPE_MARK:
4647 ret = flow_dv_validate_item_mark(dev, items, attr,
4651 last_item = MLX5_FLOW_ITEM_MARK;
4653 case RTE_FLOW_ITEM_TYPE_META:
4654 ret = flow_dv_validate_item_meta(dev, items, attr,
4658 last_item = MLX5_FLOW_ITEM_METADATA;
4660 case RTE_FLOW_ITEM_TYPE_ICMP:
4661 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4666 last_item = MLX5_FLOW_LAYER_ICMP;
4668 case RTE_FLOW_ITEM_TYPE_ICMP6:
4669 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4674 last_item = MLX5_FLOW_LAYER_ICMP6;
4676 case RTE_FLOW_ITEM_TYPE_TAG:
4677 ret = flow_dv_validate_item_tag(dev, items,
4681 last_item = MLX5_FLOW_ITEM_TAG;
4683 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4684 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4686 case RTE_FLOW_ITEM_TYPE_GTP:
4687 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4691 last_item = MLX5_FLOW_LAYER_GTP;
4694 return rte_flow_error_set(error, ENOTSUP,
4695 RTE_FLOW_ERROR_TYPE_ITEM,
4696 NULL, "item not supported");
4698 item_flags |= last_item;
4700 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4701 int type = actions->type;
4702 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4703 return rte_flow_error_set(error, ENOTSUP,
4704 RTE_FLOW_ERROR_TYPE_ACTION,
4705 actions, "too many actions");
4707 case RTE_FLOW_ACTION_TYPE_VOID:
4709 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4710 ret = flow_dv_validate_action_port_id(dev,
4717 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4720 case RTE_FLOW_ACTION_TYPE_FLAG:
4721 ret = flow_dv_validate_action_flag(dev, action_flags,
4725 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4726 /* Count all modify-header actions as one. */
4727 if (!(action_flags &
4728 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4730 action_flags |= MLX5_FLOW_ACTION_FLAG |
4731 MLX5_FLOW_ACTION_MARK_EXT;
4733 action_flags |= MLX5_FLOW_ACTION_FLAG;
4737 case RTE_FLOW_ACTION_TYPE_MARK:
4738 ret = flow_dv_validate_action_mark(dev, actions,
4743 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4744 /* Count all modify-header actions as one. */
4745 if (!(action_flags &
4746 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4748 action_flags |= MLX5_FLOW_ACTION_MARK |
4749 MLX5_FLOW_ACTION_MARK_EXT;
4751 action_flags |= MLX5_FLOW_ACTION_MARK;
4755 case RTE_FLOW_ACTION_TYPE_SET_META:
4756 ret = flow_dv_validate_action_set_meta(dev, actions,
4761 /* Count all modify-header actions as one action. */
4762 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4764 action_flags |= MLX5_FLOW_ACTION_SET_META;
4766 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4767 ret = flow_dv_validate_action_set_tag(dev, actions,
4772 /* Count all modify-header actions as one action. */
4773 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4775 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4777 case RTE_FLOW_ACTION_TYPE_DROP:
4778 ret = mlx5_flow_validate_action_drop(action_flags,
4782 action_flags |= MLX5_FLOW_ACTION_DROP;
4785 case RTE_FLOW_ACTION_TYPE_QUEUE:
4786 ret = mlx5_flow_validate_action_queue(actions,
4791 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4794 case RTE_FLOW_ACTION_TYPE_RSS:
4795 ret = mlx5_flow_validate_action_rss(actions,
4801 action_flags |= MLX5_FLOW_ACTION_RSS;
4804 case RTE_FLOW_ACTION_TYPE_COUNT:
4805 ret = flow_dv_validate_action_count(dev, error);
4808 action_flags |= MLX5_FLOW_ACTION_COUNT;
4811 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4812 if (flow_dv_validate_action_pop_vlan(dev,
4818 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4821 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4822 ret = flow_dv_validate_action_push_vlan(action_flags,
4828 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4831 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4832 ret = flow_dv_validate_action_set_vlan_pcp
4833 (action_flags, actions, error);
4836 /* Count PCP with push_vlan command. */
4837 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4839 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4840 ret = flow_dv_validate_action_set_vlan_vid
4841 (item_flags, action_flags,
4845 /* Count VID with push_vlan command. */
4846 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4848 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4849 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4850 ret = flow_dv_validate_action_l2_encap(action_flags,
4855 action_flags |= actions->type ==
4856 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4857 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4858 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4861 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4862 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4863 ret = flow_dv_validate_action_l2_decap(action_flags,
4867 action_flags |= actions->type ==
4868 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4869 MLX5_FLOW_ACTION_VXLAN_DECAP :
4870 MLX5_FLOW_ACTION_NVGRE_DECAP;
4873 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4874 ret = flow_dv_validate_action_raw_encap(action_flags,
4879 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4882 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4883 ret = flow_dv_validate_action_raw_decap(action_flags,
4888 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4891 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4892 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4893 ret = flow_dv_validate_action_modify_mac(action_flags,
4899 /* Count all modify-header actions as one action. */
4900 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4902 action_flags |= actions->type ==
4903 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4904 MLX5_FLOW_ACTION_SET_MAC_SRC :
4905 MLX5_FLOW_ACTION_SET_MAC_DST;
4908 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4909 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4910 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4916 /* Count all modify-header actions as one action. */
4917 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4919 action_flags |= actions->type ==
4920 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4921 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4922 MLX5_FLOW_ACTION_SET_IPV4_DST;
4924 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4925 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4926 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4932 /* Count all modify-header actions as one action. */
4933 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4935 action_flags |= actions->type ==
4936 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4937 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4938 MLX5_FLOW_ACTION_SET_IPV6_DST;
4940 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4941 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4942 ret = flow_dv_validate_action_modify_tp(action_flags,
4948 /* Count all modify-header actions as one action. */
4949 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4951 action_flags |= actions->type ==
4952 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4953 MLX5_FLOW_ACTION_SET_TP_SRC :
4954 MLX5_FLOW_ACTION_SET_TP_DST;
4956 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4957 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4958 ret = flow_dv_validate_action_modify_ttl(action_flags,
4964 /* Count all modify-header actions as one action. */
4965 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4967 action_flags |= actions->type ==
4968 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4969 MLX5_FLOW_ACTION_SET_TTL :
4970 MLX5_FLOW_ACTION_DEC_TTL;
4972 case RTE_FLOW_ACTION_TYPE_JUMP:
4973 ret = flow_dv_validate_action_jump(actions,
4980 action_flags |= MLX5_FLOW_ACTION_JUMP;
4982 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4983 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4984 ret = flow_dv_validate_action_modify_tcp_seq
4991 /* Count all modify-header actions as one action. */
4992 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4994 action_flags |= actions->type ==
4995 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4996 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4997 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4999 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5000 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5001 ret = flow_dv_validate_action_modify_tcp_ack
5008 /* Count all modify-header actions as one action. */
5009 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5011 action_flags |= actions->type ==
5012 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5013 MLX5_FLOW_ACTION_INC_TCP_ACK :
5014 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5016 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5017 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5018 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5020 case RTE_FLOW_ACTION_TYPE_METER:
5021 ret = mlx5_flow_validate_action_meter(dev,
5027 action_flags |= MLX5_FLOW_ACTION_METER;
5030 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5031 ret = flow_dv_validate_action_modify_ipv4_dscp
5038 /* Count all modify-header actions as one action. */
5039 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5041 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5043 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5044 ret = flow_dv_validate_action_modify_ipv6_dscp
5051 /* Count all modify-header actions as one action. */
5052 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5054 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5057 return rte_flow_error_set(error, ENOTSUP,
5058 RTE_FLOW_ERROR_TYPE_ACTION,
5060 "action not supported");
5063 /* Eswitch has few restrictions on using items and actions */
5064 if (attr->transfer) {
5065 if (!mlx5_flow_ext_mreg_supported(dev) &&
5066 action_flags & MLX5_FLOW_ACTION_FLAG)
5067 return rte_flow_error_set(error, ENOTSUP,
5068 RTE_FLOW_ERROR_TYPE_ACTION,
5070 "unsupported action FLAG");
5071 if (!mlx5_flow_ext_mreg_supported(dev) &&
5072 action_flags & MLX5_FLOW_ACTION_MARK)
5073 return rte_flow_error_set(error, ENOTSUP,
5074 RTE_FLOW_ERROR_TYPE_ACTION,
5076 "unsupported action MARK");
5077 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5078 return rte_flow_error_set(error, ENOTSUP,
5079 RTE_FLOW_ERROR_TYPE_ACTION,
5081 "unsupported action QUEUE");
5082 if (action_flags & MLX5_FLOW_ACTION_RSS)
5083 return rte_flow_error_set(error, ENOTSUP,
5084 RTE_FLOW_ERROR_TYPE_ACTION,
5086 "unsupported action RSS");
5087 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5088 return rte_flow_error_set(error, EINVAL,
5089 RTE_FLOW_ERROR_TYPE_ACTION,
5091 "no fate action is found");
5093 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5094 return rte_flow_error_set(error, EINVAL,
5095 RTE_FLOW_ERROR_TYPE_ACTION,
5097 "no fate action is found");
5103 * Internal preparation function. Allocates the DV flow size,
5104 * this size is constant.
5107 * Pointer to the flow attributes.
5109 * Pointer to the list of items.
5110 * @param[in] actions
5111 * Pointer to the list of actions.
5113 * Pointer to the error structure.
5116 * Pointer to mlx5_flow object on success,
5117 * otherwise NULL and rte_errno is set.
5119 static struct mlx5_flow *
5120 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5121 const struct rte_flow_item items[] __rte_unused,
5122 const struct rte_flow_action actions[] __rte_unused,
5123 struct rte_flow_error *error)
5125 size_t size = sizeof(struct mlx5_flow);
5126 struct mlx5_flow *dev_flow;
5128 dev_flow = rte_calloc(__func__, 1, size, 0);
5130 rte_flow_error_set(error, ENOMEM,
5131 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5132 "not enough memory to create flow");
5135 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5136 dev_flow->ingress = attr->ingress;
5137 dev_flow->transfer = attr->transfer;
5143 * Sanity check for match mask and value. Similar to check_valid_spec() in
5144 * kernel driver. If unmasked bit is present in value, it returns failure.
5147 * pointer to match mask buffer.
5148 * @param match_value
5149 * pointer to match value buffer.
5152 * 0 if valid, -EINVAL otherwise.
5155 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5157 uint8_t *m = match_mask;
5158 uint8_t *v = match_value;
5161 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5164 "match_value differs from match_criteria"
5165 " %p[%u] != %p[%u]",
5166 match_value, i, match_mask, i);
5175 * Add Ethernet item to matcher and to the value.
5177 * @param[in, out] matcher
5179 * @param[in, out] key
5180 * Flow matcher value.
5182 * Flow pattern to translate.
5184 * Item is inner pattern.
5187 flow_dv_translate_item_eth(void *matcher, void *key,
5188 const struct rte_flow_item *item, int inner)
5190 const struct rte_flow_item_eth *eth_m = item->mask;
5191 const struct rte_flow_item_eth *eth_v = item->spec;
5192 const struct rte_flow_item_eth nic_mask = {
5193 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5194 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5195 .type = RTE_BE16(0xffff),
5207 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5209 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5211 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5213 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5215 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5216 ð_m->dst, sizeof(eth_m->dst));
5217 /* The value must be in the range of the mask. */
5218 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5219 for (i = 0; i < sizeof(eth_m->dst); ++i)
5220 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5221 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5222 ð_m->src, sizeof(eth_m->src));
5223 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5224 /* The value must be in the range of the mask. */
5225 for (i = 0; i < sizeof(eth_m->dst); ++i)
5226 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5227 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5228 rte_be_to_cpu_16(eth_m->type));
5229 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5230 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5234 * Add VLAN item to matcher and to the value.
5236 * @param[in, out] dev_flow
5238 * @param[in, out] matcher
5240 * @param[in, out] key
5241 * Flow matcher value.
5243 * Flow pattern to translate.
5245 * Item is inner pattern.
5248 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5249 void *matcher, void *key,
5250 const struct rte_flow_item *item,
5253 const struct rte_flow_item_vlan *vlan_m = item->mask;
5254 const struct rte_flow_item_vlan *vlan_v = item->spec;
5263 vlan_m = &rte_flow_item_vlan_mask;
5265 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5267 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5269 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5271 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5273 * This is workaround, masks are not supported,
5274 * and pre-validated.
5276 dev_flow->dv.vf_vlan.tag =
5277 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5279 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5280 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5281 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5283 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5284 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5285 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5286 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5287 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5288 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5289 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5290 rte_be_to_cpu_16(vlan_m->inner_type));
5291 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5292 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5296 * Add IPV4 item to matcher and to the value.
5298 * @param[in, out] matcher
5300 * @param[in, out] key
5301 * Flow matcher value.
5303 * Flow pattern to translate.
5305 * Item is inner pattern.
5307 * The group to insert the rule.
5310 flow_dv_translate_item_ipv4(void *matcher, void *key,
5311 const struct rte_flow_item *item,
5312 int inner, uint32_t group)
5314 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5315 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5316 const struct rte_flow_item_ipv4 nic_mask = {
5318 .src_addr = RTE_BE32(0xffffffff),
5319 .dst_addr = RTE_BE32(0xffffffff),
5320 .type_of_service = 0xff,
5321 .next_proto_id = 0xff,
5331 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5333 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5335 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5337 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5340 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5342 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5343 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5348 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5349 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5350 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5351 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5352 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5353 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5354 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5355 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5356 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5357 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5358 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5359 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5360 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5361 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5362 ipv4_m->hdr.type_of_service);
5363 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5364 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5365 ipv4_m->hdr.type_of_service >> 2);
5366 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5367 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5368 ipv4_m->hdr.next_proto_id);
5369 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5370 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5374 * Add IPV6 item to matcher and to the value.
5376 * @param[in, out] matcher
5378 * @param[in, out] key
5379 * Flow matcher value.
5381 * Flow pattern to translate.
5383 * Item is inner pattern.
5385 * The group to insert the rule.
5388 flow_dv_translate_item_ipv6(void *matcher, void *key,
5389 const struct rte_flow_item *item,
5390 int inner, uint32_t group)
5392 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5393 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5394 const struct rte_flow_item_ipv6 nic_mask = {
5397 "\xff\xff\xff\xff\xff\xff\xff\xff"
5398 "\xff\xff\xff\xff\xff\xff\xff\xff",
5400 "\xff\xff\xff\xff\xff\xff\xff\xff"
5401 "\xff\xff\xff\xff\xff\xff\xff\xff",
5402 .vtc_flow = RTE_BE32(0xffffffff),
5409 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5410 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5419 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5421 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5423 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5425 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5428 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5430 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5431 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5436 size = sizeof(ipv6_m->hdr.dst_addr);
5437 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5438 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5439 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5440 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5441 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5442 for (i = 0; i < size; ++i)
5443 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5444 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5445 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5446 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5447 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5448 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5449 for (i = 0; i < size; ++i)
5450 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5452 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5453 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5454 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5455 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5456 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5457 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5460 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5462 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5465 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5467 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5471 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5473 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5474 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5478 * Add TCP item to matcher and to the value.
5480 * @param[in, out] matcher
5482 * @param[in, out] key
5483 * Flow matcher value.
5485 * Flow pattern to translate.
5487 * Item is inner pattern.
5490 flow_dv_translate_item_tcp(void *matcher, void *key,
5491 const struct rte_flow_item *item,
5494 const struct rte_flow_item_tcp *tcp_m = item->mask;
5495 const struct rte_flow_item_tcp *tcp_v = item->spec;
5500 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5502 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5504 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5506 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5508 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5509 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5513 tcp_m = &rte_flow_item_tcp_mask;
5514 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5515 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5517 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5518 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5519 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5521 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5522 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5523 tcp_m->hdr.tcp_flags);
5524 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5525 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5529 * Add UDP item to matcher and to the value.
5531 * @param[in, out] matcher
5533 * @param[in, out] key
5534 * Flow matcher value.
5536 * Flow pattern to translate.
5538 * Item is inner pattern.
5541 flow_dv_translate_item_udp(void *matcher, void *key,
5542 const struct rte_flow_item *item,
5545 const struct rte_flow_item_udp *udp_m = item->mask;
5546 const struct rte_flow_item_udp *udp_v = item->spec;
5551 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5553 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5555 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5557 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5559 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5560 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5564 udp_m = &rte_flow_item_udp_mask;
5565 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5566 rte_be_to_cpu_16(udp_m->hdr.src_port));
5567 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5568 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5569 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5570 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5571 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5572 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5576 * Add GRE optional Key item to matcher and to the value.
5578 * @param[in, out] matcher
5580 * @param[in, out] key
5581 * Flow matcher value.
5583 * Flow pattern to translate.
5585 * Item is inner pattern.
5588 flow_dv_translate_item_gre_key(void *matcher, void *key,
5589 const struct rte_flow_item *item)
5591 const rte_be32_t *key_m = item->mask;
5592 const rte_be32_t *key_v = item->spec;
5593 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5594 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5595 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5600 key_m = &gre_key_default_mask;
5601 /* GRE K bit must be on and should already be validated */
5602 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5603 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5604 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5605 rte_be_to_cpu_32(*key_m) >> 8);
5606 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5607 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5608 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5609 rte_be_to_cpu_32(*key_m) & 0xFF);
5610 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5611 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5615 * Add GRE item to matcher and to the value.
5617 * @param[in, out] matcher
5619 * @param[in, out] key
5620 * Flow matcher value.
5622 * Flow pattern to translate.
5624 * Item is inner pattern.
5627 flow_dv_translate_item_gre(void *matcher, void *key,
5628 const struct rte_flow_item *item,
5631 const struct rte_flow_item_gre *gre_m = item->mask;
5632 const struct rte_flow_item_gre *gre_v = item->spec;
5635 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5636 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5643 uint16_t s_present:1;
5644 uint16_t k_present:1;
5645 uint16_t rsvd_bit1:1;
5646 uint16_t c_present:1;
5650 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5653 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5655 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5657 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5659 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5661 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5666 gre_m = &rte_flow_item_gre_mask;
5667 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5668 rte_be_to_cpu_16(gre_m->protocol));
5669 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5670 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5671 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5672 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5673 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5674 gre_crks_rsvd0_ver_m.c_present);
5675 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5676 gre_crks_rsvd0_ver_v.c_present &
5677 gre_crks_rsvd0_ver_m.c_present);
5678 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5679 gre_crks_rsvd0_ver_m.k_present);
5680 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5681 gre_crks_rsvd0_ver_v.k_present &
5682 gre_crks_rsvd0_ver_m.k_present);
5683 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5684 gre_crks_rsvd0_ver_m.s_present);
5685 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5686 gre_crks_rsvd0_ver_v.s_present &
5687 gre_crks_rsvd0_ver_m.s_present);
5691 * Add NVGRE item to matcher and to the value.
5693 * @param[in, out] matcher
5695 * @param[in, out] key
5696 * Flow matcher value.
5698 * Flow pattern to translate.
5700 * Item is inner pattern.
5703 flow_dv_translate_item_nvgre(void *matcher, void *key,
5704 const struct rte_flow_item *item,
5707 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5708 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5709 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5710 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5711 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5712 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5718 /* For NVGRE, GRE header fields must be set with defined values. */
5719 const struct rte_flow_item_gre gre_spec = {
5720 .c_rsvd0_ver = RTE_BE16(0x2000),
5721 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5723 const struct rte_flow_item_gre gre_mask = {
5724 .c_rsvd0_ver = RTE_BE16(0xB000),
5725 .protocol = RTE_BE16(UINT16_MAX),
5727 const struct rte_flow_item gre_item = {
5732 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5736 nvgre_m = &rte_flow_item_nvgre_mask;
5737 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5738 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5739 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5740 memcpy(gre_key_m, tni_flow_id_m, size);
5741 for (i = 0; i < size; ++i)
5742 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5746 * Add VXLAN item to matcher and to the value.
5748 * @param[in, out] matcher
5750 * @param[in, out] key
5751 * Flow matcher value.
5753 * Flow pattern to translate.
5755 * Item is inner pattern.
5758 flow_dv_translate_item_vxlan(void *matcher, void *key,
5759 const struct rte_flow_item *item,
5762 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5763 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5766 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5767 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5775 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5777 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5779 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5781 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5783 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5784 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5785 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5786 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5792 vxlan_m = &rte_flow_item_vxlan_mask;
5793 size = sizeof(vxlan_m->vni);
5794 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5795 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5796 memcpy(vni_m, vxlan_m->vni, size);
5797 for (i = 0; i < size; ++i)
5798 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5802 * Add Geneve item to matcher and to the value.
5804 * @param[in, out] matcher
5806 * @param[in, out] key
5807 * Flow matcher value.
5809 * Flow pattern to translate.
5811 * Item is inner pattern.
5815 flow_dv_translate_item_geneve(void *matcher, void *key,
5816 const struct rte_flow_item *item, int inner)
5818 const struct rte_flow_item_geneve *geneve_m = item->mask;
5819 const struct rte_flow_item_geneve *geneve_v = item->spec;
5822 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5823 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5832 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5834 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5836 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5838 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5840 dport = MLX5_UDP_PORT_GENEVE;
5841 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5842 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5843 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5848 geneve_m = &rte_flow_item_geneve_mask;
5849 size = sizeof(geneve_m->vni);
5850 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5851 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5852 memcpy(vni_m, geneve_m->vni, size);
5853 for (i = 0; i < size; ++i)
5854 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5855 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5856 rte_be_to_cpu_16(geneve_m->protocol));
5857 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5858 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5859 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5860 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5861 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5862 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5863 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5864 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5865 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5866 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5867 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5868 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5869 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5873 * Add MPLS item to matcher and to the value.
5875 * @param[in, out] matcher
5877 * @param[in, out] key
5878 * Flow matcher value.
5880 * Flow pattern to translate.
5881 * @param[in] prev_layer
5882 * The protocol layer indicated in previous item.
5884 * Item is inner pattern.
5887 flow_dv_translate_item_mpls(void *matcher, void *key,
5888 const struct rte_flow_item *item,
5889 uint64_t prev_layer,
5892 const uint32_t *in_mpls_m = item->mask;
5893 const uint32_t *in_mpls_v = item->spec;
5894 uint32_t *out_mpls_m = 0;
5895 uint32_t *out_mpls_v = 0;
5896 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5897 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5898 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5900 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5901 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5902 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5904 switch (prev_layer) {
5905 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5906 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5907 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5908 MLX5_UDP_PORT_MPLS);
5910 case MLX5_FLOW_LAYER_GRE:
5911 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5912 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5913 RTE_ETHER_TYPE_MPLS);
5916 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5917 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5924 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5925 switch (prev_layer) {
5926 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5928 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5929 outer_first_mpls_over_udp);
5931 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5932 outer_first_mpls_over_udp);
5934 case MLX5_FLOW_LAYER_GRE:
5936 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5937 outer_first_mpls_over_gre);
5939 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5940 outer_first_mpls_over_gre);
5943 /* Inner MPLS not over GRE is not supported. */
5946 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5950 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5956 if (out_mpls_m && out_mpls_v) {
5957 *out_mpls_m = *in_mpls_m;
5958 *out_mpls_v = *in_mpls_v & *in_mpls_m;
5963 * Add metadata register item to matcher
5965 * @param[in, out] matcher
5967 * @param[in, out] key
5968 * Flow matcher value.
5969 * @param[in] reg_type
5970 * Type of device metadata register
5977 flow_dv_match_meta_reg(void *matcher, void *key,
5978 enum modify_reg reg_type,
5979 uint32_t data, uint32_t mask)
5982 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5984 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5990 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5991 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5994 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5995 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5999 * The metadata register C0 field might be divided into
6000 * source vport index and META item value, we should set
6001 * this field according to specified mask, not as whole one.
6003 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6005 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6006 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6009 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6012 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6013 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6016 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6017 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6020 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6021 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6024 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6025 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6028 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6029 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6032 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6033 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6036 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6037 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6046 * Add MARK item to matcher
6049 * The device to configure through.
6050 * @param[in, out] matcher
6052 * @param[in, out] key
6053 * Flow matcher value.
6055 * Flow pattern to translate.
6058 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6059 void *matcher, void *key,
6060 const struct rte_flow_item *item)
6062 struct mlx5_priv *priv = dev->data->dev_private;
6063 const struct rte_flow_item_mark *mark;
6067 mark = item->mask ? (const void *)item->mask :
6068 &rte_flow_item_mark_mask;
6069 mask = mark->id & priv->sh->dv_mark_mask;
6070 mark = (const void *)item->spec;
6072 value = mark->id & priv->sh->dv_mark_mask & mask;
6074 enum modify_reg reg;
6076 /* Get the metadata register index for the mark. */
6077 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6079 if (reg == REG_C_0) {
6080 struct mlx5_priv *priv = dev->data->dev_private;
6081 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6082 uint32_t shl_c0 = rte_bsf32(msk_c0);
6088 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6093 * Add META item to matcher
6096 * The devich to configure through.
6097 * @param[in, out] matcher
6099 * @param[in, out] key
6100 * Flow matcher value.
6102 * Attributes of flow that includes this item.
6104 * Flow pattern to translate.
6107 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6108 void *matcher, void *key,
6109 const struct rte_flow_attr *attr,
6110 const struct rte_flow_item *item)
6112 const struct rte_flow_item_meta *meta_m;
6113 const struct rte_flow_item_meta *meta_v;
6115 meta_m = (const void *)item->mask;
6117 meta_m = &rte_flow_item_meta_mask;
6118 meta_v = (const void *)item->spec;
6120 enum modify_reg reg;
6121 uint32_t value = meta_v->data;
6122 uint32_t mask = meta_m->data;
6124 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6128 * In datapath code there is no endianness
6129 * coversions for perfromance reasons, all
6130 * pattern conversions are done in rte_flow.
6132 value = rte_cpu_to_be_32(value);
6133 mask = rte_cpu_to_be_32(mask);
6134 if (reg == REG_C_0) {
6135 struct mlx5_priv *priv = dev->data->dev_private;
6136 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6137 uint32_t shl_c0 = rte_bsf32(msk_c0);
6138 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6139 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6147 assert(!(~msk_c0 & mask));
6149 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6154 * Add vport metadata Reg C0 item to matcher
6156 * @param[in, out] matcher
6158 * @param[in, out] key
6159 * Flow matcher value.
6161 * Flow pattern to translate.
6164 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6165 uint32_t value, uint32_t mask)
6167 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6171 * Add tag item to matcher
6174 * The devich to configure through.
6175 * @param[in, out] matcher
6177 * @param[in, out] key
6178 * Flow matcher value.
6180 * Flow pattern to translate.
6183 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6184 void *matcher, void *key,
6185 const struct rte_flow_item *item)
6187 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6188 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6189 uint32_t mask, value;
6192 value = tag_v->data;
6193 mask = tag_m ? tag_m->data : UINT32_MAX;
6194 if (tag_v->id == REG_C_0) {
6195 struct mlx5_priv *priv = dev->data->dev_private;
6196 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6197 uint32_t shl_c0 = rte_bsf32(msk_c0);
6203 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6207 * Add TAG item to matcher
6210 * The devich to configure through.
6211 * @param[in, out] matcher
6213 * @param[in, out] key
6214 * Flow matcher value.
6216 * Flow pattern to translate.
6219 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6220 void *matcher, void *key,
6221 const struct rte_flow_item *item)
6223 const struct rte_flow_item_tag *tag_v = item->spec;
6224 const struct rte_flow_item_tag *tag_m = item->mask;
6225 enum modify_reg reg;
6228 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6229 /* Get the metadata register index for the tag. */
6230 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6232 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6236 * Add source vport match to the specified matcher.
6238 * @param[in, out] matcher
6240 * @param[in, out] key
6241 * Flow matcher value.
6243 * Source vport value to match
6248 flow_dv_translate_item_source_vport(void *matcher, void *key,
6249 int16_t port, uint16_t mask)
6251 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6252 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6254 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6255 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6259 * Translate port-id item to eswitch match on port-id.
6262 * The devich to configure through.
6263 * @param[in, out] matcher
6265 * @param[in, out] key
6266 * Flow matcher value.
6268 * Flow pattern to translate.
6271 * 0 on success, a negative errno value otherwise.
6274 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6275 void *key, const struct rte_flow_item *item)
6277 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6278 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6279 struct mlx5_priv *priv;
6282 mask = pid_m ? pid_m->id : 0xffff;
6283 id = pid_v ? pid_v->id : dev->data->port_id;
6284 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6287 /* Translate to vport field or to metadata, depending on mode. */
6288 if (priv->vport_meta_mask)
6289 flow_dv_translate_item_meta_vport(matcher, key,
6290 priv->vport_meta_tag,
6291 priv->vport_meta_mask);
6293 flow_dv_translate_item_source_vport(matcher, key,
6294 priv->vport_id, mask);
6299 * Add ICMP6 item to matcher and to the value.
6301 * @param[in, out] matcher
6303 * @param[in, out] key
6304 * Flow matcher value.
6306 * Flow pattern to translate.
6308 * Item is inner pattern.
6311 flow_dv_translate_item_icmp6(void *matcher, void *key,
6312 const struct rte_flow_item *item,
6315 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6316 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6319 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6321 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6323 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6325 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6327 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6329 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6331 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6332 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6336 icmp6_m = &rte_flow_item_icmp6_mask;
6337 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6338 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6339 icmp6_v->type & icmp6_m->type);
6340 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6341 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6342 icmp6_v->code & icmp6_m->code);
6346 * Add ICMP item to matcher and to the value.
6348 * @param[in, out] matcher
6350 * @param[in, out] key
6351 * Flow matcher value.
6353 * Flow pattern to translate.
6355 * Item is inner pattern.
6358 flow_dv_translate_item_icmp(void *matcher, void *key,
6359 const struct rte_flow_item *item,
6362 const struct rte_flow_item_icmp *icmp_m = item->mask;
6363 const struct rte_flow_item_icmp *icmp_v = item->spec;
6366 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6368 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6370 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6372 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6374 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6376 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6378 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6379 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6383 icmp_m = &rte_flow_item_icmp_mask;
6384 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6385 icmp_m->hdr.icmp_type);
6386 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6387 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6388 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6389 icmp_m->hdr.icmp_code);
6390 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6391 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6395 * Add GTP item to matcher and to the value.
6397 * @param[in, out] matcher
6399 * @param[in, out] key
6400 * Flow matcher value.
6402 * Flow pattern to translate.
6404 * Item is inner pattern.
6407 flow_dv_translate_item_gtp(void *matcher, void *key,
6408 const struct rte_flow_item *item, int inner)
6410 const struct rte_flow_item_gtp *gtp_m = item->mask;
6411 const struct rte_flow_item_gtp *gtp_v = item->spec;
6414 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6416 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6417 uint16_t dport = RTE_GTPU_UDP_PORT;
6420 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6422 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6424 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6426 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6428 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6429 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6435 gtp_m = &rte_flow_item_gtp_mask;
6436 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6437 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6438 gtp_v->msg_type & gtp_m->msg_type);
6439 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6440 rte_be_to_cpu_32(gtp_m->teid));
6441 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6442 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6445 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6447 #define HEADER_IS_ZERO(match_criteria, headers) \
6448 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6449 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6452 * Calculate flow matcher enable bitmap.
6454 * @param match_criteria
6455 * Pointer to flow matcher criteria.
6458 * Bitmap of enabled fields.
6461 flow_dv_matcher_enable(uint32_t *match_criteria)
6463 uint8_t match_criteria_enable;
6465 match_criteria_enable =
6466 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6467 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6468 match_criteria_enable |=
6469 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6470 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6471 match_criteria_enable |=
6472 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6473 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6474 match_criteria_enable |=
6475 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6476 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6477 match_criteria_enable |=
6478 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6479 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6480 return match_criteria_enable;
6487 * @param[in, out] dev
6488 * Pointer to rte_eth_dev structure.
6489 * @param[in] table_id
6492 * Direction of the table.
6493 * @param[in] transfer
6494 * E-Switch or NIC flow.
6496 * pointer to error structure.
6499 * Returns tables resource based on the index, NULL in case of failed.
6501 static struct mlx5_flow_tbl_resource *
6502 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6503 uint32_t table_id, uint8_t egress,
6505 struct rte_flow_error *error)
6507 struct mlx5_priv *priv = dev->data->dev_private;
6508 struct mlx5_ibv_shared *sh = priv->sh;
6509 struct mlx5_flow_tbl_resource *tbl;
6510 union mlx5_flow_tbl_key table_key = {
6512 .table_id = table_id,
6514 .domain = !!transfer,
6515 .direction = !!egress,
6518 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6520 struct mlx5_flow_tbl_data_entry *tbl_data;
6525 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6527 tbl = &tbl_data->tbl;
6528 rte_atomic32_inc(&tbl->refcnt);
6531 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6533 rte_flow_error_set(error, ENOMEM,
6534 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6536 "cannot allocate flow table data entry");
6539 tbl = &tbl_data->tbl;
6540 pos = &tbl_data->entry;
6542 domain = sh->fdb_domain;
6544 domain = sh->tx_domain;
6546 domain = sh->rx_domain;
6547 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6549 rte_flow_error_set(error, ENOMEM,
6550 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6551 NULL, "cannot create flow table object");
6556 * No multi-threads now, but still better to initialize the reference
6557 * count before insert it into the hash list.
6559 rte_atomic32_init(&tbl->refcnt);
6560 /* Jump action reference count is initialized here. */
6561 rte_atomic32_init(&tbl_data->jump.refcnt);
6562 pos->key = table_key.v64;
6563 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6565 rte_flow_error_set(error, -ret,
6566 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6567 "cannot insert flow table data entry");
6568 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6571 rte_atomic32_inc(&tbl->refcnt);
6576 * Release a flow table.
6579 * Pointer to rte_eth_dev structure.
6581 * Table resource to be released.
6584 * Returns 0 if table was released, else return 1;
6587 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6588 struct mlx5_flow_tbl_resource *tbl)
6590 struct mlx5_priv *priv = dev->data->dev_private;
6591 struct mlx5_ibv_shared *sh = priv->sh;
6592 struct mlx5_flow_tbl_data_entry *tbl_data =
6593 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6597 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6598 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6600 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6602 /* remove the entry from the hash list and free memory. */
6603 mlx5_hlist_remove(sh->flow_tbls, pos);
6611 * Register the flow matcher.
6613 * @param[in, out] dev
6614 * Pointer to rte_eth_dev structure.
6615 * @param[in, out] matcher
6616 * Pointer to flow matcher.
6617 * @param[in, out] key
6618 * Pointer to flow table key.
6619 * @parm[in, out] dev_flow
6620 * Pointer to the dev_flow.
6622 * pointer to error structure.
6625 * 0 on success otherwise -errno and errno is set.
6628 flow_dv_matcher_register(struct rte_eth_dev *dev,
6629 struct mlx5_flow_dv_matcher *matcher,
6630 union mlx5_flow_tbl_key *key,
6631 struct mlx5_flow *dev_flow,
6632 struct rte_flow_error *error)
6634 struct mlx5_priv *priv = dev->data->dev_private;
6635 struct mlx5_ibv_shared *sh = priv->sh;
6636 struct mlx5_flow_dv_matcher *cache_matcher;
6637 struct mlx5dv_flow_matcher_attr dv_attr = {
6638 .type = IBV_FLOW_ATTR_NORMAL,
6639 .match_mask = (void *)&matcher->mask,
6641 struct mlx5_flow_tbl_resource *tbl;
6642 struct mlx5_flow_tbl_data_entry *tbl_data;
6644 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6645 key->domain, error);
6647 return -rte_errno; /* No need to refill the error info */
6648 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6649 /* Lookup from cache. */
6650 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6651 if (matcher->crc == cache_matcher->crc &&
6652 matcher->priority == cache_matcher->priority &&
6653 !memcmp((const void *)matcher->mask.buf,
6654 (const void *)cache_matcher->mask.buf,
6655 cache_matcher->mask.size)) {
6657 "%s group %u priority %hd use %s "
6658 "matcher %p: refcnt %d++",
6659 key->domain ? "FDB" : "NIC", key->table_id,
6660 cache_matcher->priority,
6661 key->direction ? "tx" : "rx",
6662 (void *)cache_matcher,
6663 rte_atomic32_read(&cache_matcher->refcnt));
6664 rte_atomic32_inc(&cache_matcher->refcnt);
6665 dev_flow->dv.matcher = cache_matcher;
6666 /* old matcher should not make the table ref++. */
6667 flow_dv_tbl_resource_release(dev, tbl);
6671 /* Register new matcher. */
6672 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6673 if (!cache_matcher) {
6674 flow_dv_tbl_resource_release(dev, tbl);
6675 return rte_flow_error_set(error, ENOMEM,
6676 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6677 "cannot allocate matcher memory");
6679 *cache_matcher = *matcher;
6680 dv_attr.match_criteria_enable =
6681 flow_dv_matcher_enable(cache_matcher->mask.buf);
6682 dv_attr.priority = matcher->priority;
6684 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6685 cache_matcher->matcher_object =
6686 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6687 if (!cache_matcher->matcher_object) {
6688 rte_free(cache_matcher);
6689 #ifdef HAVE_MLX5DV_DR
6690 flow_dv_tbl_resource_release(dev, tbl);
6692 return rte_flow_error_set(error, ENOMEM,
6693 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6694 NULL, "cannot create matcher");
6696 /* Save the table information */
6697 cache_matcher->tbl = tbl;
6698 rte_atomic32_init(&cache_matcher->refcnt);
6699 /* only matcher ref++, table ref++ already done above in get API. */
6700 rte_atomic32_inc(&cache_matcher->refcnt);
6701 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6702 dev_flow->dv.matcher = cache_matcher;
6703 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6704 key->domain ? "FDB" : "NIC", key->table_id,
6705 cache_matcher->priority,
6706 key->direction ? "tx" : "rx", (void *)cache_matcher,
6707 rte_atomic32_read(&cache_matcher->refcnt));
6712 * Find existing tag resource or create and register a new one.
6714 * @param dev[in, out]
6715 * Pointer to rte_eth_dev structure.
6716 * @param[in, out] tag_be24
6717 * Tag value in big endian then R-shift 8.
6718 * @parm[in, out] dev_flow
6719 * Pointer to the dev_flow.
6721 * pointer to error structure.
6724 * 0 on success otherwise -errno and errno is set.
6727 flow_dv_tag_resource_register
6728 (struct rte_eth_dev *dev,
6730 struct mlx5_flow *dev_flow,
6731 struct rte_flow_error *error)
6733 struct mlx5_priv *priv = dev->data->dev_private;
6734 struct mlx5_ibv_shared *sh = priv->sh;
6735 struct mlx5_flow_dv_tag_resource *cache_resource;
6736 struct mlx5_hlist_entry *entry;
6738 /* Lookup a matching resource from cache. */
6739 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6741 cache_resource = container_of
6742 (entry, struct mlx5_flow_dv_tag_resource, entry);
6743 rte_atomic32_inc(&cache_resource->refcnt);
6744 dev_flow->dv.tag_resource = cache_resource;
6745 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6746 (void *)cache_resource,
6747 rte_atomic32_read(&cache_resource->refcnt));
6750 /* Register new resource. */
6751 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6752 if (!cache_resource)
6753 return rte_flow_error_set(error, ENOMEM,
6754 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6755 "cannot allocate resource memory");
6756 cache_resource->entry.key = (uint64_t)tag_be24;
6757 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6758 if (!cache_resource->action) {
6759 rte_free(cache_resource);
6760 return rte_flow_error_set(error, ENOMEM,
6761 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6762 NULL, "cannot create action");
6764 rte_atomic32_init(&cache_resource->refcnt);
6765 rte_atomic32_inc(&cache_resource->refcnt);
6766 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6767 mlx5_glue->destroy_flow_action(cache_resource->action);
6768 rte_free(cache_resource);
6769 return rte_flow_error_set(error, EEXIST,
6770 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6771 NULL, "cannot insert tag");
6773 dev_flow->dv.tag_resource = cache_resource;
6774 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6775 (void *)cache_resource,
6776 rte_atomic32_read(&cache_resource->refcnt));
6784 * Pointer to Ethernet device.
6786 * Pointer to mlx5_flow.
6789 * 1 while a reference on it exists, 0 when freed.
6792 flow_dv_tag_release(struct rte_eth_dev *dev,
6793 struct mlx5_flow_dv_tag_resource *tag)
6795 struct mlx5_priv *priv = dev->data->dev_private;
6796 struct mlx5_ibv_shared *sh = priv->sh;
6799 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6800 dev->data->port_id, (void *)tag,
6801 rte_atomic32_read(&tag->refcnt));
6802 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6803 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6804 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6805 DRV_LOG(DEBUG, "port %u tag %p: removed",
6806 dev->data->port_id, (void *)tag);
6814 * Translate port ID action to vport.
6817 * Pointer to rte_eth_dev structure.
6819 * Pointer to the port ID action.
6820 * @param[out] dst_port_id
6821 * The target port ID.
6823 * Pointer to the error structure.
6826 * 0 on success, a negative errno value otherwise and rte_errno is set.
6829 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6830 const struct rte_flow_action *action,
6831 uint32_t *dst_port_id,
6832 struct rte_flow_error *error)
6835 struct mlx5_priv *priv;
6836 const struct rte_flow_action_port_id *conf =
6837 (const struct rte_flow_action_port_id *)action->conf;
6839 port = conf->original ? dev->data->port_id : conf->id;
6840 priv = mlx5_port_to_eswitch_info(port, false);
6842 return rte_flow_error_set(error, -rte_errno,
6843 RTE_FLOW_ERROR_TYPE_ACTION,
6845 "No eswitch info was found for port");
6846 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6848 * This parameter is transferred to
6849 * mlx5dv_dr_action_create_dest_ib_port().
6851 *dst_port_id = priv->ibv_port;
6854 * Legacy mode, no LAG configurations is supported.
6855 * This parameter is transferred to
6856 * mlx5dv_dr_action_create_dest_vport().
6858 *dst_port_id = priv->vport_id;
6864 * Add Tx queue matcher
6867 * Pointer to the dev struct.
6868 * @param[in, out] matcher
6870 * @param[in, out] key
6871 * Flow matcher value.
6873 * Flow pattern to translate.
6875 * Item is inner pattern.
6878 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6879 void *matcher, void *key,
6880 const struct rte_flow_item *item)
6882 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6883 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6885 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6887 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6888 struct mlx5_txq_ctrl *txq;
6892 queue_m = (const void *)item->mask;
6895 queue_v = (const void *)item->spec;
6898 txq = mlx5_txq_get(dev, queue_v->queue);
6901 queue = txq->obj->sq->id;
6902 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6903 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6904 queue & queue_m->queue);
6905 mlx5_txq_release(dev, queue_v->queue);
6909 * Set the hash fields according to the @p flow information.
6911 * @param[in] dev_flow
6912 * Pointer to the mlx5_flow.
6915 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
6917 struct rte_flow *flow = dev_flow->flow;
6918 uint64_t items = dev_flow->layers;
6920 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
6922 dev_flow->hash_fields = 0;
6923 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
6924 if (flow->rss.level >= 2) {
6925 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
6929 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
6930 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
6931 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
6932 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6933 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
6934 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6935 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
6937 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
6939 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
6940 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
6941 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
6942 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6943 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
6944 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6945 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
6947 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
6950 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
6951 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
6952 if (rss_types & ETH_RSS_UDP) {
6953 if (rss_types & ETH_RSS_L4_SRC_ONLY)
6954 dev_flow->hash_fields |=
6955 IBV_RX_HASH_SRC_PORT_UDP;
6956 else if (rss_types & ETH_RSS_L4_DST_ONLY)
6957 dev_flow->hash_fields |=
6958 IBV_RX_HASH_DST_PORT_UDP;
6960 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
6962 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
6963 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
6964 if (rss_types & ETH_RSS_TCP) {
6965 if (rss_types & ETH_RSS_L4_SRC_ONLY)
6966 dev_flow->hash_fields |=
6967 IBV_RX_HASH_SRC_PORT_TCP;
6968 else if (rss_types & ETH_RSS_L4_DST_ONLY)
6969 dev_flow->hash_fields |=
6970 IBV_RX_HASH_DST_PORT_TCP;
6972 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
6978 * Fill the flow with DV spec, lock free
6979 * (mutex should be acquired by caller).
6982 * Pointer to rte_eth_dev structure.
6983 * @param[in, out] dev_flow
6984 * Pointer to the sub flow.
6986 * Pointer to the flow attributes.
6988 * Pointer to the list of items.
6989 * @param[in] actions
6990 * Pointer to the list of actions.
6992 * Pointer to the error structure.
6995 * 0 on success, a negative errno value otherwise and rte_errno is set.
6998 __flow_dv_translate(struct rte_eth_dev *dev,
6999 struct mlx5_flow *dev_flow,
7000 const struct rte_flow_attr *attr,
7001 const struct rte_flow_item items[],
7002 const struct rte_flow_action actions[],
7003 struct rte_flow_error *error)
7005 struct mlx5_priv *priv = dev->data->dev_private;
7006 struct mlx5_dev_config *dev_conf = &priv->config;
7007 struct rte_flow *flow = dev_flow->flow;
7008 uint64_t item_flags = 0;
7009 uint64_t last_item = 0;
7010 uint64_t action_flags = 0;
7011 uint64_t priority = attr->priority;
7012 struct mlx5_flow_dv_matcher matcher = {
7014 .size = sizeof(matcher.mask.buf),
7018 bool actions_end = false;
7020 struct mlx5_flow_dv_modify_hdr_resource res;
7021 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7022 sizeof(struct mlx5_modification_cmd) *
7023 (MLX5_MAX_MODIFY_NUM + 1)];
7025 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7026 union flow_dv_attr flow_attr = { .attr = 0 };
7028 union mlx5_flow_tbl_key tbl_key;
7029 uint32_t modify_action_position = UINT32_MAX;
7030 void *match_mask = matcher.mask.buf;
7031 void *match_value = dev_flow->dv.value.buf;
7032 uint8_t next_protocol = 0xff;
7033 struct rte_vlan_hdr vlan = { 0 };
7037 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7038 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7039 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7043 dev_flow->group = table;
7045 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7046 if (priority == MLX5_FLOW_PRIO_RSVD)
7047 priority = dev_conf->flow_prio - 1;
7048 /* number of actions must be set to 0 in case of dirty stack. */
7049 mhdr_res->actions_num = 0;
7050 for (; !actions_end ; actions++) {
7051 const struct rte_flow_action_queue *queue;
7052 const struct rte_flow_action_rss *rss;
7053 const struct rte_flow_action *action = actions;
7054 const struct rte_flow_action_count *count = action->conf;
7055 const uint8_t *rss_key;
7056 const struct rte_flow_action_jump *jump_data;
7057 const struct rte_flow_action_meter *mtr;
7058 struct mlx5_flow_tbl_resource *tbl;
7059 uint32_t port_id = 0;
7060 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7061 int action_type = actions->type;
7062 const struct rte_flow_action *found_action = NULL;
7064 switch (action_type) {
7065 case RTE_FLOW_ACTION_TYPE_VOID:
7067 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7068 if (flow_dv_translate_action_port_id(dev, action,
7071 port_id_resource.port_id = port_id;
7072 if (flow_dv_port_id_action_resource_register
7073 (dev, &port_id_resource, dev_flow, error))
7075 dev_flow->dv.actions[actions_n++] =
7076 dev_flow->dv.port_id_action->action;
7077 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7079 case RTE_FLOW_ACTION_TYPE_FLAG:
7080 action_flags |= MLX5_FLOW_ACTION_FLAG;
7081 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7082 struct rte_flow_action_mark mark = {
7083 .id = MLX5_FLOW_MARK_DEFAULT,
7086 if (flow_dv_convert_action_mark(dev, &mark,
7090 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7093 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7094 if (!dev_flow->dv.tag_resource)
7095 if (flow_dv_tag_resource_register
7096 (dev, tag_be, dev_flow, error))
7098 dev_flow->dv.actions[actions_n++] =
7099 dev_flow->dv.tag_resource->action;
7101 case RTE_FLOW_ACTION_TYPE_MARK:
7102 action_flags |= MLX5_FLOW_ACTION_MARK;
7103 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7104 const struct rte_flow_action_mark *mark =
7105 (const struct rte_flow_action_mark *)
7108 if (flow_dv_convert_action_mark(dev, mark,
7112 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7116 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7117 /* Legacy (non-extensive) MARK action. */
7118 tag_be = mlx5_flow_mark_set
7119 (((const struct rte_flow_action_mark *)
7120 (actions->conf))->id);
7121 if (!dev_flow->dv.tag_resource)
7122 if (flow_dv_tag_resource_register
7123 (dev, tag_be, dev_flow, error))
7125 dev_flow->dv.actions[actions_n++] =
7126 dev_flow->dv.tag_resource->action;
7128 case RTE_FLOW_ACTION_TYPE_SET_META:
7129 if (flow_dv_convert_action_set_meta
7130 (dev, mhdr_res, attr,
7131 (const struct rte_flow_action_set_meta *)
7132 actions->conf, error))
7134 action_flags |= MLX5_FLOW_ACTION_SET_META;
7136 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7137 if (flow_dv_convert_action_set_tag
7139 (const struct rte_flow_action_set_tag *)
7140 actions->conf, error))
7142 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7144 case RTE_FLOW_ACTION_TYPE_DROP:
7145 action_flags |= MLX5_FLOW_ACTION_DROP;
7147 case RTE_FLOW_ACTION_TYPE_QUEUE:
7148 assert(flow->rss.queue);
7149 queue = actions->conf;
7150 flow->rss.queue_num = 1;
7151 (*flow->rss.queue)[0] = queue->index;
7152 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7154 case RTE_FLOW_ACTION_TYPE_RSS:
7155 assert(flow->rss.queue);
7156 rss = actions->conf;
7157 if (flow->rss.queue)
7158 memcpy((*flow->rss.queue), rss->queue,
7159 rss->queue_num * sizeof(uint16_t));
7160 flow->rss.queue_num = rss->queue_num;
7161 /* NULL RSS key indicates default RSS key. */
7162 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7163 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7165 * rss->level and rss.types should be set in advance
7166 * when expanding items for RSS.
7168 action_flags |= MLX5_FLOW_ACTION_RSS;
7170 case RTE_FLOW_ACTION_TYPE_COUNT:
7171 if (!dev_conf->devx) {
7172 rte_errno = ENOTSUP;
7175 flow->counter = flow_dv_counter_alloc(dev,
7179 if (flow->counter == NULL)
7181 dev_flow->dv.actions[actions_n++] =
7182 flow->counter->action;
7183 action_flags |= MLX5_FLOW_ACTION_COUNT;
7186 if (rte_errno == ENOTSUP)
7187 return rte_flow_error_set
7189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7191 "count action not supported");
7193 return rte_flow_error_set
7195 RTE_FLOW_ERROR_TYPE_ACTION,
7197 "cannot create counter"
7200 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7201 dev_flow->dv.actions[actions_n++] =
7202 priv->sh->pop_vlan_action;
7203 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7205 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7206 flow_dev_get_vlan_info_from_items(items, &vlan);
7207 vlan.eth_proto = rte_be_to_cpu_16
7208 ((((const struct rte_flow_action_of_push_vlan *)
7209 actions->conf)->ethertype));
7210 found_action = mlx5_flow_find_action
7212 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7214 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7215 found_action = mlx5_flow_find_action
7217 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7219 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7220 if (flow_dv_create_action_push_vlan
7221 (dev, attr, &vlan, dev_flow, error))
7223 dev_flow->dv.actions[actions_n++] =
7224 dev_flow->dv.push_vlan_res->action;
7225 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7227 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7228 /* of_vlan_push action handled this action */
7229 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7231 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7232 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7234 flow_dev_get_vlan_info_from_items(items, &vlan);
7235 mlx5_update_vlan_vid_pcp(actions, &vlan);
7236 /* If no VLAN push - this is a modify header action */
7237 if (flow_dv_convert_action_modify_vlan_vid
7238 (mhdr_res, actions, error))
7240 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7242 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7243 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7244 if (flow_dv_create_action_l2_encap(dev, actions,
7249 dev_flow->dv.actions[actions_n++] =
7250 dev_flow->dv.encap_decap->verbs_action;
7251 action_flags |= actions->type ==
7252 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
7253 MLX5_FLOW_ACTION_VXLAN_ENCAP :
7254 MLX5_FLOW_ACTION_NVGRE_ENCAP;
7256 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7257 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7258 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7262 dev_flow->dv.actions[actions_n++] =
7263 dev_flow->dv.encap_decap->verbs_action;
7264 action_flags |= actions->type ==
7265 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7266 MLX5_FLOW_ACTION_VXLAN_DECAP :
7267 MLX5_FLOW_ACTION_NVGRE_DECAP;
7269 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7270 /* Handle encap with preceding decap. */
7271 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
7272 if (flow_dv_create_action_raw_encap
7273 (dev, actions, dev_flow, attr, error))
7275 dev_flow->dv.actions[actions_n++] =
7276 dev_flow->dv.encap_decap->verbs_action;
7278 /* Handle encap without preceding decap. */
7279 if (flow_dv_create_action_l2_encap
7280 (dev, actions, dev_flow, attr->transfer,
7283 dev_flow->dv.actions[actions_n++] =
7284 dev_flow->dv.encap_decap->verbs_action;
7286 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
7288 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7289 /* Check if this decap is followed by encap. */
7290 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
7291 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
7294 /* Handle decap only if it isn't followed by encap. */
7295 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7296 if (flow_dv_create_action_l2_decap
7297 (dev, dev_flow, attr->transfer, error))
7299 dev_flow->dv.actions[actions_n++] =
7300 dev_flow->dv.encap_decap->verbs_action;
7302 /* If decap is followed by encap, handle it at encap. */
7303 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
7305 case RTE_FLOW_ACTION_TYPE_JUMP:
7306 jump_data = action->conf;
7307 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7308 jump_data->group, &table,
7312 tbl = flow_dv_tbl_resource_get(dev, table,
7314 attr->transfer, error);
7316 return rte_flow_error_set
7318 RTE_FLOW_ERROR_TYPE_ACTION,
7320 "cannot create jump action.");
7321 if (flow_dv_jump_tbl_resource_register
7322 (dev, tbl, dev_flow, error)) {
7323 flow_dv_tbl_resource_release(dev, tbl);
7324 return rte_flow_error_set
7326 RTE_FLOW_ERROR_TYPE_ACTION,
7328 "cannot create jump action.");
7330 dev_flow->dv.actions[actions_n++] =
7331 dev_flow->dv.jump->action;
7332 action_flags |= MLX5_FLOW_ACTION_JUMP;
7334 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7335 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7336 if (flow_dv_convert_action_modify_mac
7337 (mhdr_res, actions, error))
7339 action_flags |= actions->type ==
7340 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7341 MLX5_FLOW_ACTION_SET_MAC_SRC :
7342 MLX5_FLOW_ACTION_SET_MAC_DST;
7344 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7345 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7346 if (flow_dv_convert_action_modify_ipv4
7347 (mhdr_res, actions, error))
7349 action_flags |= actions->type ==
7350 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7351 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7352 MLX5_FLOW_ACTION_SET_IPV4_DST;
7354 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7355 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7356 if (flow_dv_convert_action_modify_ipv6
7357 (mhdr_res, actions, error))
7359 action_flags |= actions->type ==
7360 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7361 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7362 MLX5_FLOW_ACTION_SET_IPV6_DST;
7364 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7365 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7366 if (flow_dv_convert_action_modify_tp
7367 (mhdr_res, actions, items,
7370 action_flags |= actions->type ==
7371 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7372 MLX5_FLOW_ACTION_SET_TP_SRC :
7373 MLX5_FLOW_ACTION_SET_TP_DST;
7375 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7376 if (flow_dv_convert_action_modify_dec_ttl
7377 (mhdr_res, items, &flow_attr, error))
7379 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7381 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7382 if (flow_dv_convert_action_modify_ttl
7383 (mhdr_res, actions, items,
7386 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7388 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7389 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7390 if (flow_dv_convert_action_modify_tcp_seq
7391 (mhdr_res, actions, error))
7393 action_flags |= actions->type ==
7394 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7395 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7396 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7399 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7400 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7401 if (flow_dv_convert_action_modify_tcp_ack
7402 (mhdr_res, actions, error))
7404 action_flags |= actions->type ==
7405 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7406 MLX5_FLOW_ACTION_INC_TCP_ACK :
7407 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7409 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7410 if (flow_dv_convert_action_set_reg
7411 (mhdr_res, actions, error))
7413 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7415 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7416 if (flow_dv_convert_action_copy_mreg
7417 (dev, mhdr_res, actions, error))
7419 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7421 case RTE_FLOW_ACTION_TYPE_METER:
7422 mtr = actions->conf;
7424 flow->meter = mlx5_flow_meter_attach(priv,
7428 return rte_flow_error_set(error,
7430 RTE_FLOW_ERROR_TYPE_ACTION,
7433 "or invalid parameters");
7435 /* Set the meter action. */
7436 dev_flow->dv.actions[actions_n++] =
7437 flow->meter->mfts->meter_action;
7438 action_flags |= MLX5_FLOW_ACTION_METER;
7440 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7441 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7444 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7446 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7447 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7450 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7452 case RTE_FLOW_ACTION_TYPE_END:
7454 if (mhdr_res->actions_num) {
7455 /* create modify action if needed. */
7456 if (flow_dv_modify_hdr_resource_register
7457 (dev, mhdr_res, dev_flow, error))
7459 dev_flow->dv.actions[modify_action_position] =
7460 dev_flow->dv.modify_hdr->verbs_action;
7466 if (mhdr_res->actions_num &&
7467 modify_action_position == UINT32_MAX)
7468 modify_action_position = actions_n++;
7470 dev_flow->dv.actions_n = actions_n;
7471 dev_flow->actions = action_flags;
7472 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7473 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7474 int item_type = items->type;
7476 switch (item_type) {
7477 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7478 flow_dv_translate_item_port_id(dev, match_mask,
7479 match_value, items);
7480 last_item = MLX5_FLOW_ITEM_PORT_ID;
7482 case RTE_FLOW_ITEM_TYPE_ETH:
7483 flow_dv_translate_item_eth(match_mask, match_value,
7485 matcher.priority = MLX5_PRIORITY_MAP_L2;
7486 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7487 MLX5_FLOW_LAYER_OUTER_L2;
7489 case RTE_FLOW_ITEM_TYPE_VLAN:
7490 flow_dv_translate_item_vlan(dev_flow,
7491 match_mask, match_value,
7493 matcher.priority = MLX5_PRIORITY_MAP_L2;
7494 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7495 MLX5_FLOW_LAYER_INNER_VLAN) :
7496 (MLX5_FLOW_LAYER_OUTER_L2 |
7497 MLX5_FLOW_LAYER_OUTER_VLAN);
7499 case RTE_FLOW_ITEM_TYPE_IPV4:
7500 mlx5_flow_tunnel_ip_check(items, next_protocol,
7501 &item_flags, &tunnel);
7502 flow_dv_translate_item_ipv4(match_mask, match_value,
7505 matcher.priority = MLX5_PRIORITY_MAP_L3;
7506 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7507 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7508 if (items->mask != NULL &&
7509 ((const struct rte_flow_item_ipv4 *)
7510 items->mask)->hdr.next_proto_id) {
7512 ((const struct rte_flow_item_ipv4 *)
7513 (items->spec))->hdr.next_proto_id;
7515 ((const struct rte_flow_item_ipv4 *)
7516 (items->mask))->hdr.next_proto_id;
7518 /* Reset for inner layer. */
7519 next_protocol = 0xff;
7522 case RTE_FLOW_ITEM_TYPE_IPV6:
7523 mlx5_flow_tunnel_ip_check(items, next_protocol,
7524 &item_flags, &tunnel);
7525 flow_dv_translate_item_ipv6(match_mask, match_value,
7528 matcher.priority = MLX5_PRIORITY_MAP_L3;
7529 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7530 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7531 if (items->mask != NULL &&
7532 ((const struct rte_flow_item_ipv6 *)
7533 items->mask)->hdr.proto) {
7535 ((const struct rte_flow_item_ipv6 *)
7536 items->spec)->hdr.proto;
7538 ((const struct rte_flow_item_ipv6 *)
7539 items->mask)->hdr.proto;
7541 /* Reset for inner layer. */
7542 next_protocol = 0xff;
7545 case RTE_FLOW_ITEM_TYPE_TCP:
7546 flow_dv_translate_item_tcp(match_mask, match_value,
7548 matcher.priority = MLX5_PRIORITY_MAP_L4;
7549 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7550 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7552 case RTE_FLOW_ITEM_TYPE_UDP:
7553 flow_dv_translate_item_udp(match_mask, match_value,
7555 matcher.priority = MLX5_PRIORITY_MAP_L4;
7556 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7557 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7559 case RTE_FLOW_ITEM_TYPE_GRE:
7560 flow_dv_translate_item_gre(match_mask, match_value,
7562 last_item = MLX5_FLOW_LAYER_GRE;
7564 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7565 flow_dv_translate_item_gre_key(match_mask,
7566 match_value, items);
7567 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7569 case RTE_FLOW_ITEM_TYPE_NVGRE:
7570 flow_dv_translate_item_nvgre(match_mask, match_value,
7572 last_item = MLX5_FLOW_LAYER_GRE;
7574 case RTE_FLOW_ITEM_TYPE_VXLAN:
7575 flow_dv_translate_item_vxlan(match_mask, match_value,
7577 last_item = MLX5_FLOW_LAYER_VXLAN;
7579 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7580 flow_dv_translate_item_vxlan(match_mask, match_value,
7582 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7584 case RTE_FLOW_ITEM_TYPE_GENEVE:
7585 flow_dv_translate_item_geneve(match_mask, match_value,
7587 last_item = MLX5_FLOW_LAYER_GENEVE;
7589 case RTE_FLOW_ITEM_TYPE_MPLS:
7590 flow_dv_translate_item_mpls(match_mask, match_value,
7591 items, last_item, tunnel);
7592 last_item = MLX5_FLOW_LAYER_MPLS;
7594 case RTE_FLOW_ITEM_TYPE_MARK:
7595 flow_dv_translate_item_mark(dev, match_mask,
7596 match_value, items);
7597 last_item = MLX5_FLOW_ITEM_MARK;
7599 case RTE_FLOW_ITEM_TYPE_META:
7600 flow_dv_translate_item_meta(dev, match_mask,
7601 match_value, attr, items);
7602 last_item = MLX5_FLOW_ITEM_METADATA;
7604 case RTE_FLOW_ITEM_TYPE_ICMP:
7605 flow_dv_translate_item_icmp(match_mask, match_value,
7607 last_item = MLX5_FLOW_LAYER_ICMP;
7609 case RTE_FLOW_ITEM_TYPE_ICMP6:
7610 flow_dv_translate_item_icmp6(match_mask, match_value,
7612 last_item = MLX5_FLOW_LAYER_ICMP6;
7614 case RTE_FLOW_ITEM_TYPE_TAG:
7615 flow_dv_translate_item_tag(dev, match_mask,
7616 match_value, items);
7617 last_item = MLX5_FLOW_ITEM_TAG;
7619 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7620 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7621 match_value, items);
7622 last_item = MLX5_FLOW_ITEM_TAG;
7624 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7625 flow_dv_translate_item_tx_queue(dev, match_mask,
7628 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7630 case RTE_FLOW_ITEM_TYPE_GTP:
7631 flow_dv_translate_item_gtp(match_mask, match_value,
7633 last_item = MLX5_FLOW_LAYER_GTP;
7638 item_flags |= last_item;
7641 * In case of ingress traffic when E-Switch mode is enabled,
7642 * we have two cases where we need to set the source port manually.
7643 * The first one, is in case of Nic steering rule, and the second is
7644 * E-Switch rule where no port_id item was found. In both cases
7645 * the source port is set according the current port in use.
7647 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
7648 (priv->representor || priv->master)) {
7649 if (flow_dv_translate_item_port_id(dev, match_mask,
7653 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
7654 dev_flow->dv.value.buf));
7655 dev_flow->layers = item_flags;
7656 if (action_flags & MLX5_FLOW_ACTION_RSS)
7657 flow_dv_hashfields_set(dev_flow);
7658 /* Register matcher. */
7659 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7661 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7663 /* reserved field no needs to be set to 0 here. */
7664 tbl_key.domain = attr->transfer;
7665 tbl_key.direction = attr->egress;
7666 tbl_key.table_id = dev_flow->group;
7667 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7673 * Apply the flow to the NIC, lock free,
7674 * (mutex should be acquired by caller).
7677 * Pointer to the Ethernet device structure.
7678 * @param[in, out] flow
7679 * Pointer to flow structure.
7681 * Pointer to error structure.
7684 * 0 on success, a negative errno value otherwise and rte_errno is set.
7687 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7688 struct rte_flow_error *error)
7690 struct mlx5_flow_dv *dv;
7691 struct mlx5_flow *dev_flow;
7692 struct mlx5_priv *priv = dev->data->dev_private;
7696 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7699 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7700 if (dev_flow->transfer) {
7701 dv->actions[n++] = priv->sh->esw_drop_action;
7703 dv->hrxq = mlx5_hrxq_drop_new(dev);
7707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7709 "cannot get drop hash queue");
7712 dv->actions[n++] = dv->hrxq->action;
7714 } else if (dev_flow->actions &
7715 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7716 struct mlx5_hrxq *hrxq;
7718 assert(flow->rss.queue);
7719 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7720 MLX5_RSS_HASH_KEY_LEN,
7721 dev_flow->hash_fields,
7723 flow->rss.queue_num);
7725 hrxq = mlx5_hrxq_new
7726 (dev, flow->rss.key,
7727 MLX5_RSS_HASH_KEY_LEN,
7728 dev_flow->hash_fields,
7730 flow->rss.queue_num,
7731 !!(dev_flow->layers &
7732 MLX5_FLOW_LAYER_TUNNEL));
7737 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7738 "cannot get hash queue");
7742 dv->actions[n++] = dv->hrxq->action;
7745 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7746 (void *)&dv->value, n,
7749 rte_flow_error_set(error, errno,
7750 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7752 "hardware refuses to create flow");
7755 if (priv->vmwa_context &&
7756 dev_flow->dv.vf_vlan.tag &&
7757 !dev_flow->dv.vf_vlan.created) {
7759 * The rule contains the VLAN pattern.
7760 * For VF we are going to create VLAN
7761 * interface to make hypervisor set correct
7762 * e-Switch vport context.
7764 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7769 err = rte_errno; /* Save rte_errno before cleanup. */
7770 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7771 struct mlx5_flow_dv *dv = &dev_flow->dv;
7773 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7774 mlx5_hrxq_drop_release(dev);
7776 mlx5_hrxq_release(dev, dv->hrxq);
7779 if (dev_flow->dv.vf_vlan.tag &&
7780 dev_flow->dv.vf_vlan.created)
7781 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7783 rte_errno = err; /* Restore rte_errno. */
7788 * Release the flow matcher.
7791 * Pointer to Ethernet device.
7793 * Pointer to mlx5_flow.
7796 * 1 while a reference on it exists, 0 when freed.
7799 flow_dv_matcher_release(struct rte_eth_dev *dev,
7800 struct mlx5_flow *flow)
7802 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7804 assert(matcher->matcher_object);
7805 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7806 dev->data->port_id, (void *)matcher,
7807 rte_atomic32_read(&matcher->refcnt));
7808 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7809 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7810 (matcher->matcher_object));
7811 LIST_REMOVE(matcher, next);
7812 /* table ref-- in release interface. */
7813 flow_dv_tbl_resource_release(dev, matcher->tbl);
7815 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7816 dev->data->port_id, (void *)matcher);
7823 * Release an encap/decap resource.
7826 * Pointer to mlx5_flow.
7829 * 1 while a reference on it exists, 0 when freed.
7832 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7834 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7835 flow->dv.encap_decap;
7837 assert(cache_resource->verbs_action);
7838 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7839 (void *)cache_resource,
7840 rte_atomic32_read(&cache_resource->refcnt));
7841 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7842 claim_zero(mlx5_glue->destroy_flow_action
7843 (cache_resource->verbs_action));
7844 LIST_REMOVE(cache_resource, next);
7845 rte_free(cache_resource);
7846 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7847 (void *)cache_resource);
7854 * Release an jump to table action resource.
7857 * Pointer to Ethernet device.
7859 * Pointer to mlx5_flow.
7862 * 1 while a reference on it exists, 0 when freed.
7865 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7866 struct mlx5_flow *flow)
7868 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7869 struct mlx5_flow_tbl_data_entry *tbl_data =
7870 container_of(cache_resource,
7871 struct mlx5_flow_tbl_data_entry, jump);
7873 assert(cache_resource->action);
7874 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7875 (void *)cache_resource,
7876 rte_atomic32_read(&cache_resource->refcnt));
7877 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7878 claim_zero(mlx5_glue->destroy_flow_action
7879 (cache_resource->action));
7880 /* jump action memory free is inside the table release. */
7881 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7882 DRV_LOG(DEBUG, "jump table resource %p: removed",
7883 (void *)cache_resource);
7890 * Release a modify-header resource.
7893 * Pointer to mlx5_flow.
7896 * 1 while a reference on it exists, 0 when freed.
7899 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7901 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7902 flow->dv.modify_hdr;
7904 assert(cache_resource->verbs_action);
7905 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7906 (void *)cache_resource,
7907 rte_atomic32_read(&cache_resource->refcnt));
7908 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7909 claim_zero(mlx5_glue->destroy_flow_action
7910 (cache_resource->verbs_action));
7911 LIST_REMOVE(cache_resource, next);
7912 rte_free(cache_resource);
7913 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7914 (void *)cache_resource);
7921 * Release port ID action resource.
7924 * Pointer to mlx5_flow.
7927 * 1 while a reference on it exists, 0 when freed.
7930 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
7932 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
7933 flow->dv.port_id_action;
7935 assert(cache_resource->action);
7936 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
7937 (void *)cache_resource,
7938 rte_atomic32_read(&cache_resource->refcnt));
7939 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7940 claim_zero(mlx5_glue->destroy_flow_action
7941 (cache_resource->action));
7942 LIST_REMOVE(cache_resource, next);
7943 rte_free(cache_resource);
7944 DRV_LOG(DEBUG, "port id action resource %p: removed",
7945 (void *)cache_resource);
7952 * Release push vlan action resource.
7955 * Pointer to mlx5_flow.
7958 * 1 while a reference on it exists, 0 when freed.
7961 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
7963 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
7964 flow->dv.push_vlan_res;
7966 assert(cache_resource->action);
7967 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
7968 (void *)cache_resource,
7969 rte_atomic32_read(&cache_resource->refcnt));
7970 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7971 claim_zero(mlx5_glue->destroy_flow_action
7972 (cache_resource->action));
7973 LIST_REMOVE(cache_resource, next);
7974 rte_free(cache_resource);
7975 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
7976 (void *)cache_resource);
7983 * Remove the flow from the NIC but keeps it in memory.
7984 * Lock free, (mutex should be acquired by caller).
7987 * Pointer to Ethernet device.
7988 * @param[in, out] flow
7989 * Pointer to flow structure.
7992 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7994 struct mlx5_flow_dv *dv;
7995 struct mlx5_flow *dev_flow;
7999 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8002 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8006 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8007 mlx5_hrxq_drop_release(dev);
8009 mlx5_hrxq_release(dev, dv->hrxq);
8012 if (dev_flow->dv.vf_vlan.tag &&
8013 dev_flow->dv.vf_vlan.created)
8014 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8019 * Remove the flow from the NIC and the memory.
8020 * Lock free, (mutex should be acquired by caller).
8023 * Pointer to the Ethernet device structure.
8024 * @param[in, out] flow
8025 * Pointer to flow structure.
8028 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8030 struct mlx5_flow *dev_flow;
8034 __flow_dv_remove(dev, flow);
8035 if (flow->counter) {
8036 flow_dv_counter_release(dev, flow->counter);
8037 flow->counter = NULL;
8040 mlx5_flow_meter_detach(flow->meter);
8043 while (!LIST_EMPTY(&flow->dev_flows)) {
8044 dev_flow = LIST_FIRST(&flow->dev_flows);
8045 LIST_REMOVE(dev_flow, next);
8046 if (dev_flow->dv.matcher)
8047 flow_dv_matcher_release(dev, dev_flow);
8048 if (dev_flow->dv.encap_decap)
8049 flow_dv_encap_decap_resource_release(dev_flow);
8050 if (dev_flow->dv.modify_hdr)
8051 flow_dv_modify_hdr_resource_release(dev_flow);
8052 if (dev_flow->dv.jump)
8053 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8054 if (dev_flow->dv.port_id_action)
8055 flow_dv_port_id_action_resource_release(dev_flow);
8056 if (dev_flow->dv.push_vlan_res)
8057 flow_dv_push_vlan_action_resource_release(dev_flow);
8058 if (dev_flow->dv.tag_resource)
8059 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8065 * Query a dv flow rule for its statistics via devx.
8068 * Pointer to Ethernet device.
8070 * Pointer to the sub flow.
8072 * data retrieved by the query.
8074 * Perform verbose error reporting if not NULL.
8077 * 0 on success, a negative errno value otherwise and rte_errno is set.
8080 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8081 void *data, struct rte_flow_error *error)
8083 struct mlx5_priv *priv = dev->data->dev_private;
8084 struct rte_flow_query_count *qc = data;
8086 if (!priv->config.devx)
8087 return rte_flow_error_set(error, ENOTSUP,
8088 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8090 "counters are not supported");
8091 if (flow->counter) {
8092 uint64_t pkts, bytes;
8093 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8097 return rte_flow_error_set(error, -err,
8098 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8099 NULL, "cannot read counters");
8102 qc->hits = pkts - flow->counter->hits;
8103 qc->bytes = bytes - flow->counter->bytes;
8105 flow->counter->hits = pkts;
8106 flow->counter->bytes = bytes;
8110 return rte_flow_error_set(error, EINVAL,
8111 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8113 "counters are not available");
8119 * @see rte_flow_query()
8123 flow_dv_query(struct rte_eth_dev *dev,
8124 struct rte_flow *flow __rte_unused,
8125 const struct rte_flow_action *actions __rte_unused,
8126 void *data __rte_unused,
8127 struct rte_flow_error *error __rte_unused)
8131 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8132 switch (actions->type) {
8133 case RTE_FLOW_ACTION_TYPE_VOID:
8135 case RTE_FLOW_ACTION_TYPE_COUNT:
8136 ret = flow_dv_query_count(dev, flow, data, error);
8139 return rte_flow_error_set(error, ENOTSUP,
8140 RTE_FLOW_ERROR_TYPE_ACTION,
8142 "action not supported");
8149 * Destroy the meter table set.
8150 * Lock free, (mutex should be acquired by caller).
8153 * Pointer to Ethernet device.
8155 * Pointer to the meter table set.
8161 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8162 struct mlx5_meter_domains_infos *tbl)
8164 struct mlx5_priv *priv = dev->data->dev_private;
8165 struct mlx5_meter_domains_infos *mtd =
8166 (struct mlx5_meter_domains_infos *)tbl;
8168 if (!mtd || !priv->config.dv_flow_en)
8170 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8171 claim_zero(mlx5_glue->dv_destroy_flow
8172 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8173 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8174 claim_zero(mlx5_glue->dv_destroy_flow
8175 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8176 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8177 claim_zero(mlx5_glue->dv_destroy_flow
8178 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8179 if (mtd->egress.color_matcher)
8180 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8181 (mtd->egress.color_matcher));
8182 if (mtd->egress.any_matcher)
8183 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8184 (mtd->egress.any_matcher));
8185 if (mtd->egress.tbl)
8186 claim_zero(flow_dv_tbl_resource_release(dev,
8188 if (mtd->ingress.color_matcher)
8189 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8190 (mtd->ingress.color_matcher));
8191 if (mtd->ingress.any_matcher)
8192 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8193 (mtd->ingress.any_matcher));
8194 if (mtd->ingress.tbl)
8195 claim_zero(flow_dv_tbl_resource_release(dev,
8197 if (mtd->transfer.color_matcher)
8198 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8199 (mtd->transfer.color_matcher));
8200 if (mtd->transfer.any_matcher)
8201 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8202 (mtd->transfer.any_matcher));
8203 if (mtd->transfer.tbl)
8204 claim_zero(flow_dv_tbl_resource_release(dev,
8205 mtd->transfer.tbl));
8207 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8212 /* Number of meter flow actions, count and jump or count and drop. */
8213 #define METER_ACTIONS 2
8216 * Create specify domain meter table and suffix table.
8219 * Pointer to Ethernet device.
8220 * @param[in,out] mtb
8221 * Pointer to DV meter table set.
8224 * @param[in] transfer
8226 * @param[in] color_reg_c_idx
8227 * Reg C index for color match.
8230 * 0 on success, -1 otherwise and rte_errno is set.
8233 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8234 struct mlx5_meter_domains_infos *mtb,
8235 uint8_t egress, uint8_t transfer,
8236 uint32_t color_reg_c_idx)
8238 struct mlx5_priv *priv = dev->data->dev_private;
8239 struct mlx5_ibv_shared *sh = priv->sh;
8240 struct mlx5_flow_dv_match_params mask = {
8241 .size = sizeof(mask.buf),
8243 struct mlx5_flow_dv_match_params value = {
8244 .size = sizeof(value.buf),
8246 struct mlx5dv_flow_matcher_attr dv_attr = {
8247 .type = IBV_FLOW_ATTR_NORMAL,
8249 .match_criteria_enable = 0,
8250 .match_mask = (void *)&mask,
8252 void *actions[METER_ACTIONS];
8253 struct mlx5_flow_tbl_resource **sfx_tbl;
8254 struct mlx5_meter_domain_info *dtb;
8255 struct rte_flow_error error;
8259 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8260 dtb = &mtb->transfer;
8261 } else if (egress) {
8262 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8265 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8266 dtb = &mtb->ingress;
8268 /* If the suffix table in missing, create it. */
8270 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8271 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8272 egress, transfer, &error);
8274 DRV_LOG(ERR, "Failed to create meter suffix table.");
8278 /* Create the meter table with METER level. */
8279 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8280 egress, transfer, &error);
8282 DRV_LOG(ERR, "Failed to create meter policer table.");
8285 /* Create matchers, Any and Color. */
8286 dv_attr.priority = 3;
8287 dv_attr.match_criteria_enable = 0;
8288 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8291 if (!dtb->any_matcher) {
8292 DRV_LOG(ERR, "Failed to create meter"
8293 " policer default matcher.");
8296 dv_attr.priority = 0;
8297 dv_attr.match_criteria_enable =
8298 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8299 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8300 rte_col_2_mlx5_col(RTE_COLORS), UINT32_MAX);
8301 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8304 if (!dtb->color_matcher) {
8305 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8308 if (mtb->count_actns[RTE_MTR_DROPPED])
8309 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8310 actions[i++] = mtb->drop_actn;
8311 /* Default rule: lowest priority, match any, actions: drop. */
8312 dtb->policer_rules[RTE_MTR_DROPPED] =
8313 mlx5_glue->dv_create_flow(dtb->any_matcher,
8314 (void *)&value, i, actions);
8315 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8316 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8325 * Create the needed meter and suffix tables.
8326 * Lock free, (mutex should be acquired by caller).
8329 * Pointer to Ethernet device.
8331 * Pointer to the flow meter.
8334 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8336 static struct mlx5_meter_domains_infos *
8337 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8338 const struct mlx5_flow_meter *fm)
8340 struct mlx5_priv *priv = dev->data->dev_private;
8341 struct mlx5_meter_domains_infos *mtb;
8345 if (!priv->mtr_en) {
8346 rte_errno = ENOTSUP;
8349 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8351 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8354 /* Create meter count actions */
8355 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8356 if (!fm->policer_stats.cnt[i])
8358 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8360 /* Create drop action. */
8361 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8362 if (!mtb->drop_actn) {
8363 DRV_LOG(ERR, "Failed to create drop action.");
8366 /* Egress meter table. */
8367 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8369 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8372 /* Ingress meter table. */
8373 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8375 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8378 /* FDB meter table. */
8379 if (priv->config.dv_esw_en) {
8380 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8381 priv->mtr_color_reg);
8383 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8389 flow_dv_destroy_mtr_tbl(dev, mtb);
8394 * Destroy domain policer rule.
8397 * Pointer to domain table.
8400 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8404 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8405 if (dt->policer_rules[i]) {
8406 claim_zero(mlx5_glue->dv_destroy_flow
8407 (dt->policer_rules[i]));
8408 dt->policer_rules[i] = NULL;
8411 if (dt->jump_actn) {
8412 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8413 dt->jump_actn = NULL;
8418 * Destroy policer rules.
8421 * Pointer to Ethernet device.
8423 * Pointer to flow meter structure.
8425 * Pointer to flow attributes.
8431 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8432 const struct mlx5_flow_meter *fm,
8433 const struct rte_flow_attr *attr)
8435 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8440 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8442 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8444 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8449 * Create specify domain meter policer rule.
8452 * Pointer to flow meter structure.
8454 * Pointer to DV meter table set.
8456 * Pointer to suffix table.
8457 * @param[in] mtr_reg_c
8458 * Color match REG_C.
8461 * 0 on success, -1 otherwise.
8464 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8465 struct mlx5_meter_domain_info *dtb,
8466 struct mlx5_flow_tbl_resource *sfx_tb,
8469 struct mlx5_flow_dv_match_params matcher = {
8470 .size = sizeof(matcher.buf),
8472 struct mlx5_flow_dv_match_params value = {
8473 .size = sizeof(value.buf),
8475 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8476 void *actions[METER_ACTIONS];
8479 /* Create jump action. */
8482 if (!dtb->jump_actn)
8484 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8486 if (!dtb->jump_actn) {
8487 DRV_LOG(ERR, "Failed to create policer jump action.");
8490 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8493 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8494 rte_col_2_mlx5_col(i), UINT32_MAX);
8495 if (mtb->count_actns[i])
8496 actions[j++] = mtb->count_actns[i];
8497 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8498 actions[j++] = mtb->drop_actn;
8500 actions[j++] = dtb->jump_actn;
8501 dtb->policer_rules[i] =
8502 mlx5_glue->dv_create_flow(dtb->color_matcher,
8505 if (!dtb->policer_rules[i]) {
8506 DRV_LOG(ERR, "Failed to create policer rule.");
8517 * Create policer rules.
8520 * Pointer to Ethernet device.
8522 * Pointer to flow meter structure.
8524 * Pointer to flow attributes.
8527 * 0 on success, -1 otherwise.
8530 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8531 struct mlx5_flow_meter *fm,
8532 const struct rte_flow_attr *attr)
8534 struct mlx5_priv *priv = dev->data->dev_private;
8535 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8539 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8540 priv->sh->tx_mtr_sfx_tbl,
8541 priv->mtr_color_reg);
8543 DRV_LOG(ERR, "Failed to create egress policer.");
8547 if (attr->ingress) {
8548 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8549 priv->sh->rx_mtr_sfx_tbl,
8550 priv->mtr_color_reg);
8552 DRV_LOG(ERR, "Failed to create ingress policer.");
8556 if (attr->transfer) {
8557 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8558 priv->sh->fdb_mtr_sfx_tbl,
8559 priv->mtr_color_reg);
8561 DRV_LOG(ERR, "Failed to create transfer policer.");
8567 flow_dv_destroy_policer_rules(dev, fm, attr);
8572 * Query a devx counter.
8575 * Pointer to the Ethernet device structure.
8577 * Pointer to the flow counter.
8579 * Set to clear the counter statistics.
8581 * The statistics value of packets.
8583 * The statistics value of bytes.
8586 * 0 on success, otherwise return -1.
8589 flow_dv_counter_query(struct rte_eth_dev *dev,
8590 struct mlx5_flow_counter *cnt, bool clear,
8591 uint64_t *pkts, uint64_t *bytes)
8593 struct mlx5_priv *priv = dev->data->dev_private;
8594 uint64_t inn_pkts, inn_bytes;
8597 if (!priv->config.devx)
8599 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8602 *pkts = inn_pkts - cnt->hits;
8603 *bytes = inn_bytes - cnt->bytes;
8605 cnt->hits = inn_pkts;
8606 cnt->bytes = inn_bytes;
8612 * Mutex-protected thunk to lock-free __flow_dv_translate().
8615 flow_dv_translate(struct rte_eth_dev *dev,
8616 struct mlx5_flow *dev_flow,
8617 const struct rte_flow_attr *attr,
8618 const struct rte_flow_item items[],
8619 const struct rte_flow_action actions[],
8620 struct rte_flow_error *error)
8624 flow_dv_shared_lock(dev);
8625 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8626 flow_dv_shared_unlock(dev);
8631 * Mutex-protected thunk to lock-free __flow_dv_apply().
8634 flow_dv_apply(struct rte_eth_dev *dev,
8635 struct rte_flow *flow,
8636 struct rte_flow_error *error)
8640 flow_dv_shared_lock(dev);
8641 ret = __flow_dv_apply(dev, flow, error);
8642 flow_dv_shared_unlock(dev);
8647 * Mutex-protected thunk to lock-free __flow_dv_remove().
8650 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8652 flow_dv_shared_lock(dev);
8653 __flow_dv_remove(dev, flow);
8654 flow_dv_shared_unlock(dev);
8658 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8661 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8663 flow_dv_shared_lock(dev);
8664 __flow_dv_destroy(dev, flow);
8665 flow_dv_shared_unlock(dev);
8669 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8671 static struct mlx5_flow_counter *
8672 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8674 struct mlx5_flow_counter *cnt;
8676 flow_dv_shared_lock(dev);
8677 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8678 flow_dv_shared_unlock(dev);
8683 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8686 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8688 flow_dv_shared_lock(dev);
8689 flow_dv_counter_release(dev, cnt);
8690 flow_dv_shared_unlock(dev);
8693 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8694 .validate = flow_dv_validate,
8695 .prepare = flow_dv_prepare,
8696 .translate = flow_dv_translate,
8697 .apply = flow_dv_apply,
8698 .remove = flow_dv_remove,
8699 .destroy = flow_dv_destroy,
8700 .query = flow_dv_query,
8701 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8702 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8703 .create_policer_rules = flow_dv_create_policer_rules,
8704 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8705 .counter_alloc = flow_dv_counter_allocate,
8706 .counter_free = flow_dv_counter_free,
8707 .counter_query = flow_dv_counter_query,
8710 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */