1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79 uint32_t encap_decap_idx);
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
92 * Initialize flow attributes structure according to flow items' types.
94 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
95 * mode. For tunnel mode, the items to be modified are the outermost ones.
98 * Pointer to item specification.
100 * Pointer to flow attributes structure.
101 * @param[in] dev_flow
102 * Pointer to the sub flow.
103 * @param[in] tunnel_decap
104 * Whether action is after tunnel decapsulation.
107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
108 struct mlx5_flow *dev_flow, bool tunnel_decap)
110 uint64_t layers = dev_flow->handle->layers;
113 * If layers is already initialized, it means this dev_flow is the
114 * suffix flow, the layers flags is set by the prefix flow. Need to
115 * use the layer flags from prefix flow as the suffix flow may not
116 * have the user defined items as the flow is split.
119 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
123 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
125 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
130 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
131 uint8_t next_protocol = 0xff;
132 switch (item->type) {
133 case RTE_FLOW_ITEM_TYPE_GRE:
134 case RTE_FLOW_ITEM_TYPE_NVGRE:
135 case RTE_FLOW_ITEM_TYPE_VXLAN:
136 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
137 case RTE_FLOW_ITEM_TYPE_GENEVE:
138 case RTE_FLOW_ITEM_TYPE_MPLS:
142 case RTE_FLOW_ITEM_TYPE_IPV4:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv4 *)
147 item->mask)->hdr.next_proto_id)
149 ((const struct rte_flow_item_ipv4 *)
150 (item->spec))->hdr.next_proto_id &
151 ((const struct rte_flow_item_ipv4 *)
152 (item->mask))->hdr.next_proto_id;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_IPV6:
160 if (item->mask != NULL &&
161 ((const struct rte_flow_item_ipv6 *)
162 item->mask)->hdr.proto)
164 ((const struct rte_flow_item_ipv6 *)
165 (item->spec))->hdr.proto &
166 ((const struct rte_flow_item_ipv6 *)
167 (item->mask))->hdr.proto;
168 if ((next_protocol == IPPROTO_IPIP ||
169 next_protocol == IPPROTO_IPV6) && tunnel_decap)
172 case RTE_FLOW_ITEM_TYPE_UDP:
176 case RTE_FLOW_ITEM_TYPE_TCP:
188 * Convert rte_mtr_color to mlx5 color.
197 rte_col_2_mlx5_col(enum rte_color rcol)
200 case RTE_COLOR_GREEN:
201 return MLX5_FLOW_COLOR_GREEN;
202 case RTE_COLOR_YELLOW:
203 return MLX5_FLOW_COLOR_YELLOW;
205 return MLX5_FLOW_COLOR_RED;
209 return MLX5_FLOW_COLOR_UNDEFINED;
212 struct field_modify_info {
213 uint32_t size; /* Size of field in protocol header, in bytes. */
214 uint32_t offset; /* Offset of field in protocol header, in bytes. */
215 enum mlx5_modification_field id;
218 struct field_modify_info modify_eth[] = {
219 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
220 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
221 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
222 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
226 struct field_modify_info modify_vlan_out_first_vid[] = {
227 /* Size in bits !!! */
228 {12, 0, MLX5_MODI_OUT_FIRST_VID},
232 struct field_modify_info modify_ipv4[] = {
233 {1, 1, MLX5_MODI_OUT_IP_DSCP},
234 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
235 {4, 12, MLX5_MODI_OUT_SIPV4},
236 {4, 16, MLX5_MODI_OUT_DIPV4},
240 struct field_modify_info modify_ipv6[] = {
241 {1, 0, MLX5_MODI_OUT_IP_DSCP},
242 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
243 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
244 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
245 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
246 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
247 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
248 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
249 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
250 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
254 struct field_modify_info modify_udp[] = {
255 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
256 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
260 struct field_modify_info modify_tcp[] = {
261 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
262 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
263 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
264 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
270 uint8_t next_protocol, uint64_t *item_flags,
273 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
274 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
275 if (next_protocol == IPPROTO_IPIP) {
276 *item_flags |= MLX5_FLOW_LAYER_IPIP;
279 if (next_protocol == IPPROTO_IPV6) {
280 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
285 /* Update VLAN's VID/PCP based on input rte_flow_action.
288 * Pointer to struct rte_flow_action.
290 * Pointer to struct rte_vlan_hdr.
293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
294 struct rte_vlan_hdr *vlan)
297 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
299 ((const struct rte_flow_action_of_set_vlan_pcp *)
300 action->conf)->vlan_pcp;
301 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
302 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
303 vlan->vlan_tci |= vlan_tci;
304 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
305 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
306 vlan->vlan_tci |= rte_be_to_cpu_16
307 (((const struct rte_flow_action_of_set_vlan_vid *)
308 action->conf)->vlan_vid);
313 * Fetch 1, 2, 3 or 4 byte field from the byte array
314 * and return as unsigned integer in host-endian format.
317 * Pointer to data array.
319 * Size of field to extract.
322 * converted field in host endian format.
324 static inline uint32_t
325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
334 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
337 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = (ret << 8) | *(data + sizeof(uint16_t));
341 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
352 * Convert modify-header action to DV specification.
354 * Data length of each action is determined by provided field description
355 * and the item mask. Data bit offset and width of each action is determined
356 * by provided item mask.
359 * Pointer to item specification.
361 * Pointer to field modification information.
362 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
363 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
366 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
367 * Negative offset value sets the same offset as source offset.
368 * size field is ignored, value is taken from source field.
369 * @param[in,out] resource
370 * Pointer to the modify-header resource.
372 * Type of modification.
374 * Pointer to the error structure.
377 * 0 on success, a negative errno value otherwise and rte_errno is set.
380 flow_dv_convert_modify_action(struct rte_flow_item *item,
381 struct field_modify_info *field,
382 struct field_modify_info *dcopy,
383 struct mlx5_flow_dv_modify_hdr_resource *resource,
384 uint32_t type, struct rte_flow_error *error)
386 uint32_t i = resource->actions_num;
387 struct mlx5_modification_cmd *actions = resource->actions;
390 * The item and mask are provided in big-endian format.
391 * The fields should be presented as in big-endian format either.
392 * Mask must be always present, it defines the actual field width.
394 MLX5_ASSERT(item->mask);
395 MLX5_ASSERT(field->size);
402 if (i >= MLX5_MAX_MODIFY_NUM)
403 return rte_flow_error_set(error, EINVAL,
404 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
405 "too many items to modify");
406 /* Fetch variable byte size mask from the array. */
407 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
408 field->offset, field->size);
413 /* Deduce actual data width in bits from mask value. */
414 off_b = rte_bsf32(mask);
415 size_b = sizeof(uint32_t) * CHAR_BIT -
416 off_b - __builtin_clz(mask);
418 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
419 actions[i] = (struct mlx5_modification_cmd) {
425 /* Convert entire record to expected big-endian format. */
426 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
427 if (type == MLX5_MODIFICATION_TYPE_COPY) {
429 actions[i].dst_field = dcopy->id;
430 actions[i].dst_offset =
431 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
432 /* Convert entire record to big-endian format. */
433 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
435 MLX5_ASSERT(item->spec);
436 data = flow_dv_fetch_field((const uint8_t *)item->spec +
437 field->offset, field->size);
438 /* Shift out the trailing masked bits from data. */
439 data = (data & mask) >> off_b;
440 actions[i].data1 = rte_cpu_to_be_32(data);
444 } while (field->size);
445 if (resource->actions_num == i)
446 return rte_flow_error_set(error, EINVAL,
447 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
448 "invalid modification flow item");
449 resource->actions_num = i;
454 * Convert modify-header set IPv4 address action to DV specification.
456 * @param[in,out] resource
457 * Pointer to the modify-header resource.
459 * Pointer to action specification.
461 * Pointer to the error structure.
464 * 0 on success, a negative errno value otherwise and rte_errno is set.
467 flow_dv_convert_action_modify_ipv4
468 (struct mlx5_flow_dv_modify_hdr_resource *resource,
469 const struct rte_flow_action *action,
470 struct rte_flow_error *error)
472 const struct rte_flow_action_set_ipv4 *conf =
473 (const struct rte_flow_action_set_ipv4 *)(action->conf);
474 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
475 struct rte_flow_item_ipv4 ipv4;
476 struct rte_flow_item_ipv4 ipv4_mask;
478 memset(&ipv4, 0, sizeof(ipv4));
479 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
480 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
481 ipv4.hdr.src_addr = conf->ipv4_addr;
482 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
484 ipv4.hdr.dst_addr = conf->ipv4_addr;
485 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
488 item.mask = &ipv4_mask;
489 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
490 MLX5_MODIFICATION_TYPE_SET, error);
494 * Convert modify-header set IPv6 address action to DV specification.
496 * @param[in,out] resource
497 * Pointer to the modify-header resource.
499 * Pointer to action specification.
501 * Pointer to the error structure.
504 * 0 on success, a negative errno value otherwise and rte_errno is set.
507 flow_dv_convert_action_modify_ipv6
508 (struct mlx5_flow_dv_modify_hdr_resource *resource,
509 const struct rte_flow_action *action,
510 struct rte_flow_error *error)
512 const struct rte_flow_action_set_ipv6 *conf =
513 (const struct rte_flow_action_set_ipv6 *)(action->conf);
514 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
515 struct rte_flow_item_ipv6 ipv6;
516 struct rte_flow_item_ipv6 ipv6_mask;
518 memset(&ipv6, 0, sizeof(ipv6));
519 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
520 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
521 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
522 sizeof(ipv6.hdr.src_addr));
523 memcpy(&ipv6_mask.hdr.src_addr,
524 &rte_flow_item_ipv6_mask.hdr.src_addr,
525 sizeof(ipv6.hdr.src_addr));
527 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
528 sizeof(ipv6.hdr.dst_addr));
529 memcpy(&ipv6_mask.hdr.dst_addr,
530 &rte_flow_item_ipv6_mask.hdr.dst_addr,
531 sizeof(ipv6.hdr.dst_addr));
534 item.mask = &ipv6_mask;
535 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
536 MLX5_MODIFICATION_TYPE_SET, error);
540 * Convert modify-header set MAC address action to DV specification.
542 * @param[in,out] resource
543 * Pointer to the modify-header resource.
545 * Pointer to action specification.
547 * Pointer to the error structure.
550 * 0 on success, a negative errno value otherwise and rte_errno is set.
553 flow_dv_convert_action_modify_mac
554 (struct mlx5_flow_dv_modify_hdr_resource *resource,
555 const struct rte_flow_action *action,
556 struct rte_flow_error *error)
558 const struct rte_flow_action_set_mac *conf =
559 (const struct rte_flow_action_set_mac *)(action->conf);
560 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
561 struct rte_flow_item_eth eth;
562 struct rte_flow_item_eth eth_mask;
564 memset(ð, 0, sizeof(eth));
565 memset(ð_mask, 0, sizeof(eth_mask));
566 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
567 memcpy(ð.src.addr_bytes, &conf->mac_addr,
568 sizeof(eth.src.addr_bytes));
569 memcpy(ð_mask.src.addr_bytes,
570 &rte_flow_item_eth_mask.src.addr_bytes,
571 sizeof(eth_mask.src.addr_bytes));
573 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
574 sizeof(eth.dst.addr_bytes));
575 memcpy(ð_mask.dst.addr_bytes,
576 &rte_flow_item_eth_mask.dst.addr_bytes,
577 sizeof(eth_mask.dst.addr_bytes));
580 item.mask = ð_mask;
581 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
582 MLX5_MODIFICATION_TYPE_SET, error);
586 * Convert modify-header set VLAN VID action to DV specification.
588 * @param[in,out] resource
589 * Pointer to the modify-header resource.
591 * Pointer to action specification.
593 * Pointer to the error structure.
596 * 0 on success, a negative errno value otherwise and rte_errno is set.
599 flow_dv_convert_action_modify_vlan_vid
600 (struct mlx5_flow_dv_modify_hdr_resource *resource,
601 const struct rte_flow_action *action,
602 struct rte_flow_error *error)
604 const struct rte_flow_action_of_set_vlan_vid *conf =
605 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
606 int i = resource->actions_num;
607 struct mlx5_modification_cmd *actions = resource->actions;
608 struct field_modify_info *field = modify_vlan_out_first_vid;
610 if (i >= MLX5_MAX_MODIFY_NUM)
611 return rte_flow_error_set(error, EINVAL,
612 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
613 "too many items to modify");
614 actions[i] = (struct mlx5_modification_cmd) {
615 .action_type = MLX5_MODIFICATION_TYPE_SET,
617 .length = field->size,
618 .offset = field->offset,
620 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
621 actions[i].data1 = conf->vlan_vid;
622 actions[i].data1 = actions[i].data1 << 16;
623 resource->actions_num = ++i;
628 * Convert modify-header set TP action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
638 * @param[in] dev_flow
639 * Pointer to the sub flow.
640 * @param[in] tunnel_decap
641 * Whether action is after tunnel decapsulation.
643 * Pointer to the error structure.
646 * 0 on success, a negative errno value otherwise and rte_errno is set.
649 flow_dv_convert_action_modify_tp
650 (struct mlx5_flow_dv_modify_hdr_resource *resource,
651 const struct rte_flow_action *action,
652 const struct rte_flow_item *items,
653 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
654 bool tunnel_decap, struct rte_flow_error *error)
656 const struct rte_flow_action_set_tp *conf =
657 (const struct rte_flow_action_set_tp *)(action->conf);
658 struct rte_flow_item item;
659 struct rte_flow_item_udp udp;
660 struct rte_flow_item_udp udp_mask;
661 struct rte_flow_item_tcp tcp;
662 struct rte_flow_item_tcp tcp_mask;
663 struct field_modify_info *field;
666 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
668 memset(&udp, 0, sizeof(udp));
669 memset(&udp_mask, 0, sizeof(udp_mask));
670 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
671 udp.hdr.src_port = conf->port;
672 udp_mask.hdr.src_port =
673 rte_flow_item_udp_mask.hdr.src_port;
675 udp.hdr.dst_port = conf->port;
676 udp_mask.hdr.dst_port =
677 rte_flow_item_udp_mask.hdr.dst_port;
679 item.type = RTE_FLOW_ITEM_TYPE_UDP;
681 item.mask = &udp_mask;
684 MLX5_ASSERT(attr->tcp);
685 memset(&tcp, 0, sizeof(tcp));
686 memset(&tcp_mask, 0, sizeof(tcp_mask));
687 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
688 tcp.hdr.src_port = conf->port;
689 tcp_mask.hdr.src_port =
690 rte_flow_item_tcp_mask.hdr.src_port;
692 tcp.hdr.dst_port = conf->port;
693 tcp_mask.hdr.dst_port =
694 rte_flow_item_tcp_mask.hdr.dst_port;
696 item.type = RTE_FLOW_ITEM_TYPE_TCP;
698 item.mask = &tcp_mask;
701 return flow_dv_convert_modify_action(&item, field, NULL, resource,
702 MLX5_MODIFICATION_TYPE_SET, error);
706 * Convert modify-header set TTL action to DV specification.
708 * @param[in,out] resource
709 * Pointer to the modify-header resource.
711 * Pointer to action specification.
713 * Pointer to rte_flow_item objects list.
715 * Pointer to flow attributes structure.
716 * @param[in] dev_flow
717 * Pointer to the sub flow.
718 * @param[in] tunnel_decap
719 * Whether action is after tunnel decapsulation.
721 * Pointer to the error structure.
724 * 0 on success, a negative errno value otherwise and rte_errno is set.
727 flow_dv_convert_action_modify_ttl
728 (struct mlx5_flow_dv_modify_hdr_resource *resource,
729 const struct rte_flow_action *action,
730 const struct rte_flow_item *items,
731 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
732 bool tunnel_decap, struct rte_flow_error *error)
734 const struct rte_flow_action_set_ttl *conf =
735 (const struct rte_flow_action_set_ttl *)(action->conf);
736 struct rte_flow_item item;
737 struct rte_flow_item_ipv4 ipv4;
738 struct rte_flow_item_ipv4 ipv4_mask;
739 struct rte_flow_item_ipv6 ipv6;
740 struct rte_flow_item_ipv6 ipv6_mask;
741 struct field_modify_info *field;
744 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
746 memset(&ipv4, 0, sizeof(ipv4));
747 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
748 ipv4.hdr.time_to_live = conf->ttl_value;
749 ipv4_mask.hdr.time_to_live = 0xFF;
750 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
752 item.mask = &ipv4_mask;
755 MLX5_ASSERT(attr->ipv6);
756 memset(&ipv6, 0, sizeof(ipv6));
757 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
758 ipv6.hdr.hop_limits = conf->ttl_value;
759 ipv6_mask.hdr.hop_limits = 0xFF;
760 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
762 item.mask = &ipv6_mask;
765 return flow_dv_convert_modify_action(&item, field, NULL, resource,
766 MLX5_MODIFICATION_TYPE_SET, error);
770 * Convert modify-header decrement TTL action to DV specification.
772 * @param[in,out] resource
773 * Pointer to the modify-header resource.
775 * Pointer to action specification.
777 * Pointer to rte_flow_item objects list.
779 * Pointer to flow attributes structure.
780 * @param[in] dev_flow
781 * Pointer to the sub flow.
782 * @param[in] tunnel_decap
783 * Whether action is after tunnel decapsulation.
785 * Pointer to the error structure.
788 * 0 on success, a negative errno value otherwise and rte_errno is set.
791 flow_dv_convert_action_modify_dec_ttl
792 (struct mlx5_flow_dv_modify_hdr_resource *resource,
793 const struct rte_flow_item *items,
794 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
795 bool tunnel_decap, struct rte_flow_error *error)
797 struct rte_flow_item item;
798 struct rte_flow_item_ipv4 ipv4;
799 struct rte_flow_item_ipv4 ipv4_mask;
800 struct rte_flow_item_ipv6 ipv6;
801 struct rte_flow_item_ipv6 ipv6_mask;
802 struct field_modify_info *field;
805 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
807 memset(&ipv4, 0, sizeof(ipv4));
808 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
809 ipv4.hdr.time_to_live = 0xFF;
810 ipv4_mask.hdr.time_to_live = 0xFF;
811 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
813 item.mask = &ipv4_mask;
816 MLX5_ASSERT(attr->ipv6);
817 memset(&ipv6, 0, sizeof(ipv6));
818 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
819 ipv6.hdr.hop_limits = 0xFF;
820 ipv6_mask.hdr.hop_limits = 0xFF;
821 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
823 item.mask = &ipv6_mask;
826 return flow_dv_convert_modify_action(&item, field, NULL, resource,
827 MLX5_MODIFICATION_TYPE_ADD, error);
831 * Convert modify-header increment/decrement TCP Sequence number
832 * to DV specification.
834 * @param[in,out] resource
835 * Pointer to the modify-header resource.
837 * Pointer to action specification.
839 * Pointer to the error structure.
842 * 0 on success, a negative errno value otherwise and rte_errno is set.
845 flow_dv_convert_action_modify_tcp_seq
846 (struct mlx5_flow_dv_modify_hdr_resource *resource,
847 const struct rte_flow_action *action,
848 struct rte_flow_error *error)
850 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
851 uint64_t value = rte_be_to_cpu_32(*conf);
852 struct rte_flow_item item;
853 struct rte_flow_item_tcp tcp;
854 struct rte_flow_item_tcp tcp_mask;
856 memset(&tcp, 0, sizeof(tcp));
857 memset(&tcp_mask, 0, sizeof(tcp_mask));
858 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
860 * The HW has no decrement operation, only increment operation.
861 * To simulate decrement X from Y using increment operation
862 * we need to add UINT32_MAX X times to Y.
863 * Each adding of UINT32_MAX decrements Y by 1.
866 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
867 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
868 item.type = RTE_FLOW_ITEM_TYPE_TCP;
870 item.mask = &tcp_mask;
871 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
872 MLX5_MODIFICATION_TYPE_ADD, error);
876 * Convert modify-header increment/decrement TCP Acknowledgment number
877 * to DV specification.
879 * @param[in,out] resource
880 * Pointer to the modify-header resource.
882 * Pointer to action specification.
884 * Pointer to the error structure.
887 * 0 on success, a negative errno value otherwise and rte_errno is set.
890 flow_dv_convert_action_modify_tcp_ack
891 (struct mlx5_flow_dv_modify_hdr_resource *resource,
892 const struct rte_flow_action *action,
893 struct rte_flow_error *error)
895 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
896 uint64_t value = rte_be_to_cpu_32(*conf);
897 struct rte_flow_item item;
898 struct rte_flow_item_tcp tcp;
899 struct rte_flow_item_tcp tcp_mask;
901 memset(&tcp, 0, sizeof(tcp));
902 memset(&tcp_mask, 0, sizeof(tcp_mask));
903 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
905 * The HW has no decrement operation, only increment operation.
906 * To simulate decrement X from Y using increment operation
907 * we need to add UINT32_MAX X times to Y.
908 * Each adding of UINT32_MAX decrements Y by 1.
911 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
912 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
913 item.type = RTE_FLOW_ITEM_TYPE_TCP;
915 item.mask = &tcp_mask;
916 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
917 MLX5_MODIFICATION_TYPE_ADD, error);
920 static enum mlx5_modification_field reg_to_field[] = {
921 [REG_NON] = MLX5_MODI_OUT_NONE,
922 [REG_A] = MLX5_MODI_META_DATA_REG_A,
923 [REG_B] = MLX5_MODI_META_DATA_REG_B,
924 [REG_C_0] = MLX5_MODI_META_REG_C_0,
925 [REG_C_1] = MLX5_MODI_META_REG_C_1,
926 [REG_C_2] = MLX5_MODI_META_REG_C_2,
927 [REG_C_3] = MLX5_MODI_META_REG_C_3,
928 [REG_C_4] = MLX5_MODI_META_REG_C_4,
929 [REG_C_5] = MLX5_MODI_META_REG_C_5,
930 [REG_C_6] = MLX5_MODI_META_REG_C_6,
931 [REG_C_7] = MLX5_MODI_META_REG_C_7,
935 * Convert register set to DV specification.
937 * @param[in,out] resource
938 * Pointer to the modify-header resource.
940 * Pointer to action specification.
942 * Pointer to the error structure.
945 * 0 on success, a negative errno value otherwise and rte_errno is set.
948 flow_dv_convert_action_set_reg
949 (struct mlx5_flow_dv_modify_hdr_resource *resource,
950 const struct rte_flow_action *action,
951 struct rte_flow_error *error)
953 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
954 struct mlx5_modification_cmd *actions = resource->actions;
955 uint32_t i = resource->actions_num;
957 if (i >= MLX5_MAX_MODIFY_NUM)
958 return rte_flow_error_set(error, EINVAL,
959 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
960 "too many items to modify");
961 MLX5_ASSERT(conf->id != REG_NON);
962 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
963 actions[i] = (struct mlx5_modification_cmd) {
964 .action_type = MLX5_MODIFICATION_TYPE_SET,
965 .field = reg_to_field[conf->id],
967 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
968 actions[i].data1 = rte_cpu_to_be_32(conf->data);
970 resource->actions_num = i;
975 * Convert SET_TAG action to DV specification.
978 * Pointer to the rte_eth_dev structure.
979 * @param[in,out] resource
980 * Pointer to the modify-header resource.
982 * Pointer to action specification.
984 * Pointer to the error structure.
987 * 0 on success, a negative errno value otherwise and rte_errno is set.
990 flow_dv_convert_action_set_tag
991 (struct rte_eth_dev *dev,
992 struct mlx5_flow_dv_modify_hdr_resource *resource,
993 const struct rte_flow_action_set_tag *conf,
994 struct rte_flow_error *error)
996 rte_be32_t data = rte_cpu_to_be_32(conf->data);
997 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
998 struct rte_flow_item item = {
1002 struct field_modify_info reg_c_x[] = {
1005 enum mlx5_modification_field reg_type;
1008 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1011 MLX5_ASSERT(ret != REG_NON);
1012 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1013 reg_type = reg_to_field[ret];
1014 MLX5_ASSERT(reg_type > 0);
1015 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1016 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1017 MLX5_MODIFICATION_TYPE_SET, error);
1021 * Convert internal COPY_REG action to DV specification.
1024 * Pointer to the rte_eth_dev structure.
1025 * @param[in,out] res
1026 * Pointer to the modify-header resource.
1028 * Pointer to action specification.
1030 * Pointer to the error structure.
1033 * 0 on success, a negative errno value otherwise and rte_errno is set.
1036 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1037 struct mlx5_flow_dv_modify_hdr_resource *res,
1038 const struct rte_flow_action *action,
1039 struct rte_flow_error *error)
1041 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1042 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1043 struct rte_flow_item item = {
1047 struct field_modify_info reg_src[] = {
1048 {4, 0, reg_to_field[conf->src]},
1051 struct field_modify_info reg_dst = {
1053 .id = reg_to_field[conf->dst],
1055 /* Adjust reg_c[0] usage according to reported mask. */
1056 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1057 struct mlx5_priv *priv = dev->data->dev_private;
1058 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060 MLX5_ASSERT(reg_c0);
1061 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1062 if (conf->dst == REG_C_0) {
1063 /* Copy to reg_c[0], within mask only. */
1064 reg_dst.offset = rte_bsf32(reg_c0);
1066 * Mask is ignoring the enianness, because
1067 * there is no conversion in datapath.
1069 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1070 /* Copy from destination lower bits to reg_c[0]. */
1071 mask = reg_c0 >> reg_dst.offset;
1073 /* Copy from destination upper bits to reg_c[0]. */
1074 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1075 rte_fls_u32(reg_c0));
1078 mask = rte_cpu_to_be_32(reg_c0);
1079 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1080 /* Copy from reg_c[0] to destination lower bits. */
1083 /* Copy from reg_c[0] to destination upper bits. */
1084 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1085 (rte_fls_u32(reg_c0) -
1090 return flow_dv_convert_modify_action(&item,
1091 reg_src, ®_dst, res,
1092 MLX5_MODIFICATION_TYPE_COPY,
1097 * Convert MARK action to DV specification. This routine is used
1098 * in extensive metadata only and requires metadata register to be
1099 * handled. In legacy mode hardware tag resource is engaged.
1102 * Pointer to the rte_eth_dev structure.
1104 * Pointer to MARK action specification.
1105 * @param[in,out] resource
1106 * Pointer to the modify-header resource.
1108 * Pointer to the error structure.
1111 * 0 on success, a negative errno value otherwise and rte_errno is set.
1114 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1115 const struct rte_flow_action_mark *conf,
1116 struct mlx5_flow_dv_modify_hdr_resource *resource,
1117 struct rte_flow_error *error)
1119 struct mlx5_priv *priv = dev->data->dev_private;
1120 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1121 priv->sh->dv_mark_mask);
1122 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1123 struct rte_flow_item item = {
1127 struct field_modify_info reg_c_x[] = {
1133 return rte_flow_error_set(error, EINVAL,
1134 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1135 NULL, "zero mark action mask");
1136 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1139 MLX5_ASSERT(reg > 0);
1140 if (reg == REG_C_0) {
1141 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1142 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1145 mask = rte_cpu_to_be_32(mask) & msk_c0;
1146 mask = rte_cpu_to_be_32(mask << shl_c0);
1148 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1149 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1150 MLX5_MODIFICATION_TYPE_SET, error);
1154 * Get metadata register index for specified steering domain.
1157 * Pointer to the rte_eth_dev structure.
1159 * Attributes of flow to determine steering domain.
1161 * Pointer to the error structure.
1164 * positive index on success, a negative errno value otherwise
1165 * and rte_errno is set.
1167 static enum modify_reg
1168 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1169 const struct rte_flow_attr *attr,
1170 struct rte_flow_error *error)
1173 mlx5_flow_get_reg_id(dev, attr->transfer ?
1177 MLX5_METADATA_RX, 0, error);
1179 return rte_flow_error_set(error,
1180 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1181 NULL, "unavailable "
1182 "metadata register");
1187 * Convert SET_META action to DV specification.
1190 * Pointer to the rte_eth_dev structure.
1191 * @param[in,out] resource
1192 * Pointer to the modify-header resource.
1194 * Attributes of flow that includes this item.
1196 * Pointer to action specification.
1198 * Pointer to the error structure.
1201 * 0 on success, a negative errno value otherwise and rte_errno is set.
1204 flow_dv_convert_action_set_meta
1205 (struct rte_eth_dev *dev,
1206 struct mlx5_flow_dv_modify_hdr_resource *resource,
1207 const struct rte_flow_attr *attr,
1208 const struct rte_flow_action_set_meta *conf,
1209 struct rte_flow_error *error)
1211 uint32_t data = conf->data;
1212 uint32_t mask = conf->mask;
1213 struct rte_flow_item item = {
1217 struct field_modify_info reg_c_x[] = {
1220 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1224 MLX5_ASSERT(reg != REG_NON);
1226 * In datapath code there is no endianness
1227 * coversions for perfromance reasons, all
1228 * pattern conversions are done in rte_flow.
1230 if (reg == REG_C_0) {
1231 struct mlx5_priv *priv = dev->data->dev_private;
1232 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1235 MLX5_ASSERT(msk_c0);
1236 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1237 shl_c0 = rte_bsf32(msk_c0);
1239 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1243 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1246 /* The routine expects parameters in memory as big-endian ones. */
1247 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1248 MLX5_MODIFICATION_TYPE_SET, error);
1252 * Convert modify-header set IPv4 DSCP action to DV specification.
1254 * @param[in,out] resource
1255 * Pointer to the modify-header resource.
1257 * Pointer to action specification.
1259 * Pointer to the error structure.
1262 * 0 on success, a negative errno value otherwise and rte_errno is set.
1265 flow_dv_convert_action_modify_ipv4_dscp
1266 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1267 const struct rte_flow_action *action,
1268 struct rte_flow_error *error)
1270 const struct rte_flow_action_set_dscp *conf =
1271 (const struct rte_flow_action_set_dscp *)(action->conf);
1272 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1273 struct rte_flow_item_ipv4 ipv4;
1274 struct rte_flow_item_ipv4 ipv4_mask;
1276 memset(&ipv4, 0, sizeof(ipv4));
1277 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1278 ipv4.hdr.type_of_service = conf->dscp;
1279 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281 item.mask = &ipv4_mask;
1282 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1283 MLX5_MODIFICATION_TYPE_SET, error);
1287 * Convert modify-header set IPv6 DSCP action to DV specification.
1289 * @param[in,out] resource
1290 * Pointer to the modify-header resource.
1292 * Pointer to action specification.
1294 * Pointer to the error structure.
1297 * 0 on success, a negative errno value otherwise and rte_errno is set.
1300 flow_dv_convert_action_modify_ipv6_dscp
1301 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1302 const struct rte_flow_action *action,
1303 struct rte_flow_error *error)
1305 const struct rte_flow_action_set_dscp *conf =
1306 (const struct rte_flow_action_set_dscp *)(action->conf);
1307 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1308 struct rte_flow_item_ipv6 ipv6;
1309 struct rte_flow_item_ipv6 ipv6_mask;
1311 memset(&ipv6, 0, sizeof(ipv6));
1312 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1315 * rdma-core only accept the DSCP bits byte aligned start from
1316 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1317 * bits in IPv6 case as rdma-core requires byte aligned value.
1319 ipv6.hdr.vtc_flow = conf->dscp;
1320 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322 item.mask = &ipv6_mask;
1323 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1324 MLX5_MODIFICATION_TYPE_SET, error);
1328 * Validate MARK item.
1331 * Pointer to the rte_eth_dev structure.
1333 * Item specification.
1335 * Attributes of flow that includes this item.
1337 * Pointer to error structure.
1340 * 0 on success, a negative errno value otherwise and rte_errno is set.
1343 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1344 const struct rte_flow_item *item,
1345 const struct rte_flow_attr *attr __rte_unused,
1346 struct rte_flow_error *error)
1348 struct mlx5_priv *priv = dev->data->dev_private;
1349 struct mlx5_dev_config *config = &priv->config;
1350 const struct rte_flow_item_mark *spec = item->spec;
1351 const struct rte_flow_item_mark *mask = item->mask;
1352 const struct rte_flow_item_mark nic_mask = {
1353 .id = priv->sh->dv_mark_mask,
1357 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1358 return rte_flow_error_set(error, ENOTSUP,
1359 RTE_FLOW_ERROR_TYPE_ITEM, item,
1360 "extended metadata feature"
1362 if (!mlx5_flow_ext_mreg_supported(dev))
1363 return rte_flow_error_set(error, ENOTSUP,
1364 RTE_FLOW_ERROR_TYPE_ITEM, item,
1365 "extended metadata register"
1366 " isn't supported");
1368 return rte_flow_error_set(error, ENOTSUP,
1369 RTE_FLOW_ERROR_TYPE_ITEM, item,
1370 "extended metadata register"
1371 " isn't available");
1372 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1376 return rte_flow_error_set(error, EINVAL,
1377 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1379 "data cannot be empty");
1380 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1381 return rte_flow_error_set(error, EINVAL,
1382 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1384 "mark id exceeds the limit");
1388 return rte_flow_error_set(error, EINVAL,
1389 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1390 "mask cannot be zero");
1392 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1393 (const uint8_t *)&nic_mask,
1394 sizeof(struct rte_flow_item_mark),
1395 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1402 * Validate META item.
1405 * Pointer to the rte_eth_dev structure.
1407 * Item specification.
1409 * Attributes of flow that includes this item.
1411 * Pointer to error structure.
1414 * 0 on success, a negative errno value otherwise and rte_errno is set.
1417 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1418 const struct rte_flow_item *item,
1419 const struct rte_flow_attr *attr,
1420 struct rte_flow_error *error)
1422 struct mlx5_priv *priv = dev->data->dev_private;
1423 struct mlx5_dev_config *config = &priv->config;
1424 const struct rte_flow_item_meta *spec = item->spec;
1425 const struct rte_flow_item_meta *mask = item->mask;
1426 struct rte_flow_item_meta nic_mask = {
1433 return rte_flow_error_set(error, EINVAL,
1434 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1436 "data cannot be empty");
1437 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1438 if (!mlx5_flow_ext_mreg_supported(dev))
1439 return rte_flow_error_set(error, ENOTSUP,
1440 RTE_FLOW_ERROR_TYPE_ITEM, item,
1441 "extended metadata register"
1442 " isn't supported");
1443 reg = flow_dv_get_metadata_reg(dev, attr, error);
1447 return rte_flow_error_set(error, ENOTSUP,
1448 RTE_FLOW_ERROR_TYPE_ITEM, item,
1449 "unavalable extended metadata register");
1451 return rte_flow_error_set(error, ENOTSUP,
1452 RTE_FLOW_ERROR_TYPE_ITEM, item,
1456 nic_mask.data = priv->sh->dv_meta_mask;
1457 } else if (attr->transfer) {
1458 return rte_flow_error_set(error, ENOTSUP,
1459 RTE_FLOW_ERROR_TYPE_ITEM, item,
1460 "extended metadata feature "
1461 "should be enabled when "
1462 "meta item is requested "
1463 "with e-switch mode ");
1466 mask = &rte_flow_item_meta_mask;
1468 return rte_flow_error_set(error, EINVAL,
1469 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1470 "mask cannot be zero");
1472 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1473 (const uint8_t *)&nic_mask,
1474 sizeof(struct rte_flow_item_meta),
1475 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1480 * Validate TAG item.
1483 * Pointer to the rte_eth_dev structure.
1485 * Item specification.
1487 * Attributes of flow that includes this item.
1489 * Pointer to error structure.
1492 * 0 on success, a negative errno value otherwise and rte_errno is set.
1495 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1496 const struct rte_flow_item *item,
1497 const struct rte_flow_attr *attr __rte_unused,
1498 struct rte_flow_error *error)
1500 const struct rte_flow_item_tag *spec = item->spec;
1501 const struct rte_flow_item_tag *mask = item->mask;
1502 const struct rte_flow_item_tag nic_mask = {
1503 .data = RTE_BE32(UINT32_MAX),
1508 if (!mlx5_flow_ext_mreg_supported(dev))
1509 return rte_flow_error_set(error, ENOTSUP,
1510 RTE_FLOW_ERROR_TYPE_ITEM, item,
1511 "extensive metadata register"
1512 " isn't supported");
1514 return rte_flow_error_set(error, EINVAL,
1515 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1517 "data cannot be empty");
1519 mask = &rte_flow_item_tag_mask;
1521 return rte_flow_error_set(error, EINVAL,
1522 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1523 "mask cannot be zero");
1525 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1526 (const uint8_t *)&nic_mask,
1527 sizeof(struct rte_flow_item_tag),
1528 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1531 if (mask->index != 0xff)
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534 "partial mask for tag index"
1535 " is not supported");
1536 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1539 MLX5_ASSERT(ret != REG_NON);
1544 * Validate vport item.
1547 * Pointer to the rte_eth_dev structure.
1549 * Item specification.
1551 * Attributes of flow that includes this item.
1552 * @param[in] item_flags
1553 * Bit-fields that holds the items detected until now.
1555 * Pointer to error structure.
1558 * 0 on success, a negative errno value otherwise and rte_errno is set.
1561 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1562 const struct rte_flow_item *item,
1563 const struct rte_flow_attr *attr,
1564 uint64_t item_flags,
1565 struct rte_flow_error *error)
1567 const struct rte_flow_item_port_id *spec = item->spec;
1568 const struct rte_flow_item_port_id *mask = item->mask;
1569 const struct rte_flow_item_port_id switch_mask = {
1572 struct mlx5_priv *esw_priv;
1573 struct mlx5_priv *dev_priv;
1576 if (!attr->transfer)
1577 return rte_flow_error_set(error, EINVAL,
1578 RTE_FLOW_ERROR_TYPE_ITEM,
1580 "match on port id is valid only"
1581 " when transfer flag is enabled");
1582 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1583 return rte_flow_error_set(error, ENOTSUP,
1584 RTE_FLOW_ERROR_TYPE_ITEM, item,
1585 "multiple source ports are not"
1588 mask = &switch_mask;
1589 if (mask->id != 0xffffffff)
1590 return rte_flow_error_set(error, ENOTSUP,
1591 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1593 "no support for partial mask on"
1595 ret = mlx5_flow_item_acceptable
1596 (item, (const uint8_t *)mask,
1597 (const uint8_t *)&rte_flow_item_port_id_mask,
1598 sizeof(struct rte_flow_item_port_id),
1599 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1604 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1606 return rte_flow_error_set(error, rte_errno,
1607 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1608 "failed to obtain E-Switch info for"
1610 dev_priv = mlx5_dev_to_eswitch_info(dev);
1612 return rte_flow_error_set(error, rte_errno,
1613 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1615 "failed to obtain E-Switch info");
1616 if (esw_priv->domain_id != dev_priv->domain_id)
1617 return rte_flow_error_set(error, EINVAL,
1618 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619 "cannot match on a port from a"
1620 " different E-Switch");
1625 * Validate VLAN item.
1628 * Item specification.
1629 * @param[in] item_flags
1630 * Bit-fields that holds the items detected until now.
1632 * Ethernet device flow is being created on.
1634 * Pointer to error structure.
1637 * 0 on success, a negative errno value otherwise and rte_errno is set.
1640 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1641 uint64_t item_flags,
1642 struct rte_eth_dev *dev,
1643 struct rte_flow_error *error)
1645 const struct rte_flow_item_vlan *mask = item->mask;
1646 const struct rte_flow_item_vlan nic_mask = {
1647 .tci = RTE_BE16(UINT16_MAX),
1648 .inner_type = RTE_BE16(UINT16_MAX),
1651 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1653 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1654 MLX5_FLOW_LAYER_INNER_L4) :
1655 (MLX5_FLOW_LAYER_OUTER_L3 |
1656 MLX5_FLOW_LAYER_OUTER_L4);
1657 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1658 MLX5_FLOW_LAYER_OUTER_VLAN;
1660 if (item_flags & vlanm)
1661 return rte_flow_error_set(error, EINVAL,
1662 RTE_FLOW_ERROR_TYPE_ITEM, item,
1663 "multiple VLAN layers not supported");
1664 else if ((item_flags & l34m) != 0)
1665 return rte_flow_error_set(error, EINVAL,
1666 RTE_FLOW_ERROR_TYPE_ITEM, item,
1667 "VLAN cannot follow L3/L4 layer");
1669 mask = &rte_flow_item_vlan_mask;
1670 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1671 (const uint8_t *)&nic_mask,
1672 sizeof(struct rte_flow_item_vlan),
1673 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1676 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1677 struct mlx5_priv *priv = dev->data->dev_private;
1679 if (priv->vmwa_context) {
1681 * Non-NULL context means we have a virtual machine
1682 * and SR-IOV enabled, we have to create VLAN interface
1683 * to make hypervisor to setup E-Switch vport
1684 * context correctly. We avoid creating the multiple
1685 * VLAN interfaces, so we cannot support VLAN tag mask.
1687 return rte_flow_error_set(error, EINVAL,
1688 RTE_FLOW_ERROR_TYPE_ITEM,
1690 "VLAN tag mask is not"
1691 " supported in virtual"
1699 * GTP flags are contained in 1 byte of the format:
1700 * -------------------------------------------
1701 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1702 * |-----------------------------------------|
1703 * | value | Version | PT | Res | E | S | PN |
1704 * -------------------------------------------
1706 * Matching is supported only for GTP flags E, S, PN.
1708 #define MLX5_GTP_FLAGS_MASK 0x07
1711 * Validate GTP item.
1714 * Pointer to the rte_eth_dev structure.
1716 * Item specification.
1717 * @param[in] item_flags
1718 * Bit-fields that holds the items detected until now.
1720 * Pointer to error structure.
1723 * 0 on success, a negative errno value otherwise and rte_errno is set.
1726 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1727 const struct rte_flow_item *item,
1728 uint64_t item_flags,
1729 struct rte_flow_error *error)
1731 struct mlx5_priv *priv = dev->data->dev_private;
1732 const struct rte_flow_item_gtp *spec = item->spec;
1733 const struct rte_flow_item_gtp *mask = item->mask;
1734 const struct rte_flow_item_gtp nic_mask = {
1735 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1737 .teid = RTE_BE32(0xffffffff),
1740 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1741 return rte_flow_error_set(error, ENOTSUP,
1742 RTE_FLOW_ERROR_TYPE_ITEM, item,
1743 "GTP support is not enabled");
1744 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1745 return rte_flow_error_set(error, ENOTSUP,
1746 RTE_FLOW_ERROR_TYPE_ITEM, item,
1747 "multiple tunnel layers not"
1749 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1750 return rte_flow_error_set(error, EINVAL,
1751 RTE_FLOW_ERROR_TYPE_ITEM, item,
1752 "no outer UDP layer found");
1754 mask = &rte_flow_item_gtp_mask;
1755 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1756 return rte_flow_error_set(error, ENOTSUP,
1757 RTE_FLOW_ERROR_TYPE_ITEM, item,
1758 "Match is supported for GTP"
1760 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1761 (const uint8_t *)&nic_mask,
1762 sizeof(struct rte_flow_item_gtp),
1763 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1767 * Validate GTP PSC item.
1770 * Item specification.
1771 * @param[in] last_item
1772 * Previous validated item in the pattern items.
1773 * @param[in] gtp_item
1774 * Previous GTP item specification.
1776 * Pointer to flow attributes.
1778 * Pointer to error structure.
1781 * 0 on success, a negative errno value otherwise and rte_errno is set.
1784 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1786 const struct rte_flow_item *gtp_item,
1787 const struct rte_flow_attr *attr,
1788 struct rte_flow_error *error)
1790 const struct rte_flow_item_gtp *gtp_spec;
1791 const struct rte_flow_item_gtp *gtp_mask;
1792 const struct rte_flow_item_gtp_psc *spec;
1793 const struct rte_flow_item_gtp_psc *mask;
1794 const struct rte_flow_item_gtp_psc nic_mask = {
1799 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1800 return rte_flow_error_set
1801 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1802 "GTP PSC item must be preceded with GTP item");
1803 gtp_spec = gtp_item->spec;
1804 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1805 /* GTP spec and E flag is requested to match zero. */
1807 (gtp_mask->v_pt_rsv_flags &
1808 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1809 return rte_flow_error_set
1810 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1811 "GTP E flag must be 1 to match GTP PSC");
1812 /* Check the flow is not created in group zero. */
1813 if (!attr->transfer && !attr->group)
1814 return rte_flow_error_set
1815 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1816 "GTP PSC is not supported for group 0");
1817 /* GTP spec is here and E flag is requested to match zero. */
1821 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1822 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1823 return rte_flow_error_set
1824 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1825 "PDU type should be smaller than 16");
1826 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1827 (const uint8_t *)&nic_mask,
1828 sizeof(struct rte_flow_item_gtp_psc),
1829 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1833 * Validate IPV4 item.
1834 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1835 * add specific validation of fragment_offset field,
1838 * Item specification.
1839 * @param[in] item_flags
1840 * Bit-fields that holds the items detected until now.
1842 * Pointer to error structure.
1845 * 0 on success, a negative errno value otherwise and rte_errno is set.
1848 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1849 uint64_t item_flags,
1851 uint16_t ether_type,
1852 struct rte_flow_error *error)
1855 const struct rte_flow_item_ipv4 *spec = item->spec;
1856 const struct rte_flow_item_ipv4 *last = item->last;
1857 const struct rte_flow_item_ipv4 *mask = item->mask;
1858 rte_be16_t fragment_offset_spec = 0;
1859 rte_be16_t fragment_offset_last = 0;
1860 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1862 .src_addr = RTE_BE32(0xffffffff),
1863 .dst_addr = RTE_BE32(0xffffffff),
1864 .type_of_service = 0xff,
1865 .fragment_offset = RTE_BE16(0xffff),
1866 .next_proto_id = 0xff,
1867 .time_to_live = 0xff,
1871 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1872 ether_type, &nic_ipv4_mask,
1873 MLX5_ITEM_RANGE_ACCEPTED, error);
1877 fragment_offset_spec = spec->hdr.fragment_offset &
1878 mask->hdr.fragment_offset;
1879 if (!fragment_offset_spec)
1882 * spec and mask are valid, enforce using full mask to make sure the
1883 * complete value is used correctly.
1885 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1886 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1887 return rte_flow_error_set(error, EINVAL,
1888 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1889 item, "must use full mask for"
1890 " fragment_offset");
1892 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1893 * indicating this is 1st fragment of fragmented packet.
1894 * This is not yet supported in MLX5, return appropriate error message.
1896 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1897 return rte_flow_error_set(error, ENOTSUP,
1898 RTE_FLOW_ERROR_TYPE_ITEM, item,
1899 "match on first fragment not "
1901 if (fragment_offset_spec && !last)
1902 return rte_flow_error_set(error, ENOTSUP,
1903 RTE_FLOW_ERROR_TYPE_ITEM, item,
1904 "specified value not supported");
1905 /* spec and last are valid, validate the specified range. */
1906 fragment_offset_last = last->hdr.fragment_offset &
1907 mask->hdr.fragment_offset;
1909 * Match on fragment_offset spec 0x2001 and last 0x3fff
1910 * means MF is 1 and frag-offset is > 0.
1911 * This packet is fragment 2nd and onward, excluding last.
1912 * This is not yet supported in MLX5, return appropriate
1915 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1916 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1917 return rte_flow_error_set(error, ENOTSUP,
1918 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1919 last, "match on following "
1920 "fragments not supported");
1922 * Match on fragment_offset spec 0x0001 and last 0x1fff
1923 * means MF is 0 and frag-offset is > 0.
1924 * This packet is last fragment of fragmented packet.
1925 * This is not yet supported in MLX5, return appropriate
1928 if (fragment_offset_spec == RTE_BE16(1) &&
1929 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1930 return rte_flow_error_set(error, ENOTSUP,
1931 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1932 last, "match on last "
1933 "fragment not supported");
1935 * Match on fragment_offset spec 0x0001 and last 0x3fff
1936 * means MF and/or frag-offset is not 0.
1937 * This is a fragmented packet.
1938 * Other range values are invalid and rejected.
1940 if (!(fragment_offset_spec == RTE_BE16(1) &&
1941 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1944 "specified range not supported");
1949 * Validate IPV6 fragment extension item.
1952 * Item specification.
1953 * @param[in] item_flags
1954 * Bit-fields that holds the items detected until now.
1956 * Pointer to error structure.
1959 * 0 on success, a negative errno value otherwise and rte_errno is set.
1962 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1963 uint64_t item_flags,
1964 struct rte_flow_error *error)
1966 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1967 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1968 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1969 rte_be16_t frag_data_spec = 0;
1970 rte_be16_t frag_data_last = 0;
1971 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1972 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1973 MLX5_FLOW_LAYER_OUTER_L4;
1975 struct rte_flow_item_ipv6_frag_ext nic_mask = {
1977 .next_header = 0xff,
1978 .frag_data = RTE_BE16(0xffff),
1982 if (item_flags & l4m)
1983 return rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ITEM, item,
1985 "ipv6 fragment extension item cannot "
1987 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1988 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1989 return rte_flow_error_set(error, EINVAL,
1990 RTE_FLOW_ERROR_TYPE_ITEM, item,
1991 "ipv6 fragment extension item must "
1992 "follow ipv6 item");
1994 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1995 if (!frag_data_spec)
1998 * spec and mask are valid, enforce using full mask to make sure the
1999 * complete value is used correctly.
2001 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2002 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2003 return rte_flow_error_set(error, EINVAL,
2004 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2005 item, "must use full mask for"
2008 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2009 * This is 1st fragment of fragmented packet.
2011 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2012 return rte_flow_error_set(error, ENOTSUP,
2013 RTE_FLOW_ERROR_TYPE_ITEM, item,
2014 "match on first fragment not "
2016 if (frag_data_spec && !last)
2017 return rte_flow_error_set(error, EINVAL,
2018 RTE_FLOW_ERROR_TYPE_ITEM, item,
2019 "specified value not supported");
2020 ret = mlx5_flow_item_acceptable
2021 (item, (const uint8_t *)mask,
2022 (const uint8_t *)&nic_mask,
2023 sizeof(struct rte_flow_item_ipv6_frag_ext),
2024 MLX5_ITEM_RANGE_ACCEPTED, error);
2027 /* spec and last are valid, validate the specified range. */
2028 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2030 * Match on frag_data spec 0x0009 and last 0xfff9
2031 * means M is 1 and frag-offset is > 0.
2032 * This packet is fragment 2nd and onward, excluding last.
2033 * This is not yet supported in MLX5, return appropriate
2036 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2037 RTE_IPV6_EHDR_MF_MASK) &&
2038 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2039 return rte_flow_error_set(error, ENOTSUP,
2040 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2041 last, "match on following "
2042 "fragments not supported");
2044 * Match on frag_data spec 0x0008 and last 0xfff8
2045 * means M is 0 and frag-offset is > 0.
2046 * This packet is last fragment of fragmented packet.
2047 * This is not yet supported in MLX5, return appropriate
2050 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2051 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2054 last, "match on last "
2055 "fragment not supported");
2056 /* Other range values are invalid and rejected. */
2057 return rte_flow_error_set(error, EINVAL,
2058 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2059 "specified range not supported");
2063 * Validate the pop VLAN action.
2066 * Pointer to the rte_eth_dev structure.
2067 * @param[in] action_flags
2068 * Holds the actions detected until now.
2070 * Pointer to the pop vlan action.
2071 * @param[in] item_flags
2072 * The items found in this flow rule.
2074 * Pointer to flow attributes.
2076 * Pointer to error structure.
2079 * 0 on success, a negative errno value otherwise and rte_errno is set.
2082 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2083 uint64_t action_flags,
2084 const struct rte_flow_action *action,
2085 uint64_t item_flags,
2086 const struct rte_flow_attr *attr,
2087 struct rte_flow_error *error)
2089 const struct mlx5_priv *priv = dev->data->dev_private;
2093 if (!priv->sh->pop_vlan_action)
2094 return rte_flow_error_set(error, ENOTSUP,
2095 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2097 "pop vlan action is not supported");
2099 return rte_flow_error_set(error, ENOTSUP,
2100 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2102 "pop vlan action not supported for "
2104 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2105 return rte_flow_error_set(error, ENOTSUP,
2106 RTE_FLOW_ERROR_TYPE_ACTION, action,
2107 "no support for multiple VLAN "
2109 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2110 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2111 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2112 return rte_flow_error_set(error, ENOTSUP,
2113 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2115 "cannot pop vlan after decap without "
2116 "match on inner vlan in the flow");
2117 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2118 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2119 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2120 return rte_flow_error_set(error, ENOTSUP,
2121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2123 "cannot pop vlan without a "
2124 "match on (outer) vlan in the flow");
2125 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2126 return rte_flow_error_set(error, EINVAL,
2127 RTE_FLOW_ERROR_TYPE_ACTION, action,
2128 "wrong action order, port_id should "
2129 "be after pop VLAN action");
2130 if (!attr->transfer && priv->representor)
2131 return rte_flow_error_set(error, ENOTSUP,
2132 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2133 "pop vlan action for VF representor "
2134 "not supported on NIC table");
2139 * Get VLAN default info from vlan match info.
2142 * the list of item specifications.
2144 * pointer VLAN info to fill to.
2147 * 0 on success, a negative errno value otherwise and rte_errno is set.
2150 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2151 struct rte_vlan_hdr *vlan)
2153 const struct rte_flow_item_vlan nic_mask = {
2154 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2155 MLX5DV_FLOW_VLAN_VID_MASK),
2156 .inner_type = RTE_BE16(0xffff),
2161 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2162 int type = items->type;
2164 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2165 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2168 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2169 const struct rte_flow_item_vlan *vlan_m = items->mask;
2170 const struct rte_flow_item_vlan *vlan_v = items->spec;
2172 /* If VLAN item in pattern doesn't contain data, return here. */
2177 /* Only full match values are accepted */
2178 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2179 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2180 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2182 rte_be_to_cpu_16(vlan_v->tci &
2183 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2185 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2186 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2187 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2189 rte_be_to_cpu_16(vlan_v->tci &
2190 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2192 if (vlan_m->inner_type == nic_mask.inner_type)
2193 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2194 vlan_m->inner_type);
2199 * Validate the push VLAN action.
2202 * Pointer to the rte_eth_dev structure.
2203 * @param[in] action_flags
2204 * Holds the actions detected until now.
2205 * @param[in] item_flags
2206 * The items found in this flow rule.
2208 * Pointer to the action structure.
2210 * Pointer to flow attributes
2212 * Pointer to error structure.
2215 * 0 on success, a negative errno value otherwise and rte_errno is set.
2218 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2219 uint64_t action_flags,
2220 const struct rte_flow_item_vlan *vlan_m,
2221 const struct rte_flow_action *action,
2222 const struct rte_flow_attr *attr,
2223 struct rte_flow_error *error)
2225 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2226 const struct mlx5_priv *priv = dev->data->dev_private;
2228 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2229 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2230 return rte_flow_error_set(error, EINVAL,
2231 RTE_FLOW_ERROR_TYPE_ACTION, action,
2232 "invalid vlan ethertype");
2233 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2234 return rte_flow_error_set(error, EINVAL,
2235 RTE_FLOW_ERROR_TYPE_ACTION, action,
2236 "wrong action order, port_id should "
2237 "be after push VLAN");
2238 if (!attr->transfer && priv->representor)
2239 return rte_flow_error_set(error, ENOTSUP,
2240 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2241 "push vlan action for VF representor "
2242 "not supported on NIC table");
2244 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2245 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2246 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2247 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2248 !(mlx5_flow_find_action
2249 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2250 return rte_flow_error_set(error, EINVAL,
2251 RTE_FLOW_ERROR_TYPE_ACTION, action,
2252 "not full match mask on VLAN PCP and "
2253 "there is no of_set_vlan_pcp action, "
2254 "push VLAN action cannot figure out "
2257 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2258 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2259 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2260 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2261 !(mlx5_flow_find_action
2262 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2263 return rte_flow_error_set(error, EINVAL,
2264 RTE_FLOW_ERROR_TYPE_ACTION, action,
2265 "not full match mask on VLAN VID and "
2266 "there is no of_set_vlan_vid action, "
2267 "push VLAN action cannot figure out "
2274 * Validate the set VLAN PCP.
2276 * @param[in] action_flags
2277 * Holds the actions detected until now.
2278 * @param[in] actions
2279 * Pointer to the list of actions remaining in the flow rule.
2281 * Pointer to error structure.
2284 * 0 on success, a negative errno value otherwise and rte_errno is set.
2287 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2288 const struct rte_flow_action actions[],
2289 struct rte_flow_error *error)
2291 const struct rte_flow_action *action = actions;
2292 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2294 if (conf->vlan_pcp > 7)
2295 return rte_flow_error_set(error, EINVAL,
2296 RTE_FLOW_ERROR_TYPE_ACTION, action,
2297 "VLAN PCP value is too big");
2298 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2299 return rte_flow_error_set(error, ENOTSUP,
2300 RTE_FLOW_ERROR_TYPE_ACTION, action,
2301 "set VLAN PCP action must follow "
2302 "the push VLAN action");
2303 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2304 return rte_flow_error_set(error, ENOTSUP,
2305 RTE_FLOW_ERROR_TYPE_ACTION, action,
2306 "Multiple VLAN PCP modification are "
2308 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2309 return rte_flow_error_set(error, EINVAL,
2310 RTE_FLOW_ERROR_TYPE_ACTION, action,
2311 "wrong action order, port_id should "
2312 "be after set VLAN PCP");
2317 * Validate the set VLAN VID.
2319 * @param[in] item_flags
2320 * Holds the items detected in this rule.
2321 * @param[in] action_flags
2322 * Holds the actions detected until now.
2323 * @param[in] actions
2324 * Pointer to the list of actions remaining in the flow rule.
2326 * Pointer to error structure.
2329 * 0 on success, a negative errno value otherwise and rte_errno is set.
2332 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2333 uint64_t action_flags,
2334 const struct rte_flow_action actions[],
2335 struct rte_flow_error *error)
2337 const struct rte_flow_action *action = actions;
2338 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2340 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2341 return rte_flow_error_set(error, EINVAL,
2342 RTE_FLOW_ERROR_TYPE_ACTION, action,
2343 "VLAN VID value is too big");
2344 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2345 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2346 return rte_flow_error_set(error, ENOTSUP,
2347 RTE_FLOW_ERROR_TYPE_ACTION, action,
2348 "set VLAN VID action must follow push"
2349 " VLAN action or match on VLAN item");
2350 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2351 return rte_flow_error_set(error, ENOTSUP,
2352 RTE_FLOW_ERROR_TYPE_ACTION, action,
2353 "Multiple VLAN VID modifications are "
2355 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2356 return rte_flow_error_set(error, EINVAL,
2357 RTE_FLOW_ERROR_TYPE_ACTION, action,
2358 "wrong action order, port_id should "
2359 "be after set VLAN VID");
2364 * Validate the FLAG action.
2367 * Pointer to the rte_eth_dev structure.
2368 * @param[in] action_flags
2369 * Holds the actions detected until now.
2371 * Pointer to flow attributes
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2380 uint64_t action_flags,
2381 const struct rte_flow_attr *attr,
2382 struct rte_flow_error *error)
2384 struct mlx5_priv *priv = dev->data->dev_private;
2385 struct mlx5_dev_config *config = &priv->config;
2388 /* Fall back if no extended metadata register support. */
2389 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2390 return mlx5_flow_validate_action_flag(action_flags, attr,
2392 /* Extensive metadata mode requires registers. */
2393 if (!mlx5_flow_ext_mreg_supported(dev))
2394 return rte_flow_error_set(error, ENOTSUP,
2395 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2396 "no metadata registers "
2397 "to support flag action");
2398 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2399 return rte_flow_error_set(error, ENOTSUP,
2400 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2401 "extended metadata register"
2402 " isn't available");
2403 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2406 MLX5_ASSERT(ret > 0);
2407 if (action_flags & MLX5_FLOW_ACTION_MARK)
2408 return rte_flow_error_set(error, EINVAL,
2409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410 "can't mark and flag in same flow");
2411 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2412 return rte_flow_error_set(error, EINVAL,
2413 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2415 " actions in same flow");
2420 * Validate MARK action.
2423 * Pointer to the rte_eth_dev structure.
2425 * Pointer to action.
2426 * @param[in] action_flags
2427 * Holds the actions detected until now.
2429 * Pointer to flow attributes
2431 * Pointer to error structure.
2434 * 0 on success, a negative errno value otherwise and rte_errno is set.
2437 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2438 const struct rte_flow_action *action,
2439 uint64_t action_flags,
2440 const struct rte_flow_attr *attr,
2441 struct rte_flow_error *error)
2443 struct mlx5_priv *priv = dev->data->dev_private;
2444 struct mlx5_dev_config *config = &priv->config;
2445 const struct rte_flow_action_mark *mark = action->conf;
2448 /* Fall back if no extended metadata register support. */
2449 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2450 return mlx5_flow_validate_action_mark(action, action_flags,
2452 /* Extensive metadata mode requires registers. */
2453 if (!mlx5_flow_ext_mreg_supported(dev))
2454 return rte_flow_error_set(error, ENOTSUP,
2455 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2456 "no metadata registers "
2457 "to support mark action");
2458 if (!priv->sh->dv_mark_mask)
2459 return rte_flow_error_set(error, ENOTSUP,
2460 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2461 "extended metadata register"
2462 " isn't available");
2463 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2466 MLX5_ASSERT(ret > 0);
2468 return rte_flow_error_set(error, EINVAL,
2469 RTE_FLOW_ERROR_TYPE_ACTION, action,
2470 "configuration cannot be null");
2471 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2472 return rte_flow_error_set(error, EINVAL,
2473 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2475 "mark id exceeds the limit");
2476 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2477 return rte_flow_error_set(error, EINVAL,
2478 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2479 "can't flag and mark in same flow");
2480 if (action_flags & MLX5_FLOW_ACTION_MARK)
2481 return rte_flow_error_set(error, EINVAL,
2482 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2483 "can't have 2 mark actions in same"
2489 * Validate SET_META action.
2492 * Pointer to the rte_eth_dev structure.
2494 * Pointer to the action structure.
2495 * @param[in] action_flags
2496 * Holds the actions detected until now.
2498 * Pointer to flow attributes
2500 * Pointer to error structure.
2503 * 0 on success, a negative errno value otherwise and rte_errno is set.
2506 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2507 const struct rte_flow_action *action,
2508 uint64_t action_flags __rte_unused,
2509 const struct rte_flow_attr *attr,
2510 struct rte_flow_error *error)
2512 const struct rte_flow_action_set_meta *conf;
2513 uint32_t nic_mask = UINT32_MAX;
2516 if (!mlx5_flow_ext_mreg_supported(dev))
2517 return rte_flow_error_set(error, ENOTSUP,
2518 RTE_FLOW_ERROR_TYPE_ACTION, action,
2519 "extended metadata register"
2520 " isn't supported");
2521 reg = flow_dv_get_metadata_reg(dev, attr, error);
2525 return rte_flow_error_set(error, ENOTSUP,
2526 RTE_FLOW_ERROR_TYPE_ACTION, action,
2527 "unavalable extended metadata register");
2528 if (reg != REG_A && reg != REG_B) {
2529 struct mlx5_priv *priv = dev->data->dev_private;
2531 nic_mask = priv->sh->dv_meta_mask;
2533 if (!(action->conf))
2534 return rte_flow_error_set(error, EINVAL,
2535 RTE_FLOW_ERROR_TYPE_ACTION, action,
2536 "configuration cannot be null");
2537 conf = (const struct rte_flow_action_set_meta *)action->conf;
2539 return rte_flow_error_set(error, EINVAL,
2540 RTE_FLOW_ERROR_TYPE_ACTION, action,
2541 "zero mask doesn't have any effect");
2542 if (conf->mask & ~nic_mask)
2543 return rte_flow_error_set(error, EINVAL,
2544 RTE_FLOW_ERROR_TYPE_ACTION, action,
2545 "meta data must be within reg C0");
2550 * Validate SET_TAG action.
2553 * Pointer to the rte_eth_dev structure.
2555 * Pointer to the action structure.
2556 * @param[in] action_flags
2557 * Holds the actions detected until now.
2559 * Pointer to flow attributes
2561 * Pointer to error structure.
2564 * 0 on success, a negative errno value otherwise and rte_errno is set.
2567 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2568 const struct rte_flow_action *action,
2569 uint64_t action_flags,
2570 const struct rte_flow_attr *attr,
2571 struct rte_flow_error *error)
2573 const struct rte_flow_action_set_tag *conf;
2574 const uint64_t terminal_action_flags =
2575 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2576 MLX5_FLOW_ACTION_RSS;
2579 if (!mlx5_flow_ext_mreg_supported(dev))
2580 return rte_flow_error_set(error, ENOTSUP,
2581 RTE_FLOW_ERROR_TYPE_ACTION, action,
2582 "extensive metadata register"
2583 " isn't supported");
2584 if (!(action->conf))
2585 return rte_flow_error_set(error, EINVAL,
2586 RTE_FLOW_ERROR_TYPE_ACTION, action,
2587 "configuration cannot be null");
2588 conf = (const struct rte_flow_action_set_tag *)action->conf;
2590 return rte_flow_error_set(error, EINVAL,
2591 RTE_FLOW_ERROR_TYPE_ACTION, action,
2592 "zero mask doesn't have any effect");
2593 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2596 if (!attr->transfer && attr->ingress &&
2597 (action_flags & terminal_action_flags))
2598 return rte_flow_error_set(error, EINVAL,
2599 RTE_FLOW_ERROR_TYPE_ACTION, action,
2600 "set_tag has no effect"
2601 " with terminal actions");
2606 * Validate count action.
2609 * Pointer to rte_eth_dev structure.
2611 * Pointer to error structure.
2614 * 0 on success, a negative errno value otherwise and rte_errno is set.
2617 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2618 struct rte_flow_error *error)
2620 struct mlx5_priv *priv = dev->data->dev_private;
2622 if (!priv->config.devx)
2624 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2628 return rte_flow_error_set
2630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2632 "count action not supported");
2636 * Validate the L2 encap action.
2639 * Pointer to the rte_eth_dev structure.
2640 * @param[in] action_flags
2641 * Holds the actions detected until now.
2643 * Pointer to the action structure.
2645 * Pointer to flow attributes.
2647 * Pointer to error structure.
2650 * 0 on success, a negative errno value otherwise and rte_errno is set.
2653 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2654 uint64_t action_flags,
2655 const struct rte_flow_action *action,
2656 const struct rte_flow_attr *attr,
2657 struct rte_flow_error *error)
2659 const struct mlx5_priv *priv = dev->data->dev_private;
2661 if (!(action->conf))
2662 return rte_flow_error_set(error, EINVAL,
2663 RTE_FLOW_ERROR_TYPE_ACTION, action,
2664 "configuration cannot be null");
2665 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2666 return rte_flow_error_set(error, EINVAL,
2667 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2668 "can only have a single encap action "
2670 if (!attr->transfer && priv->representor)
2671 return rte_flow_error_set(error, ENOTSUP,
2672 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2673 "encap action for VF representor "
2674 "not supported on NIC table");
2679 * Validate a decap action.
2682 * Pointer to the rte_eth_dev structure.
2683 * @param[in] action_flags
2684 * Holds the actions detected until now.
2686 * Pointer to the action structure.
2687 * @param[in] item_flags
2688 * Holds the items detected.
2690 * Pointer to flow attributes
2692 * Pointer to error structure.
2695 * 0 on success, a negative errno value otherwise and rte_errno is set.
2698 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2699 uint64_t action_flags,
2700 const struct rte_flow_action *action,
2701 const uint64_t item_flags,
2702 const struct rte_flow_attr *attr,
2703 struct rte_flow_error *error)
2705 const struct mlx5_priv *priv = dev->data->dev_private;
2707 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2708 !priv->config.decap_en)
2709 return rte_flow_error_set(error, ENOTSUP,
2710 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2711 "decap is not enabled");
2712 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2713 return rte_flow_error_set(error, ENOTSUP,
2714 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2716 MLX5_FLOW_ACTION_DECAP ? "can only "
2717 "have a single decap action" : "decap "
2718 "after encap is not supported");
2719 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2720 return rte_flow_error_set(error, EINVAL,
2721 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2722 "can't have decap action after"
2725 return rte_flow_error_set(error, ENOTSUP,
2726 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2728 "decap action not supported for "
2730 if (!attr->transfer && priv->representor)
2731 return rte_flow_error_set(error, ENOTSUP,
2732 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2733 "decap action for VF representor "
2734 "not supported on NIC table");
2735 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2736 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2737 return rte_flow_error_set(error, ENOTSUP,
2738 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2739 "VXLAN item should be present for VXLAN decap");
2743 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2746 * Validate the raw encap and decap actions.
2749 * Pointer to the rte_eth_dev structure.
2751 * Pointer to the decap action.
2753 * Pointer to the encap action.
2755 * Pointer to flow attributes
2756 * @param[in/out] action_flags
2757 * Holds the actions detected until now.
2758 * @param[out] actions_n
2759 * pointer to the number of actions counter.
2761 * Pointer to the action structure.
2762 * @param[in] item_flags
2763 * Holds the items detected.
2765 * Pointer to error structure.
2768 * 0 on success, a negative errno value otherwise and rte_errno is set.
2771 flow_dv_validate_action_raw_encap_decap
2772 (struct rte_eth_dev *dev,
2773 const struct rte_flow_action_raw_decap *decap,
2774 const struct rte_flow_action_raw_encap *encap,
2775 const struct rte_flow_attr *attr, uint64_t *action_flags,
2776 int *actions_n, const struct rte_flow_action *action,
2777 uint64_t item_flags, struct rte_flow_error *error)
2779 const struct mlx5_priv *priv = dev->data->dev_private;
2782 if (encap && (!encap->size || !encap->data))
2783 return rte_flow_error_set(error, EINVAL,
2784 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2785 "raw encap data cannot be empty");
2786 if (decap && encap) {
2787 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2788 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2791 else if (encap->size <=
2792 MLX5_ENCAPSULATION_DECISION_SIZE &&
2794 MLX5_ENCAPSULATION_DECISION_SIZE)
2797 else if (encap->size >
2798 MLX5_ENCAPSULATION_DECISION_SIZE &&
2800 MLX5_ENCAPSULATION_DECISION_SIZE)
2801 /* 2 L2 actions: encap and decap. */
2804 return rte_flow_error_set(error,
2806 RTE_FLOW_ERROR_TYPE_ACTION,
2807 NULL, "unsupported too small "
2808 "raw decap and too small raw "
2809 "encap combination");
2812 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2813 item_flags, attr, error);
2816 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2820 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2821 return rte_flow_error_set(error, ENOTSUP,
2822 RTE_FLOW_ERROR_TYPE_ACTION,
2824 "small raw encap size");
2825 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2826 return rte_flow_error_set(error, EINVAL,
2827 RTE_FLOW_ERROR_TYPE_ACTION,
2829 "more than one encap action");
2830 if (!attr->transfer && priv->representor)
2831 return rte_flow_error_set
2833 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2834 "encap action for VF representor "
2835 "not supported on NIC table");
2836 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2843 * Match encap_decap resource.
2846 * Pointer to the hash list.
2848 * Pointer to exist resource entry object.
2850 * Key of the new entry.
2852 * Pointer to new encap_decap resource.
2855 * 0 on matching, none-zero otherwise.
2858 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2859 struct mlx5_hlist_entry *entry,
2860 uint64_t key __rte_unused, void *cb_ctx)
2862 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2863 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2864 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2866 cache_resource = container_of(entry,
2867 struct mlx5_flow_dv_encap_decap_resource,
2869 if (resource->reformat_type == cache_resource->reformat_type &&
2870 resource->ft_type == cache_resource->ft_type &&
2871 resource->flags == cache_resource->flags &&
2872 resource->size == cache_resource->size &&
2873 !memcmp((const void *)resource->buf,
2874 (const void *)cache_resource->buf,
2881 * Allocate encap_decap resource.
2884 * Pointer to the hash list.
2886 * Pointer to exist resource entry object.
2888 * Pointer to new encap_decap resource.
2891 * 0 on matching, none-zero otherwise.
2893 struct mlx5_hlist_entry *
2894 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2895 uint64_t key __rte_unused,
2898 struct mlx5_dev_ctx_shared *sh = list->ctx;
2899 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2900 struct mlx5dv_dr_domain *domain;
2901 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2902 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2906 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2907 domain = sh->fdb_domain;
2908 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2909 domain = sh->rx_domain;
2911 domain = sh->tx_domain;
2912 /* Register new encap/decap resource. */
2913 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2915 if (!cache_resource) {
2916 rte_flow_error_set(ctx->error, ENOMEM,
2917 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2918 "cannot allocate resource memory");
2921 *cache_resource = *resource;
2922 cache_resource->idx = idx;
2923 ret = mlx5_flow_os_create_flow_action_packet_reformat
2924 (sh->ctx, domain, cache_resource,
2925 &cache_resource->action);
2927 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2928 rte_flow_error_set(ctx->error, ENOMEM,
2929 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2930 NULL, "cannot create action");
2934 return &cache_resource->entry;
2938 * Find existing encap/decap resource or create and register a new one.
2940 * @param[in, out] dev
2941 * Pointer to rte_eth_dev structure.
2942 * @param[in, out] resource
2943 * Pointer to encap/decap resource.
2944 * @parm[in, out] dev_flow
2945 * Pointer to the dev_flow.
2947 * pointer to error structure.
2950 * 0 on success otherwise -errno and errno is set.
2953 flow_dv_encap_decap_resource_register
2954 (struct rte_eth_dev *dev,
2955 struct mlx5_flow_dv_encap_decap_resource *resource,
2956 struct mlx5_flow *dev_flow,
2957 struct rte_flow_error *error)
2959 struct mlx5_priv *priv = dev->data->dev_private;
2960 struct mlx5_dev_ctx_shared *sh = priv->sh;
2961 struct mlx5_hlist_entry *entry;
2965 uint32_t refmt_type:8;
2967 * Header reformat actions can be shared between
2968 * non-root tables. One bit to indicate non-root
2972 uint32_t reserve:15;
2975 } encap_decap_key = {
2977 .ft_type = resource->ft_type,
2978 .refmt_type = resource->reformat_type,
2979 .is_root = !!dev_flow->dv.group,
2983 struct mlx5_flow_cb_ctx ctx = {
2989 resource->flags = dev_flow->dv.group ? 0 : 1;
2990 key64 = __rte_raw_cksum(&encap_decap_key.v32,
2991 sizeof(encap_decap_key.v32), 0);
2992 if (resource->reformat_type !=
2993 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2995 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2996 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2999 resource = container_of(entry, typeof(*resource), entry);
3000 dev_flow->dv.encap_decap = resource;
3001 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3006 * Find existing table jump resource or create and register a new one.
3008 * @param[in, out] dev
3009 * Pointer to rte_eth_dev structure.
3010 * @param[in, out] tbl
3011 * Pointer to flow table resource.
3012 * @parm[in, out] dev_flow
3013 * Pointer to the dev_flow.
3015 * pointer to error structure.
3018 * 0 on success otherwise -errno and errno is set.
3021 flow_dv_jump_tbl_resource_register
3022 (struct rte_eth_dev *dev __rte_unused,
3023 struct mlx5_flow_tbl_resource *tbl,
3024 struct mlx5_flow *dev_flow,
3025 struct rte_flow_error *error __rte_unused)
3027 struct mlx5_flow_tbl_data_entry *tbl_data =
3028 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3031 MLX5_ASSERT(tbl_data->jump.action);
3032 dev_flow->handle->rix_jump = tbl_data->idx;
3033 dev_flow->dv.jump = &tbl_data->jump;
3038 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3039 struct mlx5_cache_entry *entry, void *cb_ctx)
3041 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3042 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3043 struct mlx5_flow_dv_port_id_action_resource *res =
3044 container_of(entry, typeof(*res), entry);
3046 return ref->port_id != res->port_id;
3049 struct mlx5_cache_entry *
3050 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3051 struct mlx5_cache_entry *entry __rte_unused,
3054 struct mlx5_dev_ctx_shared *sh = list->ctx;
3055 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3056 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3057 struct mlx5_flow_dv_port_id_action_resource *cache;
3061 /* Register new port id action resource. */
3062 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3064 rte_flow_error_set(ctx->error, ENOMEM,
3065 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3066 "cannot allocate port_id action cache memory");
3070 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3074 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3075 rte_flow_error_set(ctx->error, ENOMEM,
3076 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3077 "cannot create action");
3080 return &cache->entry;
3084 * Find existing table port ID resource or create and register a new one.
3086 * @param[in, out] dev
3087 * Pointer to rte_eth_dev structure.
3088 * @param[in, out] resource
3089 * Pointer to port ID action resource.
3090 * @parm[in, out] dev_flow
3091 * Pointer to the dev_flow.
3093 * pointer to error structure.
3096 * 0 on success otherwise -errno and errno is set.
3099 flow_dv_port_id_action_resource_register
3100 (struct rte_eth_dev *dev,
3101 struct mlx5_flow_dv_port_id_action_resource *resource,
3102 struct mlx5_flow *dev_flow,
3103 struct rte_flow_error *error)
3105 struct mlx5_priv *priv = dev->data->dev_private;
3106 struct mlx5_cache_entry *entry;
3107 struct mlx5_flow_dv_port_id_action_resource *cache;
3108 struct mlx5_flow_cb_ctx ctx = {
3113 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3116 cache = container_of(entry, typeof(*cache), entry);
3117 dev_flow->dv.port_id_action = cache;
3118 dev_flow->handle->rix_port_id_action = cache->idx;
3123 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3124 struct mlx5_cache_entry *entry, void *cb_ctx)
3126 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3127 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3128 struct mlx5_flow_dv_push_vlan_action_resource *res =
3129 container_of(entry, typeof(*res), entry);
3131 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3134 struct mlx5_cache_entry *
3135 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3136 struct mlx5_cache_entry *entry __rte_unused,
3139 struct mlx5_dev_ctx_shared *sh = list->ctx;
3140 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3141 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3142 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3143 struct mlx5dv_dr_domain *domain;
3147 /* Register new port id action resource. */
3148 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3150 rte_flow_error_set(ctx->error, ENOMEM,
3151 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3152 "cannot allocate push_vlan action cache memory");
3156 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3157 domain = sh->fdb_domain;
3158 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3159 domain = sh->rx_domain;
3161 domain = sh->tx_domain;
3162 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3165 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3166 rte_flow_error_set(ctx->error, ENOMEM,
3167 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3168 "cannot create push vlan action");
3171 return &cache->entry;
3175 * Find existing push vlan resource or create and register a new one.
3177 * @param [in, out] dev
3178 * Pointer to rte_eth_dev structure.
3179 * @param[in, out] resource
3180 * Pointer to port ID action resource.
3181 * @parm[in, out] dev_flow
3182 * Pointer to the dev_flow.
3184 * pointer to error structure.
3187 * 0 on success otherwise -errno and errno is set.
3190 flow_dv_push_vlan_action_resource_register
3191 (struct rte_eth_dev *dev,
3192 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3193 struct mlx5_flow *dev_flow,
3194 struct rte_flow_error *error)
3196 struct mlx5_priv *priv = dev->data->dev_private;
3197 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3198 struct mlx5_cache_entry *entry;
3199 struct mlx5_flow_cb_ctx ctx = {
3204 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3207 cache = container_of(entry, typeof(*cache), entry);
3209 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3210 dev_flow->dv.push_vlan_res = cache;
3215 * Get the size of specific rte_flow_item_type hdr size
3217 * @param[in] item_type
3218 * Tested rte_flow_item_type.
3221 * sizeof struct item_type, 0 if void or irrelevant.
3224 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3228 switch (item_type) {
3229 case RTE_FLOW_ITEM_TYPE_ETH:
3230 retval = sizeof(struct rte_ether_hdr);
3232 case RTE_FLOW_ITEM_TYPE_VLAN:
3233 retval = sizeof(struct rte_vlan_hdr);
3235 case RTE_FLOW_ITEM_TYPE_IPV4:
3236 retval = sizeof(struct rte_ipv4_hdr);
3238 case RTE_FLOW_ITEM_TYPE_IPV6:
3239 retval = sizeof(struct rte_ipv6_hdr);
3241 case RTE_FLOW_ITEM_TYPE_UDP:
3242 retval = sizeof(struct rte_udp_hdr);
3244 case RTE_FLOW_ITEM_TYPE_TCP:
3245 retval = sizeof(struct rte_tcp_hdr);
3247 case RTE_FLOW_ITEM_TYPE_VXLAN:
3248 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3249 retval = sizeof(struct rte_vxlan_hdr);
3251 case RTE_FLOW_ITEM_TYPE_GRE:
3252 case RTE_FLOW_ITEM_TYPE_NVGRE:
3253 retval = sizeof(struct rte_gre_hdr);
3255 case RTE_FLOW_ITEM_TYPE_MPLS:
3256 retval = sizeof(struct rte_mpls_hdr);
3258 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3266 #define MLX5_ENCAP_IPV4_VERSION 0x40
3267 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3268 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3269 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3270 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3271 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3272 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3275 * Convert the encap action data from list of rte_flow_item to raw buffer
3278 * Pointer to rte_flow_item objects list.
3280 * Pointer to the output buffer.
3282 * Pointer to the output buffer size.
3284 * Pointer to the error structure.
3287 * 0 on success, a negative errno value otherwise and rte_errno is set.
3290 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3291 size_t *size, struct rte_flow_error *error)
3293 struct rte_ether_hdr *eth = NULL;
3294 struct rte_vlan_hdr *vlan = NULL;
3295 struct rte_ipv4_hdr *ipv4 = NULL;
3296 struct rte_ipv6_hdr *ipv6 = NULL;
3297 struct rte_udp_hdr *udp = NULL;
3298 struct rte_vxlan_hdr *vxlan = NULL;
3299 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3300 struct rte_gre_hdr *gre = NULL;
3302 size_t temp_size = 0;
3305 return rte_flow_error_set(error, EINVAL,
3306 RTE_FLOW_ERROR_TYPE_ACTION,
3307 NULL, "invalid empty data");
3308 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3309 len = flow_dv_get_item_hdr_len(items->type);
3310 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION,
3313 (void *)items->type,
3314 "items total size is too big"
3315 " for encap action");
3316 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3317 switch (items->type) {
3318 case RTE_FLOW_ITEM_TYPE_ETH:
3319 eth = (struct rte_ether_hdr *)&buf[temp_size];
3321 case RTE_FLOW_ITEM_TYPE_VLAN:
3322 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3324 return rte_flow_error_set(error, EINVAL,
3325 RTE_FLOW_ERROR_TYPE_ACTION,
3326 (void *)items->type,
3327 "eth header not found");
3328 if (!eth->ether_type)
3329 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3331 case RTE_FLOW_ITEM_TYPE_IPV4:
3332 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3334 return rte_flow_error_set(error, EINVAL,
3335 RTE_FLOW_ERROR_TYPE_ACTION,
3336 (void *)items->type,
3337 "neither eth nor vlan"
3339 if (vlan && !vlan->eth_proto)
3340 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3341 else if (eth && !eth->ether_type)
3342 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3343 if (!ipv4->version_ihl)
3344 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3345 MLX5_ENCAP_IPV4_IHL_MIN;
3346 if (!ipv4->time_to_live)
3347 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3349 case RTE_FLOW_ITEM_TYPE_IPV6:
3350 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3352 return rte_flow_error_set(error, EINVAL,
3353 RTE_FLOW_ERROR_TYPE_ACTION,
3354 (void *)items->type,
3355 "neither eth nor vlan"
3357 if (vlan && !vlan->eth_proto)
3358 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3359 else if (eth && !eth->ether_type)
3360 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3361 if (!ipv6->vtc_flow)
3363 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3364 if (!ipv6->hop_limits)
3365 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3367 case RTE_FLOW_ITEM_TYPE_UDP:
3368 udp = (struct rte_udp_hdr *)&buf[temp_size];
3370 return rte_flow_error_set(error, EINVAL,
3371 RTE_FLOW_ERROR_TYPE_ACTION,
3372 (void *)items->type,
3373 "ip header not found");
3374 if (ipv4 && !ipv4->next_proto_id)
3375 ipv4->next_proto_id = IPPROTO_UDP;
3376 else if (ipv6 && !ipv6->proto)
3377 ipv6->proto = IPPROTO_UDP;
3379 case RTE_FLOW_ITEM_TYPE_VXLAN:
3380 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3382 return rte_flow_error_set(error, EINVAL,
3383 RTE_FLOW_ERROR_TYPE_ACTION,
3384 (void *)items->type,
3385 "udp header not found");
3387 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3388 if (!vxlan->vx_flags)
3390 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3392 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3393 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3395 return rte_flow_error_set(error, EINVAL,
3396 RTE_FLOW_ERROR_TYPE_ACTION,
3397 (void *)items->type,
3398 "udp header not found");
3399 if (!vxlan_gpe->proto)
3400 return rte_flow_error_set(error, EINVAL,
3401 RTE_FLOW_ERROR_TYPE_ACTION,
3402 (void *)items->type,
3403 "next protocol not found");
3406 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3407 if (!vxlan_gpe->vx_flags)
3408 vxlan_gpe->vx_flags =
3409 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3411 case RTE_FLOW_ITEM_TYPE_GRE:
3412 case RTE_FLOW_ITEM_TYPE_NVGRE:
3413 gre = (struct rte_gre_hdr *)&buf[temp_size];
3415 return rte_flow_error_set(error, EINVAL,
3416 RTE_FLOW_ERROR_TYPE_ACTION,
3417 (void *)items->type,
3418 "next protocol not found");
3420 return rte_flow_error_set(error, EINVAL,
3421 RTE_FLOW_ERROR_TYPE_ACTION,
3422 (void *)items->type,
3423 "ip header not found");
3424 if (ipv4 && !ipv4->next_proto_id)
3425 ipv4->next_proto_id = IPPROTO_GRE;
3426 else if (ipv6 && !ipv6->proto)
3427 ipv6->proto = IPPROTO_GRE;
3429 case RTE_FLOW_ITEM_TYPE_VOID:
3432 return rte_flow_error_set(error, EINVAL,
3433 RTE_FLOW_ERROR_TYPE_ACTION,
3434 (void *)items->type,
3435 "unsupported item type");
3445 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3447 struct rte_ether_hdr *eth = NULL;
3448 struct rte_vlan_hdr *vlan = NULL;
3449 struct rte_ipv6_hdr *ipv6 = NULL;
3450 struct rte_udp_hdr *udp = NULL;
3454 eth = (struct rte_ether_hdr *)data;
3455 next_hdr = (char *)(eth + 1);
3456 proto = RTE_BE16(eth->ether_type);
3459 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3460 vlan = (struct rte_vlan_hdr *)next_hdr;
3461 proto = RTE_BE16(vlan->eth_proto);
3462 next_hdr += sizeof(struct rte_vlan_hdr);
3465 /* HW calculates IPv4 csum. no need to proceed */
3466 if (proto == RTE_ETHER_TYPE_IPV4)
3469 /* non IPv4/IPv6 header. not supported */
3470 if (proto != RTE_ETHER_TYPE_IPV6) {
3471 return rte_flow_error_set(error, ENOTSUP,
3472 RTE_FLOW_ERROR_TYPE_ACTION,
3473 NULL, "Cannot offload non IPv4/IPv6");
3476 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3478 /* ignore non UDP */
3479 if (ipv6->proto != IPPROTO_UDP)
3482 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3483 udp->dgram_cksum = 0;
3489 * Convert L2 encap action to DV specification.
3492 * Pointer to rte_eth_dev structure.
3494 * Pointer to action structure.
3495 * @param[in, out] dev_flow
3496 * Pointer to the mlx5_flow.
3497 * @param[in] transfer
3498 * Mark if the flow is E-Switch flow.
3500 * Pointer to the error structure.
3503 * 0 on success, a negative errno value otherwise and rte_errno is set.
3506 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3507 const struct rte_flow_action *action,
3508 struct mlx5_flow *dev_flow,
3510 struct rte_flow_error *error)
3512 const struct rte_flow_item *encap_data;
3513 const struct rte_flow_action_raw_encap *raw_encap_data;
3514 struct mlx5_flow_dv_encap_decap_resource res = {
3516 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3517 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3518 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3521 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3523 (const struct rte_flow_action_raw_encap *)action->conf;
3524 res.size = raw_encap_data->size;
3525 memcpy(res.buf, raw_encap_data->data, res.size);
3527 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3529 ((const struct rte_flow_action_vxlan_encap *)
3530 action->conf)->definition;
3533 ((const struct rte_flow_action_nvgre_encap *)
3534 action->conf)->definition;
3535 if (flow_dv_convert_encap_data(encap_data, res.buf,
3539 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3541 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3542 return rte_flow_error_set(error, EINVAL,
3543 RTE_FLOW_ERROR_TYPE_ACTION,
3544 NULL, "can't create L2 encap action");
3549 * Convert L2 decap action to DV specification.
3552 * Pointer to rte_eth_dev structure.
3553 * @param[in, out] dev_flow
3554 * Pointer to the mlx5_flow.
3555 * @param[in] transfer
3556 * Mark if the flow is E-Switch flow.
3558 * Pointer to the error structure.
3561 * 0 on success, a negative errno value otherwise and rte_errno is set.
3564 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3565 struct mlx5_flow *dev_flow,
3567 struct rte_flow_error *error)
3569 struct mlx5_flow_dv_encap_decap_resource res = {
3572 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3573 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3574 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3577 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3578 return rte_flow_error_set(error, EINVAL,
3579 RTE_FLOW_ERROR_TYPE_ACTION,
3580 NULL, "can't create L2 decap action");
3585 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3588 * Pointer to rte_eth_dev structure.
3590 * Pointer to action structure.
3591 * @param[in, out] dev_flow
3592 * Pointer to the mlx5_flow.
3594 * Pointer to the flow attributes.
3596 * Pointer to the error structure.
3599 * 0 on success, a negative errno value otherwise and rte_errno is set.
3602 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3603 const struct rte_flow_action *action,
3604 struct mlx5_flow *dev_flow,
3605 const struct rte_flow_attr *attr,
3606 struct rte_flow_error *error)
3608 const struct rte_flow_action_raw_encap *encap_data;
3609 struct mlx5_flow_dv_encap_decap_resource res;
3611 memset(&res, 0, sizeof(res));
3612 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3613 res.size = encap_data->size;
3614 memcpy(res.buf, encap_data->data, res.size);
3615 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3616 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3617 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3619 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3621 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3622 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3623 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3624 return rte_flow_error_set(error, EINVAL,
3625 RTE_FLOW_ERROR_TYPE_ACTION,
3626 NULL, "can't create encap action");
3631 * Create action push VLAN.
3634 * Pointer to rte_eth_dev structure.
3636 * Pointer to the flow attributes.
3638 * Pointer to the vlan to push to the Ethernet header.
3639 * @param[in, out] dev_flow
3640 * Pointer to the mlx5_flow.
3642 * Pointer to the error structure.
3645 * 0 on success, a negative errno value otherwise and rte_errno is set.
3648 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3649 const struct rte_flow_attr *attr,
3650 const struct rte_vlan_hdr *vlan,
3651 struct mlx5_flow *dev_flow,
3652 struct rte_flow_error *error)
3654 struct mlx5_flow_dv_push_vlan_action_resource res;
3656 memset(&res, 0, sizeof(res));
3658 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3661 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3663 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3664 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3665 return flow_dv_push_vlan_action_resource_register
3666 (dev, &res, dev_flow, error);
3669 static int fdb_mirror_limit;
3672 * Validate the modify-header actions.
3674 * @param[in] action_flags
3675 * Holds the actions detected until now.
3677 * Pointer to the modify action.
3679 * Pointer to error structure.
3682 * 0 on success, a negative errno value otherwise and rte_errno is set.
3685 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3686 const struct rte_flow_action *action,
3687 struct rte_flow_error *error)
3689 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3690 return rte_flow_error_set(error, EINVAL,
3691 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3692 NULL, "action configuration not set");
3693 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3694 return rte_flow_error_set(error, EINVAL,
3695 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3696 "can't have encap action before"
3698 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror_limit)
3699 return rte_flow_error_set(error, EINVAL,
3700 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3701 "can't support sample action before"
3702 " modify action for E-Switch"
3708 * Validate the modify-header MAC address actions.
3710 * @param[in] action_flags
3711 * Holds the actions detected until now.
3713 * Pointer to the modify action.
3714 * @param[in] item_flags
3715 * Holds the items detected.
3717 * Pointer to error structure.
3720 * 0 on success, a negative errno value otherwise and rte_errno is set.
3723 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3724 const struct rte_flow_action *action,
3725 const uint64_t item_flags,
3726 struct rte_flow_error *error)
3730 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3732 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3733 return rte_flow_error_set(error, EINVAL,
3734 RTE_FLOW_ERROR_TYPE_ACTION,
3736 "no L2 item in pattern");
3742 * Validate the modify-header IPv4 address actions.
3744 * @param[in] action_flags
3745 * Holds the actions detected until now.
3747 * Pointer to the modify action.
3748 * @param[in] item_flags
3749 * Holds the items detected.
3751 * Pointer to error structure.
3754 * 0 on success, a negative errno value otherwise and rte_errno is set.
3757 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3758 const struct rte_flow_action *action,
3759 const uint64_t item_flags,
3760 struct rte_flow_error *error)
3765 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3767 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3768 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3769 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3770 if (!(item_flags & layer))
3771 return rte_flow_error_set(error, EINVAL,
3772 RTE_FLOW_ERROR_TYPE_ACTION,
3774 "no ipv4 item in pattern");
3780 * Validate the modify-header IPv6 address actions.
3782 * @param[in] action_flags
3783 * Holds the actions detected until now.
3785 * Pointer to the modify action.
3786 * @param[in] item_flags
3787 * Holds the items detected.
3789 * Pointer to error structure.
3792 * 0 on success, a negative errno value otherwise and rte_errno is set.
3795 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3796 const struct rte_flow_action *action,
3797 const uint64_t item_flags,
3798 struct rte_flow_error *error)
3803 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3805 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3806 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3807 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3808 if (!(item_flags & layer))
3809 return rte_flow_error_set(error, EINVAL,
3810 RTE_FLOW_ERROR_TYPE_ACTION,
3812 "no ipv6 item in pattern");
3818 * Validate the modify-header TP actions.
3820 * @param[in] action_flags
3821 * Holds the actions detected until now.
3823 * Pointer to the modify action.
3824 * @param[in] item_flags
3825 * Holds the items detected.
3827 * Pointer to error structure.
3830 * 0 on success, a negative errno value otherwise and rte_errno is set.
3833 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3834 const struct rte_flow_action *action,
3835 const uint64_t item_flags,
3836 struct rte_flow_error *error)
3841 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3843 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3844 MLX5_FLOW_LAYER_INNER_L4 :
3845 MLX5_FLOW_LAYER_OUTER_L4;
3846 if (!(item_flags & layer))
3847 return rte_flow_error_set(error, EINVAL,
3848 RTE_FLOW_ERROR_TYPE_ACTION,
3849 NULL, "no transport layer "
3856 * Validate the modify-header actions of increment/decrement
3857 * TCP Sequence-number.
3859 * @param[in] action_flags
3860 * Holds the actions detected until now.
3862 * Pointer to the modify action.
3863 * @param[in] item_flags
3864 * Holds the items detected.
3866 * Pointer to error structure.
3869 * 0 on success, a negative errno value otherwise and rte_errno is set.
3872 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3873 const struct rte_flow_action *action,
3874 const uint64_t item_flags,
3875 struct rte_flow_error *error)
3880 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3882 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3883 MLX5_FLOW_LAYER_INNER_L4_TCP :
3884 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3885 if (!(item_flags & layer))
3886 return rte_flow_error_set(error, EINVAL,
3887 RTE_FLOW_ERROR_TYPE_ACTION,
3888 NULL, "no TCP item in"
3890 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3891 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3892 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3893 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3894 return rte_flow_error_set(error, EINVAL,
3895 RTE_FLOW_ERROR_TYPE_ACTION,
3897 "cannot decrease and increase"
3898 " TCP sequence number"
3899 " at the same time");
3905 * Validate the modify-header actions of increment/decrement
3906 * TCP Acknowledgment number.
3908 * @param[in] action_flags
3909 * Holds the actions detected until now.
3911 * Pointer to the modify action.
3912 * @param[in] item_flags
3913 * Holds the items detected.
3915 * Pointer to error structure.
3918 * 0 on success, a negative errno value otherwise and rte_errno is set.
3921 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3922 const struct rte_flow_action *action,
3923 const uint64_t item_flags,
3924 struct rte_flow_error *error)
3929 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3931 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3932 MLX5_FLOW_LAYER_INNER_L4_TCP :
3933 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3934 if (!(item_flags & layer))
3935 return rte_flow_error_set(error, EINVAL,
3936 RTE_FLOW_ERROR_TYPE_ACTION,
3937 NULL, "no TCP item in"
3939 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3940 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3941 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3942 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3943 return rte_flow_error_set(error, EINVAL,
3944 RTE_FLOW_ERROR_TYPE_ACTION,
3946 "cannot decrease and increase"
3947 " TCP acknowledgment number"
3948 " at the same time");
3954 * Validate the modify-header TTL actions.
3956 * @param[in] action_flags
3957 * Holds the actions detected until now.
3959 * Pointer to the modify action.
3960 * @param[in] item_flags
3961 * Holds the items detected.
3963 * Pointer to error structure.
3966 * 0 on success, a negative errno value otherwise and rte_errno is set.
3969 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3970 const struct rte_flow_action *action,
3971 const uint64_t item_flags,
3972 struct rte_flow_error *error)
3977 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3979 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3980 MLX5_FLOW_LAYER_INNER_L3 :
3981 MLX5_FLOW_LAYER_OUTER_L3;
3982 if (!(item_flags & layer))
3983 return rte_flow_error_set(error, EINVAL,
3984 RTE_FLOW_ERROR_TYPE_ACTION,
3986 "no IP protocol in pattern");
3992 * Validate jump action.
3995 * Pointer to the jump action.
3996 * @param[in] action_flags
3997 * Holds the actions detected until now.
3998 * @param[in] attributes
3999 * Pointer to flow attributes
4000 * @param[in] external
4001 * Action belongs to flow rule created by request external to PMD.
4003 * Pointer to error structure.
4006 * 0 on success, a negative errno value otherwise and rte_errno is set.
4009 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4010 const struct mlx5_flow_tunnel *tunnel,
4011 const struct rte_flow_action *action,
4012 uint64_t action_flags,
4013 const struct rte_flow_attr *attributes,
4014 bool external, struct rte_flow_error *error)
4016 uint32_t target_group, table;
4018 struct flow_grp_info grp_info = {
4019 .external = !!external,
4020 .transfer = !!attributes->transfer,
4024 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4025 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4026 return rte_flow_error_set(error, EINVAL,
4027 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4028 "can't have 2 fate actions in"
4030 if (action_flags & MLX5_FLOW_ACTION_METER)
4031 return rte_flow_error_set(error, ENOTSUP,
4032 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4033 "jump with meter not support");
4035 return rte_flow_error_set(error, EINVAL,
4036 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4037 NULL, "action configuration not set");
4039 ((const struct rte_flow_action_jump *)action->conf)->group;
4040 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4044 if (attributes->group == target_group &&
4045 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4046 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4047 return rte_flow_error_set(error, EINVAL,
4048 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4049 "target group must be other than"
4050 " the current flow group");
4055 * Validate the port_id action.
4058 * Pointer to rte_eth_dev structure.
4059 * @param[in] action_flags
4060 * Bit-fields that holds the actions detected until now.
4062 * Port_id RTE action structure.
4064 * Attributes of flow that includes this action.
4066 * Pointer to error structure.
4069 * 0 on success, a negative errno value otherwise and rte_errno is set.
4072 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4073 uint64_t action_flags,
4074 const struct rte_flow_action *action,
4075 const struct rte_flow_attr *attr,
4076 struct rte_flow_error *error)
4078 const struct rte_flow_action_port_id *port_id;
4079 struct mlx5_priv *act_priv;
4080 struct mlx5_priv *dev_priv;
4083 if (!attr->transfer)
4084 return rte_flow_error_set(error, ENOTSUP,
4085 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4087 "port id action is valid in transfer"
4089 if (!action || !action->conf)
4090 return rte_flow_error_set(error, ENOTSUP,
4091 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4093 "port id action parameters must be"
4095 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4096 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4097 return rte_flow_error_set(error, EINVAL,
4098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4099 "can have only one fate actions in"
4101 dev_priv = mlx5_dev_to_eswitch_info(dev);
4103 return rte_flow_error_set(error, rte_errno,
4104 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4106 "failed to obtain E-Switch info");
4107 port_id = action->conf;
4108 port = port_id->original ? dev->data->port_id : port_id->id;
4109 act_priv = mlx5_port_to_eswitch_info(port, false);
4111 return rte_flow_error_set
4113 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4114 "failed to obtain E-Switch port id for port");
4115 if (act_priv->domain_id != dev_priv->domain_id)
4116 return rte_flow_error_set
4118 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4119 "port does not belong to"
4120 " E-Switch being configured");
4125 * Get the maximum number of modify header actions.
4128 * Pointer to rte_eth_dev structure.
4130 * Flags bits to check if root level.
4133 * Max number of modify header actions device can support.
4135 static inline unsigned int
4136 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4140 * There's no way to directly query the max capacity from FW.
4141 * The maximal value on root table should be assumed to be supported.
4143 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4144 return MLX5_MAX_MODIFY_NUM;
4146 return MLX5_ROOT_TBL_MODIFY_NUM;
4150 * Validate the meter action.
4153 * Pointer to rte_eth_dev structure.
4154 * @param[in] action_flags
4155 * Bit-fields that holds the actions detected until now.
4157 * Pointer to the meter action.
4159 * Attributes of flow that includes this action.
4161 * Pointer to error structure.
4164 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4167 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4168 uint64_t action_flags,
4169 const struct rte_flow_action *action,
4170 const struct rte_flow_attr *attr,
4171 struct rte_flow_error *error)
4173 struct mlx5_priv *priv = dev->data->dev_private;
4174 const struct rte_flow_action_meter *am = action->conf;
4175 struct mlx5_flow_meter *fm;
4178 return rte_flow_error_set(error, EINVAL,
4179 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4180 "meter action conf is NULL");
4182 if (action_flags & MLX5_FLOW_ACTION_METER)
4183 return rte_flow_error_set(error, ENOTSUP,
4184 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4185 "meter chaining not support");
4186 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4187 return rte_flow_error_set(error, ENOTSUP,
4188 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4189 "meter with jump not support");
4191 return rte_flow_error_set(error, ENOTSUP,
4192 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4194 "meter action not supported");
4195 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4197 return rte_flow_error_set(error, EINVAL,
4198 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4200 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4201 (!fm->ingress && !attr->ingress && attr->egress) ||
4202 (!fm->egress && !attr->egress && attr->ingress))))
4203 return rte_flow_error_set(error, EINVAL,
4204 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4205 "Flow attributes are either invalid "
4206 "or have a conflict with current "
4207 "meter attributes");
4212 * Validate the age action.
4214 * @param[in] action_flags
4215 * Holds the actions detected until now.
4217 * Pointer to the age action.
4219 * Pointer to the Ethernet device structure.
4221 * Pointer to error structure.
4224 * 0 on success, a negative errno value otherwise and rte_errno is set.
4227 flow_dv_validate_action_age(uint64_t action_flags,
4228 const struct rte_flow_action *action,
4229 struct rte_eth_dev *dev,
4230 struct rte_flow_error *error)
4232 struct mlx5_priv *priv = dev->data->dev_private;
4233 const struct rte_flow_action_age *age = action->conf;
4235 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4236 !priv->sh->aso_age_mng))
4237 return rte_flow_error_set(error, ENOTSUP,
4238 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4240 "age action not supported");
4241 if (!(action->conf))
4242 return rte_flow_error_set(error, EINVAL,
4243 RTE_FLOW_ERROR_TYPE_ACTION, action,
4244 "configuration cannot be null");
4245 if (!(age->timeout))
4246 return rte_flow_error_set(error, EINVAL,
4247 RTE_FLOW_ERROR_TYPE_ACTION, action,
4248 "invalid timeout value 0");
4249 if (action_flags & MLX5_FLOW_ACTION_AGE)
4250 return rte_flow_error_set(error, EINVAL,
4251 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4252 "duplicate age actions set");
4257 * Validate the modify-header IPv4 DSCP actions.
4259 * @param[in] action_flags
4260 * Holds the actions detected until now.
4262 * Pointer to the modify action.
4263 * @param[in] item_flags
4264 * Holds the items detected.
4266 * Pointer to error structure.
4269 * 0 on success, a negative errno value otherwise and rte_errno is set.
4272 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4273 const struct rte_flow_action *action,
4274 const uint64_t item_flags,
4275 struct rte_flow_error *error)
4279 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4281 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4282 return rte_flow_error_set(error, EINVAL,
4283 RTE_FLOW_ERROR_TYPE_ACTION,
4285 "no ipv4 item in pattern");
4291 * Validate the modify-header IPv6 DSCP actions.
4293 * @param[in] action_flags
4294 * Holds the actions detected until now.
4296 * Pointer to the modify action.
4297 * @param[in] item_flags
4298 * Holds the items detected.
4300 * Pointer to error structure.
4303 * 0 on success, a negative errno value otherwise and rte_errno is set.
4306 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4307 const struct rte_flow_action *action,
4308 const uint64_t item_flags,
4309 struct rte_flow_error *error)
4313 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4315 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4316 return rte_flow_error_set(error, EINVAL,
4317 RTE_FLOW_ERROR_TYPE_ACTION,
4319 "no ipv6 item in pattern");
4325 * Match modify-header resource.
4328 * Pointer to the hash list.
4330 * Pointer to exist resource entry object.
4332 * Key of the new entry.
4334 * Pointer to new modify-header resource.
4337 * 0 on matching, non-zero otherwise.
4340 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4341 struct mlx5_hlist_entry *entry,
4342 uint64_t key __rte_unused, void *cb_ctx)
4344 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4345 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4346 struct mlx5_flow_dv_modify_hdr_resource *resource =
4347 container_of(entry, typeof(*resource), entry);
4348 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4350 key_len += ref->actions_num * sizeof(ref->actions[0]);
4351 return ref->actions_num != resource->actions_num ||
4352 memcmp(&ref->ft_type, &resource->ft_type, key_len);
4355 struct mlx5_hlist_entry *
4356 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4359 struct mlx5_dev_ctx_shared *sh = list->ctx;
4360 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4361 struct mlx5dv_dr_domain *ns;
4362 struct mlx5_flow_dv_modify_hdr_resource *entry;
4363 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4365 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4366 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4368 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4371 rte_flow_error_set(ctx->error, ENOMEM,
4372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4373 "cannot allocate resource memory");
4376 rte_memcpy(&entry->ft_type,
4377 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4378 key_len + data_len);
4379 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4380 ns = sh->fdb_domain;
4381 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4385 ret = mlx5_flow_os_create_flow_action_modify_header
4386 (sh->ctx, ns, entry,
4387 data_len, &entry->action);
4390 rte_flow_error_set(ctx->error, ENOMEM,
4391 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4392 NULL, "cannot create modification action");
4395 return &entry->entry;
4399 * Validate the sample action.
4401 * @param[in] action_flags
4402 * Holds the actions detected until now.
4404 * Pointer to the sample action.
4406 * Pointer to the Ethernet device structure.
4408 * Attributes of flow that includes this action.
4409 * @param[in] item_flags
4410 * Holds the items detected.
4412 * Pointer to the RSS action.
4413 * @param[out] sample_rss
4414 * Pointer to the RSS action in sample action list.
4416 * Pointer to error structure.
4419 * 0 on success, a negative errno value otherwise and rte_errno is set.
4422 flow_dv_validate_action_sample(uint64_t action_flags,
4423 const struct rte_flow_action *action,
4424 struct rte_eth_dev *dev,
4425 const struct rte_flow_attr *attr,
4426 uint64_t item_flags,
4427 const struct rte_flow_action_rss *rss,
4428 const struct rte_flow_action_rss **sample_rss,
4429 struct rte_flow_error *error)
4431 struct mlx5_priv *priv = dev->data->dev_private;
4432 struct mlx5_dev_config *dev_conf = &priv->config;
4433 const struct rte_flow_action_sample *sample = action->conf;
4434 const struct rte_flow_action *act;
4435 uint64_t sub_action_flags = 0;
4436 uint16_t queue_index = 0xFFFF;
4440 fdb_mirror_limit = 0;
4442 return rte_flow_error_set(error, EINVAL,
4443 RTE_FLOW_ERROR_TYPE_ACTION, action,
4444 "configuration cannot be NULL");
4445 if (sample->ratio == 0)
4446 return rte_flow_error_set(error, EINVAL,
4447 RTE_FLOW_ERROR_TYPE_ACTION, action,
4448 "ratio value starts from 1");
4449 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4450 return rte_flow_error_set(error, ENOTSUP,
4451 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4453 "sample action not supported");
4454 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4455 return rte_flow_error_set(error, EINVAL,
4456 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4457 "Multiple sample actions not "
4459 if (action_flags & MLX5_FLOW_ACTION_METER)
4460 return rte_flow_error_set(error, EINVAL,
4461 RTE_FLOW_ERROR_TYPE_ACTION, action,
4462 "wrong action order, meter should "
4463 "be after sample action");
4464 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4465 return rte_flow_error_set(error, EINVAL,
4466 RTE_FLOW_ERROR_TYPE_ACTION, action,
4467 "wrong action order, jump should "
4468 "be after sample action");
4469 act = sample->actions;
4470 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4471 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4472 return rte_flow_error_set(error, ENOTSUP,
4473 RTE_FLOW_ERROR_TYPE_ACTION,
4474 act, "too many actions");
4475 switch (act->type) {
4476 case RTE_FLOW_ACTION_TYPE_QUEUE:
4477 ret = mlx5_flow_validate_action_queue(act,
4483 queue_index = ((const struct rte_flow_action_queue *)
4484 (act->conf))->index;
4485 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4488 case RTE_FLOW_ACTION_TYPE_RSS:
4489 *sample_rss = act->conf;
4490 ret = mlx5_flow_validate_action_rss(act,
4497 if (rss && *sample_rss &&
4498 ((*sample_rss)->level != rss->level ||
4499 (*sample_rss)->types != rss->types))
4500 return rte_flow_error_set(error, ENOTSUP,
4501 RTE_FLOW_ERROR_TYPE_ACTION,
4503 "Can't use the different RSS types "
4504 "or level in the same flow");
4505 if (*sample_rss != NULL && (*sample_rss)->queue_num)
4506 queue_index = (*sample_rss)->queue[0];
4507 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
4510 case RTE_FLOW_ACTION_TYPE_MARK:
4511 ret = flow_dv_validate_action_mark(dev, act,
4516 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4517 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4518 MLX5_FLOW_ACTION_MARK_EXT;
4520 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4523 case RTE_FLOW_ACTION_TYPE_COUNT:
4524 ret = flow_dv_validate_action_count(dev, error);
4527 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4530 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4531 ret = flow_dv_validate_action_port_id(dev,
4538 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4541 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4542 ret = flow_dv_validate_action_raw_encap_decap
4543 (dev, NULL, act->conf, attr, &sub_action_flags,
4544 &actions_n, action, item_flags, error);
4550 return rte_flow_error_set(error, ENOTSUP,
4551 RTE_FLOW_ERROR_TYPE_ACTION,
4553 "Doesn't support optional "
4557 if (attr->ingress && !attr->transfer) {
4558 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
4559 MLX5_FLOW_ACTION_RSS)))
4560 return rte_flow_error_set(error, EINVAL,
4561 RTE_FLOW_ERROR_TYPE_ACTION,
4563 "Ingress must has a dest "
4564 "QUEUE for Sample");
4565 } else if (attr->egress && !attr->transfer) {
4566 return rte_flow_error_set(error, ENOTSUP,
4567 RTE_FLOW_ERROR_TYPE_ACTION,
4569 "Sample Only support Ingress "
4571 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4572 MLX5_ASSERT(attr->transfer);
4573 if (sample->ratio > 1)
4574 return rte_flow_error_set(error, ENOTSUP,
4575 RTE_FLOW_ERROR_TYPE_ACTION,
4577 "E-Switch doesn't support "
4578 "any optional action "
4580 fdb_mirror_limit = 1;
4581 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4582 return rte_flow_error_set(error, ENOTSUP,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "unsupported action QUEUE");
4586 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
4587 return rte_flow_error_set(error, ENOTSUP,
4588 RTE_FLOW_ERROR_TYPE_ACTION,
4590 "unsupported action QUEUE");
4591 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4592 return rte_flow_error_set(error, EINVAL,
4593 RTE_FLOW_ERROR_TYPE_ACTION,
4595 "E-Switch must has a dest "
4596 "port for mirroring");
4598 /* Continue validation for Xcap actions.*/
4599 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4600 (queue_index == 0xFFFF ||
4601 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4602 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4603 MLX5_FLOW_XCAP_ACTIONS)
4604 return rte_flow_error_set(error, ENOTSUP,
4605 RTE_FLOW_ERROR_TYPE_ACTION,
4606 NULL, "encap and decap "
4607 "combination aren't "
4609 if (!attr->transfer && attr->ingress && (sub_action_flags &
4610 MLX5_FLOW_ACTION_ENCAP))
4611 return rte_flow_error_set(error, ENOTSUP,
4612 RTE_FLOW_ERROR_TYPE_ACTION,
4613 NULL, "encap is not supported"
4614 " for ingress traffic");
4620 * Find existing modify-header resource or create and register a new one.
4622 * @param dev[in, out]
4623 * Pointer to rte_eth_dev structure.
4624 * @param[in, out] resource
4625 * Pointer to modify-header resource.
4626 * @parm[in, out] dev_flow
4627 * Pointer to the dev_flow.
4629 * pointer to error structure.
4632 * 0 on success otherwise -errno and errno is set.
4635 flow_dv_modify_hdr_resource_register
4636 (struct rte_eth_dev *dev,
4637 struct mlx5_flow_dv_modify_hdr_resource *resource,
4638 struct mlx5_flow *dev_flow,
4639 struct rte_flow_error *error)
4641 struct mlx5_priv *priv = dev->data->dev_private;
4642 struct mlx5_dev_ctx_shared *sh = priv->sh;
4643 uint32_t key_len = sizeof(*resource) -
4644 offsetof(typeof(*resource), ft_type) +
4645 resource->actions_num * sizeof(resource->actions[0]);
4646 struct mlx5_hlist_entry *entry;
4647 struct mlx5_flow_cb_ctx ctx = {
4653 resource->flags = dev_flow->dv.group ? 0 :
4654 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4655 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4657 return rte_flow_error_set(error, EOVERFLOW,
4658 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4659 "too many modify header items");
4660 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4661 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4664 resource = container_of(entry, typeof(*resource), entry);
4665 dev_flow->handle->dvh.modify_hdr = resource;
4670 * Get DV flow counter by index.
4673 * Pointer to the Ethernet device structure.
4675 * mlx5 flow counter index in the container.
4677 * mlx5 flow counter pool in the container,
4680 * Pointer to the counter, NULL otherwise.
4682 static struct mlx5_flow_counter *
4683 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4685 struct mlx5_flow_counter_pool **ppool)
4687 struct mlx5_priv *priv = dev->data->dev_private;
4688 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4689 struct mlx5_flow_counter_pool *pool;
4691 /* Decrease to original index and clear shared bit. */
4692 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4693 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4694 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4698 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4702 * Check the devx counter belongs to the pool.
4705 * Pointer to the counter pool.
4707 * The counter devx ID.
4710 * True if counter belongs to the pool, false otherwise.
4713 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4715 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4716 MLX5_COUNTERS_PER_POOL;
4718 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4724 * Get a pool by devx counter ID.
4727 * Pointer to the counter management.
4729 * The counter devx ID.
4732 * The counter pool pointer if exists, NULL otherwise,
4734 static struct mlx5_flow_counter_pool *
4735 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4738 struct mlx5_flow_counter_pool *pool = NULL;
4740 rte_spinlock_lock(&cmng->pool_update_sl);
4741 /* Check last used pool. */
4742 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4743 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4744 pool = cmng->pools[cmng->last_pool_idx];
4747 /* ID out of range means no suitable pool in the container. */
4748 if (id > cmng->max_id || id < cmng->min_id)
4751 * Find the pool from the end of the container, since mostly counter
4752 * ID is sequence increasing, and the last pool should be the needed
4757 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4759 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4765 rte_spinlock_unlock(&cmng->pool_update_sl);
4770 * Resize a counter container.
4773 * Pointer to the Ethernet device structure.
4776 * 0 on success, otherwise negative errno value and rte_errno is set.
4779 flow_dv_container_resize(struct rte_eth_dev *dev)
4781 struct mlx5_priv *priv = dev->data->dev_private;
4782 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4783 void *old_pools = cmng->pools;
4784 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4785 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4786 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4793 memcpy(pools, old_pools, cmng->n *
4794 sizeof(struct mlx5_flow_counter_pool *));
4796 cmng->pools = pools;
4798 mlx5_free(old_pools);
4803 * Query a devx flow counter.
4806 * Pointer to the Ethernet device structure.
4808 * Index to the flow counter.
4810 * The statistics value of packets.
4812 * The statistics value of bytes.
4815 * 0 on success, otherwise a negative errno value and rte_errno is set.
4818 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4821 struct mlx5_priv *priv = dev->data->dev_private;
4822 struct mlx5_flow_counter_pool *pool = NULL;
4823 struct mlx5_flow_counter *cnt;
4826 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4828 if (priv->sh->cmng.counter_fallback)
4829 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4830 0, pkts, bytes, 0, NULL, NULL, 0);
4831 rte_spinlock_lock(&pool->sl);
4836 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4837 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4838 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4840 rte_spinlock_unlock(&pool->sl);
4845 * Create and initialize a new counter pool.
4848 * Pointer to the Ethernet device structure.
4850 * The devX counter handle.
4852 * Whether the pool is for counter that was allocated for aging.
4853 * @param[in/out] cont_cur
4854 * Pointer to the container pointer, it will be update in pool resize.
4857 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4859 static struct mlx5_flow_counter_pool *
4860 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4863 struct mlx5_priv *priv = dev->data->dev_private;
4864 struct mlx5_flow_counter_pool *pool;
4865 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4866 bool fallback = priv->sh->cmng.counter_fallback;
4867 uint32_t size = sizeof(*pool);
4869 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4870 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4871 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4877 pool->is_aged = !!age;
4878 pool->query_gen = 0;
4879 pool->min_dcs = dcs;
4880 rte_spinlock_init(&pool->sl);
4881 rte_spinlock_init(&pool->csl);
4882 TAILQ_INIT(&pool->counters[0]);
4883 TAILQ_INIT(&pool->counters[1]);
4884 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4885 rte_spinlock_lock(&cmng->pool_update_sl);
4886 pool->index = cmng->n_valid;
4887 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4889 rte_spinlock_unlock(&cmng->pool_update_sl);
4892 cmng->pools[pool->index] = pool;
4894 if (unlikely(fallback)) {
4895 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4897 if (base < cmng->min_id)
4898 cmng->min_id = base;
4899 if (base > cmng->max_id)
4900 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4901 cmng->last_pool_idx = pool->index;
4903 rte_spinlock_unlock(&cmng->pool_update_sl);
4908 * Prepare a new counter and/or a new counter pool.
4911 * Pointer to the Ethernet device structure.
4912 * @param[out] cnt_free
4913 * Where to put the pointer of a new counter.
4915 * Whether the pool is for counter that was allocated for aging.
4918 * The counter pool pointer and @p cnt_free is set on success,
4919 * NULL otherwise and rte_errno is set.
4921 static struct mlx5_flow_counter_pool *
4922 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4923 struct mlx5_flow_counter **cnt_free,
4926 struct mlx5_priv *priv = dev->data->dev_private;
4927 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4928 struct mlx5_flow_counter_pool *pool;
4929 struct mlx5_counters tmp_tq;
4930 struct mlx5_devx_obj *dcs = NULL;
4931 struct mlx5_flow_counter *cnt;
4932 enum mlx5_counter_type cnt_type =
4933 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4934 bool fallback = priv->sh->cmng.counter_fallback;
4938 /* bulk_bitmap must be 0 for single counter allocation. */
4939 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4942 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4944 pool = flow_dv_pool_create(dev, dcs, age);
4946 mlx5_devx_cmd_destroy(dcs);
4950 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4951 cnt = MLX5_POOL_GET_CNT(pool, i);
4953 cnt->dcs_when_free = dcs;
4957 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4959 rte_errno = ENODATA;
4962 pool = flow_dv_pool_create(dev, dcs, age);
4964 mlx5_devx_cmd_destroy(dcs);
4967 TAILQ_INIT(&tmp_tq);
4968 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4969 cnt = MLX5_POOL_GET_CNT(pool, i);
4971 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4973 rte_spinlock_lock(&cmng->csl[cnt_type]);
4974 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4975 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4976 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4977 (*cnt_free)->pool = pool;
4982 * Allocate a flow counter.
4985 * Pointer to the Ethernet device structure.
4987 * Whether the counter was allocated for aging.
4990 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4993 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4995 struct mlx5_priv *priv = dev->data->dev_private;
4996 struct mlx5_flow_counter_pool *pool = NULL;
4997 struct mlx5_flow_counter *cnt_free = NULL;
4998 bool fallback = priv->sh->cmng.counter_fallback;
4999 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5000 enum mlx5_counter_type cnt_type =
5001 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5004 if (!priv->config.devx) {
5005 rte_errno = ENOTSUP;
5008 /* Get free counters from container. */
5009 rte_spinlock_lock(&cmng->csl[cnt_type]);
5010 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5012 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5013 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5014 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5016 pool = cnt_free->pool;
5018 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5019 /* Create a DV counter action only in the first time usage. */
5020 if (!cnt_free->action) {
5022 struct mlx5_devx_obj *dcs;
5026 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5027 dcs = pool->min_dcs;
5030 dcs = cnt_free->dcs_when_free;
5032 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5039 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5040 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5041 /* Update the counter reset values. */
5042 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5045 if (!fallback && !priv->sh->cmng.query_thread_on)
5046 /* Start the asynchronous batch query by the host thread. */
5047 mlx5_set_query_alarm(priv->sh);
5051 cnt_free->pool = pool;
5053 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5054 rte_spinlock_lock(&cmng->csl[cnt_type]);
5055 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5056 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5062 * Allocate a shared flow counter.
5065 * Pointer to the shared counter configuration.
5067 * Pointer to save the allocated counter index.
5070 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5074 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5076 struct mlx5_shared_counter_conf *conf = ctx;
5077 struct rte_eth_dev *dev = conf->dev;
5078 struct mlx5_flow_counter *cnt;
5080 data->dword = flow_dv_counter_alloc(dev, 0);
5081 data->dword |= MLX5_CNT_SHARED_OFFSET;
5082 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5083 cnt->shared_info.id = conf->id;
5088 * Get a shared flow counter.
5091 * Pointer to the Ethernet device structure.
5093 * Counter identifier.
5096 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5099 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5101 struct mlx5_priv *priv = dev->data->dev_private;
5102 struct mlx5_shared_counter_conf conf = {
5106 union mlx5_l3t_data data = {
5110 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5111 flow_dv_counter_alloc_shared_cb, &conf);
5116 * Get age param from counter index.
5119 * Pointer to the Ethernet device structure.
5120 * @param[in] counter
5121 * Index to the counter handler.
5124 * The aging parameter specified for the counter index.
5126 static struct mlx5_age_param*
5127 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5130 struct mlx5_flow_counter *cnt;
5131 struct mlx5_flow_counter_pool *pool = NULL;
5133 flow_dv_counter_get_by_idx(dev, counter, &pool);
5134 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5135 cnt = MLX5_POOL_GET_CNT(pool, counter);
5136 return MLX5_CNT_TO_AGE(cnt);
5140 * Remove a flow counter from aged counter list.
5143 * Pointer to the Ethernet device structure.
5144 * @param[in] counter
5145 * Index to the counter handler.
5147 * Pointer to the counter handler.
5150 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5151 uint32_t counter, struct mlx5_flow_counter *cnt)
5153 struct mlx5_age_info *age_info;
5154 struct mlx5_age_param *age_param;
5155 struct mlx5_priv *priv = dev->data->dev_private;
5156 uint16_t expected = AGE_CANDIDATE;
5158 age_info = GET_PORT_AGE_INFO(priv);
5159 age_param = flow_dv_counter_idx_get_age(dev, counter);
5160 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5161 AGE_FREE, false, __ATOMIC_RELAXED,
5162 __ATOMIC_RELAXED)) {
5164 * We need the lock even it is age timeout,
5165 * since counter may still in process.
5167 rte_spinlock_lock(&age_info->aged_sl);
5168 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5169 rte_spinlock_unlock(&age_info->aged_sl);
5170 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5175 * Release a flow counter.
5178 * Pointer to the Ethernet device structure.
5179 * @param[in] counter
5180 * Index to the counter handler.
5183 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5185 struct mlx5_priv *priv = dev->data->dev_private;
5186 struct mlx5_flow_counter_pool *pool = NULL;
5187 struct mlx5_flow_counter *cnt;
5188 enum mlx5_counter_type cnt_type;
5192 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5194 if (IS_SHARED_CNT(counter) &&
5195 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5198 flow_dv_counter_remove_from_age(dev, counter, cnt);
5201 * Put the counter back to list to be updated in none fallback mode.
5202 * Currently, we are using two list alternately, while one is in query,
5203 * add the freed counter to the other list based on the pool query_gen
5204 * value. After query finishes, add counter the list to the global
5205 * container counter list. The list changes while query starts. In
5206 * this case, lock will not be needed as query callback and release
5207 * function both operate with the different list.
5210 if (!priv->sh->cmng.counter_fallback) {
5211 rte_spinlock_lock(&pool->csl);
5212 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5213 rte_spinlock_unlock(&pool->csl);
5215 cnt->dcs_when_free = cnt->dcs_when_active;
5216 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5217 MLX5_COUNTER_TYPE_ORIGIN;
5218 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5219 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5221 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5226 * Verify the @p attributes will be correctly understood by the NIC and store
5227 * them in the @p flow if everything is correct.
5230 * Pointer to dev struct.
5231 * @param[in] attributes
5232 * Pointer to flow attributes
5233 * @param[in] external
5234 * This flow rule is created by request external to PMD.
5236 * Pointer to error structure.
5239 * - 0 on success and non root table.
5240 * - 1 on success and root table.
5241 * - a negative errno value otherwise and rte_errno is set.
5244 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5245 const struct mlx5_flow_tunnel *tunnel,
5246 const struct rte_flow_attr *attributes,
5247 const struct flow_grp_info *grp_info,
5248 struct rte_flow_error *error)
5250 struct mlx5_priv *priv = dev->data->dev_private;
5251 uint32_t priority_max = priv->config.flow_prio - 1;
5254 #ifndef HAVE_MLX5DV_DR
5255 RTE_SET_USED(tunnel);
5256 RTE_SET_USED(grp_info);
5257 if (attributes->group)
5258 return rte_flow_error_set(error, ENOTSUP,
5259 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5261 "groups are not supported");
5265 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5270 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5272 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5273 attributes->priority >= priority_max)
5274 return rte_flow_error_set(error, ENOTSUP,
5275 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5277 "priority out of range");
5278 if (attributes->transfer) {
5279 if (!priv->config.dv_esw_en)
5280 return rte_flow_error_set
5282 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5283 "E-Switch dr is not supported");
5284 if (!(priv->representor || priv->master))
5285 return rte_flow_error_set
5286 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5287 NULL, "E-Switch configuration can only be"
5288 " done by a master or a representor device");
5289 if (attributes->egress)
5290 return rte_flow_error_set
5292 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5293 "egress is not supported");
5295 if (!(attributes->egress ^ attributes->ingress))
5296 return rte_flow_error_set(error, ENOTSUP,
5297 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5298 "must specify exactly one of "
5299 "ingress or egress");
5304 * Internal validation function. For validating both actions and items.
5307 * Pointer to the rte_eth_dev structure.
5309 * Pointer to the flow attributes.
5311 * Pointer to the list of items.
5312 * @param[in] actions
5313 * Pointer to the list of actions.
5314 * @param[in] external
5315 * This flow rule is created by request external to PMD.
5316 * @param[in] hairpin
5317 * Number of hairpin TX actions, 0 means classic flow.
5319 * Pointer to the error structure.
5322 * 0 on success, a negative errno value otherwise and rte_errno is set.
5325 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5326 const struct rte_flow_item items[],
5327 const struct rte_flow_action actions[],
5328 bool external, int hairpin, struct rte_flow_error *error)
5331 uint64_t action_flags = 0;
5332 uint64_t item_flags = 0;
5333 uint64_t last_item = 0;
5334 uint8_t next_protocol = 0xff;
5335 uint16_t ether_type = 0;
5337 uint8_t item_ipv6_proto = 0;
5338 const struct rte_flow_item *geneve_item = NULL;
5339 const struct rte_flow_item *gre_item = NULL;
5340 const struct rte_flow_item *gtp_item = NULL;
5341 const struct rte_flow_action_raw_decap *decap;
5342 const struct rte_flow_action_raw_encap *encap;
5343 const struct rte_flow_action_rss *rss = NULL;
5344 const struct rte_flow_action_rss *sample_rss = NULL;
5345 const struct rte_flow_item_tcp nic_tcp_mask = {
5348 .src_port = RTE_BE16(UINT16_MAX),
5349 .dst_port = RTE_BE16(UINT16_MAX),
5352 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5355 "\xff\xff\xff\xff\xff\xff\xff\xff"
5356 "\xff\xff\xff\xff\xff\xff\xff\xff",
5358 "\xff\xff\xff\xff\xff\xff\xff\xff"
5359 "\xff\xff\xff\xff\xff\xff\xff\xff",
5360 .vtc_flow = RTE_BE32(0xffffffff),
5366 const struct rte_flow_item_ecpri nic_ecpri_mask = {
5370 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5374 .dummy[0] = 0xffffffff,
5377 struct mlx5_priv *priv = dev->data->dev_private;
5378 struct mlx5_dev_config *dev_conf = &priv->config;
5379 uint16_t queue_index = 0xFFFF;
5380 const struct rte_flow_item_vlan *vlan_m = NULL;
5381 int16_t rw_act_num = 0;
5383 const struct mlx5_flow_tunnel *tunnel;
5384 struct flow_grp_info grp_info = {
5385 .external = !!external,
5386 .transfer = !!attr->transfer,
5387 .fdb_def_rule = !!priv->fdb_def_rule,
5389 const struct rte_eth_hairpin_conf *conf;
5393 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5394 tunnel = flow_items_to_tunnel(items);
5395 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5396 MLX5_FLOW_ACTION_DECAP;
5397 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5398 tunnel = flow_actions_to_tunnel(actions);
5399 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5403 if (tunnel && priv->representor)
5404 return rte_flow_error_set(error, ENOTSUP,
5405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5406 "decap not supported "
5407 "for VF representor");
5408 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5409 (dev, tunnel, attr, items, actions);
5410 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5413 is_root = (uint64_t)ret;
5414 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5415 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5416 int type = items->type;
5418 if (!mlx5_flow_os_item_supported(type))
5419 return rte_flow_error_set(error, ENOTSUP,
5420 RTE_FLOW_ERROR_TYPE_ITEM,
5421 NULL, "item not supported");
5423 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5424 if (items[0].type != (typeof(items[0].type))
5425 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5426 return rte_flow_error_set
5428 RTE_FLOW_ERROR_TYPE_ITEM,
5429 NULL, "MLX5 private items "
5430 "must be the first");
5432 case RTE_FLOW_ITEM_TYPE_VOID:
5434 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5435 ret = flow_dv_validate_item_port_id
5436 (dev, items, attr, item_flags, error);
5439 last_item = MLX5_FLOW_ITEM_PORT_ID;
5441 case RTE_FLOW_ITEM_TYPE_ETH:
5442 ret = mlx5_flow_validate_item_eth(items, item_flags,
5446 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5447 MLX5_FLOW_LAYER_OUTER_L2;
5448 if (items->mask != NULL && items->spec != NULL) {
5450 ((const struct rte_flow_item_eth *)
5453 ((const struct rte_flow_item_eth *)
5455 ether_type = rte_be_to_cpu_16(ether_type);
5460 case RTE_FLOW_ITEM_TYPE_VLAN:
5461 ret = flow_dv_validate_item_vlan(items, item_flags,
5465 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5466 MLX5_FLOW_LAYER_OUTER_VLAN;
5467 if (items->mask != NULL && items->spec != NULL) {
5469 ((const struct rte_flow_item_vlan *)
5470 items->spec)->inner_type;
5472 ((const struct rte_flow_item_vlan *)
5473 items->mask)->inner_type;
5474 ether_type = rte_be_to_cpu_16(ether_type);
5478 /* Store outer VLAN mask for of_push_vlan action. */
5480 vlan_m = items->mask;
5482 case RTE_FLOW_ITEM_TYPE_IPV4:
5483 mlx5_flow_tunnel_ip_check(items, next_protocol,
5484 &item_flags, &tunnel);
5485 ret = flow_dv_validate_item_ipv4(items, item_flags,
5486 last_item, ether_type,
5490 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5491 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5492 if (items->mask != NULL &&
5493 ((const struct rte_flow_item_ipv4 *)
5494 items->mask)->hdr.next_proto_id) {
5496 ((const struct rte_flow_item_ipv4 *)
5497 (items->spec))->hdr.next_proto_id;
5499 ((const struct rte_flow_item_ipv4 *)
5500 (items->mask))->hdr.next_proto_id;
5502 /* Reset for inner layer. */
5503 next_protocol = 0xff;
5506 case RTE_FLOW_ITEM_TYPE_IPV6:
5507 mlx5_flow_tunnel_ip_check(items, next_protocol,
5508 &item_flags, &tunnel);
5509 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5516 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5517 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5518 if (items->mask != NULL &&
5519 ((const struct rte_flow_item_ipv6 *)
5520 items->mask)->hdr.proto) {
5522 ((const struct rte_flow_item_ipv6 *)
5523 items->spec)->hdr.proto;
5525 ((const struct rte_flow_item_ipv6 *)
5526 items->spec)->hdr.proto;
5528 ((const struct rte_flow_item_ipv6 *)
5529 items->mask)->hdr.proto;
5531 /* Reset for inner layer. */
5532 next_protocol = 0xff;
5535 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5536 ret = flow_dv_validate_item_ipv6_frag_ext(items,
5541 last_item = tunnel ?
5542 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5543 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5544 if (items->mask != NULL &&
5545 ((const struct rte_flow_item_ipv6_frag_ext *)
5546 items->mask)->hdr.next_header) {
5548 ((const struct rte_flow_item_ipv6_frag_ext *)
5549 items->spec)->hdr.next_header;
5551 ((const struct rte_flow_item_ipv6_frag_ext *)
5552 items->mask)->hdr.next_header;
5554 /* Reset for inner layer. */
5555 next_protocol = 0xff;
5558 case RTE_FLOW_ITEM_TYPE_TCP:
5559 ret = mlx5_flow_validate_item_tcp
5566 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5567 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5569 case RTE_FLOW_ITEM_TYPE_UDP:
5570 ret = mlx5_flow_validate_item_udp(items, item_flags,
5575 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5576 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5578 case RTE_FLOW_ITEM_TYPE_GRE:
5579 ret = mlx5_flow_validate_item_gre(items, item_flags,
5580 next_protocol, error);
5584 last_item = MLX5_FLOW_LAYER_GRE;
5586 case RTE_FLOW_ITEM_TYPE_NVGRE:
5587 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5592 last_item = MLX5_FLOW_LAYER_NVGRE;
5594 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5595 ret = mlx5_flow_validate_item_gre_key
5596 (items, item_flags, gre_item, error);
5599 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5601 case RTE_FLOW_ITEM_TYPE_VXLAN:
5602 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5606 last_item = MLX5_FLOW_LAYER_VXLAN;
5608 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5609 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5614 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5616 case RTE_FLOW_ITEM_TYPE_GENEVE:
5617 ret = mlx5_flow_validate_item_geneve(items,
5622 geneve_item = items;
5623 last_item = MLX5_FLOW_LAYER_GENEVE;
5625 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
5626 ret = mlx5_flow_validate_item_geneve_opt(items,
5633 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
5635 case RTE_FLOW_ITEM_TYPE_MPLS:
5636 ret = mlx5_flow_validate_item_mpls(dev, items,
5641 last_item = MLX5_FLOW_LAYER_MPLS;
5644 case RTE_FLOW_ITEM_TYPE_MARK:
5645 ret = flow_dv_validate_item_mark(dev, items, attr,
5649 last_item = MLX5_FLOW_ITEM_MARK;
5651 case RTE_FLOW_ITEM_TYPE_META:
5652 ret = flow_dv_validate_item_meta(dev, items, attr,
5656 last_item = MLX5_FLOW_ITEM_METADATA;
5658 case RTE_FLOW_ITEM_TYPE_ICMP:
5659 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5664 last_item = MLX5_FLOW_LAYER_ICMP;
5666 case RTE_FLOW_ITEM_TYPE_ICMP6:
5667 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5672 item_ipv6_proto = IPPROTO_ICMPV6;
5673 last_item = MLX5_FLOW_LAYER_ICMP6;
5675 case RTE_FLOW_ITEM_TYPE_TAG:
5676 ret = flow_dv_validate_item_tag(dev, items,
5680 last_item = MLX5_FLOW_ITEM_TAG;
5682 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5683 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5685 case RTE_FLOW_ITEM_TYPE_GTP:
5686 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5691 last_item = MLX5_FLOW_LAYER_GTP;
5693 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5694 ret = flow_dv_validate_item_gtp_psc(items, last_item,
5699 last_item = MLX5_FLOW_LAYER_GTP_PSC;
5701 case RTE_FLOW_ITEM_TYPE_ECPRI:
5702 /* Capacity will be checked in the translate stage. */
5703 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5710 last_item = MLX5_FLOW_LAYER_ECPRI;
5713 return rte_flow_error_set(error, ENOTSUP,
5714 RTE_FLOW_ERROR_TYPE_ITEM,
5715 NULL, "item not supported");
5717 item_flags |= last_item;
5719 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5720 int type = actions->type;
5722 if (!mlx5_flow_os_action_supported(type))
5723 return rte_flow_error_set(error, ENOTSUP,
5724 RTE_FLOW_ERROR_TYPE_ACTION,
5726 "action not supported");
5727 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5728 return rte_flow_error_set(error, ENOTSUP,
5729 RTE_FLOW_ERROR_TYPE_ACTION,
5730 actions, "too many actions");
5732 case RTE_FLOW_ACTION_TYPE_VOID:
5734 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5735 ret = flow_dv_validate_action_port_id(dev,
5742 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5745 case RTE_FLOW_ACTION_TYPE_FLAG:
5746 ret = flow_dv_validate_action_flag(dev, action_flags,
5750 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5751 /* Count all modify-header actions as one. */
5752 if (!(action_flags &
5753 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5755 action_flags |= MLX5_FLOW_ACTION_FLAG |
5756 MLX5_FLOW_ACTION_MARK_EXT;
5758 action_flags |= MLX5_FLOW_ACTION_FLAG;
5761 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5763 case RTE_FLOW_ACTION_TYPE_MARK:
5764 ret = flow_dv_validate_action_mark(dev, actions,
5769 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5770 /* Count all modify-header actions as one. */
5771 if (!(action_flags &
5772 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5774 action_flags |= MLX5_FLOW_ACTION_MARK |
5775 MLX5_FLOW_ACTION_MARK_EXT;
5777 action_flags |= MLX5_FLOW_ACTION_MARK;
5780 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5782 case RTE_FLOW_ACTION_TYPE_SET_META:
5783 ret = flow_dv_validate_action_set_meta(dev, actions,
5788 /* Count all modify-header actions as one action. */
5789 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5791 action_flags |= MLX5_FLOW_ACTION_SET_META;
5792 rw_act_num += MLX5_ACT_NUM_SET_META;
5794 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5795 ret = flow_dv_validate_action_set_tag(dev, actions,
5800 /* Count all modify-header actions as one action. */
5801 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5803 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5804 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5806 case RTE_FLOW_ACTION_TYPE_DROP:
5807 ret = mlx5_flow_validate_action_drop(action_flags,
5811 action_flags |= MLX5_FLOW_ACTION_DROP;
5814 case RTE_FLOW_ACTION_TYPE_QUEUE:
5815 ret = mlx5_flow_validate_action_queue(actions,
5820 queue_index = ((const struct rte_flow_action_queue *)
5821 (actions->conf))->index;
5822 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5825 case RTE_FLOW_ACTION_TYPE_RSS:
5826 rss = actions->conf;
5827 ret = mlx5_flow_validate_action_rss(actions,
5833 if (rss && sample_rss &&
5834 (sample_rss->level != rss->level ||
5835 sample_rss->types != rss->types))
5836 return rte_flow_error_set(error, ENOTSUP,
5837 RTE_FLOW_ERROR_TYPE_ACTION,
5839 "Can't use the different RSS types "
5840 "or level in the same flow");
5841 if (rss != NULL && rss->queue_num)
5842 queue_index = rss->queue[0];
5843 action_flags |= MLX5_FLOW_ACTION_RSS;
5846 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5848 mlx5_flow_validate_action_default_miss(action_flags,
5852 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5855 case RTE_FLOW_ACTION_TYPE_COUNT:
5856 ret = flow_dv_validate_action_count(dev, error);
5859 action_flags |= MLX5_FLOW_ACTION_COUNT;
5862 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5863 if (flow_dv_validate_action_pop_vlan(dev,
5869 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5872 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5873 ret = flow_dv_validate_action_push_vlan(dev,
5880 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5883 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5884 ret = flow_dv_validate_action_set_vlan_pcp
5885 (action_flags, actions, error);
5888 /* Count PCP with push_vlan command. */
5889 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5891 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5892 ret = flow_dv_validate_action_set_vlan_vid
5893 (item_flags, action_flags,
5897 /* Count VID with push_vlan command. */
5898 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5899 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5901 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5902 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5903 ret = flow_dv_validate_action_l2_encap(dev,
5909 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5912 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5913 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5914 ret = flow_dv_validate_action_decap(dev, action_flags,
5915 actions, item_flags,
5919 action_flags |= MLX5_FLOW_ACTION_DECAP;
5922 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5923 ret = flow_dv_validate_action_raw_encap_decap
5924 (dev, NULL, actions->conf, attr, &action_flags,
5925 &actions_n, actions, item_flags, error);
5929 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5930 decap = actions->conf;
5931 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5933 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5937 encap = actions->conf;
5939 ret = flow_dv_validate_action_raw_encap_decap
5941 decap ? decap : &empty_decap, encap,
5942 attr, &action_flags, &actions_n,
5943 actions, item_flags, error);
5947 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5948 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5949 ret = flow_dv_validate_action_modify_mac(action_flags,
5955 /* Count all modify-header actions as one action. */
5956 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5958 action_flags |= actions->type ==
5959 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5960 MLX5_FLOW_ACTION_SET_MAC_SRC :
5961 MLX5_FLOW_ACTION_SET_MAC_DST;
5963 * Even if the source and destination MAC addresses have
5964 * overlap in the header with 4B alignment, the convert
5965 * function will handle them separately and 4 SW actions
5966 * will be created. And 2 actions will be added each
5967 * time no matter how many bytes of address will be set.
5969 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5971 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5972 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5973 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5979 /* Count all modify-header actions as one action. */
5980 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5982 action_flags |= actions->type ==
5983 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5984 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5985 MLX5_FLOW_ACTION_SET_IPV4_DST;
5986 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5988 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5989 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5990 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5996 if (item_ipv6_proto == IPPROTO_ICMPV6)
5997 return rte_flow_error_set(error, ENOTSUP,
5998 RTE_FLOW_ERROR_TYPE_ACTION,
6000 "Can't change header "
6001 "with ICMPv6 proto");
6002 /* Count all modify-header actions as one action. */
6003 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6005 action_flags |= actions->type ==
6006 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6007 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6008 MLX5_FLOW_ACTION_SET_IPV6_DST;
6009 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6011 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6012 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6013 ret = flow_dv_validate_action_modify_tp(action_flags,
6019 /* Count all modify-header actions as one action. */
6020 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6022 action_flags |= actions->type ==
6023 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6024 MLX5_FLOW_ACTION_SET_TP_SRC :
6025 MLX5_FLOW_ACTION_SET_TP_DST;
6026 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6028 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6029 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6030 ret = flow_dv_validate_action_modify_ttl(action_flags,
6036 /* Count all modify-header actions as one action. */
6037 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6039 action_flags |= actions->type ==
6040 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6041 MLX5_FLOW_ACTION_SET_TTL :
6042 MLX5_FLOW_ACTION_DEC_TTL;
6043 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6045 case RTE_FLOW_ACTION_TYPE_JUMP:
6046 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6053 action_flags |= MLX5_FLOW_ACTION_JUMP;
6055 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6056 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6057 ret = flow_dv_validate_action_modify_tcp_seq
6064 /* Count all modify-header actions as one action. */
6065 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6067 action_flags |= actions->type ==
6068 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6069 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6070 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6071 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6073 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6074 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6075 ret = flow_dv_validate_action_modify_tcp_ack
6082 /* Count all modify-header actions as one action. */
6083 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6085 action_flags |= actions->type ==
6086 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6087 MLX5_FLOW_ACTION_INC_TCP_ACK :
6088 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6089 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6091 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6093 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6094 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6095 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6097 case RTE_FLOW_ACTION_TYPE_METER:
6098 ret = mlx5_flow_validate_action_meter(dev,
6104 action_flags |= MLX5_FLOW_ACTION_METER;
6106 /* Meter action will add one more TAG action. */
6107 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6109 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6110 if (!attr->transfer && !attr->group)
6111 return rte_flow_error_set(error, ENOTSUP,
6112 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6114 "Shared ASO age action is not supported for group 0");
6115 action_flags |= MLX5_FLOW_ACTION_AGE;
6118 case RTE_FLOW_ACTION_TYPE_AGE:
6119 ret = flow_dv_validate_action_age(action_flags,
6124 action_flags |= MLX5_FLOW_ACTION_AGE;
6127 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6128 ret = flow_dv_validate_action_modify_ipv4_dscp
6135 /* Count all modify-header actions as one action. */
6136 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6138 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6139 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6141 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6142 ret = flow_dv_validate_action_modify_ipv6_dscp
6149 /* Count all modify-header actions as one action. */
6150 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6152 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6153 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6155 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6156 ret = flow_dv_validate_action_sample(action_flags,
6163 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6166 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6167 if (actions[0].type != (typeof(actions[0].type))
6168 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6169 return rte_flow_error_set
6171 RTE_FLOW_ERROR_TYPE_ACTION,
6172 NULL, "MLX5 private action "
6173 "must be the first");
6175 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6178 return rte_flow_error_set(error, ENOTSUP,
6179 RTE_FLOW_ERROR_TYPE_ACTION,
6181 "action not supported");
6185 * Validate actions in flow rules
6186 * - Explicit decap action is prohibited by the tunnel offload API.
6187 * - Drop action in tunnel steer rule is prohibited by the API.
6188 * - Application cannot use MARK action because it's value can mask
6189 * tunnel default miss nitification.
6190 * - JUMP in tunnel match rule has no support in current PMD
6192 * - TAG & META are reserved for future uses.
6194 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6195 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6196 MLX5_FLOW_ACTION_MARK |
6197 MLX5_FLOW_ACTION_SET_TAG |
6198 MLX5_FLOW_ACTION_SET_META |
6199 MLX5_FLOW_ACTION_DROP;
6201 if (action_flags & bad_actions_mask)
6202 return rte_flow_error_set
6204 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6205 "Invalid RTE action in tunnel "
6207 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6208 return rte_flow_error_set
6210 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6211 "tunnel set decap rule must terminate "
6214 return rte_flow_error_set
6216 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6217 "tunnel flows for ingress traffic only");
6219 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6220 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6221 MLX5_FLOW_ACTION_MARK |
6222 MLX5_FLOW_ACTION_SET_TAG |
6223 MLX5_FLOW_ACTION_SET_META;
6225 if (action_flags & bad_actions_mask)
6226 return rte_flow_error_set
6228 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6229 "Invalid RTE action in tunnel "
6233 * Validate the drop action mutual exclusion with other actions.
6234 * Drop action is mutually-exclusive with any other action, except for
6237 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6238 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6239 return rte_flow_error_set(error, EINVAL,
6240 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6241 "Drop action is mutually-exclusive "
6242 "with any other action, except for "
6244 /* Eswitch has few restrictions on using items and actions */
6245 if (attr->transfer) {
6246 if (!mlx5_flow_ext_mreg_supported(dev) &&
6247 action_flags & MLX5_FLOW_ACTION_FLAG)
6248 return rte_flow_error_set(error, ENOTSUP,
6249 RTE_FLOW_ERROR_TYPE_ACTION,
6251 "unsupported action FLAG");
6252 if (!mlx5_flow_ext_mreg_supported(dev) &&
6253 action_flags & MLX5_FLOW_ACTION_MARK)
6254 return rte_flow_error_set(error, ENOTSUP,
6255 RTE_FLOW_ERROR_TYPE_ACTION,
6257 "unsupported action MARK");
6258 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6259 return rte_flow_error_set(error, ENOTSUP,
6260 RTE_FLOW_ERROR_TYPE_ACTION,
6262 "unsupported action QUEUE");
6263 if (action_flags & MLX5_FLOW_ACTION_RSS)
6264 return rte_flow_error_set(error, ENOTSUP,
6265 RTE_FLOW_ERROR_TYPE_ACTION,
6267 "unsupported action RSS");
6268 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6269 return rte_flow_error_set(error, EINVAL,
6270 RTE_FLOW_ERROR_TYPE_ACTION,
6272 "no fate action is found");
6274 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6275 return rte_flow_error_set(error, EINVAL,
6276 RTE_FLOW_ERROR_TYPE_ACTION,
6278 "no fate action is found");
6281 * Continue validation for Xcap and VLAN actions.
6282 * If hairpin is working in explicit TX rule mode, there is no actions
6283 * splitting and the validation of hairpin ingress flow should be the
6284 * same as other standard flows.
6286 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6287 MLX5_FLOW_VLAN_ACTIONS)) &&
6288 (queue_index == 0xFFFF ||
6289 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6290 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6291 conf->tx_explicit != 0))) {
6292 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6293 MLX5_FLOW_XCAP_ACTIONS)
6294 return rte_flow_error_set(error, ENOTSUP,
6295 RTE_FLOW_ERROR_TYPE_ACTION,
6296 NULL, "encap and decap "
6297 "combination aren't supported");
6298 if (!attr->transfer && attr->ingress) {
6299 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6300 return rte_flow_error_set
6302 RTE_FLOW_ERROR_TYPE_ACTION,
6303 NULL, "encap is not supported"
6304 " for ingress traffic");
6305 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6306 return rte_flow_error_set
6308 RTE_FLOW_ERROR_TYPE_ACTION,
6309 NULL, "push VLAN action not "
6310 "supported for ingress");
6311 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6312 MLX5_FLOW_VLAN_ACTIONS)
6313 return rte_flow_error_set
6315 RTE_FLOW_ERROR_TYPE_ACTION,
6316 NULL, "no support for "
6317 "multiple VLAN actions");
6321 * Hairpin flow will add one more TAG action in TX implicit mode.
6322 * In TX explicit mode, there will be no hairpin flow ID.
6325 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6326 /* extra metadata enabled: one more TAG action will be add. */
6327 if (dev_conf->dv_flow_en &&
6328 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6329 mlx5_flow_ext_mreg_supported(dev))
6330 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6331 if ((uint32_t)rw_act_num >
6332 flow_dv_modify_hdr_action_max(dev, is_root)) {
6333 return rte_flow_error_set(error, ENOTSUP,
6334 RTE_FLOW_ERROR_TYPE_ACTION,
6335 NULL, "too many header modify"
6336 " actions to support");
6342 * Internal preparation function. Allocates the DV flow size,
6343 * this size is constant.
6346 * Pointer to the rte_eth_dev structure.
6348 * Pointer to the flow attributes.
6350 * Pointer to the list of items.
6351 * @param[in] actions
6352 * Pointer to the list of actions.
6354 * Pointer to the error structure.
6357 * Pointer to mlx5_flow object on success,
6358 * otherwise NULL and rte_errno is set.
6360 static struct mlx5_flow *
6361 flow_dv_prepare(struct rte_eth_dev *dev,
6362 const struct rte_flow_attr *attr __rte_unused,
6363 const struct rte_flow_item items[] __rte_unused,
6364 const struct rte_flow_action actions[] __rte_unused,
6365 struct rte_flow_error *error)
6367 uint32_t handle_idx = 0;
6368 struct mlx5_flow *dev_flow;
6369 struct mlx5_flow_handle *dev_handle;
6370 struct mlx5_priv *priv = dev->data->dev_private;
6371 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6374 /* In case of corrupting the memory. */
6375 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6376 rte_flow_error_set(error, ENOSPC,
6377 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6378 "not free temporary device flow");
6381 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6384 rte_flow_error_set(error, ENOMEM,
6385 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6386 "not enough memory to create flow handle");
6389 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6390 dev_flow = &wks->flows[wks->flow_idx++];
6391 memset(dev_flow, 0, sizeof(*dev_flow));
6392 dev_flow->handle = dev_handle;
6393 dev_flow->handle_idx = handle_idx;
6395 * In some old rdma-core releases, before continuing, a check of the
6396 * length of matching parameter will be done at first. It needs to use
6397 * the length without misc4 param. If the flow has misc4 support, then
6398 * the length needs to be adjusted accordingly. Each param member is
6399 * aligned with a 64B boundary naturally.
6401 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6402 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6403 dev_flow->ingress = attr->ingress;
6404 dev_flow->dv.transfer = attr->transfer;
6408 #ifdef RTE_LIBRTE_MLX5_DEBUG
6410 * Sanity check for match mask and value. Similar to check_valid_spec() in
6411 * kernel driver. If unmasked bit is present in value, it returns failure.
6414 * pointer to match mask buffer.
6415 * @param match_value
6416 * pointer to match value buffer.
6419 * 0 if valid, -EINVAL otherwise.
6422 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6424 uint8_t *m = match_mask;
6425 uint8_t *v = match_value;
6428 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6431 "match_value differs from match_criteria"
6432 " %p[%u] != %p[%u]",
6433 match_value, i, match_mask, i);
6442 * Add match of ip_version.
6446 * @param[in] headers_v
6447 * Values header pointer.
6448 * @param[in] headers_m
6449 * Masks header pointer.
6450 * @param[in] ip_version
6451 * The IP version to set.
6454 flow_dv_set_match_ip_version(uint32_t group,
6460 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6462 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6464 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6465 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6466 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6470 * Add Ethernet item to matcher and to the value.
6472 * @param[in, out] matcher
6474 * @param[in, out] key
6475 * Flow matcher value.
6477 * Flow pattern to translate.
6479 * Item is inner pattern.
6482 flow_dv_translate_item_eth(void *matcher, void *key,
6483 const struct rte_flow_item *item, int inner,
6486 const struct rte_flow_item_eth *eth_m = item->mask;
6487 const struct rte_flow_item_eth *eth_v = item->spec;
6488 const struct rte_flow_item_eth nic_mask = {
6489 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6490 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6491 .type = RTE_BE16(0xffff),
6504 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6506 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6508 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6510 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6512 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6513 ð_m->dst, sizeof(eth_m->dst));
6514 /* The value must be in the range of the mask. */
6515 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6516 for (i = 0; i < sizeof(eth_m->dst); ++i)
6517 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6518 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6519 ð_m->src, sizeof(eth_m->src));
6520 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6521 /* The value must be in the range of the mask. */
6522 for (i = 0; i < sizeof(eth_m->dst); ++i)
6523 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6525 * HW supports match on one Ethertype, the Ethertype following the last
6526 * VLAN tag of the packet (see PRM).
6527 * Set match on ethertype only if ETH header is not followed by VLAN.
6528 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6529 * ethertype, and use ip_version field instead.
6530 * eCPRI over Ether layer will use type value 0xAEFE.
6532 if (eth_m->type == 0xFFFF) {
6533 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6534 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6535 switch (eth_v->type) {
6536 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6537 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6539 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6540 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6541 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6543 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6544 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6546 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6547 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6553 if (eth_m->has_vlan) {
6554 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6555 if (eth_v->has_vlan) {
6557 * Here, when also has_more_vlan field in VLAN item is
6558 * not set, only single-tagged packets will be matched.
6560 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6564 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6565 rte_be_to_cpu_16(eth_m->type));
6566 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6567 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6571 * Add VLAN item to matcher and to the value.
6573 * @param[in, out] dev_flow
6575 * @param[in, out] matcher
6577 * @param[in, out] key
6578 * Flow matcher value.
6580 * Flow pattern to translate.
6582 * Item is inner pattern.
6585 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6586 void *matcher, void *key,
6587 const struct rte_flow_item *item,
6588 int inner, uint32_t group)
6590 const struct rte_flow_item_vlan *vlan_m = item->mask;
6591 const struct rte_flow_item_vlan *vlan_v = item->spec;
6598 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6600 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6602 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6604 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6606 * This is workaround, masks are not supported,
6607 * and pre-validated.
6610 dev_flow->handle->vf_vlan.tag =
6611 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6614 * When VLAN item exists in flow, mark packet as tagged,
6615 * even if TCI is not specified.
6617 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6618 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6619 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6624 vlan_m = &rte_flow_item_vlan_mask;
6625 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6626 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6627 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6628 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6629 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6630 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6631 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6632 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6634 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6635 * ethertype, and use ip_version field instead.
6637 if (vlan_m->inner_type == 0xFFFF) {
6638 switch (vlan_v->inner_type) {
6639 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6640 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6641 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6642 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6644 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6645 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6647 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6648 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6654 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6655 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6656 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6657 /* Only one vlan_tag bit can be set. */
6658 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6661 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6662 rte_be_to_cpu_16(vlan_m->inner_type));
6663 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6664 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6668 * Add IPV4 item to matcher and to the value.
6670 * @param[in, out] matcher
6672 * @param[in, out] key
6673 * Flow matcher value.
6675 * Flow pattern to translate.
6677 * Item is inner pattern.
6679 * The group to insert the rule.
6682 flow_dv_translate_item_ipv4(void *matcher, void *key,
6683 const struct rte_flow_item *item,
6684 int inner, uint32_t group)
6686 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6687 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6688 const struct rte_flow_item_ipv4 nic_mask = {
6690 .src_addr = RTE_BE32(0xffffffff),
6691 .dst_addr = RTE_BE32(0xffffffff),
6692 .type_of_service = 0xff,
6693 .next_proto_id = 0xff,
6694 .time_to_live = 0xff,
6704 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6706 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6708 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6710 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6712 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6717 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6718 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6719 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6720 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6721 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6722 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6723 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6724 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6725 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6726 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6727 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6728 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6729 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6730 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6731 ipv4_m->hdr.type_of_service);
6732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6733 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6734 ipv4_m->hdr.type_of_service >> 2);
6735 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6736 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6737 ipv4_m->hdr.next_proto_id);
6738 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6739 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6740 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6741 ipv4_m->hdr.time_to_live);
6742 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6743 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6744 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6745 !!(ipv4_m->hdr.fragment_offset));
6746 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6747 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6751 * Add IPV6 item to matcher and to the value.
6753 * @param[in, out] matcher
6755 * @param[in, out] key
6756 * Flow matcher value.
6758 * Flow pattern to translate.
6760 * Item is inner pattern.
6762 * The group to insert the rule.
6765 flow_dv_translate_item_ipv6(void *matcher, void *key,
6766 const struct rte_flow_item *item,
6767 int inner, uint32_t group)
6769 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6770 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6771 const struct rte_flow_item_ipv6 nic_mask = {
6774 "\xff\xff\xff\xff\xff\xff\xff\xff"
6775 "\xff\xff\xff\xff\xff\xff\xff\xff",
6777 "\xff\xff\xff\xff\xff\xff\xff\xff"
6778 "\xff\xff\xff\xff\xff\xff\xff\xff",
6779 .vtc_flow = RTE_BE32(0xffffffff),
6786 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6787 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6796 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6798 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6800 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6802 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6804 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6809 size = sizeof(ipv6_m->hdr.dst_addr);
6810 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6811 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6812 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6813 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6814 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6815 for (i = 0; i < size; ++i)
6816 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6817 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6818 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6819 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6820 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6821 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6822 for (i = 0; i < size; ++i)
6823 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6825 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6826 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6827 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6828 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6829 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6830 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6833 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6835 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6838 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6840 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6844 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6846 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6847 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6849 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6850 ipv6_m->hdr.hop_limits);
6851 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6852 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6853 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6854 !!(ipv6_m->has_frag_ext));
6855 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6856 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6860 * Add IPV6 fragment extension item to matcher and to the value.
6862 * @param[in, out] matcher
6864 * @param[in, out] key
6865 * Flow matcher value.
6867 * Flow pattern to translate.
6869 * Item is inner pattern.
6872 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6873 const struct rte_flow_item *item,
6876 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6877 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6878 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6880 .next_header = 0xff,
6881 .frag_data = RTE_BE16(0xffff),
6888 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6890 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6892 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6894 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6896 /* IPv6 fragment extension item exists, so packet is IP fragment. */
6897 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6898 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6899 if (!ipv6_frag_ext_v)
6901 if (!ipv6_frag_ext_m)
6902 ipv6_frag_ext_m = &nic_mask;
6903 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6904 ipv6_frag_ext_m->hdr.next_header);
6905 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6906 ipv6_frag_ext_v->hdr.next_header &
6907 ipv6_frag_ext_m->hdr.next_header);
6911 * Add TCP item to matcher and to the value.
6913 * @param[in, out] matcher
6915 * @param[in, out] key
6916 * Flow matcher value.
6918 * Flow pattern to translate.
6920 * Item is inner pattern.
6923 flow_dv_translate_item_tcp(void *matcher, void *key,
6924 const struct rte_flow_item *item,
6927 const struct rte_flow_item_tcp *tcp_m = item->mask;
6928 const struct rte_flow_item_tcp *tcp_v = item->spec;
6933 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6935 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6937 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6939 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6941 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6942 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6946 tcp_m = &rte_flow_item_tcp_mask;
6947 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6948 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6949 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6950 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6951 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6952 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6953 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6954 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6955 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6956 tcp_m->hdr.tcp_flags);
6957 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6958 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6962 * Add UDP item to matcher and to the value.
6964 * @param[in, out] matcher
6966 * @param[in, out] key
6967 * Flow matcher value.
6969 * Flow pattern to translate.
6971 * Item is inner pattern.
6974 flow_dv_translate_item_udp(void *matcher, void *key,
6975 const struct rte_flow_item *item,
6978 const struct rte_flow_item_udp *udp_m = item->mask;
6979 const struct rte_flow_item_udp *udp_v = item->spec;
6984 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6986 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6988 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6990 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6992 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6993 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6997 udp_m = &rte_flow_item_udp_mask;
6998 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6999 rte_be_to_cpu_16(udp_m->hdr.src_port));
7000 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7001 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7002 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7003 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7004 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7005 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7009 * Add GRE optional Key item to matcher and to the value.
7011 * @param[in, out] matcher
7013 * @param[in, out] key
7014 * Flow matcher value.
7016 * Flow pattern to translate.
7018 * Item is inner pattern.
7021 flow_dv_translate_item_gre_key(void *matcher, void *key,
7022 const struct rte_flow_item *item)
7024 const rte_be32_t *key_m = item->mask;
7025 const rte_be32_t *key_v = item->spec;
7026 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7027 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7028 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7030 /* GRE K bit must be on and should already be validated */
7031 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7032 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7036 key_m = &gre_key_default_mask;
7037 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7038 rte_be_to_cpu_32(*key_m) >> 8);
7039 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7040 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7041 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7042 rte_be_to_cpu_32(*key_m) & 0xFF);
7043 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7044 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7048 * Add GRE item to matcher and to the value.
7050 * @param[in, out] matcher
7052 * @param[in, out] key
7053 * Flow matcher value.
7055 * Flow pattern to translate.
7057 * Item is inner pattern.
7060 flow_dv_translate_item_gre(void *matcher, void *key,
7061 const struct rte_flow_item *item,
7064 const struct rte_flow_item_gre *gre_m = item->mask;
7065 const struct rte_flow_item_gre *gre_v = item->spec;
7068 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7069 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7076 uint16_t s_present:1;
7077 uint16_t k_present:1;
7078 uint16_t rsvd_bit1:1;
7079 uint16_t c_present:1;
7083 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7086 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7088 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7090 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7092 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7094 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7095 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7099 gre_m = &rte_flow_item_gre_mask;
7100 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7101 rte_be_to_cpu_16(gre_m->protocol));
7102 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7103 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7104 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7105 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7106 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7107 gre_crks_rsvd0_ver_m.c_present);
7108 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7109 gre_crks_rsvd0_ver_v.c_present &
7110 gre_crks_rsvd0_ver_m.c_present);
7111 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7112 gre_crks_rsvd0_ver_m.k_present);
7113 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7114 gre_crks_rsvd0_ver_v.k_present &
7115 gre_crks_rsvd0_ver_m.k_present);
7116 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7117 gre_crks_rsvd0_ver_m.s_present);
7118 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7119 gre_crks_rsvd0_ver_v.s_present &
7120 gre_crks_rsvd0_ver_m.s_present);
7124 * Add NVGRE item to matcher and to the value.
7126 * @param[in, out] matcher
7128 * @param[in, out] key
7129 * Flow matcher value.
7131 * Flow pattern to translate.
7133 * Item is inner pattern.
7136 flow_dv_translate_item_nvgre(void *matcher, void *key,
7137 const struct rte_flow_item *item,
7140 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7141 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7142 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7143 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7144 const char *tni_flow_id_m;
7145 const char *tni_flow_id_v;
7151 /* For NVGRE, GRE header fields must be set with defined values. */
7152 const struct rte_flow_item_gre gre_spec = {
7153 .c_rsvd0_ver = RTE_BE16(0x2000),
7154 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7156 const struct rte_flow_item_gre gre_mask = {
7157 .c_rsvd0_ver = RTE_BE16(0xB000),
7158 .protocol = RTE_BE16(UINT16_MAX),
7160 const struct rte_flow_item gre_item = {
7165 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7169 nvgre_m = &rte_flow_item_nvgre_mask;
7170 tni_flow_id_m = (const char *)nvgre_m->tni;
7171 tni_flow_id_v = (const char *)nvgre_v->tni;
7172 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7173 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7174 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7175 memcpy(gre_key_m, tni_flow_id_m, size);
7176 for (i = 0; i < size; ++i)
7177 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7181 * Add VXLAN item to matcher and to the value.
7183 * @param[in, out] matcher
7185 * @param[in, out] key
7186 * Flow matcher value.
7188 * Flow pattern to translate.
7190 * Item is inner pattern.
7193 flow_dv_translate_item_vxlan(void *matcher, void *key,
7194 const struct rte_flow_item *item,
7197 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7198 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7201 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7202 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7210 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7212 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7214 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7216 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7218 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7219 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7220 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7221 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7222 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7227 vxlan_m = &rte_flow_item_vxlan_mask;
7228 size = sizeof(vxlan_m->vni);
7229 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7230 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7231 memcpy(vni_m, vxlan_m->vni, size);
7232 for (i = 0; i < size; ++i)
7233 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7237 * Add VXLAN-GPE item to matcher and to the value.
7239 * @param[in, out] matcher
7241 * @param[in, out] key
7242 * Flow matcher value.
7244 * Flow pattern to translate.
7246 * Item is inner pattern.
7250 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7251 const struct rte_flow_item *item, int inner)
7253 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7254 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7258 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7260 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7266 uint8_t flags_m = 0xff;
7267 uint8_t flags_v = 0xc;
7270 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7272 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7274 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7276 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7278 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7279 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7280 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7281 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7287 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7288 size = sizeof(vxlan_m->vni);
7289 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7290 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7291 memcpy(vni_m, vxlan_m->vni, size);
7292 for (i = 0; i < size; ++i)
7293 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7294 if (vxlan_m->flags) {
7295 flags_m = vxlan_m->flags;
7296 flags_v = vxlan_v->flags;
7298 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7299 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7300 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7302 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7307 * Add Geneve item to matcher and to the value.
7309 * @param[in, out] matcher
7311 * @param[in, out] key
7312 * Flow matcher value.
7314 * Flow pattern to translate.
7316 * Item is inner pattern.
7320 flow_dv_translate_item_geneve(void *matcher, void *key,
7321 const struct rte_flow_item *item, int inner)
7323 const struct rte_flow_item_geneve *geneve_m = item->mask;
7324 const struct rte_flow_item_geneve *geneve_v = item->spec;
7327 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7328 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7337 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7339 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7341 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7343 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7345 dport = MLX5_UDP_PORT_GENEVE;
7346 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7347 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7348 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7353 geneve_m = &rte_flow_item_geneve_mask;
7354 size = sizeof(geneve_m->vni);
7355 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7356 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7357 memcpy(vni_m, geneve_m->vni, size);
7358 for (i = 0; i < size; ++i)
7359 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7360 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7361 rte_be_to_cpu_16(geneve_m->protocol));
7362 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7363 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7364 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7365 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7366 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7367 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7368 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7369 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7370 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7371 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7372 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7373 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7374 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7378 * Create Geneve TLV option resource.
7380 * @param dev[in, out]
7381 * Pointer to rte_eth_dev structure.
7382 * @param[in, out] tag_be24
7383 * Tag value in big endian then R-shift 8.
7384 * @parm[in, out] dev_flow
7385 * Pointer to the dev_flow.
7387 * pointer to error structure.
7390 * 0 on success otherwise -errno and errno is set.
7394 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7395 const struct rte_flow_item *item,
7396 struct rte_flow_error *error)
7398 struct mlx5_priv *priv = dev->data->dev_private;
7399 struct mlx5_dev_ctx_shared *sh = priv->sh;
7400 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7401 sh->geneve_tlv_option_resource;
7402 struct mlx5_devx_obj *obj;
7403 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7408 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7409 if (geneve_opt_resource != NULL) {
7410 if (geneve_opt_resource->option_class ==
7411 geneve_opt_v->option_class &&
7412 geneve_opt_resource->option_type ==
7413 geneve_opt_v->option_type &&
7414 geneve_opt_resource->length ==
7415 geneve_opt_v->option_len) {
7416 /* We already have GENVE TLV option obj allocated. */
7417 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7420 ret = rte_flow_error_set(error, ENOMEM,
7421 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7422 "Only one GENEVE TLV option supported");
7426 /* Create a GENEVE TLV object and resource. */
7427 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7428 geneve_opt_v->option_class,
7429 geneve_opt_v->option_type,
7430 geneve_opt_v->option_len);
7432 ret = rte_flow_error_set(error, ENODATA,
7433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7434 "Failed to create GENEVE TLV Devx object");
7437 sh->geneve_tlv_option_resource =
7438 mlx5_malloc(MLX5_MEM_ZERO,
7439 sizeof(*geneve_opt_resource),
7441 if (!sh->geneve_tlv_option_resource) {
7442 claim_zero(mlx5_devx_cmd_destroy(obj));
7443 ret = rte_flow_error_set(error, ENOMEM,
7444 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7445 "GENEVE TLV object memory allocation failed");
7448 geneve_opt_resource = sh->geneve_tlv_option_resource;
7449 geneve_opt_resource->obj = obj;
7450 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7451 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7452 geneve_opt_resource->length = geneve_opt_v->option_len;
7453 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7457 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7462 * Add Geneve TLV option item to matcher.
7464 * @param[in, out] dev
7465 * Pointer to rte_eth_dev structure.
7466 * @param[in, out] matcher
7468 * @param[in, out] key
7469 * Flow matcher value.
7471 * Flow pattern to translate.
7473 * Pointer to error structure.
7476 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
7477 void *key, const struct rte_flow_item *item,
7478 struct rte_flow_error *error)
7480 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
7481 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7482 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7483 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7484 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7486 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7487 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
7493 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
7494 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
7497 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
7501 * Set the option length in GENEVE header if not requested.
7502 * The GENEVE TLV option length is expressed by the option length field
7503 * in the GENEVE header.
7504 * If the option length was not requested but the GENEVE TLV option item
7505 * is present we set the option length field implicitly.
7507 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
7508 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7509 MLX5_GENEVE_OPTLEN_MASK);
7510 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7511 geneve_opt_v->option_len + 1);
7514 if (geneve_opt_v->data) {
7515 memcpy(&opt_data_key, geneve_opt_v->data,
7516 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7517 sizeof(opt_data_key)));
7518 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7519 sizeof(opt_data_key));
7520 memcpy(&opt_data_mask, geneve_opt_m->data,
7521 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7522 sizeof(opt_data_mask)));
7523 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7524 sizeof(opt_data_mask));
7525 MLX5_SET(fte_match_set_misc3, misc3_m,
7526 geneve_tlv_option_0_data,
7527 rte_be_to_cpu_32(opt_data_mask));
7528 MLX5_SET(fte_match_set_misc3, misc3_v,
7529 geneve_tlv_option_0_data,
7530 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
7536 * Add MPLS item to matcher and to the value.
7538 * @param[in, out] matcher
7540 * @param[in, out] key
7541 * Flow matcher value.
7543 * Flow pattern to translate.
7544 * @param[in] prev_layer
7545 * The protocol layer indicated in previous item.
7547 * Item is inner pattern.
7550 flow_dv_translate_item_mpls(void *matcher, void *key,
7551 const struct rte_flow_item *item,
7552 uint64_t prev_layer,
7555 const uint32_t *in_mpls_m = item->mask;
7556 const uint32_t *in_mpls_v = item->spec;
7557 uint32_t *out_mpls_m = 0;
7558 uint32_t *out_mpls_v = 0;
7559 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7560 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7561 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7563 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7564 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7565 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7567 switch (prev_layer) {
7568 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7569 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7570 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7571 MLX5_UDP_PORT_MPLS);
7573 case MLX5_FLOW_LAYER_GRE:
7574 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7575 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7576 RTE_ETHER_TYPE_MPLS);
7579 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7580 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7587 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7588 switch (prev_layer) {
7589 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7591 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7592 outer_first_mpls_over_udp);
7594 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7595 outer_first_mpls_over_udp);
7597 case MLX5_FLOW_LAYER_GRE:
7599 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7600 outer_first_mpls_over_gre);
7602 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7603 outer_first_mpls_over_gre);
7606 /* Inner MPLS not over GRE is not supported. */
7609 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7613 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7619 if (out_mpls_m && out_mpls_v) {
7620 *out_mpls_m = *in_mpls_m;
7621 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7626 * Add metadata register item to matcher
7628 * @param[in, out] matcher
7630 * @param[in, out] key
7631 * Flow matcher value.
7632 * @param[in] reg_type
7633 * Type of device metadata register
7640 flow_dv_match_meta_reg(void *matcher, void *key,
7641 enum modify_reg reg_type,
7642 uint32_t data, uint32_t mask)
7645 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7647 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7653 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7654 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7657 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7658 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7662 * The metadata register C0 field might be divided into
7663 * source vport index and META item value, we should set
7664 * this field according to specified mask, not as whole one.
7666 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7668 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7669 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7672 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7675 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7676 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7679 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7680 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7683 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7684 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7687 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7688 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7691 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7692 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7695 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7696 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7699 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7700 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7709 * Add MARK item to matcher
7712 * The device to configure through.
7713 * @param[in, out] matcher
7715 * @param[in, out] key
7716 * Flow matcher value.
7718 * Flow pattern to translate.
7721 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7722 void *matcher, void *key,
7723 const struct rte_flow_item *item)
7725 struct mlx5_priv *priv = dev->data->dev_private;
7726 const struct rte_flow_item_mark *mark;
7730 mark = item->mask ? (const void *)item->mask :
7731 &rte_flow_item_mark_mask;
7732 mask = mark->id & priv->sh->dv_mark_mask;
7733 mark = (const void *)item->spec;
7735 value = mark->id & priv->sh->dv_mark_mask & mask;
7737 enum modify_reg reg;
7739 /* Get the metadata register index for the mark. */
7740 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7741 MLX5_ASSERT(reg > 0);
7742 if (reg == REG_C_0) {
7743 struct mlx5_priv *priv = dev->data->dev_private;
7744 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7745 uint32_t shl_c0 = rte_bsf32(msk_c0);
7751 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7756 * Add META item to matcher
7759 * The devich to configure through.
7760 * @param[in, out] matcher
7762 * @param[in, out] key
7763 * Flow matcher value.
7765 * Attributes of flow that includes this item.
7767 * Flow pattern to translate.
7770 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7771 void *matcher, void *key,
7772 const struct rte_flow_attr *attr,
7773 const struct rte_flow_item *item)
7775 const struct rte_flow_item_meta *meta_m;
7776 const struct rte_flow_item_meta *meta_v;
7778 meta_m = (const void *)item->mask;
7780 meta_m = &rte_flow_item_meta_mask;
7781 meta_v = (const void *)item->spec;
7784 uint32_t value = meta_v->data;
7785 uint32_t mask = meta_m->data;
7787 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7790 MLX5_ASSERT(reg != REG_NON);
7792 * In datapath code there is no endianness
7793 * coversions for perfromance reasons, all
7794 * pattern conversions are done in rte_flow.
7796 value = rte_cpu_to_be_32(value);
7797 mask = rte_cpu_to_be_32(mask);
7798 if (reg == REG_C_0) {
7799 struct mlx5_priv *priv = dev->data->dev_private;
7800 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7801 uint32_t shl_c0 = rte_bsf32(msk_c0);
7802 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7803 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7810 MLX5_ASSERT(msk_c0);
7811 MLX5_ASSERT(!(~msk_c0 & mask));
7813 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7818 * Add vport metadata Reg C0 item to matcher
7820 * @param[in, out] matcher
7822 * @param[in, out] key
7823 * Flow matcher value.
7825 * Flow pattern to translate.
7828 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7829 uint32_t value, uint32_t mask)
7831 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7835 * Add tag item to matcher
7838 * The devich to configure through.
7839 * @param[in, out] matcher
7841 * @param[in, out] key
7842 * Flow matcher value.
7844 * Flow pattern to translate.
7847 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7848 void *matcher, void *key,
7849 const struct rte_flow_item *item)
7851 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7852 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7853 uint32_t mask, value;
7856 value = tag_v->data;
7857 mask = tag_m ? tag_m->data : UINT32_MAX;
7858 if (tag_v->id == REG_C_0) {
7859 struct mlx5_priv *priv = dev->data->dev_private;
7860 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7861 uint32_t shl_c0 = rte_bsf32(msk_c0);
7867 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7871 * Add TAG item to matcher
7874 * The devich to configure through.
7875 * @param[in, out] matcher
7877 * @param[in, out] key
7878 * Flow matcher value.
7880 * Flow pattern to translate.
7883 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7884 void *matcher, void *key,
7885 const struct rte_flow_item *item)
7887 const struct rte_flow_item_tag *tag_v = item->spec;
7888 const struct rte_flow_item_tag *tag_m = item->mask;
7889 enum modify_reg reg;
7892 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7893 /* Get the metadata register index for the tag. */
7894 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7895 MLX5_ASSERT(reg > 0);
7896 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7900 * Add source vport match to the specified matcher.
7902 * @param[in, out] matcher
7904 * @param[in, out] key
7905 * Flow matcher value.
7907 * Source vport value to match
7912 flow_dv_translate_item_source_vport(void *matcher, void *key,
7913 int16_t port, uint16_t mask)
7915 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7916 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7918 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7919 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7923 * Translate port-id item to eswitch match on port-id.
7926 * The devich to configure through.
7927 * @param[in, out] matcher
7929 * @param[in, out] key
7930 * Flow matcher value.
7932 * Flow pattern to translate.
7937 * 0 on success, a negative errno value otherwise.
7940 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7941 void *key, const struct rte_flow_item *item,
7942 const struct rte_flow_attr *attr)
7944 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7945 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7946 struct mlx5_priv *priv;
7949 mask = pid_m ? pid_m->id : 0xffff;
7950 id = pid_v ? pid_v->id : dev->data->port_id;
7951 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7955 * Translate to vport field or to metadata, depending on mode.
7956 * Kernel can use either misc.source_port or half of C0 metadata
7959 if (priv->vport_meta_mask) {
7961 * Provide the hint for SW steering library
7962 * to insert the flow into ingress domain and
7963 * save the extra vport match.
7965 if (mask == 0xffff && priv->vport_id == 0xffff &&
7966 priv->pf_bond < 0 && attr->transfer)
7967 flow_dv_translate_item_source_vport
7968 (matcher, key, priv->vport_id, mask);
7970 flow_dv_translate_item_meta_vport
7972 priv->vport_meta_tag,
7973 priv->vport_meta_mask);
7975 flow_dv_translate_item_source_vport(matcher, key,
7976 priv->vport_id, mask);
7982 * Add ICMP6 item to matcher and to the value.
7984 * @param[in, out] matcher
7986 * @param[in, out] key
7987 * Flow matcher value.
7989 * Flow pattern to translate.
7991 * Item is inner pattern.
7994 flow_dv_translate_item_icmp6(void *matcher, void *key,
7995 const struct rte_flow_item *item,
7998 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7999 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8002 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8004 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8006 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8008 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8010 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8012 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8014 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8015 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8019 icmp6_m = &rte_flow_item_icmp6_mask;
8020 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8021 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8022 icmp6_v->type & icmp6_m->type);
8023 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8024 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8025 icmp6_v->code & icmp6_m->code);
8029 * Add ICMP item to matcher and to the value.
8031 * @param[in, out] matcher
8033 * @param[in, out] key
8034 * Flow matcher value.
8036 * Flow pattern to translate.
8038 * Item is inner pattern.
8041 flow_dv_translate_item_icmp(void *matcher, void *key,
8042 const struct rte_flow_item *item,
8045 const struct rte_flow_item_icmp *icmp_m = item->mask;
8046 const struct rte_flow_item_icmp *icmp_v = item->spec;
8047 uint32_t icmp_header_data_m = 0;
8048 uint32_t icmp_header_data_v = 0;
8051 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8053 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8055 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8057 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8059 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8061 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8063 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8064 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8068 icmp_m = &rte_flow_item_icmp_mask;
8069 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8070 icmp_m->hdr.icmp_type);
8071 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8072 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8073 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8074 icmp_m->hdr.icmp_code);
8075 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8076 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8077 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8078 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8079 if (icmp_header_data_m) {
8080 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8081 icmp_header_data_v |=
8082 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8083 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8084 icmp_header_data_m);
8085 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8086 icmp_header_data_v & icmp_header_data_m);
8091 * Add GTP item to matcher and to the value.
8093 * @param[in, out] matcher
8095 * @param[in, out] key
8096 * Flow matcher value.
8098 * Flow pattern to translate.
8100 * Item is inner pattern.
8103 flow_dv_translate_item_gtp(void *matcher, void *key,
8104 const struct rte_flow_item *item, int inner)
8106 const struct rte_flow_item_gtp *gtp_m = item->mask;
8107 const struct rte_flow_item_gtp *gtp_v = item->spec;
8110 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8112 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8113 uint16_t dport = RTE_GTPU_UDP_PORT;
8116 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8118 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8120 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8122 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8124 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8125 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8126 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8131 gtp_m = &rte_flow_item_gtp_mask;
8132 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8133 gtp_m->v_pt_rsv_flags);
8134 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8135 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8136 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8137 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8138 gtp_v->msg_type & gtp_m->msg_type);
8139 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8140 rte_be_to_cpu_32(gtp_m->teid));
8141 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8142 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8146 * Add GTP PSC item to matcher.
8148 * @param[in, out] matcher
8150 * @param[in, out] key
8151 * Flow matcher value.
8153 * Flow pattern to translate.
8156 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8157 const struct rte_flow_item *item)
8159 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8160 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8161 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8163 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8169 uint8_t next_ext_header_type;
8174 /* Always set E-flag match on one, regardless of GTP item settings. */
8175 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8176 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8177 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8178 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8179 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8180 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8181 /*Set next extension header type. */
8184 dw_2.next_ext_header_type = 0xff;
8185 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8186 rte_cpu_to_be_32(dw_2.w32));
8189 dw_2.next_ext_header_type = 0x85;
8190 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8191 rte_cpu_to_be_32(dw_2.w32));
8203 /*Set extension header PDU type and Qos. */
8205 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8207 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8208 dw_0.qfi = gtp_psc_m->qfi;
8209 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8210 rte_cpu_to_be_32(dw_0.w32));
8212 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8213 gtp_psc_m->pdu_type);
8214 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8215 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8216 rte_cpu_to_be_32(dw_0.w32));
8222 * Add eCPRI item to matcher and to the value.
8225 * The devich to configure through.
8226 * @param[in, out] matcher
8228 * @param[in, out] key
8229 * Flow matcher value.
8231 * Flow pattern to translate.
8232 * @param[in] samples
8233 * Sample IDs to be used in the matching.
8236 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8237 void *key, const struct rte_flow_item *item)
8239 struct mlx5_priv *priv = dev->data->dev_private;
8240 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8241 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8242 struct rte_ecpri_common_hdr common;
8243 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8245 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8253 ecpri_m = &rte_flow_item_ecpri_mask;
8255 * Maximal four DW samples are supported in a single matching now.
8256 * Two are used now for a eCPRI matching:
8257 * 1. Type: one byte, mask should be 0x00ff0000 in network order
8258 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8261 if (!ecpri_m->hdr.common.u32)
8263 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8264 /* Need to take the whole DW as the mask to fill the entry. */
8265 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8266 prog_sample_field_value_0);
8267 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8268 prog_sample_field_value_0);
8269 /* Already big endian (network order) in the header. */
8270 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8271 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8272 /* Sample#0, used for matching type, offset 0. */
8273 MLX5_SET(fte_match_set_misc4, misc4_m,
8274 prog_sample_field_id_0, samples[0]);
8275 /* It makes no sense to set the sample ID in the mask field. */
8276 MLX5_SET(fte_match_set_misc4, misc4_v,
8277 prog_sample_field_id_0, samples[0]);
8279 * Checking if message body part needs to be matched.
8280 * Some wildcard rules only matching type field should be supported.
8282 if (ecpri_m->hdr.dummy[0]) {
8283 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8284 switch (common.type) {
8285 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8286 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8287 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8288 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8289 prog_sample_field_value_1);
8290 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8291 prog_sample_field_value_1);
8292 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8293 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8294 ecpri_m->hdr.dummy[0];
8295 /* Sample#1, to match message body, offset 4. */
8296 MLX5_SET(fte_match_set_misc4, misc4_m,
8297 prog_sample_field_id_1, samples[1]);
8298 MLX5_SET(fte_match_set_misc4, misc4_v,
8299 prog_sample_field_id_1, samples[1]);
8302 /* Others, do not match any sample ID. */
8308 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8310 #define HEADER_IS_ZERO(match_criteria, headers) \
8311 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
8312 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8315 * Calculate flow matcher enable bitmap.
8317 * @param match_criteria
8318 * Pointer to flow matcher criteria.
8321 * Bitmap of enabled fields.
8324 flow_dv_matcher_enable(uint32_t *match_criteria)
8326 uint8_t match_criteria_enable;
8328 match_criteria_enable =
8329 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8330 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8331 match_criteria_enable |=
8332 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8333 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8334 match_criteria_enable |=
8335 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8336 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8337 match_criteria_enable |=
8338 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8339 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8340 match_criteria_enable |=
8341 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8342 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8343 match_criteria_enable |=
8344 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8345 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8346 return match_criteria_enable;
8349 struct mlx5_hlist_entry *
8350 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8352 struct mlx5_dev_ctx_shared *sh = list->ctx;
8353 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8354 struct rte_eth_dev *dev = ctx->dev;
8355 struct mlx5_flow_tbl_data_entry *tbl_data;
8356 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8357 struct rte_flow_error *error = ctx->error;
8358 union mlx5_flow_tbl_key key = { .v64 = key64 };
8359 struct mlx5_flow_tbl_resource *tbl;
8364 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8366 rte_flow_error_set(error, ENOMEM,
8367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8369 "cannot allocate flow table data entry");
8372 tbl_data->idx = idx;
8373 tbl_data->tunnel = tt_prm->tunnel;
8374 tbl_data->group_id = tt_prm->group_id;
8375 tbl_data->external = !!tt_prm->external;
8376 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8377 tbl_data->is_egress = !!key.direction;
8378 tbl_data->is_transfer = !!key.domain;
8379 tbl_data->dummy = !!key.dummy;
8380 tbl_data->table_id = key.table_id;
8381 tbl = &tbl_data->tbl;
8383 return &tbl_data->entry;
8385 domain = sh->fdb_domain;
8386 else if (key.direction)
8387 domain = sh->tx_domain;
8389 domain = sh->rx_domain;
8390 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8392 rte_flow_error_set(error, ENOMEM,
8393 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8394 NULL, "cannot create flow table object");
8395 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8399 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8400 (tbl->obj, &tbl_data->jump.action);
8402 rte_flow_error_set(error, ENOMEM,
8403 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8405 "cannot create flow jump action");
8406 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8407 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8411 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8412 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8414 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8415 flow_dv_matcher_create_cb,
8416 flow_dv_matcher_match_cb,
8417 flow_dv_matcher_remove_cb);
8418 return &tbl_data->entry;
8422 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8423 struct mlx5_hlist_entry *entry, uint64_t key64,
8424 void *cb_ctx __rte_unused)
8426 struct mlx5_flow_tbl_data_entry *tbl_data =
8427 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8428 union mlx5_flow_tbl_key key = { .v64 = key64 };
8430 return tbl_data->table_id != key.table_id ||
8431 tbl_data->dummy != key.dummy ||
8432 tbl_data->is_transfer != key.domain ||
8433 tbl_data->is_egress != key.direction;
8439 * @param[in, out] dev
8440 * Pointer to rte_eth_dev structure.
8441 * @param[in] table_id
8444 * Direction of the table.
8445 * @param[in] transfer
8446 * E-Switch or NIC flow.
8448 * Dummy entry for dv API.
8450 * pointer to error structure.
8453 * Returns tables resource based on the index, NULL in case of failed.
8455 struct mlx5_flow_tbl_resource *
8456 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8457 uint32_t table_id, uint8_t egress,
8460 const struct mlx5_flow_tunnel *tunnel,
8461 uint32_t group_id, uint8_t dummy,
8462 struct rte_flow_error *error)
8464 struct mlx5_priv *priv = dev->data->dev_private;
8465 union mlx5_flow_tbl_key table_key = {
8467 .table_id = table_id,
8469 .domain = !!transfer,
8470 .direction = !!egress,
8473 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8475 .group_id = group_id,
8476 .external = external,
8478 struct mlx5_flow_cb_ctx ctx = {
8483 struct mlx5_hlist_entry *entry;
8484 struct mlx5_flow_tbl_data_entry *tbl_data;
8486 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8488 rte_flow_error_set(error, ENOMEM,
8489 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8490 "cannot get table");
8493 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8494 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8495 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8496 return &tbl_data->tbl;
8500 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8501 struct mlx5_hlist_entry *entry)
8503 struct mlx5_dev_ctx_shared *sh = list->ctx;
8504 struct mlx5_flow_tbl_data_entry *tbl_data =
8505 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8507 MLX5_ASSERT(entry && sh);
8508 if (tbl_data->jump.action)
8509 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8510 if (tbl_data->tbl.obj)
8511 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8512 if (tbl_data->tunnel_offload && tbl_data->external) {
8513 struct mlx5_hlist_entry *he;
8514 struct mlx5_hlist *tunnel_grp_hash;
8515 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8516 union tunnel_tbl_key tunnel_key = {
8517 .tunnel_id = tbl_data->tunnel ?
8518 tbl_data->tunnel->tunnel_id : 0,
8519 .group = tbl_data->group_id
8521 uint32_t table_id = tbl_data->table_id;
8523 tunnel_grp_hash = tbl_data->tunnel ?
8524 tbl_data->tunnel->groups :
8526 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8528 mlx5_hlist_unregister(tunnel_grp_hash, he);
8530 "Table_id %u tunnel %u group %u released.",
8533 tbl_data->tunnel->tunnel_id : 0,
8534 tbl_data->group_id);
8536 mlx5_cache_list_destroy(&tbl_data->matchers);
8537 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8541 * Release a flow table.
8544 * Pointer to device shared structure.
8546 * Table resource to be released.
8549 * Returns 0 if table was released, else return 1;
8552 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8553 struct mlx5_flow_tbl_resource *tbl)
8555 struct mlx5_flow_tbl_data_entry *tbl_data =
8556 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8560 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8564 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8565 struct mlx5_cache_entry *entry, void *cb_ctx)
8567 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8568 struct mlx5_flow_dv_matcher *ref = ctx->data;
8569 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8572 return cur->crc != ref->crc ||
8573 cur->priority != ref->priority ||
8574 memcmp((const void *)cur->mask.buf,
8575 (const void *)ref->mask.buf, ref->mask.size);
8578 struct mlx5_cache_entry *
8579 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8580 struct mlx5_cache_entry *entry __rte_unused,
8583 struct mlx5_dev_ctx_shared *sh = list->ctx;
8584 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8585 struct mlx5_flow_dv_matcher *ref = ctx->data;
8586 struct mlx5_flow_dv_matcher *cache;
8587 struct mlx5dv_flow_matcher_attr dv_attr = {
8588 .type = IBV_FLOW_ATTR_NORMAL,
8589 .match_mask = (void *)&ref->mask,
8591 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8595 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8597 rte_flow_error_set(ctx->error, ENOMEM,
8598 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8599 "cannot create matcher");
8603 dv_attr.match_criteria_enable =
8604 flow_dv_matcher_enable(cache->mask.buf);
8605 dv_attr.priority = ref->priority;
8607 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8608 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8609 &cache->matcher_object);
8612 rte_flow_error_set(ctx->error, ENOMEM,
8613 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8614 "cannot create matcher");
8617 return &cache->entry;
8621 * Register the flow matcher.
8623 * @param[in, out] dev
8624 * Pointer to rte_eth_dev structure.
8625 * @param[in, out] matcher
8626 * Pointer to flow matcher.
8627 * @param[in, out] key
8628 * Pointer to flow table key.
8629 * @parm[in, out] dev_flow
8630 * Pointer to the dev_flow.
8632 * pointer to error structure.
8635 * 0 on success otherwise -errno and errno is set.
8638 flow_dv_matcher_register(struct rte_eth_dev *dev,
8639 struct mlx5_flow_dv_matcher *ref,
8640 union mlx5_flow_tbl_key *key,
8641 struct mlx5_flow *dev_flow,
8642 const struct mlx5_flow_tunnel *tunnel,
8644 struct rte_flow_error *error)
8646 struct mlx5_cache_entry *entry;
8647 struct mlx5_flow_dv_matcher *cache;
8648 struct mlx5_flow_tbl_resource *tbl;
8649 struct mlx5_flow_tbl_data_entry *tbl_data;
8650 struct mlx5_flow_cb_ctx ctx = {
8656 * tunnel offload API requires this registration for cases when
8657 * tunnel match rule was inserted before tunnel set rule.
8659 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8660 key->direction, key->domain,
8661 dev_flow->external, tunnel,
8662 group_id, 0, error);
8664 return -rte_errno; /* No need to refill the error info */
8665 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8667 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8669 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8670 return rte_flow_error_set(error, ENOMEM,
8671 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8672 "cannot allocate ref memory");
8674 cache = container_of(entry, typeof(*cache), entry);
8675 dev_flow->handle->dvh.matcher = cache;
8679 struct mlx5_hlist_entry *
8680 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8682 struct mlx5_dev_ctx_shared *sh = list->ctx;
8683 struct rte_flow_error *error = ctx;
8684 struct mlx5_flow_dv_tag_resource *entry;
8688 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8690 rte_flow_error_set(error, ENOMEM,
8691 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8692 "cannot allocate resource memory");
8696 entry->tag_id = key;
8697 ret = mlx5_flow_os_create_flow_action_tag(key,
8700 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8701 rte_flow_error_set(error, ENOMEM,
8702 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8703 NULL, "cannot create action");
8706 return &entry->entry;
8710 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8711 struct mlx5_hlist_entry *entry, uint64_t key,
8712 void *cb_ctx __rte_unused)
8714 struct mlx5_flow_dv_tag_resource *tag =
8715 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8717 return key != tag->tag_id;
8721 * Find existing tag resource or create and register a new one.
8723 * @param dev[in, out]
8724 * Pointer to rte_eth_dev structure.
8725 * @param[in, out] tag_be24
8726 * Tag value in big endian then R-shift 8.
8727 * @parm[in, out] dev_flow
8728 * Pointer to the dev_flow.
8730 * pointer to error structure.
8733 * 0 on success otherwise -errno and errno is set.
8736 flow_dv_tag_resource_register
8737 (struct rte_eth_dev *dev,
8739 struct mlx5_flow *dev_flow,
8740 struct rte_flow_error *error)
8742 struct mlx5_priv *priv = dev->data->dev_private;
8743 struct mlx5_flow_dv_tag_resource *cache_resource;
8744 struct mlx5_hlist_entry *entry;
8746 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8748 cache_resource = container_of
8749 (entry, struct mlx5_flow_dv_tag_resource, entry);
8750 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8751 dev_flow->dv.tag_resource = cache_resource;
8758 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8759 struct mlx5_hlist_entry *entry)
8761 struct mlx5_dev_ctx_shared *sh = list->ctx;
8762 struct mlx5_flow_dv_tag_resource *tag =
8763 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8765 MLX5_ASSERT(tag && sh && tag->action);
8766 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8767 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8768 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8775 * Pointer to Ethernet device.
8780 * 1 while a reference on it exists, 0 when freed.
8783 flow_dv_tag_release(struct rte_eth_dev *dev,
8786 struct mlx5_priv *priv = dev->data->dev_private;
8787 struct mlx5_flow_dv_tag_resource *tag;
8789 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8792 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8793 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8794 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8798 * Translate port ID action to vport.
8801 * Pointer to rte_eth_dev structure.
8803 * Pointer to the port ID action.
8804 * @param[out] dst_port_id
8805 * The target port ID.
8807 * Pointer to the error structure.
8810 * 0 on success, a negative errno value otherwise and rte_errno is set.
8813 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8814 const struct rte_flow_action *action,
8815 uint32_t *dst_port_id,
8816 struct rte_flow_error *error)
8819 struct mlx5_priv *priv;
8820 const struct rte_flow_action_port_id *conf =
8821 (const struct rte_flow_action_port_id *)action->conf;
8823 port = conf->original ? dev->data->port_id : conf->id;
8824 priv = mlx5_port_to_eswitch_info(port, false);
8826 return rte_flow_error_set(error, -rte_errno,
8827 RTE_FLOW_ERROR_TYPE_ACTION,
8829 "No eswitch info was found for port");
8830 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8832 * This parameter is transferred to
8833 * mlx5dv_dr_action_create_dest_ib_port().
8835 *dst_port_id = priv->dev_port;
8838 * Legacy mode, no LAG configurations is supported.
8839 * This parameter is transferred to
8840 * mlx5dv_dr_action_create_dest_vport().
8842 *dst_port_id = priv->vport_id;
8848 * Create a counter with aging configuration.
8851 * Pointer to rte_eth_dev structure.
8853 * Pointer to the counter action configuration.
8855 * Pointer to the aging action configuration.
8858 * Index to flow counter on success, 0 otherwise.
8861 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8862 struct mlx5_flow *dev_flow,
8863 const struct rte_flow_action_count *count,
8864 const struct rte_flow_action_age *age)
8867 struct mlx5_age_param *age_param;
8869 if (count && count->shared)
8870 counter = flow_dv_counter_get_shared(dev, count->id);
8872 counter = flow_dv_counter_alloc(dev, !!age);
8873 if (!counter || age == NULL)
8875 age_param = flow_dv_counter_idx_get_age(dev, counter);
8876 age_param->context = age->context ? age->context :
8877 (void *)(uintptr_t)(dev_flow->flow_idx);
8878 age_param->timeout = age->timeout;
8879 age_param->port_id = dev->data->port_id;
8880 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8881 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8886 * Add Tx queue matcher
8889 * Pointer to the dev struct.
8890 * @param[in, out] matcher
8892 * @param[in, out] key
8893 * Flow matcher value.
8895 * Flow pattern to translate.
8897 * Item is inner pattern.
8900 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8901 void *matcher, void *key,
8902 const struct rte_flow_item *item)
8904 const struct mlx5_rte_flow_item_tx_queue *queue_m;
8905 const struct mlx5_rte_flow_item_tx_queue *queue_v;
8907 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8909 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8910 struct mlx5_txq_ctrl *txq;
8914 queue_m = (const void *)item->mask;
8917 queue_v = (const void *)item->spec;
8920 txq = mlx5_txq_get(dev, queue_v->queue);
8923 queue = txq->obj->sq->id;
8924 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8925 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8926 queue & queue_m->queue);
8927 mlx5_txq_release(dev, queue_v->queue);
8931 * Set the hash fields according to the @p flow information.
8933 * @param[in] dev_flow
8934 * Pointer to the mlx5_flow.
8935 * @param[in] rss_desc
8936 * Pointer to the mlx5_flow_rss_desc.
8939 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8940 struct mlx5_flow_rss_desc *rss_desc)
8942 uint64_t items = dev_flow->handle->layers;
8944 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8946 dev_flow->hash_fields = 0;
8947 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8948 if (rss_desc->level >= 2) {
8949 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8953 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8954 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8955 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8956 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8957 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8958 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8959 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8961 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8963 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8964 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8965 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8966 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8967 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8968 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8969 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8971 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8974 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8975 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8976 if (rss_types & ETH_RSS_UDP) {
8977 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8978 dev_flow->hash_fields |=
8979 IBV_RX_HASH_SRC_PORT_UDP;
8980 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8981 dev_flow->hash_fields |=
8982 IBV_RX_HASH_DST_PORT_UDP;
8984 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8986 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8987 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8988 if (rss_types & ETH_RSS_TCP) {
8989 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8990 dev_flow->hash_fields |=
8991 IBV_RX_HASH_SRC_PORT_TCP;
8992 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8993 dev_flow->hash_fields |=
8994 IBV_RX_HASH_DST_PORT_TCP;
8996 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9002 * Prepare an Rx Hash queue.
9005 * Pointer to Ethernet device.
9006 * @param[in] dev_flow
9007 * Pointer to the mlx5_flow.
9008 * @param[in] rss_desc
9009 * Pointer to the mlx5_flow_rss_desc.
9010 * @param[out] hrxq_idx
9011 * Hash Rx queue index.
9014 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9016 static struct mlx5_hrxq *
9017 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9018 struct mlx5_flow *dev_flow,
9019 struct mlx5_flow_rss_desc *rss_desc,
9022 struct mlx5_priv *priv = dev->data->dev_private;
9023 struct mlx5_flow_handle *dh = dev_flow->handle;
9024 struct mlx5_hrxq *hrxq;
9026 MLX5_ASSERT(rss_desc->queue_num);
9027 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9028 rss_desc->hash_fields = dev_flow->hash_fields;
9029 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9030 rss_desc->shared_rss = 0;
9031 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9034 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9040 * Release sample sub action resource.
9042 * @param[in, out] dev
9043 * Pointer to rte_eth_dev structure.
9044 * @param[in] act_res
9045 * Pointer to sample sub action resource.
9048 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9049 struct mlx5_flow_sub_actions_idx *act_res)
9051 if (act_res->rix_hrxq) {
9052 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9053 act_res->rix_hrxq = 0;
9055 if (act_res->rix_encap_decap) {
9056 flow_dv_encap_decap_resource_release(dev,
9057 act_res->rix_encap_decap);
9058 act_res->rix_encap_decap = 0;
9060 if (act_res->rix_port_id_action) {
9061 flow_dv_port_id_action_resource_release(dev,
9062 act_res->rix_port_id_action);
9063 act_res->rix_port_id_action = 0;
9065 if (act_res->rix_tag) {
9066 flow_dv_tag_release(dev, act_res->rix_tag);
9067 act_res->rix_tag = 0;
9070 flow_dv_counter_free(dev, act_res->cnt);
9073 if (act_res->rix_jump) {
9074 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9075 act_res->rix_jump = 0;
9080 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9081 struct mlx5_cache_entry *entry, void *cb_ctx)
9083 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9084 struct rte_eth_dev *dev = ctx->dev;
9085 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9086 struct mlx5_flow_dv_sample_resource *cache_resource =
9087 container_of(entry, typeof(*cache_resource), entry);
9089 if (resource->ratio == cache_resource->ratio &&
9090 resource->ft_type == cache_resource->ft_type &&
9091 resource->ft_id == cache_resource->ft_id &&
9092 resource->set_action == cache_resource->set_action &&
9093 !memcmp((void *)&resource->sample_act,
9094 (void *)&cache_resource->sample_act,
9095 sizeof(struct mlx5_flow_sub_actions_list))) {
9097 * Existing sample action should release the prepared
9098 * sub-actions reference counter.
9100 flow_dv_sample_sub_actions_release(dev,
9101 &resource->sample_idx);
9107 struct mlx5_cache_entry *
9108 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9109 struct mlx5_cache_entry *entry __rte_unused,
9112 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9113 struct rte_eth_dev *dev = ctx->dev;
9114 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9115 void **sample_dv_actions = resource->sub_actions;
9116 struct mlx5_flow_dv_sample_resource *cache_resource;
9117 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9118 struct mlx5_priv *priv = dev->data->dev_private;
9119 struct mlx5_dev_ctx_shared *sh = priv->sh;
9120 struct mlx5_flow_tbl_resource *tbl;
9122 const uint32_t next_ft_step = 1;
9123 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9124 uint8_t is_egress = 0;
9125 uint8_t is_transfer = 0;
9126 struct rte_flow_error *error = ctx->error;
9128 /* Register new sample resource. */
9129 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9130 if (!cache_resource) {
9131 rte_flow_error_set(error, ENOMEM,
9132 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9134 "cannot allocate resource memory");
9137 *cache_resource = *resource;
9138 /* Create normal path table level */
9139 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9141 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9143 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9144 is_egress, is_transfer,
9145 true, NULL, 0, 0, error);
9147 rte_flow_error_set(error, ENOMEM,
9148 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9150 "fail to create normal path table "
9156 cache_resource->normal_path_tbl = tbl;
9157 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9158 ret = mlx5_flow_os_create_flow_action_default_miss
9159 (&cache_resource->default_miss);
9161 rte_flow_error_set(error, ENOMEM,
9162 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9164 "cannot create default miss "
9168 sample_dv_actions[resource->sample_act.actions_num++] =
9169 cache_resource->default_miss;
9171 /* Create a DR sample action */
9172 sampler_attr.sample_ratio = cache_resource->ratio;
9173 sampler_attr.default_next_table = tbl->obj;
9174 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9175 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9176 &sample_dv_actions[0];
9177 sampler_attr.action = cache_resource->set_action;
9178 if (mlx5_os_flow_dr_create_flow_action_sampler
9179 (&sampler_attr, &cache_resource->verbs_action)) {
9180 rte_flow_error_set(error, ENOMEM,
9181 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9182 NULL, "cannot create sample action");
9185 cache_resource->idx = idx;
9186 cache_resource->dev = dev;
9187 return &cache_resource->entry;
9189 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
9190 cache_resource->default_miss)
9191 claim_zero(mlx5_flow_os_destroy_flow_action
9192 (cache_resource->default_miss));
9194 flow_dv_sample_sub_actions_release(dev,
9195 &cache_resource->sample_idx);
9196 if (cache_resource->normal_path_tbl)
9197 flow_dv_tbl_resource_release(MLX5_SH(dev),
9198 cache_resource->normal_path_tbl);
9199 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9205 * Find existing sample resource or create and register a new one.
9207 * @param[in, out] dev
9208 * Pointer to rte_eth_dev structure.
9209 * @param[in] resource
9210 * Pointer to sample resource.
9211 * @parm[in, out] dev_flow
9212 * Pointer to the dev_flow.
9214 * pointer to error structure.
9217 * 0 on success otherwise -errno and errno is set.
9220 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9221 struct mlx5_flow_dv_sample_resource *resource,
9222 struct mlx5_flow *dev_flow,
9223 struct rte_flow_error *error)
9225 struct mlx5_flow_dv_sample_resource *cache_resource;
9226 struct mlx5_cache_entry *entry;
9227 struct mlx5_priv *priv = dev->data->dev_private;
9228 struct mlx5_flow_cb_ctx ctx = {
9234 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9237 cache_resource = container_of(entry, typeof(*cache_resource), entry);
9238 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9239 dev_flow->dv.sample_res = cache_resource;
9244 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9245 struct mlx5_cache_entry *entry, void *cb_ctx)
9247 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9248 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9249 struct rte_eth_dev *dev = ctx->dev;
9250 struct mlx5_flow_dv_dest_array_resource *cache_resource =
9251 container_of(entry, typeof(*cache_resource), entry);
9254 if (resource->num_of_dest == cache_resource->num_of_dest &&
9255 resource->ft_type == cache_resource->ft_type &&
9256 !memcmp((void *)cache_resource->sample_act,
9257 (void *)resource->sample_act,
9258 (resource->num_of_dest *
9259 sizeof(struct mlx5_flow_sub_actions_list)))) {
9261 * Existing sample action should release the prepared
9262 * sub-actions reference counter.
9264 for (idx = 0; idx < resource->num_of_dest; idx++)
9265 flow_dv_sample_sub_actions_release(dev,
9266 &resource->sample_idx[idx]);
9272 struct mlx5_cache_entry *
9273 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9274 struct mlx5_cache_entry *entry __rte_unused,
9277 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9278 struct rte_eth_dev *dev = ctx->dev;
9279 struct mlx5_flow_dv_dest_array_resource *cache_resource;
9280 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9281 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9282 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9283 struct mlx5_priv *priv = dev->data->dev_private;
9284 struct mlx5_dev_ctx_shared *sh = priv->sh;
9285 struct mlx5_flow_sub_actions_list *sample_act;
9286 struct mlx5dv_dr_domain *domain;
9287 uint32_t idx = 0, res_idx = 0;
9288 struct rte_flow_error *error = ctx->error;
9289 uint64_t action_flags;
9292 /* Register new destination array resource. */
9293 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9295 if (!cache_resource) {
9296 rte_flow_error_set(error, ENOMEM,
9297 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9299 "cannot allocate resource memory");
9302 *cache_resource = *resource;
9303 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9304 domain = sh->fdb_domain;
9305 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9306 domain = sh->rx_domain;
9308 domain = sh->tx_domain;
9309 for (idx = 0; idx < resource->num_of_dest; idx++) {
9310 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9311 mlx5_malloc(MLX5_MEM_ZERO,
9312 sizeof(struct mlx5dv_dr_action_dest_attr),
9314 if (!dest_attr[idx]) {
9315 rte_flow_error_set(error, ENOMEM,
9316 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9318 "cannot allocate resource memory");
9321 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9322 sample_act = &resource->sample_act[idx];
9323 action_flags = sample_act->action_flags;
9324 switch (action_flags) {
9325 case MLX5_FLOW_ACTION_QUEUE:
9326 dest_attr[idx]->dest = sample_act->dr_queue_action;
9328 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
9329 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9330 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9331 dest_attr[idx]->dest_reformat->reformat =
9332 sample_act->dr_encap_action;
9333 dest_attr[idx]->dest_reformat->dest =
9334 sample_act->dr_port_id_action;
9336 case MLX5_FLOW_ACTION_PORT_ID:
9337 dest_attr[idx]->dest = sample_act->dr_port_id_action;
9339 case MLX5_FLOW_ACTION_JUMP:
9340 dest_attr[idx]->dest = sample_act->dr_jump_action;
9343 rte_flow_error_set(error, EINVAL,
9344 RTE_FLOW_ERROR_TYPE_ACTION,
9346 "unsupported actions type");
9350 /* create a dest array actioin */
9351 ret = mlx5_os_flow_dr_create_flow_action_dest_array
9353 cache_resource->num_of_dest,
9355 &cache_resource->action);
9357 rte_flow_error_set(error, ENOMEM,
9358 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9360 "cannot create destination array action");
9363 cache_resource->idx = res_idx;
9364 cache_resource->dev = dev;
9365 for (idx = 0; idx < resource->num_of_dest; idx++)
9366 mlx5_free(dest_attr[idx]);
9367 return &cache_resource->entry;
9369 for (idx = 0; idx < resource->num_of_dest; idx++) {
9370 struct mlx5_flow_sub_actions_idx *act_res =
9371 &cache_resource->sample_idx[idx];
9372 if (act_res->rix_hrxq &&
9373 !mlx5_hrxq_release(dev,
9375 act_res->rix_hrxq = 0;
9376 if (act_res->rix_encap_decap &&
9377 !flow_dv_encap_decap_resource_release(dev,
9378 act_res->rix_encap_decap))
9379 act_res->rix_encap_decap = 0;
9380 if (act_res->rix_port_id_action &&
9381 !flow_dv_port_id_action_resource_release(dev,
9382 act_res->rix_port_id_action))
9383 act_res->rix_port_id_action = 0;
9384 if (act_res->rix_jump &&
9385 !flow_dv_jump_tbl_resource_release(dev,
9387 act_res->rix_jump = 0;
9389 mlx5_free(dest_attr[idx]);
9392 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9397 * Find existing destination array resource or create and register a new one.
9399 * @param[in, out] dev
9400 * Pointer to rte_eth_dev structure.
9401 * @param[in] resource
9402 * Pointer to destination array resource.
9403 * @parm[in, out] dev_flow
9404 * Pointer to the dev_flow.
9406 * pointer to error structure.
9409 * 0 on success otherwise -errno and errno is set.
9412 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9413 struct mlx5_flow_dv_dest_array_resource *resource,
9414 struct mlx5_flow *dev_flow,
9415 struct rte_flow_error *error)
9417 struct mlx5_flow_dv_dest_array_resource *cache_resource;
9418 struct mlx5_priv *priv = dev->data->dev_private;
9419 struct mlx5_cache_entry *entry;
9420 struct mlx5_flow_cb_ctx ctx = {
9426 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9429 cache_resource = container_of(entry, typeof(*cache_resource), entry);
9430 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9431 dev_flow->dv.dest_array_res = cache_resource;
9436 * Convert Sample action to DV specification.
9439 * Pointer to rte_eth_dev structure.
9441 * Pointer to sample action structure.
9442 * @param[in, out] dev_flow
9443 * Pointer to the mlx5_flow.
9445 * Pointer to the flow attributes.
9446 * @param[in, out] num_of_dest
9447 * Pointer to the num of destination.
9448 * @param[in, out] sample_actions
9449 * Pointer to sample actions list.
9450 * @param[in, out] res
9451 * Pointer to sample resource.
9453 * Pointer to the error structure.
9456 * 0 on success, a negative errno value otherwise and rte_errno is set.
9459 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9460 const struct rte_flow_action_sample *action,
9461 struct mlx5_flow *dev_flow,
9462 const struct rte_flow_attr *attr,
9463 uint32_t *num_of_dest,
9464 void **sample_actions,
9465 struct mlx5_flow_dv_sample_resource *res,
9466 struct rte_flow_error *error)
9468 struct mlx5_priv *priv = dev->data->dev_private;
9469 const struct rte_flow_action *sub_actions;
9470 struct mlx5_flow_sub_actions_list *sample_act;
9471 struct mlx5_flow_sub_actions_idx *sample_idx;
9472 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9473 struct mlx5_flow_rss_desc *rss_desc;
9474 uint64_t action_flags = 0;
9477 rss_desc = &wks->rss_desc;
9478 sample_act = &res->sample_act;
9479 sample_idx = &res->sample_idx;
9480 res->ratio = action->ratio;
9481 sub_actions = action->actions;
9482 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9483 int type = sub_actions->type;
9484 uint32_t pre_rix = 0;
9487 case RTE_FLOW_ACTION_TYPE_QUEUE:
9489 const struct rte_flow_action_queue *queue;
9490 struct mlx5_hrxq *hrxq;
9493 queue = sub_actions->conf;
9494 rss_desc->queue_num = 1;
9495 rss_desc->queue[0] = queue->index;
9496 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9497 rss_desc, &hrxq_idx);
9499 return rte_flow_error_set
9501 RTE_FLOW_ERROR_TYPE_ACTION,
9503 "cannot create fate queue");
9504 sample_act->dr_queue_action = hrxq->action;
9505 sample_idx->rix_hrxq = hrxq_idx;
9506 sample_actions[sample_act->actions_num++] =
9509 action_flags |= MLX5_FLOW_ACTION_QUEUE;
9510 if (action_flags & MLX5_FLOW_ACTION_MARK)
9511 dev_flow->handle->rix_hrxq = hrxq_idx;
9512 dev_flow->handle->fate_action =
9513 MLX5_FLOW_FATE_QUEUE;
9516 case RTE_FLOW_ACTION_TYPE_RSS:
9518 struct mlx5_hrxq *hrxq;
9520 const struct rte_flow_action_rss *rss;
9521 const uint8_t *rss_key;
9523 rss = sub_actions->conf;
9524 memcpy(rss_desc->queue, rss->queue,
9525 rss->queue_num * sizeof(uint16_t));
9526 rss_desc->queue_num = rss->queue_num;
9527 /* NULL RSS key indicates default RSS key. */
9528 rss_key = !rss->key ? rss_hash_default_key : rss->key;
9529 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9531 * rss->level and rss.types should be set in advance
9532 * when expanding items for RSS.
9534 flow_dv_hashfields_set(dev_flow, rss_desc);
9535 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9536 rss_desc, &hrxq_idx);
9538 return rte_flow_error_set
9540 RTE_FLOW_ERROR_TYPE_ACTION,
9542 "cannot create fate queue");
9543 sample_act->dr_queue_action = hrxq->action;
9544 sample_idx->rix_hrxq = hrxq_idx;
9545 sample_actions[sample_act->actions_num++] =
9548 action_flags |= MLX5_FLOW_ACTION_RSS;
9549 if (action_flags & MLX5_FLOW_ACTION_MARK)
9550 dev_flow->handle->rix_hrxq = hrxq_idx;
9551 dev_flow->handle->fate_action =
9552 MLX5_FLOW_FATE_QUEUE;
9555 case RTE_FLOW_ACTION_TYPE_MARK:
9557 uint32_t tag_be = mlx5_flow_mark_set
9558 (((const struct rte_flow_action_mark *)
9559 (sub_actions->conf))->id);
9561 dev_flow->handle->mark = 1;
9562 pre_rix = dev_flow->handle->dvh.rix_tag;
9563 /* Save the mark resource before sample */
9564 pre_r = dev_flow->dv.tag_resource;
9565 if (flow_dv_tag_resource_register(dev, tag_be,
9568 MLX5_ASSERT(dev_flow->dv.tag_resource);
9569 sample_act->dr_tag_action =
9570 dev_flow->dv.tag_resource->action;
9571 sample_idx->rix_tag =
9572 dev_flow->handle->dvh.rix_tag;
9573 sample_actions[sample_act->actions_num++] =
9574 sample_act->dr_tag_action;
9575 /* Recover the mark resource after sample */
9576 dev_flow->dv.tag_resource = pre_r;
9577 dev_flow->handle->dvh.rix_tag = pre_rix;
9578 action_flags |= MLX5_FLOW_ACTION_MARK;
9581 case RTE_FLOW_ACTION_TYPE_COUNT:
9585 counter = flow_dv_translate_create_counter(dev,
9586 dev_flow, sub_actions->conf, 0);
9588 return rte_flow_error_set
9590 RTE_FLOW_ERROR_TYPE_ACTION,
9592 "cannot create counter"
9594 sample_idx->cnt = counter;
9595 sample_act->dr_cnt_action =
9596 (flow_dv_counter_get_by_idx(dev,
9597 counter, NULL))->action;
9598 sample_actions[sample_act->actions_num++] =
9599 sample_act->dr_cnt_action;
9600 action_flags |= MLX5_FLOW_ACTION_COUNT;
9603 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9605 struct mlx5_flow_dv_port_id_action_resource
9607 uint32_t port_id = 0;
9609 memset(&port_id_resource, 0, sizeof(port_id_resource));
9610 /* Save the port id resource before sample */
9611 pre_rix = dev_flow->handle->rix_port_id_action;
9612 pre_r = dev_flow->dv.port_id_action;
9613 if (flow_dv_translate_action_port_id(dev, sub_actions,
9616 port_id_resource.port_id = port_id;
9617 if (flow_dv_port_id_action_resource_register
9618 (dev, &port_id_resource, dev_flow, error))
9620 sample_act->dr_port_id_action =
9621 dev_flow->dv.port_id_action->action;
9622 sample_idx->rix_port_id_action =
9623 dev_flow->handle->rix_port_id_action;
9624 sample_actions[sample_act->actions_num++] =
9625 sample_act->dr_port_id_action;
9626 /* Recover the port id resource after sample */
9627 dev_flow->dv.port_id_action = pre_r;
9628 dev_flow->handle->rix_port_id_action = pre_rix;
9630 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9633 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9634 /* Save the encap resource before sample */
9635 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9636 pre_r = dev_flow->dv.encap_decap;
9637 if (flow_dv_create_action_l2_encap(dev, sub_actions,
9642 sample_act->dr_encap_action =
9643 dev_flow->dv.encap_decap->action;
9644 sample_idx->rix_encap_decap =
9645 dev_flow->handle->dvh.rix_encap_decap;
9646 sample_actions[sample_act->actions_num++] =
9647 sample_act->dr_encap_action;
9648 /* Recover the encap resource after sample */
9649 dev_flow->dv.encap_decap = pre_r;
9650 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9651 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9654 return rte_flow_error_set(error, EINVAL,
9655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9657 "Not support for sampler action");
9660 sample_act->action_flags = action_flags;
9661 res->ft_id = dev_flow->dv.group;
9662 if (attr->transfer) {
9664 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9665 uint64_t set_action;
9666 } action_ctx = { .set_action = 0 };
9668 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9669 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9670 MLX5_MODIFICATION_TYPE_SET);
9671 MLX5_SET(set_action_in, action_ctx.action_in, field,
9672 MLX5_MODI_META_REG_C_0);
9673 MLX5_SET(set_action_in, action_ctx.action_in, data,
9674 priv->vport_meta_tag);
9675 res->set_action = action_ctx.set_action;
9676 } else if (attr->ingress) {
9677 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9679 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9685 * Convert Sample action to DV specification.
9688 * Pointer to rte_eth_dev structure.
9689 * @param[in, out] dev_flow
9690 * Pointer to the mlx5_flow.
9691 * @param[in] num_of_dest
9692 * The num of destination.
9693 * @param[in, out] res
9694 * Pointer to sample resource.
9695 * @param[in, out] mdest_res
9696 * Pointer to destination array resource.
9697 * @param[in] sample_actions
9698 * Pointer to sample path actions list.
9699 * @param[in] action_flags
9700 * Holds the actions detected until now.
9702 * Pointer to the error structure.
9705 * 0 on success, a negative errno value otherwise and rte_errno is set.
9708 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9709 struct mlx5_flow *dev_flow,
9710 uint32_t num_of_dest,
9711 struct mlx5_flow_dv_sample_resource *res,
9712 struct mlx5_flow_dv_dest_array_resource *mdest_res,
9713 void **sample_actions,
9714 uint64_t action_flags,
9715 struct rte_flow_error *error)
9717 /* update normal path action resource into last index of array */
9718 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9719 struct mlx5_flow_sub_actions_list *sample_act =
9720 &mdest_res->sample_act[dest_index];
9721 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9722 struct mlx5_flow_rss_desc *rss_desc;
9723 uint32_t normal_idx = 0;
9724 struct mlx5_hrxq *hrxq;
9728 rss_desc = &wks->rss_desc;
9729 if (num_of_dest > 1) {
9730 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9731 /* Handle QP action for mirroring */
9732 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9733 rss_desc, &hrxq_idx);
9735 return rte_flow_error_set
9737 RTE_FLOW_ERROR_TYPE_ACTION,
9739 "cannot create rx queue");
9741 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9742 sample_act->dr_queue_action = hrxq->action;
9743 if (action_flags & MLX5_FLOW_ACTION_MARK)
9744 dev_flow->handle->rix_hrxq = hrxq_idx;
9745 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9747 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9749 mdest_res->sample_idx[dest_index].rix_encap_decap =
9750 dev_flow->handle->dvh.rix_encap_decap;
9751 sample_act->dr_encap_action =
9752 dev_flow->dv.encap_decap->action;
9754 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9756 mdest_res->sample_idx[dest_index].rix_port_id_action =
9757 dev_flow->handle->rix_port_id_action;
9758 sample_act->dr_port_id_action =
9759 dev_flow->dv.port_id_action->action;
9761 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
9763 mdest_res->sample_idx[dest_index].rix_jump =
9764 dev_flow->handle->rix_jump;
9765 sample_act->dr_jump_action =
9766 dev_flow->dv.jump->action;
9767 dev_flow->handle->rix_jump = 0;
9769 sample_act->actions_num = normal_idx;
9770 /* update sample action resource into first index of array */
9771 mdest_res->ft_type = res->ft_type;
9772 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9773 sizeof(struct mlx5_flow_sub_actions_idx));
9774 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9775 sizeof(struct mlx5_flow_sub_actions_list));
9776 mdest_res->num_of_dest = num_of_dest;
9777 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9779 return rte_flow_error_set(error, EINVAL,
9780 RTE_FLOW_ERROR_TYPE_ACTION,
9781 NULL, "can't create sample "
9784 res->sub_actions = sample_actions;
9785 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9786 return rte_flow_error_set(error, EINVAL,
9787 RTE_FLOW_ERROR_TYPE_ACTION,
9789 "can't create sample action");
9795 * Remove an ASO age action from age actions list.
9798 * Pointer to the Ethernet device structure.
9800 * Pointer to the aso age action handler.
9803 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9804 struct mlx5_aso_age_action *age)
9806 struct mlx5_age_info *age_info;
9807 struct mlx5_age_param *age_param = &age->age_params;
9808 struct mlx5_priv *priv = dev->data->dev_private;
9809 uint16_t expected = AGE_CANDIDATE;
9811 age_info = GET_PORT_AGE_INFO(priv);
9812 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9813 AGE_FREE, false, __ATOMIC_RELAXED,
9814 __ATOMIC_RELAXED)) {
9816 * We need the lock even it is age timeout,
9817 * since age action may still in process.
9819 rte_spinlock_lock(&age_info->aged_sl);
9820 LIST_REMOVE(age, next);
9821 rte_spinlock_unlock(&age_info->aged_sl);
9822 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9827 * Release an ASO age action.
9830 * Pointer to the Ethernet device structure.
9831 * @param[in] age_idx
9832 * Index of ASO age action to release.
9834 * True if the release operation is during flow destroy operation.
9835 * False if the release operation is during action destroy operation.
9838 * 0 when age action was removed, otherwise the number of references.
9841 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9843 struct mlx5_priv *priv = dev->data->dev_private;
9844 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9845 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9846 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9849 flow_dv_aso_age_remove_from_age(dev, age);
9850 rte_spinlock_lock(&mng->free_sl);
9851 LIST_INSERT_HEAD(&mng->free, age, next);
9852 rte_spinlock_unlock(&mng->free_sl);
9858 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9861 * Pointer to the Ethernet device structure.
9864 * 0 on success, otherwise negative errno value and rte_errno is set.
9867 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9869 struct mlx5_priv *priv = dev->data->dev_private;
9870 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9871 void *old_pools = mng->pools;
9872 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9873 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9874 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9881 memcpy(pools, old_pools,
9882 mng->n * sizeof(struct mlx5_flow_counter_pool *));
9883 mlx5_free(old_pools);
9885 /* First ASO flow hit allocation - starting ASO data-path. */
9886 int ret = mlx5_aso_queue_start(priv->sh);
9899 * Create and initialize a new ASO aging pool.
9902 * Pointer to the Ethernet device structure.
9903 * @param[out] age_free
9904 * Where to put the pointer of a new age action.
9907 * The age actions pool pointer and @p age_free is set on success,
9908 * NULL otherwise and rte_errno is set.
9910 static struct mlx5_aso_age_pool *
9911 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9912 struct mlx5_aso_age_action **age_free)
9914 struct mlx5_priv *priv = dev->data->dev_private;
9915 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9916 struct mlx5_aso_age_pool *pool = NULL;
9917 struct mlx5_devx_obj *obj = NULL;
9920 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9923 rte_errno = ENODATA;
9924 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9927 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9929 claim_zero(mlx5_devx_cmd_destroy(obj));
9933 pool->flow_hit_aso_obj = obj;
9934 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9935 rte_spinlock_lock(&mng->resize_sl);
9936 pool->index = mng->next;
9937 /* Resize pools array if there is no room for the new pool in it. */
9938 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9939 claim_zero(mlx5_devx_cmd_destroy(obj));
9941 rte_spinlock_unlock(&mng->resize_sl);
9944 mng->pools[pool->index] = pool;
9946 rte_spinlock_unlock(&mng->resize_sl);
9947 /* Assign the first action in the new pool, the rest go to free list. */
9948 *age_free = &pool->actions[0];
9949 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9950 pool->actions[i].offset = i;
9951 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9957 * Allocate a ASO aging bit.
9960 * Pointer to the Ethernet device structure.
9962 * Pointer to the error structure.
9965 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
9968 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9970 struct mlx5_priv *priv = dev->data->dev_private;
9971 const struct mlx5_aso_age_pool *pool;
9972 struct mlx5_aso_age_action *age_free = NULL;
9973 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9976 /* Try to get the next free age action bit. */
9977 rte_spinlock_lock(&mng->free_sl);
9978 age_free = LIST_FIRST(&mng->free);
9980 LIST_REMOVE(age_free, next);
9981 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9982 rte_spinlock_unlock(&mng->free_sl);
9983 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9984 NULL, "failed to create ASO age pool");
9985 return 0; /* 0 is an error. */
9987 rte_spinlock_unlock(&mng->free_sl);
9989 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9990 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9992 if (!age_free->dr_action) {
9993 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9997 rte_flow_error_set(error, rte_errno,
9998 RTE_FLOW_ERROR_TYPE_ACTION,
9999 NULL, "failed to get reg_c "
10000 "for ASO flow hit");
10001 return 0; /* 0 is an error. */
10003 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10004 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10005 (priv->sh->rx_domain,
10006 pool->flow_hit_aso_obj->obj, age_free->offset,
10007 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10008 (reg_c - REG_C_0));
10009 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10010 if (!age_free->dr_action) {
10012 rte_spinlock_lock(&mng->free_sl);
10013 LIST_INSERT_HEAD(&mng->free, age_free, next);
10014 rte_spinlock_unlock(&mng->free_sl);
10015 rte_flow_error_set(error, rte_errno,
10016 RTE_FLOW_ERROR_TYPE_ACTION,
10017 NULL, "failed to create ASO "
10018 "flow hit action");
10019 return 0; /* 0 is an error. */
10022 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10023 return pool->index | ((age_free->offset + 1) << 16);
10027 * Create a age action using ASO mechanism.
10030 * Pointer to rte_eth_dev structure.
10032 * Pointer to the aging action configuration.
10033 * @param[out] error
10034 * Pointer to the error structure.
10037 * Index to flow counter on success, 0 otherwise.
10040 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10041 const struct rte_flow_action_age *age,
10042 struct rte_flow_error *error)
10044 uint32_t age_idx = 0;
10045 struct mlx5_aso_age_action *aso_age;
10047 age_idx = flow_dv_aso_age_alloc(dev, error);
10050 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10051 aso_age->age_params.context = age->context;
10052 aso_age->age_params.timeout = age->timeout;
10053 aso_age->age_params.port_id = dev->data->port_id;
10054 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10056 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10062 * Fill the flow with DV spec, lock free
10063 * (mutex should be acquired by caller).
10066 * Pointer to rte_eth_dev structure.
10067 * @param[in, out] dev_flow
10068 * Pointer to the sub flow.
10070 * Pointer to the flow attributes.
10072 * Pointer to the list of items.
10073 * @param[in] actions
10074 * Pointer to the list of actions.
10075 * @param[out] error
10076 * Pointer to the error structure.
10079 * 0 on success, a negative errno value otherwise and rte_errno is set.
10082 flow_dv_translate(struct rte_eth_dev *dev,
10083 struct mlx5_flow *dev_flow,
10084 const struct rte_flow_attr *attr,
10085 const struct rte_flow_item items[],
10086 const struct rte_flow_action actions[],
10087 struct rte_flow_error *error)
10089 struct mlx5_priv *priv = dev->data->dev_private;
10090 struct mlx5_dev_config *dev_conf = &priv->config;
10091 struct rte_flow *flow = dev_flow->flow;
10092 struct mlx5_flow_handle *handle = dev_flow->handle;
10093 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10094 struct mlx5_flow_rss_desc *rss_desc;
10095 uint64_t item_flags = 0;
10096 uint64_t last_item = 0;
10097 uint64_t action_flags = 0;
10098 uint64_t priority = attr->priority;
10099 struct mlx5_flow_dv_matcher matcher = {
10101 .size = sizeof(matcher.mask.buf) -
10102 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10106 bool actions_end = false;
10108 struct mlx5_flow_dv_modify_hdr_resource res;
10109 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10110 sizeof(struct mlx5_modification_cmd) *
10111 (MLX5_MAX_MODIFY_NUM + 1)];
10113 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10114 const struct rte_flow_action_count *count = NULL;
10115 const struct rte_flow_action_age *age = NULL;
10116 union flow_dv_attr flow_attr = { .attr = 0 };
10118 union mlx5_flow_tbl_key tbl_key;
10119 uint32_t modify_action_position = UINT32_MAX;
10120 void *match_mask = matcher.mask.buf;
10121 void *match_value = dev_flow->dv.value.buf;
10122 uint8_t next_protocol = 0xff;
10123 struct rte_vlan_hdr vlan = { 0 };
10124 struct mlx5_flow_dv_dest_array_resource mdest_res;
10125 struct mlx5_flow_dv_sample_resource sample_res;
10126 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10127 const struct rte_flow_action_sample *sample = NULL;
10128 struct mlx5_flow_sub_actions_list *sample_act;
10129 uint32_t sample_act_pos = UINT32_MAX;
10130 uint32_t num_of_dest = 0;
10131 int tmp_actions_n = 0;
10134 const struct mlx5_flow_tunnel *tunnel;
10135 struct flow_grp_info grp_info = {
10136 .external = !!dev_flow->external,
10137 .transfer = !!attr->transfer,
10138 .fdb_def_rule = !!priv->fdb_def_rule,
10139 .skip_scale = dev_flow->skip_scale &
10140 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10144 return rte_flow_error_set(error, ENOMEM,
10145 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10147 "failed to push flow workspace");
10148 rss_desc = &wks->rss_desc;
10149 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10150 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10151 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10152 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10153 /* update normal path action resource into last index of array */
10154 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10155 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10156 flow_items_to_tunnel(items) :
10157 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10158 flow_actions_to_tunnel(actions) :
10159 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10160 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10161 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10162 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10163 (dev, tunnel, attr, items, actions);
10164 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10168 dev_flow->dv.group = table;
10169 if (attr->transfer)
10170 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10171 if (priority == MLX5_FLOW_PRIO_RSVD)
10172 priority = dev_conf->flow_prio - 1;
10173 /* number of actions must be set to 0 in case of dirty stack. */
10174 mhdr_res->actions_num = 0;
10175 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10177 * do not add decap action if match rule drops packet
10178 * HW rejects rules with decap & drop
10180 * if tunnel match rule was inserted before matching tunnel set
10181 * rule flow table used in the match rule must be registered.
10182 * current implementation handles that in the
10183 * flow_dv_match_register() at the function end.
10185 bool add_decap = true;
10186 const struct rte_flow_action *ptr = actions;
10188 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10189 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10195 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10199 dev_flow->dv.actions[actions_n++] =
10200 dev_flow->dv.encap_decap->action;
10201 action_flags |= MLX5_FLOW_ACTION_DECAP;
10204 for (; !actions_end ; actions++) {
10205 const struct rte_flow_action_queue *queue;
10206 const struct rte_flow_action_rss *rss;
10207 const struct rte_flow_action *action = actions;
10208 const uint8_t *rss_key;
10209 const struct rte_flow_action_meter *mtr;
10210 struct mlx5_flow_tbl_resource *tbl;
10211 struct mlx5_aso_age_action *age_act;
10212 uint32_t port_id = 0;
10213 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10214 int action_type = actions->type;
10215 const struct rte_flow_action *found_action = NULL;
10216 struct mlx5_flow_meter *fm = NULL;
10217 uint32_t jump_group = 0;
10219 if (!mlx5_flow_os_action_supported(action_type))
10220 return rte_flow_error_set(error, ENOTSUP,
10221 RTE_FLOW_ERROR_TYPE_ACTION,
10223 "action not supported");
10224 switch (action_type) {
10225 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10226 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10228 case RTE_FLOW_ACTION_TYPE_VOID:
10230 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10231 if (flow_dv_translate_action_port_id(dev, action,
10234 port_id_resource.port_id = port_id;
10235 MLX5_ASSERT(!handle->rix_port_id_action);
10236 if (flow_dv_port_id_action_resource_register
10237 (dev, &port_id_resource, dev_flow, error))
10239 dev_flow->dv.actions[actions_n++] =
10240 dev_flow->dv.port_id_action->action;
10241 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10242 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10243 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10246 case RTE_FLOW_ACTION_TYPE_FLAG:
10247 action_flags |= MLX5_FLOW_ACTION_FLAG;
10248 dev_flow->handle->mark = 1;
10249 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10250 struct rte_flow_action_mark mark = {
10251 .id = MLX5_FLOW_MARK_DEFAULT,
10254 if (flow_dv_convert_action_mark(dev, &mark,
10258 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10261 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10263 * Only one FLAG or MARK is supported per device flow
10264 * right now. So the pointer to the tag resource must be
10265 * zero before the register process.
10267 MLX5_ASSERT(!handle->dvh.rix_tag);
10268 if (flow_dv_tag_resource_register(dev, tag_be,
10271 MLX5_ASSERT(dev_flow->dv.tag_resource);
10272 dev_flow->dv.actions[actions_n++] =
10273 dev_flow->dv.tag_resource->action;
10275 case RTE_FLOW_ACTION_TYPE_MARK:
10276 action_flags |= MLX5_FLOW_ACTION_MARK;
10277 dev_flow->handle->mark = 1;
10278 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10279 const struct rte_flow_action_mark *mark =
10280 (const struct rte_flow_action_mark *)
10283 if (flow_dv_convert_action_mark(dev, mark,
10287 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10291 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10292 /* Legacy (non-extensive) MARK action. */
10293 tag_be = mlx5_flow_mark_set
10294 (((const struct rte_flow_action_mark *)
10295 (actions->conf))->id);
10296 MLX5_ASSERT(!handle->dvh.rix_tag);
10297 if (flow_dv_tag_resource_register(dev, tag_be,
10300 MLX5_ASSERT(dev_flow->dv.tag_resource);
10301 dev_flow->dv.actions[actions_n++] =
10302 dev_flow->dv.tag_resource->action;
10304 case RTE_FLOW_ACTION_TYPE_SET_META:
10305 if (flow_dv_convert_action_set_meta
10306 (dev, mhdr_res, attr,
10307 (const struct rte_flow_action_set_meta *)
10308 actions->conf, error))
10310 action_flags |= MLX5_FLOW_ACTION_SET_META;
10312 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10313 if (flow_dv_convert_action_set_tag
10315 (const struct rte_flow_action_set_tag *)
10316 actions->conf, error))
10318 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10320 case RTE_FLOW_ACTION_TYPE_DROP:
10321 action_flags |= MLX5_FLOW_ACTION_DROP;
10322 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10324 case RTE_FLOW_ACTION_TYPE_QUEUE:
10325 queue = actions->conf;
10326 rss_desc->queue_num = 1;
10327 rss_desc->queue[0] = queue->index;
10328 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10329 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10330 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10333 case RTE_FLOW_ACTION_TYPE_RSS:
10334 rss = actions->conf;
10335 memcpy(rss_desc->queue, rss->queue,
10336 rss->queue_num * sizeof(uint16_t));
10337 rss_desc->queue_num = rss->queue_num;
10338 /* NULL RSS key indicates default RSS key. */
10339 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10340 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10342 * rss->level and rss.types should be set in advance
10343 * when expanding items for RSS.
10345 action_flags |= MLX5_FLOW_ACTION_RSS;
10346 dev_flow->handle->fate_action = rss_desc->shared_rss ?
10347 MLX5_FLOW_FATE_SHARED_RSS :
10348 MLX5_FLOW_FATE_QUEUE;
10350 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10351 flow->age = (uint32_t)(uintptr_t)(action->conf);
10352 age_act = flow_aso_age_get_by_idx(dev, flow->age);
10353 __atomic_fetch_add(&age_act->refcnt, 1,
10355 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10356 action_flags |= MLX5_FLOW_ACTION_AGE;
10358 case RTE_FLOW_ACTION_TYPE_AGE:
10359 if (priv->sh->flow_hit_aso_en && attr->group) {
10360 flow->age = flow_dv_translate_create_aso_age
10361 (dev, action->conf, error);
10363 return rte_flow_error_set
10365 RTE_FLOW_ERROR_TYPE_ACTION,
10367 "can't create ASO age action");
10368 dev_flow->dv.actions[actions_n++] =
10369 (flow_aso_age_get_by_idx
10370 (dev, flow->age))->dr_action;
10371 action_flags |= MLX5_FLOW_ACTION_AGE;
10375 case RTE_FLOW_ACTION_TYPE_COUNT:
10376 if (!dev_conf->devx) {
10377 return rte_flow_error_set
10379 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10381 "count action not supported");
10383 /* Save information first, will apply later. */
10384 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10385 count = action->conf;
10387 age = action->conf;
10388 action_flags |= MLX5_FLOW_ACTION_COUNT;
10390 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10391 dev_flow->dv.actions[actions_n++] =
10392 priv->sh->pop_vlan_action;
10393 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10395 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10396 if (!(action_flags &
10397 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10398 flow_dev_get_vlan_info_from_items(items, &vlan);
10399 vlan.eth_proto = rte_be_to_cpu_16
10400 ((((const struct rte_flow_action_of_push_vlan *)
10401 actions->conf)->ethertype));
10402 found_action = mlx5_flow_find_action
10404 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10406 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10407 found_action = mlx5_flow_find_action
10409 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10411 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10412 if (flow_dv_create_action_push_vlan
10413 (dev, attr, &vlan, dev_flow, error))
10415 dev_flow->dv.actions[actions_n++] =
10416 dev_flow->dv.push_vlan_res->action;
10417 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10419 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10420 /* of_vlan_push action handled this action */
10421 MLX5_ASSERT(action_flags &
10422 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10424 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10425 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10427 flow_dev_get_vlan_info_from_items(items, &vlan);
10428 mlx5_update_vlan_vid_pcp(actions, &vlan);
10429 /* If no VLAN push - this is a modify header action */
10430 if (flow_dv_convert_action_modify_vlan_vid
10431 (mhdr_res, actions, error))
10433 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10435 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10436 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10437 if (flow_dv_create_action_l2_encap(dev, actions,
10442 dev_flow->dv.actions[actions_n++] =
10443 dev_flow->dv.encap_decap->action;
10444 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10445 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10446 sample_act->action_flags |=
10447 MLX5_FLOW_ACTION_ENCAP;
10449 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10450 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10451 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10455 dev_flow->dv.actions[actions_n++] =
10456 dev_flow->dv.encap_decap->action;
10457 action_flags |= MLX5_FLOW_ACTION_DECAP;
10459 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10460 /* Handle encap with preceding decap. */
10461 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10462 if (flow_dv_create_action_raw_encap
10463 (dev, actions, dev_flow, attr, error))
10465 dev_flow->dv.actions[actions_n++] =
10466 dev_flow->dv.encap_decap->action;
10468 /* Handle encap without preceding decap. */
10469 if (flow_dv_create_action_l2_encap
10470 (dev, actions, dev_flow, attr->transfer,
10473 dev_flow->dv.actions[actions_n++] =
10474 dev_flow->dv.encap_decap->action;
10476 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10477 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10478 sample_act->action_flags |=
10479 MLX5_FLOW_ACTION_ENCAP;
10481 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10482 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10484 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10485 if (flow_dv_create_action_l2_decap
10486 (dev, dev_flow, attr->transfer, error))
10488 dev_flow->dv.actions[actions_n++] =
10489 dev_flow->dv.encap_decap->action;
10491 /* If decap is followed by encap, handle it at encap. */
10492 action_flags |= MLX5_FLOW_ACTION_DECAP;
10494 case RTE_FLOW_ACTION_TYPE_JUMP:
10495 jump_group = ((const struct rte_flow_action_jump *)
10496 action->conf)->group;
10497 grp_info.std_tbl_fix = 0;
10498 if (dev_flow->skip_scale &
10499 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
10500 grp_info.skip_scale = 1;
10502 grp_info.skip_scale = 0;
10503 ret = mlx5_flow_group_to_table(dev, tunnel,
10509 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10511 !!dev_flow->external,
10512 tunnel, jump_group, 0,
10515 return rte_flow_error_set
10517 RTE_FLOW_ERROR_TYPE_ACTION,
10519 "cannot create jump action.");
10520 if (flow_dv_jump_tbl_resource_register
10521 (dev, tbl, dev_flow, error)) {
10522 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10523 return rte_flow_error_set
10525 RTE_FLOW_ERROR_TYPE_ACTION,
10527 "cannot create jump action.");
10529 dev_flow->dv.actions[actions_n++] =
10530 dev_flow->dv.jump->action;
10531 action_flags |= MLX5_FLOW_ACTION_JUMP;
10532 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10533 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
10536 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10537 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10538 if (flow_dv_convert_action_modify_mac
10539 (mhdr_res, actions, error))
10541 action_flags |= actions->type ==
10542 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10543 MLX5_FLOW_ACTION_SET_MAC_SRC :
10544 MLX5_FLOW_ACTION_SET_MAC_DST;
10546 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10547 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10548 if (flow_dv_convert_action_modify_ipv4
10549 (mhdr_res, actions, error))
10551 action_flags |= actions->type ==
10552 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10553 MLX5_FLOW_ACTION_SET_IPV4_SRC :
10554 MLX5_FLOW_ACTION_SET_IPV4_DST;
10556 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10557 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10558 if (flow_dv_convert_action_modify_ipv6
10559 (mhdr_res, actions, error))
10561 action_flags |= actions->type ==
10562 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10563 MLX5_FLOW_ACTION_SET_IPV6_SRC :
10564 MLX5_FLOW_ACTION_SET_IPV6_DST;
10566 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10567 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10568 if (flow_dv_convert_action_modify_tp
10569 (mhdr_res, actions, items,
10570 &flow_attr, dev_flow, !!(action_flags &
10571 MLX5_FLOW_ACTION_DECAP), error))
10573 action_flags |= actions->type ==
10574 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10575 MLX5_FLOW_ACTION_SET_TP_SRC :
10576 MLX5_FLOW_ACTION_SET_TP_DST;
10578 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10579 if (flow_dv_convert_action_modify_dec_ttl
10580 (mhdr_res, items, &flow_attr, dev_flow,
10582 MLX5_FLOW_ACTION_DECAP), error))
10584 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10586 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10587 if (flow_dv_convert_action_modify_ttl
10588 (mhdr_res, actions, items, &flow_attr,
10589 dev_flow, !!(action_flags &
10590 MLX5_FLOW_ACTION_DECAP), error))
10592 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10594 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10595 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10596 if (flow_dv_convert_action_modify_tcp_seq
10597 (mhdr_res, actions, error))
10599 action_flags |= actions->type ==
10600 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10601 MLX5_FLOW_ACTION_INC_TCP_SEQ :
10602 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10605 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10606 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10607 if (flow_dv_convert_action_modify_tcp_ack
10608 (mhdr_res, actions, error))
10610 action_flags |= actions->type ==
10611 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10612 MLX5_FLOW_ACTION_INC_TCP_ACK :
10613 MLX5_FLOW_ACTION_DEC_TCP_ACK;
10615 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10616 if (flow_dv_convert_action_set_reg
10617 (mhdr_res, actions, error))
10619 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10621 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10622 if (flow_dv_convert_action_copy_mreg
10623 (dev, mhdr_res, actions, error))
10625 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10627 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10628 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10629 dev_flow->handle->fate_action =
10630 MLX5_FLOW_FATE_DEFAULT_MISS;
10632 case RTE_FLOW_ACTION_TYPE_METER:
10633 mtr = actions->conf;
10634 if (!flow->meter) {
10635 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10638 return rte_flow_error_set(error,
10640 RTE_FLOW_ERROR_TYPE_ACTION,
10643 "or invalid parameters");
10644 flow->meter = fm->idx;
10646 /* Set the meter action. */
10648 fm = mlx5_ipool_get(priv->sh->ipool
10649 [MLX5_IPOOL_MTR], flow->meter);
10651 return rte_flow_error_set(error,
10653 RTE_FLOW_ERROR_TYPE_ACTION,
10656 "or invalid parameters");
10658 dev_flow->dv.actions[actions_n++] =
10659 fm->mfts->meter_action;
10660 action_flags |= MLX5_FLOW_ACTION_METER;
10662 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10663 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10666 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10668 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10669 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10672 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10674 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10675 sample_act_pos = actions_n;
10676 sample = (const struct rte_flow_action_sample *)
10679 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10680 /* put encap action into group if work with port id */
10681 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10682 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10683 sample_act->action_flags |=
10684 MLX5_FLOW_ACTION_ENCAP;
10686 case RTE_FLOW_ACTION_TYPE_END:
10687 actions_end = true;
10688 if (mhdr_res->actions_num) {
10689 /* create modify action if needed. */
10690 if (flow_dv_modify_hdr_resource_register
10691 (dev, mhdr_res, dev_flow, error))
10693 dev_flow->dv.actions[modify_action_position] =
10694 handle->dvh.modify_hdr->action;
10696 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10698 flow_dv_translate_create_counter(dev,
10699 dev_flow, count, age);
10701 if (!flow->counter)
10702 return rte_flow_error_set
10704 RTE_FLOW_ERROR_TYPE_ACTION,
10706 "cannot create counter"
10708 dev_flow->dv.actions[actions_n] =
10709 (flow_dv_counter_get_by_idx(dev,
10710 flow->counter, NULL))->action;
10716 if (mhdr_res->actions_num &&
10717 modify_action_position == UINT32_MAX)
10718 modify_action_position = actions_n++;
10720 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10721 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10722 int item_type = items->type;
10724 if (!mlx5_flow_os_item_supported(item_type))
10725 return rte_flow_error_set(error, ENOTSUP,
10726 RTE_FLOW_ERROR_TYPE_ITEM,
10727 NULL, "item not supported");
10728 switch (item_type) {
10729 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10730 flow_dv_translate_item_port_id
10731 (dev, match_mask, match_value, items, attr);
10732 last_item = MLX5_FLOW_ITEM_PORT_ID;
10734 case RTE_FLOW_ITEM_TYPE_ETH:
10735 flow_dv_translate_item_eth(match_mask, match_value,
10737 dev_flow->dv.group);
10738 matcher.priority = action_flags &
10739 MLX5_FLOW_ACTION_DEFAULT_MISS &&
10740 !dev_flow->external ?
10741 MLX5_PRIORITY_MAP_L3 :
10742 MLX5_PRIORITY_MAP_L2;
10743 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10744 MLX5_FLOW_LAYER_OUTER_L2;
10746 case RTE_FLOW_ITEM_TYPE_VLAN:
10747 flow_dv_translate_item_vlan(dev_flow,
10748 match_mask, match_value,
10750 dev_flow->dv.group);
10751 matcher.priority = MLX5_PRIORITY_MAP_L2;
10752 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10753 MLX5_FLOW_LAYER_INNER_VLAN) :
10754 (MLX5_FLOW_LAYER_OUTER_L2 |
10755 MLX5_FLOW_LAYER_OUTER_VLAN);
10757 case RTE_FLOW_ITEM_TYPE_IPV4:
10758 mlx5_flow_tunnel_ip_check(items, next_protocol,
10759 &item_flags, &tunnel);
10760 flow_dv_translate_item_ipv4(match_mask, match_value,
10762 dev_flow->dv.group);
10763 matcher.priority = MLX5_PRIORITY_MAP_L3;
10764 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10765 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10766 if (items->mask != NULL &&
10767 ((const struct rte_flow_item_ipv4 *)
10768 items->mask)->hdr.next_proto_id) {
10770 ((const struct rte_flow_item_ipv4 *)
10771 (items->spec))->hdr.next_proto_id;
10773 ((const struct rte_flow_item_ipv4 *)
10774 (items->mask))->hdr.next_proto_id;
10776 /* Reset for inner layer. */
10777 next_protocol = 0xff;
10780 case RTE_FLOW_ITEM_TYPE_IPV6:
10781 mlx5_flow_tunnel_ip_check(items, next_protocol,
10782 &item_flags, &tunnel);
10783 flow_dv_translate_item_ipv6(match_mask, match_value,
10785 dev_flow->dv.group);
10786 matcher.priority = MLX5_PRIORITY_MAP_L3;
10787 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10788 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10789 if (items->mask != NULL &&
10790 ((const struct rte_flow_item_ipv6 *)
10791 items->mask)->hdr.proto) {
10793 ((const struct rte_flow_item_ipv6 *)
10794 items->spec)->hdr.proto;
10796 ((const struct rte_flow_item_ipv6 *)
10797 items->mask)->hdr.proto;
10799 /* Reset for inner layer. */
10800 next_protocol = 0xff;
10803 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10804 flow_dv_translate_item_ipv6_frag_ext(match_mask,
10807 last_item = tunnel ?
10808 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10809 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10810 if (items->mask != NULL &&
10811 ((const struct rte_flow_item_ipv6_frag_ext *)
10812 items->mask)->hdr.next_header) {
10814 ((const struct rte_flow_item_ipv6_frag_ext *)
10815 items->spec)->hdr.next_header;
10817 ((const struct rte_flow_item_ipv6_frag_ext *)
10818 items->mask)->hdr.next_header;
10820 /* Reset for inner layer. */
10821 next_protocol = 0xff;
10824 case RTE_FLOW_ITEM_TYPE_TCP:
10825 flow_dv_translate_item_tcp(match_mask, match_value,
10827 matcher.priority = MLX5_PRIORITY_MAP_L4;
10828 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10829 MLX5_FLOW_LAYER_OUTER_L4_TCP;
10831 case RTE_FLOW_ITEM_TYPE_UDP:
10832 flow_dv_translate_item_udp(match_mask, match_value,
10834 matcher.priority = MLX5_PRIORITY_MAP_L4;
10835 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10836 MLX5_FLOW_LAYER_OUTER_L4_UDP;
10838 case RTE_FLOW_ITEM_TYPE_GRE:
10839 flow_dv_translate_item_gre(match_mask, match_value,
10841 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10842 last_item = MLX5_FLOW_LAYER_GRE;
10844 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10845 flow_dv_translate_item_gre_key(match_mask,
10846 match_value, items);
10847 last_item = MLX5_FLOW_LAYER_GRE_KEY;
10849 case RTE_FLOW_ITEM_TYPE_NVGRE:
10850 flow_dv_translate_item_nvgre(match_mask, match_value,
10852 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10853 last_item = MLX5_FLOW_LAYER_GRE;
10855 case RTE_FLOW_ITEM_TYPE_VXLAN:
10856 flow_dv_translate_item_vxlan(match_mask, match_value,
10858 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10859 last_item = MLX5_FLOW_LAYER_VXLAN;
10861 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10862 flow_dv_translate_item_vxlan_gpe(match_mask,
10863 match_value, items,
10865 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10866 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10868 case RTE_FLOW_ITEM_TYPE_GENEVE:
10869 flow_dv_translate_item_geneve(match_mask, match_value,
10871 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10872 last_item = MLX5_FLOW_LAYER_GENEVE;
10874 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
10875 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
10879 return rte_flow_error_set(error, -ret,
10880 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10881 "cannot create GENEVE TLV option");
10882 flow->geneve_tlv_option = 1;
10883 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
10885 case RTE_FLOW_ITEM_TYPE_MPLS:
10886 flow_dv_translate_item_mpls(match_mask, match_value,
10887 items, last_item, tunnel);
10888 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10889 last_item = MLX5_FLOW_LAYER_MPLS;
10891 case RTE_FLOW_ITEM_TYPE_MARK:
10892 flow_dv_translate_item_mark(dev, match_mask,
10893 match_value, items);
10894 last_item = MLX5_FLOW_ITEM_MARK;
10896 case RTE_FLOW_ITEM_TYPE_META:
10897 flow_dv_translate_item_meta(dev, match_mask,
10898 match_value, attr, items);
10899 last_item = MLX5_FLOW_ITEM_METADATA;
10901 case RTE_FLOW_ITEM_TYPE_ICMP:
10902 flow_dv_translate_item_icmp(match_mask, match_value,
10904 last_item = MLX5_FLOW_LAYER_ICMP;
10906 case RTE_FLOW_ITEM_TYPE_ICMP6:
10907 flow_dv_translate_item_icmp6(match_mask, match_value,
10909 last_item = MLX5_FLOW_LAYER_ICMP6;
10911 case RTE_FLOW_ITEM_TYPE_TAG:
10912 flow_dv_translate_item_tag(dev, match_mask,
10913 match_value, items);
10914 last_item = MLX5_FLOW_ITEM_TAG;
10916 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10917 flow_dv_translate_mlx5_item_tag(dev, match_mask,
10918 match_value, items);
10919 last_item = MLX5_FLOW_ITEM_TAG;
10921 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10922 flow_dv_translate_item_tx_queue(dev, match_mask,
10925 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10927 case RTE_FLOW_ITEM_TYPE_GTP:
10928 flow_dv_translate_item_gtp(match_mask, match_value,
10930 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10931 last_item = MLX5_FLOW_LAYER_GTP;
10933 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10934 ret = flow_dv_translate_item_gtp_psc(match_mask,
10938 return rte_flow_error_set(error, -ret,
10939 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10940 "cannot create GTP PSC item");
10941 last_item = MLX5_FLOW_LAYER_GTP_PSC;
10943 case RTE_FLOW_ITEM_TYPE_ECPRI:
10944 if (!mlx5_flex_parser_ecpri_exist(dev)) {
10945 /* Create it only the first time to be used. */
10946 ret = mlx5_flex_parser_ecpri_alloc(dev);
10948 return rte_flow_error_set
10950 RTE_FLOW_ERROR_TYPE_ITEM,
10952 "cannot create eCPRI parser");
10954 /* Adjust the length matcher and device flow value. */
10955 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10956 dev_flow->dv.value.size =
10957 MLX5_ST_SZ_BYTES(fte_match_param);
10958 flow_dv_translate_item_ecpri(dev, match_mask,
10959 match_value, items);
10960 /* No other protocol should follow eCPRI layer. */
10961 last_item = MLX5_FLOW_LAYER_ECPRI;
10966 item_flags |= last_item;
10969 * When E-Switch mode is enabled, we have two cases where we need to
10970 * set the source port manually.
10971 * The first one, is in case of Nic steering rule, and the second is
10972 * E-Switch rule where no port_id item was found. In both cases
10973 * the source port is set according the current port in use.
10975 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10976 (priv->representor || priv->master)) {
10977 if (flow_dv_translate_item_port_id(dev, match_mask,
10978 match_value, NULL, attr))
10981 #ifdef RTE_LIBRTE_MLX5_DEBUG
10982 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10983 dev_flow->dv.value.buf));
10986 * Layers may be already initialized from prefix flow if this dev_flow
10987 * is the suffix flow.
10989 handle->layers |= item_flags;
10990 if (action_flags & MLX5_FLOW_ACTION_RSS)
10991 flow_dv_hashfields_set(dev_flow, rss_desc);
10992 /* If has RSS action in the sample action, the Sample/Mirror resource
10993 * should be registered after the hash filed be update.
10995 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10996 ret = flow_dv_translate_action_sample(dev,
11005 ret = flow_dv_create_action_sample(dev,
11014 return rte_flow_error_set
11016 RTE_FLOW_ERROR_TYPE_ACTION,
11018 "cannot create sample action");
11019 if (num_of_dest > 1) {
11020 dev_flow->dv.actions[sample_act_pos] =
11021 dev_flow->dv.dest_array_res->action;
11023 dev_flow->dv.actions[sample_act_pos] =
11024 dev_flow->dv.sample_res->verbs_action;
11028 * For multiple destination (sample action with ratio=1), the encap
11029 * action and port id action will be combined into group action.
11030 * So need remove the original these actions in the flow and only
11031 * use the sample action instead of.
11033 if (num_of_dest > 1 &&
11034 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11036 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11038 for (i = 0; i < actions_n; i++) {
11039 if ((sample_act->dr_encap_action &&
11040 sample_act->dr_encap_action ==
11041 dev_flow->dv.actions[i]) ||
11042 (sample_act->dr_port_id_action &&
11043 sample_act->dr_port_id_action ==
11044 dev_flow->dv.actions[i]) ||
11045 (sample_act->dr_jump_action &&
11046 sample_act->dr_jump_action ==
11047 dev_flow->dv.actions[i]))
11049 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11051 memcpy((void *)dev_flow->dv.actions,
11052 (void *)temp_actions,
11053 tmp_actions_n * sizeof(void *));
11054 actions_n = tmp_actions_n;
11056 dev_flow->dv.actions_n = actions_n;
11057 dev_flow->act_flags = action_flags;
11058 /* Register matcher. */
11059 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11060 matcher.mask.size);
11061 matcher.priority = mlx5_os_flow_adjust_priority(dev,
11064 /* reserved field no needs to be set to 0 here. */
11065 tbl_key.domain = attr->transfer;
11066 tbl_key.direction = attr->egress;
11067 tbl_key.table_id = dev_flow->dv.group;
11068 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11069 tunnel, attr->group, error))
11075 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11078 * @param[in, out] action
11079 * Shred RSS action holding hash RX queue objects.
11080 * @param[in] hash_fields
11081 * Defines combination of packet fields to participate in RX hash.
11082 * @param[in] tunnel
11084 * @param[in] hrxq_idx
11085 * Hash RX queue index to set.
11088 * 0 on success, otherwise negative errno value.
11091 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11092 const uint64_t hash_fields,
11096 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11098 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11099 case MLX5_RSS_HASH_IPV4:
11100 hrxqs[0] = hrxq_idx;
11102 case MLX5_RSS_HASH_IPV4_TCP:
11103 hrxqs[1] = hrxq_idx;
11105 case MLX5_RSS_HASH_IPV4_UDP:
11106 hrxqs[2] = hrxq_idx;
11108 case MLX5_RSS_HASH_IPV6:
11109 hrxqs[3] = hrxq_idx;
11111 case MLX5_RSS_HASH_IPV6_TCP:
11112 hrxqs[4] = hrxq_idx;
11114 case MLX5_RSS_HASH_IPV6_UDP:
11115 hrxqs[5] = hrxq_idx;
11117 case MLX5_RSS_HASH_NONE:
11118 hrxqs[6] = hrxq_idx;
11126 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11130 * Pointer to the Ethernet device structure.
11132 * Shared RSS action ID holding hash RX queue objects.
11133 * @param[in] hash_fields
11134 * Defines combination of packet fields to participate in RX hash.
11135 * @param[in] tunnel
11139 * Valid hash RX queue index, otherwise 0.
11142 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11143 const uint64_t hash_fields,
11146 struct mlx5_priv *priv = dev->data->dev_private;
11147 struct mlx5_shared_action_rss *shared_rss =
11148 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11149 const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11150 shared_rss->hrxq_tunnel;
11152 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11153 case MLX5_RSS_HASH_IPV4:
11155 case MLX5_RSS_HASH_IPV4_TCP:
11157 case MLX5_RSS_HASH_IPV4_UDP:
11159 case MLX5_RSS_HASH_IPV6:
11161 case MLX5_RSS_HASH_IPV6_TCP:
11163 case MLX5_RSS_HASH_IPV6_UDP:
11165 case MLX5_RSS_HASH_NONE:
11173 * Apply the flow to the NIC, lock free,
11174 * (mutex should be acquired by caller).
11177 * Pointer to the Ethernet device structure.
11178 * @param[in, out] flow
11179 * Pointer to flow structure.
11180 * @param[out] error
11181 * Pointer to error structure.
11184 * 0 on success, a negative errno value otherwise and rte_errno is set.
11187 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11188 struct rte_flow_error *error)
11190 struct mlx5_flow_dv_workspace *dv;
11191 struct mlx5_flow_handle *dh;
11192 struct mlx5_flow_handle_dv *dv_h;
11193 struct mlx5_flow *dev_flow;
11194 struct mlx5_priv *priv = dev->data->dev_private;
11195 uint32_t handle_idx;
11199 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11200 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11203 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11204 dev_flow = &wks->flows[idx];
11205 dv = &dev_flow->dv;
11206 dh = dev_flow->handle;
11209 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11210 if (dv->transfer) {
11211 dv->actions[n++] = priv->sh->esw_drop_action;
11213 MLX5_ASSERT(priv->drop_queue.hrxq);
11215 priv->drop_queue.hrxq->action;
11217 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11218 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11219 struct mlx5_hrxq *hrxq;
11222 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11227 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11228 "cannot get hash queue");
11231 dh->rix_hrxq = hrxq_idx;
11232 dv->actions[n++] = hrxq->action;
11233 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11234 struct mlx5_hrxq *hrxq = NULL;
11237 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11238 rss_desc->shared_rss,
11239 dev_flow->hash_fields,
11241 MLX5_FLOW_LAYER_TUNNEL));
11243 hrxq = mlx5_ipool_get
11244 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11249 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11250 "cannot get hash queue");
11253 dh->rix_srss = rss_desc->shared_rss;
11254 dv->actions[n++] = hrxq->action;
11255 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11256 if (!priv->sh->default_miss_action) {
11259 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11260 "default miss action not be created.");
11263 dv->actions[n++] = priv->sh->default_miss_action;
11265 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11266 (void *)&dv->value, n,
11267 dv->actions, &dh->drv_flow);
11269 rte_flow_error_set(error, errno,
11270 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11272 "hardware refuses to create flow");
11275 if (priv->vmwa_context &&
11276 dh->vf_vlan.tag && !dh->vf_vlan.created) {
11278 * The rule contains the VLAN pattern.
11279 * For VF we are going to create VLAN
11280 * interface to make hypervisor set correct
11281 * e-Switch vport context.
11283 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11288 err = rte_errno; /* Save rte_errno before cleanup. */
11289 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11290 handle_idx, dh, next) {
11291 /* hrxq is union, don't clear it if the flag is not set. */
11292 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11293 mlx5_hrxq_release(dev, dh->rix_hrxq);
11295 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11298 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11299 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11301 rte_errno = err; /* Restore rte_errno. */
11306 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11307 struct mlx5_cache_entry *entry)
11309 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11312 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11317 * Release the flow matcher.
11320 * Pointer to Ethernet device.
11322 * Index to port ID action resource.
11325 * 1 while a reference on it exists, 0 when freed.
11328 flow_dv_matcher_release(struct rte_eth_dev *dev,
11329 struct mlx5_flow_handle *handle)
11331 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11332 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11333 typeof(*tbl), tbl);
11336 MLX5_ASSERT(matcher->matcher_object);
11337 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11338 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11343 * Release encap_decap resource.
11346 * Pointer to the hash list.
11348 * Pointer to exist resource entry object.
11351 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11352 struct mlx5_hlist_entry *entry)
11354 struct mlx5_dev_ctx_shared *sh = list->ctx;
11355 struct mlx5_flow_dv_encap_decap_resource *res =
11356 container_of(entry, typeof(*res), entry);
11358 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11359 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11363 * Release an encap/decap resource.
11366 * Pointer to Ethernet device.
11367 * @param encap_decap_idx
11368 * Index of encap decap resource.
11371 * 1 while a reference on it exists, 0 when freed.
11374 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11375 uint32_t encap_decap_idx)
11377 struct mlx5_priv *priv = dev->data->dev_private;
11378 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11380 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11382 if (!cache_resource)
11384 MLX5_ASSERT(cache_resource->action);
11385 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11386 &cache_resource->entry);
11390 * Release an jump to table action resource.
11393 * Pointer to Ethernet device.
11395 * Index to the jump action resource.
11398 * 1 while a reference on it exists, 0 when freed.
11401 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11404 struct mlx5_priv *priv = dev->data->dev_private;
11405 struct mlx5_flow_tbl_data_entry *tbl_data;
11407 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11411 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11415 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11416 struct mlx5_hlist_entry *entry)
11418 struct mlx5_flow_dv_modify_hdr_resource *res =
11419 container_of(entry, typeof(*res), entry);
11421 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11426 * Release a modify-header resource.
11429 * Pointer to Ethernet device.
11431 * Pointer to mlx5_flow_handle.
11434 * 1 while a reference on it exists, 0 when freed.
11437 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11438 struct mlx5_flow_handle *handle)
11440 struct mlx5_priv *priv = dev->data->dev_private;
11441 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11443 MLX5_ASSERT(entry->action);
11444 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11448 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11449 struct mlx5_cache_entry *entry)
11451 struct mlx5_dev_ctx_shared *sh = list->ctx;
11452 struct mlx5_flow_dv_port_id_action_resource *cache =
11453 container_of(entry, typeof(*cache), entry);
11455 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11456 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11460 * Release port ID action resource.
11463 * Pointer to Ethernet device.
11465 * Pointer to mlx5_flow_handle.
11468 * 1 while a reference on it exists, 0 when freed.
11471 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11474 struct mlx5_priv *priv = dev->data->dev_private;
11475 struct mlx5_flow_dv_port_id_action_resource *cache;
11477 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11480 MLX5_ASSERT(cache->action);
11481 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11486 * Release shared RSS action resource.
11489 * Pointer to Ethernet device.
11491 * Shared RSS action index.
11494 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11496 struct mlx5_priv *priv = dev->data->dev_private;
11497 struct mlx5_shared_action_rss *shared_rss;
11499 shared_rss = mlx5_ipool_get
11500 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11501 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11505 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11506 struct mlx5_cache_entry *entry)
11508 struct mlx5_dev_ctx_shared *sh = list->ctx;
11509 struct mlx5_flow_dv_push_vlan_action_resource *cache =
11510 container_of(entry, typeof(*cache), entry);
11512 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11513 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11517 * Release push vlan action resource.
11520 * Pointer to Ethernet device.
11522 * Pointer to mlx5_flow_handle.
11525 * 1 while a reference on it exists, 0 when freed.
11528 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11529 struct mlx5_flow_handle *handle)
11531 struct mlx5_priv *priv = dev->data->dev_private;
11532 struct mlx5_flow_dv_push_vlan_action_resource *cache;
11533 uint32_t idx = handle->dvh.rix_push_vlan;
11535 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11538 MLX5_ASSERT(cache->action);
11539 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11544 * Release the fate resource.
11547 * Pointer to Ethernet device.
11549 * Pointer to mlx5_flow_handle.
11552 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11553 struct mlx5_flow_handle *handle)
11555 if (!handle->rix_fate)
11557 switch (handle->fate_action) {
11558 case MLX5_FLOW_FATE_QUEUE:
11559 mlx5_hrxq_release(dev, handle->rix_hrxq);
11561 case MLX5_FLOW_FATE_JUMP:
11562 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
11564 case MLX5_FLOW_FATE_PORT_ID:
11565 flow_dv_port_id_action_resource_release(dev,
11566 handle->rix_port_id_action);
11569 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11572 handle->rix_fate = 0;
11576 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11577 struct mlx5_cache_entry *entry)
11579 struct mlx5_flow_dv_sample_resource *cache_resource =
11580 container_of(entry, typeof(*cache_resource), entry);
11581 struct rte_eth_dev *dev = cache_resource->dev;
11582 struct mlx5_priv *priv = dev->data->dev_private;
11584 if (cache_resource->verbs_action)
11585 claim_zero(mlx5_flow_os_destroy_flow_action
11586 (cache_resource->verbs_action));
11587 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11588 if (cache_resource->default_miss)
11589 claim_zero(mlx5_flow_os_destroy_flow_action
11590 (cache_resource->default_miss));
11592 if (cache_resource->normal_path_tbl)
11593 flow_dv_tbl_resource_release(MLX5_SH(dev),
11594 cache_resource->normal_path_tbl);
11595 flow_dv_sample_sub_actions_release(dev,
11596 &cache_resource->sample_idx);
11597 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11598 cache_resource->idx);
11599 DRV_LOG(DEBUG, "sample resource %p: removed",
11600 (void *)cache_resource);
11604 * Release an sample resource.
11607 * Pointer to Ethernet device.
11609 * Pointer to mlx5_flow_handle.
11612 * 1 while a reference on it exists, 0 when freed.
11615 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11616 struct mlx5_flow_handle *handle)
11618 struct mlx5_priv *priv = dev->data->dev_private;
11619 struct mlx5_flow_dv_sample_resource *cache_resource;
11621 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11622 handle->dvh.rix_sample);
11623 if (!cache_resource)
11625 MLX5_ASSERT(cache_resource->verbs_action);
11626 return mlx5_cache_unregister(&priv->sh->sample_action_list,
11627 &cache_resource->entry);
11631 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11632 struct mlx5_cache_entry *entry)
11634 struct mlx5_flow_dv_dest_array_resource *cache_resource =
11635 container_of(entry, typeof(*cache_resource), entry);
11636 struct rte_eth_dev *dev = cache_resource->dev;
11637 struct mlx5_priv *priv = dev->data->dev_private;
11640 MLX5_ASSERT(cache_resource->action);
11641 if (cache_resource->action)
11642 claim_zero(mlx5_flow_os_destroy_flow_action
11643 (cache_resource->action));
11644 for (; i < cache_resource->num_of_dest; i++)
11645 flow_dv_sample_sub_actions_release(dev,
11646 &cache_resource->sample_idx[i]);
11647 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11648 cache_resource->idx);
11649 DRV_LOG(DEBUG, "destination array resource %p: removed",
11650 (void *)cache_resource);
11654 * Release an destination array resource.
11657 * Pointer to Ethernet device.
11659 * Pointer to mlx5_flow_handle.
11662 * 1 while a reference on it exists, 0 when freed.
11665 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11666 struct mlx5_flow_handle *handle)
11668 struct mlx5_priv *priv = dev->data->dev_private;
11669 struct mlx5_flow_dv_dest_array_resource *cache;
11671 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11672 handle->dvh.rix_dest_array);
11675 MLX5_ASSERT(cache->action);
11676 return mlx5_cache_unregister(&priv->sh->dest_array_list,
11681 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11683 struct mlx5_priv *priv = dev->data->dev_private;
11684 struct mlx5_dev_ctx_shared *sh = priv->sh;
11685 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11686 sh->geneve_tlv_option_resource;
11687 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11688 if (geneve_opt_resource) {
11689 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11690 __ATOMIC_RELAXED))) {
11691 claim_zero(mlx5_devx_cmd_destroy
11692 (geneve_opt_resource->obj));
11693 mlx5_free(sh->geneve_tlv_option_resource);
11694 sh->geneve_tlv_option_resource = NULL;
11697 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11701 * Remove the flow from the NIC but keeps it in memory.
11702 * Lock free, (mutex should be acquired by caller).
11705 * Pointer to Ethernet device.
11706 * @param[in, out] flow
11707 * Pointer to flow structure.
11710 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11712 struct mlx5_flow_handle *dh;
11713 uint32_t handle_idx;
11714 struct mlx5_priv *priv = dev->data->dev_private;
11718 handle_idx = flow->dev_handles;
11719 while (handle_idx) {
11720 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11724 if (dh->drv_flow) {
11725 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11726 dh->drv_flow = NULL;
11728 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11729 flow_dv_fate_resource_release(dev, dh);
11730 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11731 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11732 handle_idx = dh->next.next;
11737 * Remove the flow from the NIC and the memory.
11738 * Lock free, (mutex should be acquired by caller).
11741 * Pointer to the Ethernet device structure.
11742 * @param[in, out] flow
11743 * Pointer to flow structure.
11746 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11748 struct mlx5_flow_handle *dev_handle;
11749 struct mlx5_priv *priv = dev->data->dev_private;
11754 flow_dv_remove(dev, flow);
11755 if (flow->counter) {
11756 flow_dv_counter_free(dev, flow->counter);
11760 struct mlx5_flow_meter *fm;
11762 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11765 mlx5_flow_meter_detach(fm);
11769 flow_dv_aso_age_release(dev, flow->age);
11770 if (flow->geneve_tlv_option) {
11771 flow_dv_geneve_tlv_option_resource_release(dev);
11772 flow->geneve_tlv_option = 0;
11774 while (flow->dev_handles) {
11775 uint32_t tmp_idx = flow->dev_handles;
11777 dev_handle = mlx5_ipool_get(priv->sh->ipool
11778 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11781 flow->dev_handles = dev_handle->next.next;
11782 if (dev_handle->dvh.matcher)
11783 flow_dv_matcher_release(dev, dev_handle);
11784 if (dev_handle->dvh.rix_sample)
11785 flow_dv_sample_resource_release(dev, dev_handle);
11786 if (dev_handle->dvh.rix_dest_array)
11787 flow_dv_dest_array_resource_release(dev, dev_handle);
11788 if (dev_handle->dvh.rix_encap_decap)
11789 flow_dv_encap_decap_resource_release(dev,
11790 dev_handle->dvh.rix_encap_decap);
11791 if (dev_handle->dvh.modify_hdr)
11792 flow_dv_modify_hdr_resource_release(dev, dev_handle);
11793 if (dev_handle->dvh.rix_push_vlan)
11794 flow_dv_push_vlan_action_resource_release(dev,
11796 if (dev_handle->dvh.rix_tag)
11797 flow_dv_tag_release(dev,
11798 dev_handle->dvh.rix_tag);
11799 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11800 flow_dv_fate_resource_release(dev, dev_handle);
11802 srss = dev_handle->rix_srss;
11803 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11807 flow_dv_shared_rss_action_release(dev, srss);
11811 * Release array of hash RX queue objects.
11815 * Pointer to the Ethernet device structure.
11816 * @param[in, out] hrxqs
11817 * Array of hash RX queue objects.
11820 * Total number of references to hash RX queue objects in *hrxqs* array
11821 * after this operation.
11824 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11825 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11830 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11831 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11841 * Release all hash RX queue objects representing shared RSS action.
11844 * Pointer to the Ethernet device structure.
11845 * @param[in, out] action
11846 * Shared RSS action to remove hash RX queue objects from.
11849 * Total number of references to hash RX queue objects stored in *action*
11850 * after this operation.
11851 * Expected to be 0 if no external references held.
11854 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11855 struct mlx5_shared_action_rss *action)
11857 return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11858 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11862 * Setup shared RSS action.
11863 * Prepare set of hash RX queue objects sufficient to handle all valid
11864 * hash_fields combinations (see enum ibv_rx_hash_fields).
11867 * Pointer to the Ethernet device structure.
11868 * @param[in] action_idx
11869 * Shared RSS action ipool index.
11870 * @param[in, out] action
11871 * Partially initialized shared RSS action.
11872 * @param[out] error
11873 * Perform verbose error reporting if not NULL. Initialized in case of
11877 * 0 on success, otherwise negative errno value.
11880 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11881 uint32_t action_idx,
11882 struct mlx5_shared_action_rss *action,
11883 struct rte_flow_error *error)
11885 struct mlx5_flow_rss_desc rss_desc = { 0 };
11889 if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11890 return rte_flow_error_set(error, rte_errno,
11891 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11892 "cannot setup indirection table");
11894 memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11895 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11896 rss_desc.const_q = action->origin.queue;
11897 rss_desc.queue_num = action->origin.queue_num;
11898 /* Set non-zero value to indicate a shared RSS. */
11899 rss_desc.shared_rss = action_idx;
11900 rss_desc.ind_tbl = action->ind_tbl;
11901 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11903 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11906 for (tunnel = 0; tunnel < 2; tunnel++) {
11907 rss_desc.tunnel = tunnel;
11908 rss_desc.hash_fields = hash_fields;
11909 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11914 "cannot get hash queue");
11915 goto error_hrxq_new;
11917 err = __flow_dv_action_rss_hrxq_set
11918 (action, hash_fields, tunnel, hrxq_idx);
11925 __flow_dv_action_rss_hrxqs_release(dev, action);
11926 if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11927 action->ind_tbl = NULL;
11933 * Create shared RSS action.
11936 * Pointer to the Ethernet device structure.
11938 * Shared action configuration.
11940 * RSS action specification used to create shared action.
11941 * @param[out] error
11942 * Perform verbose error reporting if not NULL. Initialized in case of
11946 * A valid shared action ID in case of success, 0 otherwise and
11947 * rte_errno is set.
11950 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11951 const struct rte_flow_shared_action_conf *conf,
11952 const struct rte_flow_action_rss *rss,
11953 struct rte_flow_error *error)
11955 struct mlx5_priv *priv = dev->data->dev_private;
11956 struct mlx5_shared_action_rss *shared_action = NULL;
11957 void *queue = NULL;
11958 struct rte_flow_action_rss *origin;
11959 const uint8_t *rss_key;
11960 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11963 RTE_SET_USED(conf);
11964 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11966 shared_action = mlx5_ipool_zmalloc
11967 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11968 if (!shared_action || !queue) {
11969 rte_flow_error_set(error, ENOMEM,
11970 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11971 "cannot allocate resource memory");
11972 goto error_rss_init;
11974 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11975 rte_flow_error_set(error, E2BIG,
11976 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11977 "rss action number out of range");
11978 goto error_rss_init;
11980 shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11981 sizeof(*shared_action->ind_tbl),
11983 if (!shared_action->ind_tbl) {
11984 rte_flow_error_set(error, ENOMEM,
11985 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11986 "cannot allocate resource memory");
11987 goto error_rss_init;
11989 memcpy(queue, rss->queue, queue_size);
11990 shared_action->ind_tbl->queues = queue;
11991 shared_action->ind_tbl->queues_n = rss->queue_num;
11992 origin = &shared_action->origin;
11993 origin->func = rss->func;
11994 origin->level = rss->level;
11995 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11996 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11997 /* NULL RSS key indicates default RSS key. */
11998 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11999 memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12000 origin->key = &shared_action->key[0];
12001 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12002 origin->queue = queue;
12003 origin->queue_num = rss->queue_num;
12004 if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
12005 goto error_rss_init;
12006 rte_spinlock_init(&shared_action->action_rss_sl);
12007 __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
12008 rte_spinlock_lock(&priv->shared_act_sl);
12009 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12010 &priv->rss_shared_actions, idx, shared_action, next);
12011 rte_spinlock_unlock(&priv->shared_act_sl);
12014 if (shared_action) {
12015 if (shared_action->ind_tbl)
12016 mlx5_free(shared_action->ind_tbl);
12017 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12026 * Destroy the shared RSS action.
12027 * Release related hash RX queue objects.
12030 * Pointer to the Ethernet device structure.
12032 * The shared RSS action object ID to be removed.
12033 * @param[out] error
12034 * Perform verbose error reporting if not NULL. Initialized in case of
12038 * 0 on success, otherwise negative errno value.
12041 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12042 struct rte_flow_error *error)
12044 struct mlx5_priv *priv = dev->data->dev_private;
12045 struct mlx5_shared_action_rss *shared_rss =
12046 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12047 uint32_t old_refcnt = 1;
12049 uint16_t *queue = NULL;
12052 return rte_flow_error_set(error, EINVAL,
12053 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12054 "invalid shared action");
12055 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12057 return rte_flow_error_set(error, EBUSY,
12058 RTE_FLOW_ERROR_TYPE_ACTION,
12060 "shared rss hrxq has references");
12061 queue = shared_rss->ind_tbl->queues;
12062 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12064 return rte_flow_error_set(error, EBUSY,
12065 RTE_FLOW_ERROR_TYPE_ACTION,
12067 "shared rss indirection table has"
12069 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12070 0, 0, __ATOMIC_ACQUIRE,
12072 return rte_flow_error_set(error, EBUSY,
12073 RTE_FLOW_ERROR_TYPE_ACTION,
12075 "shared rss has references");
12077 rte_spinlock_lock(&priv->shared_act_sl);
12078 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12079 &priv->rss_shared_actions, idx, shared_rss, next);
12080 rte_spinlock_unlock(&priv->shared_act_sl);
12081 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12087 * Create shared action, lock free,
12088 * (mutex should be acquired by caller).
12089 * Dispatcher for action type specific call.
12092 * Pointer to the Ethernet device structure.
12094 * Shared action configuration.
12095 * @param[in] action
12096 * Action specification used to create shared action.
12097 * @param[out] error
12098 * Perform verbose error reporting if not NULL. Initialized in case of
12102 * A valid shared action handle in case of success, NULL otherwise and
12103 * rte_errno is set.
12105 static struct rte_flow_shared_action *
12106 flow_dv_action_create(struct rte_eth_dev *dev,
12107 const struct rte_flow_shared_action_conf *conf,
12108 const struct rte_flow_action *action,
12109 struct rte_flow_error *err)
12114 switch (action->type) {
12115 case RTE_FLOW_ACTION_TYPE_RSS:
12116 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12117 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12118 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12120 case RTE_FLOW_ACTION_TYPE_AGE:
12121 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12122 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12123 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12125 struct mlx5_aso_age_action *aso_age =
12126 flow_aso_age_get_by_idx(dev, ret);
12128 if (!aso_age->age_params.context)
12129 aso_age->age_params.context =
12130 (void *)(uintptr_t)idx;
12134 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12135 NULL, "action type not supported");
12138 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12142 * Destroy the shared action.
12143 * Release action related resources on the NIC and the memory.
12144 * Lock free, (mutex should be acquired by caller).
12145 * Dispatcher for action type specific call.
12148 * Pointer to the Ethernet device structure.
12149 * @param[in] action
12150 * The shared action object to be removed.
12151 * @param[out] error
12152 * Perform verbose error reporting if not NULL. Initialized in case of
12156 * 0 on success, otherwise negative errno value.
12159 flow_dv_action_destroy(struct rte_eth_dev *dev,
12160 struct rte_flow_shared_action *action,
12161 struct rte_flow_error *error)
12163 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12164 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12165 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12169 case MLX5_SHARED_ACTION_TYPE_RSS:
12170 return __flow_dv_action_rss_release(dev, idx, error);
12171 case MLX5_SHARED_ACTION_TYPE_AGE:
12172 ret = flow_dv_aso_age_release(dev, idx);
12175 * In this case, the last flow has a reference will
12176 * actually release the age action.
12178 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12179 " released with references %d.", idx, ret);
12182 return rte_flow_error_set(error, ENOTSUP,
12183 RTE_FLOW_ERROR_TYPE_ACTION,
12185 "action type not supported");
12190 * Updates in place shared RSS action configuration.
12193 * Pointer to the Ethernet device structure.
12195 * The shared RSS action object ID to be updated.
12196 * @param[in] action_conf
12197 * RSS action specification used to modify *shared_rss*.
12198 * @param[out] error
12199 * Perform verbose error reporting if not NULL. Initialized in case of
12203 * 0 on success, otherwise negative errno value.
12204 * @note: currently only support update of RSS queues.
12207 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12208 const struct rte_flow_action_rss *action_conf,
12209 struct rte_flow_error *error)
12211 struct mlx5_priv *priv = dev->data->dev_private;
12212 struct mlx5_shared_action_rss *shared_rss =
12213 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12215 void *queue = NULL;
12216 uint16_t *queue_old = NULL;
12217 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12220 return rte_flow_error_set(error, EINVAL,
12221 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12222 "invalid shared action to update");
12223 queue = mlx5_malloc(MLX5_MEM_ZERO,
12224 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12227 return rte_flow_error_set(error, ENOMEM,
12228 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12230 "cannot allocate resource memory");
12231 memcpy(queue, action_conf->queue, queue_size);
12232 MLX5_ASSERT(shared_rss->ind_tbl);
12233 rte_spinlock_lock(&shared_rss->action_rss_sl);
12234 queue_old = shared_rss->ind_tbl->queues;
12235 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12236 queue, action_conf->queue_num, true);
12239 ret = rte_flow_error_set(error, rte_errno,
12240 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12241 "cannot update indirection table");
12243 mlx5_free(queue_old);
12244 shared_rss->origin.queue = queue;
12245 shared_rss->origin.queue_num = action_conf->queue_num;
12247 rte_spinlock_unlock(&shared_rss->action_rss_sl);
12252 * Updates in place shared action configuration, lock free,
12253 * (mutex should be acquired by caller).
12256 * Pointer to the Ethernet device structure.
12257 * @param[in] action
12258 * The shared action object to be updated.
12259 * @param[in] action_conf
12260 * Action specification used to modify *action*.
12261 * *action_conf* should be of type correlating with type of the *action*,
12262 * otherwise considered as invalid.
12263 * @param[out] error
12264 * Perform verbose error reporting if not NULL. Initialized in case of
12268 * 0 on success, otherwise negative errno value.
12271 flow_dv_action_update(struct rte_eth_dev *dev,
12272 struct rte_flow_shared_action *action,
12273 const void *action_conf,
12274 struct rte_flow_error *err)
12276 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12277 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12278 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12281 case MLX5_SHARED_ACTION_TYPE_RSS:
12282 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12284 return rte_flow_error_set(err, ENOTSUP,
12285 RTE_FLOW_ERROR_TYPE_ACTION,
12287 "action type update not supported");
12292 flow_dv_action_query(struct rte_eth_dev *dev,
12293 const struct rte_flow_shared_action *action, void *data,
12294 struct rte_flow_error *error)
12296 struct mlx5_age_param *age_param;
12297 struct rte_flow_query_age *resp;
12298 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12299 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12300 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12303 case MLX5_SHARED_ACTION_TYPE_AGE:
12304 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12306 resp->aged = __atomic_load_n(&age_param->state,
12307 __ATOMIC_RELAXED) == AGE_TMOUT ?
12309 resp->sec_since_last_hit_valid = !resp->aged;
12310 if (resp->sec_since_last_hit_valid)
12311 resp->sec_since_last_hit = __atomic_load_n
12312 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12315 return rte_flow_error_set(error, ENOTSUP,
12316 RTE_FLOW_ERROR_TYPE_ACTION,
12318 "action type query not supported");
12323 * Query a dv flow rule for its statistics via devx.
12326 * Pointer to Ethernet device.
12328 * Pointer to the sub flow.
12330 * data retrieved by the query.
12331 * @param[out] error
12332 * Perform verbose error reporting if not NULL.
12335 * 0 on success, a negative errno value otherwise and rte_errno is set.
12338 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12339 void *data, struct rte_flow_error *error)
12341 struct mlx5_priv *priv = dev->data->dev_private;
12342 struct rte_flow_query_count *qc = data;
12344 if (!priv->config.devx)
12345 return rte_flow_error_set(error, ENOTSUP,
12346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12348 "counters are not supported");
12349 if (flow->counter) {
12350 uint64_t pkts, bytes;
12351 struct mlx5_flow_counter *cnt;
12353 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12355 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12359 return rte_flow_error_set(error, -err,
12360 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12361 NULL, "cannot read counters");
12364 qc->hits = pkts - cnt->hits;
12365 qc->bytes = bytes - cnt->bytes;
12368 cnt->bytes = bytes;
12372 return rte_flow_error_set(error, EINVAL,
12373 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12375 "counters are not available");
12379 * Query a flow rule AGE action for aging information.
12382 * Pointer to Ethernet device.
12384 * Pointer to the sub flow.
12386 * data retrieved by the query.
12387 * @param[out] error
12388 * Perform verbose error reporting if not NULL.
12391 * 0 on success, a negative errno value otherwise and rte_errno is set.
12394 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12395 void *data, struct rte_flow_error *error)
12397 struct rte_flow_query_age *resp = data;
12398 struct mlx5_age_param *age_param;
12401 struct mlx5_aso_age_action *act =
12402 flow_aso_age_get_by_idx(dev, flow->age);
12404 age_param = &act->age_params;
12405 } else if (flow->counter) {
12406 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12408 if (!age_param || !age_param->timeout)
12409 return rte_flow_error_set
12411 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12412 NULL, "cannot read age data");
12414 return rte_flow_error_set(error, EINVAL,
12415 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12416 NULL, "age data not available");
12418 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12420 resp->sec_since_last_hit_valid = !resp->aged;
12421 if (resp->sec_since_last_hit_valid)
12422 resp->sec_since_last_hit = __atomic_load_n
12423 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12430 * @see rte_flow_query()
12431 * @see rte_flow_ops
12434 flow_dv_query(struct rte_eth_dev *dev,
12435 struct rte_flow *flow __rte_unused,
12436 const struct rte_flow_action *actions __rte_unused,
12437 void *data __rte_unused,
12438 struct rte_flow_error *error __rte_unused)
12442 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12443 switch (actions->type) {
12444 case RTE_FLOW_ACTION_TYPE_VOID:
12446 case RTE_FLOW_ACTION_TYPE_COUNT:
12447 ret = flow_dv_query_count(dev, flow, data, error);
12449 case RTE_FLOW_ACTION_TYPE_AGE:
12450 ret = flow_dv_query_age(dev, flow, data, error);
12453 return rte_flow_error_set(error, ENOTSUP,
12454 RTE_FLOW_ERROR_TYPE_ACTION,
12456 "action not supported");
12463 * Destroy the meter table set.
12464 * Lock free, (mutex should be acquired by caller).
12467 * Pointer to Ethernet device.
12469 * Pointer to the meter table set.
12475 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12476 struct mlx5_meter_domains_infos *tbl)
12478 struct mlx5_priv *priv = dev->data->dev_private;
12479 struct mlx5_meter_domains_infos *mtd =
12480 (struct mlx5_meter_domains_infos *)tbl;
12482 if (!mtd || !priv->config.dv_flow_en)
12484 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12485 claim_zero(mlx5_flow_os_destroy_flow
12486 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12487 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12488 claim_zero(mlx5_flow_os_destroy_flow
12489 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12490 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12491 claim_zero(mlx5_flow_os_destroy_flow
12492 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12493 if (mtd->egress.color_matcher)
12494 claim_zero(mlx5_flow_os_destroy_flow_matcher
12495 (mtd->egress.color_matcher));
12496 if (mtd->egress.any_matcher)
12497 claim_zero(mlx5_flow_os_destroy_flow_matcher
12498 (mtd->egress.any_matcher));
12499 if (mtd->egress.tbl)
12500 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12501 if (mtd->egress.sfx_tbl)
12502 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12503 if (mtd->ingress.color_matcher)
12504 claim_zero(mlx5_flow_os_destroy_flow_matcher
12505 (mtd->ingress.color_matcher));
12506 if (mtd->ingress.any_matcher)
12507 claim_zero(mlx5_flow_os_destroy_flow_matcher
12508 (mtd->ingress.any_matcher));
12509 if (mtd->ingress.tbl)
12510 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12511 if (mtd->ingress.sfx_tbl)
12512 flow_dv_tbl_resource_release(MLX5_SH(dev),
12513 mtd->ingress.sfx_tbl);
12514 if (mtd->transfer.color_matcher)
12515 claim_zero(mlx5_flow_os_destroy_flow_matcher
12516 (mtd->transfer.color_matcher));
12517 if (mtd->transfer.any_matcher)
12518 claim_zero(mlx5_flow_os_destroy_flow_matcher
12519 (mtd->transfer.any_matcher));
12520 if (mtd->transfer.tbl)
12521 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12522 if (mtd->transfer.sfx_tbl)
12523 flow_dv_tbl_resource_release(MLX5_SH(dev),
12524 mtd->transfer.sfx_tbl);
12525 if (mtd->drop_actn)
12526 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12531 /* Number of meter flow actions, count and jump or count and drop. */
12532 #define METER_ACTIONS 2
12535 * Create specify domain meter table and suffix table.
12538 * Pointer to Ethernet device.
12539 * @param[in,out] mtb
12540 * Pointer to DV meter table set.
12541 * @param[in] egress
12543 * @param[in] transfer
12545 * @param[in] color_reg_c_idx
12546 * Reg C index for color match.
12549 * 0 on success, -1 otherwise and rte_errno is set.
12552 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12553 struct mlx5_meter_domains_infos *mtb,
12554 uint8_t egress, uint8_t transfer,
12555 uint32_t color_reg_c_idx)
12557 struct mlx5_priv *priv = dev->data->dev_private;
12558 struct mlx5_dev_ctx_shared *sh = priv->sh;
12559 struct mlx5_flow_dv_match_params mask = {
12560 .size = sizeof(mask.buf),
12562 struct mlx5_flow_dv_match_params value = {
12563 .size = sizeof(value.buf),
12565 struct mlx5dv_flow_matcher_attr dv_attr = {
12566 .type = IBV_FLOW_ATTR_NORMAL,
12568 .match_criteria_enable = 0,
12569 .match_mask = (void *)&mask,
12571 void *actions[METER_ACTIONS];
12572 struct mlx5_meter_domain_info *dtb;
12573 struct rte_flow_error error;
12578 dtb = &mtb->transfer;
12580 dtb = &mtb->egress;
12582 dtb = &mtb->ingress;
12583 /* Create the meter table with METER level. */
12584 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12585 egress, transfer, false, NULL, 0,
12588 DRV_LOG(ERR, "Failed to create meter policer table.");
12591 /* Create the meter suffix table with SUFFIX level. */
12592 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12593 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12594 egress, transfer, false, NULL, 0,
12596 if (!dtb->sfx_tbl) {
12597 DRV_LOG(ERR, "Failed to create meter suffix table.");
12600 /* Create matchers, Any and Color. */
12601 dv_attr.priority = 3;
12602 dv_attr.match_criteria_enable = 0;
12603 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12604 &dtb->any_matcher);
12606 DRV_LOG(ERR, "Failed to create meter"
12607 " policer default matcher.");
12610 dv_attr.priority = 0;
12611 dv_attr.match_criteria_enable =
12612 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12613 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12614 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12615 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12616 &dtb->color_matcher);
12618 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12621 if (mtb->count_actns[RTE_MTR_DROPPED])
12622 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12623 actions[i++] = mtb->drop_actn;
12624 /* Default rule: lowest priority, match any, actions: drop. */
12625 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12627 &dtb->policer_rules[RTE_MTR_DROPPED]);
12629 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12638 * Create the needed meter and suffix tables.
12639 * Lock free, (mutex should be acquired by caller).
12642 * Pointer to Ethernet device.
12644 * Pointer to the flow meter.
12647 * Pointer to table set on success, NULL otherwise and rte_errno is set.
12649 static struct mlx5_meter_domains_infos *
12650 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12651 const struct mlx5_flow_meter *fm)
12653 struct mlx5_priv *priv = dev->data->dev_private;
12654 struct mlx5_meter_domains_infos *mtb;
12658 if (!priv->mtr_en) {
12659 rte_errno = ENOTSUP;
12662 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12664 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12667 /* Create meter count actions */
12668 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12669 struct mlx5_flow_counter *cnt;
12670 if (!fm->policer_stats.cnt[i])
12672 cnt = flow_dv_counter_get_by_idx(dev,
12673 fm->policer_stats.cnt[i], NULL);
12674 mtb->count_actns[i] = cnt->action;
12676 /* Create drop action. */
12677 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12679 DRV_LOG(ERR, "Failed to create drop action.");
12682 /* Egress meter table. */
12683 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12685 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12688 /* Ingress meter table. */
12689 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12691 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12694 /* FDB meter table. */
12695 if (priv->config.dv_esw_en) {
12696 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12697 priv->mtr_color_reg);
12699 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12705 flow_dv_destroy_mtr_tbl(dev, mtb);
12710 * Destroy domain policer rule.
12713 * Pointer to domain table.
12716 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12720 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12721 if (dt->policer_rules[i]) {
12722 claim_zero(mlx5_flow_os_destroy_flow
12723 (dt->policer_rules[i]));
12724 dt->policer_rules[i] = NULL;
12727 if (dt->jump_actn) {
12728 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12729 dt->jump_actn = NULL;
12734 * Destroy policer rules.
12737 * Pointer to Ethernet device.
12739 * Pointer to flow meter structure.
12741 * Pointer to flow attributes.
12747 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12748 const struct mlx5_flow_meter *fm,
12749 const struct rte_flow_attr *attr)
12751 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12756 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12758 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12759 if (attr->transfer)
12760 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12765 * Create specify domain meter policer rule.
12768 * Pointer to flow meter structure.
12770 * Pointer to DV meter table set.
12771 * @param[in] mtr_reg_c
12772 * Color match REG_C.
12775 * 0 on success, -1 otherwise.
12778 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12779 struct mlx5_meter_domain_info *dtb,
12782 struct mlx5_flow_dv_match_params matcher = {
12783 .size = sizeof(matcher.buf),
12785 struct mlx5_flow_dv_match_params value = {
12786 .size = sizeof(value.buf),
12788 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12789 void *actions[METER_ACTIONS];
12793 /* Create jump action. */
12794 if (!dtb->jump_actn)
12795 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12796 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12798 DRV_LOG(ERR, "Failed to create policer jump action.");
12801 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12804 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12805 rte_col_2_mlx5_col(i), UINT8_MAX);
12806 if (mtb->count_actns[i])
12807 actions[j++] = mtb->count_actns[i];
12808 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12809 actions[j++] = mtb->drop_actn;
12811 actions[j++] = dtb->jump_actn;
12812 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12813 (void *)&value, j, actions,
12814 &dtb->policer_rules[i]);
12816 DRV_LOG(ERR, "Failed to create policer rule.");
12827 * Create policer rules.
12830 * Pointer to Ethernet device.
12832 * Pointer to flow meter structure.
12834 * Pointer to flow attributes.
12837 * 0 on success, -1 otherwise.
12840 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12841 struct mlx5_flow_meter *fm,
12842 const struct rte_flow_attr *attr)
12844 struct mlx5_priv *priv = dev->data->dev_private;
12845 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12848 if (attr->egress) {
12849 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12850 priv->mtr_color_reg);
12852 DRV_LOG(ERR, "Failed to create egress policer.");
12856 if (attr->ingress) {
12857 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12858 priv->mtr_color_reg);
12860 DRV_LOG(ERR, "Failed to create ingress policer.");
12864 if (attr->transfer) {
12865 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12866 priv->mtr_color_reg);
12868 DRV_LOG(ERR, "Failed to create transfer policer.");
12874 flow_dv_destroy_policer_rules(dev, fm, attr);
12879 * Validate the batch counter support in root table.
12881 * Create a simple flow with invalid counter and drop action on root table to
12882 * validate if batch counter with offset on root table is supported or not.
12885 * Pointer to rte_eth_dev structure.
12888 * 0 on success, a negative errno value otherwise and rte_errno is set.
12891 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12893 struct mlx5_priv *priv = dev->data->dev_private;
12894 struct mlx5_dev_ctx_shared *sh = priv->sh;
12895 struct mlx5_flow_dv_match_params mask = {
12896 .size = sizeof(mask.buf),
12898 struct mlx5_flow_dv_match_params value = {
12899 .size = sizeof(value.buf),
12901 struct mlx5dv_flow_matcher_attr dv_attr = {
12902 .type = IBV_FLOW_ATTR_NORMAL,
12904 .match_criteria_enable = 0,
12905 .match_mask = (void *)&mask,
12907 void *actions[2] = { 0 };
12908 struct mlx5_flow_tbl_resource *tbl = NULL;
12909 struct mlx5_devx_obj *dcs = NULL;
12910 void *matcher = NULL;
12914 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12917 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12920 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12924 actions[1] = priv->drop_queue.hrxq->action;
12925 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12926 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12930 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12934 * If batch counter with offset is not supported, the driver will not
12935 * validate the invalid offset value, flow create should success.
12936 * In this case, it means batch counter is not supported in root table.
12938 * Otherwise, if flow create is failed, counter offset is supported.
12941 DRV_LOG(INFO, "Batch counter is not supported in root "
12942 "table. Switch to fallback mode.");
12943 rte_errno = ENOTSUP;
12945 claim_zero(mlx5_flow_os_destroy_flow(flow));
12947 /* Check matcher to make sure validate fail at flow create. */
12948 if (!matcher || (matcher && errno != EINVAL))
12949 DRV_LOG(ERR, "Unexpected error in counter offset "
12950 "support detection");
12954 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12956 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12958 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12960 claim_zero(mlx5_devx_cmd_destroy(dcs));
12965 * Query a devx counter.
12968 * Pointer to the Ethernet device structure.
12970 * Index to the flow counter.
12972 * Set to clear the counter statistics.
12974 * The statistics value of packets.
12975 * @param[out] bytes
12976 * The statistics value of bytes.
12979 * 0 on success, otherwise return -1.
12982 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12983 uint64_t *pkts, uint64_t *bytes)
12985 struct mlx5_priv *priv = dev->data->dev_private;
12986 struct mlx5_flow_counter *cnt;
12987 uint64_t inn_pkts, inn_bytes;
12990 if (!priv->config.devx)
12993 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12996 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12997 *pkts = inn_pkts - cnt->hits;
12998 *bytes = inn_bytes - cnt->bytes;
13000 cnt->hits = inn_pkts;
13001 cnt->bytes = inn_bytes;
13007 * Get aged-out flows.
13010 * Pointer to the Ethernet device structure.
13011 * @param[in] context
13012 * The address of an array of pointers to the aged-out flows contexts.
13013 * @param[in] nb_contexts
13014 * The length of context array pointers.
13015 * @param[out] error
13016 * Perform verbose error reporting if not NULL. Initialized in case of
13020 * how many contexts get in success, otherwise negative errno value.
13021 * if nb_contexts is 0, return the amount of all aged contexts.
13022 * if nb_contexts is not 0 , return the amount of aged flows reported
13023 * in the context array.
13024 * @note: only stub for now
13027 flow_get_aged_flows(struct rte_eth_dev *dev,
13029 uint32_t nb_contexts,
13030 struct rte_flow_error *error)
13032 struct mlx5_priv *priv = dev->data->dev_private;
13033 struct mlx5_age_info *age_info;
13034 struct mlx5_age_param *age_param;
13035 struct mlx5_flow_counter *counter;
13036 struct mlx5_aso_age_action *act;
13039 if (nb_contexts && !context)
13040 return rte_flow_error_set(error, EINVAL,
13041 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13042 NULL, "empty context");
13043 age_info = GET_PORT_AGE_INFO(priv);
13044 rte_spinlock_lock(&age_info->aged_sl);
13045 LIST_FOREACH(act, &age_info->aged_aso, next) {
13048 context[nb_flows - 1] =
13049 act->age_params.context;
13050 if (!(--nb_contexts))
13054 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13057 age_param = MLX5_CNT_TO_AGE(counter);
13058 context[nb_flows - 1] = age_param->context;
13059 if (!(--nb_contexts))
13063 rte_spinlock_unlock(&age_info->aged_sl);
13064 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13069 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13072 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13074 return flow_dv_counter_alloc(dev, 0);
13078 * Validate shared action.
13079 * Dispatcher for action type specific validation.
13082 * Pointer to the Ethernet device structure.
13084 * Shared action configuration.
13085 * @param[in] action
13086 * The shared action object to validate.
13087 * @param[out] error
13088 * Perform verbose error reporting if not NULL. Initialized in case of
13092 * 0 on success, otherwise negative errno value.
13095 flow_dv_action_validate(struct rte_eth_dev *dev,
13096 const struct rte_flow_shared_action_conf *conf,
13097 const struct rte_flow_action *action,
13098 struct rte_flow_error *err)
13100 struct mlx5_priv *priv = dev->data->dev_private;
13102 RTE_SET_USED(conf);
13103 switch (action->type) {
13104 case RTE_FLOW_ACTION_TYPE_RSS:
13105 return mlx5_validate_action_rss(dev, action, err);
13106 case RTE_FLOW_ACTION_TYPE_AGE:
13107 if (!priv->sh->aso_age_mng)
13108 return rte_flow_error_set(err, ENOTSUP,
13109 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13111 "shared age action not supported");
13112 return flow_dv_validate_action_age(0, action, dev, err);
13114 return rte_flow_error_set(err, ENOTSUP,
13115 RTE_FLOW_ERROR_TYPE_ACTION,
13117 "action type not supported");
13122 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13124 struct mlx5_priv *priv = dev->data->dev_private;
13127 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13128 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13133 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13134 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13138 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13139 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13146 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13147 .validate = flow_dv_validate,
13148 .prepare = flow_dv_prepare,
13149 .translate = flow_dv_translate,
13150 .apply = flow_dv_apply,
13151 .remove = flow_dv_remove,
13152 .destroy = flow_dv_destroy,
13153 .query = flow_dv_query,
13154 .create_mtr_tbls = flow_dv_create_mtr_tbl,
13155 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13156 .create_policer_rules = flow_dv_create_policer_rules,
13157 .destroy_policer_rules = flow_dv_destroy_policer_rules,
13158 .counter_alloc = flow_dv_counter_allocate,
13159 .counter_free = flow_dv_counter_free,
13160 .counter_query = flow_dv_counter_query,
13161 .get_aged_flows = flow_get_aged_flows,
13162 .action_validate = flow_dv_action_validate,
13163 .action_create = flow_dv_action_create,
13164 .action_destroy = flow_dv_action_destroy,
13165 .action_update = flow_dv_action_update,
13166 .action_query = flow_dv_action_query,
13167 .sync_domain = flow_dv_sync_domain,
13170 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */