1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
58 sizeof(struct rte_flow_item_ipv4))
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 * Initialize flow attributes structure according to flow items' types.
81 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
82 * mode. For tunnel mode, the items to be modified are the outermost ones.
85 * Pointer to item specification.
87 * Pointer to flow attributes structure.
90 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
92 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
94 case RTE_FLOW_ITEM_TYPE_IPV4:
98 case RTE_FLOW_ITEM_TYPE_IPV6:
102 case RTE_FLOW_ITEM_TYPE_UDP:
106 case RTE_FLOW_ITEM_TYPE_TCP:
118 * Convert rte_mtr_color to mlx5 color.
127 rte_col_2_mlx5_col(enum rte_color rcol)
130 case RTE_COLOR_GREEN:
131 return MLX5_FLOW_COLOR_GREEN;
132 case RTE_COLOR_YELLOW:
133 return MLX5_FLOW_COLOR_YELLOW;
135 return MLX5_FLOW_COLOR_RED;
139 return MLX5_FLOW_COLOR_UNDEFINED;
142 struct field_modify_info {
143 uint32_t size; /* Size of field in protocol header, in bytes. */
144 uint32_t offset; /* Offset of field in protocol header, in bytes. */
145 enum mlx5_modification_field id;
148 struct field_modify_info modify_eth[] = {
149 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
150 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
151 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
152 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
156 struct field_modify_info modify_vlan_out_first_vid[] = {
157 /* Size in bits !!! */
158 {12, 0, MLX5_MODI_OUT_FIRST_VID},
162 struct field_modify_info modify_ipv4[] = {
163 {1, 1, MLX5_MODI_OUT_IP_DSCP},
164 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
165 {4, 12, MLX5_MODI_OUT_SIPV4},
166 {4, 16, MLX5_MODI_OUT_DIPV4},
170 struct field_modify_info modify_ipv6[] = {
171 {1, 0, MLX5_MODI_OUT_IP_DSCP},
172 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
173 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
174 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
175 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
176 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
177 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
178 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
179 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
180 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
184 struct field_modify_info modify_udp[] = {
185 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
186 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
190 struct field_modify_info modify_tcp[] = {
191 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
192 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
193 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
194 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
199 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
200 uint8_t next_protocol, uint64_t *item_flags,
203 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
204 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
205 if (next_protocol == IPPROTO_IPIP) {
206 *item_flags |= MLX5_FLOW_LAYER_IPIP;
209 if (next_protocol == IPPROTO_IPV6) {
210 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
216 * Acquire the synchronizing object to protect multithreaded access
217 * to shared dv context. Lock occurs only if context is actually
218 * shared, i.e. we have multiport IB device and representors are
222 * Pointer to the rte_eth_dev structure.
225 flow_dv_shared_lock(struct rte_eth_dev *dev)
227 struct mlx5_priv *priv = dev->data->dev_private;
228 struct mlx5_ibv_shared *sh = priv->sh;
230 if (sh->dv_refcnt > 1) {
233 ret = pthread_mutex_lock(&sh->dv_mutex);
240 flow_dv_shared_unlock(struct rte_eth_dev *dev)
242 struct mlx5_priv *priv = dev->data->dev_private;
243 struct mlx5_ibv_shared *sh = priv->sh;
245 if (sh->dv_refcnt > 1) {
248 ret = pthread_mutex_unlock(&sh->dv_mutex);
254 /* Update VLAN's VID/PCP based on input rte_flow_action.
257 * Pointer to struct rte_flow_action.
259 * Pointer to struct rte_vlan_hdr.
262 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
263 struct rte_vlan_hdr *vlan)
266 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
268 ((const struct rte_flow_action_of_set_vlan_pcp *)
269 action->conf)->vlan_pcp;
270 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
271 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
272 vlan->vlan_tci |= vlan_tci;
273 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
274 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
275 vlan->vlan_tci |= rte_be_to_cpu_16
276 (((const struct rte_flow_action_of_set_vlan_vid *)
277 action->conf)->vlan_vid);
282 * Fetch 1, 2, 3 or 4 byte field from the byte array
283 * and return as unsigned integer in host-endian format.
286 * Pointer to data array.
288 * Size of field to extract.
291 * converted field in host endian format.
293 static inline uint32_t
294 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
303 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
306 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
307 ret = (ret << 8) | *(data + sizeof(uint16_t));
310 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
321 * Convert modify-header action to DV specification.
323 * Data length of each action is determined by provided field description
324 * and the item mask. Data bit offset and width of each action is determined
325 * by provided item mask.
328 * Pointer to item specification.
330 * Pointer to field modification information.
331 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
332 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
333 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
335 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
336 * Negative offset value sets the same offset as source offset.
337 * size field is ignored, value is taken from source field.
338 * @param[in,out] resource
339 * Pointer to the modify-header resource.
341 * Type of modification.
343 * Pointer to the error structure.
346 * 0 on success, a negative errno value otherwise and rte_errno is set.
349 flow_dv_convert_modify_action(struct rte_flow_item *item,
350 struct field_modify_info *field,
351 struct field_modify_info *dcopy,
352 struct mlx5_flow_dv_modify_hdr_resource *resource,
353 uint32_t type, struct rte_flow_error *error)
355 uint32_t i = resource->actions_num;
356 struct mlx5_modification_cmd *actions = resource->actions;
359 * The item and mask are provided in big-endian format.
360 * The fields should be presented as in big-endian format either.
361 * Mask must be always present, it defines the actual field width.
363 MLX5_ASSERT(item->mask);
364 MLX5_ASSERT(field->size);
371 if (i >= MLX5_MAX_MODIFY_NUM)
372 return rte_flow_error_set(error, EINVAL,
373 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
374 "too many items to modify");
375 /* Fetch variable byte size mask from the array. */
376 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
377 field->offset, field->size);
382 /* Deduce actual data width in bits from mask value. */
383 off_b = rte_bsf32(mask);
384 size_b = sizeof(uint32_t) * CHAR_BIT -
385 off_b - __builtin_clz(mask);
387 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
388 actions[i] = (struct mlx5_modification_cmd) {
394 /* Convert entire record to expected big-endian format. */
395 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
396 if (type == MLX5_MODIFICATION_TYPE_COPY) {
398 actions[i].dst_field = dcopy->id;
399 actions[i].dst_offset =
400 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
401 /* Convert entire record to big-endian format. */
402 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
404 MLX5_ASSERT(item->spec);
405 data = flow_dv_fetch_field((const uint8_t *)item->spec +
406 field->offset, field->size);
407 /* Shift out the trailing masked bits from data. */
408 data = (data & mask) >> off_b;
409 actions[i].data1 = rte_cpu_to_be_32(data);
413 } while (field->size);
414 if (resource->actions_num == i)
415 return rte_flow_error_set(error, EINVAL,
416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
417 "invalid modification flow item");
418 resource->actions_num = i;
423 * Convert modify-header set IPv4 address action to DV specification.
425 * @param[in,out] resource
426 * Pointer to the modify-header resource.
428 * Pointer to action specification.
430 * Pointer to the error structure.
433 * 0 on success, a negative errno value otherwise and rte_errno is set.
436 flow_dv_convert_action_modify_ipv4
437 (struct mlx5_flow_dv_modify_hdr_resource *resource,
438 const struct rte_flow_action *action,
439 struct rte_flow_error *error)
441 const struct rte_flow_action_set_ipv4 *conf =
442 (const struct rte_flow_action_set_ipv4 *)(action->conf);
443 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
444 struct rte_flow_item_ipv4 ipv4;
445 struct rte_flow_item_ipv4 ipv4_mask;
447 memset(&ipv4, 0, sizeof(ipv4));
448 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
449 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
450 ipv4.hdr.src_addr = conf->ipv4_addr;
451 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
453 ipv4.hdr.dst_addr = conf->ipv4_addr;
454 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
457 item.mask = &ipv4_mask;
458 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
459 MLX5_MODIFICATION_TYPE_SET, error);
463 * Convert modify-header set IPv6 address action to DV specification.
465 * @param[in,out] resource
466 * Pointer to the modify-header resource.
468 * Pointer to action specification.
470 * Pointer to the error structure.
473 * 0 on success, a negative errno value otherwise and rte_errno is set.
476 flow_dv_convert_action_modify_ipv6
477 (struct mlx5_flow_dv_modify_hdr_resource *resource,
478 const struct rte_flow_action *action,
479 struct rte_flow_error *error)
481 const struct rte_flow_action_set_ipv6 *conf =
482 (const struct rte_flow_action_set_ipv6 *)(action->conf);
483 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
484 struct rte_flow_item_ipv6 ipv6;
485 struct rte_flow_item_ipv6 ipv6_mask;
487 memset(&ipv6, 0, sizeof(ipv6));
488 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
489 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
490 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
491 sizeof(ipv6.hdr.src_addr));
492 memcpy(&ipv6_mask.hdr.src_addr,
493 &rte_flow_item_ipv6_mask.hdr.src_addr,
494 sizeof(ipv6.hdr.src_addr));
496 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
497 sizeof(ipv6.hdr.dst_addr));
498 memcpy(&ipv6_mask.hdr.dst_addr,
499 &rte_flow_item_ipv6_mask.hdr.dst_addr,
500 sizeof(ipv6.hdr.dst_addr));
503 item.mask = &ipv6_mask;
504 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
505 MLX5_MODIFICATION_TYPE_SET, error);
509 * Convert modify-header set MAC address action to DV specification.
511 * @param[in,out] resource
512 * Pointer to the modify-header resource.
514 * Pointer to action specification.
516 * Pointer to the error structure.
519 * 0 on success, a negative errno value otherwise and rte_errno is set.
522 flow_dv_convert_action_modify_mac
523 (struct mlx5_flow_dv_modify_hdr_resource *resource,
524 const struct rte_flow_action *action,
525 struct rte_flow_error *error)
527 const struct rte_flow_action_set_mac *conf =
528 (const struct rte_flow_action_set_mac *)(action->conf);
529 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
530 struct rte_flow_item_eth eth;
531 struct rte_flow_item_eth eth_mask;
533 memset(ð, 0, sizeof(eth));
534 memset(ð_mask, 0, sizeof(eth_mask));
535 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
536 memcpy(ð.src.addr_bytes, &conf->mac_addr,
537 sizeof(eth.src.addr_bytes));
538 memcpy(ð_mask.src.addr_bytes,
539 &rte_flow_item_eth_mask.src.addr_bytes,
540 sizeof(eth_mask.src.addr_bytes));
542 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
543 sizeof(eth.dst.addr_bytes));
544 memcpy(ð_mask.dst.addr_bytes,
545 &rte_flow_item_eth_mask.dst.addr_bytes,
546 sizeof(eth_mask.dst.addr_bytes));
549 item.mask = ð_mask;
550 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
551 MLX5_MODIFICATION_TYPE_SET, error);
555 * Convert modify-header set VLAN VID action to DV specification.
557 * @param[in,out] resource
558 * Pointer to the modify-header resource.
560 * Pointer to action specification.
562 * Pointer to the error structure.
565 * 0 on success, a negative errno value otherwise and rte_errno is set.
568 flow_dv_convert_action_modify_vlan_vid
569 (struct mlx5_flow_dv_modify_hdr_resource *resource,
570 const struct rte_flow_action *action,
571 struct rte_flow_error *error)
573 const struct rte_flow_action_of_set_vlan_vid *conf =
574 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
575 int i = resource->actions_num;
576 struct mlx5_modification_cmd *actions = resource->actions;
577 struct field_modify_info *field = modify_vlan_out_first_vid;
579 if (i >= MLX5_MAX_MODIFY_NUM)
580 return rte_flow_error_set(error, EINVAL,
581 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
582 "too many items to modify");
583 actions[i] = (struct mlx5_modification_cmd) {
584 .action_type = MLX5_MODIFICATION_TYPE_SET,
586 .length = field->size,
587 .offset = field->offset,
589 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
590 actions[i].data1 = conf->vlan_vid;
591 actions[i].data1 = actions[i].data1 << 16;
592 resource->actions_num = ++i;
597 * Convert modify-header set TP action to DV specification.
599 * @param[in,out] resource
600 * Pointer to the modify-header resource.
602 * Pointer to action specification.
604 * Pointer to rte_flow_item objects list.
606 * Pointer to flow attributes structure.
608 * Pointer to the error structure.
611 * 0 on success, a negative errno value otherwise and rte_errno is set.
614 flow_dv_convert_action_modify_tp
615 (struct mlx5_flow_dv_modify_hdr_resource *resource,
616 const struct rte_flow_action *action,
617 const struct rte_flow_item *items,
618 union flow_dv_attr *attr,
619 struct rte_flow_error *error)
621 const struct rte_flow_action_set_tp *conf =
622 (const struct rte_flow_action_set_tp *)(action->conf);
623 struct rte_flow_item item;
624 struct rte_flow_item_udp udp;
625 struct rte_flow_item_udp udp_mask;
626 struct rte_flow_item_tcp tcp;
627 struct rte_flow_item_tcp tcp_mask;
628 struct field_modify_info *field;
631 flow_dv_attr_init(items, attr);
633 memset(&udp, 0, sizeof(udp));
634 memset(&udp_mask, 0, sizeof(udp_mask));
635 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
636 udp.hdr.src_port = conf->port;
637 udp_mask.hdr.src_port =
638 rte_flow_item_udp_mask.hdr.src_port;
640 udp.hdr.dst_port = conf->port;
641 udp_mask.hdr.dst_port =
642 rte_flow_item_udp_mask.hdr.dst_port;
644 item.type = RTE_FLOW_ITEM_TYPE_UDP;
646 item.mask = &udp_mask;
650 memset(&tcp, 0, sizeof(tcp));
651 memset(&tcp_mask, 0, sizeof(tcp_mask));
652 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
653 tcp.hdr.src_port = conf->port;
654 tcp_mask.hdr.src_port =
655 rte_flow_item_tcp_mask.hdr.src_port;
657 tcp.hdr.dst_port = conf->port;
658 tcp_mask.hdr.dst_port =
659 rte_flow_item_tcp_mask.hdr.dst_port;
661 item.type = RTE_FLOW_ITEM_TYPE_TCP;
663 item.mask = &tcp_mask;
666 return flow_dv_convert_modify_action(&item, field, NULL, resource,
667 MLX5_MODIFICATION_TYPE_SET, error);
671 * Convert modify-header set TTL action to DV specification.
673 * @param[in,out] resource
674 * Pointer to the modify-header resource.
676 * Pointer to action specification.
678 * Pointer to rte_flow_item objects list.
680 * Pointer to flow attributes structure.
682 * Pointer to the error structure.
685 * 0 on success, a negative errno value otherwise and rte_errno is set.
688 flow_dv_convert_action_modify_ttl
689 (struct mlx5_flow_dv_modify_hdr_resource *resource,
690 const struct rte_flow_action *action,
691 const struct rte_flow_item *items,
692 union flow_dv_attr *attr,
693 struct rte_flow_error *error)
695 const struct rte_flow_action_set_ttl *conf =
696 (const struct rte_flow_action_set_ttl *)(action->conf);
697 struct rte_flow_item item;
698 struct rte_flow_item_ipv4 ipv4;
699 struct rte_flow_item_ipv4 ipv4_mask;
700 struct rte_flow_item_ipv6 ipv6;
701 struct rte_flow_item_ipv6 ipv6_mask;
702 struct field_modify_info *field;
705 flow_dv_attr_init(items, attr);
707 memset(&ipv4, 0, sizeof(ipv4));
708 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
709 ipv4.hdr.time_to_live = conf->ttl_value;
710 ipv4_mask.hdr.time_to_live = 0xFF;
711 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
713 item.mask = &ipv4_mask;
717 memset(&ipv6, 0, sizeof(ipv6));
718 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
719 ipv6.hdr.hop_limits = conf->ttl_value;
720 ipv6_mask.hdr.hop_limits = 0xFF;
721 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
723 item.mask = &ipv6_mask;
726 return flow_dv_convert_modify_action(&item, field, NULL, resource,
727 MLX5_MODIFICATION_TYPE_SET, error);
731 * Convert modify-header decrement TTL action to DV specification.
733 * @param[in,out] resource
734 * Pointer to the modify-header resource.
736 * Pointer to action specification.
738 * Pointer to rte_flow_item objects list.
740 * Pointer to flow attributes structure.
742 * Pointer to the error structure.
745 * 0 on success, a negative errno value otherwise and rte_errno is set.
748 flow_dv_convert_action_modify_dec_ttl
749 (struct mlx5_flow_dv_modify_hdr_resource *resource,
750 const struct rte_flow_item *items,
751 union flow_dv_attr *attr,
752 struct rte_flow_error *error)
754 struct rte_flow_item item;
755 struct rte_flow_item_ipv4 ipv4;
756 struct rte_flow_item_ipv4 ipv4_mask;
757 struct rte_flow_item_ipv6 ipv6;
758 struct rte_flow_item_ipv6 ipv6_mask;
759 struct field_modify_info *field;
762 flow_dv_attr_init(items, attr);
764 memset(&ipv4, 0, sizeof(ipv4));
765 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
766 ipv4.hdr.time_to_live = 0xFF;
767 ipv4_mask.hdr.time_to_live = 0xFF;
768 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
770 item.mask = &ipv4_mask;
774 memset(&ipv6, 0, sizeof(ipv6));
775 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
776 ipv6.hdr.hop_limits = 0xFF;
777 ipv6_mask.hdr.hop_limits = 0xFF;
778 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
780 item.mask = &ipv6_mask;
783 return flow_dv_convert_modify_action(&item, field, NULL, resource,
784 MLX5_MODIFICATION_TYPE_ADD, error);
788 * Convert modify-header increment/decrement TCP Sequence number
789 * to DV specification.
791 * @param[in,out] resource
792 * Pointer to the modify-header resource.
794 * Pointer to action specification.
796 * Pointer to the error structure.
799 * 0 on success, a negative errno value otherwise and rte_errno is set.
802 flow_dv_convert_action_modify_tcp_seq
803 (struct mlx5_flow_dv_modify_hdr_resource *resource,
804 const struct rte_flow_action *action,
805 struct rte_flow_error *error)
807 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
808 uint64_t value = rte_be_to_cpu_32(*conf);
809 struct rte_flow_item item;
810 struct rte_flow_item_tcp tcp;
811 struct rte_flow_item_tcp tcp_mask;
813 memset(&tcp, 0, sizeof(tcp));
814 memset(&tcp_mask, 0, sizeof(tcp_mask));
815 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
817 * The HW has no decrement operation, only increment operation.
818 * To simulate decrement X from Y using increment operation
819 * we need to add UINT32_MAX X times to Y.
820 * Each adding of UINT32_MAX decrements Y by 1.
823 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
824 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
825 item.type = RTE_FLOW_ITEM_TYPE_TCP;
827 item.mask = &tcp_mask;
828 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
829 MLX5_MODIFICATION_TYPE_ADD, error);
833 * Convert modify-header increment/decrement TCP Acknowledgment number
834 * to DV specification.
836 * @param[in,out] resource
837 * Pointer to the modify-header resource.
839 * Pointer to action specification.
841 * Pointer to the error structure.
844 * 0 on success, a negative errno value otherwise and rte_errno is set.
847 flow_dv_convert_action_modify_tcp_ack
848 (struct mlx5_flow_dv_modify_hdr_resource *resource,
849 const struct rte_flow_action *action,
850 struct rte_flow_error *error)
852 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
853 uint64_t value = rte_be_to_cpu_32(*conf);
854 struct rte_flow_item item;
855 struct rte_flow_item_tcp tcp;
856 struct rte_flow_item_tcp tcp_mask;
858 memset(&tcp, 0, sizeof(tcp));
859 memset(&tcp_mask, 0, sizeof(tcp_mask));
860 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
862 * The HW has no decrement operation, only increment operation.
863 * To simulate decrement X from Y using increment operation
864 * we need to add UINT32_MAX X times to Y.
865 * Each adding of UINT32_MAX decrements Y by 1.
868 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
869 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
870 item.type = RTE_FLOW_ITEM_TYPE_TCP;
872 item.mask = &tcp_mask;
873 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
874 MLX5_MODIFICATION_TYPE_ADD, error);
877 static enum mlx5_modification_field reg_to_field[] = {
878 [REG_NONE] = MLX5_MODI_OUT_NONE,
879 [REG_A] = MLX5_MODI_META_DATA_REG_A,
880 [REG_B] = MLX5_MODI_META_DATA_REG_B,
881 [REG_C_0] = MLX5_MODI_META_REG_C_0,
882 [REG_C_1] = MLX5_MODI_META_REG_C_1,
883 [REG_C_2] = MLX5_MODI_META_REG_C_2,
884 [REG_C_3] = MLX5_MODI_META_REG_C_3,
885 [REG_C_4] = MLX5_MODI_META_REG_C_4,
886 [REG_C_5] = MLX5_MODI_META_REG_C_5,
887 [REG_C_6] = MLX5_MODI_META_REG_C_6,
888 [REG_C_7] = MLX5_MODI_META_REG_C_7,
892 * Convert register set to DV specification.
894 * @param[in,out] resource
895 * Pointer to the modify-header resource.
897 * Pointer to action specification.
899 * Pointer to the error structure.
902 * 0 on success, a negative errno value otherwise and rte_errno is set.
905 flow_dv_convert_action_set_reg
906 (struct mlx5_flow_dv_modify_hdr_resource *resource,
907 const struct rte_flow_action *action,
908 struct rte_flow_error *error)
910 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
911 struct mlx5_modification_cmd *actions = resource->actions;
912 uint32_t i = resource->actions_num;
914 if (i >= MLX5_MAX_MODIFY_NUM)
915 return rte_flow_error_set(error, EINVAL,
916 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
917 "too many items to modify");
918 MLX5_ASSERT(conf->id != REG_NONE);
919 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
920 actions[i] = (struct mlx5_modification_cmd) {
921 .action_type = MLX5_MODIFICATION_TYPE_SET,
922 .field = reg_to_field[conf->id],
924 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
925 actions[i].data1 = rte_cpu_to_be_32(conf->data);
927 resource->actions_num = i;
932 * Convert SET_TAG action to DV specification.
935 * Pointer to the rte_eth_dev structure.
936 * @param[in,out] resource
937 * Pointer to the modify-header resource.
939 * Pointer to action specification.
941 * Pointer to the error structure.
944 * 0 on success, a negative errno value otherwise and rte_errno is set.
947 flow_dv_convert_action_set_tag
948 (struct rte_eth_dev *dev,
949 struct mlx5_flow_dv_modify_hdr_resource *resource,
950 const struct rte_flow_action_set_tag *conf,
951 struct rte_flow_error *error)
953 rte_be32_t data = rte_cpu_to_be_32(conf->data);
954 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
955 struct rte_flow_item item = {
959 struct field_modify_info reg_c_x[] = {
962 enum mlx5_modification_field reg_type;
965 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
968 MLX5_ASSERT(ret != REG_NONE);
969 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
970 reg_type = reg_to_field[ret];
971 MLX5_ASSERT(reg_type > 0);
972 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
973 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
974 MLX5_MODIFICATION_TYPE_SET, error);
978 * Convert internal COPY_REG action to DV specification.
981 * Pointer to the rte_eth_dev structure.
983 * Pointer to the modify-header resource.
985 * Pointer to action specification.
987 * Pointer to the error structure.
990 * 0 on success, a negative errno value otherwise and rte_errno is set.
993 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
994 struct mlx5_flow_dv_modify_hdr_resource *res,
995 const struct rte_flow_action *action,
996 struct rte_flow_error *error)
998 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
999 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1000 struct rte_flow_item item = {
1004 struct field_modify_info reg_src[] = {
1005 {4, 0, reg_to_field[conf->src]},
1008 struct field_modify_info reg_dst = {
1010 .id = reg_to_field[conf->dst],
1012 /* Adjust reg_c[0] usage according to reported mask. */
1013 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1014 struct mlx5_priv *priv = dev->data->dev_private;
1015 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1017 MLX5_ASSERT(reg_c0);
1018 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1019 if (conf->dst == REG_C_0) {
1020 /* Copy to reg_c[0], within mask only. */
1021 reg_dst.offset = rte_bsf32(reg_c0);
1023 * Mask is ignoring the enianness, because
1024 * there is no conversion in datapath.
1026 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1027 /* Copy from destination lower bits to reg_c[0]. */
1028 mask = reg_c0 >> reg_dst.offset;
1030 /* Copy from destination upper bits to reg_c[0]. */
1031 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1032 rte_fls_u32(reg_c0));
1035 mask = rte_cpu_to_be_32(reg_c0);
1036 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1037 /* Copy from reg_c[0] to destination lower bits. */
1040 /* Copy from reg_c[0] to destination upper bits. */
1041 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1042 (rte_fls_u32(reg_c0) -
1047 return flow_dv_convert_modify_action(&item,
1048 reg_src, ®_dst, res,
1049 MLX5_MODIFICATION_TYPE_COPY,
1054 * Convert MARK action to DV specification. This routine is used
1055 * in extensive metadata only and requires metadata register to be
1056 * handled. In legacy mode hardware tag resource is engaged.
1059 * Pointer to the rte_eth_dev structure.
1061 * Pointer to MARK action specification.
1062 * @param[in,out] resource
1063 * Pointer to the modify-header resource.
1065 * Pointer to the error structure.
1068 * 0 on success, a negative errno value otherwise and rte_errno is set.
1071 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1072 const struct rte_flow_action_mark *conf,
1073 struct mlx5_flow_dv_modify_hdr_resource *resource,
1074 struct rte_flow_error *error)
1076 struct mlx5_priv *priv = dev->data->dev_private;
1077 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1078 priv->sh->dv_mark_mask);
1079 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1080 struct rte_flow_item item = {
1084 struct field_modify_info reg_c_x[] = {
1085 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1091 return rte_flow_error_set(error, EINVAL,
1092 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1093 NULL, "zero mark action mask");
1094 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1097 MLX5_ASSERT(reg > 0);
1098 if (reg == REG_C_0) {
1099 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1100 uint32_t shl_c0 = rte_bsf32(msk_c0);
1102 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1103 mask = rte_cpu_to_be_32(mask) & msk_c0;
1104 mask = rte_cpu_to_be_32(mask << shl_c0);
1106 reg_c_x[0].id = reg_to_field[reg];
1107 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1108 MLX5_MODIFICATION_TYPE_SET, error);
1112 * Get metadata register index for specified steering domain.
1115 * Pointer to the rte_eth_dev structure.
1117 * Attributes of flow to determine steering domain.
1119 * Pointer to the error structure.
1122 * positive index on success, a negative errno value otherwise
1123 * and rte_errno is set.
1125 static enum modify_reg
1126 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1127 const struct rte_flow_attr *attr,
1128 struct rte_flow_error *error)
1131 mlx5_flow_get_reg_id(dev, attr->transfer ?
1135 MLX5_METADATA_RX, 0, error);
1137 return rte_flow_error_set(error,
1138 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1139 NULL, "unavailable "
1140 "metadata register");
1145 * Convert SET_META action to DV specification.
1148 * Pointer to the rte_eth_dev structure.
1149 * @param[in,out] resource
1150 * Pointer to the modify-header resource.
1152 * Attributes of flow that includes this item.
1154 * Pointer to action specification.
1156 * Pointer to the error structure.
1159 * 0 on success, a negative errno value otherwise and rte_errno is set.
1162 flow_dv_convert_action_set_meta
1163 (struct rte_eth_dev *dev,
1164 struct mlx5_flow_dv_modify_hdr_resource *resource,
1165 const struct rte_flow_attr *attr,
1166 const struct rte_flow_action_set_meta *conf,
1167 struct rte_flow_error *error)
1169 uint32_t data = conf->data;
1170 uint32_t mask = conf->mask;
1171 struct rte_flow_item item = {
1175 struct field_modify_info reg_c_x[] = {
1178 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1183 * In datapath code there is no endianness
1184 * coversions for perfromance reasons, all
1185 * pattern conversions are done in rte_flow.
1187 if (reg == REG_C_0) {
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1192 MLX5_ASSERT(msk_c0);
1193 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1194 shl_c0 = rte_bsf32(msk_c0);
1196 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1200 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1202 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1203 /* The routine expects parameters in memory as big-endian ones. */
1204 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1205 MLX5_MODIFICATION_TYPE_SET, error);
1209 * Convert modify-header set IPv4 DSCP action to DV specification.
1211 * @param[in,out] resource
1212 * Pointer to the modify-header resource.
1214 * Pointer to action specification.
1216 * Pointer to the error structure.
1219 * 0 on success, a negative errno value otherwise and rte_errno is set.
1222 flow_dv_convert_action_modify_ipv4_dscp
1223 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1224 const struct rte_flow_action *action,
1225 struct rte_flow_error *error)
1227 const struct rte_flow_action_set_dscp *conf =
1228 (const struct rte_flow_action_set_dscp *)(action->conf);
1229 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1230 struct rte_flow_item_ipv4 ipv4;
1231 struct rte_flow_item_ipv4 ipv4_mask;
1233 memset(&ipv4, 0, sizeof(ipv4));
1234 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1235 ipv4.hdr.type_of_service = conf->dscp;
1236 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1238 item.mask = &ipv4_mask;
1239 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1240 MLX5_MODIFICATION_TYPE_SET, error);
1244 * Convert modify-header set IPv6 DSCP action to DV specification.
1246 * @param[in,out] resource
1247 * Pointer to the modify-header resource.
1249 * Pointer to action specification.
1251 * Pointer to the error structure.
1254 * 0 on success, a negative errno value otherwise and rte_errno is set.
1257 flow_dv_convert_action_modify_ipv6_dscp
1258 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1259 const struct rte_flow_action *action,
1260 struct rte_flow_error *error)
1262 const struct rte_flow_action_set_dscp *conf =
1263 (const struct rte_flow_action_set_dscp *)(action->conf);
1264 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1265 struct rte_flow_item_ipv6 ipv6;
1266 struct rte_flow_item_ipv6 ipv6_mask;
1268 memset(&ipv6, 0, sizeof(ipv6));
1269 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1271 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1272 * rdma-core only accept the DSCP bits byte aligned start from
1273 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1274 * bits in IPv6 case as rdma-core requires byte aligned value.
1276 ipv6.hdr.vtc_flow = conf->dscp;
1277 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1279 item.mask = &ipv6_mask;
1280 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1281 MLX5_MODIFICATION_TYPE_SET, error);
1285 * Validate MARK item.
1288 * Pointer to the rte_eth_dev structure.
1290 * Item specification.
1292 * Attributes of flow that includes this item.
1294 * Pointer to error structure.
1297 * 0 on success, a negative errno value otherwise and rte_errno is set.
1300 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1301 const struct rte_flow_item *item,
1302 const struct rte_flow_attr *attr __rte_unused,
1303 struct rte_flow_error *error)
1305 struct mlx5_priv *priv = dev->data->dev_private;
1306 struct mlx5_dev_config *config = &priv->config;
1307 const struct rte_flow_item_mark *spec = item->spec;
1308 const struct rte_flow_item_mark *mask = item->mask;
1309 const struct rte_flow_item_mark nic_mask = {
1310 .id = priv->sh->dv_mark_mask,
1314 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1315 return rte_flow_error_set(error, ENOTSUP,
1316 RTE_FLOW_ERROR_TYPE_ITEM, item,
1317 "extended metadata feature"
1319 if (!mlx5_flow_ext_mreg_supported(dev))
1320 return rte_flow_error_set(error, ENOTSUP,
1321 RTE_FLOW_ERROR_TYPE_ITEM, item,
1322 "extended metadata register"
1323 " isn't supported");
1325 return rte_flow_error_set(error, ENOTSUP,
1326 RTE_FLOW_ERROR_TYPE_ITEM, item,
1327 "extended metadata register"
1328 " isn't available");
1329 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1333 return rte_flow_error_set(error, EINVAL,
1334 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1336 "data cannot be empty");
1337 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1338 return rte_flow_error_set(error, EINVAL,
1339 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1341 "mark id exceeds the limit");
1344 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1345 (const uint8_t *)&nic_mask,
1346 sizeof(struct rte_flow_item_mark),
1354 * Validate META item.
1357 * Pointer to the rte_eth_dev structure.
1359 * Item specification.
1361 * Attributes of flow that includes this item.
1363 * Pointer to error structure.
1366 * 0 on success, a negative errno value otherwise and rte_errno is set.
1369 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1370 const struct rte_flow_item *item,
1371 const struct rte_flow_attr *attr,
1372 struct rte_flow_error *error)
1374 struct mlx5_priv *priv = dev->data->dev_private;
1375 struct mlx5_dev_config *config = &priv->config;
1376 const struct rte_flow_item_meta *spec = item->spec;
1377 const struct rte_flow_item_meta *mask = item->mask;
1378 struct rte_flow_item_meta nic_mask = {
1385 return rte_flow_error_set(error, EINVAL,
1386 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1388 "data cannot be empty");
1390 return rte_flow_error_set(error, EINVAL,
1391 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1392 "data cannot be zero");
1393 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1394 if (!mlx5_flow_ext_mreg_supported(dev))
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1397 "extended metadata register"
1398 " isn't supported");
1399 reg = flow_dv_get_metadata_reg(dev, attr, error);
1403 return rte_flow_error_set(error, ENOTSUP,
1404 RTE_FLOW_ERROR_TYPE_ITEM, item,
1408 nic_mask.data = priv->sh->dv_meta_mask;
1411 mask = &rte_flow_item_meta_mask;
1412 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1413 (const uint8_t *)&nic_mask,
1414 sizeof(struct rte_flow_item_meta),
1420 * Validate TAG item.
1423 * Pointer to the rte_eth_dev structure.
1425 * Item specification.
1427 * Attributes of flow that includes this item.
1429 * Pointer to error structure.
1432 * 0 on success, a negative errno value otherwise and rte_errno is set.
1435 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1436 const struct rte_flow_item *item,
1437 const struct rte_flow_attr *attr __rte_unused,
1438 struct rte_flow_error *error)
1440 const struct rte_flow_item_tag *spec = item->spec;
1441 const struct rte_flow_item_tag *mask = item->mask;
1442 const struct rte_flow_item_tag nic_mask = {
1443 .data = RTE_BE32(UINT32_MAX),
1448 if (!mlx5_flow_ext_mreg_supported(dev))
1449 return rte_flow_error_set(error, ENOTSUP,
1450 RTE_FLOW_ERROR_TYPE_ITEM, item,
1451 "extensive metadata register"
1452 " isn't supported");
1454 return rte_flow_error_set(error, EINVAL,
1455 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1457 "data cannot be empty");
1459 mask = &rte_flow_item_tag_mask;
1460 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1461 (const uint8_t *)&nic_mask,
1462 sizeof(struct rte_flow_item_tag),
1466 if (mask->index != 0xff)
1467 return rte_flow_error_set(error, EINVAL,
1468 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1469 "partial mask for tag index"
1470 " is not supported");
1471 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1474 MLX5_ASSERT(ret != REG_NONE);
1479 * Validate vport item.
1482 * Pointer to the rte_eth_dev structure.
1484 * Item specification.
1486 * Attributes of flow that includes this item.
1487 * @param[in] item_flags
1488 * Bit-fields that holds the items detected until now.
1490 * Pointer to error structure.
1493 * 0 on success, a negative errno value otherwise and rte_errno is set.
1496 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1497 const struct rte_flow_item *item,
1498 const struct rte_flow_attr *attr,
1499 uint64_t item_flags,
1500 struct rte_flow_error *error)
1502 const struct rte_flow_item_port_id *spec = item->spec;
1503 const struct rte_flow_item_port_id *mask = item->mask;
1504 const struct rte_flow_item_port_id switch_mask = {
1507 struct mlx5_priv *esw_priv;
1508 struct mlx5_priv *dev_priv;
1511 if (!attr->transfer)
1512 return rte_flow_error_set(error, EINVAL,
1513 RTE_FLOW_ERROR_TYPE_ITEM,
1515 "match on port id is valid only"
1516 " when transfer flag is enabled");
1517 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1518 return rte_flow_error_set(error, ENOTSUP,
1519 RTE_FLOW_ERROR_TYPE_ITEM, item,
1520 "multiple source ports are not"
1523 mask = &switch_mask;
1524 if (mask->id != 0xffffffff)
1525 return rte_flow_error_set(error, ENOTSUP,
1526 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1528 "no support for partial mask on"
1530 ret = mlx5_flow_item_acceptable
1531 (item, (const uint8_t *)mask,
1532 (const uint8_t *)&rte_flow_item_port_id_mask,
1533 sizeof(struct rte_flow_item_port_id),
1539 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1541 return rte_flow_error_set(error, rte_errno,
1542 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1543 "failed to obtain E-Switch info for"
1545 dev_priv = mlx5_dev_to_eswitch_info(dev);
1547 return rte_flow_error_set(error, rte_errno,
1548 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1550 "failed to obtain E-Switch info");
1551 if (esw_priv->domain_id != dev_priv->domain_id)
1552 return rte_flow_error_set(error, EINVAL,
1553 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1554 "cannot match on a port from a"
1555 " different E-Switch");
1560 * Validate GTP item.
1563 * Pointer to the rte_eth_dev structure.
1565 * Item specification.
1566 * @param[in] item_flags
1567 * Bit-fields that holds the items detected until now.
1569 * Pointer to error structure.
1572 * 0 on success, a negative errno value otherwise and rte_errno is set.
1575 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1576 const struct rte_flow_item *item,
1577 uint64_t item_flags,
1578 struct rte_flow_error *error)
1580 struct mlx5_priv *priv = dev->data->dev_private;
1581 const struct rte_flow_item_gtp *mask = item->mask;
1582 const struct rte_flow_item_gtp nic_mask = {
1584 .teid = RTE_BE32(0xffffffff),
1587 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1588 return rte_flow_error_set(error, ENOTSUP,
1589 RTE_FLOW_ERROR_TYPE_ITEM, item,
1590 "GTP support is not enabled");
1591 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1592 return rte_flow_error_set(error, ENOTSUP,
1593 RTE_FLOW_ERROR_TYPE_ITEM, item,
1594 "multiple tunnel layers not"
1596 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1597 return rte_flow_error_set(error, EINVAL,
1598 RTE_FLOW_ERROR_TYPE_ITEM, item,
1599 "no outer UDP layer found");
1601 mask = &rte_flow_item_gtp_mask;
1602 return mlx5_flow_item_acceptable
1603 (item, (const uint8_t *)mask,
1604 (const uint8_t *)&nic_mask,
1605 sizeof(struct rte_flow_item_gtp),
1610 * Validate the pop VLAN action.
1613 * Pointer to the rte_eth_dev structure.
1614 * @param[in] action_flags
1615 * Holds the actions detected until now.
1617 * Pointer to the pop vlan action.
1618 * @param[in] item_flags
1619 * The items found in this flow rule.
1621 * Pointer to flow attributes.
1623 * Pointer to error structure.
1626 * 0 on success, a negative errno value otherwise and rte_errno is set.
1629 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1630 uint64_t action_flags,
1631 const struct rte_flow_action *action,
1632 uint64_t item_flags,
1633 const struct rte_flow_attr *attr,
1634 struct rte_flow_error *error)
1636 struct mlx5_priv *priv = dev->data->dev_private;
1640 if (!priv->sh->pop_vlan_action)
1641 return rte_flow_error_set(error, ENOTSUP,
1642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1644 "pop vlan action is not supported");
1646 return rte_flow_error_set(error, ENOTSUP,
1647 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1649 "pop vlan action not supported for "
1651 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1652 return rte_flow_error_set(error, ENOTSUP,
1653 RTE_FLOW_ERROR_TYPE_ACTION, action,
1654 "no support for multiple VLAN "
1656 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1657 return rte_flow_error_set(error, ENOTSUP,
1658 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1660 "cannot pop vlan without a "
1661 "match on (outer) vlan in the flow");
1662 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1663 return rte_flow_error_set(error, EINVAL,
1664 RTE_FLOW_ERROR_TYPE_ACTION, action,
1665 "wrong action order, port_id should "
1666 "be after pop VLAN action");
1671 * Get VLAN default info from vlan match info.
1674 * the list of item specifications.
1676 * pointer VLAN info to fill to.
1679 * 0 on success, a negative errno value otherwise and rte_errno is set.
1682 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1683 struct rte_vlan_hdr *vlan)
1685 const struct rte_flow_item_vlan nic_mask = {
1686 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1687 MLX5DV_FLOW_VLAN_VID_MASK),
1688 .inner_type = RTE_BE16(0xffff),
1693 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1694 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1696 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1697 const struct rte_flow_item_vlan *vlan_m = items->mask;
1698 const struct rte_flow_item_vlan *vlan_v = items->spec;
1702 /* Only full match values are accepted */
1703 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1704 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1705 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1707 rte_be_to_cpu_16(vlan_v->tci &
1708 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1710 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1711 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1712 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1714 rte_be_to_cpu_16(vlan_v->tci &
1715 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1717 if (vlan_m->inner_type == nic_mask.inner_type)
1718 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1719 vlan_m->inner_type);
1724 * Validate the push VLAN action.
1726 * @param[in] action_flags
1727 * Holds the actions detected until now.
1728 * @param[in] item_flags
1729 * The items found in this flow rule.
1731 * Pointer to the action structure.
1733 * Pointer to flow attributes
1735 * Pointer to error structure.
1738 * 0 on success, a negative errno value otherwise and rte_errno is set.
1741 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1742 uint64_t item_flags __rte_unused,
1743 const struct rte_flow_action *action,
1744 const struct rte_flow_attr *attr,
1745 struct rte_flow_error *error)
1747 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1749 if (!attr->transfer && attr->ingress)
1750 return rte_flow_error_set(error, ENOTSUP,
1751 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1753 "push VLAN action not supported for "
1755 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1756 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1757 return rte_flow_error_set(error, EINVAL,
1758 RTE_FLOW_ERROR_TYPE_ACTION, action,
1759 "invalid vlan ethertype");
1760 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1761 return rte_flow_error_set(error, ENOTSUP,
1762 RTE_FLOW_ERROR_TYPE_ACTION, action,
1763 "no support for multiple VLAN "
1765 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1766 return rte_flow_error_set(error, EINVAL,
1767 RTE_FLOW_ERROR_TYPE_ACTION, action,
1768 "wrong action order, port_id should "
1769 "be after push VLAN");
1775 * Validate the set VLAN PCP.
1777 * @param[in] action_flags
1778 * Holds the actions detected until now.
1779 * @param[in] actions
1780 * Pointer to the list of actions remaining in the flow rule.
1782 * Pointer to error structure.
1785 * 0 on success, a negative errno value otherwise and rte_errno is set.
1788 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1789 const struct rte_flow_action actions[],
1790 struct rte_flow_error *error)
1792 const struct rte_flow_action *action = actions;
1793 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1795 if (conf->vlan_pcp > 7)
1796 return rte_flow_error_set(error, EINVAL,
1797 RTE_FLOW_ERROR_TYPE_ACTION, action,
1798 "VLAN PCP value is too big");
1799 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1800 return rte_flow_error_set(error, ENOTSUP,
1801 RTE_FLOW_ERROR_TYPE_ACTION, action,
1802 "set VLAN PCP action must follow "
1803 "the push VLAN action");
1804 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1805 return rte_flow_error_set(error, ENOTSUP,
1806 RTE_FLOW_ERROR_TYPE_ACTION, action,
1807 "Multiple VLAN PCP modification are "
1809 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1810 return rte_flow_error_set(error, EINVAL,
1811 RTE_FLOW_ERROR_TYPE_ACTION, action,
1812 "wrong action order, port_id should "
1813 "be after set VLAN PCP");
1818 * Validate the set VLAN VID.
1820 * @param[in] item_flags
1821 * Holds the items detected in this rule.
1822 * @param[in] action_flags
1823 * Holds the actions detected until now.
1824 * @param[in] actions
1825 * Pointer to the list of actions remaining in the flow rule.
1827 * Pointer to error structure.
1830 * 0 on success, a negative errno value otherwise and rte_errno is set.
1833 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1834 uint64_t action_flags,
1835 const struct rte_flow_action actions[],
1836 struct rte_flow_error *error)
1838 const struct rte_flow_action *action = actions;
1839 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1841 if (conf->vlan_vid > RTE_BE16(0xFFE))
1842 return rte_flow_error_set(error, EINVAL,
1843 RTE_FLOW_ERROR_TYPE_ACTION, action,
1844 "VLAN VID value is too big");
1845 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1846 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_ACTION, action,
1849 "set VLAN VID action must follow push"
1850 " VLAN action or match on VLAN item");
1851 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1852 return rte_flow_error_set(error, ENOTSUP,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "Multiple VLAN VID modifications are "
1856 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1857 return rte_flow_error_set(error, EINVAL,
1858 RTE_FLOW_ERROR_TYPE_ACTION, action,
1859 "wrong action order, port_id should "
1860 "be after set VLAN VID");
1865 * Validate the FLAG action.
1868 * Pointer to the rte_eth_dev structure.
1869 * @param[in] action_flags
1870 * Holds the actions detected until now.
1872 * Pointer to flow attributes
1874 * Pointer to error structure.
1877 * 0 on success, a negative errno value otherwise and rte_errno is set.
1880 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1881 uint64_t action_flags,
1882 const struct rte_flow_attr *attr,
1883 struct rte_flow_error *error)
1885 struct mlx5_priv *priv = dev->data->dev_private;
1886 struct mlx5_dev_config *config = &priv->config;
1889 /* Fall back if no extended metadata register support. */
1890 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1891 return mlx5_flow_validate_action_flag(action_flags, attr,
1893 /* Extensive metadata mode requires registers. */
1894 if (!mlx5_flow_ext_mreg_supported(dev))
1895 return rte_flow_error_set(error, ENOTSUP,
1896 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1897 "no metadata registers "
1898 "to support flag action");
1899 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1900 return rte_flow_error_set(error, ENOTSUP,
1901 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1902 "extended metadata register"
1903 " isn't available");
1904 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1907 MLX5_ASSERT(ret > 0);
1908 if (action_flags & MLX5_FLOW_ACTION_MARK)
1909 return rte_flow_error_set(error, EINVAL,
1910 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1911 "can't mark and flag in same flow");
1912 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1913 return rte_flow_error_set(error, EINVAL,
1914 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1916 " actions in same flow");
1921 * Validate MARK action.
1924 * Pointer to the rte_eth_dev structure.
1926 * Pointer to action.
1927 * @param[in] action_flags
1928 * Holds the actions detected until now.
1930 * Pointer to flow attributes
1932 * Pointer to error structure.
1935 * 0 on success, a negative errno value otherwise and rte_errno is set.
1938 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1939 const struct rte_flow_action *action,
1940 uint64_t action_flags,
1941 const struct rte_flow_attr *attr,
1942 struct rte_flow_error *error)
1944 struct mlx5_priv *priv = dev->data->dev_private;
1945 struct mlx5_dev_config *config = &priv->config;
1946 const struct rte_flow_action_mark *mark = action->conf;
1949 /* Fall back if no extended metadata register support. */
1950 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1951 return mlx5_flow_validate_action_mark(action, action_flags,
1953 /* Extensive metadata mode requires registers. */
1954 if (!mlx5_flow_ext_mreg_supported(dev))
1955 return rte_flow_error_set(error, ENOTSUP,
1956 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1957 "no metadata registers "
1958 "to support mark action");
1959 if (!priv->sh->dv_mark_mask)
1960 return rte_flow_error_set(error, ENOTSUP,
1961 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1962 "extended metadata register"
1963 " isn't available");
1964 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1967 MLX5_ASSERT(ret > 0);
1969 return rte_flow_error_set(error, EINVAL,
1970 RTE_FLOW_ERROR_TYPE_ACTION, action,
1971 "configuration cannot be null");
1972 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1973 return rte_flow_error_set(error, EINVAL,
1974 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1976 "mark id exceeds the limit");
1977 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1978 return rte_flow_error_set(error, EINVAL,
1979 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1980 "can't flag and mark in same flow");
1981 if (action_flags & MLX5_FLOW_ACTION_MARK)
1982 return rte_flow_error_set(error, EINVAL,
1983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1984 "can't have 2 mark actions in same"
1990 * Validate SET_META action.
1993 * Pointer to the rte_eth_dev structure.
1995 * Pointer to the action structure.
1996 * @param[in] action_flags
1997 * Holds the actions detected until now.
1999 * Pointer to flow attributes
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2008 const struct rte_flow_action *action,
2009 uint64_t action_flags __rte_unused,
2010 const struct rte_flow_attr *attr,
2011 struct rte_flow_error *error)
2013 const struct rte_flow_action_set_meta *conf;
2014 uint32_t nic_mask = UINT32_MAX;
2017 if (!mlx5_flow_ext_mreg_supported(dev))
2018 return rte_flow_error_set(error, ENOTSUP,
2019 RTE_FLOW_ERROR_TYPE_ACTION, action,
2020 "extended metadata register"
2021 " isn't supported");
2022 reg = flow_dv_get_metadata_reg(dev, attr, error);
2025 if (reg != REG_A && reg != REG_B) {
2026 struct mlx5_priv *priv = dev->data->dev_private;
2028 nic_mask = priv->sh->dv_meta_mask;
2030 if (!(action->conf))
2031 return rte_flow_error_set(error, EINVAL,
2032 RTE_FLOW_ERROR_TYPE_ACTION, action,
2033 "configuration cannot be null");
2034 conf = (const struct rte_flow_action_set_meta *)action->conf;
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, action,
2038 "zero mask doesn't have any effect");
2039 if (conf->mask & ~nic_mask)
2040 return rte_flow_error_set(error, EINVAL,
2041 RTE_FLOW_ERROR_TYPE_ACTION, action,
2042 "meta data must be within reg C0");
2043 if (!(conf->data & conf->mask))
2044 return rte_flow_error_set(error, EINVAL,
2045 RTE_FLOW_ERROR_TYPE_ACTION, action,
2046 "zero value has no effect");
2051 * Validate SET_TAG action.
2054 * Pointer to the rte_eth_dev structure.
2056 * Pointer to the action structure.
2057 * @param[in] action_flags
2058 * Holds the actions detected until now.
2060 * Pointer to flow attributes
2062 * Pointer to error structure.
2065 * 0 on success, a negative errno value otherwise and rte_errno is set.
2068 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2069 const struct rte_flow_action *action,
2070 uint64_t action_flags,
2071 const struct rte_flow_attr *attr,
2072 struct rte_flow_error *error)
2074 const struct rte_flow_action_set_tag *conf;
2075 const uint64_t terminal_action_flags =
2076 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2077 MLX5_FLOW_ACTION_RSS;
2080 if (!mlx5_flow_ext_mreg_supported(dev))
2081 return rte_flow_error_set(error, ENOTSUP,
2082 RTE_FLOW_ERROR_TYPE_ACTION, action,
2083 "extensive metadata register"
2084 " isn't supported");
2085 if (!(action->conf))
2086 return rte_flow_error_set(error, EINVAL,
2087 RTE_FLOW_ERROR_TYPE_ACTION, action,
2088 "configuration cannot be null");
2089 conf = (const struct rte_flow_action_set_tag *)action->conf;
2091 return rte_flow_error_set(error, EINVAL,
2092 RTE_FLOW_ERROR_TYPE_ACTION, action,
2093 "zero mask doesn't have any effect");
2094 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2097 if (!attr->transfer && attr->ingress &&
2098 (action_flags & terminal_action_flags))
2099 return rte_flow_error_set(error, EINVAL,
2100 RTE_FLOW_ERROR_TYPE_ACTION, action,
2101 "set_tag has no effect"
2102 " with terminal actions");
2107 * Validate count action.
2110 * Pointer to rte_eth_dev structure.
2112 * Pointer to error structure.
2115 * 0 on success, a negative errno value otherwise and rte_errno is set.
2118 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2119 struct rte_flow_error *error)
2121 struct mlx5_priv *priv = dev->data->dev_private;
2123 if (!priv->config.devx)
2125 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2129 return rte_flow_error_set
2131 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2133 "count action not supported");
2137 * Validate the L2 encap action.
2139 * @param[in] action_flags
2140 * Holds the actions detected until now.
2142 * Pointer to the action structure.
2144 * Pointer to error structure.
2147 * 0 on success, a negative errno value otherwise and rte_errno is set.
2150 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2151 const struct rte_flow_action *action,
2152 struct rte_flow_error *error)
2154 if (!(action->conf))
2155 return rte_flow_error_set(error, EINVAL,
2156 RTE_FLOW_ERROR_TYPE_ACTION, action,
2157 "configuration cannot be null");
2158 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2159 return rte_flow_error_set(error, EINVAL,
2160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2161 "can only have a single encap action "
2167 * Validate a decap action.
2169 * @param[in] action_flags
2170 * Holds the actions detected until now.
2172 * Pointer to flow attributes
2174 * Pointer to error structure.
2177 * 0 on success, a negative errno value otherwise and rte_errno is set.
2180 flow_dv_validate_action_decap(uint64_t action_flags,
2181 const struct rte_flow_attr *attr,
2182 struct rte_flow_error *error)
2184 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2185 return rte_flow_error_set(error, ENOTSUP,
2186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 MLX5_FLOW_ACTION_DECAP ? "can only "
2189 "have a single decap action" : "decap "
2190 "after encap is not supported");
2191 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2192 return rte_flow_error_set(error, EINVAL,
2193 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2194 "can't have decap action after"
2197 return rte_flow_error_set(error, ENOTSUP,
2198 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2200 "decap action not supported for "
2205 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2208 * Validate the raw encap and decap actions.
2211 * Pointer to the decap action.
2213 * Pointer to the encap action.
2215 * Pointer to flow attributes
2216 * @param[in/out] action_flags
2217 * Holds the actions detected until now.
2218 * @param[out] actions_n
2219 * pointer to the number of actions counter.
2221 * Pointer to error structure.
2224 * 0 on success, a negative errno value otherwise and rte_errno is set.
2227 flow_dv_validate_action_raw_encap_decap
2228 (const struct rte_flow_action_raw_decap *decap,
2229 const struct rte_flow_action_raw_encap *encap,
2230 const struct rte_flow_attr *attr, uint64_t *action_flags,
2231 int *actions_n, struct rte_flow_error *error)
2235 if (encap && (!encap->size || !encap->data))
2236 return rte_flow_error_set(error, EINVAL,
2237 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2238 "raw encap data cannot be empty");
2239 if (decap && encap) {
2240 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2241 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2244 else if (encap->size <=
2245 MLX5_ENCAPSULATION_DECISION_SIZE &&
2247 MLX5_ENCAPSULATION_DECISION_SIZE)
2250 else if (encap->size >
2251 MLX5_ENCAPSULATION_DECISION_SIZE &&
2253 MLX5_ENCAPSULATION_DECISION_SIZE)
2254 /* 2 L2 actions: encap and decap. */
2257 return rte_flow_error_set(error,
2259 RTE_FLOW_ERROR_TYPE_ACTION,
2260 NULL, "unsupported too small "
2261 "raw decap and too small raw "
2262 "encap combination");
2265 ret = flow_dv_validate_action_decap(*action_flags, attr, error);
2268 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2272 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2273 return rte_flow_error_set(error, ENOTSUP,
2274 RTE_FLOW_ERROR_TYPE_ACTION,
2276 "small raw encap size");
2277 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2278 return rte_flow_error_set(error, EINVAL,
2279 RTE_FLOW_ERROR_TYPE_ACTION,
2281 "more than one encap action");
2282 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2289 * Find existing encap/decap resource or create and register a new one.
2291 * @param[in, out] dev
2292 * Pointer to rte_eth_dev structure.
2293 * @param[in, out] resource
2294 * Pointer to encap/decap resource.
2295 * @parm[in, out] dev_flow
2296 * Pointer to the dev_flow.
2298 * pointer to error structure.
2301 * 0 on success otherwise -errno and errno is set.
2304 flow_dv_encap_decap_resource_register
2305 (struct rte_eth_dev *dev,
2306 struct mlx5_flow_dv_encap_decap_resource *resource,
2307 struct mlx5_flow *dev_flow,
2308 struct rte_flow_error *error)
2310 struct mlx5_priv *priv = dev->data->dev_private;
2311 struct mlx5_ibv_shared *sh = priv->sh;
2312 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2313 struct mlx5dv_dr_domain *domain;
2315 resource->flags = dev_flow->group ? 0 : 1;
2316 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2317 domain = sh->fdb_domain;
2318 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2319 domain = sh->rx_domain;
2321 domain = sh->tx_domain;
2322 /* Lookup a matching resource from cache. */
2323 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2324 if (resource->reformat_type == cache_resource->reformat_type &&
2325 resource->ft_type == cache_resource->ft_type &&
2326 resource->flags == cache_resource->flags &&
2327 resource->size == cache_resource->size &&
2328 !memcmp((const void *)resource->buf,
2329 (const void *)cache_resource->buf,
2331 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2332 (void *)cache_resource,
2333 rte_atomic32_read(&cache_resource->refcnt));
2334 rte_atomic32_inc(&cache_resource->refcnt);
2335 dev_flow->dv.encap_decap = cache_resource;
2339 /* Register new encap/decap resource. */
2340 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2341 if (!cache_resource)
2342 return rte_flow_error_set(error, ENOMEM,
2343 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2344 "cannot allocate resource memory");
2345 *cache_resource = *resource;
2346 cache_resource->verbs_action =
2347 mlx5_glue->dv_create_flow_action_packet_reformat
2348 (sh->ctx, cache_resource->reformat_type,
2349 cache_resource->ft_type, domain, cache_resource->flags,
2350 cache_resource->size,
2351 (cache_resource->size ? cache_resource->buf : NULL));
2352 if (!cache_resource->verbs_action) {
2353 rte_free(cache_resource);
2354 return rte_flow_error_set(error, ENOMEM,
2355 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2356 NULL, "cannot create action");
2358 rte_atomic32_init(&cache_resource->refcnt);
2359 rte_atomic32_inc(&cache_resource->refcnt);
2360 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2361 dev_flow->dv.encap_decap = cache_resource;
2362 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2363 (void *)cache_resource,
2364 rte_atomic32_read(&cache_resource->refcnt));
2369 * Find existing table jump resource or create and register a new one.
2371 * @param[in, out] dev
2372 * Pointer to rte_eth_dev structure.
2373 * @param[in, out] tbl
2374 * Pointer to flow table resource.
2375 * @parm[in, out] dev_flow
2376 * Pointer to the dev_flow.
2378 * pointer to error structure.
2381 * 0 on success otherwise -errno and errno is set.
2384 flow_dv_jump_tbl_resource_register
2385 (struct rte_eth_dev *dev __rte_unused,
2386 struct mlx5_flow_tbl_resource *tbl,
2387 struct mlx5_flow *dev_flow,
2388 struct rte_flow_error *error)
2390 struct mlx5_flow_tbl_data_entry *tbl_data =
2391 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2395 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2397 tbl_data->jump.action =
2398 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2400 if (!tbl_data->jump.action)
2401 return rte_flow_error_set(error, ENOMEM,
2402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2403 NULL, "cannot create jump action");
2404 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2405 (void *)&tbl_data->jump, cnt);
2407 MLX5_ASSERT(tbl_data->jump.action);
2408 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2409 (void *)&tbl_data->jump, cnt);
2411 rte_atomic32_inc(&tbl_data->jump.refcnt);
2412 dev_flow->dv.jump = &tbl_data->jump;
2417 * Find existing table port ID resource or create and register a new one.
2419 * @param[in, out] dev
2420 * Pointer to rte_eth_dev structure.
2421 * @param[in, out] resource
2422 * Pointer to port ID action resource.
2423 * @parm[in, out] dev_flow
2424 * Pointer to the dev_flow.
2426 * pointer to error structure.
2429 * 0 on success otherwise -errno and errno is set.
2432 flow_dv_port_id_action_resource_register
2433 (struct rte_eth_dev *dev,
2434 struct mlx5_flow_dv_port_id_action_resource *resource,
2435 struct mlx5_flow *dev_flow,
2436 struct rte_flow_error *error)
2438 struct mlx5_priv *priv = dev->data->dev_private;
2439 struct mlx5_ibv_shared *sh = priv->sh;
2440 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2442 /* Lookup a matching resource from cache. */
2443 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2444 if (resource->port_id == cache_resource->port_id) {
2445 DRV_LOG(DEBUG, "port id action resource resource %p: "
2447 (void *)cache_resource,
2448 rte_atomic32_read(&cache_resource->refcnt));
2449 rte_atomic32_inc(&cache_resource->refcnt);
2450 dev_flow->dv.port_id_action = cache_resource;
2454 /* Register new port id action resource. */
2455 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2456 if (!cache_resource)
2457 return rte_flow_error_set(error, ENOMEM,
2458 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2459 "cannot allocate resource memory");
2460 *cache_resource = *resource;
2462 * Depending on rdma_core version the glue routine calls
2463 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2464 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2466 cache_resource->action =
2467 mlx5_glue->dr_create_flow_action_dest_port
2468 (priv->sh->fdb_domain, resource->port_id);
2469 if (!cache_resource->action) {
2470 rte_free(cache_resource);
2471 return rte_flow_error_set(error, ENOMEM,
2472 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2473 NULL, "cannot create action");
2475 rte_atomic32_init(&cache_resource->refcnt);
2476 rte_atomic32_inc(&cache_resource->refcnt);
2477 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2478 dev_flow->dv.port_id_action = cache_resource;
2479 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2480 (void *)cache_resource,
2481 rte_atomic32_read(&cache_resource->refcnt));
2486 * Find existing push vlan resource or create and register a new one.
2488 * @param [in, out] dev
2489 * Pointer to rte_eth_dev structure.
2490 * @param[in, out] resource
2491 * Pointer to port ID action resource.
2492 * @parm[in, out] dev_flow
2493 * Pointer to the dev_flow.
2495 * pointer to error structure.
2498 * 0 on success otherwise -errno and errno is set.
2501 flow_dv_push_vlan_action_resource_register
2502 (struct rte_eth_dev *dev,
2503 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2504 struct mlx5_flow *dev_flow,
2505 struct rte_flow_error *error)
2507 struct mlx5_priv *priv = dev->data->dev_private;
2508 struct mlx5_ibv_shared *sh = priv->sh;
2509 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2510 struct mlx5dv_dr_domain *domain;
2512 /* Lookup a matching resource from cache. */
2513 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2514 if (resource->vlan_tag == cache_resource->vlan_tag &&
2515 resource->ft_type == cache_resource->ft_type) {
2516 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2518 (void *)cache_resource,
2519 rte_atomic32_read(&cache_resource->refcnt));
2520 rte_atomic32_inc(&cache_resource->refcnt);
2521 dev_flow->dv.push_vlan_res = cache_resource;
2525 /* Register new push_vlan action resource. */
2526 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2527 if (!cache_resource)
2528 return rte_flow_error_set(error, ENOMEM,
2529 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2530 "cannot allocate resource memory");
2531 *cache_resource = *resource;
2532 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2533 domain = sh->fdb_domain;
2534 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2535 domain = sh->rx_domain;
2537 domain = sh->tx_domain;
2538 cache_resource->action =
2539 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2540 resource->vlan_tag);
2541 if (!cache_resource->action) {
2542 rte_free(cache_resource);
2543 return rte_flow_error_set(error, ENOMEM,
2544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2545 NULL, "cannot create action");
2547 rte_atomic32_init(&cache_resource->refcnt);
2548 rte_atomic32_inc(&cache_resource->refcnt);
2549 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2550 dev_flow->dv.push_vlan_res = cache_resource;
2551 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2552 (void *)cache_resource,
2553 rte_atomic32_read(&cache_resource->refcnt));
2557 * Get the size of specific rte_flow_item_type
2559 * @param[in] item_type
2560 * Tested rte_flow_item_type.
2563 * sizeof struct item_type, 0 if void or irrelevant.
2566 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2570 switch (item_type) {
2571 case RTE_FLOW_ITEM_TYPE_ETH:
2572 retval = sizeof(struct rte_flow_item_eth);
2574 case RTE_FLOW_ITEM_TYPE_VLAN:
2575 retval = sizeof(struct rte_flow_item_vlan);
2577 case RTE_FLOW_ITEM_TYPE_IPV4:
2578 retval = sizeof(struct rte_flow_item_ipv4);
2580 case RTE_FLOW_ITEM_TYPE_IPV6:
2581 retval = sizeof(struct rte_flow_item_ipv6);
2583 case RTE_FLOW_ITEM_TYPE_UDP:
2584 retval = sizeof(struct rte_flow_item_udp);
2586 case RTE_FLOW_ITEM_TYPE_TCP:
2587 retval = sizeof(struct rte_flow_item_tcp);
2589 case RTE_FLOW_ITEM_TYPE_VXLAN:
2590 retval = sizeof(struct rte_flow_item_vxlan);
2592 case RTE_FLOW_ITEM_TYPE_GRE:
2593 retval = sizeof(struct rte_flow_item_gre);
2595 case RTE_FLOW_ITEM_TYPE_NVGRE:
2596 retval = sizeof(struct rte_flow_item_nvgre);
2598 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2599 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2601 case RTE_FLOW_ITEM_TYPE_MPLS:
2602 retval = sizeof(struct rte_flow_item_mpls);
2604 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2612 #define MLX5_ENCAP_IPV4_VERSION 0x40
2613 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2614 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2615 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2616 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2617 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2618 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2621 * Convert the encap action data from list of rte_flow_item to raw buffer
2624 * Pointer to rte_flow_item objects list.
2626 * Pointer to the output buffer.
2628 * Pointer to the output buffer size.
2630 * Pointer to the error structure.
2633 * 0 on success, a negative errno value otherwise and rte_errno is set.
2636 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2637 size_t *size, struct rte_flow_error *error)
2639 struct rte_ether_hdr *eth = NULL;
2640 struct rte_vlan_hdr *vlan = NULL;
2641 struct rte_ipv4_hdr *ipv4 = NULL;
2642 struct rte_ipv6_hdr *ipv6 = NULL;
2643 struct rte_udp_hdr *udp = NULL;
2644 struct rte_vxlan_hdr *vxlan = NULL;
2645 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2646 struct rte_gre_hdr *gre = NULL;
2648 size_t temp_size = 0;
2651 return rte_flow_error_set(error, EINVAL,
2652 RTE_FLOW_ERROR_TYPE_ACTION,
2653 NULL, "invalid empty data");
2654 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2655 len = flow_dv_get_item_len(items->type);
2656 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2657 return rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ACTION,
2659 (void *)items->type,
2660 "items total size is too big"
2661 " for encap action");
2662 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2663 switch (items->type) {
2664 case RTE_FLOW_ITEM_TYPE_ETH:
2665 eth = (struct rte_ether_hdr *)&buf[temp_size];
2667 case RTE_FLOW_ITEM_TYPE_VLAN:
2668 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2670 return rte_flow_error_set(error, EINVAL,
2671 RTE_FLOW_ERROR_TYPE_ACTION,
2672 (void *)items->type,
2673 "eth header not found");
2674 if (!eth->ether_type)
2675 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2677 case RTE_FLOW_ITEM_TYPE_IPV4:
2678 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2680 return rte_flow_error_set(error, EINVAL,
2681 RTE_FLOW_ERROR_TYPE_ACTION,
2682 (void *)items->type,
2683 "neither eth nor vlan"
2685 if (vlan && !vlan->eth_proto)
2686 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2687 else if (eth && !eth->ether_type)
2688 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2689 if (!ipv4->version_ihl)
2690 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2691 MLX5_ENCAP_IPV4_IHL_MIN;
2692 if (!ipv4->time_to_live)
2693 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2695 case RTE_FLOW_ITEM_TYPE_IPV6:
2696 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2698 return rte_flow_error_set(error, EINVAL,
2699 RTE_FLOW_ERROR_TYPE_ACTION,
2700 (void *)items->type,
2701 "neither eth nor vlan"
2703 if (vlan && !vlan->eth_proto)
2704 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2705 else if (eth && !eth->ether_type)
2706 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2707 if (!ipv6->vtc_flow)
2709 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2710 if (!ipv6->hop_limits)
2711 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2713 case RTE_FLOW_ITEM_TYPE_UDP:
2714 udp = (struct rte_udp_hdr *)&buf[temp_size];
2716 return rte_flow_error_set(error, EINVAL,
2717 RTE_FLOW_ERROR_TYPE_ACTION,
2718 (void *)items->type,
2719 "ip header not found");
2720 if (ipv4 && !ipv4->next_proto_id)
2721 ipv4->next_proto_id = IPPROTO_UDP;
2722 else if (ipv6 && !ipv6->proto)
2723 ipv6->proto = IPPROTO_UDP;
2725 case RTE_FLOW_ITEM_TYPE_VXLAN:
2726 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2728 return rte_flow_error_set(error, EINVAL,
2729 RTE_FLOW_ERROR_TYPE_ACTION,
2730 (void *)items->type,
2731 "udp header not found");
2733 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2734 if (!vxlan->vx_flags)
2736 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2738 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2739 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2741 return rte_flow_error_set(error, EINVAL,
2742 RTE_FLOW_ERROR_TYPE_ACTION,
2743 (void *)items->type,
2744 "udp header not found");
2745 if (!vxlan_gpe->proto)
2746 return rte_flow_error_set(error, EINVAL,
2747 RTE_FLOW_ERROR_TYPE_ACTION,
2748 (void *)items->type,
2749 "next protocol not found");
2752 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2753 if (!vxlan_gpe->vx_flags)
2754 vxlan_gpe->vx_flags =
2755 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2757 case RTE_FLOW_ITEM_TYPE_GRE:
2758 case RTE_FLOW_ITEM_TYPE_NVGRE:
2759 gre = (struct rte_gre_hdr *)&buf[temp_size];
2761 return rte_flow_error_set(error, EINVAL,
2762 RTE_FLOW_ERROR_TYPE_ACTION,
2763 (void *)items->type,
2764 "next protocol not found");
2766 return rte_flow_error_set(error, EINVAL,
2767 RTE_FLOW_ERROR_TYPE_ACTION,
2768 (void *)items->type,
2769 "ip header not found");
2770 if (ipv4 && !ipv4->next_proto_id)
2771 ipv4->next_proto_id = IPPROTO_GRE;
2772 else if (ipv6 && !ipv6->proto)
2773 ipv6->proto = IPPROTO_GRE;
2775 case RTE_FLOW_ITEM_TYPE_VOID:
2778 return rte_flow_error_set(error, EINVAL,
2779 RTE_FLOW_ERROR_TYPE_ACTION,
2780 (void *)items->type,
2781 "unsupported item type");
2791 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2793 struct rte_ether_hdr *eth = NULL;
2794 struct rte_vlan_hdr *vlan = NULL;
2795 struct rte_ipv6_hdr *ipv6 = NULL;
2796 struct rte_udp_hdr *udp = NULL;
2800 eth = (struct rte_ether_hdr *)data;
2801 next_hdr = (char *)(eth + 1);
2802 proto = RTE_BE16(eth->ether_type);
2805 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2806 vlan = (struct rte_vlan_hdr *)next_hdr;
2807 proto = RTE_BE16(vlan->eth_proto);
2808 next_hdr += sizeof(struct rte_vlan_hdr);
2811 /* HW calculates IPv4 csum. no need to proceed */
2812 if (proto == RTE_ETHER_TYPE_IPV4)
2815 /* non IPv4/IPv6 header. not supported */
2816 if (proto != RTE_ETHER_TYPE_IPV6) {
2817 return rte_flow_error_set(error, ENOTSUP,
2818 RTE_FLOW_ERROR_TYPE_ACTION,
2819 NULL, "Cannot offload non IPv4/IPv6");
2822 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2824 /* ignore non UDP */
2825 if (ipv6->proto != IPPROTO_UDP)
2828 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2829 udp->dgram_cksum = 0;
2835 * Convert L2 encap action to DV specification.
2838 * Pointer to rte_eth_dev structure.
2840 * Pointer to action structure.
2841 * @param[in, out] dev_flow
2842 * Pointer to the mlx5_flow.
2843 * @param[in] transfer
2844 * Mark if the flow is E-Switch flow.
2846 * Pointer to the error structure.
2849 * 0 on success, a negative errno value otherwise and rte_errno is set.
2852 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2853 const struct rte_flow_action *action,
2854 struct mlx5_flow *dev_flow,
2856 struct rte_flow_error *error)
2858 const struct rte_flow_item *encap_data;
2859 const struct rte_flow_action_raw_encap *raw_encap_data;
2860 struct mlx5_flow_dv_encap_decap_resource res = {
2862 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2863 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2864 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2867 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2869 (const struct rte_flow_action_raw_encap *)action->conf;
2870 res.size = raw_encap_data->size;
2871 memcpy(res.buf, raw_encap_data->data, res.size);
2873 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2875 ((const struct rte_flow_action_vxlan_encap *)
2876 action->conf)->definition;
2879 ((const struct rte_flow_action_nvgre_encap *)
2880 action->conf)->definition;
2881 if (flow_dv_convert_encap_data(encap_data, res.buf,
2885 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2887 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2888 return rte_flow_error_set(error, EINVAL,
2889 RTE_FLOW_ERROR_TYPE_ACTION,
2890 NULL, "can't create L2 encap action");
2895 * Convert L2 decap action to DV specification.
2898 * Pointer to rte_eth_dev structure.
2899 * @param[in, out] dev_flow
2900 * Pointer to the mlx5_flow.
2901 * @param[in] transfer
2902 * Mark if the flow is E-Switch flow.
2904 * Pointer to the error structure.
2907 * 0 on success, a negative errno value otherwise and rte_errno is set.
2910 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2911 struct mlx5_flow *dev_flow,
2913 struct rte_flow_error *error)
2915 struct mlx5_flow_dv_encap_decap_resource res = {
2918 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2919 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2920 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2923 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2924 return rte_flow_error_set(error, EINVAL,
2925 RTE_FLOW_ERROR_TYPE_ACTION,
2926 NULL, "can't create L2 decap action");
2931 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2934 * Pointer to rte_eth_dev structure.
2936 * Pointer to action structure.
2937 * @param[in, out] dev_flow
2938 * Pointer to the mlx5_flow.
2940 * Pointer to the flow attributes.
2942 * Pointer to the error structure.
2945 * 0 on success, a negative errno value otherwise and rte_errno is set.
2948 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2949 const struct rte_flow_action *action,
2950 struct mlx5_flow *dev_flow,
2951 const struct rte_flow_attr *attr,
2952 struct rte_flow_error *error)
2954 const struct rte_flow_action_raw_encap *encap_data;
2955 struct mlx5_flow_dv_encap_decap_resource res;
2957 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2958 res.size = encap_data->size;
2959 memcpy(res.buf, encap_data->data, res.size);
2960 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
2961 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
2962 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
2964 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2966 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2967 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2968 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2969 return rte_flow_error_set(error, EINVAL,
2970 RTE_FLOW_ERROR_TYPE_ACTION,
2971 NULL, "can't create encap action");
2976 * Create action push VLAN.
2979 * Pointer to rte_eth_dev structure.
2981 * Pointer to the flow attributes.
2983 * Pointer to the vlan to push to the Ethernet header.
2984 * @param[in, out] dev_flow
2985 * Pointer to the mlx5_flow.
2987 * Pointer to the error structure.
2990 * 0 on success, a negative errno value otherwise and rte_errno is set.
2993 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2994 const struct rte_flow_attr *attr,
2995 const struct rte_vlan_hdr *vlan,
2996 struct mlx5_flow *dev_flow,
2997 struct rte_flow_error *error)
2999 struct mlx5_flow_dv_push_vlan_action_resource res;
3002 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3005 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3007 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3008 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3009 return flow_dv_push_vlan_action_resource_register
3010 (dev, &res, dev_flow, error);
3014 * Validate the modify-header actions.
3016 * @param[in] action_flags
3017 * Holds the actions detected until now.
3019 * Pointer to the modify action.
3021 * Pointer to error structure.
3024 * 0 on success, a negative errno value otherwise and rte_errno is set.
3027 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3028 const struct rte_flow_action *action,
3029 struct rte_flow_error *error)
3031 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3032 return rte_flow_error_set(error, EINVAL,
3033 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3034 NULL, "action configuration not set");
3035 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3036 return rte_flow_error_set(error, EINVAL,
3037 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3038 "can't have encap action before"
3044 * Validate the modify-header MAC address actions.
3046 * @param[in] action_flags
3047 * Holds the actions detected until now.
3049 * Pointer to the modify action.
3050 * @param[in] item_flags
3051 * Holds the items detected.
3053 * Pointer to error structure.
3056 * 0 on success, a negative errno value otherwise and rte_errno is set.
3059 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3060 const struct rte_flow_action *action,
3061 const uint64_t item_flags,
3062 struct rte_flow_error *error)
3066 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3068 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3069 return rte_flow_error_set(error, EINVAL,
3070 RTE_FLOW_ERROR_TYPE_ACTION,
3072 "no L2 item in pattern");
3078 * Validate the modify-header IPv4 address actions.
3080 * @param[in] action_flags
3081 * Holds the actions detected until now.
3083 * Pointer to the modify action.
3084 * @param[in] item_flags
3085 * Holds the items detected.
3087 * Pointer to error structure.
3090 * 0 on success, a negative errno value otherwise and rte_errno is set.
3093 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3094 const struct rte_flow_action *action,
3095 const uint64_t item_flags,
3096 struct rte_flow_error *error)
3100 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3102 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3103 return rte_flow_error_set(error, EINVAL,
3104 RTE_FLOW_ERROR_TYPE_ACTION,
3106 "no ipv4 item in pattern");
3112 * Validate the modify-header IPv6 address actions.
3114 * @param[in] action_flags
3115 * Holds the actions detected until now.
3117 * Pointer to the modify action.
3118 * @param[in] item_flags
3119 * Holds the items detected.
3121 * Pointer to error structure.
3124 * 0 on success, a negative errno value otherwise and rte_errno is set.
3127 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3128 const struct rte_flow_action *action,
3129 const uint64_t item_flags,
3130 struct rte_flow_error *error)
3134 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3136 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3137 return rte_flow_error_set(error, EINVAL,
3138 RTE_FLOW_ERROR_TYPE_ACTION,
3140 "no ipv6 item in pattern");
3146 * Validate the modify-header TP actions.
3148 * @param[in] action_flags
3149 * Holds the actions detected until now.
3151 * Pointer to the modify action.
3152 * @param[in] item_flags
3153 * Holds the items detected.
3155 * Pointer to error structure.
3158 * 0 on success, a negative errno value otherwise and rte_errno is set.
3161 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3162 const struct rte_flow_action *action,
3163 const uint64_t item_flags,
3164 struct rte_flow_error *error)
3168 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3170 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3171 return rte_flow_error_set(error, EINVAL,
3172 RTE_FLOW_ERROR_TYPE_ACTION,
3173 NULL, "no transport layer "
3180 * Validate the modify-header actions of increment/decrement
3181 * TCP Sequence-number.
3183 * @param[in] action_flags
3184 * Holds the actions detected until now.
3186 * Pointer to the modify action.
3187 * @param[in] item_flags
3188 * Holds the items detected.
3190 * Pointer to error structure.
3193 * 0 on success, a negative errno value otherwise and rte_errno is set.
3196 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3197 const struct rte_flow_action *action,
3198 const uint64_t item_flags,
3199 struct rte_flow_error *error)
3203 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3205 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3206 return rte_flow_error_set(error, EINVAL,
3207 RTE_FLOW_ERROR_TYPE_ACTION,
3208 NULL, "no TCP item in"
3210 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3211 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3212 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3213 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3214 return rte_flow_error_set(error, EINVAL,
3215 RTE_FLOW_ERROR_TYPE_ACTION,
3217 "cannot decrease and increase"
3218 " TCP sequence number"
3219 " at the same time");
3225 * Validate the modify-header actions of increment/decrement
3226 * TCP Acknowledgment number.
3228 * @param[in] action_flags
3229 * Holds the actions detected until now.
3231 * Pointer to the modify action.
3232 * @param[in] item_flags
3233 * Holds the items detected.
3235 * Pointer to error structure.
3238 * 0 on success, a negative errno value otherwise and rte_errno is set.
3241 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3242 const struct rte_flow_action *action,
3243 const uint64_t item_flags,
3244 struct rte_flow_error *error)
3248 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3250 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3251 return rte_flow_error_set(error, EINVAL,
3252 RTE_FLOW_ERROR_TYPE_ACTION,
3253 NULL, "no TCP item in"
3255 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3256 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3257 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3258 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3259 return rte_flow_error_set(error, EINVAL,
3260 RTE_FLOW_ERROR_TYPE_ACTION,
3262 "cannot decrease and increase"
3263 " TCP acknowledgment number"
3264 " at the same time");
3270 * Validate the modify-header TTL actions.
3272 * @param[in] action_flags
3273 * Holds the actions detected until now.
3275 * Pointer to the modify action.
3276 * @param[in] item_flags
3277 * Holds the items detected.
3279 * Pointer to error structure.
3282 * 0 on success, a negative errno value otherwise and rte_errno is set.
3285 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3286 const struct rte_flow_action *action,
3287 const uint64_t item_flags,
3288 struct rte_flow_error *error)
3292 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3294 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3295 return rte_flow_error_set(error, EINVAL,
3296 RTE_FLOW_ERROR_TYPE_ACTION,
3298 "no IP protocol in pattern");
3304 * Validate jump action.
3307 * Pointer to the jump action.
3308 * @param[in] action_flags
3309 * Holds the actions detected until now.
3310 * @param[in] attributes
3311 * Pointer to flow attributes
3312 * @param[in] external
3313 * Action belongs to flow rule created by request external to PMD.
3315 * Pointer to error structure.
3318 * 0 on success, a negative errno value otherwise and rte_errno is set.
3321 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3322 uint64_t action_flags,
3323 const struct rte_flow_attr *attributes,
3324 bool external, struct rte_flow_error *error)
3326 uint32_t target_group, table;
3329 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3330 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3331 return rte_flow_error_set(error, EINVAL,
3332 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3333 "can't have 2 fate actions in"
3335 if (action_flags & MLX5_FLOW_ACTION_METER)
3336 return rte_flow_error_set(error, ENOTSUP,
3337 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3338 "jump with meter not support");
3340 return rte_flow_error_set(error, EINVAL,
3341 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3342 NULL, "action configuration not set");
3344 ((const struct rte_flow_action_jump *)action->conf)->group;
3345 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3346 true, &table, error);
3349 if (attributes->group == target_group)
3350 return rte_flow_error_set(error, EINVAL,
3351 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3352 "target group must be other than"
3353 " the current flow group");
3358 * Validate the port_id action.
3361 * Pointer to rte_eth_dev structure.
3362 * @param[in] action_flags
3363 * Bit-fields that holds the actions detected until now.
3365 * Port_id RTE action structure.
3367 * Attributes of flow that includes this action.
3369 * Pointer to error structure.
3372 * 0 on success, a negative errno value otherwise and rte_errno is set.
3375 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3376 uint64_t action_flags,
3377 const struct rte_flow_action *action,
3378 const struct rte_flow_attr *attr,
3379 struct rte_flow_error *error)
3381 const struct rte_flow_action_port_id *port_id;
3382 struct mlx5_priv *act_priv;
3383 struct mlx5_priv *dev_priv;
3386 if (!attr->transfer)
3387 return rte_flow_error_set(error, ENOTSUP,
3388 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3390 "port id action is valid in transfer"
3392 if (!action || !action->conf)
3393 return rte_flow_error_set(error, ENOTSUP,
3394 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3396 "port id action parameters must be"
3398 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3399 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3400 return rte_flow_error_set(error, EINVAL,
3401 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3402 "can have only one fate actions in"
3404 dev_priv = mlx5_dev_to_eswitch_info(dev);
3406 return rte_flow_error_set(error, rte_errno,
3407 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3409 "failed to obtain E-Switch info");
3410 port_id = action->conf;
3411 port = port_id->original ? dev->data->port_id : port_id->id;
3412 act_priv = mlx5_port_to_eswitch_info(port, false);
3414 return rte_flow_error_set
3416 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3417 "failed to obtain E-Switch port id for port");
3418 if (act_priv->domain_id != dev_priv->domain_id)
3419 return rte_flow_error_set
3421 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3422 "port does not belong to"
3423 " E-Switch being configured");
3428 * Get the maximum number of modify header actions.
3431 * Pointer to rte_eth_dev structure.
3433 * Flags bits to check if root level.
3436 * Max number of modify header actions device can support.
3439 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3442 * There's no way to directly query the max cap. Although it has to be
3443 * acquried by iterative trial, it is a safe assumption that more
3444 * actions are supported by FW if extensive metadata register is
3445 * supported. (Only in the root table)
3447 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3448 return MLX5_MAX_MODIFY_NUM;
3450 return mlx5_flow_ext_mreg_supported(dev) ?
3451 MLX5_ROOT_TBL_MODIFY_NUM :
3452 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3456 * Validate the meter action.
3459 * Pointer to rte_eth_dev structure.
3460 * @param[in] action_flags
3461 * Bit-fields that holds the actions detected until now.
3463 * Pointer to the meter action.
3465 * Attributes of flow that includes this action.
3467 * Pointer to error structure.
3470 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3473 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3474 uint64_t action_flags,
3475 const struct rte_flow_action *action,
3476 const struct rte_flow_attr *attr,
3477 struct rte_flow_error *error)
3479 struct mlx5_priv *priv = dev->data->dev_private;
3480 const struct rte_flow_action_meter *am = action->conf;
3481 struct mlx5_flow_meter *fm;
3484 return rte_flow_error_set(error, EINVAL,
3485 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3486 "meter action conf is NULL");
3488 if (action_flags & MLX5_FLOW_ACTION_METER)
3489 return rte_flow_error_set(error, ENOTSUP,
3490 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3491 "meter chaining not support");
3492 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3493 return rte_flow_error_set(error, ENOTSUP,
3494 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3495 "meter with jump not support");
3497 return rte_flow_error_set(error, ENOTSUP,
3498 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3500 "meter action not supported");
3501 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3503 return rte_flow_error_set(error, EINVAL,
3504 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3506 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3507 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3508 (!fm->attr.egress && !attr->egress && attr->ingress))))
3509 return rte_flow_error_set(error, EINVAL,
3510 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3511 "Flow attributes are either invalid "
3512 "or have a conflict with current "
3513 "meter attributes");
3518 * Validate the modify-header IPv4 DSCP actions.
3520 * @param[in] action_flags
3521 * Holds the actions detected until now.
3523 * Pointer to the modify action.
3524 * @param[in] item_flags
3525 * Holds the items detected.
3527 * Pointer to error structure.
3530 * 0 on success, a negative errno value otherwise and rte_errno is set.
3533 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3534 const struct rte_flow_action *action,
3535 const uint64_t item_flags,
3536 struct rte_flow_error *error)
3540 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3542 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3543 return rte_flow_error_set(error, EINVAL,
3544 RTE_FLOW_ERROR_TYPE_ACTION,
3546 "no ipv4 item in pattern");
3552 * Validate the modify-header IPv6 DSCP actions.
3554 * @param[in] action_flags
3555 * Holds the actions detected until now.
3557 * Pointer to the modify action.
3558 * @param[in] item_flags
3559 * Holds the items detected.
3561 * Pointer to error structure.
3564 * 0 on success, a negative errno value otherwise and rte_errno is set.
3567 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3568 const struct rte_flow_action *action,
3569 const uint64_t item_flags,
3570 struct rte_flow_error *error)
3574 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3576 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3577 return rte_flow_error_set(error, EINVAL,
3578 RTE_FLOW_ERROR_TYPE_ACTION,
3580 "no ipv6 item in pattern");
3586 * Find existing modify-header resource or create and register a new one.
3588 * @param dev[in, out]
3589 * Pointer to rte_eth_dev structure.
3590 * @param[in, out] resource
3591 * Pointer to modify-header resource.
3592 * @parm[in, out] dev_flow
3593 * Pointer to the dev_flow.
3595 * pointer to error structure.
3598 * 0 on success otherwise -errno and errno is set.
3601 flow_dv_modify_hdr_resource_register
3602 (struct rte_eth_dev *dev,
3603 struct mlx5_flow_dv_modify_hdr_resource *resource,
3604 struct mlx5_flow *dev_flow,
3605 struct rte_flow_error *error)
3607 struct mlx5_priv *priv = dev->data->dev_private;
3608 struct mlx5_ibv_shared *sh = priv->sh;
3609 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3610 struct mlx5dv_dr_domain *ns;
3611 uint32_t actions_len;
3614 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3615 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3617 return rte_flow_error_set(error, EOVERFLOW,
3618 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3619 "too many modify header items");
3620 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3621 ns = sh->fdb_domain;
3622 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3626 /* Lookup a matching resource from cache. */
3627 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3628 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3629 if (resource->ft_type == cache_resource->ft_type &&
3630 resource->actions_num == cache_resource->actions_num &&
3631 resource->flags == cache_resource->flags &&
3632 !memcmp((const void *)resource->actions,
3633 (const void *)cache_resource->actions,
3635 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3636 (void *)cache_resource,
3637 rte_atomic32_read(&cache_resource->refcnt));
3638 rte_atomic32_inc(&cache_resource->refcnt);
3639 dev_flow->dv.modify_hdr = cache_resource;
3643 /* Register new modify-header resource. */
3644 cache_resource = rte_calloc(__func__, 1,
3645 sizeof(*cache_resource) + actions_len, 0);
3646 if (!cache_resource)
3647 return rte_flow_error_set(error, ENOMEM,
3648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3649 "cannot allocate resource memory");
3650 *cache_resource = *resource;
3651 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3652 cache_resource->verbs_action =
3653 mlx5_glue->dv_create_flow_action_modify_header
3654 (sh->ctx, cache_resource->ft_type, ns,
3655 cache_resource->flags, actions_len,
3656 (uint64_t *)cache_resource->actions);
3657 if (!cache_resource->verbs_action) {
3658 rte_free(cache_resource);
3659 return rte_flow_error_set(error, ENOMEM,
3660 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3661 NULL, "cannot create action");
3663 rte_atomic32_init(&cache_resource->refcnt);
3664 rte_atomic32_inc(&cache_resource->refcnt);
3665 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3666 dev_flow->dv.modify_hdr = cache_resource;
3667 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3668 (void *)cache_resource,
3669 rte_atomic32_read(&cache_resource->refcnt));
3673 #define MLX5_CNT_CONTAINER_RESIZE 64
3676 * Get or create a flow counter.
3679 * Pointer to the Ethernet device structure.
3681 * Indicate if this counter is shared with other flows.
3683 * Counter identifier.
3686 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3688 static struct mlx5_flow_counter *
3689 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3692 struct mlx5_priv *priv = dev->data->dev_private;
3693 struct mlx5_flow_counter *cnt = NULL;
3694 struct mlx5_devx_obj *dcs = NULL;
3696 if (!priv->config.devx) {
3697 rte_errno = ENOTSUP;
3701 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3702 if (cnt->shared && cnt->id == id) {
3708 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3711 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3713 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3717 struct mlx5_flow_counter tmpl = {
3723 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3725 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3731 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3736 * Release a flow counter.
3739 * Pointer to the Ethernet device structure.
3740 * @param[in] counter
3741 * Pointer to the counter handler.
3744 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3745 struct mlx5_flow_counter *counter)
3747 struct mlx5_priv *priv = dev->data->dev_private;
3751 if (--counter->ref_cnt == 0) {
3752 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3753 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3759 * Query a devx flow counter.
3762 * Pointer to the Ethernet device structure.
3764 * Pointer to the flow counter.
3766 * The statistics value of packets.
3768 * The statistics value of bytes.
3771 * 0 on success, otherwise a negative errno value and rte_errno is set.
3774 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3775 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3778 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3783 * Get a pool by a counter.
3786 * Pointer to the counter.
3791 static struct mlx5_flow_counter_pool *
3792 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3795 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3796 return (struct mlx5_flow_counter_pool *)cnt - 1;
3802 * Get a pool by devx counter ID.
3805 * Pointer to the counter container.
3807 * The counter devx ID.
3810 * The counter pool pointer if exists, NULL otherwise,
3812 static struct mlx5_flow_counter_pool *
3813 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3815 struct mlx5_flow_counter_pool *pool;
3817 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3818 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3819 MLX5_COUNTERS_PER_POOL;
3821 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3828 * Allocate a new memory for the counter values wrapped by all the needed
3832 * Pointer to the Ethernet device structure.
3834 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3837 * The new memory management pointer on success, otherwise NULL and rte_errno
3840 static struct mlx5_counter_stats_mem_mng *
3841 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3843 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3844 (dev->data->dev_private))->sh;
3845 struct mlx5_devx_mkey_attr mkey_attr;
3846 struct mlx5_counter_stats_mem_mng *mem_mng;
3847 volatile struct flow_counter_stats *raw_data;
3848 int size = (sizeof(struct flow_counter_stats) *
3849 MLX5_COUNTERS_PER_POOL +
3850 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3851 sizeof(struct mlx5_counter_stats_mem_mng);
3852 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3859 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3860 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3861 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3862 IBV_ACCESS_LOCAL_WRITE);
3863 if (!mem_mng->umem) {
3868 mkey_attr.addr = (uintptr_t)mem;
3869 mkey_attr.size = size;
3870 mkey_attr.umem_id = mem_mng->umem->umem_id;
3871 mkey_attr.pd = sh->pdn;
3872 mkey_attr.log_entity_size = 0;
3873 mkey_attr.pg_access = 0;
3874 mkey_attr.klm_array = NULL;
3875 mkey_attr.klm_num = 0;
3876 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3878 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3883 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3884 raw_data = (volatile struct flow_counter_stats *)mem;
3885 for (i = 0; i < raws_n; ++i) {
3886 mem_mng->raws[i].mem_mng = mem_mng;
3887 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3889 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3894 * Resize a counter container.
3897 * Pointer to the Ethernet device structure.
3899 * Whether the pool is for counter that was allocated by batch command.
3902 * The new container pointer on success, otherwise NULL and rte_errno is set.
3904 static struct mlx5_pools_container *
3905 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3907 struct mlx5_priv *priv = dev->data->dev_private;
3908 struct mlx5_pools_container *cont =
3909 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3910 struct mlx5_pools_container *new_cont =
3911 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3912 struct mlx5_counter_stats_mem_mng *mem_mng;
3913 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3914 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3917 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3918 /* The last resize still hasn't detected by the host thread. */
3922 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3923 if (!new_cont->pools) {
3928 memcpy(new_cont->pools, cont->pools, cont->n *
3929 sizeof(struct mlx5_flow_counter_pool *));
3930 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3931 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3933 rte_free(new_cont->pools);
3936 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3937 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3938 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3940 new_cont->n = resize;
3941 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3942 TAILQ_INIT(&new_cont->pool_list);
3943 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3944 new_cont->init_mem_mng = mem_mng;
3946 /* Flip the master container. */
3947 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3952 * Query a devx flow counter.
3955 * Pointer to the Ethernet device structure.
3957 * Pointer to the flow counter.
3959 * The statistics value of packets.
3961 * The statistics value of bytes.
3964 * 0 on success, otherwise a negative errno value and rte_errno is set.
3967 _flow_dv_query_count(struct rte_eth_dev *dev,
3968 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3971 struct mlx5_priv *priv = dev->data->dev_private;
3972 struct mlx5_flow_counter_pool *pool =
3973 flow_dv_counter_pool_get(cnt);
3974 int offset = cnt - &pool->counters_raw[0];
3976 if (priv->counter_fallback)
3977 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3979 rte_spinlock_lock(&pool->sl);
3981 * The single counters allocation may allocate smaller ID than the
3982 * current allocated in parallel to the host reading.
3983 * In this case the new counter values must be reported as 0.
3985 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3989 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3990 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3992 rte_spinlock_unlock(&pool->sl);
3997 * Create and initialize a new counter pool.
4000 * Pointer to the Ethernet device structure.
4002 * The devX counter handle.
4004 * Whether the pool is for counter that was allocated by batch command.
4007 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4009 static struct mlx5_flow_counter_pool *
4010 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4013 struct mlx5_priv *priv = dev->data->dev_private;
4014 struct mlx5_flow_counter_pool *pool;
4015 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4017 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4020 if (cont->n == n_valid) {
4021 cont = flow_dv_container_resize(dev, batch);
4025 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4026 sizeof(struct mlx5_flow_counter);
4027 pool = rte_calloc(__func__, 1, size, 0);
4032 pool->min_dcs = dcs;
4033 pool->raw = cont->init_mem_mng->raws + n_valid %
4034 MLX5_CNT_CONTAINER_RESIZE;
4035 pool->raw_hw = NULL;
4036 rte_spinlock_init(&pool->sl);
4038 * The generation of the new allocated counters in this pool is 0, 2 in
4039 * the pool generation makes all the counters valid for allocation.
4041 rte_atomic64_set(&pool->query_gen, 0x2);
4042 TAILQ_INIT(&pool->counters);
4043 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4044 cont->pools[n_valid] = pool;
4045 /* Pool initialization must be updated before host thread access. */
4047 rte_atomic16_add(&cont->n_valid, 1);
4052 * Prepare a new counter and/or a new counter pool.
4055 * Pointer to the Ethernet device structure.
4056 * @param[out] cnt_free
4057 * Where to put the pointer of a new counter.
4059 * Whether the pool is for counter that was allocated by batch command.
4062 * The free counter pool pointer and @p cnt_free is set on success,
4063 * NULL otherwise and rte_errno is set.
4065 static struct mlx5_flow_counter_pool *
4066 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4067 struct mlx5_flow_counter **cnt_free,
4070 struct mlx5_priv *priv = dev->data->dev_private;
4071 struct mlx5_flow_counter_pool *pool;
4072 struct mlx5_devx_obj *dcs = NULL;
4073 struct mlx5_flow_counter *cnt;
4077 /* bulk_bitmap must be 0 for single counter allocation. */
4078 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4081 pool = flow_dv_find_pool_by_id
4082 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4084 pool = flow_dv_pool_create(dev, dcs, batch);
4086 mlx5_devx_cmd_destroy(dcs);
4089 } else if (dcs->id < pool->min_dcs->id) {
4090 rte_atomic64_set(&pool->a64_dcs,
4091 (int64_t)(uintptr_t)dcs);
4093 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4094 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4099 /* bulk_bitmap is in 128 counters units. */
4100 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4101 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4103 rte_errno = ENODATA;
4106 pool = flow_dv_pool_create(dev, dcs, batch);
4108 mlx5_devx_cmd_destroy(dcs);
4111 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4112 cnt = &pool->counters_raw[i];
4114 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4116 *cnt_free = &pool->counters_raw[0];
4121 * Search for existed shared counter.
4124 * Pointer to the relevant counter pool container.
4126 * The shared counter ID to search.
4129 * NULL if not existed, otherwise pointer to the shared counter.
4131 static struct mlx5_flow_counter *
4132 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4135 static struct mlx5_flow_counter *cnt;
4136 struct mlx5_flow_counter_pool *pool;
4139 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4140 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4141 cnt = &pool->counters_raw[i];
4142 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4150 * Allocate a flow counter.
4153 * Pointer to the Ethernet device structure.
4155 * Indicate if this counter is shared with other flows.
4157 * Counter identifier.
4159 * Counter flow group.
4162 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4164 static struct mlx5_flow_counter *
4165 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4168 struct mlx5_priv *priv = dev->data->dev_private;
4169 struct mlx5_flow_counter_pool *pool = NULL;
4170 struct mlx5_flow_counter *cnt_free = NULL;
4172 * Currently group 0 flow counter cannot be assigned to a flow if it is
4173 * not the first one in the batch counter allocation, so it is better
4174 * to allocate counters one by one for these flows in a separate
4176 * A counter can be shared between different groups so need to take
4177 * shared counters from the single container.
4179 uint32_t batch = (group && !shared) ? 1 : 0;
4180 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4183 if (priv->counter_fallback)
4184 return flow_dv_counter_alloc_fallback(dev, shared, id);
4185 if (!priv->config.devx) {
4186 rte_errno = ENOTSUP;
4190 cnt_free = flow_dv_counter_shared_search(cont, id);
4192 if (cnt_free->ref_cnt + 1 == 0) {
4196 cnt_free->ref_cnt++;
4200 /* Pools which has a free counters are in the start. */
4201 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4203 * The free counter reset values must be updated between the
4204 * counter release to the counter allocation, so, at least one
4205 * query must be done in this time. ensure it by saving the
4206 * query generation in the release time.
4207 * The free list is sorted according to the generation - so if
4208 * the first one is not updated, all the others are not
4211 cnt_free = TAILQ_FIRST(&pool->counters);
4212 if (cnt_free && cnt_free->query_gen + 1 <
4213 rte_atomic64_read(&pool->query_gen))
4218 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4222 cnt_free->batch = batch;
4223 /* Create a DV counter action only in the first time usage. */
4224 if (!cnt_free->action) {
4226 struct mlx5_devx_obj *dcs;
4229 offset = cnt_free - &pool->counters_raw[0];
4230 dcs = pool->min_dcs;
4233 dcs = cnt_free->dcs;
4235 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4237 if (!cnt_free->action) {
4242 /* Update the counter reset values. */
4243 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4246 cnt_free->shared = shared;
4247 cnt_free->ref_cnt = 1;
4249 if (!priv->sh->cmng.query_thread_on)
4250 /* Start the asynchronous batch query by the host thread. */
4251 mlx5_set_query_alarm(priv->sh);
4252 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4253 if (TAILQ_EMPTY(&pool->counters)) {
4254 /* Move the pool to the end of the container pool list. */
4255 TAILQ_REMOVE(&cont->pool_list, pool, next);
4256 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4262 * Release a flow counter.
4265 * Pointer to the Ethernet device structure.
4266 * @param[in] counter
4267 * Pointer to the counter handler.
4270 flow_dv_counter_release(struct rte_eth_dev *dev,
4271 struct mlx5_flow_counter *counter)
4273 struct mlx5_priv *priv = dev->data->dev_private;
4277 if (priv->counter_fallback) {
4278 flow_dv_counter_release_fallback(dev, counter);
4281 if (--counter->ref_cnt == 0) {
4282 struct mlx5_flow_counter_pool *pool =
4283 flow_dv_counter_pool_get(counter);
4285 /* Put the counter in the end - the last updated one. */
4286 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4287 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4292 * Verify the @p attributes will be correctly understood by the NIC and store
4293 * them in the @p flow if everything is correct.
4296 * Pointer to dev struct.
4297 * @param[in] attributes
4298 * Pointer to flow attributes
4299 * @param[in] external
4300 * This flow rule is created by request external to PMD.
4302 * Pointer to error structure.
4305 * 0 on success, a negative errno value otherwise and rte_errno is set.
4308 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4309 const struct rte_flow_attr *attributes,
4310 bool external __rte_unused,
4311 struct rte_flow_error *error)
4313 struct mlx5_priv *priv = dev->data->dev_private;
4314 uint32_t priority_max = priv->config.flow_prio - 1;
4316 #ifndef HAVE_MLX5DV_DR
4317 if (attributes->group)
4318 return rte_flow_error_set(error, ENOTSUP,
4319 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4321 "groups are not supported");
4326 ret = mlx5_flow_group_to_table(attributes, external,
4327 attributes->group, !!priv->fdb_def_rule,
4332 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4333 attributes->priority >= priority_max)
4334 return rte_flow_error_set(error, ENOTSUP,
4335 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4337 "priority out of range");
4338 if (attributes->transfer) {
4339 if (!priv->config.dv_esw_en)
4340 return rte_flow_error_set
4342 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4343 "E-Switch dr is not supported");
4344 if (!(priv->representor || priv->master))
4345 return rte_flow_error_set
4346 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4347 NULL, "E-Switch configuration can only be"
4348 " done by a master or a representor device");
4349 if (attributes->egress)
4350 return rte_flow_error_set
4352 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4353 "egress is not supported");
4355 if (!(attributes->egress ^ attributes->ingress))
4356 return rte_flow_error_set(error, ENOTSUP,
4357 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4358 "must specify exactly one of "
4359 "ingress or egress");
4364 * Internal validation function. For validating both actions and items.
4367 * Pointer to the rte_eth_dev structure.
4369 * Pointer to the flow attributes.
4371 * Pointer to the list of items.
4372 * @param[in] actions
4373 * Pointer to the list of actions.
4374 * @param[in] external
4375 * This flow rule is created by request external to PMD.
4377 * Pointer to the error structure.
4380 * 0 on success, a negative errno value otherwise and rte_errno is set.
4383 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4384 const struct rte_flow_item items[],
4385 const struct rte_flow_action actions[],
4386 bool external, struct rte_flow_error *error)
4389 uint64_t action_flags = 0;
4390 uint64_t item_flags = 0;
4391 uint64_t last_item = 0;
4392 uint8_t next_protocol = 0xff;
4393 uint16_t ether_type = 0;
4395 uint8_t item_ipv6_proto = 0;
4396 const struct rte_flow_item *gre_item = NULL;
4397 const struct rte_flow_action_raw_decap *decap;
4398 const struct rte_flow_action_raw_encap *encap;
4399 const struct rte_flow_action_rss *rss;
4400 struct rte_flow_item_tcp nic_tcp_mask = {
4403 .src_port = RTE_BE16(UINT16_MAX),
4404 .dst_port = RTE_BE16(UINT16_MAX),
4407 struct mlx5_priv *priv = dev->data->dev_private;
4408 struct mlx5_dev_config *dev_conf = &priv->config;
4409 uint16_t queue_index = 0xFFFF;
4413 ret = flow_dv_validate_attributes(dev, attr, external, error);
4416 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4417 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4418 int type = items->type;
4421 case RTE_FLOW_ITEM_TYPE_VOID:
4423 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4424 ret = flow_dv_validate_item_port_id
4425 (dev, items, attr, item_flags, error);
4428 last_item = MLX5_FLOW_ITEM_PORT_ID;
4430 case RTE_FLOW_ITEM_TYPE_ETH:
4431 ret = mlx5_flow_validate_item_eth(items, item_flags,
4435 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4436 MLX5_FLOW_LAYER_OUTER_L2;
4437 if (items->mask != NULL && items->spec != NULL) {
4439 ((const struct rte_flow_item_eth *)
4442 ((const struct rte_flow_item_eth *)
4444 ether_type = rte_be_to_cpu_16(ether_type);
4449 case RTE_FLOW_ITEM_TYPE_VLAN:
4450 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4454 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4455 MLX5_FLOW_LAYER_OUTER_VLAN;
4456 if (items->mask != NULL && items->spec != NULL) {
4458 ((const struct rte_flow_item_vlan *)
4459 items->spec)->inner_type;
4461 ((const struct rte_flow_item_vlan *)
4462 items->mask)->inner_type;
4463 ether_type = rte_be_to_cpu_16(ether_type);
4468 case RTE_FLOW_ITEM_TYPE_IPV4:
4469 mlx5_flow_tunnel_ip_check(items, next_protocol,
4470 &item_flags, &tunnel);
4471 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4477 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4478 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4479 if (items->mask != NULL &&
4480 ((const struct rte_flow_item_ipv4 *)
4481 items->mask)->hdr.next_proto_id) {
4483 ((const struct rte_flow_item_ipv4 *)
4484 (items->spec))->hdr.next_proto_id;
4486 ((const struct rte_flow_item_ipv4 *)
4487 (items->mask))->hdr.next_proto_id;
4489 /* Reset for inner layer. */
4490 next_protocol = 0xff;
4493 case RTE_FLOW_ITEM_TYPE_IPV6:
4494 mlx5_flow_tunnel_ip_check(items, next_protocol,
4495 &item_flags, &tunnel);
4496 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4502 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4503 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4504 if (items->mask != NULL &&
4505 ((const struct rte_flow_item_ipv6 *)
4506 items->mask)->hdr.proto) {
4508 ((const struct rte_flow_item_ipv6 *)
4509 items->spec)->hdr.proto;
4511 ((const struct rte_flow_item_ipv6 *)
4512 items->spec)->hdr.proto;
4514 ((const struct rte_flow_item_ipv6 *)
4515 items->mask)->hdr.proto;
4517 /* Reset for inner layer. */
4518 next_protocol = 0xff;
4521 case RTE_FLOW_ITEM_TYPE_TCP:
4522 ret = mlx5_flow_validate_item_tcp
4529 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4530 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4532 case RTE_FLOW_ITEM_TYPE_UDP:
4533 ret = mlx5_flow_validate_item_udp(items, item_flags,
4538 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4539 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4541 case RTE_FLOW_ITEM_TYPE_GRE:
4542 ret = mlx5_flow_validate_item_gre(items, item_flags,
4543 next_protocol, error);
4547 last_item = MLX5_FLOW_LAYER_GRE;
4549 case RTE_FLOW_ITEM_TYPE_NVGRE:
4550 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4555 last_item = MLX5_FLOW_LAYER_NVGRE;
4557 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4558 ret = mlx5_flow_validate_item_gre_key
4559 (items, item_flags, gre_item, error);
4562 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4564 case RTE_FLOW_ITEM_TYPE_VXLAN:
4565 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4569 last_item = MLX5_FLOW_LAYER_VXLAN;
4571 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4572 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4577 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4579 case RTE_FLOW_ITEM_TYPE_GENEVE:
4580 ret = mlx5_flow_validate_item_geneve(items,
4585 last_item = MLX5_FLOW_LAYER_GENEVE;
4587 case RTE_FLOW_ITEM_TYPE_MPLS:
4588 ret = mlx5_flow_validate_item_mpls(dev, items,
4593 last_item = MLX5_FLOW_LAYER_MPLS;
4596 case RTE_FLOW_ITEM_TYPE_MARK:
4597 ret = flow_dv_validate_item_mark(dev, items, attr,
4601 last_item = MLX5_FLOW_ITEM_MARK;
4603 case RTE_FLOW_ITEM_TYPE_META:
4604 ret = flow_dv_validate_item_meta(dev, items, attr,
4608 last_item = MLX5_FLOW_ITEM_METADATA;
4610 case RTE_FLOW_ITEM_TYPE_ICMP:
4611 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4616 last_item = MLX5_FLOW_LAYER_ICMP;
4618 case RTE_FLOW_ITEM_TYPE_ICMP6:
4619 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4624 item_ipv6_proto = IPPROTO_ICMPV6;
4625 last_item = MLX5_FLOW_LAYER_ICMP6;
4627 case RTE_FLOW_ITEM_TYPE_TAG:
4628 ret = flow_dv_validate_item_tag(dev, items,
4632 last_item = MLX5_FLOW_ITEM_TAG;
4634 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4635 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4637 case RTE_FLOW_ITEM_TYPE_GTP:
4638 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4642 last_item = MLX5_FLOW_LAYER_GTP;
4645 return rte_flow_error_set(error, ENOTSUP,
4646 RTE_FLOW_ERROR_TYPE_ITEM,
4647 NULL, "item not supported");
4649 item_flags |= last_item;
4651 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4652 int type = actions->type;
4653 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4654 return rte_flow_error_set(error, ENOTSUP,
4655 RTE_FLOW_ERROR_TYPE_ACTION,
4656 actions, "too many actions");
4658 case RTE_FLOW_ACTION_TYPE_VOID:
4660 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4661 ret = flow_dv_validate_action_port_id(dev,
4668 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4671 case RTE_FLOW_ACTION_TYPE_FLAG:
4672 ret = flow_dv_validate_action_flag(dev, action_flags,
4676 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4677 /* Count all modify-header actions as one. */
4678 if (!(action_flags &
4679 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4681 action_flags |= MLX5_FLOW_ACTION_FLAG |
4682 MLX5_FLOW_ACTION_MARK_EXT;
4684 action_flags |= MLX5_FLOW_ACTION_FLAG;
4688 case RTE_FLOW_ACTION_TYPE_MARK:
4689 ret = flow_dv_validate_action_mark(dev, actions,
4694 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4695 /* Count all modify-header actions as one. */
4696 if (!(action_flags &
4697 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4699 action_flags |= MLX5_FLOW_ACTION_MARK |
4700 MLX5_FLOW_ACTION_MARK_EXT;
4702 action_flags |= MLX5_FLOW_ACTION_MARK;
4706 case RTE_FLOW_ACTION_TYPE_SET_META:
4707 ret = flow_dv_validate_action_set_meta(dev, actions,
4712 /* Count all modify-header actions as one action. */
4713 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4715 action_flags |= MLX5_FLOW_ACTION_SET_META;
4717 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4718 ret = flow_dv_validate_action_set_tag(dev, actions,
4723 /* Count all modify-header actions as one action. */
4724 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4726 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4728 case RTE_FLOW_ACTION_TYPE_DROP:
4729 ret = mlx5_flow_validate_action_drop(action_flags,
4733 action_flags |= MLX5_FLOW_ACTION_DROP;
4736 case RTE_FLOW_ACTION_TYPE_QUEUE:
4737 ret = mlx5_flow_validate_action_queue(actions,
4742 queue_index = ((const struct rte_flow_action_queue *)
4743 (actions->conf))->index;
4744 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4747 case RTE_FLOW_ACTION_TYPE_RSS:
4748 rss = actions->conf;
4749 ret = mlx5_flow_validate_action_rss(actions,
4755 if (rss != NULL && rss->queue_num)
4756 queue_index = rss->queue[0];
4757 action_flags |= MLX5_FLOW_ACTION_RSS;
4760 case RTE_FLOW_ACTION_TYPE_COUNT:
4761 ret = flow_dv_validate_action_count(dev, error);
4764 action_flags |= MLX5_FLOW_ACTION_COUNT;
4767 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4768 if (flow_dv_validate_action_pop_vlan(dev,
4774 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4777 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4778 ret = flow_dv_validate_action_push_vlan(action_flags,
4784 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4787 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4788 ret = flow_dv_validate_action_set_vlan_pcp
4789 (action_flags, actions, error);
4792 /* Count PCP with push_vlan command. */
4793 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4795 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4796 ret = flow_dv_validate_action_set_vlan_vid
4797 (item_flags, action_flags,
4801 /* Count VID with push_vlan command. */
4802 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4804 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4805 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4806 ret = flow_dv_validate_action_l2_encap(action_flags,
4810 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4813 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4814 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4815 ret = flow_dv_validate_action_decap(action_flags, attr,
4819 action_flags |= MLX5_FLOW_ACTION_DECAP;
4822 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4823 ret = flow_dv_validate_action_raw_encap_decap
4824 (NULL, actions->conf, attr, &action_flags,
4829 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4830 decap = actions->conf;
4831 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
4833 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4837 encap = actions->conf;
4839 ret = flow_dv_validate_action_raw_encap_decap
4840 (decap ? decap : &empty_decap, encap,
4841 attr, &action_flags, &actions_n,
4846 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4847 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4848 ret = flow_dv_validate_action_modify_mac(action_flags,
4854 /* Count all modify-header actions as one action. */
4855 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4857 action_flags |= actions->type ==
4858 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4859 MLX5_FLOW_ACTION_SET_MAC_SRC :
4860 MLX5_FLOW_ACTION_SET_MAC_DST;
4863 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4864 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4865 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4871 /* Count all modify-header actions as one action. */
4872 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4874 action_flags |= actions->type ==
4875 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4876 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4877 MLX5_FLOW_ACTION_SET_IPV4_DST;
4879 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4880 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4881 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4887 if (item_ipv6_proto == IPPROTO_ICMPV6)
4888 return rte_flow_error_set(error, ENOTSUP,
4889 RTE_FLOW_ERROR_TYPE_ACTION,
4891 "Can't change header "
4892 "with ICMPv6 proto");
4893 /* Count all modify-header actions as one action. */
4894 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4896 action_flags |= actions->type ==
4897 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4898 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4899 MLX5_FLOW_ACTION_SET_IPV6_DST;
4901 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4902 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4903 ret = flow_dv_validate_action_modify_tp(action_flags,
4909 /* Count all modify-header actions as one action. */
4910 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4912 action_flags |= actions->type ==
4913 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4914 MLX5_FLOW_ACTION_SET_TP_SRC :
4915 MLX5_FLOW_ACTION_SET_TP_DST;
4917 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4918 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4919 ret = flow_dv_validate_action_modify_ttl(action_flags,
4925 /* Count all modify-header actions as one action. */
4926 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4928 action_flags |= actions->type ==
4929 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4930 MLX5_FLOW_ACTION_SET_TTL :
4931 MLX5_FLOW_ACTION_DEC_TTL;
4933 case RTE_FLOW_ACTION_TYPE_JUMP:
4934 ret = flow_dv_validate_action_jump(actions,
4941 action_flags |= MLX5_FLOW_ACTION_JUMP;
4943 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4944 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4945 ret = flow_dv_validate_action_modify_tcp_seq
4952 /* Count all modify-header actions as one action. */
4953 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4955 action_flags |= actions->type ==
4956 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4957 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4958 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4960 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4961 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4962 ret = flow_dv_validate_action_modify_tcp_ack
4969 /* Count all modify-header actions as one action. */
4970 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4972 action_flags |= actions->type ==
4973 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4974 MLX5_FLOW_ACTION_INC_TCP_ACK :
4975 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4977 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4978 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
4979 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4981 case RTE_FLOW_ACTION_TYPE_METER:
4982 ret = mlx5_flow_validate_action_meter(dev,
4988 action_flags |= MLX5_FLOW_ACTION_METER;
4991 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
4992 ret = flow_dv_validate_action_modify_ipv4_dscp
4999 /* Count all modify-header actions as one action. */
5000 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5002 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5004 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5005 ret = flow_dv_validate_action_modify_ipv6_dscp
5012 /* Count all modify-header actions as one action. */
5013 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5015 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5018 return rte_flow_error_set(error, ENOTSUP,
5019 RTE_FLOW_ERROR_TYPE_ACTION,
5021 "action not supported");
5025 * Validate the drop action mutual exclusion with other actions.
5026 * Drop action is mutually-exclusive with any other action, except for
5029 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5030 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5031 return rte_flow_error_set(error, EINVAL,
5032 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5033 "Drop action is mutually-exclusive "
5034 "with any other action, except for "
5036 /* Eswitch has few restrictions on using items and actions */
5037 if (attr->transfer) {
5038 if (!mlx5_flow_ext_mreg_supported(dev) &&
5039 action_flags & MLX5_FLOW_ACTION_FLAG)
5040 return rte_flow_error_set(error, ENOTSUP,
5041 RTE_FLOW_ERROR_TYPE_ACTION,
5043 "unsupported action FLAG");
5044 if (!mlx5_flow_ext_mreg_supported(dev) &&
5045 action_flags & MLX5_FLOW_ACTION_MARK)
5046 return rte_flow_error_set(error, ENOTSUP,
5047 RTE_FLOW_ERROR_TYPE_ACTION,
5049 "unsupported action MARK");
5050 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5051 return rte_flow_error_set(error, ENOTSUP,
5052 RTE_FLOW_ERROR_TYPE_ACTION,
5054 "unsupported action QUEUE");
5055 if (action_flags & MLX5_FLOW_ACTION_RSS)
5056 return rte_flow_error_set(error, ENOTSUP,
5057 RTE_FLOW_ERROR_TYPE_ACTION,
5059 "unsupported action RSS");
5060 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5061 return rte_flow_error_set(error, EINVAL,
5062 RTE_FLOW_ERROR_TYPE_ACTION,
5064 "no fate action is found");
5066 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5067 return rte_flow_error_set(error, EINVAL,
5068 RTE_FLOW_ERROR_TYPE_ACTION,
5070 "no fate action is found");
5072 /* Continue validation for Xcap actions.*/
5073 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5074 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5075 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5076 MLX5_FLOW_XCAP_ACTIONS)
5077 return rte_flow_error_set(error, ENOTSUP,
5078 RTE_FLOW_ERROR_TYPE_ACTION,
5079 NULL, "encap and decap "
5080 "combination aren't supported");
5081 if (!attr->transfer && attr->ingress && (action_flags &
5082 MLX5_FLOW_ACTION_ENCAP))
5083 return rte_flow_error_set(error, ENOTSUP,
5084 RTE_FLOW_ERROR_TYPE_ACTION,
5085 NULL, "encap is not supported"
5086 " for ingress traffic");
5092 * Internal preparation function. Allocates the DV flow size,
5093 * this size is constant.
5096 * Pointer to the flow attributes.
5098 * Pointer to the list of items.
5099 * @param[in] actions
5100 * Pointer to the list of actions.
5102 * Pointer to the error structure.
5105 * Pointer to mlx5_flow object on success,
5106 * otherwise NULL and rte_errno is set.
5108 static struct mlx5_flow *
5109 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5110 const struct rte_flow_item items[] __rte_unused,
5111 const struct rte_flow_action actions[] __rte_unused,
5112 struct rte_flow_error *error)
5114 size_t size = sizeof(struct mlx5_flow);
5115 struct mlx5_flow *dev_flow;
5117 dev_flow = rte_calloc(__func__, 1, size, 0);
5119 rte_flow_error_set(error, ENOMEM,
5120 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5121 "not enough memory to create flow");
5124 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5125 dev_flow->ingress = attr->ingress;
5126 dev_flow->transfer = attr->transfer;
5130 #ifdef RTE_LIBRTE_MLX5_DEBUG
5132 * Sanity check for match mask and value. Similar to check_valid_spec() in
5133 * kernel driver. If unmasked bit is present in value, it returns failure.
5136 * pointer to match mask buffer.
5137 * @param match_value
5138 * pointer to match value buffer.
5141 * 0 if valid, -EINVAL otherwise.
5144 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5146 uint8_t *m = match_mask;
5147 uint8_t *v = match_value;
5150 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5153 "match_value differs from match_criteria"
5154 " %p[%u] != %p[%u]",
5155 match_value, i, match_mask, i);
5164 * Add Ethernet item to matcher and to the value.
5166 * @param[in, out] matcher
5168 * @param[in, out] key
5169 * Flow matcher value.
5171 * Flow pattern to translate.
5173 * Item is inner pattern.
5176 flow_dv_translate_item_eth(void *matcher, void *key,
5177 const struct rte_flow_item *item, int inner)
5179 const struct rte_flow_item_eth *eth_m = item->mask;
5180 const struct rte_flow_item_eth *eth_v = item->spec;
5181 const struct rte_flow_item_eth nic_mask = {
5182 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5183 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5184 .type = RTE_BE16(0xffff),
5196 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5198 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5200 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5202 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5204 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5205 ð_m->dst, sizeof(eth_m->dst));
5206 /* The value must be in the range of the mask. */
5207 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5208 for (i = 0; i < sizeof(eth_m->dst); ++i)
5209 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5210 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5211 ð_m->src, sizeof(eth_m->src));
5212 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5213 /* The value must be in the range of the mask. */
5214 for (i = 0; i < sizeof(eth_m->dst); ++i)
5215 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5217 rte_be_to_cpu_16(eth_m->type));
5218 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5219 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5221 /* When ethertype is present set mask for tagged VLAN. */
5222 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5223 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5224 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5225 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ))
5226 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5232 * Add VLAN item to matcher and to the value.
5234 * @param[in, out] dev_flow
5236 * @param[in, out] matcher
5238 * @param[in, out] key
5239 * Flow matcher value.
5241 * Flow pattern to translate.
5243 * Item is inner pattern.
5246 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5247 void *matcher, void *key,
5248 const struct rte_flow_item *item,
5251 const struct rte_flow_item_vlan *vlan_m = item->mask;
5252 const struct rte_flow_item_vlan *vlan_v = item->spec;
5261 vlan_m = &rte_flow_item_vlan_mask;
5263 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5265 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5267 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5269 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5271 * This is workaround, masks are not supported,
5272 * and pre-validated.
5274 dev_flow->dv.vf_vlan.tag =
5275 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5277 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5278 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5279 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5280 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5281 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5283 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5284 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5285 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5286 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5287 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5288 rte_be_to_cpu_16(vlan_m->inner_type));
5289 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5290 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5294 * Add IPV4 item to matcher and to the value.
5296 * @param[in, out] matcher
5298 * @param[in, out] key
5299 * Flow matcher value.
5301 * Flow pattern to translate.
5303 * Item is inner pattern.
5305 * The group to insert the rule.
5308 flow_dv_translate_item_ipv4(void *matcher, void *key,
5309 const struct rte_flow_item *item,
5310 int inner, uint32_t group)
5312 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5313 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5314 const struct rte_flow_item_ipv4 nic_mask = {
5316 .src_addr = RTE_BE32(0xffffffff),
5317 .dst_addr = RTE_BE32(0xffffffff),
5318 .type_of_service = 0xff,
5319 .next_proto_id = 0xff,
5329 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5331 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5333 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5335 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5338 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5340 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5341 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5346 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5347 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5348 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5349 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5350 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5351 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5352 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5353 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5354 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5355 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5356 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5357 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5358 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5359 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5360 ipv4_m->hdr.type_of_service);
5361 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5362 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5363 ipv4_m->hdr.type_of_service >> 2);
5364 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5365 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5366 ipv4_m->hdr.next_proto_id);
5367 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5368 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5369 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5373 * Add IPV6 item to matcher and to the value.
5375 * @param[in, out] matcher
5377 * @param[in, out] key
5378 * Flow matcher value.
5380 * Flow pattern to translate.
5382 * Item is inner pattern.
5384 * The group to insert the rule.
5387 flow_dv_translate_item_ipv6(void *matcher, void *key,
5388 const struct rte_flow_item *item,
5389 int inner, uint32_t group)
5391 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5392 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5393 const struct rte_flow_item_ipv6 nic_mask = {
5396 "\xff\xff\xff\xff\xff\xff\xff\xff"
5397 "\xff\xff\xff\xff\xff\xff\xff\xff",
5399 "\xff\xff\xff\xff\xff\xff\xff\xff"
5400 "\xff\xff\xff\xff\xff\xff\xff\xff",
5401 .vtc_flow = RTE_BE32(0xffffffff),
5408 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5409 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5418 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5420 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5422 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5424 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5427 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5429 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5435 size = sizeof(ipv6_m->hdr.dst_addr);
5436 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5437 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5438 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5439 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5440 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5441 for (i = 0; i < size; ++i)
5442 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5443 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5444 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5445 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5446 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5447 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5448 for (i = 0; i < size; ++i)
5449 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5451 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5452 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5453 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5454 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5455 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5456 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5459 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5461 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5464 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5466 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5470 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5472 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5473 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5474 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5478 * Add TCP item to matcher and to the value.
5480 * @param[in, out] matcher
5482 * @param[in, out] key
5483 * Flow matcher value.
5485 * Flow pattern to translate.
5487 * Item is inner pattern.
5490 flow_dv_translate_item_tcp(void *matcher, void *key,
5491 const struct rte_flow_item *item,
5494 const struct rte_flow_item_tcp *tcp_m = item->mask;
5495 const struct rte_flow_item_tcp *tcp_v = item->spec;
5500 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5502 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5504 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5506 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5508 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5509 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5513 tcp_m = &rte_flow_item_tcp_mask;
5514 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5515 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5517 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5518 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5519 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5521 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5522 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5523 tcp_m->hdr.tcp_flags);
5524 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5525 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5529 * Add UDP item to matcher and to the value.
5531 * @param[in, out] matcher
5533 * @param[in, out] key
5534 * Flow matcher value.
5536 * Flow pattern to translate.
5538 * Item is inner pattern.
5541 flow_dv_translate_item_udp(void *matcher, void *key,
5542 const struct rte_flow_item *item,
5545 const struct rte_flow_item_udp *udp_m = item->mask;
5546 const struct rte_flow_item_udp *udp_v = item->spec;
5551 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5553 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5555 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5557 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5559 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5560 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5564 udp_m = &rte_flow_item_udp_mask;
5565 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5566 rte_be_to_cpu_16(udp_m->hdr.src_port));
5567 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5568 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5569 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5570 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5571 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5572 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5576 * Add GRE optional Key item to matcher and to the value.
5578 * @param[in, out] matcher
5580 * @param[in, out] key
5581 * Flow matcher value.
5583 * Flow pattern to translate.
5585 * Item is inner pattern.
5588 flow_dv_translate_item_gre_key(void *matcher, void *key,
5589 const struct rte_flow_item *item)
5591 const rte_be32_t *key_m = item->mask;
5592 const rte_be32_t *key_v = item->spec;
5593 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5594 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5595 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5597 /* GRE K bit must be on and should already be validated */
5598 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5599 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5603 key_m = &gre_key_default_mask;
5604 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5605 rte_be_to_cpu_32(*key_m) >> 8);
5606 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5607 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5608 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5609 rte_be_to_cpu_32(*key_m) & 0xFF);
5610 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5611 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5615 * Add GRE item to matcher and to the value.
5617 * @param[in, out] matcher
5619 * @param[in, out] key
5620 * Flow matcher value.
5622 * Flow pattern to translate.
5624 * Item is inner pattern.
5627 flow_dv_translate_item_gre(void *matcher, void *key,
5628 const struct rte_flow_item *item,
5631 const struct rte_flow_item_gre *gre_m = item->mask;
5632 const struct rte_flow_item_gre *gre_v = item->spec;
5635 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5636 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5643 uint16_t s_present:1;
5644 uint16_t k_present:1;
5645 uint16_t rsvd_bit1:1;
5646 uint16_t c_present:1;
5650 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5653 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5655 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5657 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5659 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5661 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5666 gre_m = &rte_flow_item_gre_mask;
5667 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5668 rte_be_to_cpu_16(gre_m->protocol));
5669 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5670 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5671 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5672 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5673 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5674 gre_crks_rsvd0_ver_m.c_present);
5675 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5676 gre_crks_rsvd0_ver_v.c_present &
5677 gre_crks_rsvd0_ver_m.c_present);
5678 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5679 gre_crks_rsvd0_ver_m.k_present);
5680 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5681 gre_crks_rsvd0_ver_v.k_present &
5682 gre_crks_rsvd0_ver_m.k_present);
5683 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5684 gre_crks_rsvd0_ver_m.s_present);
5685 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5686 gre_crks_rsvd0_ver_v.s_present &
5687 gre_crks_rsvd0_ver_m.s_present);
5691 * Add NVGRE item to matcher and to the value.
5693 * @param[in, out] matcher
5695 * @param[in, out] key
5696 * Flow matcher value.
5698 * Flow pattern to translate.
5700 * Item is inner pattern.
5703 flow_dv_translate_item_nvgre(void *matcher, void *key,
5704 const struct rte_flow_item *item,
5707 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5708 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5709 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5710 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5711 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5712 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5718 /* For NVGRE, GRE header fields must be set with defined values. */
5719 const struct rte_flow_item_gre gre_spec = {
5720 .c_rsvd0_ver = RTE_BE16(0x2000),
5721 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5723 const struct rte_flow_item_gre gre_mask = {
5724 .c_rsvd0_ver = RTE_BE16(0xB000),
5725 .protocol = RTE_BE16(UINT16_MAX),
5727 const struct rte_flow_item gre_item = {
5732 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5736 nvgre_m = &rte_flow_item_nvgre_mask;
5737 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5738 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5739 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5740 memcpy(gre_key_m, tni_flow_id_m, size);
5741 for (i = 0; i < size; ++i)
5742 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5746 * Add VXLAN item to matcher and to the value.
5748 * @param[in, out] matcher
5750 * @param[in, out] key
5751 * Flow matcher value.
5753 * Flow pattern to translate.
5755 * Item is inner pattern.
5758 flow_dv_translate_item_vxlan(void *matcher, void *key,
5759 const struct rte_flow_item *item,
5762 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5763 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5766 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5767 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5775 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5777 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5779 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5781 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5783 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5784 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5785 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5786 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5792 vxlan_m = &rte_flow_item_vxlan_mask;
5793 size = sizeof(vxlan_m->vni);
5794 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5795 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5796 memcpy(vni_m, vxlan_m->vni, size);
5797 for (i = 0; i < size; ++i)
5798 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5802 * Add VXLAN-GPE item to matcher and to the value.
5804 * @param[in, out] matcher
5806 * @param[in, out] key
5807 * Flow matcher value.
5809 * Flow pattern to translate.
5811 * Item is inner pattern.
5815 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
5816 const struct rte_flow_item *item, int inner)
5818 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
5819 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
5823 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
5825 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5831 uint8_t flags_m = 0xff;
5832 uint8_t flags_v = 0xc;
5835 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5837 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5839 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5841 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5843 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5844 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5845 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5846 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5847 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5852 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
5853 size = sizeof(vxlan_m->vni);
5854 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
5855 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
5856 memcpy(vni_m, vxlan_m->vni, size);
5857 for (i = 0; i < size; ++i)
5858 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5859 if (vxlan_m->flags) {
5860 flags_m = vxlan_m->flags;
5861 flags_v = vxlan_v->flags;
5863 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
5864 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
5865 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
5867 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
5872 * Add Geneve item to matcher and to the value.
5874 * @param[in, out] matcher
5876 * @param[in, out] key
5877 * Flow matcher value.
5879 * Flow pattern to translate.
5881 * Item is inner pattern.
5885 flow_dv_translate_item_geneve(void *matcher, void *key,
5886 const struct rte_flow_item *item, int inner)
5888 const struct rte_flow_item_geneve *geneve_m = item->mask;
5889 const struct rte_flow_item_geneve *geneve_v = item->spec;
5892 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5893 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5902 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5904 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5906 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5908 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5910 dport = MLX5_UDP_PORT_GENEVE;
5911 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5912 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5913 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5918 geneve_m = &rte_flow_item_geneve_mask;
5919 size = sizeof(geneve_m->vni);
5920 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5921 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5922 memcpy(vni_m, geneve_m->vni, size);
5923 for (i = 0; i < size; ++i)
5924 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5925 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5926 rte_be_to_cpu_16(geneve_m->protocol));
5927 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5928 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5929 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5930 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5931 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5932 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5933 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5934 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5935 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5936 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5937 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5938 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5939 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5943 * Add MPLS item to matcher and to the value.
5945 * @param[in, out] matcher
5947 * @param[in, out] key
5948 * Flow matcher value.
5950 * Flow pattern to translate.
5951 * @param[in] prev_layer
5952 * The protocol layer indicated in previous item.
5954 * Item is inner pattern.
5957 flow_dv_translate_item_mpls(void *matcher, void *key,
5958 const struct rte_flow_item *item,
5959 uint64_t prev_layer,
5962 const uint32_t *in_mpls_m = item->mask;
5963 const uint32_t *in_mpls_v = item->spec;
5964 uint32_t *out_mpls_m = 0;
5965 uint32_t *out_mpls_v = 0;
5966 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5967 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5968 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5970 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5971 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5972 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5974 switch (prev_layer) {
5975 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5976 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5977 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5978 MLX5_UDP_PORT_MPLS);
5980 case MLX5_FLOW_LAYER_GRE:
5981 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5982 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5983 RTE_ETHER_TYPE_MPLS);
5986 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5987 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5994 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5995 switch (prev_layer) {
5996 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5998 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5999 outer_first_mpls_over_udp);
6001 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6002 outer_first_mpls_over_udp);
6004 case MLX5_FLOW_LAYER_GRE:
6006 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6007 outer_first_mpls_over_gre);
6009 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6010 outer_first_mpls_over_gre);
6013 /* Inner MPLS not over GRE is not supported. */
6016 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6020 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6026 if (out_mpls_m && out_mpls_v) {
6027 *out_mpls_m = *in_mpls_m;
6028 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6033 * Add metadata register item to matcher
6035 * @param[in, out] matcher
6037 * @param[in, out] key
6038 * Flow matcher value.
6039 * @param[in] reg_type
6040 * Type of device metadata register
6047 flow_dv_match_meta_reg(void *matcher, void *key,
6048 enum modify_reg reg_type,
6049 uint32_t data, uint32_t mask)
6052 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6054 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6060 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6061 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6064 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6065 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6069 * The metadata register C0 field might be divided into
6070 * source vport index and META item value, we should set
6071 * this field according to specified mask, not as whole one.
6073 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6075 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6076 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6079 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6082 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6083 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6086 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6087 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6090 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6091 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6094 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6095 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6098 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6099 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6102 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6103 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6106 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6107 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6116 * Add MARK item to matcher
6119 * The device to configure through.
6120 * @param[in, out] matcher
6122 * @param[in, out] key
6123 * Flow matcher value.
6125 * Flow pattern to translate.
6128 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6129 void *matcher, void *key,
6130 const struct rte_flow_item *item)
6132 struct mlx5_priv *priv = dev->data->dev_private;
6133 const struct rte_flow_item_mark *mark;
6137 mark = item->mask ? (const void *)item->mask :
6138 &rte_flow_item_mark_mask;
6139 mask = mark->id & priv->sh->dv_mark_mask;
6140 mark = (const void *)item->spec;
6142 value = mark->id & priv->sh->dv_mark_mask & mask;
6144 enum modify_reg reg;
6146 /* Get the metadata register index for the mark. */
6147 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6148 MLX5_ASSERT(reg > 0);
6149 if (reg == REG_C_0) {
6150 struct mlx5_priv *priv = dev->data->dev_private;
6151 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6152 uint32_t shl_c0 = rte_bsf32(msk_c0);
6158 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6163 * Add META item to matcher
6166 * The devich to configure through.
6167 * @param[in, out] matcher
6169 * @param[in, out] key
6170 * Flow matcher value.
6172 * Attributes of flow that includes this item.
6174 * Flow pattern to translate.
6177 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6178 void *matcher, void *key,
6179 const struct rte_flow_attr *attr,
6180 const struct rte_flow_item *item)
6182 const struct rte_flow_item_meta *meta_m;
6183 const struct rte_flow_item_meta *meta_v;
6185 meta_m = (const void *)item->mask;
6187 meta_m = &rte_flow_item_meta_mask;
6188 meta_v = (const void *)item->spec;
6191 uint32_t value = meta_v->data;
6192 uint32_t mask = meta_m->data;
6194 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6198 * In datapath code there is no endianness
6199 * coversions for perfromance reasons, all
6200 * pattern conversions are done in rte_flow.
6202 value = rte_cpu_to_be_32(value);
6203 mask = rte_cpu_to_be_32(mask);
6204 if (reg == REG_C_0) {
6205 struct mlx5_priv *priv = dev->data->dev_private;
6206 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6207 uint32_t shl_c0 = rte_bsf32(msk_c0);
6208 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6209 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6216 MLX5_ASSERT(msk_c0);
6217 MLX5_ASSERT(!(~msk_c0 & mask));
6219 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6224 * Add vport metadata Reg C0 item to matcher
6226 * @param[in, out] matcher
6228 * @param[in, out] key
6229 * Flow matcher value.
6231 * Flow pattern to translate.
6234 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6235 uint32_t value, uint32_t mask)
6237 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6241 * Add tag item to matcher
6244 * The devich to configure through.
6245 * @param[in, out] matcher
6247 * @param[in, out] key
6248 * Flow matcher value.
6250 * Flow pattern to translate.
6253 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6254 void *matcher, void *key,
6255 const struct rte_flow_item *item)
6257 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6258 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6259 uint32_t mask, value;
6262 value = tag_v->data;
6263 mask = tag_m ? tag_m->data : UINT32_MAX;
6264 if (tag_v->id == REG_C_0) {
6265 struct mlx5_priv *priv = dev->data->dev_private;
6266 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6267 uint32_t shl_c0 = rte_bsf32(msk_c0);
6273 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6277 * Add TAG item to matcher
6280 * The devich to configure through.
6281 * @param[in, out] matcher
6283 * @param[in, out] key
6284 * Flow matcher value.
6286 * Flow pattern to translate.
6289 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6290 void *matcher, void *key,
6291 const struct rte_flow_item *item)
6293 const struct rte_flow_item_tag *tag_v = item->spec;
6294 const struct rte_flow_item_tag *tag_m = item->mask;
6295 enum modify_reg reg;
6298 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6299 /* Get the metadata register index for the tag. */
6300 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6301 MLX5_ASSERT(reg > 0);
6302 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6306 * Add source vport match to the specified matcher.
6308 * @param[in, out] matcher
6310 * @param[in, out] key
6311 * Flow matcher value.
6313 * Source vport value to match
6318 flow_dv_translate_item_source_vport(void *matcher, void *key,
6319 int16_t port, uint16_t mask)
6321 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6322 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6324 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6325 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6329 * Translate port-id item to eswitch match on port-id.
6332 * The devich to configure through.
6333 * @param[in, out] matcher
6335 * @param[in, out] key
6336 * Flow matcher value.
6338 * Flow pattern to translate.
6341 * 0 on success, a negative errno value otherwise.
6344 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6345 void *key, const struct rte_flow_item *item)
6347 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6348 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6349 struct mlx5_priv *priv;
6352 mask = pid_m ? pid_m->id : 0xffff;
6353 id = pid_v ? pid_v->id : dev->data->port_id;
6354 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6357 /* Translate to vport field or to metadata, depending on mode. */
6358 if (priv->vport_meta_mask)
6359 flow_dv_translate_item_meta_vport(matcher, key,
6360 priv->vport_meta_tag,
6361 priv->vport_meta_mask);
6363 flow_dv_translate_item_source_vport(matcher, key,
6364 priv->vport_id, mask);
6369 * Add ICMP6 item to matcher and to the value.
6371 * @param[in, out] matcher
6373 * @param[in, out] key
6374 * Flow matcher value.
6376 * Flow pattern to translate.
6378 * Item is inner pattern.
6381 flow_dv_translate_item_icmp6(void *matcher, void *key,
6382 const struct rte_flow_item *item,
6385 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6386 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6389 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6391 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6393 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6395 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6397 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6399 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6401 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6402 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6406 icmp6_m = &rte_flow_item_icmp6_mask;
6408 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6409 * If only the protocol is specified, no need to match the frag.
6411 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6412 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6413 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6414 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6415 icmp6_v->type & icmp6_m->type);
6416 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6417 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6418 icmp6_v->code & icmp6_m->code);
6422 * Add ICMP item to matcher and to the value.
6424 * @param[in, out] matcher
6426 * @param[in, out] key
6427 * Flow matcher value.
6429 * Flow pattern to translate.
6431 * Item is inner pattern.
6434 flow_dv_translate_item_icmp(void *matcher, void *key,
6435 const struct rte_flow_item *item,
6438 const struct rte_flow_item_icmp *icmp_m = item->mask;
6439 const struct rte_flow_item_icmp *icmp_v = item->spec;
6442 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6444 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6446 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6448 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6450 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6452 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6454 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6455 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6459 icmp_m = &rte_flow_item_icmp_mask;
6461 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6462 * If only the protocol is specified, no need to match the frag.
6464 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6465 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6466 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6467 icmp_m->hdr.icmp_type);
6468 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6469 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6470 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6471 icmp_m->hdr.icmp_code);
6472 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6473 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6477 * Add GTP item to matcher and to the value.
6479 * @param[in, out] matcher
6481 * @param[in, out] key
6482 * Flow matcher value.
6484 * Flow pattern to translate.
6486 * Item is inner pattern.
6489 flow_dv_translate_item_gtp(void *matcher, void *key,
6490 const struct rte_flow_item *item, int inner)
6492 const struct rte_flow_item_gtp *gtp_m = item->mask;
6493 const struct rte_flow_item_gtp *gtp_v = item->spec;
6496 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6498 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6499 uint16_t dport = RTE_GTPU_UDP_PORT;
6502 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6504 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6506 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6508 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6510 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6511 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6512 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6517 gtp_m = &rte_flow_item_gtp_mask;
6518 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6519 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6520 gtp_v->msg_type & gtp_m->msg_type);
6521 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6522 rte_be_to_cpu_32(gtp_m->teid));
6523 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6524 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6527 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6529 #define HEADER_IS_ZERO(match_criteria, headers) \
6530 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6531 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6534 * Calculate flow matcher enable bitmap.
6536 * @param match_criteria
6537 * Pointer to flow matcher criteria.
6540 * Bitmap of enabled fields.
6543 flow_dv_matcher_enable(uint32_t *match_criteria)
6545 uint8_t match_criteria_enable;
6547 match_criteria_enable =
6548 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6549 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6550 match_criteria_enable |=
6551 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6552 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6553 match_criteria_enable |=
6554 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6555 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6556 match_criteria_enable |=
6557 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6558 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6559 match_criteria_enable |=
6560 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6561 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6562 return match_criteria_enable;
6569 * @param[in, out] dev
6570 * Pointer to rte_eth_dev structure.
6571 * @param[in] table_id
6574 * Direction of the table.
6575 * @param[in] transfer
6576 * E-Switch or NIC flow.
6578 * pointer to error structure.
6581 * Returns tables resource based on the index, NULL in case of failed.
6583 static struct mlx5_flow_tbl_resource *
6584 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6585 uint32_t table_id, uint8_t egress,
6587 struct rte_flow_error *error)
6589 struct mlx5_priv *priv = dev->data->dev_private;
6590 struct mlx5_ibv_shared *sh = priv->sh;
6591 struct mlx5_flow_tbl_resource *tbl;
6592 union mlx5_flow_tbl_key table_key = {
6594 .table_id = table_id,
6596 .domain = !!transfer,
6597 .direction = !!egress,
6600 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6602 struct mlx5_flow_tbl_data_entry *tbl_data;
6607 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6609 tbl = &tbl_data->tbl;
6610 rte_atomic32_inc(&tbl->refcnt);
6613 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6615 rte_flow_error_set(error, ENOMEM,
6616 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6618 "cannot allocate flow table data entry");
6621 tbl = &tbl_data->tbl;
6622 pos = &tbl_data->entry;
6624 domain = sh->fdb_domain;
6626 domain = sh->tx_domain;
6628 domain = sh->rx_domain;
6629 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6631 rte_flow_error_set(error, ENOMEM,
6632 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6633 NULL, "cannot create flow table object");
6638 * No multi-threads now, but still better to initialize the reference
6639 * count before insert it into the hash list.
6641 rte_atomic32_init(&tbl->refcnt);
6642 /* Jump action reference count is initialized here. */
6643 rte_atomic32_init(&tbl_data->jump.refcnt);
6644 pos->key = table_key.v64;
6645 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6647 rte_flow_error_set(error, -ret,
6648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6649 "cannot insert flow table data entry");
6650 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6653 rte_atomic32_inc(&tbl->refcnt);
6658 * Release a flow table.
6661 * Pointer to rte_eth_dev structure.
6663 * Table resource to be released.
6666 * Returns 0 if table was released, else return 1;
6669 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6670 struct mlx5_flow_tbl_resource *tbl)
6672 struct mlx5_priv *priv = dev->data->dev_private;
6673 struct mlx5_ibv_shared *sh = priv->sh;
6674 struct mlx5_flow_tbl_data_entry *tbl_data =
6675 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6679 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6680 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6682 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6684 /* remove the entry from the hash list and free memory. */
6685 mlx5_hlist_remove(sh->flow_tbls, pos);
6693 * Register the flow matcher.
6695 * @param[in, out] dev
6696 * Pointer to rte_eth_dev structure.
6697 * @param[in, out] matcher
6698 * Pointer to flow matcher.
6699 * @param[in, out] key
6700 * Pointer to flow table key.
6701 * @parm[in, out] dev_flow
6702 * Pointer to the dev_flow.
6704 * pointer to error structure.
6707 * 0 on success otherwise -errno and errno is set.
6710 flow_dv_matcher_register(struct rte_eth_dev *dev,
6711 struct mlx5_flow_dv_matcher *matcher,
6712 union mlx5_flow_tbl_key *key,
6713 struct mlx5_flow *dev_flow,
6714 struct rte_flow_error *error)
6716 struct mlx5_priv *priv = dev->data->dev_private;
6717 struct mlx5_ibv_shared *sh = priv->sh;
6718 struct mlx5_flow_dv_matcher *cache_matcher;
6719 struct mlx5dv_flow_matcher_attr dv_attr = {
6720 .type = IBV_FLOW_ATTR_NORMAL,
6721 .match_mask = (void *)&matcher->mask,
6723 struct mlx5_flow_tbl_resource *tbl;
6724 struct mlx5_flow_tbl_data_entry *tbl_data;
6726 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6727 key->domain, error);
6729 return -rte_errno; /* No need to refill the error info */
6730 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6731 /* Lookup from cache. */
6732 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6733 if (matcher->crc == cache_matcher->crc &&
6734 matcher->priority == cache_matcher->priority &&
6735 !memcmp((const void *)matcher->mask.buf,
6736 (const void *)cache_matcher->mask.buf,
6737 cache_matcher->mask.size)) {
6739 "%s group %u priority %hd use %s "
6740 "matcher %p: refcnt %d++",
6741 key->domain ? "FDB" : "NIC", key->table_id,
6742 cache_matcher->priority,
6743 key->direction ? "tx" : "rx",
6744 (void *)cache_matcher,
6745 rte_atomic32_read(&cache_matcher->refcnt));
6746 rte_atomic32_inc(&cache_matcher->refcnt);
6747 dev_flow->dv.matcher = cache_matcher;
6748 /* old matcher should not make the table ref++. */
6749 flow_dv_tbl_resource_release(dev, tbl);
6753 /* Register new matcher. */
6754 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6755 if (!cache_matcher) {
6756 flow_dv_tbl_resource_release(dev, tbl);
6757 return rte_flow_error_set(error, ENOMEM,
6758 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6759 "cannot allocate matcher memory");
6761 *cache_matcher = *matcher;
6762 dv_attr.match_criteria_enable =
6763 flow_dv_matcher_enable(cache_matcher->mask.buf);
6764 dv_attr.priority = matcher->priority;
6766 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6767 cache_matcher->matcher_object =
6768 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6769 if (!cache_matcher->matcher_object) {
6770 rte_free(cache_matcher);
6771 #ifdef HAVE_MLX5DV_DR
6772 flow_dv_tbl_resource_release(dev, tbl);
6774 return rte_flow_error_set(error, ENOMEM,
6775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6776 NULL, "cannot create matcher");
6778 /* Save the table information */
6779 cache_matcher->tbl = tbl;
6780 rte_atomic32_init(&cache_matcher->refcnt);
6781 /* only matcher ref++, table ref++ already done above in get API. */
6782 rte_atomic32_inc(&cache_matcher->refcnt);
6783 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6784 dev_flow->dv.matcher = cache_matcher;
6785 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6786 key->domain ? "FDB" : "NIC", key->table_id,
6787 cache_matcher->priority,
6788 key->direction ? "tx" : "rx", (void *)cache_matcher,
6789 rte_atomic32_read(&cache_matcher->refcnt));
6794 * Find existing tag resource or create and register a new one.
6796 * @param dev[in, out]
6797 * Pointer to rte_eth_dev structure.
6798 * @param[in, out] tag_be24
6799 * Tag value in big endian then R-shift 8.
6800 * @parm[in, out] dev_flow
6801 * Pointer to the dev_flow.
6803 * pointer to error structure.
6806 * 0 on success otherwise -errno and errno is set.
6809 flow_dv_tag_resource_register
6810 (struct rte_eth_dev *dev,
6812 struct mlx5_flow *dev_flow,
6813 struct rte_flow_error *error)
6815 struct mlx5_priv *priv = dev->data->dev_private;
6816 struct mlx5_ibv_shared *sh = priv->sh;
6817 struct mlx5_flow_dv_tag_resource *cache_resource;
6818 struct mlx5_hlist_entry *entry;
6820 /* Lookup a matching resource from cache. */
6821 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6823 cache_resource = container_of
6824 (entry, struct mlx5_flow_dv_tag_resource, entry);
6825 rte_atomic32_inc(&cache_resource->refcnt);
6826 dev_flow->dv.tag_resource = cache_resource;
6827 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6828 (void *)cache_resource,
6829 rte_atomic32_read(&cache_resource->refcnt));
6832 /* Register new resource. */
6833 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6834 if (!cache_resource)
6835 return rte_flow_error_set(error, ENOMEM,
6836 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6837 "cannot allocate resource memory");
6838 cache_resource->entry.key = (uint64_t)tag_be24;
6839 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6840 if (!cache_resource->action) {
6841 rte_free(cache_resource);
6842 return rte_flow_error_set(error, ENOMEM,
6843 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6844 NULL, "cannot create action");
6846 rte_atomic32_init(&cache_resource->refcnt);
6847 rte_atomic32_inc(&cache_resource->refcnt);
6848 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6849 mlx5_glue->destroy_flow_action(cache_resource->action);
6850 rte_free(cache_resource);
6851 return rte_flow_error_set(error, EEXIST,
6852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6853 NULL, "cannot insert tag");
6855 dev_flow->dv.tag_resource = cache_resource;
6856 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6857 (void *)cache_resource,
6858 rte_atomic32_read(&cache_resource->refcnt));
6866 * Pointer to Ethernet device.
6868 * Pointer to mlx5_flow.
6871 * 1 while a reference on it exists, 0 when freed.
6874 flow_dv_tag_release(struct rte_eth_dev *dev,
6875 struct mlx5_flow_dv_tag_resource *tag)
6877 struct mlx5_priv *priv = dev->data->dev_private;
6878 struct mlx5_ibv_shared *sh = priv->sh;
6881 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6882 dev->data->port_id, (void *)tag,
6883 rte_atomic32_read(&tag->refcnt));
6884 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6885 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6886 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6887 DRV_LOG(DEBUG, "port %u tag %p: removed",
6888 dev->data->port_id, (void *)tag);
6896 * Translate port ID action to vport.
6899 * Pointer to rte_eth_dev structure.
6901 * Pointer to the port ID action.
6902 * @param[out] dst_port_id
6903 * The target port ID.
6905 * Pointer to the error structure.
6908 * 0 on success, a negative errno value otherwise and rte_errno is set.
6911 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6912 const struct rte_flow_action *action,
6913 uint32_t *dst_port_id,
6914 struct rte_flow_error *error)
6917 struct mlx5_priv *priv;
6918 const struct rte_flow_action_port_id *conf =
6919 (const struct rte_flow_action_port_id *)action->conf;
6921 port = conf->original ? dev->data->port_id : conf->id;
6922 priv = mlx5_port_to_eswitch_info(port, false);
6924 return rte_flow_error_set(error, -rte_errno,
6925 RTE_FLOW_ERROR_TYPE_ACTION,
6927 "No eswitch info was found for port");
6928 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6930 * This parameter is transferred to
6931 * mlx5dv_dr_action_create_dest_ib_port().
6933 *dst_port_id = priv->ibv_port;
6936 * Legacy mode, no LAG configurations is supported.
6937 * This parameter is transferred to
6938 * mlx5dv_dr_action_create_dest_vport().
6940 *dst_port_id = priv->vport_id;
6946 * Add Tx queue matcher
6949 * Pointer to the dev struct.
6950 * @param[in, out] matcher
6952 * @param[in, out] key
6953 * Flow matcher value.
6955 * Flow pattern to translate.
6957 * Item is inner pattern.
6960 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6961 void *matcher, void *key,
6962 const struct rte_flow_item *item)
6964 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6965 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6967 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6969 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6970 struct mlx5_txq_ctrl *txq;
6974 queue_m = (const void *)item->mask;
6977 queue_v = (const void *)item->spec;
6980 txq = mlx5_txq_get(dev, queue_v->queue);
6983 queue = txq->obj->sq->id;
6984 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6985 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6986 queue & queue_m->queue);
6987 mlx5_txq_release(dev, queue_v->queue);
6991 * Set the hash fields according to the @p flow information.
6993 * @param[in] dev_flow
6994 * Pointer to the mlx5_flow.
6997 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
6999 struct rte_flow *flow = dev_flow->flow;
7000 uint64_t items = dev_flow->layers;
7002 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7004 dev_flow->hash_fields = 0;
7005 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7006 if (flow->rss.level >= 2) {
7007 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7011 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7012 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7013 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7014 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7015 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7016 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7017 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7019 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7021 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7022 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7023 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7024 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7025 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7026 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7027 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7029 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7032 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7033 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7034 if (rss_types & ETH_RSS_UDP) {
7035 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7036 dev_flow->hash_fields |=
7037 IBV_RX_HASH_SRC_PORT_UDP;
7038 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7039 dev_flow->hash_fields |=
7040 IBV_RX_HASH_DST_PORT_UDP;
7042 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7044 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7045 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7046 if (rss_types & ETH_RSS_TCP) {
7047 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7048 dev_flow->hash_fields |=
7049 IBV_RX_HASH_SRC_PORT_TCP;
7050 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7051 dev_flow->hash_fields |=
7052 IBV_RX_HASH_DST_PORT_TCP;
7054 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7060 * Fill the flow with DV spec, lock free
7061 * (mutex should be acquired by caller).
7064 * Pointer to rte_eth_dev structure.
7065 * @param[in, out] dev_flow
7066 * Pointer to the sub flow.
7068 * Pointer to the flow attributes.
7070 * Pointer to the list of items.
7071 * @param[in] actions
7072 * Pointer to the list of actions.
7074 * Pointer to the error structure.
7077 * 0 on success, a negative errno value otherwise and rte_errno is set.
7080 __flow_dv_translate(struct rte_eth_dev *dev,
7081 struct mlx5_flow *dev_flow,
7082 const struct rte_flow_attr *attr,
7083 const struct rte_flow_item items[],
7084 const struct rte_flow_action actions[],
7085 struct rte_flow_error *error)
7087 struct mlx5_priv *priv = dev->data->dev_private;
7088 struct mlx5_dev_config *dev_conf = &priv->config;
7089 struct rte_flow *flow = dev_flow->flow;
7090 uint64_t item_flags = 0;
7091 uint64_t last_item = 0;
7092 uint64_t action_flags = 0;
7093 uint64_t priority = attr->priority;
7094 struct mlx5_flow_dv_matcher matcher = {
7096 .size = sizeof(matcher.mask.buf),
7100 bool actions_end = false;
7102 struct mlx5_flow_dv_modify_hdr_resource res;
7103 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7104 sizeof(struct mlx5_modification_cmd) *
7105 (MLX5_MAX_MODIFY_NUM + 1)];
7107 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7108 union flow_dv_attr flow_attr = { .attr = 0 };
7110 union mlx5_flow_tbl_key tbl_key;
7111 uint32_t modify_action_position = UINT32_MAX;
7112 void *match_mask = matcher.mask.buf;
7113 void *match_value = dev_flow->dv.value.buf;
7114 uint8_t next_protocol = 0xff;
7115 struct rte_vlan_hdr vlan = { 0 };
7119 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7120 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7121 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7122 !!priv->fdb_def_rule, &table, error);
7125 dev_flow->group = table;
7127 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7128 if (priority == MLX5_FLOW_PRIO_RSVD)
7129 priority = dev_conf->flow_prio - 1;
7130 /* number of actions must be set to 0 in case of dirty stack. */
7131 mhdr_res->actions_num = 0;
7132 for (; !actions_end ; actions++) {
7133 const struct rte_flow_action_queue *queue;
7134 const struct rte_flow_action_rss *rss;
7135 const struct rte_flow_action *action = actions;
7136 const struct rte_flow_action_count *count = action->conf;
7137 const uint8_t *rss_key;
7138 const struct rte_flow_action_jump *jump_data;
7139 const struct rte_flow_action_meter *mtr;
7140 struct mlx5_flow_tbl_resource *tbl;
7141 uint32_t port_id = 0;
7142 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7143 int action_type = actions->type;
7144 const struct rte_flow_action *found_action = NULL;
7146 switch (action_type) {
7147 case RTE_FLOW_ACTION_TYPE_VOID:
7149 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7150 if (flow_dv_translate_action_port_id(dev, action,
7153 port_id_resource.port_id = port_id;
7154 if (flow_dv_port_id_action_resource_register
7155 (dev, &port_id_resource, dev_flow, error))
7157 dev_flow->dv.actions[actions_n++] =
7158 dev_flow->dv.port_id_action->action;
7159 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7161 case RTE_FLOW_ACTION_TYPE_FLAG:
7162 action_flags |= MLX5_FLOW_ACTION_FLAG;
7163 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7164 struct rte_flow_action_mark mark = {
7165 .id = MLX5_FLOW_MARK_DEFAULT,
7168 if (flow_dv_convert_action_mark(dev, &mark,
7172 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7175 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7176 if (!dev_flow->dv.tag_resource)
7177 if (flow_dv_tag_resource_register
7178 (dev, tag_be, dev_flow, error))
7180 dev_flow->dv.actions[actions_n++] =
7181 dev_flow->dv.tag_resource->action;
7183 case RTE_FLOW_ACTION_TYPE_MARK:
7184 action_flags |= MLX5_FLOW_ACTION_MARK;
7185 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7186 const struct rte_flow_action_mark *mark =
7187 (const struct rte_flow_action_mark *)
7190 if (flow_dv_convert_action_mark(dev, mark,
7194 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7198 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7199 /* Legacy (non-extensive) MARK action. */
7200 tag_be = mlx5_flow_mark_set
7201 (((const struct rte_flow_action_mark *)
7202 (actions->conf))->id);
7203 if (!dev_flow->dv.tag_resource)
7204 if (flow_dv_tag_resource_register
7205 (dev, tag_be, dev_flow, error))
7207 dev_flow->dv.actions[actions_n++] =
7208 dev_flow->dv.tag_resource->action;
7210 case RTE_FLOW_ACTION_TYPE_SET_META:
7211 if (flow_dv_convert_action_set_meta
7212 (dev, mhdr_res, attr,
7213 (const struct rte_flow_action_set_meta *)
7214 actions->conf, error))
7216 action_flags |= MLX5_FLOW_ACTION_SET_META;
7218 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7219 if (flow_dv_convert_action_set_tag
7221 (const struct rte_flow_action_set_tag *)
7222 actions->conf, error))
7224 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7226 case RTE_FLOW_ACTION_TYPE_DROP:
7227 action_flags |= MLX5_FLOW_ACTION_DROP;
7229 case RTE_FLOW_ACTION_TYPE_QUEUE:
7230 MLX5_ASSERT(flow->rss.queue);
7231 queue = actions->conf;
7232 flow->rss.queue_num = 1;
7233 (*flow->rss.queue)[0] = queue->index;
7234 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7236 case RTE_FLOW_ACTION_TYPE_RSS:
7237 MLX5_ASSERT(flow->rss.queue);
7238 rss = actions->conf;
7239 if (flow->rss.queue)
7240 memcpy((*flow->rss.queue), rss->queue,
7241 rss->queue_num * sizeof(uint16_t));
7242 flow->rss.queue_num = rss->queue_num;
7243 /* NULL RSS key indicates default RSS key. */
7244 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7245 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7247 * rss->level and rss.types should be set in advance
7248 * when expanding items for RSS.
7250 action_flags |= MLX5_FLOW_ACTION_RSS;
7252 case RTE_FLOW_ACTION_TYPE_COUNT:
7253 if (!dev_conf->devx) {
7254 rte_errno = ENOTSUP;
7257 flow->counter = flow_dv_counter_alloc(dev,
7261 if (flow->counter == NULL)
7263 dev_flow->dv.actions[actions_n++] =
7264 flow->counter->action;
7265 action_flags |= MLX5_FLOW_ACTION_COUNT;
7268 if (rte_errno == ENOTSUP)
7269 return rte_flow_error_set
7271 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7273 "count action not supported");
7275 return rte_flow_error_set
7277 RTE_FLOW_ERROR_TYPE_ACTION,
7279 "cannot create counter"
7282 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7283 dev_flow->dv.actions[actions_n++] =
7284 priv->sh->pop_vlan_action;
7285 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7287 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7288 flow_dev_get_vlan_info_from_items(items, &vlan);
7289 vlan.eth_proto = rte_be_to_cpu_16
7290 ((((const struct rte_flow_action_of_push_vlan *)
7291 actions->conf)->ethertype));
7292 found_action = mlx5_flow_find_action
7294 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7296 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7297 found_action = mlx5_flow_find_action
7299 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7301 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7302 if (flow_dv_create_action_push_vlan
7303 (dev, attr, &vlan, dev_flow, error))
7305 dev_flow->dv.actions[actions_n++] =
7306 dev_flow->dv.push_vlan_res->action;
7307 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7309 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7310 /* of_vlan_push action handled this action */
7311 MLX5_ASSERT(action_flags &
7312 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7314 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7315 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7317 flow_dev_get_vlan_info_from_items(items, &vlan);
7318 mlx5_update_vlan_vid_pcp(actions, &vlan);
7319 /* If no VLAN push - this is a modify header action */
7320 if (flow_dv_convert_action_modify_vlan_vid
7321 (mhdr_res, actions, error))
7323 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7325 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7326 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7327 if (flow_dv_create_action_l2_encap(dev, actions,
7332 dev_flow->dv.actions[actions_n++] =
7333 dev_flow->dv.encap_decap->verbs_action;
7334 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7336 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7337 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7338 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7342 dev_flow->dv.actions[actions_n++] =
7343 dev_flow->dv.encap_decap->verbs_action;
7344 action_flags |= MLX5_FLOW_ACTION_DECAP;
7346 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7347 /* Handle encap with preceding decap. */
7348 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7349 if (flow_dv_create_action_raw_encap
7350 (dev, actions, dev_flow, attr, error))
7352 dev_flow->dv.actions[actions_n++] =
7353 dev_flow->dv.encap_decap->verbs_action;
7355 /* Handle encap without preceding decap. */
7356 if (flow_dv_create_action_l2_encap
7357 (dev, actions, dev_flow, attr->transfer,
7360 dev_flow->dv.actions[actions_n++] =
7361 dev_flow->dv.encap_decap->verbs_action;
7363 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7365 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7366 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7368 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7369 if (flow_dv_create_action_l2_decap
7370 (dev, dev_flow, attr->transfer, error))
7372 dev_flow->dv.actions[actions_n++] =
7373 dev_flow->dv.encap_decap->verbs_action;
7375 /* If decap is followed by encap, handle it at encap. */
7376 action_flags |= MLX5_FLOW_ACTION_DECAP;
7378 case RTE_FLOW_ACTION_TYPE_JUMP:
7379 jump_data = action->conf;
7380 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7382 !!priv->fdb_def_rule,
7386 tbl = flow_dv_tbl_resource_get(dev, table,
7388 attr->transfer, error);
7390 return rte_flow_error_set
7392 RTE_FLOW_ERROR_TYPE_ACTION,
7394 "cannot create jump action.");
7395 if (flow_dv_jump_tbl_resource_register
7396 (dev, tbl, dev_flow, error)) {
7397 flow_dv_tbl_resource_release(dev, tbl);
7398 return rte_flow_error_set
7400 RTE_FLOW_ERROR_TYPE_ACTION,
7402 "cannot create jump action.");
7404 dev_flow->dv.actions[actions_n++] =
7405 dev_flow->dv.jump->action;
7406 action_flags |= MLX5_FLOW_ACTION_JUMP;
7408 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7409 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7410 if (flow_dv_convert_action_modify_mac
7411 (mhdr_res, actions, error))
7413 action_flags |= actions->type ==
7414 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7415 MLX5_FLOW_ACTION_SET_MAC_SRC :
7416 MLX5_FLOW_ACTION_SET_MAC_DST;
7418 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7419 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7420 if (flow_dv_convert_action_modify_ipv4
7421 (mhdr_res, actions, error))
7423 action_flags |= actions->type ==
7424 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7425 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7426 MLX5_FLOW_ACTION_SET_IPV4_DST;
7428 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7429 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7430 if (flow_dv_convert_action_modify_ipv6
7431 (mhdr_res, actions, error))
7433 action_flags |= actions->type ==
7434 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7435 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7436 MLX5_FLOW_ACTION_SET_IPV6_DST;
7438 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7439 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7440 if (flow_dv_convert_action_modify_tp
7441 (mhdr_res, actions, items,
7444 action_flags |= actions->type ==
7445 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7446 MLX5_FLOW_ACTION_SET_TP_SRC :
7447 MLX5_FLOW_ACTION_SET_TP_DST;
7449 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7450 if (flow_dv_convert_action_modify_dec_ttl
7451 (mhdr_res, items, &flow_attr, error))
7453 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7455 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7456 if (flow_dv_convert_action_modify_ttl
7457 (mhdr_res, actions, items,
7460 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7462 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7463 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7464 if (flow_dv_convert_action_modify_tcp_seq
7465 (mhdr_res, actions, error))
7467 action_flags |= actions->type ==
7468 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7469 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7470 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7473 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7474 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7475 if (flow_dv_convert_action_modify_tcp_ack
7476 (mhdr_res, actions, error))
7478 action_flags |= actions->type ==
7479 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7480 MLX5_FLOW_ACTION_INC_TCP_ACK :
7481 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7483 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7484 if (flow_dv_convert_action_set_reg
7485 (mhdr_res, actions, error))
7487 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7489 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7490 if (flow_dv_convert_action_copy_mreg
7491 (dev, mhdr_res, actions, error))
7493 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7495 case RTE_FLOW_ACTION_TYPE_METER:
7496 mtr = actions->conf;
7498 flow->meter = mlx5_flow_meter_attach(priv,
7502 return rte_flow_error_set(error,
7504 RTE_FLOW_ERROR_TYPE_ACTION,
7507 "or invalid parameters");
7509 /* Set the meter action. */
7510 dev_flow->dv.actions[actions_n++] =
7511 flow->meter->mfts->meter_action;
7512 action_flags |= MLX5_FLOW_ACTION_METER;
7514 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7515 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7518 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7520 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7521 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7524 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7526 case RTE_FLOW_ACTION_TYPE_END:
7528 if (mhdr_res->actions_num) {
7529 /* create modify action if needed. */
7530 if (flow_dv_modify_hdr_resource_register
7531 (dev, mhdr_res, dev_flow, error))
7533 dev_flow->dv.actions[modify_action_position] =
7534 dev_flow->dv.modify_hdr->verbs_action;
7540 if (mhdr_res->actions_num &&
7541 modify_action_position == UINT32_MAX)
7542 modify_action_position = actions_n++;
7544 dev_flow->dv.actions_n = actions_n;
7545 dev_flow->actions = action_flags;
7546 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7547 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7548 int item_type = items->type;
7550 switch (item_type) {
7551 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7552 flow_dv_translate_item_port_id(dev, match_mask,
7553 match_value, items);
7554 last_item = MLX5_FLOW_ITEM_PORT_ID;
7556 case RTE_FLOW_ITEM_TYPE_ETH:
7557 flow_dv_translate_item_eth(match_mask, match_value,
7559 matcher.priority = MLX5_PRIORITY_MAP_L2;
7560 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7561 MLX5_FLOW_LAYER_OUTER_L2;
7563 case RTE_FLOW_ITEM_TYPE_VLAN:
7564 flow_dv_translate_item_vlan(dev_flow,
7565 match_mask, match_value,
7567 matcher.priority = MLX5_PRIORITY_MAP_L2;
7568 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7569 MLX5_FLOW_LAYER_INNER_VLAN) :
7570 (MLX5_FLOW_LAYER_OUTER_L2 |
7571 MLX5_FLOW_LAYER_OUTER_VLAN);
7573 case RTE_FLOW_ITEM_TYPE_IPV4:
7574 mlx5_flow_tunnel_ip_check(items, next_protocol,
7575 &item_flags, &tunnel);
7576 flow_dv_translate_item_ipv4(match_mask, match_value,
7579 matcher.priority = MLX5_PRIORITY_MAP_L3;
7580 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7581 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7582 if (items->mask != NULL &&
7583 ((const struct rte_flow_item_ipv4 *)
7584 items->mask)->hdr.next_proto_id) {
7586 ((const struct rte_flow_item_ipv4 *)
7587 (items->spec))->hdr.next_proto_id;
7589 ((const struct rte_flow_item_ipv4 *)
7590 (items->mask))->hdr.next_proto_id;
7592 /* Reset for inner layer. */
7593 next_protocol = 0xff;
7596 case RTE_FLOW_ITEM_TYPE_IPV6:
7597 mlx5_flow_tunnel_ip_check(items, next_protocol,
7598 &item_flags, &tunnel);
7599 flow_dv_translate_item_ipv6(match_mask, match_value,
7602 matcher.priority = MLX5_PRIORITY_MAP_L3;
7603 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7604 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7605 if (items->mask != NULL &&
7606 ((const struct rte_flow_item_ipv6 *)
7607 items->mask)->hdr.proto) {
7609 ((const struct rte_flow_item_ipv6 *)
7610 items->spec)->hdr.proto;
7612 ((const struct rte_flow_item_ipv6 *)
7613 items->mask)->hdr.proto;
7615 /* Reset for inner layer. */
7616 next_protocol = 0xff;
7619 case RTE_FLOW_ITEM_TYPE_TCP:
7620 flow_dv_translate_item_tcp(match_mask, match_value,
7622 matcher.priority = MLX5_PRIORITY_MAP_L4;
7623 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7624 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7626 case RTE_FLOW_ITEM_TYPE_UDP:
7627 flow_dv_translate_item_udp(match_mask, match_value,
7629 matcher.priority = MLX5_PRIORITY_MAP_L4;
7630 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7631 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7633 case RTE_FLOW_ITEM_TYPE_GRE:
7634 flow_dv_translate_item_gre(match_mask, match_value,
7636 matcher.priority = flow->rss.level >= 2 ?
7637 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7638 last_item = MLX5_FLOW_LAYER_GRE;
7640 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7641 flow_dv_translate_item_gre_key(match_mask,
7642 match_value, items);
7643 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7645 case RTE_FLOW_ITEM_TYPE_NVGRE:
7646 flow_dv_translate_item_nvgre(match_mask, match_value,
7648 matcher.priority = flow->rss.level >= 2 ?
7649 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7650 last_item = MLX5_FLOW_LAYER_GRE;
7652 case RTE_FLOW_ITEM_TYPE_VXLAN:
7653 flow_dv_translate_item_vxlan(match_mask, match_value,
7655 matcher.priority = flow->rss.level >= 2 ?
7656 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7657 last_item = MLX5_FLOW_LAYER_VXLAN;
7659 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7660 flow_dv_translate_item_vxlan_gpe(match_mask,
7663 matcher.priority = flow->rss.level >= 2 ?
7664 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7665 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7667 case RTE_FLOW_ITEM_TYPE_GENEVE:
7668 flow_dv_translate_item_geneve(match_mask, match_value,
7670 matcher.priority = flow->rss.level >= 2 ?
7671 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7672 last_item = MLX5_FLOW_LAYER_GENEVE;
7674 case RTE_FLOW_ITEM_TYPE_MPLS:
7675 flow_dv_translate_item_mpls(match_mask, match_value,
7676 items, last_item, tunnel);
7677 matcher.priority = flow->rss.level >= 2 ?
7678 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7679 last_item = MLX5_FLOW_LAYER_MPLS;
7681 case RTE_FLOW_ITEM_TYPE_MARK:
7682 flow_dv_translate_item_mark(dev, match_mask,
7683 match_value, items);
7684 last_item = MLX5_FLOW_ITEM_MARK;
7686 case RTE_FLOW_ITEM_TYPE_META:
7687 flow_dv_translate_item_meta(dev, match_mask,
7688 match_value, attr, items);
7689 last_item = MLX5_FLOW_ITEM_METADATA;
7691 case RTE_FLOW_ITEM_TYPE_ICMP:
7692 flow_dv_translate_item_icmp(match_mask, match_value,
7694 last_item = MLX5_FLOW_LAYER_ICMP;
7696 case RTE_FLOW_ITEM_TYPE_ICMP6:
7697 flow_dv_translate_item_icmp6(match_mask, match_value,
7699 last_item = MLX5_FLOW_LAYER_ICMP6;
7701 case RTE_FLOW_ITEM_TYPE_TAG:
7702 flow_dv_translate_item_tag(dev, match_mask,
7703 match_value, items);
7704 last_item = MLX5_FLOW_ITEM_TAG;
7706 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7707 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7708 match_value, items);
7709 last_item = MLX5_FLOW_ITEM_TAG;
7711 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7712 flow_dv_translate_item_tx_queue(dev, match_mask,
7715 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7717 case RTE_FLOW_ITEM_TYPE_GTP:
7718 flow_dv_translate_item_gtp(match_mask, match_value,
7720 matcher.priority = flow->rss.level >= 2 ?
7721 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7722 last_item = MLX5_FLOW_LAYER_GTP;
7727 item_flags |= last_item;
7730 * When E-Switch mode is enabled, we have two cases where we need to
7731 * set the source port manually.
7732 * The first one, is in case of Nic steering rule, and the second is
7733 * E-Switch rule where no port_id item was found. In both cases
7734 * the source port is set according the current port in use.
7736 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7737 (priv->representor || priv->master)) {
7738 if (flow_dv_translate_item_port_id(dev, match_mask,
7742 #ifdef RTE_LIBRTE_MLX5_DEBUG
7743 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7744 dev_flow->dv.value.buf));
7746 dev_flow->layers = item_flags;
7747 if (action_flags & MLX5_FLOW_ACTION_RSS)
7748 flow_dv_hashfields_set(dev_flow);
7749 /* Register matcher. */
7750 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7752 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7754 /* reserved field no needs to be set to 0 here. */
7755 tbl_key.domain = attr->transfer;
7756 tbl_key.direction = attr->egress;
7757 tbl_key.table_id = dev_flow->group;
7758 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7764 * Apply the flow to the NIC, lock free,
7765 * (mutex should be acquired by caller).
7768 * Pointer to the Ethernet device structure.
7769 * @param[in, out] flow
7770 * Pointer to flow structure.
7772 * Pointer to error structure.
7775 * 0 on success, a negative errno value otherwise and rte_errno is set.
7778 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7779 struct rte_flow_error *error)
7781 struct mlx5_flow_dv *dv;
7782 struct mlx5_flow *dev_flow;
7783 struct mlx5_priv *priv = dev->data->dev_private;
7787 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7790 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7791 if (dev_flow->transfer) {
7792 dv->actions[n++] = priv->sh->esw_drop_action;
7794 dv->hrxq = mlx5_hrxq_drop_new(dev);
7798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7800 "cannot get drop hash queue");
7803 dv->actions[n++] = dv->hrxq->action;
7805 } else if (dev_flow->actions &
7806 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7807 struct mlx5_hrxq *hrxq;
7809 MLX5_ASSERT(flow->rss.queue);
7810 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7811 MLX5_RSS_HASH_KEY_LEN,
7812 dev_flow->hash_fields,
7814 flow->rss.queue_num);
7816 hrxq = mlx5_hrxq_new
7817 (dev, flow->rss.key,
7818 MLX5_RSS_HASH_KEY_LEN,
7819 dev_flow->hash_fields,
7821 flow->rss.queue_num,
7822 !!(dev_flow->layers &
7823 MLX5_FLOW_LAYER_TUNNEL));
7828 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7829 "cannot get hash queue");
7833 dv->actions[n++] = dv->hrxq->action;
7836 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7837 (void *)&dv->value, n,
7840 rte_flow_error_set(error, errno,
7841 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7843 "hardware refuses to create flow");
7846 if (priv->vmwa_context &&
7847 dev_flow->dv.vf_vlan.tag &&
7848 !dev_flow->dv.vf_vlan.created) {
7850 * The rule contains the VLAN pattern.
7851 * For VF we are going to create VLAN
7852 * interface to make hypervisor set correct
7853 * e-Switch vport context.
7855 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7860 err = rte_errno; /* Save rte_errno before cleanup. */
7861 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7862 struct mlx5_flow_dv *dv = &dev_flow->dv;
7864 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7865 mlx5_hrxq_drop_release(dev);
7867 mlx5_hrxq_release(dev, dv->hrxq);
7870 if (dev_flow->dv.vf_vlan.tag &&
7871 dev_flow->dv.vf_vlan.created)
7872 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7874 rte_errno = err; /* Restore rte_errno. */
7879 * Release the flow matcher.
7882 * Pointer to Ethernet device.
7884 * Pointer to mlx5_flow.
7887 * 1 while a reference on it exists, 0 when freed.
7890 flow_dv_matcher_release(struct rte_eth_dev *dev,
7891 struct mlx5_flow *flow)
7893 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7895 MLX5_ASSERT(matcher->matcher_object);
7896 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7897 dev->data->port_id, (void *)matcher,
7898 rte_atomic32_read(&matcher->refcnt));
7899 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7900 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7901 (matcher->matcher_object));
7902 LIST_REMOVE(matcher, next);
7903 /* table ref-- in release interface. */
7904 flow_dv_tbl_resource_release(dev, matcher->tbl);
7906 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7907 dev->data->port_id, (void *)matcher);
7914 * Release an encap/decap resource.
7917 * Pointer to mlx5_flow.
7920 * 1 while a reference on it exists, 0 when freed.
7923 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7925 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7926 flow->dv.encap_decap;
7928 MLX5_ASSERT(cache_resource->verbs_action);
7929 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7930 (void *)cache_resource,
7931 rte_atomic32_read(&cache_resource->refcnt));
7932 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7933 claim_zero(mlx5_glue->destroy_flow_action
7934 (cache_resource->verbs_action));
7935 LIST_REMOVE(cache_resource, next);
7936 rte_free(cache_resource);
7937 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7938 (void *)cache_resource);
7945 * Release an jump to table action resource.
7948 * Pointer to Ethernet device.
7950 * Pointer to mlx5_flow.
7953 * 1 while a reference on it exists, 0 when freed.
7956 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7957 struct mlx5_flow *flow)
7959 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7960 struct mlx5_flow_tbl_data_entry *tbl_data =
7961 container_of(cache_resource,
7962 struct mlx5_flow_tbl_data_entry, jump);
7964 MLX5_ASSERT(cache_resource->action);
7965 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7966 (void *)cache_resource,
7967 rte_atomic32_read(&cache_resource->refcnt));
7968 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7969 claim_zero(mlx5_glue->destroy_flow_action
7970 (cache_resource->action));
7971 /* jump action memory free is inside the table release. */
7972 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7973 DRV_LOG(DEBUG, "jump table resource %p: removed",
7974 (void *)cache_resource);
7981 * Release a modify-header resource.
7984 * Pointer to mlx5_flow.
7987 * 1 while a reference on it exists, 0 when freed.
7990 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7992 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7993 flow->dv.modify_hdr;
7995 MLX5_ASSERT(cache_resource->verbs_action);
7996 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7997 (void *)cache_resource,
7998 rte_atomic32_read(&cache_resource->refcnt));
7999 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8000 claim_zero(mlx5_glue->destroy_flow_action
8001 (cache_resource->verbs_action));
8002 LIST_REMOVE(cache_resource, next);
8003 rte_free(cache_resource);
8004 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8005 (void *)cache_resource);
8012 * Release port ID action resource.
8015 * Pointer to mlx5_flow.
8018 * 1 while a reference on it exists, 0 when freed.
8021 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8023 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8024 flow->dv.port_id_action;
8026 MLX5_ASSERT(cache_resource->action);
8027 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8028 (void *)cache_resource,
8029 rte_atomic32_read(&cache_resource->refcnt));
8030 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8031 claim_zero(mlx5_glue->destroy_flow_action
8032 (cache_resource->action));
8033 LIST_REMOVE(cache_resource, next);
8034 rte_free(cache_resource);
8035 DRV_LOG(DEBUG, "port id action resource %p: removed",
8036 (void *)cache_resource);
8043 * Release push vlan action resource.
8046 * Pointer to mlx5_flow.
8049 * 1 while a reference on it exists, 0 when freed.
8052 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8054 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8055 flow->dv.push_vlan_res;
8057 MLX5_ASSERT(cache_resource->action);
8058 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8059 (void *)cache_resource,
8060 rte_atomic32_read(&cache_resource->refcnt));
8061 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8062 claim_zero(mlx5_glue->destroy_flow_action
8063 (cache_resource->action));
8064 LIST_REMOVE(cache_resource, next);
8065 rte_free(cache_resource);
8066 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8067 (void *)cache_resource);
8074 * Remove the flow from the NIC but keeps it in memory.
8075 * Lock free, (mutex should be acquired by caller).
8078 * Pointer to Ethernet device.
8079 * @param[in, out] flow
8080 * Pointer to flow structure.
8083 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8085 struct mlx5_flow_dv *dv;
8086 struct mlx5_flow *dev_flow;
8090 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8093 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8097 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8098 mlx5_hrxq_drop_release(dev);
8100 mlx5_hrxq_release(dev, dv->hrxq);
8103 if (dev_flow->dv.vf_vlan.tag &&
8104 dev_flow->dv.vf_vlan.created)
8105 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8110 * Remove the flow from the NIC and the memory.
8111 * Lock free, (mutex should be acquired by caller).
8114 * Pointer to the Ethernet device structure.
8115 * @param[in, out] flow
8116 * Pointer to flow structure.
8119 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8121 struct mlx5_flow *dev_flow;
8125 __flow_dv_remove(dev, flow);
8126 if (flow->counter) {
8127 flow_dv_counter_release(dev, flow->counter);
8128 flow->counter = NULL;
8131 mlx5_flow_meter_detach(flow->meter);
8134 while (!LIST_EMPTY(&flow->dev_flows)) {
8135 dev_flow = LIST_FIRST(&flow->dev_flows);
8136 LIST_REMOVE(dev_flow, next);
8137 if (dev_flow->dv.matcher)
8138 flow_dv_matcher_release(dev, dev_flow);
8139 if (dev_flow->dv.encap_decap)
8140 flow_dv_encap_decap_resource_release(dev_flow);
8141 if (dev_flow->dv.modify_hdr)
8142 flow_dv_modify_hdr_resource_release(dev_flow);
8143 if (dev_flow->dv.jump)
8144 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8145 if (dev_flow->dv.port_id_action)
8146 flow_dv_port_id_action_resource_release(dev_flow);
8147 if (dev_flow->dv.push_vlan_res)
8148 flow_dv_push_vlan_action_resource_release(dev_flow);
8149 if (dev_flow->dv.tag_resource)
8150 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8156 * Query a dv flow rule for its statistics via devx.
8159 * Pointer to Ethernet device.
8161 * Pointer to the sub flow.
8163 * data retrieved by the query.
8165 * Perform verbose error reporting if not NULL.
8168 * 0 on success, a negative errno value otherwise and rte_errno is set.
8171 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8172 void *data, struct rte_flow_error *error)
8174 struct mlx5_priv *priv = dev->data->dev_private;
8175 struct rte_flow_query_count *qc = data;
8177 if (!priv->config.devx)
8178 return rte_flow_error_set(error, ENOTSUP,
8179 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8181 "counters are not supported");
8182 if (flow->counter) {
8183 uint64_t pkts, bytes;
8184 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8188 return rte_flow_error_set(error, -err,
8189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8190 NULL, "cannot read counters");
8193 qc->hits = pkts - flow->counter->hits;
8194 qc->bytes = bytes - flow->counter->bytes;
8196 flow->counter->hits = pkts;
8197 flow->counter->bytes = bytes;
8201 return rte_flow_error_set(error, EINVAL,
8202 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8204 "counters are not available");
8210 * @see rte_flow_query()
8214 flow_dv_query(struct rte_eth_dev *dev,
8215 struct rte_flow *flow __rte_unused,
8216 const struct rte_flow_action *actions __rte_unused,
8217 void *data __rte_unused,
8218 struct rte_flow_error *error __rte_unused)
8222 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8223 switch (actions->type) {
8224 case RTE_FLOW_ACTION_TYPE_VOID:
8226 case RTE_FLOW_ACTION_TYPE_COUNT:
8227 ret = flow_dv_query_count(dev, flow, data, error);
8230 return rte_flow_error_set(error, ENOTSUP,
8231 RTE_FLOW_ERROR_TYPE_ACTION,
8233 "action not supported");
8240 * Destroy the meter table set.
8241 * Lock free, (mutex should be acquired by caller).
8244 * Pointer to Ethernet device.
8246 * Pointer to the meter table set.
8252 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8253 struct mlx5_meter_domains_infos *tbl)
8255 struct mlx5_priv *priv = dev->data->dev_private;
8256 struct mlx5_meter_domains_infos *mtd =
8257 (struct mlx5_meter_domains_infos *)tbl;
8259 if (!mtd || !priv->config.dv_flow_en)
8261 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8262 claim_zero(mlx5_glue->dv_destroy_flow
8263 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8264 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8265 claim_zero(mlx5_glue->dv_destroy_flow
8266 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8267 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8268 claim_zero(mlx5_glue->dv_destroy_flow
8269 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8270 if (mtd->egress.color_matcher)
8271 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8272 (mtd->egress.color_matcher));
8273 if (mtd->egress.any_matcher)
8274 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8275 (mtd->egress.any_matcher));
8276 if (mtd->egress.tbl)
8277 claim_zero(flow_dv_tbl_resource_release(dev,
8279 if (mtd->ingress.color_matcher)
8280 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8281 (mtd->ingress.color_matcher));
8282 if (mtd->ingress.any_matcher)
8283 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8284 (mtd->ingress.any_matcher));
8285 if (mtd->ingress.tbl)
8286 claim_zero(flow_dv_tbl_resource_release(dev,
8288 if (mtd->transfer.color_matcher)
8289 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8290 (mtd->transfer.color_matcher));
8291 if (mtd->transfer.any_matcher)
8292 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8293 (mtd->transfer.any_matcher));
8294 if (mtd->transfer.tbl)
8295 claim_zero(flow_dv_tbl_resource_release(dev,
8296 mtd->transfer.tbl));
8298 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8303 /* Number of meter flow actions, count and jump or count and drop. */
8304 #define METER_ACTIONS 2
8307 * Create specify domain meter table and suffix table.
8310 * Pointer to Ethernet device.
8311 * @param[in,out] mtb
8312 * Pointer to DV meter table set.
8315 * @param[in] transfer
8317 * @param[in] color_reg_c_idx
8318 * Reg C index for color match.
8321 * 0 on success, -1 otherwise and rte_errno is set.
8324 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8325 struct mlx5_meter_domains_infos *mtb,
8326 uint8_t egress, uint8_t transfer,
8327 uint32_t color_reg_c_idx)
8329 struct mlx5_priv *priv = dev->data->dev_private;
8330 struct mlx5_ibv_shared *sh = priv->sh;
8331 struct mlx5_flow_dv_match_params mask = {
8332 .size = sizeof(mask.buf),
8334 struct mlx5_flow_dv_match_params value = {
8335 .size = sizeof(value.buf),
8337 struct mlx5dv_flow_matcher_attr dv_attr = {
8338 .type = IBV_FLOW_ATTR_NORMAL,
8340 .match_criteria_enable = 0,
8341 .match_mask = (void *)&mask,
8343 void *actions[METER_ACTIONS];
8344 struct mlx5_flow_tbl_resource **sfx_tbl;
8345 struct mlx5_meter_domain_info *dtb;
8346 struct rte_flow_error error;
8350 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8351 dtb = &mtb->transfer;
8352 } else if (egress) {
8353 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8356 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8357 dtb = &mtb->ingress;
8359 /* If the suffix table in missing, create it. */
8361 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8362 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8363 egress, transfer, &error);
8365 DRV_LOG(ERR, "Failed to create meter suffix table.");
8369 /* Create the meter table with METER level. */
8370 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8371 egress, transfer, &error);
8373 DRV_LOG(ERR, "Failed to create meter policer table.");
8376 /* Create matchers, Any and Color. */
8377 dv_attr.priority = 3;
8378 dv_attr.match_criteria_enable = 0;
8379 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8382 if (!dtb->any_matcher) {
8383 DRV_LOG(ERR, "Failed to create meter"
8384 " policer default matcher.");
8387 dv_attr.priority = 0;
8388 dv_attr.match_criteria_enable =
8389 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8390 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8391 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8392 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8395 if (!dtb->color_matcher) {
8396 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8399 if (mtb->count_actns[RTE_MTR_DROPPED])
8400 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8401 actions[i++] = mtb->drop_actn;
8402 /* Default rule: lowest priority, match any, actions: drop. */
8403 dtb->policer_rules[RTE_MTR_DROPPED] =
8404 mlx5_glue->dv_create_flow(dtb->any_matcher,
8405 (void *)&value, i, actions);
8406 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8407 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8416 * Create the needed meter and suffix tables.
8417 * Lock free, (mutex should be acquired by caller).
8420 * Pointer to Ethernet device.
8422 * Pointer to the flow meter.
8425 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8427 static struct mlx5_meter_domains_infos *
8428 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8429 const struct mlx5_flow_meter *fm)
8431 struct mlx5_priv *priv = dev->data->dev_private;
8432 struct mlx5_meter_domains_infos *mtb;
8436 if (!priv->mtr_en) {
8437 rte_errno = ENOTSUP;
8440 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8442 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8445 /* Create meter count actions */
8446 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8447 if (!fm->policer_stats.cnt[i])
8449 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8451 /* Create drop action. */
8452 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8453 if (!mtb->drop_actn) {
8454 DRV_LOG(ERR, "Failed to create drop action.");
8457 /* Egress meter table. */
8458 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8460 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8463 /* Ingress meter table. */
8464 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8466 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8469 /* FDB meter table. */
8470 if (priv->config.dv_esw_en) {
8471 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8472 priv->mtr_color_reg);
8474 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8480 flow_dv_destroy_mtr_tbl(dev, mtb);
8485 * Destroy domain policer rule.
8488 * Pointer to domain table.
8491 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8495 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8496 if (dt->policer_rules[i]) {
8497 claim_zero(mlx5_glue->dv_destroy_flow
8498 (dt->policer_rules[i]));
8499 dt->policer_rules[i] = NULL;
8502 if (dt->jump_actn) {
8503 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8504 dt->jump_actn = NULL;
8509 * Destroy policer rules.
8512 * Pointer to Ethernet device.
8514 * Pointer to flow meter structure.
8516 * Pointer to flow attributes.
8522 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8523 const struct mlx5_flow_meter *fm,
8524 const struct rte_flow_attr *attr)
8526 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8531 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8533 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8535 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8540 * Create specify domain meter policer rule.
8543 * Pointer to flow meter structure.
8545 * Pointer to DV meter table set.
8547 * Pointer to suffix table.
8548 * @param[in] mtr_reg_c
8549 * Color match REG_C.
8552 * 0 on success, -1 otherwise.
8555 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8556 struct mlx5_meter_domain_info *dtb,
8557 struct mlx5_flow_tbl_resource *sfx_tb,
8560 struct mlx5_flow_dv_match_params matcher = {
8561 .size = sizeof(matcher.buf),
8563 struct mlx5_flow_dv_match_params value = {
8564 .size = sizeof(value.buf),
8566 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8567 void *actions[METER_ACTIONS];
8570 /* Create jump action. */
8573 if (!dtb->jump_actn)
8575 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8577 if (!dtb->jump_actn) {
8578 DRV_LOG(ERR, "Failed to create policer jump action.");
8581 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8584 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8585 rte_col_2_mlx5_col(i), UINT8_MAX);
8586 if (mtb->count_actns[i])
8587 actions[j++] = mtb->count_actns[i];
8588 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8589 actions[j++] = mtb->drop_actn;
8591 actions[j++] = dtb->jump_actn;
8592 dtb->policer_rules[i] =
8593 mlx5_glue->dv_create_flow(dtb->color_matcher,
8596 if (!dtb->policer_rules[i]) {
8597 DRV_LOG(ERR, "Failed to create policer rule.");
8608 * Create policer rules.
8611 * Pointer to Ethernet device.
8613 * Pointer to flow meter structure.
8615 * Pointer to flow attributes.
8618 * 0 on success, -1 otherwise.
8621 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8622 struct mlx5_flow_meter *fm,
8623 const struct rte_flow_attr *attr)
8625 struct mlx5_priv *priv = dev->data->dev_private;
8626 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8630 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8631 priv->sh->tx_mtr_sfx_tbl,
8632 priv->mtr_color_reg);
8634 DRV_LOG(ERR, "Failed to create egress policer.");
8638 if (attr->ingress) {
8639 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8640 priv->sh->rx_mtr_sfx_tbl,
8641 priv->mtr_color_reg);
8643 DRV_LOG(ERR, "Failed to create ingress policer.");
8647 if (attr->transfer) {
8648 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8649 priv->sh->fdb_mtr_sfx_tbl,
8650 priv->mtr_color_reg);
8652 DRV_LOG(ERR, "Failed to create transfer policer.");
8658 flow_dv_destroy_policer_rules(dev, fm, attr);
8663 * Query a devx counter.
8666 * Pointer to the Ethernet device structure.
8668 * Pointer to the flow counter.
8670 * Set to clear the counter statistics.
8672 * The statistics value of packets.
8674 * The statistics value of bytes.
8677 * 0 on success, otherwise return -1.
8680 flow_dv_counter_query(struct rte_eth_dev *dev,
8681 struct mlx5_flow_counter *cnt, bool clear,
8682 uint64_t *pkts, uint64_t *bytes)
8684 struct mlx5_priv *priv = dev->data->dev_private;
8685 uint64_t inn_pkts, inn_bytes;
8688 if (!priv->config.devx)
8690 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8693 *pkts = inn_pkts - cnt->hits;
8694 *bytes = inn_bytes - cnt->bytes;
8696 cnt->hits = inn_pkts;
8697 cnt->bytes = inn_bytes;
8703 * Mutex-protected thunk to lock-free __flow_dv_translate().
8706 flow_dv_translate(struct rte_eth_dev *dev,
8707 struct mlx5_flow *dev_flow,
8708 const struct rte_flow_attr *attr,
8709 const struct rte_flow_item items[],
8710 const struct rte_flow_action actions[],
8711 struct rte_flow_error *error)
8715 flow_dv_shared_lock(dev);
8716 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8717 flow_dv_shared_unlock(dev);
8722 * Mutex-protected thunk to lock-free __flow_dv_apply().
8725 flow_dv_apply(struct rte_eth_dev *dev,
8726 struct rte_flow *flow,
8727 struct rte_flow_error *error)
8731 flow_dv_shared_lock(dev);
8732 ret = __flow_dv_apply(dev, flow, error);
8733 flow_dv_shared_unlock(dev);
8738 * Mutex-protected thunk to lock-free __flow_dv_remove().
8741 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8743 flow_dv_shared_lock(dev);
8744 __flow_dv_remove(dev, flow);
8745 flow_dv_shared_unlock(dev);
8749 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8752 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8754 flow_dv_shared_lock(dev);
8755 __flow_dv_destroy(dev, flow);
8756 flow_dv_shared_unlock(dev);
8760 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8762 static struct mlx5_flow_counter *
8763 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8765 struct mlx5_flow_counter *cnt;
8767 flow_dv_shared_lock(dev);
8768 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8769 flow_dv_shared_unlock(dev);
8774 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8777 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8779 flow_dv_shared_lock(dev);
8780 flow_dv_counter_release(dev, cnt);
8781 flow_dv_shared_unlock(dev);
8784 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8785 .validate = flow_dv_validate,
8786 .prepare = flow_dv_prepare,
8787 .translate = flow_dv_translate,
8788 .apply = flow_dv_apply,
8789 .remove = flow_dv_remove,
8790 .destroy = flow_dv_destroy,
8791 .query = flow_dv_query,
8792 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8793 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8794 .create_policer_rules = flow_dv_create_policer_rules,
8795 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8796 .counter_alloc = flow_dv_counter_allocate,
8797 .counter_free = flow_dv_counter_free,
8798 .counter_query = flow_dv_counter_query,
8801 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */