drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static void
1329 mlx5_flow_field_id_to_modify_info
1330                 (const struct rte_flow_action_modify_data *data,
1331                  struct field_modify_info *info,
1332                  uint32_t *mask, uint32_t *value, uint32_t width,
1333                  struct rte_eth_dev *dev,
1334                  const struct rte_flow_attr *attr,
1335                  struct rte_flow_error *error)
1336 {
1337         uint32_t idx = 0;
1338         switch (data->field) {
1339         case RTE_FLOW_FIELD_START:
1340                 /* not supported yet */
1341                 MLX5_ASSERT(false);
1342                 break;
1343         case RTE_FLOW_FIELD_MAC_DST:
1344                 if (mask) {
1345                         if (data->offset < 32) {
1346                                 info[idx] = (struct field_modify_info){4, 0,
1347                                                 MLX5_MODI_OUT_DMAC_47_16};
1348                                 if (width < 32) {
1349                                         mask[idx] =
1350                                                 rte_cpu_to_be_32(0xffffffff >>
1351                                                                  (32 - width));
1352                                         width = 0;
1353                                 } else {
1354                                         mask[idx] = RTE_BE32(0xffffffff);
1355                                         width -= 32;
1356                                 }
1357                                 if (!width)
1358                                         break;
1359                                 ++idx;
1360                         }
1361                         info[idx] = (struct field_modify_info){2, 4 * idx,
1362                                                 MLX5_MODI_OUT_DMAC_15_0};
1363                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1364                                                      (16 - width));
1365                 } else {
1366                         if (data->offset < 32)
1367                                 info[idx++] = (struct field_modify_info){4, 0,
1368                                                 MLX5_MODI_OUT_DMAC_47_16};
1369                         info[idx] = (struct field_modify_info){2, 0,
1370                                                 MLX5_MODI_OUT_DMAC_15_0};
1371                 }
1372                 break;
1373         case RTE_FLOW_FIELD_MAC_SRC:
1374                 if (mask) {
1375                         if (data->offset < 32) {
1376                                 info[idx] = (struct field_modify_info){4, 0,
1377                                                 MLX5_MODI_OUT_SMAC_47_16};
1378                                 if (width < 32) {
1379                                         mask[idx] =
1380                                                 rte_cpu_to_be_32(0xffffffff >>
1381                                                                 (32 - width));
1382                                         width = 0;
1383                                 } else {
1384                                         mask[idx] = RTE_BE32(0xffffffff);
1385                                         width -= 32;
1386                                 }
1387                                 if (!width)
1388                                         break;
1389                                 ++idx;
1390                         }
1391                         info[idx] = (struct field_modify_info){2, 4 * idx,
1392                                                 MLX5_MODI_OUT_SMAC_15_0};
1393                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1394                                                      (16 - width));
1395                 } else {
1396                         if (data->offset < 32)
1397                                 info[idx++] = (struct field_modify_info){4, 0,
1398                                                 MLX5_MODI_OUT_SMAC_47_16};
1399                         info[idx] = (struct field_modify_info){2, 0,
1400                                                 MLX5_MODI_OUT_SMAC_15_0};
1401                 }
1402                 break;
1403         case RTE_FLOW_FIELD_VLAN_TYPE:
1404                 /* not supported yet */
1405                 break;
1406         case RTE_FLOW_FIELD_VLAN_ID:
1407                 info[idx] = (struct field_modify_info){2, 0,
1408                                         MLX5_MODI_OUT_FIRST_VID};
1409                 if (mask)
1410                         mask[idx] = rte_cpu_to_be_32(0x00000fff >>
1411                                                      (12 - width));
1412                 break;
1413         case RTE_FLOW_FIELD_MAC_TYPE:
1414                 info[idx] = (struct field_modify_info){2, 0,
1415                                         MLX5_MODI_OUT_ETHERTYPE};
1416                 if (mask)
1417                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1418                                                      (16 - width));
1419                 break;
1420         case RTE_FLOW_FIELD_IPV4_DSCP:
1421                 info[idx] = (struct field_modify_info){1, 0,
1422                                         MLX5_MODI_OUT_IP_DSCP};
1423                 if (mask)
1424                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1425                                                      (6 - width));
1426                 break;
1427         case RTE_FLOW_FIELD_IPV4_TTL:
1428                 info[idx] = (struct field_modify_info){1, 0,
1429                                         MLX5_MODI_OUT_IPV4_TTL};
1430                 if (mask)
1431                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1432                                                      (8 - width));
1433                 break;
1434         case RTE_FLOW_FIELD_IPV4_SRC:
1435                 info[idx] = (struct field_modify_info){4, 0,
1436                                         MLX5_MODI_OUT_SIPV4};
1437                 if (mask)
1438                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1439                                                      (32 - width));
1440                 break;
1441         case RTE_FLOW_FIELD_IPV4_DST:
1442                 info[idx] = (struct field_modify_info){4, 0,
1443                                         MLX5_MODI_OUT_DIPV4};
1444                 if (mask)
1445                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1446                                                      (32 - width));
1447                 break;
1448         case RTE_FLOW_FIELD_IPV6_DSCP:
1449                 info[idx] = (struct field_modify_info){1, 0,
1450                                         MLX5_MODI_OUT_IP_DSCP};
1451                 if (mask)
1452                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1453                                                      (6 - width));
1454                 break;
1455         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1456                 info[idx] = (struct field_modify_info){1, 0,
1457                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1458                 if (mask)
1459                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1460                                                      (8 - width));
1461                 break;
1462         case RTE_FLOW_FIELD_IPV6_SRC:
1463                 if (mask) {
1464                         if (data->offset < 32) {
1465                                 info[idx] = (struct field_modify_info){4, 0,
1466                                                 MLX5_MODI_OUT_SIPV6_127_96};
1467                                 if (width < 32) {
1468                                         mask[idx] =
1469                                                 rte_cpu_to_be_32(0xffffffff >>
1470                                                                  (32 - width));
1471                                         width = 0;
1472                                 } else {
1473                                         mask[idx] = RTE_BE32(0xffffffff);
1474                                         width -= 32;
1475                                 }
1476                                 if (!width)
1477                                         break;
1478                                 ++idx;
1479                         }
1480                         if (data->offset < 64) {
1481                                 info[idx] = (struct field_modify_info){4,
1482                                                 4 * idx,
1483                                                 MLX5_MODI_OUT_SIPV6_95_64};
1484                                 if (width < 32) {
1485                                         mask[idx] =
1486                                                 rte_cpu_to_be_32(0xffffffff >>
1487                                                                  (32 - width));
1488                                         width = 0;
1489                                 } else {
1490                                         mask[idx] = RTE_BE32(0xffffffff);
1491                                         width -= 32;
1492                                 }
1493                                 if (!width)
1494                                         break;
1495                                 ++idx;
1496                         }
1497                         if (data->offset < 96) {
1498                                 info[idx] = (struct field_modify_info){4,
1499                                                 8 * idx,
1500                                                 MLX5_MODI_OUT_SIPV6_63_32};
1501                                 if (width < 32) {
1502                                         mask[idx] =
1503                                                 rte_cpu_to_be_32(0xffffffff >>
1504                                                                  (32 - width));
1505                                         width = 0;
1506                                 } else {
1507                                         mask[idx] = RTE_BE32(0xffffffff);
1508                                         width -= 32;
1509                                 }
1510                                 if (!width)
1511                                         break;
1512                                 ++idx;
1513                         }
1514                         info[idx] = (struct field_modify_info){4, 12 * idx,
1515                                                 MLX5_MODI_OUT_SIPV6_31_0};
1516                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1517                                                      (32 - width));
1518                 } else {
1519                         if (data->offset < 32)
1520                                 info[idx++] = (struct field_modify_info){4, 0,
1521                                                 MLX5_MODI_OUT_SIPV6_127_96};
1522                         if (data->offset < 64)
1523                                 info[idx++] = (struct field_modify_info){4, 0,
1524                                                 MLX5_MODI_OUT_SIPV6_95_64};
1525                         if (data->offset < 96)
1526                                 info[idx++] = (struct field_modify_info){4, 0,
1527                                                 MLX5_MODI_OUT_SIPV6_63_32};
1528                         if (data->offset < 128)
1529                                 info[idx++] = (struct field_modify_info){4, 0,
1530                                                 MLX5_MODI_OUT_SIPV6_31_0};
1531                 }
1532                 break;
1533         case RTE_FLOW_FIELD_IPV6_DST:
1534                 if (mask) {
1535                         if (data->offset < 32) {
1536                                 info[idx] = (struct field_modify_info){4, 0,
1537                                                 MLX5_MODI_OUT_DIPV6_127_96};
1538                                 if (width < 32) {
1539                                         mask[idx] =
1540                                                 rte_cpu_to_be_32(0xffffffff >>
1541                                                                  (32 - width));
1542                                         width = 0;
1543                                 } else {
1544                                         mask[idx] = RTE_BE32(0xffffffff);
1545                                         width -= 32;
1546                                 }
1547                                 if (!width)
1548                                         break;
1549                                 ++idx;
1550                         }
1551                         if (data->offset < 64) {
1552                                 info[idx] = (struct field_modify_info){4,
1553                                                 4 * idx,
1554                                                 MLX5_MODI_OUT_DIPV6_95_64};
1555                                 if (width < 32) {
1556                                         mask[idx] =
1557                                                 rte_cpu_to_be_32(0xffffffff >>
1558                                                                  (32 - width));
1559                                         width = 0;
1560                                 } else {
1561                                         mask[idx] = RTE_BE32(0xffffffff);
1562                                         width -= 32;
1563                                 }
1564                                 if (!width)
1565                                         break;
1566                                 ++idx;
1567                         }
1568                         if (data->offset < 96) {
1569                                 info[idx] = (struct field_modify_info){4,
1570                                                 8 * idx,
1571                                                 MLX5_MODI_OUT_DIPV6_63_32};
1572                                 if (width < 32) {
1573                                         mask[idx] =
1574                                                 rte_cpu_to_be_32(0xffffffff >>
1575                                                                  (32 - width));
1576                                         width = 0;
1577                                 } else {
1578                                         mask[idx] = RTE_BE32(0xffffffff);
1579                                         width -= 32;
1580                                 }
1581                                 if (!width)
1582                                         break;
1583                                 ++idx;
1584                         }
1585                         info[idx] = (struct field_modify_info){4, 12 * idx,
1586                                                 MLX5_MODI_OUT_DIPV6_31_0};
1587                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1588                                                      (32 - width));
1589                 } else {
1590                         if (data->offset < 32)
1591                                 info[idx++] = (struct field_modify_info){4, 0,
1592                                                 MLX5_MODI_OUT_DIPV6_127_96};
1593                         if (data->offset < 64)
1594                                 info[idx++] = (struct field_modify_info){4, 0,
1595                                                 MLX5_MODI_OUT_DIPV6_95_64};
1596                         if (data->offset < 96)
1597                                 info[idx++] = (struct field_modify_info){4, 0,
1598                                                 MLX5_MODI_OUT_DIPV6_63_32};
1599                         if (data->offset < 128)
1600                                 info[idx++] = (struct field_modify_info){4, 0,
1601                                                 MLX5_MODI_OUT_DIPV6_31_0};
1602                 }
1603                 break;
1604         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1605                 info[idx] = (struct field_modify_info){2, 0,
1606                                         MLX5_MODI_OUT_TCP_SPORT};
1607                 if (mask)
1608                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1609                                                      (16 - width));
1610                 break;
1611         case RTE_FLOW_FIELD_TCP_PORT_DST:
1612                 info[idx] = (struct field_modify_info){2, 0,
1613                                         MLX5_MODI_OUT_TCP_DPORT};
1614                 if (mask)
1615                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1616                                                      (16 - width));
1617                 break;
1618         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1619                 info[idx] = (struct field_modify_info){4, 0,
1620                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1621                 if (mask)
1622                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1623                                                      (32 - width));
1624                 break;
1625         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1626                 info[idx] = (struct field_modify_info){4, 0,
1627                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1628                 if (mask)
1629                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1630                                                      (32 - width));
1631                 break;
1632         case RTE_FLOW_FIELD_TCP_FLAGS:
1633                 info[idx] = (struct field_modify_info){1, 0,
1634                                         MLX5_MODI_OUT_TCP_FLAGS};
1635                 if (mask)
1636                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1637                                                      (6 - width));
1638                 break;
1639         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1640                 info[idx] = (struct field_modify_info){2, 0,
1641                                         MLX5_MODI_OUT_UDP_SPORT};
1642                 if (mask)
1643                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1644                                                      (16 - width));
1645                 break;
1646         case RTE_FLOW_FIELD_UDP_PORT_DST:
1647                 info[idx] = (struct field_modify_info){2, 0,
1648                                         MLX5_MODI_OUT_UDP_DPORT};
1649                 if (mask)
1650                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1651                                                      (16 - width));
1652                 break;
1653         case RTE_FLOW_FIELD_VXLAN_VNI:
1654                 /* not supported yet */
1655                 break;
1656         case RTE_FLOW_FIELD_GENEVE_VNI:
1657                 /* not supported yet*/
1658                 break;
1659         case RTE_FLOW_FIELD_GTP_TEID:
1660                 info[idx] = (struct field_modify_info){4, 0,
1661                                         MLX5_MODI_GTP_TEID};
1662                 if (mask)
1663                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1664                                                      (32 - width));
1665                 break;
1666         case RTE_FLOW_FIELD_TAG:
1667                 {
1668                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1669                                                    data->level, error);
1670                         if (reg < 0)
1671                                 return;
1672                         MLX5_ASSERT(reg != REG_NON);
1673                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1674                         info[idx] = (struct field_modify_info){4, 0,
1675                                                 reg_to_field[reg]};
1676                         if (mask)
1677                                 mask[idx] =
1678                                         rte_cpu_to_be_32(0xffffffff >>
1679                                                          (32 - width));
1680                 }
1681                 break;
1682         case RTE_FLOW_FIELD_MARK:
1683                 {
1684                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1685                                                        0, error);
1686                         if (reg < 0)
1687                                 return;
1688                         MLX5_ASSERT(reg != REG_NON);
1689                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1690                         info[idx] = (struct field_modify_info){4, 0,
1691                                                 reg_to_field[reg]};
1692                         if (mask)
1693                                 mask[idx] =
1694                                         rte_cpu_to_be_32(0xffffffff >>
1695                                                          (32 - width));
1696                 }
1697                 break;
1698         case RTE_FLOW_FIELD_META:
1699                 {
1700                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1701                         if (reg < 0)
1702                                 return;
1703                         MLX5_ASSERT(reg != REG_NON);
1704                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1705                         info[idx] = (struct field_modify_info){4, 0,
1706                                                 reg_to_field[reg]};
1707                         if (mask)
1708                                 mask[idx] =
1709                                         rte_cpu_to_be_32(0xffffffff >>
1710                                                          (32 - width));
1711                 }
1712                 break;
1713         case RTE_FLOW_FIELD_POINTER:
1714                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1715                         if (mask[idx]) {
1716                                 memcpy(&value[idx],
1717                                         (void *)(uintptr_t)data->value, 32);
1718                                 value[idx] = rte_cpu_to_be_32(value[idx]);
1719                                 break;
1720                         }
1721                 }
1722                 break;
1723         case RTE_FLOW_FIELD_VALUE:
1724                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1725                         if (mask[idx]) {
1726                                 value[idx] =
1727                                         rte_cpu_to_be_32((uint32_t)data->value);
1728                                 break;
1729                         }
1730                 }
1731                 break;
1732         default:
1733                 MLX5_ASSERT(false);
1734                 break;
1735         }
1736 }
1737
1738 /**
1739  * Convert modify_field action to DV specification.
1740  *
1741  * @param[in] dev
1742  *   Pointer to the rte_eth_dev structure.
1743  * @param[in,out] resource
1744  *   Pointer to the modify-header resource.
1745  * @param[in] action
1746  *   Pointer to action specification.
1747  * @param[in] attr
1748  *   Attributes of flow that includes this item.
1749  * @param[out] error
1750  *   Pointer to the error structure.
1751  *
1752  * @return
1753  *   0 on success, a negative errno value otherwise and rte_errno is set.
1754  */
1755 static int
1756 flow_dv_convert_action_modify_field
1757                         (struct rte_eth_dev *dev,
1758                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1759                          const struct rte_flow_action *action,
1760                          const struct rte_flow_attr *attr,
1761                          struct rte_flow_error *error)
1762 {
1763         const struct rte_flow_action_modify_field *conf =
1764                 (const struct rte_flow_action_modify_field *)(action->conf);
1765         struct rte_flow_item item;
1766         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1767                                                                 {0, 0, 0} };
1768         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1769                                                                 {0, 0, 0} };
1770         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1771         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1772         uint32_t type;
1773
1774         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1775                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1776                 type = MLX5_MODIFICATION_TYPE_SET;
1777                 /** For SET fill the destination field (field) first. */
1778                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1779                                           value, conf->width, dev, attr, error);
1780                 /** Then copy immediate value from source as per mask. */
1781                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1782                                           value, conf->width, dev, attr, error);
1783                 item.spec = &value;
1784         } else {
1785                 type = MLX5_MODIFICATION_TYPE_COPY;
1786                 /** For COPY fill the destination field (dcopy) without mask. */
1787                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1788                                           value, conf->width, dev, attr, error);
1789                 /** Then construct the source field (field) with mask. */
1790                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1791                                           value, conf->width, dev, attr, error);
1792         }
1793         item.mask = &mask;
1794         return flow_dv_convert_modify_action(&item,
1795                         field, dcopy, resource, type, error);
1796 }
1797
1798 /**
1799  * Validate MARK item.
1800  *
1801  * @param[in] dev
1802  *   Pointer to the rte_eth_dev structure.
1803  * @param[in] item
1804  *   Item specification.
1805  * @param[in] attr
1806  *   Attributes of flow that includes this item.
1807  * @param[out] error
1808  *   Pointer to error structure.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1815                            const struct rte_flow_item *item,
1816                            const struct rte_flow_attr *attr __rte_unused,
1817                            struct rte_flow_error *error)
1818 {
1819         struct mlx5_priv *priv = dev->data->dev_private;
1820         struct mlx5_dev_config *config = &priv->config;
1821         const struct rte_flow_item_mark *spec = item->spec;
1822         const struct rte_flow_item_mark *mask = item->mask;
1823         const struct rte_flow_item_mark nic_mask = {
1824                 .id = priv->sh->dv_mark_mask,
1825         };
1826         int ret;
1827
1828         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1829                 return rte_flow_error_set(error, ENOTSUP,
1830                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1831                                           "extended metadata feature"
1832                                           " isn't enabled");
1833         if (!mlx5_flow_ext_mreg_supported(dev))
1834                 return rte_flow_error_set(error, ENOTSUP,
1835                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1836                                           "extended metadata register"
1837                                           " isn't supported");
1838         if (!nic_mask.id)
1839                 return rte_flow_error_set(error, ENOTSUP,
1840                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1841                                           "extended metadata register"
1842                                           " isn't available");
1843         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1844         if (ret < 0)
1845                 return ret;
1846         if (!spec)
1847                 return rte_flow_error_set(error, EINVAL,
1848                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1849                                           item->spec,
1850                                           "data cannot be empty");
1851         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1854                                           &spec->id,
1855                                           "mark id exceeds the limit");
1856         if (!mask)
1857                 mask = &nic_mask;
1858         if (!mask->id)
1859                 return rte_flow_error_set(error, EINVAL,
1860                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1861                                         "mask cannot be zero");
1862
1863         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1864                                         (const uint8_t *)&nic_mask,
1865                                         sizeof(struct rte_flow_item_mark),
1866                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1867         if (ret < 0)
1868                 return ret;
1869         return 0;
1870 }
1871
1872 /**
1873  * Validate META item.
1874  *
1875  * @param[in] dev
1876  *   Pointer to the rte_eth_dev structure.
1877  * @param[in] item
1878  *   Item specification.
1879  * @param[in] attr
1880  *   Attributes of flow that includes this item.
1881  * @param[out] error
1882  *   Pointer to error structure.
1883  *
1884  * @return
1885  *   0 on success, a negative errno value otherwise and rte_errno is set.
1886  */
1887 static int
1888 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1889                            const struct rte_flow_item *item,
1890                            const struct rte_flow_attr *attr,
1891                            struct rte_flow_error *error)
1892 {
1893         struct mlx5_priv *priv = dev->data->dev_private;
1894         struct mlx5_dev_config *config = &priv->config;
1895         const struct rte_flow_item_meta *spec = item->spec;
1896         const struct rte_flow_item_meta *mask = item->mask;
1897         struct rte_flow_item_meta nic_mask = {
1898                 .data = UINT32_MAX
1899         };
1900         int reg;
1901         int ret;
1902
1903         if (!spec)
1904                 return rte_flow_error_set(error, EINVAL,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1906                                           item->spec,
1907                                           "data cannot be empty");
1908         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1909                 if (!mlx5_flow_ext_mreg_supported(dev))
1910                         return rte_flow_error_set(error, ENOTSUP,
1911                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1912                                           "extended metadata register"
1913                                           " isn't supported");
1914                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1915                 if (reg < 0)
1916                         return reg;
1917                 if (reg == REG_NON)
1918                         return rte_flow_error_set(error, ENOTSUP,
1919                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1920                                         "unavalable extended metadata register");
1921                 if (reg == REG_B)
1922                         return rte_flow_error_set(error, ENOTSUP,
1923                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1924                                           "match on reg_b "
1925                                           "isn't supported");
1926                 if (reg != REG_A)
1927                         nic_mask.data = priv->sh->dv_meta_mask;
1928         } else {
1929                 if (attr->transfer)
1930                         return rte_flow_error_set(error, ENOTSUP,
1931                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1932                                         "extended metadata feature "
1933                                         "should be enabled when "
1934                                         "meta item is requested "
1935                                         "with e-switch mode ");
1936                 if (attr->ingress)
1937                         return rte_flow_error_set(error, ENOTSUP,
1938                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1939                                         "match on metadata for ingress "
1940                                         "is not supported in legacy "
1941                                         "metadata mode");
1942         }
1943         if (!mask)
1944                 mask = &rte_flow_item_meta_mask;
1945         if (!mask->data)
1946                 return rte_flow_error_set(error, EINVAL,
1947                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1948                                         "mask cannot be zero");
1949
1950         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1951                                         (const uint8_t *)&nic_mask,
1952                                         sizeof(struct rte_flow_item_meta),
1953                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1954         return ret;
1955 }
1956
1957 /**
1958  * Validate TAG item.
1959  *
1960  * @param[in] dev
1961  *   Pointer to the rte_eth_dev structure.
1962  * @param[in] item
1963  *   Item specification.
1964  * @param[in] attr
1965  *   Attributes of flow that includes this item.
1966  * @param[out] error
1967  *   Pointer to error structure.
1968  *
1969  * @return
1970  *   0 on success, a negative errno value otherwise and rte_errno is set.
1971  */
1972 static int
1973 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1974                           const struct rte_flow_item *item,
1975                           const struct rte_flow_attr *attr __rte_unused,
1976                           struct rte_flow_error *error)
1977 {
1978         const struct rte_flow_item_tag *spec = item->spec;
1979         const struct rte_flow_item_tag *mask = item->mask;
1980         const struct rte_flow_item_tag nic_mask = {
1981                 .data = RTE_BE32(UINT32_MAX),
1982                 .index = 0xff,
1983         };
1984         int ret;
1985
1986         if (!mlx5_flow_ext_mreg_supported(dev))
1987                 return rte_flow_error_set(error, ENOTSUP,
1988                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1989                                           "extensive metadata register"
1990                                           " isn't supported");
1991         if (!spec)
1992                 return rte_flow_error_set(error, EINVAL,
1993                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1994                                           item->spec,
1995                                           "data cannot be empty");
1996         if (!mask)
1997                 mask = &rte_flow_item_tag_mask;
1998         if (!mask->data)
1999                 return rte_flow_error_set(error, EINVAL,
2000                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2001                                         "mask cannot be zero");
2002
2003         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2004                                         (const uint8_t *)&nic_mask,
2005                                         sizeof(struct rte_flow_item_tag),
2006                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2007         if (ret < 0)
2008                 return ret;
2009         if (mask->index != 0xff)
2010                 return rte_flow_error_set(error, EINVAL,
2011                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2012                                           "partial mask for tag index"
2013                                           " is not supported");
2014         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2015         if (ret < 0)
2016                 return ret;
2017         MLX5_ASSERT(ret != REG_NON);
2018         return 0;
2019 }
2020
2021 /**
2022  * Validate vport item.
2023  *
2024  * @param[in] dev
2025  *   Pointer to the rte_eth_dev structure.
2026  * @param[in] item
2027  *   Item specification.
2028  * @param[in] attr
2029  *   Attributes of flow that includes this item.
2030  * @param[in] item_flags
2031  *   Bit-fields that holds the items detected until now.
2032  * @param[out] error
2033  *   Pointer to error structure.
2034  *
2035  * @return
2036  *   0 on success, a negative errno value otherwise and rte_errno is set.
2037  */
2038 static int
2039 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2040                               const struct rte_flow_item *item,
2041                               const struct rte_flow_attr *attr,
2042                               uint64_t item_flags,
2043                               struct rte_flow_error *error)
2044 {
2045         const struct rte_flow_item_port_id *spec = item->spec;
2046         const struct rte_flow_item_port_id *mask = item->mask;
2047         const struct rte_flow_item_port_id switch_mask = {
2048                         .id = 0xffffffff,
2049         };
2050         struct mlx5_priv *esw_priv;
2051         struct mlx5_priv *dev_priv;
2052         int ret;
2053
2054         if (!attr->transfer)
2055                 return rte_flow_error_set(error, EINVAL,
2056                                           RTE_FLOW_ERROR_TYPE_ITEM,
2057                                           NULL,
2058                                           "match on port id is valid only"
2059                                           " when transfer flag is enabled");
2060         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2063                                           "multiple source ports are not"
2064                                           " supported");
2065         if (!mask)
2066                 mask = &switch_mask;
2067         if (mask->id != 0xffffffff)
2068                 return rte_flow_error_set(error, ENOTSUP,
2069                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2070                                            mask,
2071                                            "no support for partial mask on"
2072                                            " \"id\" field");
2073         ret = mlx5_flow_item_acceptable
2074                                 (item, (const uint8_t *)mask,
2075                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2076                                  sizeof(struct rte_flow_item_port_id),
2077                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2078         if (ret)
2079                 return ret;
2080         if (!spec)
2081                 return 0;
2082         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2083         if (!esw_priv)
2084                 return rte_flow_error_set(error, rte_errno,
2085                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2086                                           "failed to obtain E-Switch info for"
2087                                           " port");
2088         dev_priv = mlx5_dev_to_eswitch_info(dev);
2089         if (!dev_priv)
2090                 return rte_flow_error_set(error, rte_errno,
2091                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2092                                           NULL,
2093                                           "failed to obtain E-Switch info");
2094         if (esw_priv->domain_id != dev_priv->domain_id)
2095                 return rte_flow_error_set(error, EINVAL,
2096                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2097                                           "cannot match on a port from a"
2098                                           " different E-Switch");
2099         return 0;
2100 }
2101
2102 /**
2103  * Validate VLAN item.
2104  *
2105  * @param[in] item
2106  *   Item specification.
2107  * @param[in] item_flags
2108  *   Bit-fields that holds the items detected until now.
2109  * @param[in] dev
2110  *   Ethernet device flow is being created on.
2111  * @param[out] error
2112  *   Pointer to error structure.
2113  *
2114  * @return
2115  *   0 on success, a negative errno value otherwise and rte_errno is set.
2116  */
2117 static int
2118 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2119                            uint64_t item_flags,
2120                            struct rte_eth_dev *dev,
2121                            struct rte_flow_error *error)
2122 {
2123         const struct rte_flow_item_vlan *mask = item->mask;
2124         const struct rte_flow_item_vlan nic_mask = {
2125                 .tci = RTE_BE16(UINT16_MAX),
2126                 .inner_type = RTE_BE16(UINT16_MAX),
2127                 .has_more_vlan = 1,
2128         };
2129         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2130         int ret;
2131         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2132                                         MLX5_FLOW_LAYER_INNER_L4) :
2133                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2134                                         MLX5_FLOW_LAYER_OUTER_L4);
2135         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2136                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2137
2138         if (item_flags & vlanm)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2141                                           "multiple VLAN layers not supported");
2142         else if ((item_flags & l34m) != 0)
2143                 return rte_flow_error_set(error, EINVAL,
2144                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2145                                           "VLAN cannot follow L3/L4 layer");
2146         if (!mask)
2147                 mask = &rte_flow_item_vlan_mask;
2148         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2149                                         (const uint8_t *)&nic_mask,
2150                                         sizeof(struct rte_flow_item_vlan),
2151                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2152         if (ret)
2153                 return ret;
2154         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2155                 struct mlx5_priv *priv = dev->data->dev_private;
2156
2157                 if (priv->vmwa_context) {
2158                         /*
2159                          * Non-NULL context means we have a virtual machine
2160                          * and SR-IOV enabled, we have to create VLAN interface
2161                          * to make hypervisor to setup E-Switch vport
2162                          * context correctly. We avoid creating the multiple
2163                          * VLAN interfaces, so we cannot support VLAN tag mask.
2164                          */
2165                         return rte_flow_error_set(error, EINVAL,
2166                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2167                                                   item,
2168                                                   "VLAN tag mask is not"
2169                                                   " supported in virtual"
2170                                                   " environment");
2171                 }
2172         }
2173         return 0;
2174 }
2175
2176 /*
2177  * GTP flags are contained in 1 byte of the format:
2178  * -------------------------------------------
2179  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2180  * |-----------------------------------------|
2181  * | value | Version | PT | Res | E | S | PN |
2182  * -------------------------------------------
2183  *
2184  * Matching is supported only for GTP flags E, S, PN.
2185  */
2186 #define MLX5_GTP_FLAGS_MASK     0x07
2187
2188 /**
2189  * Validate GTP item.
2190  *
2191  * @param[in] dev
2192  *   Pointer to the rte_eth_dev structure.
2193  * @param[in] item
2194  *   Item specification.
2195  * @param[in] item_flags
2196  *   Bit-fields that holds the items detected until now.
2197  * @param[out] error
2198  *   Pointer to error structure.
2199  *
2200  * @return
2201  *   0 on success, a negative errno value otherwise and rte_errno is set.
2202  */
2203 static int
2204 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2205                           const struct rte_flow_item *item,
2206                           uint64_t item_flags,
2207                           struct rte_flow_error *error)
2208 {
2209         struct mlx5_priv *priv = dev->data->dev_private;
2210         const struct rte_flow_item_gtp *spec = item->spec;
2211         const struct rte_flow_item_gtp *mask = item->mask;
2212         const struct rte_flow_item_gtp nic_mask = {
2213                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2214                 .msg_type = 0xff,
2215                 .teid = RTE_BE32(0xffffffff),
2216         };
2217
2218         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2219                 return rte_flow_error_set(error, ENOTSUP,
2220                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2221                                           "GTP support is not enabled");
2222         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2223                 return rte_flow_error_set(error, ENOTSUP,
2224                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2225                                           "multiple tunnel layers not"
2226                                           " supported");
2227         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2228                 return rte_flow_error_set(error, EINVAL,
2229                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2230                                           "no outer UDP layer found");
2231         if (!mask)
2232                 mask = &rte_flow_item_gtp_mask;
2233         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2234                 return rte_flow_error_set(error, ENOTSUP,
2235                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2236                                           "Match is supported for GTP"
2237                                           " flags only");
2238         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2239                                          (const uint8_t *)&nic_mask,
2240                                          sizeof(struct rte_flow_item_gtp),
2241                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2242 }
2243
2244 /**
2245  * Validate GTP PSC item.
2246  *
2247  * @param[in] item
2248  *   Item specification.
2249  * @param[in] last_item
2250  *   Previous validated item in the pattern items.
2251  * @param[in] gtp_item
2252  *   Previous GTP item specification.
2253  * @param[in] attr
2254  *   Pointer to flow attributes.
2255  * @param[out] error
2256  *   Pointer to error structure.
2257  *
2258  * @return
2259  *   0 on success, a negative errno value otherwise and rte_errno is set.
2260  */
2261 static int
2262 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2263                               uint64_t last_item,
2264                               const struct rte_flow_item *gtp_item,
2265                               const struct rte_flow_attr *attr,
2266                               struct rte_flow_error *error)
2267 {
2268         const struct rte_flow_item_gtp *gtp_spec;
2269         const struct rte_flow_item_gtp *gtp_mask;
2270         const struct rte_flow_item_gtp_psc *spec;
2271         const struct rte_flow_item_gtp_psc *mask;
2272         const struct rte_flow_item_gtp_psc nic_mask = {
2273                 .pdu_type = 0xFF,
2274                 .qfi = 0xFF,
2275         };
2276
2277         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2278                 return rte_flow_error_set
2279                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2280                          "GTP PSC item must be preceded with GTP item");
2281         gtp_spec = gtp_item->spec;
2282         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2283         /* GTP spec and E flag is requested to match zero. */
2284         if (gtp_spec &&
2285                 (gtp_mask->v_pt_rsv_flags &
2286                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2287                 return rte_flow_error_set
2288                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2289                          "GTP E flag must be 1 to match GTP PSC");
2290         /* Check the flow is not created in group zero. */
2291         if (!attr->transfer && !attr->group)
2292                 return rte_flow_error_set
2293                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2294                          "GTP PSC is not supported for group 0");
2295         /* GTP spec is here and E flag is requested to match zero. */
2296         if (!item->spec)
2297                 return 0;
2298         spec = item->spec;
2299         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2300         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2301                 return rte_flow_error_set
2302                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2303                          "PDU type should be smaller than 16");
2304         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2305                                          (const uint8_t *)&nic_mask,
2306                                          sizeof(struct rte_flow_item_gtp_psc),
2307                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2308 }
2309
2310 /**
2311  * Validate IPV4 item.
2312  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2313  * add specific validation of fragment_offset field,
2314  *
2315  * @param[in] item
2316  *   Item specification.
2317  * @param[in] item_flags
2318  *   Bit-fields that holds the items detected until now.
2319  * @param[out] error
2320  *   Pointer to error structure.
2321  *
2322  * @return
2323  *   0 on success, a negative errno value otherwise and rte_errno is set.
2324  */
2325 static int
2326 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2327                            uint64_t item_flags,
2328                            uint64_t last_item,
2329                            uint16_t ether_type,
2330                            struct rte_flow_error *error)
2331 {
2332         int ret;
2333         const struct rte_flow_item_ipv4 *spec = item->spec;
2334         const struct rte_flow_item_ipv4 *last = item->last;
2335         const struct rte_flow_item_ipv4 *mask = item->mask;
2336         rte_be16_t fragment_offset_spec = 0;
2337         rte_be16_t fragment_offset_last = 0;
2338         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2339                 .hdr = {
2340                         .src_addr = RTE_BE32(0xffffffff),
2341                         .dst_addr = RTE_BE32(0xffffffff),
2342                         .type_of_service = 0xff,
2343                         .fragment_offset = RTE_BE16(0xffff),
2344                         .next_proto_id = 0xff,
2345                         .time_to_live = 0xff,
2346                 },
2347         };
2348
2349         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2350                                            ether_type, &nic_ipv4_mask,
2351                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2352         if (ret < 0)
2353                 return ret;
2354         if (spec && mask)
2355                 fragment_offset_spec = spec->hdr.fragment_offset &
2356                                        mask->hdr.fragment_offset;
2357         if (!fragment_offset_spec)
2358                 return 0;
2359         /*
2360          * spec and mask are valid, enforce using full mask to make sure the
2361          * complete value is used correctly.
2362          */
2363         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2364                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2365                 return rte_flow_error_set(error, EINVAL,
2366                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2367                                           item, "must use full mask for"
2368                                           " fragment_offset");
2369         /*
2370          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2371          * indicating this is 1st fragment of fragmented packet.
2372          * This is not yet supported in MLX5, return appropriate error message.
2373          */
2374         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2375                 return rte_flow_error_set(error, ENOTSUP,
2376                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2377                                           "match on first fragment not "
2378                                           "supported");
2379         if (fragment_offset_spec && !last)
2380                 return rte_flow_error_set(error, ENOTSUP,
2381                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2382                                           "specified value not supported");
2383         /* spec and last are valid, validate the specified range. */
2384         fragment_offset_last = last->hdr.fragment_offset &
2385                                mask->hdr.fragment_offset;
2386         /*
2387          * Match on fragment_offset spec 0x2001 and last 0x3fff
2388          * means MF is 1 and frag-offset is > 0.
2389          * This packet is fragment 2nd and onward, excluding last.
2390          * This is not yet supported in MLX5, return appropriate
2391          * error message.
2392          */
2393         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2394             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2395                 return rte_flow_error_set(error, ENOTSUP,
2396                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2397                                           last, "match on following "
2398                                           "fragments not supported");
2399         /*
2400          * Match on fragment_offset spec 0x0001 and last 0x1fff
2401          * means MF is 0 and frag-offset is > 0.
2402          * This packet is last fragment of fragmented packet.
2403          * This is not yet supported in MLX5, return appropriate
2404          * error message.
2405          */
2406         if (fragment_offset_spec == RTE_BE16(1) &&
2407             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2408                 return rte_flow_error_set(error, ENOTSUP,
2409                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2410                                           last, "match on last "
2411                                           "fragment not supported");
2412         /*
2413          * Match on fragment_offset spec 0x0001 and last 0x3fff
2414          * means MF and/or frag-offset is not 0.
2415          * This is a fragmented packet.
2416          * Other range values are invalid and rejected.
2417          */
2418         if (!(fragment_offset_spec == RTE_BE16(1) &&
2419               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2420                 return rte_flow_error_set(error, ENOTSUP,
2421                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2422                                           "specified range not supported");
2423         return 0;
2424 }
2425
2426 /**
2427  * Validate IPV6 fragment extension item.
2428  *
2429  * @param[in] item
2430  *   Item specification.
2431  * @param[in] item_flags
2432  *   Bit-fields that holds the items detected until now.
2433  * @param[out] error
2434  *   Pointer to error structure.
2435  *
2436  * @return
2437  *   0 on success, a negative errno value otherwise and rte_errno is set.
2438  */
2439 static int
2440 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2441                                     uint64_t item_flags,
2442                                     struct rte_flow_error *error)
2443 {
2444         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2445         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2446         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2447         rte_be16_t frag_data_spec = 0;
2448         rte_be16_t frag_data_last = 0;
2449         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2450         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2451                                       MLX5_FLOW_LAYER_OUTER_L4;
2452         int ret = 0;
2453         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2454                 .hdr = {
2455                         .next_header = 0xff,
2456                         .frag_data = RTE_BE16(0xffff),
2457                 },
2458         };
2459
2460         if (item_flags & l4m)
2461                 return rte_flow_error_set(error, EINVAL,
2462                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2463                                           "ipv6 fragment extension item cannot "
2464                                           "follow L4 item.");
2465         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2466             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2467                 return rte_flow_error_set(error, EINVAL,
2468                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2469                                           "ipv6 fragment extension item must "
2470                                           "follow ipv6 item");
2471         if (spec && mask)
2472                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2473         if (!frag_data_spec)
2474                 return 0;
2475         /*
2476          * spec and mask are valid, enforce using full mask to make sure the
2477          * complete value is used correctly.
2478          */
2479         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2480                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483                                           item, "must use full mask for"
2484                                           " frag_data");
2485         /*
2486          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2487          * This is 1st fragment of fragmented packet.
2488          */
2489         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2490                 return rte_flow_error_set(error, ENOTSUP,
2491                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2492                                           "match on first fragment not "
2493                                           "supported");
2494         if (frag_data_spec && !last)
2495                 return rte_flow_error_set(error, EINVAL,
2496                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2497                                           "specified value not supported");
2498         ret = mlx5_flow_item_acceptable
2499                                 (item, (const uint8_t *)mask,
2500                                  (const uint8_t *)&nic_mask,
2501                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2502                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2503         if (ret)
2504                 return ret;
2505         /* spec and last are valid, validate the specified range. */
2506         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2507         /*
2508          * Match on frag_data spec 0x0009 and last 0xfff9
2509          * means M is 1 and frag-offset is > 0.
2510          * This packet is fragment 2nd and onward, excluding last.
2511          * This is not yet supported in MLX5, return appropriate
2512          * error message.
2513          */
2514         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2515                                        RTE_IPV6_EHDR_MF_MASK) &&
2516             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2517                 return rte_flow_error_set(error, ENOTSUP,
2518                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519                                           last, "match on following "
2520                                           "fragments not supported");
2521         /*
2522          * Match on frag_data spec 0x0008 and last 0xfff8
2523          * means M is 0 and frag-offset is > 0.
2524          * This packet is last fragment of fragmented packet.
2525          * This is not yet supported in MLX5, return appropriate
2526          * error message.
2527          */
2528         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2529             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2530                 return rte_flow_error_set(error, ENOTSUP,
2531                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532                                           last, "match on last "
2533                                           "fragment not supported");
2534         /* Other range values are invalid and rejected. */
2535         return rte_flow_error_set(error, EINVAL,
2536                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2537                                   "specified range not supported");
2538 }
2539
2540 /**
2541  * Validate the pop VLAN action.
2542  *
2543  * @param[in] dev
2544  *   Pointer to the rte_eth_dev structure.
2545  * @param[in] action_flags
2546  *   Holds the actions detected until now.
2547  * @param[in] action
2548  *   Pointer to the pop vlan action.
2549  * @param[in] item_flags
2550  *   The items found in this flow rule.
2551  * @param[in] attr
2552  *   Pointer to flow attributes.
2553  * @param[out] error
2554  *   Pointer to error structure.
2555  *
2556  * @return
2557  *   0 on success, a negative errno value otherwise and rte_errno is set.
2558  */
2559 static int
2560 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2561                                  uint64_t action_flags,
2562                                  const struct rte_flow_action *action,
2563                                  uint64_t item_flags,
2564                                  const struct rte_flow_attr *attr,
2565                                  struct rte_flow_error *error)
2566 {
2567         const struct mlx5_priv *priv = dev->data->dev_private;
2568
2569         (void)action;
2570         (void)attr;
2571         if (!priv->sh->pop_vlan_action)
2572                 return rte_flow_error_set(error, ENOTSUP,
2573                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2574                                           NULL,
2575                                           "pop vlan action is not supported");
2576         if (attr->egress)
2577                 return rte_flow_error_set(error, ENOTSUP,
2578                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2579                                           NULL,
2580                                           "pop vlan action not supported for "
2581                                           "egress");
2582         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2583                 return rte_flow_error_set(error, ENOTSUP,
2584                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2585                                           "no support for multiple VLAN "
2586                                           "actions");
2587         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2588         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2589             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2590                 return rte_flow_error_set(error, ENOTSUP,
2591                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2592                                           NULL,
2593                                           "cannot pop vlan after decap without "
2594                                           "match on inner vlan in the flow");
2595         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2596         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2597             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2598                 return rte_flow_error_set(error, ENOTSUP,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2600                                           NULL,
2601                                           "cannot pop vlan without a "
2602                                           "match on (outer) vlan in the flow");
2603         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2604                 return rte_flow_error_set(error, EINVAL,
2605                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2606                                           "wrong action order, port_id should "
2607                                           "be after pop VLAN action");
2608         if (!attr->transfer && priv->representor)
2609                 return rte_flow_error_set(error, ENOTSUP,
2610                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2611                                           "pop vlan action for VF representor "
2612                                           "not supported on NIC table");
2613         return 0;
2614 }
2615
2616 /**
2617  * Get VLAN default info from vlan match info.
2618  *
2619  * @param[in] items
2620  *   the list of item specifications.
2621  * @param[out] vlan
2622  *   pointer VLAN info to fill to.
2623  *
2624  * @return
2625  *   0 on success, a negative errno value otherwise and rte_errno is set.
2626  */
2627 static void
2628 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2629                                   struct rte_vlan_hdr *vlan)
2630 {
2631         const struct rte_flow_item_vlan nic_mask = {
2632                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2633                                 MLX5DV_FLOW_VLAN_VID_MASK),
2634                 .inner_type = RTE_BE16(0xffff),
2635         };
2636
2637         if (items == NULL)
2638                 return;
2639         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2640                 int type = items->type;
2641
2642                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2643                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2644                         break;
2645         }
2646         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2647                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2648                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2649
2650                 /* If VLAN item in pattern doesn't contain data, return here. */
2651                 if (!vlan_v)
2652                         return;
2653                 if (!vlan_m)
2654                         vlan_m = &nic_mask;
2655                 /* Only full match values are accepted */
2656                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2657                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2658                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2659                         vlan->vlan_tci |=
2660                                 rte_be_to_cpu_16(vlan_v->tci &
2661                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2662                 }
2663                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2664                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2665                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2666                         vlan->vlan_tci |=
2667                                 rte_be_to_cpu_16(vlan_v->tci &
2668                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2669                 }
2670                 if (vlan_m->inner_type == nic_mask.inner_type)
2671                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2672                                                            vlan_m->inner_type);
2673         }
2674 }
2675
2676 /**
2677  * Validate the push VLAN action.
2678  *
2679  * @param[in] dev
2680  *   Pointer to the rte_eth_dev structure.
2681  * @param[in] action_flags
2682  *   Holds the actions detected until now.
2683  * @param[in] item_flags
2684  *   The items found in this flow rule.
2685  * @param[in] action
2686  *   Pointer to the action structure.
2687  * @param[in] attr
2688  *   Pointer to flow attributes
2689  * @param[out] error
2690  *   Pointer to error structure.
2691  *
2692  * @return
2693  *   0 on success, a negative errno value otherwise and rte_errno is set.
2694  */
2695 static int
2696 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2697                                   uint64_t action_flags,
2698                                   const struct rte_flow_item_vlan *vlan_m,
2699                                   const struct rte_flow_action *action,
2700                                   const struct rte_flow_attr *attr,
2701                                   struct rte_flow_error *error)
2702 {
2703         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2704         const struct mlx5_priv *priv = dev->data->dev_private;
2705
2706         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2707             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2708                 return rte_flow_error_set(error, EINVAL,
2709                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2710                                           "invalid vlan ethertype");
2711         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2712                 return rte_flow_error_set(error, EINVAL,
2713                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2714                                           "wrong action order, port_id should "
2715                                           "be after push VLAN");
2716         if (!attr->transfer && priv->representor)
2717                 return rte_flow_error_set(error, ENOTSUP,
2718                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2719                                           "push vlan action for VF representor "
2720                                           "not supported on NIC table");
2721         if (vlan_m &&
2722             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2723             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2724                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2725             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2726             !(mlx5_flow_find_action
2727                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2728                 return rte_flow_error_set(error, EINVAL,
2729                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2730                                           "not full match mask on VLAN PCP and "
2731                                           "there is no of_set_vlan_pcp action, "
2732                                           "push VLAN action cannot figure out "
2733                                           "PCP value");
2734         if (vlan_m &&
2735             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2736             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2737                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2738             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2739             !(mlx5_flow_find_action
2740                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2741                 return rte_flow_error_set(error, EINVAL,
2742                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2743                                           "not full match mask on VLAN VID and "
2744                                           "there is no of_set_vlan_vid action, "
2745                                           "push VLAN action cannot figure out "
2746                                           "VID value");
2747         (void)attr;
2748         return 0;
2749 }
2750
2751 /**
2752  * Validate the set VLAN PCP.
2753  *
2754  * @param[in] action_flags
2755  *   Holds the actions detected until now.
2756  * @param[in] actions
2757  *   Pointer to the list of actions remaining in the flow rule.
2758  * @param[out] error
2759  *   Pointer to error structure.
2760  *
2761  * @return
2762  *   0 on success, a negative errno value otherwise and rte_errno is set.
2763  */
2764 static int
2765 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2766                                      const struct rte_flow_action actions[],
2767                                      struct rte_flow_error *error)
2768 {
2769         const struct rte_flow_action *action = actions;
2770         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2771
2772         if (conf->vlan_pcp > 7)
2773                 return rte_flow_error_set(error, EINVAL,
2774                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2775                                           "VLAN PCP value is too big");
2776         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2777                 return rte_flow_error_set(error, ENOTSUP,
2778                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2779                                           "set VLAN PCP action must follow "
2780                                           "the push VLAN action");
2781         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2782                 return rte_flow_error_set(error, ENOTSUP,
2783                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2784                                           "Multiple VLAN PCP modification are "
2785                                           "not supported");
2786         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2787                 return rte_flow_error_set(error, EINVAL,
2788                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2789                                           "wrong action order, port_id should "
2790                                           "be after set VLAN PCP");
2791         return 0;
2792 }
2793
2794 /**
2795  * Validate the set VLAN VID.
2796  *
2797  * @param[in] item_flags
2798  *   Holds the items detected in this rule.
2799  * @param[in] action_flags
2800  *   Holds the actions detected until now.
2801  * @param[in] actions
2802  *   Pointer to the list of actions remaining in the flow rule.
2803  * @param[out] error
2804  *   Pointer to error structure.
2805  *
2806  * @return
2807  *   0 on success, a negative errno value otherwise and rte_errno is set.
2808  */
2809 static int
2810 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2811                                      uint64_t action_flags,
2812                                      const struct rte_flow_action actions[],
2813                                      struct rte_flow_error *error)
2814 {
2815         const struct rte_flow_action *action = actions;
2816         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2817
2818         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2819                 return rte_flow_error_set(error, EINVAL,
2820                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2821                                           "VLAN VID value is too big");
2822         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2823             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2824                 return rte_flow_error_set(error, ENOTSUP,
2825                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2826                                           "set VLAN VID action must follow push"
2827                                           " VLAN action or match on VLAN item");
2828         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2829                 return rte_flow_error_set(error, ENOTSUP,
2830                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2831                                           "Multiple VLAN VID modifications are "
2832                                           "not supported");
2833         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2834                 return rte_flow_error_set(error, EINVAL,
2835                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2836                                           "wrong action order, port_id should "
2837                                           "be after set VLAN VID");
2838         return 0;
2839 }
2840
2841 /*
2842  * Validate the FLAG action.
2843  *
2844  * @param[in] dev
2845  *   Pointer to the rte_eth_dev structure.
2846  * @param[in] action_flags
2847  *   Holds the actions detected until now.
2848  * @param[in] attr
2849  *   Pointer to flow attributes
2850  * @param[out] error
2851  *   Pointer to error structure.
2852  *
2853  * @return
2854  *   0 on success, a negative errno value otherwise and rte_errno is set.
2855  */
2856 static int
2857 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2858                              uint64_t action_flags,
2859                              const struct rte_flow_attr *attr,
2860                              struct rte_flow_error *error)
2861 {
2862         struct mlx5_priv *priv = dev->data->dev_private;
2863         struct mlx5_dev_config *config = &priv->config;
2864         int ret;
2865
2866         /* Fall back if no extended metadata register support. */
2867         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2868                 return mlx5_flow_validate_action_flag(action_flags, attr,
2869                                                       error);
2870         /* Extensive metadata mode requires registers. */
2871         if (!mlx5_flow_ext_mreg_supported(dev))
2872                 return rte_flow_error_set(error, ENOTSUP,
2873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2874                                           "no metadata registers "
2875                                           "to support flag action");
2876         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2877                 return rte_flow_error_set(error, ENOTSUP,
2878                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2879                                           "extended metadata register"
2880                                           " isn't available");
2881         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2882         if (ret < 0)
2883                 return ret;
2884         MLX5_ASSERT(ret > 0);
2885         if (action_flags & MLX5_FLOW_ACTION_MARK)
2886                 return rte_flow_error_set(error, EINVAL,
2887                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2888                                           "can't mark and flag in same flow");
2889         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2890                 return rte_flow_error_set(error, EINVAL,
2891                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2892                                           "can't have 2 flag"
2893                                           " actions in same flow");
2894         return 0;
2895 }
2896
2897 /**
2898  * Validate MARK action.
2899  *
2900  * @param[in] dev
2901  *   Pointer to the rte_eth_dev structure.
2902  * @param[in] action
2903  *   Pointer to action.
2904  * @param[in] action_flags
2905  *   Holds the actions detected until now.
2906  * @param[in] attr
2907  *   Pointer to flow attributes
2908  * @param[out] error
2909  *   Pointer to error structure.
2910  *
2911  * @return
2912  *   0 on success, a negative errno value otherwise and rte_errno is set.
2913  */
2914 static int
2915 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2916                              const struct rte_flow_action *action,
2917                              uint64_t action_flags,
2918                              const struct rte_flow_attr *attr,
2919                              struct rte_flow_error *error)
2920 {
2921         struct mlx5_priv *priv = dev->data->dev_private;
2922         struct mlx5_dev_config *config = &priv->config;
2923         const struct rte_flow_action_mark *mark = action->conf;
2924         int ret;
2925
2926         if (is_tunnel_offload_active(dev))
2927                 return rte_flow_error_set(error, ENOTSUP,
2928                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2929                                           "no mark action "
2930                                           "if tunnel offload active");
2931         /* Fall back if no extended metadata register support. */
2932         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2933                 return mlx5_flow_validate_action_mark(action, action_flags,
2934                                                       attr, error);
2935         /* Extensive metadata mode requires registers. */
2936         if (!mlx5_flow_ext_mreg_supported(dev))
2937                 return rte_flow_error_set(error, ENOTSUP,
2938                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2939                                           "no metadata registers "
2940                                           "to support mark action");
2941         if (!priv->sh->dv_mark_mask)
2942                 return rte_flow_error_set(error, ENOTSUP,
2943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2944                                           "extended metadata register"
2945                                           " isn't available");
2946         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2947         if (ret < 0)
2948                 return ret;
2949         MLX5_ASSERT(ret > 0);
2950         if (!mark)
2951                 return rte_flow_error_set(error, EINVAL,
2952                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2953                                           "configuration cannot be null");
2954         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2955                 return rte_flow_error_set(error, EINVAL,
2956                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2957                                           &mark->id,
2958                                           "mark id exceeds the limit");
2959         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2960                 return rte_flow_error_set(error, EINVAL,
2961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2962                                           "can't flag and mark in same flow");
2963         if (action_flags & MLX5_FLOW_ACTION_MARK)
2964                 return rte_flow_error_set(error, EINVAL,
2965                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2966                                           "can't have 2 mark actions in same"
2967                                           " flow");
2968         return 0;
2969 }
2970
2971 /**
2972  * Validate SET_META action.
2973  *
2974  * @param[in] dev
2975  *   Pointer to the rte_eth_dev structure.
2976  * @param[in] action
2977  *   Pointer to the action structure.
2978  * @param[in] action_flags
2979  *   Holds the actions detected until now.
2980  * @param[in] attr
2981  *   Pointer to flow attributes
2982  * @param[out] error
2983  *   Pointer to error structure.
2984  *
2985  * @return
2986  *   0 on success, a negative errno value otherwise and rte_errno is set.
2987  */
2988 static int
2989 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2990                                  const struct rte_flow_action *action,
2991                                  uint64_t action_flags __rte_unused,
2992                                  const struct rte_flow_attr *attr,
2993                                  struct rte_flow_error *error)
2994 {
2995         const struct rte_flow_action_set_meta *conf;
2996         uint32_t nic_mask = UINT32_MAX;
2997         int reg;
2998
2999         if (!mlx5_flow_ext_mreg_supported(dev))
3000                 return rte_flow_error_set(error, ENOTSUP,
3001                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3002                                           "extended metadata register"
3003                                           " isn't supported");
3004         reg = flow_dv_get_metadata_reg(dev, attr, error);
3005         if (reg < 0)
3006                 return reg;
3007         if (reg == REG_NON)
3008                 return rte_flow_error_set(error, ENOTSUP,
3009                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3010                                           "unavalable extended metadata register");
3011         if (reg != REG_A && reg != REG_B) {
3012                 struct mlx5_priv *priv = dev->data->dev_private;
3013
3014                 nic_mask = priv->sh->dv_meta_mask;
3015         }
3016         if (!(action->conf))
3017                 return rte_flow_error_set(error, EINVAL,
3018                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3019                                           "configuration cannot be null");
3020         conf = (const struct rte_flow_action_set_meta *)action->conf;
3021         if (!conf->mask)
3022                 return rte_flow_error_set(error, EINVAL,
3023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3024                                           "zero mask doesn't have any effect");
3025         if (conf->mask & ~nic_mask)
3026                 return rte_flow_error_set(error, EINVAL,
3027                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3028                                           "meta data must be within reg C0");
3029         return 0;
3030 }
3031
3032 /**
3033  * Validate SET_TAG action.
3034  *
3035  * @param[in] dev
3036  *   Pointer to the rte_eth_dev structure.
3037  * @param[in] action
3038  *   Pointer to the action structure.
3039  * @param[in] action_flags
3040  *   Holds the actions detected until now.
3041  * @param[in] attr
3042  *   Pointer to flow attributes
3043  * @param[out] error
3044  *   Pointer to error structure.
3045  *
3046  * @return
3047  *   0 on success, a negative errno value otherwise and rte_errno is set.
3048  */
3049 static int
3050 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3051                                 const struct rte_flow_action *action,
3052                                 uint64_t action_flags,
3053                                 const struct rte_flow_attr *attr,
3054                                 struct rte_flow_error *error)
3055 {
3056         const struct rte_flow_action_set_tag *conf;
3057         const uint64_t terminal_action_flags =
3058                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3059                 MLX5_FLOW_ACTION_RSS;
3060         int ret;
3061
3062         if (!mlx5_flow_ext_mreg_supported(dev))
3063                 return rte_flow_error_set(error, ENOTSUP,
3064                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3065                                           "extensive metadata register"
3066                                           " isn't supported");
3067         if (!(action->conf))
3068                 return rte_flow_error_set(error, EINVAL,
3069                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3070                                           "configuration cannot be null");
3071         conf = (const struct rte_flow_action_set_tag *)action->conf;
3072         if (!conf->mask)
3073                 return rte_flow_error_set(error, EINVAL,
3074                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3075                                           "zero mask doesn't have any effect");
3076         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3077         if (ret < 0)
3078                 return ret;
3079         if (!attr->transfer && attr->ingress &&
3080             (action_flags & terminal_action_flags))
3081                 return rte_flow_error_set(error, EINVAL,
3082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3083                                           "set_tag has no effect"
3084                                           " with terminal actions");
3085         return 0;
3086 }
3087
3088 /**
3089  * Validate count action.
3090  *
3091  * @param[in] dev
3092  *   Pointer to rte_eth_dev structure.
3093  * @param[in] action
3094  *   Pointer to the action structure.
3095  * @param[in] action_flags
3096  *   Holds the actions detected until now.
3097  * @param[out] error
3098  *   Pointer to error structure.
3099  *
3100  * @return
3101  *   0 on success, a negative errno value otherwise and rte_errno is set.
3102  */
3103 static int
3104 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3105                               const struct rte_flow_action *action,
3106                               uint64_t action_flags,
3107                               struct rte_flow_error *error)
3108 {
3109         struct mlx5_priv *priv = dev->data->dev_private;
3110         const struct rte_flow_action_count *count;
3111
3112         if (!priv->config.devx)
3113                 goto notsup_err;
3114         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3115                 return rte_flow_error_set(error, EINVAL,
3116                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3117                                           "duplicate count actions set");
3118         count = (const struct rte_flow_action_count *)action->conf;
3119         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3120             !priv->sh->flow_hit_aso_en)
3121                 return rte_flow_error_set(error, EINVAL,
3122                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3123                                           "old age and shared count combination is not supported");
3124 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3125         return 0;
3126 #endif
3127 notsup_err:
3128         return rte_flow_error_set
3129                       (error, ENOTSUP,
3130                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3131                        NULL,
3132                        "count action not supported");
3133 }
3134
3135 /**
3136  * Validate the L2 encap action.
3137  *
3138  * @param[in] dev
3139  *   Pointer to the rte_eth_dev structure.
3140  * @param[in] action_flags
3141  *   Holds the actions detected until now.
3142  * @param[in] action
3143  *   Pointer to the action structure.
3144  * @param[in] attr
3145  *   Pointer to flow attributes.
3146  * @param[out] error
3147  *   Pointer to error structure.
3148  *
3149  * @return
3150  *   0 on success, a negative errno value otherwise and rte_errno is set.
3151  */
3152 static int
3153 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3154                                  uint64_t action_flags,
3155                                  const struct rte_flow_action *action,
3156                                  const struct rte_flow_attr *attr,
3157                                  struct rte_flow_error *error)
3158 {
3159         const struct mlx5_priv *priv = dev->data->dev_private;
3160
3161         if (!(action->conf))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3164                                           "configuration cannot be null");
3165         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3166                 return rte_flow_error_set(error, EINVAL,
3167                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3168                                           "can only have a single encap action "
3169                                           "in a flow");
3170         if (!attr->transfer && priv->representor)
3171                 return rte_flow_error_set(error, ENOTSUP,
3172                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173                                           "encap action for VF representor "
3174                                           "not supported on NIC table");
3175         return 0;
3176 }
3177
3178 /**
3179  * Validate a decap action.
3180  *
3181  * @param[in] dev
3182  *   Pointer to the rte_eth_dev structure.
3183  * @param[in] action_flags
3184  *   Holds the actions detected until now.
3185  * @param[in] action
3186  *   Pointer to the action structure.
3187  * @param[in] item_flags
3188  *   Holds the items detected.
3189  * @param[in] attr
3190  *   Pointer to flow attributes
3191  * @param[out] error
3192  *   Pointer to error structure.
3193  *
3194  * @return
3195  *   0 on success, a negative errno value otherwise and rte_errno is set.
3196  */
3197 static int
3198 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3199                               uint64_t action_flags,
3200                               const struct rte_flow_action *action,
3201                               const uint64_t item_flags,
3202                               const struct rte_flow_attr *attr,
3203                               struct rte_flow_error *error)
3204 {
3205         const struct mlx5_priv *priv = dev->data->dev_private;
3206
3207         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3208             !priv->config.decap_en)
3209                 return rte_flow_error_set(error, ENOTSUP,
3210                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3211                                           "decap is not enabled");
3212         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3213                 return rte_flow_error_set(error, ENOTSUP,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3215                                           action_flags &
3216                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3217                                           "have a single decap action" : "decap "
3218                                           "after encap is not supported");
3219         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3220                 return rte_flow_error_set(error, EINVAL,
3221                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3222                                           "can't have decap action after"
3223                                           " modify action");
3224         if (attr->egress)
3225                 return rte_flow_error_set(error, ENOTSUP,
3226                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3227                                           NULL,
3228                                           "decap action not supported for "
3229                                           "egress");
3230         if (!attr->transfer && priv->representor)
3231                 return rte_flow_error_set(error, ENOTSUP,
3232                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3233                                           "decap action for VF representor "
3234                                           "not supported on NIC table");
3235         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3236             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3237                 return rte_flow_error_set(error, ENOTSUP,
3238                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3239                                 "VXLAN item should be present for VXLAN decap");
3240         return 0;
3241 }
3242
3243 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3244
3245 /**
3246  * Validate the raw encap and decap actions.
3247  *
3248  * @param[in] dev
3249  *   Pointer to the rte_eth_dev structure.
3250  * @param[in] decap
3251  *   Pointer to the decap action.
3252  * @param[in] encap
3253  *   Pointer to the encap action.
3254  * @param[in] attr
3255  *   Pointer to flow attributes
3256  * @param[in/out] action_flags
3257  *   Holds the actions detected until now.
3258  * @param[out] actions_n
3259  *   pointer to the number of actions counter.
3260  * @param[in] action
3261  *   Pointer to the action structure.
3262  * @param[in] item_flags
3263  *   Holds the items detected.
3264  * @param[out] error
3265  *   Pointer to error structure.
3266  *
3267  * @return
3268  *   0 on success, a negative errno value otherwise and rte_errno is set.
3269  */
3270 static int
3271 flow_dv_validate_action_raw_encap_decap
3272         (struct rte_eth_dev *dev,
3273          const struct rte_flow_action_raw_decap *decap,
3274          const struct rte_flow_action_raw_encap *encap,
3275          const struct rte_flow_attr *attr, uint64_t *action_flags,
3276          int *actions_n, const struct rte_flow_action *action,
3277          uint64_t item_flags, struct rte_flow_error *error)
3278 {
3279         const struct mlx5_priv *priv = dev->data->dev_private;
3280         int ret;
3281
3282         if (encap && (!encap->size || !encap->data))
3283                 return rte_flow_error_set(error, EINVAL,
3284                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3285                                           "raw encap data cannot be empty");
3286         if (decap && encap) {
3287                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3288                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3289                         /* L3 encap. */
3290                         decap = NULL;
3291                 else if (encap->size <=
3292                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3293                            decap->size >
3294                            MLX5_ENCAPSULATION_DECISION_SIZE)
3295                         /* L3 decap. */
3296                         encap = NULL;
3297                 else if (encap->size >
3298                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3299                            decap->size >
3300                            MLX5_ENCAPSULATION_DECISION_SIZE)
3301                         /* 2 L2 actions: encap and decap. */
3302                         ;
3303                 else
3304                         return rte_flow_error_set(error,
3305                                 ENOTSUP,
3306                                 RTE_FLOW_ERROR_TYPE_ACTION,
3307                                 NULL, "unsupported too small "
3308                                 "raw decap and too small raw "
3309                                 "encap combination");
3310         }
3311         if (decap) {
3312                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3313                                                     item_flags, attr, error);
3314                 if (ret < 0)
3315                         return ret;
3316                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3317                 ++(*actions_n);
3318         }
3319         if (encap) {
3320                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3321                         return rte_flow_error_set(error, ENOTSUP,
3322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3323                                                   NULL,
3324                                                   "small raw encap size");
3325                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3326                         return rte_flow_error_set(error, EINVAL,
3327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3328                                                   NULL,
3329                                                   "more than one encap action");
3330                 if (!attr->transfer && priv->representor)
3331                         return rte_flow_error_set
3332                                         (error, ENOTSUP,
3333                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3334                                          "encap action for VF representor "
3335                                          "not supported on NIC table");
3336                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3337                 ++(*actions_n);
3338         }
3339         return 0;
3340 }
3341
3342 /**
3343  * Match encap_decap resource.
3344  *
3345  * @param list
3346  *   Pointer to the hash list.
3347  * @param entry
3348  *   Pointer to exist resource entry object.
3349  * @param key
3350  *   Key of the new entry.
3351  * @param ctx_cb
3352  *   Pointer to new encap_decap resource.
3353  *
3354  * @return
3355  *   0 on matching, none-zero otherwise.
3356  */
3357 int
3358 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3359                              struct mlx5_hlist_entry *entry,
3360                              uint64_t key __rte_unused, void *cb_ctx)
3361 {
3362         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3363         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3364         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3365
3366         cache_resource = container_of(entry,
3367                                       struct mlx5_flow_dv_encap_decap_resource,
3368                                       entry);
3369         if (resource->reformat_type == cache_resource->reformat_type &&
3370             resource->ft_type == cache_resource->ft_type &&
3371             resource->flags == cache_resource->flags &&
3372             resource->size == cache_resource->size &&
3373             !memcmp((const void *)resource->buf,
3374                     (const void *)cache_resource->buf,
3375                     resource->size))
3376                 return 0;
3377         return -1;
3378 }
3379
3380 /**
3381  * Allocate encap_decap resource.
3382  *
3383  * @param list
3384  *   Pointer to the hash list.
3385  * @param entry
3386  *   Pointer to exist resource entry object.
3387  * @param ctx_cb
3388  *   Pointer to new encap_decap resource.
3389  *
3390  * @return
3391  *   0 on matching, none-zero otherwise.
3392  */
3393 struct mlx5_hlist_entry *
3394 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3395                               uint64_t key __rte_unused,
3396                               void *cb_ctx)
3397 {
3398         struct mlx5_dev_ctx_shared *sh = list->ctx;
3399         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3400         struct mlx5dv_dr_domain *domain;
3401         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3402         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3403         uint32_t idx;
3404         int ret;
3405
3406         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3407                 domain = sh->fdb_domain;
3408         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3409                 domain = sh->rx_domain;
3410         else
3411                 domain = sh->tx_domain;
3412         /* Register new encap/decap resource. */
3413         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3414                                        &idx);
3415         if (!cache_resource) {
3416                 rte_flow_error_set(ctx->error, ENOMEM,
3417                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3418                                    "cannot allocate resource memory");
3419                 return NULL;
3420         }
3421         *cache_resource = *resource;
3422         cache_resource->idx = idx;
3423         ret = mlx5_flow_os_create_flow_action_packet_reformat
3424                                         (sh->ctx, domain, cache_resource,
3425                                          &cache_resource->action);
3426         if (ret) {
3427                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3428                 rte_flow_error_set(ctx->error, ENOMEM,
3429                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3430                                    NULL, "cannot create action");
3431                 return NULL;
3432         }
3433
3434         return &cache_resource->entry;
3435 }
3436
3437 /**
3438  * Find existing encap/decap resource or create and register a new one.
3439  *
3440  * @param[in, out] dev
3441  *   Pointer to rte_eth_dev structure.
3442  * @param[in, out] resource
3443  *   Pointer to encap/decap resource.
3444  * @parm[in, out] dev_flow
3445  *   Pointer to the dev_flow.
3446  * @param[out] error
3447  *   pointer to error structure.
3448  *
3449  * @return
3450  *   0 on success otherwise -errno and errno is set.
3451  */
3452 static int
3453 flow_dv_encap_decap_resource_register
3454                         (struct rte_eth_dev *dev,
3455                          struct mlx5_flow_dv_encap_decap_resource *resource,
3456                          struct mlx5_flow *dev_flow,
3457                          struct rte_flow_error *error)
3458 {
3459         struct mlx5_priv *priv = dev->data->dev_private;
3460         struct mlx5_dev_ctx_shared *sh = priv->sh;
3461         struct mlx5_hlist_entry *entry;
3462         union {
3463                 struct {
3464                         uint32_t ft_type:8;
3465                         uint32_t refmt_type:8;
3466                         /*
3467                          * Header reformat actions can be shared between
3468                          * non-root tables. One bit to indicate non-root
3469                          * table or not.
3470                          */
3471                         uint32_t is_root:1;
3472                         uint32_t reserve:15;
3473                 };
3474                 uint32_t v32;
3475         } encap_decap_key = {
3476                 {
3477                         .ft_type = resource->ft_type,
3478                         .refmt_type = resource->reformat_type,
3479                         .is_root = !!dev_flow->dv.group,
3480                         .reserve = 0,
3481                 }
3482         };
3483         struct mlx5_flow_cb_ctx ctx = {
3484                 .error = error,
3485                 .data = resource,
3486         };
3487         uint64_t key64;
3488
3489         resource->flags = dev_flow->dv.group ? 0 : 1;
3490         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3491                                  sizeof(encap_decap_key.v32), 0);
3492         if (resource->reformat_type !=
3493             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3494             resource->size)
3495                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3496         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3497         if (!entry)
3498                 return -rte_errno;
3499         resource = container_of(entry, typeof(*resource), entry);
3500         dev_flow->dv.encap_decap = resource;
3501         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3502         return 0;
3503 }
3504
3505 /**
3506  * Find existing table jump resource or create and register a new one.
3507  *
3508  * @param[in, out] dev
3509  *   Pointer to rte_eth_dev structure.
3510  * @param[in, out] tbl
3511  *   Pointer to flow table resource.
3512  * @parm[in, out] dev_flow
3513  *   Pointer to the dev_flow.
3514  * @param[out] error
3515  *   pointer to error structure.
3516  *
3517  * @return
3518  *   0 on success otherwise -errno and errno is set.
3519  */
3520 static int
3521 flow_dv_jump_tbl_resource_register
3522                         (struct rte_eth_dev *dev __rte_unused,
3523                          struct mlx5_flow_tbl_resource *tbl,
3524                          struct mlx5_flow *dev_flow,
3525                          struct rte_flow_error *error __rte_unused)
3526 {
3527         struct mlx5_flow_tbl_data_entry *tbl_data =
3528                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3529
3530         MLX5_ASSERT(tbl);
3531         MLX5_ASSERT(tbl_data->jump.action);
3532         dev_flow->handle->rix_jump = tbl_data->idx;
3533         dev_flow->dv.jump = &tbl_data->jump;
3534         return 0;
3535 }
3536
3537 int
3538 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3539                          struct mlx5_cache_entry *entry, void *cb_ctx)
3540 {
3541         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3542         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3543         struct mlx5_flow_dv_port_id_action_resource *res =
3544                         container_of(entry, typeof(*res), entry);
3545
3546         return ref->port_id != res->port_id;
3547 }
3548
3549 struct mlx5_cache_entry *
3550 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3551                           struct mlx5_cache_entry *entry __rte_unused,
3552                           void *cb_ctx)
3553 {
3554         struct mlx5_dev_ctx_shared *sh = list->ctx;
3555         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3556         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3557         struct mlx5_flow_dv_port_id_action_resource *cache;
3558         uint32_t idx;
3559         int ret;
3560
3561         /* Register new port id action resource. */
3562         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3563         if (!cache) {
3564                 rte_flow_error_set(ctx->error, ENOMEM,
3565                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3566                                    "cannot allocate port_id action cache memory");
3567                 return NULL;
3568         }
3569         *cache = *ref;
3570         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3571                                                         ref->port_id,
3572                                                         &cache->action);
3573         if (ret) {
3574                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3575                 rte_flow_error_set(ctx->error, ENOMEM,
3576                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3577                                    "cannot create action");
3578                 return NULL;
3579         }
3580         cache->idx = idx;
3581         return &cache->entry;
3582 }
3583
3584 /**
3585  * Find existing table port ID resource or create and register a new one.
3586  *
3587  * @param[in, out] dev
3588  *   Pointer to rte_eth_dev structure.
3589  * @param[in, out] resource
3590  *   Pointer to port ID action resource.
3591  * @parm[in, out] dev_flow
3592  *   Pointer to the dev_flow.
3593  * @param[out] error
3594  *   pointer to error structure.
3595  *
3596  * @return
3597  *   0 on success otherwise -errno and errno is set.
3598  */
3599 static int
3600 flow_dv_port_id_action_resource_register
3601                         (struct rte_eth_dev *dev,
3602                          struct mlx5_flow_dv_port_id_action_resource *resource,
3603                          struct mlx5_flow *dev_flow,
3604                          struct rte_flow_error *error)
3605 {
3606         struct mlx5_priv *priv = dev->data->dev_private;
3607         struct mlx5_cache_entry *entry;
3608         struct mlx5_flow_dv_port_id_action_resource *cache;
3609         struct mlx5_flow_cb_ctx ctx = {
3610                 .error = error,
3611                 .data = resource,
3612         };
3613
3614         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3615         if (!entry)
3616                 return -rte_errno;
3617         cache = container_of(entry, typeof(*cache), entry);
3618         dev_flow->dv.port_id_action = cache;
3619         dev_flow->handle->rix_port_id_action = cache->idx;
3620         return 0;
3621 }
3622
3623 int
3624 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3625                          struct mlx5_cache_entry *entry, void *cb_ctx)
3626 {
3627         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3628         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3629         struct mlx5_flow_dv_push_vlan_action_resource *res =
3630                         container_of(entry, typeof(*res), entry);
3631
3632         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3633 }
3634
3635 struct mlx5_cache_entry *
3636 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3637                           struct mlx5_cache_entry *entry __rte_unused,
3638                           void *cb_ctx)
3639 {
3640         struct mlx5_dev_ctx_shared *sh = list->ctx;
3641         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3642         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3643         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3644         struct mlx5dv_dr_domain *domain;
3645         uint32_t idx;
3646         int ret;
3647
3648         /* Register new port id action resource. */
3649         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3650         if (!cache) {
3651                 rte_flow_error_set(ctx->error, ENOMEM,
3652                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3653                                    "cannot allocate push_vlan action cache memory");
3654                 return NULL;
3655         }
3656         *cache = *ref;
3657         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3658                 domain = sh->fdb_domain;
3659         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3660                 domain = sh->rx_domain;
3661         else
3662                 domain = sh->tx_domain;
3663         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3664                                                         &cache->action);
3665         if (ret) {
3666                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3667                 rte_flow_error_set(ctx->error, ENOMEM,
3668                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3669                                    "cannot create push vlan action");
3670                 return NULL;
3671         }
3672         cache->idx = idx;
3673         return &cache->entry;
3674 }
3675
3676 /**
3677  * Find existing push vlan resource or create and register a new one.
3678  *
3679  * @param [in, out] dev
3680  *   Pointer to rte_eth_dev structure.
3681  * @param[in, out] resource
3682  *   Pointer to port ID action resource.
3683  * @parm[in, out] dev_flow
3684  *   Pointer to the dev_flow.
3685  * @param[out] error
3686  *   pointer to error structure.
3687  *
3688  * @return
3689  *   0 on success otherwise -errno and errno is set.
3690  */
3691 static int
3692 flow_dv_push_vlan_action_resource_register
3693                        (struct rte_eth_dev *dev,
3694                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3695                         struct mlx5_flow *dev_flow,
3696                         struct rte_flow_error *error)
3697 {
3698         struct mlx5_priv *priv = dev->data->dev_private;
3699         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3700         struct mlx5_cache_entry *entry;
3701         struct mlx5_flow_cb_ctx ctx = {
3702                 .error = error,
3703                 .data = resource,
3704         };
3705
3706         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3707         if (!entry)
3708                 return -rte_errno;
3709         cache = container_of(entry, typeof(*cache), entry);
3710
3711         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3712         dev_flow->dv.push_vlan_res = cache;
3713         return 0;
3714 }
3715
3716 /**
3717  * Get the size of specific rte_flow_item_type hdr size
3718  *
3719  * @param[in] item_type
3720  *   Tested rte_flow_item_type.
3721  *
3722  * @return
3723  *   sizeof struct item_type, 0 if void or irrelevant.
3724  */
3725 static size_t
3726 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3727 {
3728         size_t retval;
3729
3730         switch (item_type) {
3731         case RTE_FLOW_ITEM_TYPE_ETH:
3732                 retval = sizeof(struct rte_ether_hdr);
3733                 break;
3734         case RTE_FLOW_ITEM_TYPE_VLAN:
3735                 retval = sizeof(struct rte_vlan_hdr);
3736                 break;
3737         case RTE_FLOW_ITEM_TYPE_IPV4:
3738                 retval = sizeof(struct rte_ipv4_hdr);
3739                 break;
3740         case RTE_FLOW_ITEM_TYPE_IPV6:
3741                 retval = sizeof(struct rte_ipv6_hdr);
3742                 break;
3743         case RTE_FLOW_ITEM_TYPE_UDP:
3744                 retval = sizeof(struct rte_udp_hdr);
3745                 break;
3746         case RTE_FLOW_ITEM_TYPE_TCP:
3747                 retval = sizeof(struct rte_tcp_hdr);
3748                 break;
3749         case RTE_FLOW_ITEM_TYPE_VXLAN:
3750         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3751                 retval = sizeof(struct rte_vxlan_hdr);
3752                 break;
3753         case RTE_FLOW_ITEM_TYPE_GRE:
3754         case RTE_FLOW_ITEM_TYPE_NVGRE:
3755                 retval = sizeof(struct rte_gre_hdr);
3756                 break;
3757         case RTE_FLOW_ITEM_TYPE_MPLS:
3758                 retval = sizeof(struct rte_mpls_hdr);
3759                 break;
3760         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3761         default:
3762                 retval = 0;
3763                 break;
3764         }
3765         return retval;
3766 }
3767
3768 #define MLX5_ENCAP_IPV4_VERSION         0x40
3769 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3770 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3771 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3772 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3773 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3774 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3775
3776 /**
3777  * Convert the encap action data from list of rte_flow_item to raw buffer
3778  *
3779  * @param[in] items
3780  *   Pointer to rte_flow_item objects list.
3781  * @param[out] buf
3782  *   Pointer to the output buffer.
3783  * @param[out] size
3784  *   Pointer to the output buffer size.
3785  * @param[out] error
3786  *   Pointer to the error structure.
3787  *
3788  * @return
3789  *   0 on success, a negative errno value otherwise and rte_errno is set.
3790  */
3791 static int
3792 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3793                            size_t *size, struct rte_flow_error *error)
3794 {
3795         struct rte_ether_hdr *eth = NULL;
3796         struct rte_vlan_hdr *vlan = NULL;
3797         struct rte_ipv4_hdr *ipv4 = NULL;
3798         struct rte_ipv6_hdr *ipv6 = NULL;
3799         struct rte_udp_hdr *udp = NULL;
3800         struct rte_vxlan_hdr *vxlan = NULL;
3801         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3802         struct rte_gre_hdr *gre = NULL;
3803         size_t len;
3804         size_t temp_size = 0;
3805
3806         if (!items)
3807                 return rte_flow_error_set(error, EINVAL,
3808                                           RTE_FLOW_ERROR_TYPE_ACTION,
3809                                           NULL, "invalid empty data");
3810         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3811                 len = flow_dv_get_item_hdr_len(items->type);
3812                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3813                         return rte_flow_error_set(error, EINVAL,
3814                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3815                                                   (void *)items->type,
3816                                                   "items total size is too big"
3817                                                   " for encap action");
3818                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3819                 switch (items->type) {
3820                 case RTE_FLOW_ITEM_TYPE_ETH:
3821                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3822                         break;
3823                 case RTE_FLOW_ITEM_TYPE_VLAN:
3824                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3825                         if (!eth)
3826                                 return rte_flow_error_set(error, EINVAL,
3827                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3828                                                 (void *)items->type,
3829                                                 "eth header not found");
3830                         if (!eth->ether_type)
3831                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3832                         break;
3833                 case RTE_FLOW_ITEM_TYPE_IPV4:
3834                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3835                         if (!vlan && !eth)
3836                                 return rte_flow_error_set(error, EINVAL,
3837                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3838                                                 (void *)items->type,
3839                                                 "neither eth nor vlan"
3840                                                 " header found");
3841                         if (vlan && !vlan->eth_proto)
3842                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3843                         else if (eth && !eth->ether_type)
3844                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3845                         if (!ipv4->version_ihl)
3846                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3847                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3848                         if (!ipv4->time_to_live)
3849                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3850                         break;
3851                 case RTE_FLOW_ITEM_TYPE_IPV6:
3852                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3853                         if (!vlan && !eth)
3854                                 return rte_flow_error_set(error, EINVAL,
3855                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3856                                                 (void *)items->type,
3857                                                 "neither eth nor vlan"
3858                                                 " header found");
3859                         if (vlan && !vlan->eth_proto)
3860                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3861                         else if (eth && !eth->ether_type)
3862                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3863                         if (!ipv6->vtc_flow)
3864                                 ipv6->vtc_flow =
3865                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3866                         if (!ipv6->hop_limits)
3867                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3868                         break;
3869                 case RTE_FLOW_ITEM_TYPE_UDP:
3870                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3871                         if (!ipv4 && !ipv6)
3872                                 return rte_flow_error_set(error, EINVAL,
3873                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                 (void *)items->type,
3875                                                 "ip header not found");
3876                         if (ipv4 && !ipv4->next_proto_id)
3877                                 ipv4->next_proto_id = IPPROTO_UDP;
3878                         else if (ipv6 && !ipv6->proto)
3879                                 ipv6->proto = IPPROTO_UDP;
3880                         break;
3881                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3882                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3883                         if (!udp)
3884                                 return rte_flow_error_set(error, EINVAL,
3885                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                 (void *)items->type,
3887                                                 "udp header not found");
3888                         if (!udp->dst_port)
3889                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3890                         if (!vxlan->vx_flags)
3891                                 vxlan->vx_flags =
3892                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3893                         break;
3894                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3895                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3896                         if (!udp)
3897                                 return rte_flow_error_set(error, EINVAL,
3898                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3899                                                 (void *)items->type,
3900                                                 "udp header not found");
3901                         if (!vxlan_gpe->proto)
3902                                 return rte_flow_error_set(error, EINVAL,
3903                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3904                                                 (void *)items->type,
3905                                                 "next protocol not found");
3906                         if (!udp->dst_port)
3907                                 udp->dst_port =
3908                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3909                         if (!vxlan_gpe->vx_flags)
3910                                 vxlan_gpe->vx_flags =
3911                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3912                         break;
3913                 case RTE_FLOW_ITEM_TYPE_GRE:
3914                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3915                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3916                         if (!gre->proto)
3917                                 return rte_flow_error_set(error, EINVAL,
3918                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3919                                                 (void *)items->type,
3920                                                 "next protocol not found");
3921                         if (!ipv4 && !ipv6)
3922                                 return rte_flow_error_set(error, EINVAL,
3923                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3924                                                 (void *)items->type,
3925                                                 "ip header not found");
3926                         if (ipv4 && !ipv4->next_proto_id)
3927                                 ipv4->next_proto_id = IPPROTO_GRE;
3928                         else if (ipv6 && !ipv6->proto)
3929                                 ipv6->proto = IPPROTO_GRE;
3930                         break;
3931                 case RTE_FLOW_ITEM_TYPE_VOID:
3932                         break;
3933                 default:
3934                         return rte_flow_error_set(error, EINVAL,
3935                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3936                                                   (void *)items->type,
3937                                                   "unsupported item type");
3938                         break;
3939                 }
3940                 temp_size += len;
3941         }
3942         *size = temp_size;
3943         return 0;
3944 }
3945
3946 static int
3947 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3948 {
3949         struct rte_ether_hdr *eth = NULL;
3950         struct rte_vlan_hdr *vlan = NULL;
3951         struct rte_ipv6_hdr *ipv6 = NULL;
3952         struct rte_udp_hdr *udp = NULL;
3953         char *next_hdr;
3954         uint16_t proto;
3955
3956         eth = (struct rte_ether_hdr *)data;
3957         next_hdr = (char *)(eth + 1);
3958         proto = RTE_BE16(eth->ether_type);
3959
3960         /* VLAN skipping */
3961         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3962                 vlan = (struct rte_vlan_hdr *)next_hdr;
3963                 proto = RTE_BE16(vlan->eth_proto);
3964                 next_hdr += sizeof(struct rte_vlan_hdr);
3965         }
3966
3967         /* HW calculates IPv4 csum. no need to proceed */
3968         if (proto == RTE_ETHER_TYPE_IPV4)
3969                 return 0;
3970
3971         /* non IPv4/IPv6 header. not supported */
3972         if (proto != RTE_ETHER_TYPE_IPV6) {
3973                 return rte_flow_error_set(error, ENOTSUP,
3974                                           RTE_FLOW_ERROR_TYPE_ACTION,
3975                                           NULL, "Cannot offload non IPv4/IPv6");
3976         }
3977
3978         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3979
3980         /* ignore non UDP */
3981         if (ipv6->proto != IPPROTO_UDP)
3982                 return 0;
3983
3984         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3985         udp->dgram_cksum = 0;
3986
3987         return 0;
3988 }
3989
3990 /**
3991  * Convert L2 encap action to DV specification.
3992  *
3993  * @param[in] dev
3994  *   Pointer to rte_eth_dev structure.
3995  * @param[in] action
3996  *   Pointer to action structure.
3997  * @param[in, out] dev_flow
3998  *   Pointer to the mlx5_flow.
3999  * @param[in] transfer
4000  *   Mark if the flow is E-Switch flow.
4001  * @param[out] error
4002  *   Pointer to the error structure.
4003  *
4004  * @return
4005  *   0 on success, a negative errno value otherwise and rte_errno is set.
4006  */
4007 static int
4008 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4009                                const struct rte_flow_action *action,
4010                                struct mlx5_flow *dev_flow,
4011                                uint8_t transfer,
4012                                struct rte_flow_error *error)
4013 {
4014         const struct rte_flow_item *encap_data;
4015         const struct rte_flow_action_raw_encap *raw_encap_data;
4016         struct mlx5_flow_dv_encap_decap_resource res = {
4017                 .reformat_type =
4018                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4019                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4020                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4021         };
4022
4023         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4024                 raw_encap_data =
4025                         (const struct rte_flow_action_raw_encap *)action->conf;
4026                 res.size = raw_encap_data->size;
4027                 memcpy(res.buf, raw_encap_data->data, res.size);
4028         } else {
4029                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4030                         encap_data =
4031                                 ((const struct rte_flow_action_vxlan_encap *)
4032                                                 action->conf)->definition;
4033                 else
4034                         encap_data =
4035                                 ((const struct rte_flow_action_nvgre_encap *)
4036                                                 action->conf)->definition;
4037                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4038                                                &res.size, error))
4039                         return -rte_errno;
4040         }
4041         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4042                 return -rte_errno;
4043         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4044                 return rte_flow_error_set(error, EINVAL,
4045                                           RTE_FLOW_ERROR_TYPE_ACTION,
4046                                           NULL, "can't create L2 encap action");
4047         return 0;
4048 }
4049
4050 /**
4051  * Convert L2 decap action to DV specification.
4052  *
4053  * @param[in] dev
4054  *   Pointer to rte_eth_dev structure.
4055  * @param[in, out] dev_flow
4056  *   Pointer to the mlx5_flow.
4057  * @param[in] transfer
4058  *   Mark if the flow is E-Switch flow.
4059  * @param[out] error
4060  *   Pointer to the error structure.
4061  *
4062  * @return
4063  *   0 on success, a negative errno value otherwise and rte_errno is set.
4064  */
4065 static int
4066 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4067                                struct mlx5_flow *dev_flow,
4068                                uint8_t transfer,
4069                                struct rte_flow_error *error)
4070 {
4071         struct mlx5_flow_dv_encap_decap_resource res = {
4072                 .size = 0,
4073                 .reformat_type =
4074                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4075                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4076                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4077         };
4078
4079         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4080                 return rte_flow_error_set(error, EINVAL,
4081                                           RTE_FLOW_ERROR_TYPE_ACTION,
4082                                           NULL, "can't create L2 decap action");
4083         return 0;
4084 }
4085
4086 /**
4087  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4088  *
4089  * @param[in] dev
4090  *   Pointer to rte_eth_dev structure.
4091  * @param[in] action
4092  *   Pointer to action structure.
4093  * @param[in, out] dev_flow
4094  *   Pointer to the mlx5_flow.
4095  * @param[in] attr
4096  *   Pointer to the flow attributes.
4097  * @param[out] error
4098  *   Pointer to the error structure.
4099  *
4100  * @return
4101  *   0 on success, a negative errno value otherwise and rte_errno is set.
4102  */
4103 static int
4104 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4105                                 const struct rte_flow_action *action,
4106                                 struct mlx5_flow *dev_flow,
4107                                 const struct rte_flow_attr *attr,
4108                                 struct rte_flow_error *error)
4109 {
4110         const struct rte_flow_action_raw_encap *encap_data;
4111         struct mlx5_flow_dv_encap_decap_resource res;
4112
4113         memset(&res, 0, sizeof(res));
4114         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4115         res.size = encap_data->size;
4116         memcpy(res.buf, encap_data->data, res.size);
4117         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4118                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4119                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4120         if (attr->transfer)
4121                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4122         else
4123                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4124                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4125         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4126                 return rte_flow_error_set(error, EINVAL,
4127                                           RTE_FLOW_ERROR_TYPE_ACTION,
4128                                           NULL, "can't create encap action");
4129         return 0;
4130 }
4131
4132 /**
4133  * Create action push VLAN.
4134  *
4135  * @param[in] dev
4136  *   Pointer to rte_eth_dev structure.
4137  * @param[in] attr
4138  *   Pointer to the flow attributes.
4139  * @param[in] vlan
4140  *   Pointer to the vlan to push to the Ethernet header.
4141  * @param[in, out] dev_flow
4142  *   Pointer to the mlx5_flow.
4143  * @param[out] error
4144  *   Pointer to the error structure.
4145  *
4146  * @return
4147  *   0 on success, a negative errno value otherwise and rte_errno is set.
4148  */
4149 static int
4150 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4151                                 const struct rte_flow_attr *attr,
4152                                 const struct rte_vlan_hdr *vlan,
4153                                 struct mlx5_flow *dev_flow,
4154                                 struct rte_flow_error *error)
4155 {
4156         struct mlx5_flow_dv_push_vlan_action_resource res;
4157
4158         memset(&res, 0, sizeof(res));
4159         res.vlan_tag =
4160                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4161                                  vlan->vlan_tci);
4162         if (attr->transfer)
4163                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4164         else
4165                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4166                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4167         return flow_dv_push_vlan_action_resource_register
4168                                             (dev, &res, dev_flow, error);
4169 }
4170
4171 /**
4172  * Validate the modify-header actions.
4173  *
4174  * @param[in] action_flags
4175  *   Holds the actions detected until now.
4176  * @param[in] action
4177  *   Pointer to the modify action.
4178  * @param[out] error
4179  *   Pointer to error structure.
4180  *
4181  * @return
4182  *   0 on success, a negative errno value otherwise and rte_errno is set.
4183  */
4184 static int
4185 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4186                                    const struct rte_flow_action *action,
4187                                    struct rte_flow_error *error)
4188 {
4189         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4190                 return rte_flow_error_set(error, EINVAL,
4191                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4192                                           NULL, "action configuration not set");
4193         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4194                 return rte_flow_error_set(error, EINVAL,
4195                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4196                                           "can't have encap action before"
4197                                           " modify action");
4198         return 0;
4199 }
4200
4201 /**
4202  * Validate the modify-header MAC address actions.
4203  *
4204  * @param[in] action_flags
4205  *   Holds the actions detected until now.
4206  * @param[in] action
4207  *   Pointer to the modify action.
4208  * @param[in] item_flags
4209  *   Holds the items detected.
4210  * @param[out] error
4211  *   Pointer to error structure.
4212  *
4213  * @return
4214  *   0 on success, a negative errno value otherwise and rte_errno is set.
4215  */
4216 static int
4217 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4218                                    const struct rte_flow_action *action,
4219                                    const uint64_t item_flags,
4220                                    struct rte_flow_error *error)
4221 {
4222         int ret = 0;
4223
4224         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4225         if (!ret) {
4226                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4227                         return rte_flow_error_set(error, EINVAL,
4228                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4229                                                   NULL,
4230                                                   "no L2 item in pattern");
4231         }
4232         return ret;
4233 }
4234
4235 /**
4236  * Validate the modify-header IPv4 address actions.
4237  *
4238  * @param[in] action_flags
4239  *   Holds the actions detected until now.
4240  * @param[in] action
4241  *   Pointer to the modify action.
4242  * @param[in] item_flags
4243  *   Holds the items detected.
4244  * @param[out] error
4245  *   Pointer to error structure.
4246  *
4247  * @return
4248  *   0 on success, a negative errno value otherwise and rte_errno is set.
4249  */
4250 static int
4251 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4252                                     const struct rte_flow_action *action,
4253                                     const uint64_t item_flags,
4254                                     struct rte_flow_error *error)
4255 {
4256         int ret = 0;
4257         uint64_t layer;
4258
4259         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4260         if (!ret) {
4261                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4262                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4263                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4264                 if (!(item_flags & layer))
4265                         return rte_flow_error_set(error, EINVAL,
4266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4267                                                   NULL,
4268                                                   "no ipv4 item in pattern");
4269         }
4270         return ret;
4271 }
4272
4273 /**
4274  * Validate the modify-header IPv6 address actions.
4275  *
4276  * @param[in] action_flags
4277  *   Holds the actions detected until now.
4278  * @param[in] action
4279  *   Pointer to the modify action.
4280  * @param[in] item_flags
4281  *   Holds the items detected.
4282  * @param[out] error
4283  *   Pointer to error structure.
4284  *
4285  * @return
4286  *   0 on success, a negative errno value otherwise and rte_errno is set.
4287  */
4288 static int
4289 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4290                                     const struct rte_flow_action *action,
4291                                     const uint64_t item_flags,
4292                                     struct rte_flow_error *error)
4293 {
4294         int ret = 0;
4295         uint64_t layer;
4296
4297         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4298         if (!ret) {
4299                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4300                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4301                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4302                 if (!(item_flags & layer))
4303                         return rte_flow_error_set(error, EINVAL,
4304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4305                                                   NULL,
4306                                                   "no ipv6 item in pattern");
4307         }
4308         return ret;
4309 }
4310
4311 /**
4312  * Validate the modify-header TP actions.
4313  *
4314  * @param[in] action_flags
4315  *   Holds the actions detected until now.
4316  * @param[in] action
4317  *   Pointer to the modify action.
4318  * @param[in] item_flags
4319  *   Holds the items detected.
4320  * @param[out] error
4321  *   Pointer to error structure.
4322  *
4323  * @return
4324  *   0 on success, a negative errno value otherwise and rte_errno is set.
4325  */
4326 static int
4327 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4328                                   const struct rte_flow_action *action,
4329                                   const uint64_t item_flags,
4330                                   struct rte_flow_error *error)
4331 {
4332         int ret = 0;
4333         uint64_t layer;
4334
4335         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4336         if (!ret) {
4337                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4338                                  MLX5_FLOW_LAYER_INNER_L4 :
4339                                  MLX5_FLOW_LAYER_OUTER_L4;
4340                 if (!(item_flags & layer))
4341                         return rte_flow_error_set(error, EINVAL,
4342                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4343                                                   NULL, "no transport layer "
4344                                                   "in pattern");
4345         }
4346         return ret;
4347 }
4348
4349 /**
4350  * Validate the modify-header actions of increment/decrement
4351  * TCP Sequence-number.
4352  *
4353  * @param[in] action_flags
4354  *   Holds the actions detected until now.
4355  * @param[in] action
4356  *   Pointer to the modify action.
4357  * @param[in] item_flags
4358  *   Holds the items detected.
4359  * @param[out] error
4360  *   Pointer to error structure.
4361  *
4362  * @return
4363  *   0 on success, a negative errno value otherwise and rte_errno is set.
4364  */
4365 static int
4366 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4367                                        const struct rte_flow_action *action,
4368                                        const uint64_t item_flags,
4369                                        struct rte_flow_error *error)
4370 {
4371         int ret = 0;
4372         uint64_t layer;
4373
4374         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4375         if (!ret) {
4376                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4377                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4378                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4379                 if (!(item_flags & layer))
4380                         return rte_flow_error_set(error, EINVAL,
4381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4382                                                   NULL, "no TCP item in"
4383                                                   " pattern");
4384                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4385                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4386                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4387                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4388                         return rte_flow_error_set(error, EINVAL,
4389                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4390                                                   NULL,
4391                                                   "cannot decrease and increase"
4392                                                   " TCP sequence number"
4393                                                   " at the same time");
4394         }
4395         return ret;
4396 }
4397
4398 /**
4399  * Validate the modify-header actions of increment/decrement
4400  * TCP Acknowledgment number.
4401  *
4402  * @param[in] action_flags
4403  *   Holds the actions detected until now.
4404  * @param[in] action
4405  *   Pointer to the modify action.
4406  * @param[in] item_flags
4407  *   Holds the items detected.
4408  * @param[out] error
4409  *   Pointer to error structure.
4410  *
4411  * @return
4412  *   0 on success, a negative errno value otherwise and rte_errno is set.
4413  */
4414 static int
4415 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4416                                        const struct rte_flow_action *action,
4417                                        const uint64_t item_flags,
4418                                        struct rte_flow_error *error)
4419 {
4420         int ret = 0;
4421         uint64_t layer;
4422
4423         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4424         if (!ret) {
4425                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4426                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4427                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4428                 if (!(item_flags & layer))
4429                         return rte_flow_error_set(error, EINVAL,
4430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4431                                                   NULL, "no TCP item in"
4432                                                   " pattern");
4433                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4434                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4435                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4436                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4437                         return rte_flow_error_set(error, EINVAL,
4438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4439                                                   NULL,
4440                                                   "cannot decrease and increase"
4441                                                   " TCP acknowledgment number"
4442                                                   " at the same time");
4443         }
4444         return ret;
4445 }
4446
4447 /**
4448  * Validate the modify-header TTL actions.
4449  *
4450  * @param[in] action_flags
4451  *   Holds the actions detected until now.
4452  * @param[in] action
4453  *   Pointer to the modify action.
4454  * @param[in] item_flags
4455  *   Holds the items detected.
4456  * @param[out] error
4457  *   Pointer to error structure.
4458  *
4459  * @return
4460  *   0 on success, a negative errno value otherwise and rte_errno is set.
4461  */
4462 static int
4463 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4464                                    const struct rte_flow_action *action,
4465                                    const uint64_t item_flags,
4466                                    struct rte_flow_error *error)
4467 {
4468         int ret = 0;
4469         uint64_t layer;
4470
4471         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4472         if (!ret) {
4473                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4474                                  MLX5_FLOW_LAYER_INNER_L3 :
4475                                  MLX5_FLOW_LAYER_OUTER_L3;
4476                 if (!(item_flags & layer))
4477                         return rte_flow_error_set(error, EINVAL,
4478                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4479                                                   NULL,
4480                                                   "no IP protocol in pattern");
4481         }
4482         return ret;
4483 }
4484
4485 static int
4486 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4487 {
4488         switch (field) {
4489         case RTE_FLOW_FIELD_START:
4490                 return 32;
4491         case RTE_FLOW_FIELD_MAC_DST:
4492         case RTE_FLOW_FIELD_MAC_SRC:
4493                 return 48;
4494         case RTE_FLOW_FIELD_VLAN_TYPE:
4495                 return 16;
4496         case RTE_FLOW_FIELD_VLAN_ID:
4497                 return 12;
4498         case RTE_FLOW_FIELD_MAC_TYPE:
4499                 return 16;
4500         case RTE_FLOW_FIELD_IPV4_DSCP:
4501                 return 6;
4502         case RTE_FLOW_FIELD_IPV4_TTL:
4503                 return 8;
4504         case RTE_FLOW_FIELD_IPV4_SRC:
4505         case RTE_FLOW_FIELD_IPV4_DST:
4506                 return 32;
4507         case RTE_FLOW_FIELD_IPV6_DSCP:
4508                 return 6;
4509         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4510                 return 8;
4511         case RTE_FLOW_FIELD_IPV6_SRC:
4512         case RTE_FLOW_FIELD_IPV6_DST:
4513                 return 128;
4514         case RTE_FLOW_FIELD_TCP_PORT_SRC:
4515         case RTE_FLOW_FIELD_TCP_PORT_DST:
4516                 return 16;
4517         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4518         case RTE_FLOW_FIELD_TCP_ACK_NUM:
4519                 return 32;
4520         case RTE_FLOW_FIELD_TCP_FLAGS:
4521                 return 6;
4522         case RTE_FLOW_FIELD_UDP_PORT_SRC:
4523         case RTE_FLOW_FIELD_UDP_PORT_DST:
4524                 return 16;
4525         case RTE_FLOW_FIELD_VXLAN_VNI:
4526         case RTE_FLOW_FIELD_GENEVE_VNI:
4527                 return 24;
4528         case RTE_FLOW_FIELD_GTP_TEID:
4529         case RTE_FLOW_FIELD_TAG:
4530                 return 32;
4531         case RTE_FLOW_FIELD_MARK:
4532                 return 24;
4533         case RTE_FLOW_FIELD_META:
4534         case RTE_FLOW_FIELD_POINTER:
4535         case RTE_FLOW_FIELD_VALUE:
4536                 return 32;
4537         default:
4538                 MLX5_ASSERT(false);
4539         }
4540         return 0;
4541 }
4542
4543 /**
4544  * Validate the generic modify field actions.
4545  * @param[in] dev
4546  *   Pointer to the rte_eth_dev structure.
4547  * @param[in] action_flags
4548  *   Holds the actions detected until now.
4549  * @param[in] action
4550  *   Pointer to the modify action.
4551  * @param[in] attr
4552  *   Pointer to the flow attributes.
4553  * @param[out] error
4554  *   Pointer to error structure.
4555  *
4556  * @return
4557  *   Number of header fields to modify (0 or more) on success,
4558  *   a negative errno value otherwise and rte_errno is set.
4559  */
4560 static int
4561 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4562                                    const uint64_t action_flags,
4563                                    const struct rte_flow_action *action,
4564                                    const struct rte_flow_attr *attr,
4565                                    struct rte_flow_error *error)
4566 {
4567         int ret = 0;
4568         struct mlx5_priv *priv = dev->data->dev_private;
4569         struct mlx5_dev_config *config = &priv->config;
4570         const struct rte_flow_action_modify_field *action_modify_field =
4571                 action->conf;
4572         uint32_t dst_width =
4573                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4574         uint32_t src_width =
4575                 mlx5_flow_item_field_width(action_modify_field->src.field);
4576
4577         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4578         if (ret)
4579                 return ret;
4580
4581         if (action_modify_field->width == 0)
4582                 return rte_flow_error_set(error, EINVAL,
4583                                         RTE_FLOW_ERROR_TYPE_ACTION,
4584                                         NULL,
4585                                         "no bits are requested to be modified");
4586         else if (action_modify_field->width > dst_width ||
4587                  action_modify_field->width > src_width)
4588                 return rte_flow_error_set(error, EINVAL,
4589                                         RTE_FLOW_ERROR_TYPE_ACTION,
4590                                         NULL,
4591                                         "cannot modify more bits than"
4592                                         " the width of a field");
4593         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4594             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4595                 if ((action_modify_field->dst.offset +
4596                      action_modify_field->width > dst_width) ||
4597                     (action_modify_field->dst.offset % 32))
4598                         return rte_flow_error_set(error, EINVAL,
4599                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4600                                                 NULL,
4601                                                 "destination offset is too big"
4602                                                 " or not aligned to 4 bytes");
4603                 if (action_modify_field->dst.level &&
4604                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4605                         return rte_flow_error_set(error, EINVAL,
4606                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4607                                                 NULL,
4608                                                 "cannot modify inner headers");
4609         }
4610         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4611             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4612                 if (!attr->transfer && !attr->group)
4613                         return rte_flow_error_set(error, ENOTSUP,
4614                                         RTE_FLOW_ERROR_TYPE_ACTION,
4615                                         NULL, "modify field action "
4616                                         "is not supported for group 0");
4617                 if ((action_modify_field->src.offset +
4618                      action_modify_field->width > src_width) ||
4619                     (action_modify_field->src.offset % 32))
4620                         return rte_flow_error_set(error, EINVAL,
4621                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4622                                                 NULL,
4623                                                 "source offset is too big"
4624                                                 " or not aligned to 4 bytes");
4625                 if (action_modify_field->src.level &&
4626                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4627                         return rte_flow_error_set(error, EINVAL,
4628                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4629                                                 NULL,
4630                                                 "cannot copy from inner headers");
4631         }
4632         if (action_modify_field->dst.field ==
4633             action_modify_field->src.field)
4634                 return rte_flow_error_set(error, EINVAL,
4635                                         RTE_FLOW_ERROR_TYPE_ACTION,
4636                                         NULL,
4637                                         "source and destination fields"
4638                                         " cannot be the same");
4639         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4640             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4641                 return rte_flow_error_set(error, EINVAL,
4642                                         RTE_FLOW_ERROR_TYPE_ACTION,
4643                                         NULL,
4644                                         "immediate value or a pointer to it"
4645                                         " cannot be used as a destination");
4646         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4647             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4648                 return rte_flow_error_set(error, EINVAL,
4649                                 RTE_FLOW_ERROR_TYPE_ACTION,
4650                                 NULL,
4651                                 "modifications of an arbitrary"
4652                                 " place in a packet is not supported");
4653         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4654             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4655                 return rte_flow_error_set(error, EINVAL,
4656                                 RTE_FLOW_ERROR_TYPE_ACTION,
4657                                 NULL,
4658                                 "modifications of the 802.1Q Tag"
4659                                 " Identifier is not supported");
4660         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4661             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4662                 return rte_flow_error_set(error, EINVAL,
4663                                 RTE_FLOW_ERROR_TYPE_ACTION,
4664                                 NULL,
4665                                 "modifications of the VXLAN Network"
4666                                 " Identifier is not supported");
4667         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4668             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4669                 return rte_flow_error_set(error, EINVAL,
4670                                 RTE_FLOW_ERROR_TYPE_ACTION,
4671                                 NULL,
4672                                 "modifications of the GENEVE Network"
4673                                 " Identifier is not supported");
4674         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4675             action_modify_field->src.field == RTE_FLOW_FIELD_MARK) {
4676                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4677                     !mlx5_flow_ext_mreg_supported(dev))
4678                         return rte_flow_error_set(error, ENOTSUP,
4679                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4680                                         "cannot modify mark without extended"
4681                                         " metadata register support");
4682         }
4683         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4684                 return rte_flow_error_set(error, EINVAL,
4685                                 RTE_FLOW_ERROR_TYPE_ACTION,
4686                                 NULL,
4687                                 "add and sub operations"
4688                                 " are not supported");
4689         return (action_modify_field->width / 32) +
4690                !!(action_modify_field->width % 32);
4691 }
4692
4693 /**
4694  * Validate jump action.
4695  *
4696  * @param[in] action
4697  *   Pointer to the jump action.
4698  * @param[in] action_flags
4699  *   Holds the actions detected until now.
4700  * @param[in] attributes
4701  *   Pointer to flow attributes
4702  * @param[in] external
4703  *   Action belongs to flow rule created by request external to PMD.
4704  * @param[out] error
4705  *   Pointer to error structure.
4706  *
4707  * @return
4708  *   0 on success, a negative errno value otherwise and rte_errno is set.
4709  */
4710 static int
4711 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4712                              const struct mlx5_flow_tunnel *tunnel,
4713                              const struct rte_flow_action *action,
4714                              uint64_t action_flags,
4715                              const struct rte_flow_attr *attributes,
4716                              bool external, struct rte_flow_error *error)
4717 {
4718         uint32_t target_group, table;
4719         int ret = 0;
4720         struct flow_grp_info grp_info = {
4721                 .external = !!external,
4722                 .transfer = !!attributes->transfer,
4723                 .fdb_def_rule = 1,
4724                 .std_tbl_fix = 0
4725         };
4726         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4727                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4728                 return rte_flow_error_set(error, EINVAL,
4729                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4730                                           "can't have 2 fate actions in"
4731                                           " same flow");
4732         if (action_flags & MLX5_FLOW_ACTION_METER)
4733                 return rte_flow_error_set(error, ENOTSUP,
4734                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4735                                           "jump with meter not support");
4736         if (!action->conf)
4737                 return rte_flow_error_set(error, EINVAL,
4738                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4739                                           NULL, "action configuration not set");
4740         target_group =
4741                 ((const struct rte_flow_action_jump *)action->conf)->group;
4742         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4743                                        &grp_info, error);
4744         if (ret)
4745                 return ret;
4746         if (attributes->group == target_group &&
4747             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4748                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4749                 return rte_flow_error_set(error, EINVAL,
4750                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4751                                           "target group must be other than"
4752                                           " the current flow group");
4753         return 0;
4754 }
4755
4756 /*
4757  * Validate the port_id action.
4758  *
4759  * @param[in] dev
4760  *   Pointer to rte_eth_dev structure.
4761  * @param[in] action_flags
4762  *   Bit-fields that holds the actions detected until now.
4763  * @param[in] action
4764  *   Port_id RTE action structure.
4765  * @param[in] attr
4766  *   Attributes of flow that includes this action.
4767  * @param[out] error
4768  *   Pointer to error structure.
4769  *
4770  * @return
4771  *   0 on success, a negative errno value otherwise and rte_errno is set.
4772  */
4773 static int
4774 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4775                                 uint64_t action_flags,
4776                                 const struct rte_flow_action *action,
4777                                 const struct rte_flow_attr *attr,
4778                                 struct rte_flow_error *error)
4779 {
4780         const struct rte_flow_action_port_id *port_id;
4781         struct mlx5_priv *act_priv;
4782         struct mlx5_priv *dev_priv;
4783         uint16_t port;
4784
4785         if (!attr->transfer)
4786                 return rte_flow_error_set(error, ENOTSUP,
4787                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4788                                           NULL,
4789                                           "port id action is valid in transfer"
4790                                           " mode only");
4791         if (!action || !action->conf)
4792                 return rte_flow_error_set(error, ENOTSUP,
4793                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4794                                           NULL,
4795                                           "port id action parameters must be"
4796                                           " specified");
4797         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4798                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4799                 return rte_flow_error_set(error, EINVAL,
4800                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4801                                           "can have only one fate actions in"
4802                                           " a flow");
4803         dev_priv = mlx5_dev_to_eswitch_info(dev);
4804         if (!dev_priv)
4805                 return rte_flow_error_set(error, rte_errno,
4806                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4807                                           NULL,
4808                                           "failed to obtain E-Switch info");
4809         port_id = action->conf;
4810         port = port_id->original ? dev->data->port_id : port_id->id;
4811         act_priv = mlx5_port_to_eswitch_info(port, false);
4812         if (!act_priv)
4813                 return rte_flow_error_set
4814                                 (error, rte_errno,
4815                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4816                                  "failed to obtain E-Switch port id for port");
4817         if (act_priv->domain_id != dev_priv->domain_id)
4818                 return rte_flow_error_set
4819                                 (error, EINVAL,
4820                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4821                                  "port does not belong to"
4822                                  " E-Switch being configured");
4823         return 0;
4824 }
4825
4826 /**
4827  * Get the maximum number of modify header actions.
4828  *
4829  * @param dev
4830  *   Pointer to rte_eth_dev structure.
4831  * @param flags
4832  *   Flags bits to check if root level.
4833  *
4834  * @return
4835  *   Max number of modify header actions device can support.
4836  */
4837 static inline unsigned int
4838 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4839                               uint64_t flags)
4840 {
4841         /*
4842          * There's no way to directly query the max capacity from FW.
4843          * The maximal value on root table should be assumed to be supported.
4844          */
4845         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4846                 return MLX5_MAX_MODIFY_NUM;
4847         else
4848                 return MLX5_ROOT_TBL_MODIFY_NUM;
4849 }
4850
4851 /**
4852  * Validate the meter action.
4853  *
4854  * @param[in] dev
4855  *   Pointer to rte_eth_dev structure.
4856  * @param[in] action_flags
4857  *   Bit-fields that holds the actions detected until now.
4858  * @param[in] action
4859  *   Pointer to the meter action.
4860  * @param[in] attr
4861  *   Attributes of flow that includes this action.
4862  * @param[out] error
4863  *   Pointer to error structure.
4864  *
4865  * @return
4866  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4867  */
4868 static int
4869 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4870                                 uint64_t action_flags,
4871                                 const struct rte_flow_action *action,
4872                                 const struct rte_flow_attr *attr,
4873                                 struct rte_flow_error *error)
4874 {
4875         struct mlx5_priv *priv = dev->data->dev_private;
4876         const struct rte_flow_action_meter *am = action->conf;
4877         struct mlx5_flow_meter *fm;
4878
4879         if (!am)
4880                 return rte_flow_error_set(error, EINVAL,
4881                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4882                                           "meter action conf is NULL");
4883
4884         if (action_flags & MLX5_FLOW_ACTION_METER)
4885                 return rte_flow_error_set(error, ENOTSUP,
4886                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4887                                           "meter chaining not support");
4888         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4889                 return rte_flow_error_set(error, ENOTSUP,
4890                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4891                                           "meter with jump not support");
4892         if (!priv->mtr_en)
4893                 return rte_flow_error_set(error, ENOTSUP,
4894                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4895                                           NULL,
4896                                           "meter action not supported");
4897         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4898         if (!fm)
4899                 return rte_flow_error_set(error, EINVAL,
4900                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4901                                           "Meter not found");
4902         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4903               (!fm->ingress && !attr->ingress && attr->egress) ||
4904               (!fm->egress && !attr->egress && attr->ingress))))
4905                 return rte_flow_error_set(error, EINVAL,
4906                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4907                                           "Flow attributes are either invalid "
4908                                           "or have a conflict with current "
4909                                           "meter attributes");
4910         return 0;
4911 }
4912
4913 /**
4914  * Validate the age action.
4915  *
4916  * @param[in] action_flags
4917  *   Holds the actions detected until now.
4918  * @param[in] action
4919  *   Pointer to the age action.
4920  * @param[in] dev
4921  *   Pointer to the Ethernet device structure.
4922  * @param[out] error
4923  *   Pointer to error structure.
4924  *
4925  * @return
4926  *   0 on success, a negative errno value otherwise and rte_errno is set.
4927  */
4928 static int
4929 flow_dv_validate_action_age(uint64_t action_flags,
4930                             const struct rte_flow_action *action,
4931                             struct rte_eth_dev *dev,
4932                             struct rte_flow_error *error)
4933 {
4934         struct mlx5_priv *priv = dev->data->dev_private;
4935         const struct rte_flow_action_age *age = action->conf;
4936
4937         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4938             !priv->sh->aso_age_mng))
4939                 return rte_flow_error_set(error, ENOTSUP,
4940                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4941                                           NULL,
4942                                           "age action not supported");
4943         if (!(action->conf))
4944                 return rte_flow_error_set(error, EINVAL,
4945                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4946                                           "configuration cannot be null");
4947         if (!(age->timeout))
4948                 return rte_flow_error_set(error, EINVAL,
4949                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4950                                           "invalid timeout value 0");
4951         if (action_flags & MLX5_FLOW_ACTION_AGE)
4952                 return rte_flow_error_set(error, EINVAL,
4953                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4954                                           "duplicate age actions set");
4955         return 0;
4956 }
4957
4958 /**
4959  * Validate the modify-header IPv4 DSCP actions.
4960  *
4961  * @param[in] action_flags
4962  *   Holds the actions detected until now.
4963  * @param[in] action
4964  *   Pointer to the modify action.
4965  * @param[in] item_flags
4966  *   Holds the items detected.
4967  * @param[out] error
4968  *   Pointer to error structure.
4969  *
4970  * @return
4971  *   0 on success, a negative errno value otherwise and rte_errno is set.
4972  */
4973 static int
4974 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4975                                          const struct rte_flow_action *action,
4976                                          const uint64_t item_flags,
4977                                          struct rte_flow_error *error)
4978 {
4979         int ret = 0;
4980
4981         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4982         if (!ret) {
4983                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4984                         return rte_flow_error_set(error, EINVAL,
4985                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4986                                                   NULL,
4987                                                   "no ipv4 item in pattern");
4988         }
4989         return ret;
4990 }
4991
4992 /**
4993  * Validate the modify-header IPv6 DSCP actions.
4994  *
4995  * @param[in] action_flags
4996  *   Holds the actions detected until now.
4997  * @param[in] action
4998  *   Pointer to the modify action.
4999  * @param[in] item_flags
5000  *   Holds the items detected.
5001  * @param[out] error
5002  *   Pointer to error structure.
5003  *
5004  * @return
5005  *   0 on success, a negative errno value otherwise and rte_errno is set.
5006  */
5007 static int
5008 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5009                                          const struct rte_flow_action *action,
5010                                          const uint64_t item_flags,
5011                                          struct rte_flow_error *error)
5012 {
5013         int ret = 0;
5014
5015         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5016         if (!ret) {
5017                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5018                         return rte_flow_error_set(error, EINVAL,
5019                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5020                                                   NULL,
5021                                                   "no ipv6 item in pattern");
5022         }
5023         return ret;
5024 }
5025
5026 /**
5027  * Match modify-header resource.
5028  *
5029  * @param list
5030  *   Pointer to the hash list.
5031  * @param entry
5032  *   Pointer to exist resource entry object.
5033  * @param key
5034  *   Key of the new entry.
5035  * @param ctx
5036  *   Pointer to new modify-header resource.
5037  *
5038  * @return
5039  *   0 on matching, non-zero otherwise.
5040  */
5041 int
5042 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5043                         struct mlx5_hlist_entry *entry,
5044                         uint64_t key __rte_unused, void *cb_ctx)
5045 {
5046         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5047         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5048         struct mlx5_flow_dv_modify_hdr_resource *resource =
5049                         container_of(entry, typeof(*resource), entry);
5050         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5051
5052         key_len += ref->actions_num * sizeof(ref->actions[0]);
5053         return ref->actions_num != resource->actions_num ||
5054                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5055 }
5056
5057 struct mlx5_hlist_entry *
5058 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5059                          void *cb_ctx)
5060 {
5061         struct mlx5_dev_ctx_shared *sh = list->ctx;
5062         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5063         struct mlx5dv_dr_domain *ns;
5064         struct mlx5_flow_dv_modify_hdr_resource *entry;
5065         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5066         int ret;
5067         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5068         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5069
5070         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5071                             SOCKET_ID_ANY);
5072         if (!entry) {
5073                 rte_flow_error_set(ctx->error, ENOMEM,
5074                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5075                                    "cannot allocate resource memory");
5076                 return NULL;
5077         }
5078         rte_memcpy(&entry->ft_type,
5079                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5080                    key_len + data_len);
5081         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5082                 ns = sh->fdb_domain;
5083         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5084                 ns = sh->tx_domain;
5085         else
5086                 ns = sh->rx_domain;
5087         ret = mlx5_flow_os_create_flow_action_modify_header
5088                                         (sh->ctx, ns, entry,
5089                                          data_len, &entry->action);
5090         if (ret) {
5091                 mlx5_free(entry);
5092                 rte_flow_error_set(ctx->error, ENOMEM,
5093                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5094                                    NULL, "cannot create modification action");
5095                 return NULL;
5096         }
5097         return &entry->entry;
5098 }
5099
5100 /**
5101  * Validate the sample action.
5102  *
5103  * @param[in, out] action_flags
5104  *   Holds the actions detected until now.
5105  * @param[in] action
5106  *   Pointer to the sample action.
5107  * @param[in] dev
5108  *   Pointer to the Ethernet device structure.
5109  * @param[in] attr
5110  *   Attributes of flow that includes this action.
5111  * @param[in] item_flags
5112  *   Holds the items detected.
5113  * @param[in] rss
5114  *   Pointer to the RSS action.
5115  * @param[out] sample_rss
5116  *   Pointer to the RSS action in sample action list.
5117  * @param[out] count
5118  *   Pointer to the COUNT action in sample action list.
5119  * @param[out] fdb_mirror_limit
5120  *   Pointer to the FDB mirror limitation flag.
5121  * @param[out] error
5122  *   Pointer to error structure.
5123  *
5124  * @return
5125  *   0 on success, a negative errno value otherwise and rte_errno is set.
5126  */
5127 static int
5128 flow_dv_validate_action_sample(uint64_t *action_flags,
5129                                const struct rte_flow_action *action,
5130                                struct rte_eth_dev *dev,
5131                                const struct rte_flow_attr *attr,
5132                                uint64_t item_flags,
5133                                const struct rte_flow_action_rss *rss,
5134                                const struct rte_flow_action_rss **sample_rss,
5135                                const struct rte_flow_action_count **count,
5136                                int *fdb_mirror_limit,
5137                                struct rte_flow_error *error)
5138 {
5139         struct mlx5_priv *priv = dev->data->dev_private;
5140         struct mlx5_dev_config *dev_conf = &priv->config;
5141         const struct rte_flow_action_sample *sample = action->conf;
5142         const struct rte_flow_action *act;
5143         uint64_t sub_action_flags = 0;
5144         uint16_t queue_index = 0xFFFF;
5145         int actions_n = 0;
5146         int ret;
5147
5148         if (!sample)
5149                 return rte_flow_error_set(error, EINVAL,
5150                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5151                                           "configuration cannot be NULL");
5152         if (sample->ratio == 0)
5153                 return rte_flow_error_set(error, EINVAL,
5154                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5155                                           "ratio value starts from 1");
5156         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5157                 return rte_flow_error_set(error, ENOTSUP,
5158                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5159                                           NULL,
5160                                           "sample action not supported");
5161         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5162                 return rte_flow_error_set(error, EINVAL,
5163                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5164                                           "Multiple sample actions not "
5165                                           "supported");
5166         if (*action_flags & MLX5_FLOW_ACTION_METER)
5167                 return rte_flow_error_set(error, EINVAL,
5168                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5169                                           "wrong action order, meter should "
5170                                           "be after sample action");
5171         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5172                 return rte_flow_error_set(error, EINVAL,
5173                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5174                                           "wrong action order, jump should "
5175                                           "be after sample action");
5176         act = sample->actions;
5177         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5178                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5179                         return rte_flow_error_set(error, ENOTSUP,
5180                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5181                                                   act, "too many actions");
5182                 switch (act->type) {
5183                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5184                         ret = mlx5_flow_validate_action_queue(act,
5185                                                               sub_action_flags,
5186                                                               dev,
5187                                                               attr, error);
5188                         if (ret < 0)
5189                                 return ret;
5190                         queue_index = ((const struct rte_flow_action_queue *)
5191                                                         (act->conf))->index;
5192                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5193                         ++actions_n;
5194                         break;
5195                 case RTE_FLOW_ACTION_TYPE_RSS:
5196                         *sample_rss = act->conf;
5197                         ret = mlx5_flow_validate_action_rss(act,
5198                                                             sub_action_flags,
5199                                                             dev, attr,
5200                                                             item_flags,
5201                                                             error);
5202                         if (ret < 0)
5203                                 return ret;
5204                         if (rss && *sample_rss &&
5205                             ((*sample_rss)->level != rss->level ||
5206                             (*sample_rss)->types != rss->types))
5207                                 return rte_flow_error_set(error, ENOTSUP,
5208                                         RTE_FLOW_ERROR_TYPE_ACTION,
5209                                         NULL,
5210                                         "Can't use the different RSS types "
5211                                         "or level in the same flow");
5212                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5213                                 queue_index = (*sample_rss)->queue[0];
5214                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5215                         ++actions_n;
5216                         break;
5217                 case RTE_FLOW_ACTION_TYPE_MARK:
5218                         ret = flow_dv_validate_action_mark(dev, act,
5219                                                            sub_action_flags,
5220                                                            attr, error);
5221                         if (ret < 0)
5222                                 return ret;
5223                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5224                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5225                                                 MLX5_FLOW_ACTION_MARK_EXT;
5226                         else
5227                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5228                         ++actions_n;
5229                         break;
5230                 case RTE_FLOW_ACTION_TYPE_COUNT:
5231                         ret = flow_dv_validate_action_count
5232                                 (dev, act,
5233                                  *action_flags | sub_action_flags,
5234                                  error);
5235                         if (ret < 0)
5236                                 return ret;
5237                         *count = act->conf;
5238                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5239                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5240                         ++actions_n;
5241                         break;
5242                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5243                         ret = flow_dv_validate_action_port_id(dev,
5244                                                               sub_action_flags,
5245                                                               act,
5246                                                               attr,
5247                                                               error);
5248                         if (ret)
5249                                 return ret;
5250                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5251                         ++actions_n;
5252                         break;
5253                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5254                         ret = flow_dv_validate_action_raw_encap_decap
5255                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5256                                  &actions_n, action, item_flags, error);
5257                         if (ret < 0)
5258                                 return ret;
5259                         ++actions_n;
5260                         break;
5261                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5262                         ret = flow_dv_validate_action_l2_encap(dev,
5263                                                                sub_action_flags,
5264                                                                act, attr,
5265                                                                error);
5266                         if (ret < 0)
5267                                 return ret;
5268                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5269                         ++actions_n;
5270                         break;
5271                 default:
5272                         return rte_flow_error_set(error, ENOTSUP,
5273                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5274                                                   NULL,
5275                                                   "Doesn't support optional "
5276                                                   "action");
5277                 }
5278         }
5279         if (attr->ingress && !attr->transfer) {
5280                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5281                                           MLX5_FLOW_ACTION_RSS)))
5282                         return rte_flow_error_set(error, EINVAL,
5283                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5284                                                   NULL,
5285                                                   "Ingress must has a dest "
5286                                                   "QUEUE for Sample");
5287         } else if (attr->egress && !attr->transfer) {
5288                 return rte_flow_error_set(error, ENOTSUP,
5289                                           RTE_FLOW_ERROR_TYPE_ACTION,
5290                                           NULL,
5291                                           "Sample Only support Ingress "
5292                                           "or E-Switch");
5293         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5294                 MLX5_ASSERT(attr->transfer);
5295                 if (sample->ratio > 1)
5296                         return rte_flow_error_set(error, ENOTSUP,
5297                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5298                                                   NULL,
5299                                                   "E-Switch doesn't support "
5300                                                   "any optional action "
5301                                                   "for sampling");
5302                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5303                         return rte_flow_error_set(error, ENOTSUP,
5304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5305                                                   NULL,
5306                                                   "unsupported action QUEUE");
5307                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5308                         return rte_flow_error_set(error, ENOTSUP,
5309                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5310                                                   NULL,
5311                                                   "unsupported action QUEUE");
5312                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5313                         return rte_flow_error_set(error, EINVAL,
5314                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5315                                                   NULL,
5316                                                   "E-Switch must has a dest "
5317                                                   "port for mirroring");
5318                 if (!priv->config.hca_attr.reg_c_preserve &&
5319                      priv->representor_id != -1)
5320                         *fdb_mirror_limit = 1;
5321         }
5322         /* Continue validation for Xcap actions.*/
5323         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5324             (queue_index == 0xFFFF ||
5325              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5326                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5327                      MLX5_FLOW_XCAP_ACTIONS)
5328                         return rte_flow_error_set(error, ENOTSUP,
5329                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5330                                                   NULL, "encap and decap "
5331                                                   "combination aren't "
5332                                                   "supported");
5333                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5334                                                         MLX5_FLOW_ACTION_ENCAP))
5335                         return rte_flow_error_set(error, ENOTSUP,
5336                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5337                                                   NULL, "encap is not supported"
5338                                                   " for ingress traffic");
5339         }
5340         return 0;
5341 }
5342
5343 /**
5344  * Find existing modify-header resource or create and register a new one.
5345  *
5346  * @param dev[in, out]
5347  *   Pointer to rte_eth_dev structure.
5348  * @param[in, out] resource
5349  *   Pointer to modify-header resource.
5350  * @parm[in, out] dev_flow
5351  *   Pointer to the dev_flow.
5352  * @param[out] error
5353  *   pointer to error structure.
5354  *
5355  * @return
5356  *   0 on success otherwise -errno and errno is set.
5357  */
5358 static int
5359 flow_dv_modify_hdr_resource_register
5360                         (struct rte_eth_dev *dev,
5361                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5362                          struct mlx5_flow *dev_flow,
5363                          struct rte_flow_error *error)
5364 {
5365         struct mlx5_priv *priv = dev->data->dev_private;
5366         struct mlx5_dev_ctx_shared *sh = priv->sh;
5367         uint32_t key_len = sizeof(*resource) -
5368                            offsetof(typeof(*resource), ft_type) +
5369                            resource->actions_num * sizeof(resource->actions[0]);
5370         struct mlx5_hlist_entry *entry;
5371         struct mlx5_flow_cb_ctx ctx = {
5372                 .error = error,
5373                 .data = resource,
5374         };
5375         uint64_t key64;
5376
5377         resource->flags = dev_flow->dv.group ? 0 :
5378                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5379         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5380                                     resource->flags))
5381                 return rte_flow_error_set(error, EOVERFLOW,
5382                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5383                                           "too many modify header items");
5384         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5385         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5386         if (!entry)
5387                 return -rte_errno;
5388         resource = container_of(entry, typeof(*resource), entry);
5389         dev_flow->handle->dvh.modify_hdr = resource;
5390         return 0;
5391 }
5392
5393 /**
5394  * Get DV flow counter by index.
5395  *
5396  * @param[in] dev
5397  *   Pointer to the Ethernet device structure.
5398  * @param[in] idx
5399  *   mlx5 flow counter index in the container.
5400  * @param[out] ppool
5401  *   mlx5 flow counter pool in the container,
5402  *
5403  * @return
5404  *   Pointer to the counter, NULL otherwise.
5405  */
5406 static struct mlx5_flow_counter *
5407 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5408                            uint32_t idx,
5409                            struct mlx5_flow_counter_pool **ppool)
5410 {
5411         struct mlx5_priv *priv = dev->data->dev_private;
5412         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5413         struct mlx5_flow_counter_pool *pool;
5414
5415         /* Decrease to original index and clear shared bit. */
5416         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5417         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5418         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5419         MLX5_ASSERT(pool);
5420         if (ppool)
5421                 *ppool = pool;
5422         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5423 }
5424
5425 /**
5426  * Check the devx counter belongs to the pool.
5427  *
5428  * @param[in] pool
5429  *   Pointer to the counter pool.
5430  * @param[in] id
5431  *   The counter devx ID.
5432  *
5433  * @return
5434  *   True if counter belongs to the pool, false otherwise.
5435  */
5436 static bool
5437 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5438 {
5439         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5440                    MLX5_COUNTERS_PER_POOL;
5441
5442         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5443                 return true;
5444         return false;
5445 }
5446
5447 /**
5448  * Get a pool by devx counter ID.
5449  *
5450  * @param[in] cmng
5451  *   Pointer to the counter management.
5452  * @param[in] id
5453  *   The counter devx ID.
5454  *
5455  * @return
5456  *   The counter pool pointer if exists, NULL otherwise,
5457  */
5458 static struct mlx5_flow_counter_pool *
5459 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5460 {
5461         uint32_t i;
5462         struct mlx5_flow_counter_pool *pool = NULL;
5463
5464         rte_spinlock_lock(&cmng->pool_update_sl);
5465         /* Check last used pool. */
5466         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5467             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5468                 pool = cmng->pools[cmng->last_pool_idx];
5469                 goto out;
5470         }
5471         /* ID out of range means no suitable pool in the container. */
5472         if (id > cmng->max_id || id < cmng->min_id)
5473                 goto out;
5474         /*
5475          * Find the pool from the end of the container, since mostly counter
5476          * ID is sequence increasing, and the last pool should be the needed
5477          * one.
5478          */
5479         i = cmng->n_valid;
5480         while (i--) {
5481                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5482
5483                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5484                         pool = pool_tmp;
5485                         break;
5486                 }
5487         }
5488 out:
5489         rte_spinlock_unlock(&cmng->pool_update_sl);
5490         return pool;
5491 }
5492
5493 /**
5494  * Resize a counter container.
5495  *
5496  * @param[in] dev
5497  *   Pointer to the Ethernet device structure.
5498  *
5499  * @return
5500  *   0 on success, otherwise negative errno value and rte_errno is set.
5501  */
5502 static int
5503 flow_dv_container_resize(struct rte_eth_dev *dev)
5504 {
5505         struct mlx5_priv *priv = dev->data->dev_private;
5506         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5507         void *old_pools = cmng->pools;
5508         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5509         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5510         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5511
5512         if (!pools) {
5513                 rte_errno = ENOMEM;
5514                 return -ENOMEM;
5515         }
5516         if (old_pools)
5517                 memcpy(pools, old_pools, cmng->n *
5518                                        sizeof(struct mlx5_flow_counter_pool *));
5519         cmng->n = resize;
5520         cmng->pools = pools;
5521         if (old_pools)
5522                 mlx5_free(old_pools);
5523         return 0;
5524 }
5525
5526 /**
5527  * Query a devx flow counter.
5528  *
5529  * @param[in] dev
5530  *   Pointer to the Ethernet device structure.
5531  * @param[in] cnt
5532  *   Index to the flow counter.
5533  * @param[out] pkts
5534  *   The statistics value of packets.
5535  * @param[out] bytes
5536  *   The statistics value of bytes.
5537  *
5538  * @return
5539  *   0 on success, otherwise a negative errno value and rte_errno is set.
5540  */
5541 static inline int
5542 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5543                      uint64_t *bytes)
5544 {
5545         struct mlx5_priv *priv = dev->data->dev_private;
5546         struct mlx5_flow_counter_pool *pool = NULL;
5547         struct mlx5_flow_counter *cnt;
5548         int offset;
5549
5550         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5551         MLX5_ASSERT(pool);
5552         if (priv->sh->cmng.counter_fallback)
5553                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5554                                         0, pkts, bytes, 0, NULL, NULL, 0);
5555         rte_spinlock_lock(&pool->sl);
5556         if (!pool->raw) {
5557                 *pkts = 0;
5558                 *bytes = 0;
5559         } else {
5560                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5561                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5562                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5563         }
5564         rte_spinlock_unlock(&pool->sl);
5565         return 0;
5566 }
5567
5568 /**
5569  * Create and initialize a new counter pool.
5570  *
5571  * @param[in] dev
5572  *   Pointer to the Ethernet device structure.
5573  * @param[out] dcs
5574  *   The devX counter handle.
5575  * @param[in] age
5576  *   Whether the pool is for counter that was allocated for aging.
5577  * @param[in/out] cont_cur
5578  *   Pointer to the container pointer, it will be update in pool resize.
5579  *
5580  * @return
5581  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5582  */
5583 static struct mlx5_flow_counter_pool *
5584 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5585                     uint32_t age)
5586 {
5587         struct mlx5_priv *priv = dev->data->dev_private;
5588         struct mlx5_flow_counter_pool *pool;
5589         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5590         bool fallback = priv->sh->cmng.counter_fallback;
5591         uint32_t size = sizeof(*pool);
5592
5593         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5594         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5595         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5596         if (!pool) {
5597                 rte_errno = ENOMEM;
5598                 return NULL;
5599         }
5600         pool->raw = NULL;
5601         pool->is_aged = !!age;
5602         pool->query_gen = 0;
5603         pool->min_dcs = dcs;
5604         rte_spinlock_init(&pool->sl);
5605         rte_spinlock_init(&pool->csl);
5606         TAILQ_INIT(&pool->counters[0]);
5607         TAILQ_INIT(&pool->counters[1]);
5608         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5609         rte_spinlock_lock(&cmng->pool_update_sl);
5610         pool->index = cmng->n_valid;
5611         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5612                 mlx5_free(pool);
5613                 rte_spinlock_unlock(&cmng->pool_update_sl);
5614                 return NULL;
5615         }
5616         cmng->pools[pool->index] = pool;
5617         cmng->n_valid++;
5618         if (unlikely(fallback)) {
5619                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5620
5621                 if (base < cmng->min_id)
5622                         cmng->min_id = base;
5623                 if (base > cmng->max_id)
5624                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5625                 cmng->last_pool_idx = pool->index;
5626         }
5627         rte_spinlock_unlock(&cmng->pool_update_sl);
5628         return pool;
5629 }
5630
5631 /**
5632  * Prepare a new counter and/or a new counter pool.
5633  *
5634  * @param[in] dev
5635  *   Pointer to the Ethernet device structure.
5636  * @param[out] cnt_free
5637  *   Where to put the pointer of a new counter.
5638  * @param[in] age
5639  *   Whether the pool is for counter that was allocated for aging.
5640  *
5641  * @return
5642  *   The counter pool pointer and @p cnt_free is set on success,
5643  *   NULL otherwise and rte_errno is set.
5644  */
5645 static struct mlx5_flow_counter_pool *
5646 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5647                              struct mlx5_flow_counter **cnt_free,
5648                              uint32_t age)
5649 {
5650         struct mlx5_priv *priv = dev->data->dev_private;
5651         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5652         struct mlx5_flow_counter_pool *pool;
5653         struct mlx5_counters tmp_tq;
5654         struct mlx5_devx_obj *dcs = NULL;
5655         struct mlx5_flow_counter *cnt;
5656         enum mlx5_counter_type cnt_type =
5657                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5658         bool fallback = priv->sh->cmng.counter_fallback;
5659         uint32_t i;
5660
5661         if (fallback) {
5662                 /* bulk_bitmap must be 0 for single counter allocation. */
5663                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5664                 if (!dcs)
5665                         return NULL;
5666                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5667                 if (!pool) {
5668                         pool = flow_dv_pool_create(dev, dcs, age);
5669                         if (!pool) {
5670                                 mlx5_devx_cmd_destroy(dcs);
5671                                 return NULL;
5672                         }
5673                 }
5674                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5675                 cnt = MLX5_POOL_GET_CNT(pool, i);
5676                 cnt->pool = pool;
5677                 cnt->dcs_when_free = dcs;
5678                 *cnt_free = cnt;
5679                 return pool;
5680         }
5681         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5682         if (!dcs) {
5683                 rte_errno = ENODATA;
5684                 return NULL;
5685         }
5686         pool = flow_dv_pool_create(dev, dcs, age);
5687         if (!pool) {
5688                 mlx5_devx_cmd_destroy(dcs);
5689                 return NULL;
5690         }
5691         TAILQ_INIT(&tmp_tq);
5692         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5693                 cnt = MLX5_POOL_GET_CNT(pool, i);
5694                 cnt->pool = pool;
5695                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5696         }
5697         rte_spinlock_lock(&cmng->csl[cnt_type]);
5698         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5699         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5700         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5701         (*cnt_free)->pool = pool;
5702         return pool;
5703 }
5704
5705 /**
5706  * Allocate a flow counter.
5707  *
5708  * @param[in] dev
5709  *   Pointer to the Ethernet device structure.
5710  * @param[in] age
5711  *   Whether the counter was allocated for aging.
5712  *
5713  * @return
5714  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5715  */
5716 static uint32_t
5717 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5718 {
5719         struct mlx5_priv *priv = dev->data->dev_private;
5720         struct mlx5_flow_counter_pool *pool = NULL;
5721         struct mlx5_flow_counter *cnt_free = NULL;
5722         bool fallback = priv->sh->cmng.counter_fallback;
5723         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5724         enum mlx5_counter_type cnt_type =
5725                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5726         uint32_t cnt_idx;
5727
5728         if (!priv->config.devx) {
5729                 rte_errno = ENOTSUP;
5730                 return 0;
5731         }
5732         /* Get free counters from container. */
5733         rte_spinlock_lock(&cmng->csl[cnt_type]);
5734         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5735         if (cnt_free)
5736                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5737         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5738         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5739                 goto err;
5740         pool = cnt_free->pool;
5741         if (fallback)
5742                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5743         /* Create a DV counter action only in the first time usage. */
5744         if (!cnt_free->action) {
5745                 uint16_t offset;
5746                 struct mlx5_devx_obj *dcs;
5747                 int ret;
5748
5749                 if (!fallback) {
5750                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5751                         dcs = pool->min_dcs;
5752                 } else {
5753                         offset = 0;
5754                         dcs = cnt_free->dcs_when_free;
5755                 }
5756                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5757                                                             &cnt_free->action);
5758                 if (ret) {
5759                         rte_errno = errno;
5760                         goto err;
5761                 }
5762         }
5763         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5764                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5765         /* Update the counter reset values. */
5766         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5767                                  &cnt_free->bytes))
5768                 goto err;
5769         if (!fallback && !priv->sh->cmng.query_thread_on)
5770                 /* Start the asynchronous batch query by the host thread. */
5771                 mlx5_set_query_alarm(priv->sh);
5772         return cnt_idx;
5773 err:
5774         if (cnt_free) {
5775                 cnt_free->pool = pool;
5776                 if (fallback)
5777                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5778                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5779                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5780                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5781         }
5782         return 0;
5783 }
5784
5785 /**
5786  * Allocate a shared flow counter.
5787  *
5788  * @param[in] ctx
5789  *   Pointer to the shared counter configuration.
5790  * @param[in] data
5791  *   Pointer to save the allocated counter index.
5792  *
5793  * @return
5794  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5795  */
5796
5797 static int32_t
5798 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5799 {
5800         struct mlx5_shared_counter_conf *conf = ctx;
5801         struct rte_eth_dev *dev = conf->dev;
5802         struct mlx5_flow_counter *cnt;
5803
5804         data->dword = flow_dv_counter_alloc(dev, 0);
5805         data->dword |= MLX5_CNT_SHARED_OFFSET;
5806         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5807         cnt->shared_info.id = conf->id;
5808         return 0;
5809 }
5810
5811 /**
5812  * Get a shared flow counter.
5813  *
5814  * @param[in] dev
5815  *   Pointer to the Ethernet device structure.
5816  * @param[in] id
5817  *   Counter identifier.
5818  *
5819  * @return
5820  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5821  */
5822 static uint32_t
5823 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5824 {
5825         struct mlx5_priv *priv = dev->data->dev_private;
5826         struct mlx5_shared_counter_conf conf = {
5827                 .dev = dev,
5828                 .id = id,
5829         };
5830         union mlx5_l3t_data data = {
5831                 .dword = 0,
5832         };
5833
5834         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5835                                flow_dv_counter_alloc_shared_cb, &conf);
5836         return data.dword;
5837 }
5838
5839 /**
5840  * Get age param from counter index.
5841  *
5842  * @param[in] dev
5843  *   Pointer to the Ethernet device structure.
5844  * @param[in] counter
5845  *   Index to the counter handler.
5846  *
5847  * @return
5848  *   The aging parameter specified for the counter index.
5849  */
5850 static struct mlx5_age_param*
5851 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5852                                 uint32_t counter)
5853 {
5854         struct mlx5_flow_counter *cnt;
5855         struct mlx5_flow_counter_pool *pool = NULL;
5856
5857         flow_dv_counter_get_by_idx(dev, counter, &pool);
5858         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5859         cnt = MLX5_POOL_GET_CNT(pool, counter);
5860         return MLX5_CNT_TO_AGE(cnt);
5861 }
5862
5863 /**
5864  * Remove a flow counter from aged counter list.
5865  *
5866  * @param[in] dev
5867  *   Pointer to the Ethernet device structure.
5868  * @param[in] counter
5869  *   Index to the counter handler.
5870  * @param[in] cnt
5871  *   Pointer to the counter handler.
5872  */
5873 static void
5874 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5875                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5876 {
5877         struct mlx5_age_info *age_info;
5878         struct mlx5_age_param *age_param;
5879         struct mlx5_priv *priv = dev->data->dev_private;
5880         uint16_t expected = AGE_CANDIDATE;
5881
5882         age_info = GET_PORT_AGE_INFO(priv);
5883         age_param = flow_dv_counter_idx_get_age(dev, counter);
5884         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5885                                          AGE_FREE, false, __ATOMIC_RELAXED,
5886                                          __ATOMIC_RELAXED)) {
5887                 /**
5888                  * We need the lock even it is age timeout,
5889                  * since counter may still in process.
5890                  */
5891                 rte_spinlock_lock(&age_info->aged_sl);
5892                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5893                 rte_spinlock_unlock(&age_info->aged_sl);
5894                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5895         }
5896 }
5897
5898 /**
5899  * Release a flow counter.
5900  *
5901  * @param[in] dev
5902  *   Pointer to the Ethernet device structure.
5903  * @param[in] counter
5904  *   Index to the counter handler.
5905  */
5906 static void
5907 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5908 {
5909         struct mlx5_priv *priv = dev->data->dev_private;
5910         struct mlx5_flow_counter_pool *pool = NULL;
5911         struct mlx5_flow_counter *cnt;
5912         enum mlx5_counter_type cnt_type;
5913
5914         if (!counter)
5915                 return;
5916         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5917         MLX5_ASSERT(pool);
5918         if (IS_SHARED_CNT(counter) &&
5919             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5920                 return;
5921         if (pool->is_aged)
5922                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5923         cnt->pool = pool;
5924         /*
5925          * Put the counter back to list to be updated in none fallback mode.
5926          * Currently, we are using two list alternately, while one is in query,
5927          * add the freed counter to the other list based on the pool query_gen
5928          * value. After query finishes, add counter the list to the global
5929          * container counter list. The list changes while query starts. In
5930          * this case, lock will not be needed as query callback and release
5931          * function both operate with the different list.
5932          *
5933          */
5934         if (!priv->sh->cmng.counter_fallback) {
5935                 rte_spinlock_lock(&pool->csl);
5936                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5937                 rte_spinlock_unlock(&pool->csl);
5938         } else {
5939                 cnt->dcs_when_free = cnt->dcs_when_active;
5940                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5941                                            MLX5_COUNTER_TYPE_ORIGIN;
5942                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5943                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5944                                   cnt, next);
5945                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5946         }
5947 }
5948
5949 /**
5950  * Verify the @p attributes will be correctly understood by the NIC and store
5951  * them in the @p flow if everything is correct.
5952  *
5953  * @param[in] dev
5954  *   Pointer to dev struct.
5955  * @param[in] attributes
5956  *   Pointer to flow attributes
5957  * @param[in] external
5958  *   This flow rule is created by request external to PMD.
5959  * @param[out] error
5960  *   Pointer to error structure.
5961  *
5962  * @return
5963  *   - 0 on success and non root table.
5964  *   - 1 on success and root table.
5965  *   - a negative errno value otherwise and rte_errno is set.
5966  */
5967 static int
5968 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5969                             const struct mlx5_flow_tunnel *tunnel,
5970                             const struct rte_flow_attr *attributes,
5971                             const struct flow_grp_info *grp_info,
5972                             struct rte_flow_error *error)
5973 {
5974         struct mlx5_priv *priv = dev->data->dev_private;
5975         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5976         int ret = 0;
5977
5978 #ifndef HAVE_MLX5DV_DR
5979         RTE_SET_USED(tunnel);
5980         RTE_SET_USED(grp_info);
5981         if (attributes->group)
5982                 return rte_flow_error_set(error, ENOTSUP,
5983                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5984                                           NULL,
5985                                           "groups are not supported");
5986 #else
5987         uint32_t table = 0;
5988
5989         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5990                                        grp_info, error);
5991         if (ret)
5992                 return ret;
5993         if (!table)
5994                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5995 #endif
5996         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5997             attributes->priority > lowest_priority)
5998                 return rte_flow_error_set(error, ENOTSUP,
5999                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6000                                           NULL,
6001                                           "priority out of range");
6002         if (attributes->transfer) {
6003                 if (!priv->config.dv_esw_en)
6004                         return rte_flow_error_set
6005                                 (error, ENOTSUP,
6006                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6007                                  "E-Switch dr is not supported");
6008                 if (!(priv->representor || priv->master))
6009                         return rte_flow_error_set
6010                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6011                                  NULL, "E-Switch configuration can only be"
6012                                  " done by a master or a representor device");
6013                 if (attributes->egress)
6014                         return rte_flow_error_set
6015                                 (error, ENOTSUP,
6016                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6017                                  "egress is not supported");
6018         }
6019         if (!(attributes->egress ^ attributes->ingress))
6020                 return rte_flow_error_set(error, ENOTSUP,
6021                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6022                                           "must specify exactly one of "
6023                                           "ingress or egress");
6024         return ret;
6025 }
6026
6027 /**
6028  * Internal validation function. For validating both actions and items.
6029  *
6030  * @param[in] dev
6031  *   Pointer to the rte_eth_dev structure.
6032  * @param[in] attr
6033  *   Pointer to the flow attributes.
6034  * @param[in] items
6035  *   Pointer to the list of items.
6036  * @param[in] actions
6037  *   Pointer to the list of actions.
6038  * @param[in] external
6039  *   This flow rule is created by request external to PMD.
6040  * @param[in] hairpin
6041  *   Number of hairpin TX actions, 0 means classic flow.
6042  * @param[out] error
6043  *   Pointer to the error structure.
6044  *
6045  * @return
6046  *   0 on success, a negative errno value otherwise and rte_errno is set.
6047  */
6048 static int
6049 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6050                  const struct rte_flow_item items[],
6051                  const struct rte_flow_action actions[],
6052                  bool external, int hairpin, struct rte_flow_error *error)
6053 {
6054         int ret;
6055         uint64_t action_flags = 0;
6056         uint64_t item_flags = 0;
6057         uint64_t last_item = 0;
6058         uint8_t next_protocol = 0xff;
6059         uint16_t ether_type = 0;
6060         int actions_n = 0;
6061         uint8_t item_ipv6_proto = 0;
6062         int fdb_mirror_limit = 0;
6063         int modify_after_mirror = 0;
6064         const struct rte_flow_item *geneve_item = NULL;
6065         const struct rte_flow_item *gre_item = NULL;
6066         const struct rte_flow_item *gtp_item = NULL;
6067         const struct rte_flow_action_raw_decap *decap;
6068         const struct rte_flow_action_raw_encap *encap;
6069         const struct rte_flow_action_rss *rss = NULL;
6070         const struct rte_flow_action_rss *sample_rss = NULL;
6071         const struct rte_flow_action_count *count = NULL;
6072         const struct rte_flow_action_count *sample_count = NULL;
6073         const struct rte_flow_item_tcp nic_tcp_mask = {
6074                 .hdr = {
6075                         .tcp_flags = 0xFF,
6076                         .src_port = RTE_BE16(UINT16_MAX),
6077                         .dst_port = RTE_BE16(UINT16_MAX),
6078                 }
6079         };
6080         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6081                 .hdr = {
6082                         .src_addr =
6083                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6084                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6085                         .dst_addr =
6086                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6087                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6088                         .vtc_flow = RTE_BE32(0xffffffff),
6089                         .proto = 0xff,
6090                         .hop_limits = 0xff,
6091                 },
6092                 .has_frag_ext = 1,
6093         };
6094         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6095                 .hdr = {
6096                         .common = {
6097                                 .u32 =
6098                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6099                                         .type = 0xFF,
6100                                         }).u32),
6101                         },
6102                         .dummy[0] = 0xffffffff,
6103                 },
6104         };
6105         struct mlx5_priv *priv = dev->data->dev_private;
6106         struct mlx5_dev_config *dev_conf = &priv->config;
6107         uint16_t queue_index = 0xFFFF;
6108         const struct rte_flow_item_vlan *vlan_m = NULL;
6109         uint32_t rw_act_num = 0;
6110         uint64_t is_root;
6111         const struct mlx5_flow_tunnel *tunnel;
6112         struct flow_grp_info grp_info = {
6113                 .external = !!external,
6114                 .transfer = !!attr->transfer,
6115                 .fdb_def_rule = !!priv->fdb_def_rule,
6116         };
6117         const struct rte_eth_hairpin_conf *conf;
6118
6119         if (items == NULL)
6120                 return -1;
6121         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6122                 tunnel = flow_items_to_tunnel(items);
6123                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6124                                 MLX5_FLOW_ACTION_DECAP;
6125         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6126                 tunnel = flow_actions_to_tunnel(actions);
6127                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6128         } else {
6129                 tunnel = NULL;
6130         }
6131         if (tunnel && priv->representor)
6132                 return rte_flow_error_set(error, ENOTSUP,
6133                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6134                                           "decap not supported "
6135                                           "for VF representor");
6136         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6137                                 (dev, tunnel, attr, items, actions);
6138         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6139         if (ret < 0)
6140                 return ret;
6141         is_root = (uint64_t)ret;
6142         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6143                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6144                 int type = items->type;
6145
6146                 if (!mlx5_flow_os_item_supported(type))
6147                         return rte_flow_error_set(error, ENOTSUP,
6148                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6149                                                   NULL, "item not supported");
6150                 switch (type) {
6151                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6152                         if (items[0].type != (typeof(items[0].type))
6153                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6154                                 return rte_flow_error_set
6155                                                 (error, EINVAL,
6156                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6157                                                 NULL, "MLX5 private items "
6158                                                 "must be the first");
6159                         break;
6160                 case RTE_FLOW_ITEM_TYPE_VOID:
6161                         break;
6162                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6163                         ret = flow_dv_validate_item_port_id
6164                                         (dev, items, attr, item_flags, error);
6165                         if (ret < 0)
6166                                 return ret;
6167                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6168                         break;
6169                 case RTE_FLOW_ITEM_TYPE_ETH:
6170                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6171                                                           true, error);
6172                         if (ret < 0)
6173                                 return ret;
6174                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6175                                              MLX5_FLOW_LAYER_OUTER_L2;
6176                         if (items->mask != NULL && items->spec != NULL) {
6177                                 ether_type =
6178                                         ((const struct rte_flow_item_eth *)
6179                                          items->spec)->type;
6180                                 ether_type &=
6181                                         ((const struct rte_flow_item_eth *)
6182                                          items->mask)->type;
6183                                 ether_type = rte_be_to_cpu_16(ether_type);
6184                         } else {
6185                                 ether_type = 0;
6186                         }
6187                         break;
6188                 case RTE_FLOW_ITEM_TYPE_VLAN:
6189                         ret = flow_dv_validate_item_vlan(items, item_flags,
6190                                                          dev, error);
6191                         if (ret < 0)
6192                                 return ret;
6193                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6194                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6195                         if (items->mask != NULL && items->spec != NULL) {
6196                                 ether_type =
6197                                         ((const struct rte_flow_item_vlan *)
6198                                          items->spec)->inner_type;
6199                                 ether_type &=
6200                                         ((const struct rte_flow_item_vlan *)
6201                                          items->mask)->inner_type;
6202                                 ether_type = rte_be_to_cpu_16(ether_type);
6203                         } else {
6204                                 ether_type = 0;
6205                         }
6206                         /* Store outer VLAN mask for of_push_vlan action. */
6207                         if (!tunnel)
6208                                 vlan_m = items->mask;
6209                         break;
6210                 case RTE_FLOW_ITEM_TYPE_IPV4:
6211                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6212                                                   &item_flags, &tunnel);
6213                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6214                                                          last_item, ether_type,
6215                                                          error);
6216                         if (ret < 0)
6217                                 return ret;
6218                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6219                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6220                         if (items->mask != NULL &&
6221                             ((const struct rte_flow_item_ipv4 *)
6222                              items->mask)->hdr.next_proto_id) {
6223                                 next_protocol =
6224                                         ((const struct rte_flow_item_ipv4 *)
6225                                          (items->spec))->hdr.next_proto_id;
6226                                 next_protocol &=
6227                                         ((const struct rte_flow_item_ipv4 *)
6228                                          (items->mask))->hdr.next_proto_id;
6229                         } else {
6230                                 /* Reset for inner layer. */
6231                                 next_protocol = 0xff;
6232                         }
6233                         break;
6234                 case RTE_FLOW_ITEM_TYPE_IPV6:
6235                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6236                                                   &item_flags, &tunnel);
6237                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6238                                                            last_item,
6239                                                            ether_type,
6240                                                            &nic_ipv6_mask,
6241                                                            error);
6242                         if (ret < 0)
6243                                 return ret;
6244                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6245                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6246                         if (items->mask != NULL &&
6247                             ((const struct rte_flow_item_ipv6 *)
6248                              items->mask)->hdr.proto) {
6249                                 item_ipv6_proto =
6250                                         ((const struct rte_flow_item_ipv6 *)
6251                                          items->spec)->hdr.proto;
6252                                 next_protocol =
6253                                         ((const struct rte_flow_item_ipv6 *)
6254                                          items->spec)->hdr.proto;
6255                                 next_protocol &=
6256                                         ((const struct rte_flow_item_ipv6 *)
6257                                          items->mask)->hdr.proto;
6258                         } else {
6259                                 /* Reset for inner layer. */
6260                                 next_protocol = 0xff;
6261                         }
6262                         break;
6263                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6264                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6265                                                                   item_flags,
6266                                                                   error);
6267                         if (ret < 0)
6268                                 return ret;
6269                         last_item = tunnel ?
6270                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6271                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6272                         if (items->mask != NULL &&
6273                             ((const struct rte_flow_item_ipv6_frag_ext *)
6274                              items->mask)->hdr.next_header) {
6275                                 next_protocol =
6276                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6277                                  items->spec)->hdr.next_header;
6278                                 next_protocol &=
6279                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6280                                  items->mask)->hdr.next_header;
6281                         } else {
6282                                 /* Reset for inner layer. */
6283                                 next_protocol = 0xff;
6284                         }
6285                         break;
6286                 case RTE_FLOW_ITEM_TYPE_TCP:
6287                         ret = mlx5_flow_validate_item_tcp
6288                                                 (items, item_flags,
6289                                                  next_protocol,
6290                                                  &nic_tcp_mask,
6291                                                  error);
6292                         if (ret < 0)
6293                                 return ret;
6294                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6295                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6296                         break;
6297                 case RTE_FLOW_ITEM_TYPE_UDP:
6298                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6299                                                           next_protocol,
6300                                                           error);
6301                         if (ret < 0)
6302                                 return ret;
6303                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6304                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6305                         break;
6306                 case RTE_FLOW_ITEM_TYPE_GRE:
6307                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6308                                                           next_protocol, error);
6309                         if (ret < 0)
6310                                 return ret;
6311                         gre_item = items;
6312                         last_item = MLX5_FLOW_LAYER_GRE;
6313                         break;
6314                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6315                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6316                                                             next_protocol,
6317                                                             error);
6318                         if (ret < 0)
6319                                 return ret;
6320                         last_item = MLX5_FLOW_LAYER_NVGRE;
6321                         break;
6322                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6323                         ret = mlx5_flow_validate_item_gre_key
6324                                 (items, item_flags, gre_item, error);
6325                         if (ret < 0)
6326                                 return ret;
6327                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6328                         break;
6329                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6330                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6331                                                             error);
6332                         if (ret < 0)
6333                                 return ret;
6334                         last_item = MLX5_FLOW_LAYER_VXLAN;
6335                         break;
6336                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6337                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6338                                                                 item_flags, dev,
6339                                                                 error);
6340                         if (ret < 0)
6341                                 return ret;
6342                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6343                         break;
6344                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6345                         ret = mlx5_flow_validate_item_geneve(items,
6346                                                              item_flags, dev,
6347                                                              error);
6348                         if (ret < 0)
6349                                 return ret;
6350                         geneve_item = items;
6351                         last_item = MLX5_FLOW_LAYER_GENEVE;
6352                         break;
6353                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6354                         ret = mlx5_flow_validate_item_geneve_opt(items,
6355                                                                  last_item,
6356                                                                  geneve_item,
6357                                                                  dev,
6358                                                                  error);
6359                         if (ret < 0)
6360                                 return ret;
6361                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6362                         break;
6363                 case RTE_FLOW_ITEM_TYPE_MPLS:
6364                         ret = mlx5_flow_validate_item_mpls(dev, items,
6365                                                            item_flags,
6366                                                            last_item, error);
6367                         if (ret < 0)
6368                                 return ret;
6369                         last_item = MLX5_FLOW_LAYER_MPLS;
6370                         break;
6371
6372                 case RTE_FLOW_ITEM_TYPE_MARK:
6373                         ret = flow_dv_validate_item_mark(dev, items, attr,
6374                                                          error);
6375                         if (ret < 0)
6376                                 return ret;
6377                         last_item = MLX5_FLOW_ITEM_MARK;
6378                         break;
6379                 case RTE_FLOW_ITEM_TYPE_META:
6380                         ret = flow_dv_validate_item_meta(dev, items, attr,
6381                                                          error);
6382                         if (ret < 0)
6383                                 return ret;
6384                         last_item = MLX5_FLOW_ITEM_METADATA;
6385                         break;
6386                 case RTE_FLOW_ITEM_TYPE_ICMP:
6387                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6388                                                            next_protocol,
6389                                                            error);
6390                         if (ret < 0)
6391                                 return ret;
6392                         last_item = MLX5_FLOW_LAYER_ICMP;
6393                         break;
6394                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6395                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6396                                                             next_protocol,
6397                                                             error);
6398                         if (ret < 0)
6399                                 return ret;
6400                         item_ipv6_proto = IPPROTO_ICMPV6;
6401                         last_item = MLX5_FLOW_LAYER_ICMP6;
6402                         break;
6403                 case RTE_FLOW_ITEM_TYPE_TAG:
6404                         ret = flow_dv_validate_item_tag(dev, items,
6405                                                         attr, error);
6406                         if (ret < 0)
6407                                 return ret;
6408                         last_item = MLX5_FLOW_ITEM_TAG;
6409                         break;
6410                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6411                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6412                         break;
6413                 case RTE_FLOW_ITEM_TYPE_GTP:
6414                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6415                                                         error);
6416                         if (ret < 0)
6417                                 return ret;
6418                         gtp_item = items;
6419                         last_item = MLX5_FLOW_LAYER_GTP;
6420                         break;
6421                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6422                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6423                                                             gtp_item, attr,
6424                                                             error);
6425                         if (ret < 0)
6426                                 return ret;
6427                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6428                         break;
6429                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6430                         /* Capacity will be checked in the translate stage. */
6431                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6432                                                             last_item,
6433                                                             ether_type,
6434                                                             &nic_ecpri_mask,
6435                                                             error);
6436                         if (ret < 0)
6437                                 return ret;
6438                         last_item = MLX5_FLOW_LAYER_ECPRI;
6439                         break;
6440                 default:
6441                         return rte_flow_error_set(error, ENOTSUP,
6442                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6443                                                   NULL, "item not supported");
6444                 }
6445                 item_flags |= last_item;
6446         }
6447         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6448                 int type = actions->type;
6449
6450                 if (!mlx5_flow_os_action_supported(type))
6451                         return rte_flow_error_set(error, ENOTSUP,
6452                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6453                                                   actions,
6454                                                   "action not supported");
6455                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6456                         return rte_flow_error_set(error, ENOTSUP,
6457                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6458                                                   actions, "too many actions");
6459                 switch (type) {
6460                 case RTE_FLOW_ACTION_TYPE_VOID:
6461                         break;
6462                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6463                         ret = flow_dv_validate_action_port_id(dev,
6464                                                               action_flags,
6465                                                               actions,
6466                                                               attr,
6467                                                               error);
6468                         if (ret)
6469                                 return ret;
6470                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6471                         ++actions_n;
6472                         break;
6473                 case RTE_FLOW_ACTION_TYPE_FLAG:
6474                         ret = flow_dv_validate_action_flag(dev, action_flags,
6475                                                            attr, error);
6476                         if (ret < 0)
6477                                 return ret;
6478                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6479                                 /* Count all modify-header actions as one. */
6480                                 if (!(action_flags &
6481                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6482                                         ++actions_n;
6483                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6484                                                 MLX5_FLOW_ACTION_MARK_EXT;
6485                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6486                                         modify_after_mirror = 1;
6487
6488                         } else {
6489                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6490                                 ++actions_n;
6491                         }
6492                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6493                         break;
6494                 case RTE_FLOW_ACTION_TYPE_MARK:
6495                         ret = flow_dv_validate_action_mark(dev, actions,
6496                                                            action_flags,
6497                                                            attr, error);
6498                         if (ret < 0)
6499                                 return ret;
6500                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6501                                 /* Count all modify-header actions as one. */
6502                                 if (!(action_flags &
6503                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6504                                         ++actions_n;
6505                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6506                                                 MLX5_FLOW_ACTION_MARK_EXT;
6507                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6508                                         modify_after_mirror = 1;
6509                         } else {
6510                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6511                                 ++actions_n;
6512                         }
6513                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6514                         break;
6515                 case RTE_FLOW_ACTION_TYPE_SET_META:
6516                         ret = flow_dv_validate_action_set_meta(dev, actions,
6517                                                                action_flags,
6518                                                                attr, error);
6519                         if (ret < 0)
6520                                 return ret;
6521                         /* Count all modify-header actions as one action. */
6522                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6523                                 ++actions_n;
6524                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6525                                 modify_after_mirror = 1;
6526                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6527                         rw_act_num += MLX5_ACT_NUM_SET_META;
6528                         break;
6529                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6530                         ret = flow_dv_validate_action_set_tag(dev, actions,
6531                                                               action_flags,
6532                                                               attr, error);
6533                         if (ret < 0)
6534                                 return ret;
6535                         /* Count all modify-header actions as one action. */
6536                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6537                                 ++actions_n;
6538                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6539                                 modify_after_mirror = 1;
6540                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6541                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6542                         break;
6543                 case RTE_FLOW_ACTION_TYPE_DROP:
6544                         ret = mlx5_flow_validate_action_drop(action_flags,
6545                                                              attr, error);
6546                         if (ret < 0)
6547                                 return ret;
6548                         action_flags |= MLX5_FLOW_ACTION_DROP;
6549                         ++actions_n;
6550                         break;
6551                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6552                         ret = mlx5_flow_validate_action_queue(actions,
6553                                                               action_flags, dev,
6554                                                               attr, error);
6555                         if (ret < 0)
6556                                 return ret;
6557                         queue_index = ((const struct rte_flow_action_queue *)
6558                                                         (actions->conf))->index;
6559                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6560                         ++actions_n;
6561                         break;
6562                 case RTE_FLOW_ACTION_TYPE_RSS:
6563                         rss = actions->conf;
6564                         ret = mlx5_flow_validate_action_rss(actions,
6565                                                             action_flags, dev,
6566                                                             attr, item_flags,
6567                                                             error);
6568                         if (ret < 0)
6569                                 return ret;
6570                         if (rss && sample_rss &&
6571                             (sample_rss->level != rss->level ||
6572                             sample_rss->types != rss->types))
6573                                 return rte_flow_error_set(error, ENOTSUP,
6574                                         RTE_FLOW_ERROR_TYPE_ACTION,
6575                                         NULL,
6576                                         "Can't use the different RSS types "
6577                                         "or level in the same flow");
6578                         if (rss != NULL && rss->queue_num)
6579                                 queue_index = rss->queue[0];
6580                         action_flags |= MLX5_FLOW_ACTION_RSS;
6581                         ++actions_n;
6582                         break;
6583                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6584                         ret =
6585                         mlx5_flow_validate_action_default_miss(action_flags,
6586                                         attr, error);
6587                         if (ret < 0)
6588                                 return ret;
6589                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6590                         ++actions_n;
6591                         break;
6592                 case RTE_FLOW_ACTION_TYPE_COUNT:
6593                         ret = flow_dv_validate_action_count(dev, actions,
6594                                                             action_flags,
6595                                                             error);
6596                         if (ret < 0)
6597                                 return ret;
6598                         count = actions->conf;
6599                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6600                         ++actions_n;
6601                         break;
6602                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6603                         if (flow_dv_validate_action_pop_vlan(dev,
6604                                                              action_flags,
6605                                                              actions,
6606                                                              item_flags, attr,
6607                                                              error))
6608                                 return -rte_errno;
6609                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6610                         ++actions_n;
6611                         break;
6612                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6613                         ret = flow_dv_validate_action_push_vlan(dev,
6614                                                                 action_flags,
6615                                                                 vlan_m,
6616                                                                 actions, attr,
6617                                                                 error);
6618                         if (ret < 0)
6619                                 return ret;
6620                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6621                         ++actions_n;
6622                         break;
6623                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6624                         ret = flow_dv_validate_action_set_vlan_pcp
6625                                                 (action_flags, actions, error);
6626                         if (ret < 0)
6627                                 return ret;
6628                         /* Count PCP with push_vlan command. */
6629                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6630                         break;
6631                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6632                         ret = flow_dv_validate_action_set_vlan_vid
6633                                                 (item_flags, action_flags,
6634                                                  actions, error);
6635                         if (ret < 0)
6636                                 return ret;
6637                         /* Count VID with push_vlan command. */
6638                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6639                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6640                         break;
6641                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6642                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6643                         ret = flow_dv_validate_action_l2_encap(dev,
6644                                                                action_flags,
6645                                                                actions, attr,
6646                                                                error);
6647                         if (ret < 0)
6648                                 return ret;
6649                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6650                         ++actions_n;
6651                         break;
6652                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6653                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6654                         ret = flow_dv_validate_action_decap(dev, action_flags,
6655                                                             actions, item_flags,
6656                                                             attr, error);
6657                         if (ret < 0)
6658                                 return ret;
6659                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6660                         ++actions_n;
6661                         break;
6662                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6663                         ret = flow_dv_validate_action_raw_encap_decap
6664                                 (dev, NULL, actions->conf, attr, &action_flags,
6665                                  &actions_n, actions, item_flags, error);
6666                         if (ret < 0)
6667                                 return ret;
6668                         break;
6669                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6670                         decap = actions->conf;
6671                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6672                                 ;
6673                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6674                                 encap = NULL;
6675                                 actions--;
6676                         } else {
6677                                 encap = actions->conf;
6678                         }
6679                         ret = flow_dv_validate_action_raw_encap_decap
6680                                            (dev,
6681                                             decap ? decap : &empty_decap, encap,
6682                                             attr, &action_flags, &actions_n,
6683                                             actions, item_flags, error);
6684                         if (ret < 0)
6685                                 return ret;
6686                         break;
6687                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6688                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6689                         ret = flow_dv_validate_action_modify_mac(action_flags,
6690                                                                  actions,
6691                                                                  item_flags,
6692                                                                  error);
6693                         if (ret < 0)
6694                                 return ret;
6695                         /* Count all modify-header actions as one action. */
6696                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6697                                 ++actions_n;
6698                         action_flags |= actions->type ==
6699                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6700                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6701                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6702                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6703                                 modify_after_mirror = 1;
6704                         /*
6705                          * Even if the source and destination MAC addresses have
6706                          * overlap in the header with 4B alignment, the convert
6707                          * function will handle them separately and 4 SW actions
6708                          * will be created. And 2 actions will be added each
6709                          * time no matter how many bytes of address will be set.
6710                          */
6711                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6712                         break;
6713                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6714                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6715                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6716                                                                   actions,
6717                                                                   item_flags,
6718                                                                   error);
6719                         if (ret < 0)
6720                                 return ret;
6721                         /* Count all modify-header actions as one action. */
6722                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6723                                 ++actions_n;
6724                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6725                                 modify_after_mirror = 1;
6726                         action_flags |= actions->type ==
6727                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6728                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6729                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6730                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6731                         break;
6732                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6733                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6734                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6735                                                                   actions,
6736                                                                   item_flags,
6737                                                                   error);
6738                         if (ret < 0)
6739                                 return ret;
6740                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6741                                 return rte_flow_error_set(error, ENOTSUP,
6742                                         RTE_FLOW_ERROR_TYPE_ACTION,
6743                                         actions,
6744                                         "Can't change header "
6745                                         "with ICMPv6 proto");
6746                         /* Count all modify-header actions as one action. */
6747                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6748                                 ++actions_n;
6749                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6750                                 modify_after_mirror = 1;
6751                         action_flags |= actions->type ==
6752                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6753                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6754                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6755                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6756                         break;
6757                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6758                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6759                         ret = flow_dv_validate_action_modify_tp(action_flags,
6760                                                                 actions,
6761                                                                 item_flags,
6762                                                                 error);
6763                         if (ret < 0)
6764                                 return ret;
6765                         /* Count all modify-header actions as one action. */
6766                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6767                                 ++actions_n;
6768                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6769                                 modify_after_mirror = 1;
6770                         action_flags |= actions->type ==
6771                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6772                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6773                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6774                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6775                         break;
6776                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6777                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6778                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6779                                                                  actions,
6780                                                                  item_flags,
6781                                                                  error);
6782                         if (ret < 0)
6783                                 return ret;
6784                         /* Count all modify-header actions as one action. */
6785                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6786                                 ++actions_n;
6787                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6788                                 modify_after_mirror = 1;
6789                         action_flags |= actions->type ==
6790                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6791                                                 MLX5_FLOW_ACTION_SET_TTL :
6792                                                 MLX5_FLOW_ACTION_DEC_TTL;
6793                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6794                         break;
6795                 case RTE_FLOW_ACTION_TYPE_JUMP:
6796                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6797                                                            action_flags,
6798                                                            attr, external,
6799                                                            error);
6800                         if (ret)
6801                                 return ret;
6802                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6803                             fdb_mirror_limit)
6804                                 return rte_flow_error_set(error, EINVAL,
6805                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6806                                                   NULL,
6807                                                   "sample and jump action combination is not supported");
6808                         ++actions_n;
6809                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6810                         break;
6811                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6812                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6813                         ret = flow_dv_validate_action_modify_tcp_seq
6814                                                                 (action_flags,
6815                                                                  actions,
6816                                                                  item_flags,
6817                                                                  error);
6818                         if (ret < 0)
6819                                 return ret;
6820                         /* Count all modify-header actions as one action. */
6821                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6822                                 ++actions_n;
6823                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6824                                 modify_after_mirror = 1;
6825                         action_flags |= actions->type ==
6826                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6827                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6828                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6829                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6830                         break;
6831                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6832                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6833                         ret = flow_dv_validate_action_modify_tcp_ack
6834                                                                 (action_flags,
6835                                                                  actions,
6836                                                                  item_flags,
6837                                                                  error);
6838                         if (ret < 0)
6839                                 return ret;
6840                         /* Count all modify-header actions as one action. */
6841                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6842                                 ++actions_n;
6843                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6844                                 modify_after_mirror = 1;
6845                         action_flags |= actions->type ==
6846                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6847                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6848                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6849                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6850                         break;
6851                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6852                         break;
6853                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6854                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6855                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6856                         break;
6857                 case RTE_FLOW_ACTION_TYPE_METER:
6858                         ret = mlx5_flow_validate_action_meter(dev,
6859                                                               action_flags,
6860                                                               actions, attr,
6861                                                               error);
6862                         if (ret < 0)
6863                                 return ret;
6864                         action_flags |= MLX5_FLOW_ACTION_METER;
6865                         ++actions_n;
6866                         /* Meter action will add one more TAG action. */
6867                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6868                         break;
6869                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6870                         if (!attr->transfer && !attr->group)
6871                                 return rte_flow_error_set(error, ENOTSUP,
6872                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6873                                                                            NULL,
6874                           "Shared ASO age action is not supported for group 0");
6875                         action_flags |= MLX5_FLOW_ACTION_AGE;
6876                         ++actions_n;
6877                         break;
6878                 case RTE_FLOW_ACTION_TYPE_AGE:
6879                         ret = flow_dv_validate_action_age(action_flags,
6880                                                           actions, dev,
6881                                                           error);
6882                         if (ret < 0)
6883                                 return ret;
6884                         /*
6885                          * Validate the regular AGE action (using counter)
6886                          * mutual exclusion with share counter actions.
6887                          */
6888                         if (!priv->sh->flow_hit_aso_en) {
6889                                 if (count && count->shared)
6890                                         return rte_flow_error_set
6891                                                 (error, EINVAL,
6892                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6893                                                 NULL,
6894                                                 "old age and shared count combination is not supported");
6895                                 if (sample_count)
6896                                         return rte_flow_error_set
6897                                                 (error, EINVAL,
6898                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6899                                                 NULL,
6900                                                 "old age action and count must be in the same sub flow");
6901                         }
6902                         action_flags |= MLX5_FLOW_ACTION_AGE;
6903                         ++actions_n;
6904                         break;
6905                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6906                         ret = flow_dv_validate_action_modify_ipv4_dscp
6907                                                          (action_flags,
6908                                                           actions,
6909                                                           item_flags,
6910                                                           error);
6911                         if (ret < 0)
6912                                 return ret;
6913                         /* Count all modify-header actions as one action. */
6914                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6915                                 ++actions_n;
6916                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6917                                 modify_after_mirror = 1;
6918                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6919                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6920                         break;
6921                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6922                         ret = flow_dv_validate_action_modify_ipv6_dscp
6923                                                                 (action_flags,
6924                                                                  actions,
6925                                                                  item_flags,
6926                                                                  error);
6927                         if (ret < 0)
6928                                 return ret;
6929                         /* Count all modify-header actions as one action. */
6930                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6931                                 ++actions_n;
6932                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6933                                 modify_after_mirror = 1;
6934                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6935                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6936                         break;
6937                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6938                         ret = flow_dv_validate_action_sample(&action_flags,
6939                                                              actions, dev,
6940                                                              attr, item_flags,
6941                                                              rss, &sample_rss,
6942                                                              &sample_count,
6943                                                              &fdb_mirror_limit,
6944                                                              error);
6945                         if (ret < 0)
6946                                 return ret;
6947                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6948                         ++actions_n;
6949                         break;
6950                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6951                         if (actions[0].type != (typeof(actions[0].type))
6952                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6953                                 return rte_flow_error_set
6954                                                 (error, EINVAL,
6955                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6956                                                 NULL, "MLX5 private action "
6957                                                 "must be the first");
6958
6959                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6960                         break;
6961                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6962                         ret = flow_dv_validate_action_modify_field(dev,
6963                                                                    action_flags,
6964                                                                    actions,
6965                                                                    attr,
6966                                                                    error);
6967                         if (ret < 0)
6968                                 return ret;
6969                         /* Count all modify-header actions as one action. */
6970                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6971                                 ++actions_n;
6972                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6973                         rw_act_num += ret;
6974                         break;
6975                 default:
6976                         return rte_flow_error_set(error, ENOTSUP,
6977                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6978                                                   actions,
6979                                                   "action not supported");
6980                 }
6981         }
6982         /*
6983          * Validate actions in flow rules
6984          * - Explicit decap action is prohibited by the tunnel offload API.
6985          * - Drop action in tunnel steer rule is prohibited by the API.
6986          * - Application cannot use MARK action because it's value can mask
6987          *   tunnel default miss nitification.
6988          * - JUMP in tunnel match rule has no support in current PMD
6989          *   implementation.
6990          * - TAG & META are reserved for future uses.
6991          */
6992         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6993                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6994                                             MLX5_FLOW_ACTION_MARK     |
6995                                             MLX5_FLOW_ACTION_SET_TAG  |
6996                                             MLX5_FLOW_ACTION_SET_META |
6997                                             MLX5_FLOW_ACTION_DROP;
6998
6999                 if (action_flags & bad_actions_mask)
7000                         return rte_flow_error_set
7001                                         (error, EINVAL,
7002                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7003                                         "Invalid RTE action in tunnel "
7004                                         "set decap rule");
7005                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7006                         return rte_flow_error_set
7007                                         (error, EINVAL,
7008                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7009                                         "tunnel set decap rule must terminate "
7010                                         "with JUMP");
7011                 if (!attr->ingress)
7012                         return rte_flow_error_set
7013                                         (error, EINVAL,
7014                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7015                                         "tunnel flows for ingress traffic only");
7016         }
7017         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7018                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7019                                             MLX5_FLOW_ACTION_MARK    |
7020                                             MLX5_FLOW_ACTION_SET_TAG |
7021                                             MLX5_FLOW_ACTION_SET_META;
7022
7023                 if (action_flags & bad_actions_mask)
7024                         return rte_flow_error_set
7025                                         (error, EINVAL,
7026                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7027                                         "Invalid RTE action in tunnel "
7028                                         "set match rule");
7029         }
7030         /*
7031          * Validate the drop action mutual exclusion with other actions.
7032          * Drop action is mutually-exclusive with any other action, except for
7033          * Count action.
7034          * Drop action compatibility with tunnel offload was already validated.
7035          */
7036         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7037                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7038         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7039             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7040                 return rte_flow_error_set(error, EINVAL,
7041                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7042                                           "Drop action is mutually-exclusive "
7043                                           "with any other action, except for "
7044                                           "Count action");
7045         /* Eswitch has few restrictions on using items and actions */
7046         if (attr->transfer) {
7047                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7048                     action_flags & MLX5_FLOW_ACTION_FLAG)
7049                         return rte_flow_error_set(error, ENOTSUP,
7050                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7051                                                   NULL,
7052                                                   "unsupported action FLAG");
7053                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7054                     action_flags & MLX5_FLOW_ACTION_MARK)
7055                         return rte_flow_error_set(error, ENOTSUP,
7056                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7057                                                   NULL,
7058                                                   "unsupported action MARK");
7059                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7060                         return rte_flow_error_set(error, ENOTSUP,
7061                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7062                                                   NULL,
7063                                                   "unsupported action QUEUE");
7064                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7065                         return rte_flow_error_set(error, ENOTSUP,
7066                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7067                                                   NULL,
7068                                                   "unsupported action RSS");
7069                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7070                         return rte_flow_error_set(error, EINVAL,
7071                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7072                                                   actions,
7073                                                   "no fate action is found");
7074         } else {
7075                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7076                         return rte_flow_error_set(error, EINVAL,
7077                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7078                                                   actions,
7079                                                   "no fate action is found");
7080         }
7081         /*
7082          * Continue validation for Xcap and VLAN actions.
7083          * If hairpin is working in explicit TX rule mode, there is no actions
7084          * splitting and the validation of hairpin ingress flow should be the
7085          * same as other standard flows.
7086          */
7087         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7088                              MLX5_FLOW_VLAN_ACTIONS)) &&
7089             (queue_index == 0xFFFF ||
7090              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7091              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7092              conf->tx_explicit != 0))) {
7093                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7094                     MLX5_FLOW_XCAP_ACTIONS)
7095                         return rte_flow_error_set(error, ENOTSUP,
7096                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7097                                                   NULL, "encap and decap "
7098                                                   "combination aren't supported");
7099                 if (!attr->transfer && attr->ingress) {
7100                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7101                                 return rte_flow_error_set
7102                                                 (error, ENOTSUP,
7103                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7104                                                  NULL, "encap is not supported"
7105                                                  " for ingress traffic");
7106                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7107                                 return rte_flow_error_set
7108                                                 (error, ENOTSUP,
7109                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7110                                                  NULL, "push VLAN action not "
7111                                                  "supported for ingress");
7112                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7113                                         MLX5_FLOW_VLAN_ACTIONS)
7114                                 return rte_flow_error_set
7115                                                 (error, ENOTSUP,
7116                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7117                                                  NULL, "no support for "
7118                                                  "multiple VLAN actions");
7119                 }
7120         }
7121         /*
7122          * Hairpin flow will add one more TAG action in TX implicit mode.
7123          * In TX explicit mode, there will be no hairpin flow ID.
7124          */
7125         if (hairpin > 0)
7126                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7127         /* extra metadata enabled: one more TAG action will be add. */
7128         if (dev_conf->dv_flow_en &&
7129             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7130             mlx5_flow_ext_mreg_supported(dev))
7131                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7132         if (rw_act_num >
7133                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7134                 return rte_flow_error_set(error, ENOTSUP,
7135                                           RTE_FLOW_ERROR_TYPE_ACTION,
7136                                           NULL, "too many header modify"
7137                                           " actions to support");
7138         }
7139         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7140         if (fdb_mirror_limit && modify_after_mirror)
7141                 return rte_flow_error_set(error, EINVAL,
7142                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7143                                 "sample before modify action is not supported");
7144         return 0;
7145 }
7146
7147 /**
7148  * Internal preparation function. Allocates the DV flow size,
7149  * this size is constant.
7150  *
7151  * @param[in] dev
7152  *   Pointer to the rte_eth_dev structure.
7153  * @param[in] attr
7154  *   Pointer to the flow attributes.
7155  * @param[in] items
7156  *   Pointer to the list of items.
7157  * @param[in] actions
7158  *   Pointer to the list of actions.
7159  * @param[out] error
7160  *   Pointer to the error structure.
7161  *
7162  * @return
7163  *   Pointer to mlx5_flow object on success,
7164  *   otherwise NULL and rte_errno is set.
7165  */
7166 static struct mlx5_flow *
7167 flow_dv_prepare(struct rte_eth_dev *dev,
7168                 const struct rte_flow_attr *attr __rte_unused,
7169                 const struct rte_flow_item items[] __rte_unused,
7170                 const struct rte_flow_action actions[] __rte_unused,
7171                 struct rte_flow_error *error)
7172 {
7173         uint32_t handle_idx = 0;
7174         struct mlx5_flow *dev_flow;
7175         struct mlx5_flow_handle *dev_handle;
7176         struct mlx5_priv *priv = dev->data->dev_private;
7177         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7178
7179         MLX5_ASSERT(wks);
7180         /* In case of corrupting the memory. */
7181         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7182                 rte_flow_error_set(error, ENOSPC,
7183                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7184                                    "not free temporary device flow");
7185                 return NULL;
7186         }
7187         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7188                                    &handle_idx);
7189         if (!dev_handle) {
7190                 rte_flow_error_set(error, ENOMEM,
7191                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7192                                    "not enough memory to create flow handle");
7193                 return NULL;
7194         }
7195         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7196         dev_flow = &wks->flows[wks->flow_idx++];
7197         memset(dev_flow, 0, sizeof(*dev_flow));
7198         dev_flow->handle = dev_handle;
7199         dev_flow->handle_idx = handle_idx;
7200         /*
7201          * In some old rdma-core releases, before continuing, a check of the
7202          * length of matching parameter will be done at first. It needs to use
7203          * the length without misc4 param. If the flow has misc4 support, then
7204          * the length needs to be adjusted accordingly. Each param member is
7205          * aligned with a 64B boundary naturally.
7206          */
7207         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7208                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7209         dev_flow->ingress = attr->ingress;
7210         dev_flow->dv.transfer = attr->transfer;
7211         return dev_flow;
7212 }
7213
7214 #ifdef RTE_LIBRTE_MLX5_DEBUG
7215 /**
7216  * Sanity check for match mask and value. Similar to check_valid_spec() in
7217  * kernel driver. If unmasked bit is present in value, it returns failure.
7218  *
7219  * @param match_mask
7220  *   pointer to match mask buffer.
7221  * @param match_value
7222  *   pointer to match value buffer.
7223  *
7224  * @return
7225  *   0 if valid, -EINVAL otherwise.
7226  */
7227 static int
7228 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7229 {
7230         uint8_t *m = match_mask;
7231         uint8_t *v = match_value;
7232         unsigned int i;
7233
7234         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7235                 if (v[i] & ~m[i]) {
7236                         DRV_LOG(ERR,
7237                                 "match_value differs from match_criteria"
7238                                 " %p[%u] != %p[%u]",
7239                                 match_value, i, match_mask, i);
7240                         return -EINVAL;
7241                 }
7242         }
7243         return 0;
7244 }
7245 #endif
7246
7247 /**
7248  * Add match of ip_version.
7249  *
7250  * @param[in] group
7251  *   Flow group.
7252  * @param[in] headers_v
7253  *   Values header pointer.
7254  * @param[in] headers_m
7255  *   Masks header pointer.
7256  * @param[in] ip_version
7257  *   The IP version to set.
7258  */
7259 static inline void
7260 flow_dv_set_match_ip_version(uint32_t group,
7261                              void *headers_v,
7262                              void *headers_m,
7263                              uint8_t ip_version)
7264 {
7265         if (group == 0)
7266                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7267         else
7268                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7269                          ip_version);
7270         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7271         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7272         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7273 }
7274
7275 /**
7276  * Add Ethernet item to matcher and to the value.
7277  *
7278  * @param[in, out] matcher
7279  *   Flow matcher.
7280  * @param[in, out] key
7281  *   Flow matcher value.
7282  * @param[in] item
7283  *   Flow pattern to translate.
7284  * @param[in] inner
7285  *   Item is inner pattern.
7286  */
7287 static void
7288 flow_dv_translate_item_eth(void *matcher, void *key,
7289                            const struct rte_flow_item *item, int inner,
7290                            uint32_t group)
7291 {
7292         const struct rte_flow_item_eth *eth_m = item->mask;
7293         const struct rte_flow_item_eth *eth_v = item->spec;
7294         const struct rte_flow_item_eth nic_mask = {
7295                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7296                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7297                 .type = RTE_BE16(0xffff),
7298                 .has_vlan = 0,
7299         };
7300         void *hdrs_m;
7301         void *hdrs_v;
7302         char *l24_v;
7303         unsigned int i;
7304
7305         if (!eth_v)
7306                 return;
7307         if (!eth_m)
7308                 eth_m = &nic_mask;
7309         if (inner) {
7310                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7311                                          inner_headers);
7312                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7313         } else {
7314                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7315                                          outer_headers);
7316                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7317         }
7318         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7319                &eth_m->dst, sizeof(eth_m->dst));
7320         /* The value must be in the range of the mask. */
7321         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7322         for (i = 0; i < sizeof(eth_m->dst); ++i)
7323                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7324         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7325                &eth_m->src, sizeof(eth_m->src));
7326         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7327         /* The value must be in the range of the mask. */
7328         for (i = 0; i < sizeof(eth_m->dst); ++i)
7329                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7330         /*
7331          * HW supports match on one Ethertype, the Ethertype following the last
7332          * VLAN tag of the packet (see PRM).
7333          * Set match on ethertype only if ETH header is not followed by VLAN.
7334          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7335          * ethertype, and use ip_version field instead.
7336          * eCPRI over Ether layer will use type value 0xAEFE.
7337          */
7338         if (eth_m->type == 0xFFFF) {
7339                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7340                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7341                 switch (eth_v->type) {
7342                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7343                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7344                         return;
7345                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7346                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7347                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7348                         return;
7349                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7350                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7351                         return;
7352                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7353                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7354                         return;
7355                 default:
7356                         break;
7357                 }
7358         }
7359         if (eth_m->has_vlan) {
7360                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7361                 if (eth_v->has_vlan) {
7362                         /*
7363                          * Here, when also has_more_vlan field in VLAN item is
7364                          * not set, only single-tagged packets will be matched.
7365                          */
7366                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7367                         return;
7368                 }
7369         }
7370         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7371                  rte_be_to_cpu_16(eth_m->type));
7372         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7373         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7374 }
7375
7376 /**
7377  * Add VLAN item to matcher and to the value.
7378  *
7379  * @param[in, out] dev_flow
7380  *   Flow descriptor.
7381  * @param[in, out] matcher
7382  *   Flow matcher.
7383  * @param[in, out] key
7384  *   Flow matcher value.
7385  * @param[in] item
7386  *   Flow pattern to translate.
7387  * @param[in] inner
7388  *   Item is inner pattern.
7389  */
7390 static void
7391 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7392                             void *matcher, void *key,
7393                             const struct rte_flow_item *item,
7394                             int inner, uint32_t group)
7395 {
7396         const struct rte_flow_item_vlan *vlan_m = item->mask;
7397         const struct rte_flow_item_vlan *vlan_v = item->spec;
7398         void *hdrs_m;
7399         void *hdrs_v;
7400         uint16_t tci_m;
7401         uint16_t tci_v;
7402
7403         if (inner) {
7404                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7405                                          inner_headers);
7406                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7407         } else {
7408                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7409                                          outer_headers);
7410                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7411                 /*
7412                  * This is workaround, masks are not supported,
7413                  * and pre-validated.
7414                  */
7415                 if (vlan_v)
7416                         dev_flow->handle->vf_vlan.tag =
7417                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7418         }
7419         /*
7420          * When VLAN item exists in flow, mark packet as tagged,
7421          * even if TCI is not specified.
7422          */
7423         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7424                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7425                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7426         }
7427         if (!vlan_v)
7428                 return;
7429         if (!vlan_m)
7430                 vlan_m = &rte_flow_item_vlan_mask;
7431         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7432         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7433         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7434         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7435         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7436         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7437         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7438         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7439         /*
7440          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7441          * ethertype, and use ip_version field instead.
7442          */
7443         if (vlan_m->inner_type == 0xFFFF) {
7444                 switch (vlan_v->inner_type) {
7445                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7446                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7447                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7448                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7449                         return;
7450                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7451                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7452                         return;
7453                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7454                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7455                         return;
7456                 default:
7457                         break;
7458                 }
7459         }
7460         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7461                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7462                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7463                 /* Only one vlan_tag bit can be set. */
7464                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7465                 return;
7466         }
7467         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7468                  rte_be_to_cpu_16(vlan_m->inner_type));
7469         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7470                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7471 }
7472
7473 /**
7474  * Add IPV4 item to matcher and to the value.
7475  *
7476  * @param[in, out] matcher
7477  *   Flow matcher.
7478  * @param[in, out] key
7479  *   Flow matcher value.
7480  * @param[in] item
7481  *   Flow pattern to translate.
7482  * @param[in] inner
7483  *   Item is inner pattern.
7484  * @param[in] group
7485  *   The group to insert the rule.
7486  */
7487 static void
7488 flow_dv_translate_item_ipv4(void *matcher, void *key,
7489                             const struct rte_flow_item *item,
7490                             int inner, uint32_t group)
7491 {
7492         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7493         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7494         const struct rte_flow_item_ipv4 nic_mask = {
7495                 .hdr = {
7496                         .src_addr = RTE_BE32(0xffffffff),
7497                         .dst_addr = RTE_BE32(0xffffffff),
7498                         .type_of_service = 0xff,
7499                         .next_proto_id = 0xff,
7500                         .time_to_live = 0xff,
7501                 },
7502         };
7503         void *headers_m;
7504         void *headers_v;
7505         char *l24_m;
7506         char *l24_v;
7507         uint8_t tos;
7508
7509         if (inner) {
7510                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7511                                          inner_headers);
7512                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7513         } else {
7514                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7515                                          outer_headers);
7516                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7517         }
7518         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7519         if (!ipv4_v)
7520                 return;
7521         if (!ipv4_m)
7522                 ipv4_m = &nic_mask;
7523         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7524                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7525         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7526                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7527         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7528         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7529         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7530                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7531         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7532                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7533         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7534         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7535         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7536         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7537                  ipv4_m->hdr.type_of_service);
7538         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7539         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7540                  ipv4_m->hdr.type_of_service >> 2);
7541         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7542         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7543                  ipv4_m->hdr.next_proto_id);
7544         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7545                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7546         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7547                  ipv4_m->hdr.time_to_live);
7548         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7549                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7550         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7551                  !!(ipv4_m->hdr.fragment_offset));
7552         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7553                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7554 }
7555
7556 /**
7557  * Add IPV6 item to matcher and to the value.
7558  *
7559  * @param[in, out] matcher
7560  *   Flow matcher.
7561  * @param[in, out] key
7562  *   Flow matcher value.
7563  * @param[in] item
7564  *   Flow pattern to translate.
7565  * @param[in] inner
7566  *   Item is inner pattern.
7567  * @param[in] group
7568  *   The group to insert the rule.
7569  */
7570 static void
7571 flow_dv_translate_item_ipv6(void *matcher, void *key,
7572                             const struct rte_flow_item *item,
7573                             int inner, uint32_t group)
7574 {
7575         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7576         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7577         const struct rte_flow_item_ipv6 nic_mask = {
7578                 .hdr = {
7579                         .src_addr =
7580                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7581                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7582                         .dst_addr =
7583                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7584                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7585                         .vtc_flow = RTE_BE32(0xffffffff),
7586                         .proto = 0xff,
7587                         .hop_limits = 0xff,
7588                 },
7589         };
7590         void *headers_m;
7591         void *headers_v;
7592         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7593         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7594         char *l24_m;
7595         char *l24_v;
7596         uint32_t vtc_m;
7597         uint32_t vtc_v;
7598         int i;
7599         int size;
7600
7601         if (inner) {
7602                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7603                                          inner_headers);
7604                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7605         } else {
7606                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7607                                          outer_headers);
7608                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7609         }
7610         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7611         if (!ipv6_v)
7612                 return;
7613         if (!ipv6_m)
7614                 ipv6_m = &nic_mask;
7615         size = sizeof(ipv6_m->hdr.dst_addr);
7616         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7617                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7618         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7619                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7620         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7621         for (i = 0; i < size; ++i)
7622                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7623         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7624                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7625         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7626                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7627         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7628         for (i = 0; i < size; ++i)
7629                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7630         /* TOS. */
7631         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7632         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7633         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7634         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7635         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7636         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7637         /* Label. */
7638         if (inner) {
7639                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7640                          vtc_m);
7641                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7642                          vtc_v);
7643         } else {
7644                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7645                          vtc_m);
7646                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7647                          vtc_v);
7648         }
7649         /* Protocol. */
7650         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7651                  ipv6_m->hdr.proto);
7652         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7653                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7654         /* Hop limit. */
7655         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7656                  ipv6_m->hdr.hop_limits);
7657         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7658                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7659         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7660                  !!(ipv6_m->has_frag_ext));
7661         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7662                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7663 }
7664
7665 /**
7666  * Add IPV6 fragment extension item to matcher and to the value.
7667  *
7668  * @param[in, out] matcher
7669  *   Flow matcher.
7670  * @param[in, out] key
7671  *   Flow matcher value.
7672  * @param[in] item
7673  *   Flow pattern to translate.
7674  * @param[in] inner
7675  *   Item is inner pattern.
7676  */
7677 static void
7678 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7679                                      const struct rte_flow_item *item,
7680                                      int inner)
7681 {
7682         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7683         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7684         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7685                 .hdr = {
7686                         .next_header = 0xff,
7687                         .frag_data = RTE_BE16(0xffff),
7688                 },
7689         };
7690         void *headers_m;
7691         void *headers_v;
7692
7693         if (inner) {
7694                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7695                                          inner_headers);
7696                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7697         } else {
7698                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7699                                          outer_headers);
7700                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7701         }
7702         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7703         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7704         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7705         if (!ipv6_frag_ext_v)
7706                 return;
7707         if (!ipv6_frag_ext_m)
7708                 ipv6_frag_ext_m = &nic_mask;
7709         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7710                  ipv6_frag_ext_m->hdr.next_header);
7711         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7712                  ipv6_frag_ext_v->hdr.next_header &
7713                  ipv6_frag_ext_m->hdr.next_header);
7714 }
7715
7716 /**
7717  * Add TCP item to matcher and to the value.
7718  *
7719  * @param[in, out] matcher
7720  *   Flow matcher.
7721  * @param[in, out] key
7722  *   Flow matcher value.
7723  * @param[in] item
7724  *   Flow pattern to translate.
7725  * @param[in] inner
7726  *   Item is inner pattern.
7727  */
7728 static void
7729 flow_dv_translate_item_tcp(void *matcher, void *key,
7730                            const struct rte_flow_item *item,
7731                            int inner)
7732 {
7733         const struct rte_flow_item_tcp *tcp_m = item->mask;
7734         const struct rte_flow_item_tcp *tcp_v = item->spec;
7735         void *headers_m;
7736         void *headers_v;
7737
7738         if (inner) {
7739                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7740                                          inner_headers);
7741                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7742         } else {
7743                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7744                                          outer_headers);
7745                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7746         }
7747         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7748         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7749         if (!tcp_v)
7750                 return;
7751         if (!tcp_m)
7752                 tcp_m = &rte_flow_item_tcp_mask;
7753         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7754                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7755         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7756                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7757         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7758                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7759         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7760                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7761         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7762                  tcp_m->hdr.tcp_flags);
7763         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7764                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7765 }
7766
7767 /**
7768  * Add UDP item to matcher and to the value.
7769  *
7770  * @param[in, out] matcher
7771  *   Flow matcher.
7772  * @param[in, out] key
7773  *   Flow matcher value.
7774  * @param[in] item
7775  *   Flow pattern to translate.
7776  * @param[in] inner
7777  *   Item is inner pattern.
7778  */
7779 static void
7780 flow_dv_translate_item_udp(void *matcher, void *key,
7781                            const struct rte_flow_item *item,
7782                            int inner)
7783 {
7784         const struct rte_flow_item_udp *udp_m = item->mask;
7785         const struct rte_flow_item_udp *udp_v = item->spec;
7786         void *headers_m;
7787         void *headers_v;
7788
7789         if (inner) {
7790                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7791                                          inner_headers);
7792                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7793         } else {
7794                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7795                                          outer_headers);
7796                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7797         }
7798         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7799         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7800         if (!udp_v)
7801                 return;
7802         if (!udp_m)
7803                 udp_m = &rte_flow_item_udp_mask;
7804         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7805                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7806         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7807                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7808         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7809                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7810         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7811                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7812 }
7813
7814 /**
7815  * Add GRE optional Key item to matcher and to the value.
7816  *
7817  * @param[in, out] matcher
7818  *   Flow matcher.
7819  * @param[in, out] key
7820  *   Flow matcher value.
7821  * @param[in] item
7822  *   Flow pattern to translate.
7823  * @param[in] inner
7824  *   Item is inner pattern.
7825  */
7826 static void
7827 flow_dv_translate_item_gre_key(void *matcher, void *key,
7828                                    const struct rte_flow_item *item)
7829 {
7830         const rte_be32_t *key_m = item->mask;
7831         const rte_be32_t *key_v = item->spec;
7832         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7833         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7834         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7835
7836         /* GRE K bit must be on and should already be validated */
7837         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7838         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7839         if (!key_v)
7840                 return;
7841         if (!key_m)
7842                 key_m = &gre_key_default_mask;
7843         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7844                  rte_be_to_cpu_32(*key_m) >> 8);
7845         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7846                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7847         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7848                  rte_be_to_cpu_32(*key_m) & 0xFF);
7849         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7850                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7851 }
7852
7853 /**
7854  * Add GRE item to matcher and to the value.
7855  *
7856  * @param[in, out] matcher
7857  *   Flow matcher.
7858  * @param[in, out] key
7859  *   Flow matcher value.
7860  * @param[in] item
7861  *   Flow pattern to translate.
7862  * @param[in] inner
7863  *   Item is inner pattern.
7864  */
7865 static void
7866 flow_dv_translate_item_gre(void *matcher, void *key,
7867                            const struct rte_flow_item *item,
7868                            int inner)
7869 {
7870         const struct rte_flow_item_gre *gre_m = item->mask;
7871         const struct rte_flow_item_gre *gre_v = item->spec;
7872         void *headers_m;
7873         void *headers_v;
7874         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7875         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7876         struct {
7877                 union {
7878                         __extension__
7879                         struct {
7880                                 uint16_t version:3;
7881                                 uint16_t rsvd0:9;
7882                                 uint16_t s_present:1;
7883                                 uint16_t k_present:1;
7884                                 uint16_t rsvd_bit1:1;
7885                                 uint16_t c_present:1;
7886                         };
7887                         uint16_t value;
7888                 };
7889         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7890
7891         if (inner) {
7892                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7893                                          inner_headers);
7894                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7895         } else {
7896                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7897                                          outer_headers);
7898                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7899         }
7900         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7901         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7902         if (!gre_v)
7903                 return;
7904         if (!gre_m)
7905                 gre_m = &rte_flow_item_gre_mask;
7906         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7907                  rte_be_to_cpu_16(gre_m->protocol));
7908         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7909                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7910         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7911         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7912         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7913                  gre_crks_rsvd0_ver_m.c_present);
7914         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7915                  gre_crks_rsvd0_ver_v.c_present &
7916                  gre_crks_rsvd0_ver_m.c_present);
7917         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7918                  gre_crks_rsvd0_ver_m.k_present);
7919         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7920                  gre_crks_rsvd0_ver_v.k_present &
7921                  gre_crks_rsvd0_ver_m.k_present);
7922         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7923                  gre_crks_rsvd0_ver_m.s_present);
7924         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7925                  gre_crks_rsvd0_ver_v.s_present &
7926                  gre_crks_rsvd0_ver_m.s_present);
7927 }
7928
7929 /**
7930  * Add NVGRE item to matcher and to the value.
7931  *
7932  * @param[in, out] matcher
7933  *   Flow matcher.
7934  * @param[in, out] key
7935  *   Flow matcher value.
7936  * @param[in] item
7937  *   Flow pattern to translate.
7938  * @param[in] inner
7939  *   Item is inner pattern.
7940  */
7941 static void
7942 flow_dv_translate_item_nvgre(void *matcher, void *key,
7943                              const struct rte_flow_item *item,
7944                              int inner)
7945 {
7946         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7947         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7948         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7949         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7950         const char *tni_flow_id_m;
7951         const char *tni_flow_id_v;
7952         char *gre_key_m;
7953         char *gre_key_v;
7954         int size;
7955         int i;
7956
7957         /* For NVGRE, GRE header fields must be set with defined values. */
7958         const struct rte_flow_item_gre gre_spec = {
7959                 .c_rsvd0_ver = RTE_BE16(0x2000),
7960                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7961         };
7962         const struct rte_flow_item_gre gre_mask = {
7963                 .c_rsvd0_ver = RTE_BE16(0xB000),
7964                 .protocol = RTE_BE16(UINT16_MAX),
7965         };
7966         const struct rte_flow_item gre_item = {
7967                 .spec = &gre_spec,
7968                 .mask = &gre_mask,
7969                 .last = NULL,
7970         };
7971         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7972         if (!nvgre_v)
7973                 return;
7974         if (!nvgre_m)
7975                 nvgre_m = &rte_flow_item_nvgre_mask;
7976         tni_flow_id_m = (const char *)nvgre_m->tni;
7977         tni_flow_id_v = (const char *)nvgre_v->tni;
7978         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7979         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7980         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7981         memcpy(gre_key_m, tni_flow_id_m, size);
7982         for (i = 0; i < size; ++i)
7983                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7984 }
7985
7986 /**
7987  * Add VXLAN item to matcher and to the value.
7988  *
7989  * @param[in, out] matcher
7990  *   Flow matcher.
7991  * @param[in, out] key
7992  *   Flow matcher value.
7993  * @param[in] item
7994  *   Flow pattern to translate.
7995  * @param[in] inner
7996  *   Item is inner pattern.
7997  */
7998 static void
7999 flow_dv_translate_item_vxlan(void *matcher, void *key,
8000                              const struct rte_flow_item *item,
8001                              int inner)
8002 {
8003         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8004         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8005         void *headers_m;
8006         void *headers_v;
8007         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8008         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8009         char *vni_m;
8010         char *vni_v;
8011         uint16_t dport;
8012         int size;
8013         int i;
8014
8015         if (inner) {
8016                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8017                                          inner_headers);
8018                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8019         } else {
8020                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8021                                          outer_headers);
8022                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8023         }
8024         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8025                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8026         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8027                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8028                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8029         }
8030         if (!vxlan_v)
8031                 return;
8032         if (!vxlan_m)
8033                 vxlan_m = &rte_flow_item_vxlan_mask;
8034         size = sizeof(vxlan_m->vni);
8035         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8036         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8037         memcpy(vni_m, vxlan_m->vni, size);
8038         for (i = 0; i < size; ++i)
8039                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8040 }
8041
8042 /**
8043  * Add VXLAN-GPE item to matcher and to the value.
8044  *
8045  * @param[in, out] matcher
8046  *   Flow matcher.
8047  * @param[in, out] key
8048  *   Flow matcher value.
8049  * @param[in] item
8050  *   Flow pattern to translate.
8051  * @param[in] inner
8052  *   Item is inner pattern.
8053  */
8054
8055 static void
8056 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8057                                  const struct rte_flow_item *item, int inner)
8058 {
8059         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8060         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8061         void *headers_m;
8062         void *headers_v;
8063         void *misc_m =
8064                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8065         void *misc_v =
8066                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8067         char *vni_m;
8068         char *vni_v;
8069         uint16_t dport;
8070         int size;
8071         int i;
8072         uint8_t flags_m = 0xff;
8073         uint8_t flags_v = 0xc;
8074
8075         if (inner) {
8076                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8077                                          inner_headers);
8078                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8079         } else {
8080                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8081                                          outer_headers);
8082                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8083         }
8084         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8085                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8086         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8087                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8088                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8089         }
8090         if (!vxlan_v)
8091                 return;
8092         if (!vxlan_m)
8093                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8094         size = sizeof(vxlan_m->vni);
8095         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8096         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8097         memcpy(vni_m, vxlan_m->vni, size);
8098         for (i = 0; i < size; ++i)
8099                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8100         if (vxlan_m->flags) {
8101                 flags_m = vxlan_m->flags;
8102                 flags_v = vxlan_v->flags;
8103         }
8104         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8105         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8106         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8107                  vxlan_m->protocol);
8108         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8109                  vxlan_v->protocol);
8110 }
8111
8112 /**
8113  * Add Geneve item to matcher and to the value.
8114  *
8115  * @param[in, out] matcher
8116  *   Flow matcher.
8117  * @param[in, out] key
8118  *   Flow matcher value.
8119  * @param[in] item
8120  *   Flow pattern to translate.
8121  * @param[in] inner
8122  *   Item is inner pattern.
8123  */
8124
8125 static void
8126 flow_dv_translate_item_geneve(void *matcher, void *key,
8127                               const struct rte_flow_item *item, int inner)
8128 {
8129         const struct rte_flow_item_geneve *geneve_m = item->mask;
8130         const struct rte_flow_item_geneve *geneve_v = item->spec;
8131         void *headers_m;
8132         void *headers_v;
8133         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8134         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8135         uint16_t dport;
8136         uint16_t gbhdr_m;
8137         uint16_t gbhdr_v;
8138         char *vni_m;
8139         char *vni_v;
8140         size_t size, i;
8141
8142         if (inner) {
8143                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8144                                          inner_headers);
8145                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8146         } else {
8147                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8148                                          outer_headers);
8149                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8150         }
8151         dport = MLX5_UDP_PORT_GENEVE;
8152         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8153                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8154                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8155         }
8156         if (!geneve_v)
8157                 return;
8158         if (!geneve_m)
8159                 geneve_m = &rte_flow_item_geneve_mask;
8160         size = sizeof(geneve_m->vni);
8161         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8162         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8163         memcpy(vni_m, geneve_m->vni, size);
8164         for (i = 0; i < size; ++i)
8165                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8166         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8167                  rte_be_to_cpu_16(geneve_m->protocol));
8168         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8169                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8170         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8171         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8172         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8173                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8174         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8175                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8176         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8177                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8178         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8179                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8180                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8181 }
8182
8183 /**
8184  * Create Geneve TLV option resource.
8185  *
8186  * @param dev[in, out]
8187  *   Pointer to rte_eth_dev structure.
8188  * @param[in, out] tag_be24
8189  *   Tag value in big endian then R-shift 8.
8190  * @parm[in, out] dev_flow
8191  *   Pointer to the dev_flow.
8192  * @param[out] error
8193  *   pointer to error structure.
8194  *
8195  * @return
8196  *   0 on success otherwise -errno and errno is set.
8197  */
8198
8199 int
8200 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8201                                              const struct rte_flow_item *item,
8202                                              struct rte_flow_error *error)
8203 {
8204         struct mlx5_priv *priv = dev->data->dev_private;
8205         struct mlx5_dev_ctx_shared *sh = priv->sh;
8206         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8207                         sh->geneve_tlv_option_resource;
8208         struct mlx5_devx_obj *obj;
8209         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8210         int ret = 0;
8211
8212         if (!geneve_opt_v)
8213                 return -1;
8214         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8215         if (geneve_opt_resource != NULL) {
8216                 if (geneve_opt_resource->option_class ==
8217                         geneve_opt_v->option_class &&
8218                         geneve_opt_resource->option_type ==
8219                         geneve_opt_v->option_type &&
8220                         geneve_opt_resource->length ==
8221                         geneve_opt_v->option_len) {
8222                         /* We already have GENVE TLV option obj allocated. */
8223                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8224                                            __ATOMIC_RELAXED);
8225                 } else {
8226                         ret = rte_flow_error_set(error, ENOMEM,
8227                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8228                                 "Only one GENEVE TLV option supported");
8229                         goto exit;
8230                 }
8231         } else {
8232                 /* Create a GENEVE TLV object and resource. */
8233                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8234                                 geneve_opt_v->option_class,
8235                                 geneve_opt_v->option_type,
8236                                 geneve_opt_v->option_len);
8237                 if (!obj) {
8238                         ret = rte_flow_error_set(error, ENODATA,
8239                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8240                                 "Failed to create GENEVE TLV Devx object");
8241                         goto exit;
8242                 }
8243                 sh->geneve_tlv_option_resource =
8244                                 mlx5_malloc(MLX5_MEM_ZERO,
8245                                                 sizeof(*geneve_opt_resource),
8246                                                 0, SOCKET_ID_ANY);
8247                 if (!sh->geneve_tlv_option_resource) {
8248                         claim_zero(mlx5_devx_cmd_destroy(obj));
8249                         ret = rte_flow_error_set(error, ENOMEM,
8250                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8251                                 "GENEVE TLV object memory allocation failed");
8252                         goto exit;
8253                 }
8254                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8255                 geneve_opt_resource->obj = obj;
8256                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8257                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8258                 geneve_opt_resource->length = geneve_opt_v->option_len;
8259                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8260                                 __ATOMIC_RELAXED);
8261         }
8262 exit:
8263         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8264         return ret;
8265 }
8266
8267 /**
8268  * Add Geneve TLV option item to matcher.
8269  *
8270  * @param[in, out] dev
8271  *   Pointer to rte_eth_dev structure.
8272  * @param[in, out] matcher
8273  *   Flow matcher.
8274  * @param[in, out] key
8275  *   Flow matcher value.
8276  * @param[in] item
8277  *   Flow pattern to translate.
8278  * @param[out] error
8279  *   Pointer to error structure.
8280  */
8281 static int
8282 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8283                                   void *key, const struct rte_flow_item *item,
8284                                   struct rte_flow_error *error)
8285 {
8286         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8287         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8288         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8289         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8290         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8291                         misc_parameters_3);
8292         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8293         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8294         int ret = 0;
8295
8296         if (!geneve_opt_v)
8297                 return -1;
8298         if (!geneve_opt_m)
8299                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8300         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8301                                                            error);
8302         if (ret) {
8303                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8304                 return ret;
8305         }
8306         /*
8307          * Set the option length in GENEVE header if not requested.
8308          * The GENEVE TLV option length is expressed by the option length field
8309          * in the GENEVE header.
8310          * If the option length was not requested but the GENEVE TLV option item
8311          * is present we set the option length field implicitly.
8312          */
8313         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8314                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8315                          MLX5_GENEVE_OPTLEN_MASK);
8316                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8317                          geneve_opt_v->option_len + 1);
8318         }
8319         /* Set the data. */
8320         if (geneve_opt_v->data) {
8321                 memcpy(&opt_data_key, geneve_opt_v->data,
8322                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8323                                 sizeof(opt_data_key)));
8324                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8325                                 sizeof(opt_data_key));
8326                 memcpy(&opt_data_mask, geneve_opt_m->data,
8327                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8328                                 sizeof(opt_data_mask)));
8329                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8330                                 sizeof(opt_data_mask));
8331                 MLX5_SET(fte_match_set_misc3, misc3_m,
8332                                 geneve_tlv_option_0_data,
8333                                 rte_be_to_cpu_32(opt_data_mask));
8334                 MLX5_SET(fte_match_set_misc3, misc3_v,
8335                                 geneve_tlv_option_0_data,
8336                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8337         }
8338         return ret;
8339 }
8340
8341 /**
8342  * Add MPLS item to matcher and to the value.
8343  *
8344  * @param[in, out] matcher
8345  *   Flow matcher.
8346  * @param[in, out] key
8347  *   Flow matcher value.
8348  * @param[in] item
8349  *   Flow pattern to translate.
8350  * @param[in] prev_layer
8351  *   The protocol layer indicated in previous item.
8352  * @param[in] inner
8353  *   Item is inner pattern.
8354  */
8355 static void
8356 flow_dv_translate_item_mpls(void *matcher, void *key,
8357                             const struct rte_flow_item *item,
8358                             uint64_t prev_layer,
8359                             int inner)
8360 {
8361         const uint32_t *in_mpls_m = item->mask;
8362         const uint32_t *in_mpls_v = item->spec;
8363         uint32_t *out_mpls_m = 0;
8364         uint32_t *out_mpls_v = 0;
8365         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8366         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8367         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8368                                      misc_parameters_2);
8369         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8370         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8371         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8372
8373         switch (prev_layer) {
8374         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8375                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8376                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8377                          MLX5_UDP_PORT_MPLS);
8378                 break;
8379         case MLX5_FLOW_LAYER_GRE:
8380                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8381                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8382                          RTE_ETHER_TYPE_MPLS);
8383                 break;
8384         default:
8385                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8386                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8387                          IPPROTO_MPLS);
8388                 break;
8389         }
8390         if (!in_mpls_v)
8391                 return;
8392         if (!in_mpls_m)
8393                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8394         switch (prev_layer) {
8395         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8396                 out_mpls_m =
8397                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8398                                                  outer_first_mpls_over_udp);
8399                 out_mpls_v =
8400                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8401                                                  outer_first_mpls_over_udp);
8402                 break;
8403         case MLX5_FLOW_LAYER_GRE:
8404                 out_mpls_m =
8405                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8406                                                  outer_first_mpls_over_gre);
8407                 out_mpls_v =
8408                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8409                                                  outer_first_mpls_over_gre);
8410                 break;
8411         default:
8412                 /* Inner MPLS not over GRE is not supported. */
8413                 if (!inner) {
8414                         out_mpls_m =
8415                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8416                                                          misc2_m,
8417                                                          outer_first_mpls);
8418                         out_mpls_v =
8419                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8420                                                          misc2_v,
8421                                                          outer_first_mpls);
8422                 }
8423                 break;
8424         }
8425         if (out_mpls_m && out_mpls_v) {
8426                 *out_mpls_m = *in_mpls_m;
8427                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8428         }
8429 }
8430
8431 /**
8432  * Add metadata register item to matcher
8433  *
8434  * @param[in, out] matcher
8435  *   Flow matcher.
8436  * @param[in, out] key
8437  *   Flow matcher value.
8438  * @param[in] reg_type
8439  *   Type of device metadata register
8440  * @param[in] value
8441  *   Register value
8442  * @param[in] mask
8443  *   Register mask
8444  */
8445 static void
8446 flow_dv_match_meta_reg(void *matcher, void *key,
8447                        enum modify_reg reg_type,
8448                        uint32_t data, uint32_t mask)
8449 {
8450         void *misc2_m =
8451                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8452         void *misc2_v =
8453                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8454         uint32_t temp;
8455
8456         data &= mask;
8457         switch (reg_type) {
8458         case REG_A:
8459                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8460                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8461                 break;
8462         case REG_B:
8463                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8464                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8465                 break;
8466         case REG_C_0:
8467                 /*
8468                  * The metadata register C0 field might be divided into
8469                  * source vport index and META item value, we should set
8470                  * this field according to specified mask, not as whole one.
8471                  */
8472                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8473                 temp |= mask;
8474                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8475                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8476                 temp &= ~mask;
8477                 temp |= data;
8478                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8479                 break;
8480         case REG_C_1:
8481                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8482                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8483                 break;
8484         case REG_C_2:
8485                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8486                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8487                 break;
8488         case REG_C_3:
8489                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8490                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8491                 break;
8492         case REG_C_4:
8493                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8494                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8495                 break;
8496         case REG_C_5:
8497                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8498                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8499                 break;
8500         case REG_C_6:
8501                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8502                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8503                 break;
8504         case REG_C_7:
8505                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8506                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8507                 break;
8508         default:
8509                 MLX5_ASSERT(false);
8510                 break;
8511         }
8512 }
8513
8514 /**
8515  * Add MARK item to matcher
8516  *
8517  * @param[in] dev
8518  *   The device to configure through.
8519  * @param[in, out] matcher
8520  *   Flow matcher.
8521  * @param[in, out] key
8522  *   Flow matcher value.
8523  * @param[in] item
8524  *   Flow pattern to translate.
8525  */
8526 static void
8527 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8528                             void *matcher, void *key,
8529                             const struct rte_flow_item *item)
8530 {
8531         struct mlx5_priv *priv = dev->data->dev_private;
8532         const struct rte_flow_item_mark *mark;
8533         uint32_t value;
8534         uint32_t mask;
8535
8536         mark = item->mask ? (const void *)item->mask :
8537                             &rte_flow_item_mark_mask;
8538         mask = mark->id & priv->sh->dv_mark_mask;
8539         mark = (const void *)item->spec;
8540         MLX5_ASSERT(mark);
8541         value = mark->id & priv->sh->dv_mark_mask & mask;
8542         if (mask) {
8543                 enum modify_reg reg;
8544
8545                 /* Get the metadata register index for the mark. */
8546                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8547                 MLX5_ASSERT(reg > 0);
8548                 if (reg == REG_C_0) {
8549                         struct mlx5_priv *priv = dev->data->dev_private;
8550                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8551                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8552
8553                         mask &= msk_c0;
8554                         mask <<= shl_c0;
8555                         value <<= shl_c0;
8556                 }
8557                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8558         }
8559 }
8560
8561 /**
8562  * Add META item to matcher
8563  *
8564  * @param[in] dev
8565  *   The devich to configure through.
8566  * @param[in, out] matcher
8567  *   Flow matcher.
8568  * @param[in, out] key
8569  *   Flow matcher value.
8570  * @param[in] attr
8571  *   Attributes of flow that includes this item.
8572  * @param[in] item
8573  *   Flow pattern to translate.
8574  */
8575 static void
8576 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8577                             void *matcher, void *key,
8578                             const struct rte_flow_attr *attr,
8579                             const struct rte_flow_item *item)
8580 {
8581         const struct rte_flow_item_meta *meta_m;
8582         const struct rte_flow_item_meta *meta_v;
8583
8584         meta_m = (const void *)item->mask;
8585         if (!meta_m)
8586                 meta_m = &rte_flow_item_meta_mask;
8587         meta_v = (const void *)item->spec;
8588         if (meta_v) {
8589                 int reg;
8590                 uint32_t value = meta_v->data;
8591                 uint32_t mask = meta_m->data;
8592
8593                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8594                 if (reg < 0)
8595                         return;
8596                 MLX5_ASSERT(reg != REG_NON);
8597                 /*
8598                  * In datapath code there is no endianness
8599                  * coversions for perfromance reasons, all
8600                  * pattern conversions are done in rte_flow.
8601                  */
8602                 value = rte_cpu_to_be_32(value);
8603                 mask = rte_cpu_to_be_32(mask);
8604                 if (reg == REG_C_0) {
8605                         struct mlx5_priv *priv = dev->data->dev_private;
8606                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8607                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8608 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8609                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8610
8611                         value >>= shr_c0;
8612                         mask >>= shr_c0;
8613 #endif
8614                         value <<= shl_c0;
8615                         mask <<= shl_c0;
8616                         MLX5_ASSERT(msk_c0);
8617                         MLX5_ASSERT(!(~msk_c0 & mask));
8618                 }
8619                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8620         }
8621 }
8622
8623 /**
8624  * Add vport metadata Reg C0 item to matcher
8625  *
8626  * @param[in, out] matcher
8627  *   Flow matcher.
8628  * @param[in, out] key
8629  *   Flow matcher value.
8630  * @param[in] reg
8631  *   Flow pattern to translate.
8632  */
8633 static void
8634 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8635                                   uint32_t value, uint32_t mask)
8636 {
8637         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8638 }
8639
8640 /**
8641  * Add tag item to matcher
8642  *
8643  * @param[in] dev
8644  *   The devich to configure through.
8645  * @param[in, out] matcher
8646  *   Flow matcher.
8647  * @param[in, out] key
8648  *   Flow matcher value.
8649  * @param[in] item
8650  *   Flow pattern to translate.
8651  */
8652 static void
8653 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8654                                 void *matcher, void *key,
8655                                 const struct rte_flow_item *item)
8656 {
8657         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8658         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8659         uint32_t mask, value;
8660
8661         MLX5_ASSERT(tag_v);
8662         value = tag_v->data;
8663         mask = tag_m ? tag_m->data : UINT32_MAX;
8664         if (tag_v->id == REG_C_0) {
8665                 struct mlx5_priv *priv = dev->data->dev_private;
8666                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8667                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8668
8669                 mask &= msk_c0;
8670                 mask <<= shl_c0;
8671                 value <<= shl_c0;
8672         }
8673         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8674 }
8675
8676 /**
8677  * Add TAG item to matcher
8678  *
8679  * @param[in] dev
8680  *   The devich to configure through.
8681  * @param[in, out] matcher
8682  *   Flow matcher.
8683  * @param[in, out] key
8684  *   Flow matcher value.
8685  * @param[in] item
8686  *   Flow pattern to translate.
8687  */
8688 static void
8689 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8690                            void *matcher, void *key,
8691                            const struct rte_flow_item *item)
8692 {
8693         const struct rte_flow_item_tag *tag_v = item->spec;
8694         const struct rte_flow_item_tag *tag_m = item->mask;
8695         enum modify_reg reg;
8696
8697         MLX5_ASSERT(tag_v);
8698         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8699         /* Get the metadata register index for the tag. */
8700         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8701         MLX5_ASSERT(reg > 0);
8702         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8703 }
8704
8705 /**
8706  * Add source vport match to the specified matcher.
8707  *
8708  * @param[in, out] matcher
8709  *   Flow matcher.
8710  * @param[in, out] key
8711  *   Flow matcher value.
8712  * @param[in] port
8713  *   Source vport value to match
8714  * @param[in] mask
8715  *   Mask
8716  */
8717 static void
8718 flow_dv_translate_item_source_vport(void *matcher, void *key,
8719                                     int16_t port, uint16_t mask)
8720 {
8721         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8722         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8723
8724         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8725         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8726 }
8727
8728 /**
8729  * Translate port-id item to eswitch match on  port-id.
8730  *
8731  * @param[in] dev
8732  *   The devich to configure through.
8733  * @param[in, out] matcher
8734  *   Flow matcher.
8735  * @param[in, out] key
8736  *   Flow matcher value.
8737  * @param[in] item
8738  *   Flow pattern to translate.
8739  * @param[in]
8740  *   Flow attributes.
8741  *
8742  * @return
8743  *   0 on success, a negative errno value otherwise.
8744  */
8745 static int
8746 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8747                                void *key, const struct rte_flow_item *item,
8748                                const struct rte_flow_attr *attr)
8749 {
8750         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8751         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8752         struct mlx5_priv *priv;
8753         uint16_t mask, id;
8754
8755         mask = pid_m ? pid_m->id : 0xffff;
8756         id = pid_v ? pid_v->id : dev->data->port_id;
8757         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8758         if (!priv)
8759                 return -rte_errno;
8760         /*
8761          * Translate to vport field or to metadata, depending on mode.
8762          * Kernel can use either misc.source_port or half of C0 metadata
8763          * register.
8764          */
8765         if (priv->vport_meta_mask) {
8766                 /*
8767                  * Provide the hint for SW steering library
8768                  * to insert the flow into ingress domain and
8769                  * save the extra vport match.
8770                  */
8771                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8772                     priv->pf_bond < 0 && attr->transfer)
8773                         flow_dv_translate_item_source_vport
8774                                 (matcher, key, priv->vport_id, mask);
8775                 /*
8776                  * We should always set the vport metadata register,
8777                  * otherwise the SW steering library can drop
8778                  * the rule if wire vport metadata value is not zero,
8779                  * it depends on kernel configuration.
8780                  */
8781                 flow_dv_translate_item_meta_vport(matcher, key,
8782                                                   priv->vport_meta_tag,
8783                                                   priv->vport_meta_mask);
8784         } else {
8785                 flow_dv_translate_item_source_vport(matcher, key,
8786                                                     priv->vport_id, mask);
8787         }
8788         return 0;
8789 }
8790
8791 /**
8792  * Add ICMP6 item to matcher and to the value.
8793  *
8794  * @param[in, out] matcher
8795  *   Flow matcher.
8796  * @param[in, out] key
8797  *   Flow matcher value.
8798  * @param[in] item
8799  *   Flow pattern to translate.
8800  * @param[in] inner
8801  *   Item is inner pattern.
8802  */
8803 static void
8804 flow_dv_translate_item_icmp6(void *matcher, void *key,
8805                               const struct rte_flow_item *item,
8806                               int inner)
8807 {
8808         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8809         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8810         void *headers_m;
8811         void *headers_v;
8812         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8813                                      misc_parameters_3);
8814         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8815         if (inner) {
8816                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8817                                          inner_headers);
8818                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8819         } else {
8820                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8821                                          outer_headers);
8822                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8823         }
8824         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8825         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8826         if (!icmp6_v)
8827                 return;
8828         if (!icmp6_m)
8829                 icmp6_m = &rte_flow_item_icmp6_mask;
8830         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8831         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8832                  icmp6_v->type & icmp6_m->type);
8833         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8834         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8835                  icmp6_v->code & icmp6_m->code);
8836 }
8837
8838 /**
8839  * Add ICMP item to matcher and to the value.
8840  *
8841  * @param[in, out] matcher
8842  *   Flow matcher.
8843  * @param[in, out] key
8844  *   Flow matcher value.
8845  * @param[in] item
8846  *   Flow pattern to translate.
8847  * @param[in] inner
8848  *   Item is inner pattern.
8849  */
8850 static void
8851 flow_dv_translate_item_icmp(void *matcher, void *key,
8852                             const struct rte_flow_item *item,
8853                             int inner)
8854 {
8855         const struct rte_flow_item_icmp *icmp_m = item->mask;
8856         const struct rte_flow_item_icmp *icmp_v = item->spec;
8857         uint32_t icmp_header_data_m = 0;
8858         uint32_t icmp_header_data_v = 0;
8859         void *headers_m;
8860         void *headers_v;
8861         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8862                                      misc_parameters_3);
8863         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8864         if (inner) {
8865                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8866                                          inner_headers);
8867                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8868         } else {
8869                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8870                                          outer_headers);
8871                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8872         }
8873         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8874         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8875         if (!icmp_v)
8876                 return;
8877         if (!icmp_m)
8878                 icmp_m = &rte_flow_item_icmp_mask;
8879         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8880                  icmp_m->hdr.icmp_type);
8881         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8882                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8883         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8884                  icmp_m->hdr.icmp_code);
8885         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8886                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8887         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8888         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8889         if (icmp_header_data_m) {
8890                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8891                 icmp_header_data_v |=
8892                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8893                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8894                          icmp_header_data_m);
8895                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8896                          icmp_header_data_v & icmp_header_data_m);
8897         }
8898 }
8899
8900 /**
8901  * Add GTP item to matcher and to the value.
8902  *
8903  * @param[in, out] matcher
8904  *   Flow matcher.
8905  * @param[in, out] key
8906  *   Flow matcher value.
8907  * @param[in] item
8908  *   Flow pattern to translate.
8909  * @param[in] inner
8910  *   Item is inner pattern.
8911  */
8912 static void
8913 flow_dv_translate_item_gtp(void *matcher, void *key,
8914                            const struct rte_flow_item *item, int inner)
8915 {
8916         const struct rte_flow_item_gtp *gtp_m = item->mask;
8917         const struct rte_flow_item_gtp *gtp_v = item->spec;
8918         void *headers_m;
8919         void *headers_v;
8920         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8921                                      misc_parameters_3);
8922         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8923         uint16_t dport = RTE_GTPU_UDP_PORT;
8924
8925         if (inner) {
8926                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8927                                          inner_headers);
8928                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8929         } else {
8930                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8931                                          outer_headers);
8932                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8933         }
8934         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8935                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8936                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8937         }
8938         if (!gtp_v)
8939                 return;
8940         if (!gtp_m)
8941                 gtp_m = &rte_flow_item_gtp_mask;
8942         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8943                  gtp_m->v_pt_rsv_flags);
8944         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8945                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8946         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8947         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8948                  gtp_v->msg_type & gtp_m->msg_type);
8949         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8950                  rte_be_to_cpu_32(gtp_m->teid));
8951         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8952                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8953 }
8954
8955 /**
8956  * Add GTP PSC item to matcher.
8957  *
8958  * @param[in, out] matcher
8959  *   Flow matcher.
8960  * @param[in, out] key
8961  *   Flow matcher value.
8962  * @param[in] item
8963  *   Flow pattern to translate.
8964  */
8965 static int
8966 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8967                                const struct rte_flow_item *item)
8968 {
8969         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8970         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8971         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8972                         misc_parameters_3);
8973         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8974         union {
8975                 uint32_t w32;
8976                 struct {
8977                         uint16_t seq_num;
8978                         uint8_t npdu_num;
8979                         uint8_t next_ext_header_type;
8980                 };
8981         } dw_2;
8982         uint8_t gtp_flags;
8983
8984         /* Always set E-flag match on one, regardless of GTP item settings. */
8985         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8986         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8987         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8988         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8989         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8990         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8991         /*Set next extension header type. */
8992         dw_2.seq_num = 0;
8993         dw_2.npdu_num = 0;
8994         dw_2.next_ext_header_type = 0xff;
8995         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8996                  rte_cpu_to_be_32(dw_2.w32));
8997         dw_2.seq_num = 0;
8998         dw_2.npdu_num = 0;
8999         dw_2.next_ext_header_type = 0x85;
9000         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9001                  rte_cpu_to_be_32(dw_2.w32));
9002         if (gtp_psc_v) {
9003                 union {
9004                         uint32_t w32;
9005                         struct {
9006                                 uint8_t len;
9007                                 uint8_t type_flags;
9008                                 uint8_t qfi;
9009                                 uint8_t reserved;
9010                         };
9011                 } dw_0;
9012
9013                 /*Set extension header PDU type and Qos. */
9014                 if (!gtp_psc_m)
9015                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9016                 dw_0.w32 = 0;
9017                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9018                 dw_0.qfi = gtp_psc_m->qfi;
9019                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9020                          rte_cpu_to_be_32(dw_0.w32));
9021                 dw_0.w32 = 0;
9022                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9023                                                         gtp_psc_m->pdu_type);
9024                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9025                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9026                          rte_cpu_to_be_32(dw_0.w32));
9027         }
9028         return 0;
9029 }
9030
9031 /**
9032  * Add eCPRI item to matcher and to the value.
9033  *
9034  * @param[in] dev
9035  *   The devich to configure through.
9036  * @param[in, out] matcher
9037  *   Flow matcher.
9038  * @param[in, out] key
9039  *   Flow matcher value.
9040  * @param[in] item
9041  *   Flow pattern to translate.
9042  * @param[in] samples
9043  *   Sample IDs to be used in the matching.
9044  */
9045 static void
9046 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9047                              void *key, const struct rte_flow_item *item)
9048 {
9049         struct mlx5_priv *priv = dev->data->dev_private;
9050         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9051         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9052         struct rte_ecpri_common_hdr common;
9053         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9054                                      misc_parameters_4);
9055         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9056         uint32_t *samples;
9057         void *dw_m;
9058         void *dw_v;
9059
9060         if (!ecpri_v)
9061                 return;
9062         if (!ecpri_m)
9063                 ecpri_m = &rte_flow_item_ecpri_mask;
9064         /*
9065          * Maximal four DW samples are supported in a single matching now.
9066          * Two are used now for a eCPRI matching:
9067          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9068          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9069          *    if any.
9070          */
9071         if (!ecpri_m->hdr.common.u32)
9072                 return;
9073         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9074         /* Need to take the whole DW as the mask to fill the entry. */
9075         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9076                             prog_sample_field_value_0);
9077         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9078                             prog_sample_field_value_0);
9079         /* Already big endian (network order) in the header. */
9080         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9081         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9082         /* Sample#0, used for matching type, offset 0. */
9083         MLX5_SET(fte_match_set_misc4, misc4_m,
9084                  prog_sample_field_id_0, samples[0]);
9085         /* It makes no sense to set the sample ID in the mask field. */
9086         MLX5_SET(fte_match_set_misc4, misc4_v,
9087                  prog_sample_field_id_0, samples[0]);
9088         /*
9089          * Checking if message body part needs to be matched.
9090          * Some wildcard rules only matching type field should be supported.
9091          */
9092         if (ecpri_m->hdr.dummy[0]) {
9093                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9094                 switch (common.type) {
9095                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9096                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9097                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9098                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9099                                             prog_sample_field_value_1);
9100                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9101                                             prog_sample_field_value_1);
9102                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9103                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9104                                             ecpri_m->hdr.dummy[0];
9105                         /* Sample#1, to match message body, offset 4. */
9106                         MLX5_SET(fte_match_set_misc4, misc4_m,
9107                                  prog_sample_field_id_1, samples[1]);
9108                         MLX5_SET(fte_match_set_misc4, misc4_v,
9109                                  prog_sample_field_id_1, samples[1]);
9110                         break;
9111                 default:
9112                         /* Others, do not match any sample ID. */
9113                         break;
9114                 }
9115         }
9116 }
9117
9118 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9119
9120 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9121         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9122                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9123
9124 /**
9125  * Calculate flow matcher enable bitmap.
9126  *
9127  * @param match_criteria
9128  *   Pointer to flow matcher criteria.
9129  *
9130  * @return
9131  *   Bitmap of enabled fields.
9132  */
9133 static uint8_t
9134 flow_dv_matcher_enable(uint32_t *match_criteria)
9135 {
9136         uint8_t match_criteria_enable;
9137
9138         match_criteria_enable =
9139                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9140                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9141         match_criteria_enable |=
9142                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9143                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9144         match_criteria_enable |=
9145                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9146                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9147         match_criteria_enable |=
9148                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9149                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9150         match_criteria_enable |=
9151                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9152                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9153         match_criteria_enable |=
9154                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9155                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9156         return match_criteria_enable;
9157 }
9158
9159 struct mlx5_hlist_entry *
9160 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9161 {
9162         struct mlx5_dev_ctx_shared *sh = list->ctx;
9163         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9164         struct rte_eth_dev *dev = ctx->dev;
9165         struct mlx5_flow_tbl_data_entry *tbl_data;
9166         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9167         struct rte_flow_error *error = ctx->error;
9168         union mlx5_flow_tbl_key key = { .v64 = key64 };
9169         struct mlx5_flow_tbl_resource *tbl;
9170         void *domain;
9171         uint32_t idx = 0;
9172         int ret;
9173
9174         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9175         if (!tbl_data) {
9176                 rte_flow_error_set(error, ENOMEM,
9177                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9178                                    NULL,
9179                                    "cannot allocate flow table data entry");
9180                 return NULL;
9181         }
9182         tbl_data->idx = idx;
9183         tbl_data->tunnel = tt_prm->tunnel;
9184         tbl_data->group_id = tt_prm->group_id;
9185         tbl_data->external = !!tt_prm->external;
9186         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9187         tbl_data->is_egress = !!key.direction;
9188         tbl_data->is_transfer = !!key.domain;
9189         tbl_data->dummy = !!key.dummy;
9190         tbl_data->table_id = key.table_id;
9191         tbl = &tbl_data->tbl;
9192         if (key.dummy)
9193                 return &tbl_data->entry;
9194         if (key.domain)
9195                 domain = sh->fdb_domain;
9196         else if (key.direction)
9197                 domain = sh->tx_domain;
9198         else
9199                 domain = sh->rx_domain;
9200         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9201         if (ret) {
9202                 rte_flow_error_set(error, ENOMEM,
9203                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9204                                    NULL, "cannot create flow table object");
9205                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9206                 return NULL;
9207         }
9208         if (key.table_id) {
9209                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9210                                         (tbl->obj, &tbl_data->jump.action);
9211                 if (ret) {
9212                         rte_flow_error_set(error, ENOMEM,
9213                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9214                                            NULL,
9215                                            "cannot create flow jump action");
9216                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9217                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9218                         return NULL;
9219                 }
9220         }
9221         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9222               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9223               key.table_id);
9224         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9225                              flow_dv_matcher_create_cb,
9226                              flow_dv_matcher_match_cb,
9227                              flow_dv_matcher_remove_cb);
9228         return &tbl_data->entry;
9229 }
9230
9231 int
9232 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9233                      struct mlx5_hlist_entry *entry, uint64_t key64,
9234                      void *cb_ctx __rte_unused)
9235 {
9236         struct mlx5_flow_tbl_data_entry *tbl_data =
9237                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9238         union mlx5_flow_tbl_key key = { .v64 = key64 };
9239
9240         return tbl_data->table_id != key.table_id ||
9241                tbl_data->dummy != key.dummy ||
9242                tbl_data->is_transfer != key.domain ||
9243                tbl_data->is_egress != key.direction;
9244 }
9245
9246 /**
9247  * Get a flow table.
9248  *
9249  * @param[in, out] dev
9250  *   Pointer to rte_eth_dev structure.
9251  * @param[in] table_id
9252  *   Table id to use.
9253  * @param[in] egress
9254  *   Direction of the table.
9255  * @param[in] transfer
9256  *   E-Switch or NIC flow.
9257  * @param[in] dummy
9258  *   Dummy entry for dv API.
9259  * @param[out] error
9260  *   pointer to error structure.
9261  *
9262  * @return
9263  *   Returns tables resource based on the index, NULL in case of failed.
9264  */
9265 struct mlx5_flow_tbl_resource *
9266 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9267                          uint32_t table_id, uint8_t egress,
9268                          uint8_t transfer,
9269                          bool external,
9270                          const struct mlx5_flow_tunnel *tunnel,
9271                          uint32_t group_id, uint8_t dummy,
9272                          struct rte_flow_error *error)
9273 {
9274         struct mlx5_priv *priv = dev->data->dev_private;
9275         union mlx5_flow_tbl_key table_key = {
9276                 {
9277                         .table_id = table_id,
9278                         .dummy = dummy,
9279                         .domain = !!transfer,
9280                         .direction = !!egress,
9281                 }
9282         };
9283         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9284                 .tunnel = tunnel,
9285                 .group_id = group_id,
9286                 .external = external,
9287         };
9288         struct mlx5_flow_cb_ctx ctx = {
9289                 .dev = dev,
9290                 .error = error,
9291                 .data = &tt_prm,
9292         };
9293         struct mlx5_hlist_entry *entry;
9294         struct mlx5_flow_tbl_data_entry *tbl_data;
9295
9296         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9297         if (!entry) {
9298                 rte_flow_error_set(error, ENOMEM,
9299                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9300                                    "cannot get table");
9301                 return NULL;
9302         }
9303         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9304                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9305         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9306         return &tbl_data->tbl;
9307 }
9308
9309 void
9310 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9311                       struct mlx5_hlist_entry *entry)
9312 {
9313         struct mlx5_dev_ctx_shared *sh = list->ctx;
9314         struct mlx5_flow_tbl_data_entry *tbl_data =
9315                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9316
9317         MLX5_ASSERT(entry && sh);
9318         if (tbl_data->jump.action)
9319                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9320         if (tbl_data->tbl.obj)
9321                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9322         if (tbl_data->tunnel_offload && tbl_data->external) {
9323                 struct mlx5_hlist_entry *he;
9324                 struct mlx5_hlist *tunnel_grp_hash;
9325                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9326                 union tunnel_tbl_key tunnel_key = {
9327                         .tunnel_id = tbl_data->tunnel ?
9328                                         tbl_data->tunnel->tunnel_id : 0,
9329                         .group = tbl_data->group_id
9330                 };
9331                 uint32_t table_id = tbl_data->table_id;
9332
9333                 tunnel_grp_hash = tbl_data->tunnel ?
9334                                         tbl_data->tunnel->groups :
9335                                         thub->groups;
9336                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9337                 if (he)
9338                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9339                 DRV_LOG(DEBUG,
9340                         "Table_id %u tunnel %u group %u released.",
9341                         table_id,
9342                         tbl_data->tunnel ?
9343                         tbl_data->tunnel->tunnel_id : 0,
9344                         tbl_data->group_id);
9345         }
9346         mlx5_cache_list_destroy(&tbl_data->matchers);
9347         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9348 }
9349
9350 /**
9351  * Release a flow table.
9352  *
9353  * @param[in] sh
9354  *   Pointer to device shared structure.
9355  * @param[in] tbl
9356  *   Table resource to be released.
9357  *
9358  * @return
9359  *   Returns 0 if table was released, else return 1;
9360  */
9361 static int
9362 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9363                              struct mlx5_flow_tbl_resource *tbl)
9364 {
9365         struct mlx5_flow_tbl_data_entry *tbl_data =
9366                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9367
9368         if (!tbl)
9369                 return 0;
9370         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9371 }
9372
9373 int
9374 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9375                          struct mlx5_cache_entry *entry, void *cb_ctx)
9376 {
9377         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9378         struct mlx5_flow_dv_matcher *ref = ctx->data;
9379         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9380                                                         entry);
9381
9382         return cur->crc != ref->crc ||
9383                cur->priority != ref->priority ||
9384                memcmp((const void *)cur->mask.buf,
9385                       (const void *)ref->mask.buf, ref->mask.size);
9386 }
9387
9388 struct mlx5_cache_entry *
9389 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9390                           struct mlx5_cache_entry *entry __rte_unused,
9391                           void *cb_ctx)
9392 {
9393         struct mlx5_dev_ctx_shared *sh = list->ctx;
9394         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9395         struct mlx5_flow_dv_matcher *ref = ctx->data;
9396         struct mlx5_flow_dv_matcher *cache;
9397         struct mlx5dv_flow_matcher_attr dv_attr = {
9398                 .type = IBV_FLOW_ATTR_NORMAL,
9399                 .match_mask = (void *)&ref->mask,
9400         };
9401         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9402                                                             typeof(*tbl), tbl);
9403         int ret;
9404
9405         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9406         if (!cache) {
9407                 rte_flow_error_set(ctx->error, ENOMEM,
9408                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9409                                    "cannot create matcher");
9410                 return NULL;
9411         }
9412         *cache = *ref;
9413         dv_attr.match_criteria_enable =
9414                 flow_dv_matcher_enable(cache->mask.buf);
9415         dv_attr.priority = ref->priority;
9416         if (tbl->is_egress)
9417                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9418         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9419                                                &cache->matcher_object);
9420         if (ret) {
9421                 mlx5_free(cache);
9422                 rte_flow_error_set(ctx->error, ENOMEM,
9423                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9424                                    "cannot create matcher");
9425                 return NULL;
9426         }
9427         return &cache->entry;
9428 }
9429
9430 /**
9431  * Register the flow matcher.
9432  *
9433  * @param[in, out] dev
9434  *   Pointer to rte_eth_dev structure.
9435  * @param[in, out] matcher
9436  *   Pointer to flow matcher.
9437  * @param[in, out] key
9438  *   Pointer to flow table key.
9439  * @parm[in, out] dev_flow
9440  *   Pointer to the dev_flow.
9441  * @param[out] error
9442  *   pointer to error structure.
9443  *
9444  * @return
9445  *   0 on success otherwise -errno and errno is set.
9446  */
9447 static int
9448 flow_dv_matcher_register(struct rte_eth_dev *dev,
9449                          struct mlx5_flow_dv_matcher *ref,
9450                          union mlx5_flow_tbl_key *key,
9451                          struct mlx5_flow *dev_flow,
9452                          const struct mlx5_flow_tunnel *tunnel,
9453                          uint32_t group_id,
9454                          struct rte_flow_error *error)
9455 {
9456         struct mlx5_cache_entry *entry;
9457         struct mlx5_flow_dv_matcher *cache;
9458         struct mlx5_flow_tbl_resource *tbl;
9459         struct mlx5_flow_tbl_data_entry *tbl_data;
9460         struct mlx5_flow_cb_ctx ctx = {
9461                 .error = error,
9462                 .data = ref,
9463         };
9464
9465         /**
9466          * tunnel offload API requires this registration for cases when
9467          * tunnel match rule was inserted before tunnel set rule.
9468          */
9469         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9470                                        key->direction, key->domain,
9471                                        dev_flow->external, tunnel,
9472                                        group_id, 0, error);
9473         if (!tbl)
9474                 return -rte_errno;      /* No need to refill the error info */
9475         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9476         ref->tbl = tbl;
9477         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9478         if (!entry) {
9479                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9480                 return rte_flow_error_set(error, ENOMEM,
9481                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9482                                           "cannot allocate ref memory");
9483         }
9484         cache = container_of(entry, typeof(*cache), entry);
9485         dev_flow->handle->dvh.matcher = cache;
9486         return 0;
9487 }
9488
9489 struct mlx5_hlist_entry *
9490 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9491 {
9492         struct mlx5_dev_ctx_shared *sh = list->ctx;
9493         struct rte_flow_error *error = ctx;
9494         struct mlx5_flow_dv_tag_resource *entry;
9495         uint32_t idx = 0;
9496         int ret;
9497
9498         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9499         if (!entry) {
9500                 rte_flow_error_set(error, ENOMEM,
9501                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9502                                    "cannot allocate resource memory");
9503                 return NULL;
9504         }
9505         entry->idx = idx;
9506         entry->tag_id = key;
9507         ret = mlx5_flow_os_create_flow_action_tag(key,
9508                                                   &entry->action);
9509         if (ret) {
9510                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9511                 rte_flow_error_set(error, ENOMEM,
9512                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9513                                    NULL, "cannot create action");
9514                 return NULL;
9515         }
9516         return &entry->entry;
9517 }
9518
9519 int
9520 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9521                      struct mlx5_hlist_entry *entry, uint64_t key,
9522                      void *cb_ctx __rte_unused)
9523 {
9524         struct mlx5_flow_dv_tag_resource *tag =
9525                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9526
9527         return key != tag->tag_id;
9528 }
9529
9530 /**
9531  * Find existing tag resource or create and register a new one.
9532  *
9533  * @param dev[in, out]
9534  *   Pointer to rte_eth_dev structure.
9535  * @param[in, out] tag_be24
9536  *   Tag value in big endian then R-shift 8.
9537  * @parm[in, out] dev_flow
9538  *   Pointer to the dev_flow.
9539  * @param[out] error
9540  *   pointer to error structure.
9541  *
9542  * @return
9543  *   0 on success otherwise -errno and errno is set.
9544  */
9545 static int
9546 flow_dv_tag_resource_register
9547                         (struct rte_eth_dev *dev,
9548                          uint32_t tag_be24,
9549                          struct mlx5_flow *dev_flow,
9550                          struct rte_flow_error *error)
9551 {
9552         struct mlx5_priv *priv = dev->data->dev_private;
9553         struct mlx5_flow_dv_tag_resource *cache_resource;
9554         struct mlx5_hlist_entry *entry;
9555
9556         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9557         if (entry) {
9558                 cache_resource = container_of
9559                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9560                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9561                 dev_flow->dv.tag_resource = cache_resource;
9562                 return 0;
9563         }
9564         return -rte_errno;
9565 }
9566
9567 void
9568 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9569                       struct mlx5_hlist_entry *entry)
9570 {
9571         struct mlx5_dev_ctx_shared *sh = list->ctx;
9572         struct mlx5_flow_dv_tag_resource *tag =
9573                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9574
9575         MLX5_ASSERT(tag && sh && tag->action);
9576         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9577         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9578         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9579 }
9580
9581 /**
9582  * Release the tag.
9583  *
9584  * @param dev
9585  *   Pointer to Ethernet device.
9586  * @param tag_idx
9587  *   Tag index.
9588  *
9589  * @return
9590  *   1 while a reference on it exists, 0 when freed.
9591  */
9592 static int
9593 flow_dv_tag_release(struct rte_eth_dev *dev,
9594                     uint32_t tag_idx)
9595 {
9596         struct mlx5_priv *priv = dev->data->dev_private;
9597         struct mlx5_flow_dv_tag_resource *tag;
9598
9599         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9600         if (!tag)
9601                 return 0;
9602         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9603                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9604         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9605 }
9606
9607 /**
9608  * Translate port ID action to vport.
9609  *
9610  * @param[in] dev
9611  *   Pointer to rte_eth_dev structure.
9612  * @param[in] action
9613  *   Pointer to the port ID action.
9614  * @param[out] dst_port_id
9615  *   The target port ID.
9616  * @param[out] error
9617  *   Pointer to the error structure.
9618  *
9619  * @return
9620  *   0 on success, a negative errno value otherwise and rte_errno is set.
9621  */
9622 static int
9623 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9624                                  const struct rte_flow_action *action,
9625                                  uint32_t *dst_port_id,
9626                                  struct rte_flow_error *error)
9627 {
9628         uint32_t port;
9629         struct mlx5_priv *priv;
9630         const struct rte_flow_action_port_id *conf =
9631                         (const struct rte_flow_action_port_id *)action->conf;
9632
9633         port = conf->original ? dev->data->port_id : conf->id;
9634         priv = mlx5_port_to_eswitch_info(port, false);
9635         if (!priv)
9636                 return rte_flow_error_set(error, -rte_errno,
9637                                           RTE_FLOW_ERROR_TYPE_ACTION,
9638                                           NULL,
9639                                           "No eswitch info was found for port");
9640 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9641         /*
9642          * This parameter is transferred to
9643          * mlx5dv_dr_action_create_dest_ib_port().
9644          */
9645         *dst_port_id = priv->dev_port;
9646 #else
9647         /*
9648          * Legacy mode, no LAG configurations is supported.
9649          * This parameter is transferred to
9650          * mlx5dv_dr_action_create_dest_vport().
9651          */
9652         *dst_port_id = priv->vport_id;
9653 #endif
9654         return 0;
9655 }
9656
9657 /**
9658  * Create a counter with aging configuration.
9659  *
9660  * @param[in] dev
9661  *   Pointer to rte_eth_dev structure.
9662  * @param[out] count
9663  *   Pointer to the counter action configuration.
9664  * @param[in] age
9665  *   Pointer to the aging action configuration.
9666  *
9667  * @return
9668  *   Index to flow counter on success, 0 otherwise.
9669  */
9670 static uint32_t
9671 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9672                                 struct mlx5_flow *dev_flow,
9673                                 const struct rte_flow_action_count *count,
9674                                 const struct rte_flow_action_age *age)
9675 {
9676         uint32_t counter;
9677         struct mlx5_age_param *age_param;
9678
9679         if (count && count->shared)
9680                 counter = flow_dv_counter_get_shared(dev, count->id);
9681         else
9682                 counter = flow_dv_counter_alloc(dev, !!age);
9683         if (!counter || age == NULL)
9684                 return counter;
9685         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9686         age_param->context = age->context ? age->context :
9687                 (void *)(uintptr_t)(dev_flow->flow_idx);
9688         age_param->timeout = age->timeout;
9689         age_param->port_id = dev->data->port_id;
9690         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9691         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9692         return counter;
9693 }
9694
9695 /**
9696  * Add Tx queue matcher
9697  *
9698  * @param[in] dev
9699  *   Pointer to the dev struct.
9700  * @param[in, out] matcher
9701  *   Flow matcher.
9702  * @param[in, out] key
9703  *   Flow matcher value.
9704  * @param[in] item
9705  *   Flow pattern to translate.
9706  * @param[in] inner
9707  *   Item is inner pattern.
9708  */
9709 static void
9710 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9711                                 void *matcher, void *key,
9712                                 const struct rte_flow_item *item)
9713 {
9714         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9715         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9716         void *misc_m =
9717                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9718         void *misc_v =
9719                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9720         struct mlx5_txq_ctrl *txq;
9721         uint32_t queue;
9722
9723
9724         queue_m = (const void *)item->mask;
9725         if (!queue_m)
9726                 return;
9727         queue_v = (const void *)item->spec;
9728         if (!queue_v)
9729                 return;
9730         txq = mlx5_txq_get(dev, queue_v->queue);
9731         if (!txq)
9732                 return;
9733         queue = txq->obj->sq->id;
9734         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9735         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9736                  queue & queue_m->queue);
9737         mlx5_txq_release(dev, queue_v->queue);
9738 }
9739
9740 /**
9741  * Set the hash fields according to the @p flow information.
9742  *
9743  * @param[in] dev_flow
9744  *   Pointer to the mlx5_flow.
9745  * @param[in] rss_desc
9746  *   Pointer to the mlx5_flow_rss_desc.
9747  */
9748 static void
9749 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9750                        struct mlx5_flow_rss_desc *rss_desc)
9751 {
9752         uint64_t items = dev_flow->handle->layers;
9753         int rss_inner = 0;
9754         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9755
9756         dev_flow->hash_fields = 0;
9757 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9758         if (rss_desc->level >= 2) {
9759                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9760                 rss_inner = 1;
9761         }
9762 #endif
9763         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9764             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9765                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9766                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9767                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9768                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9769                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9770                         else
9771                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9772                 }
9773         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9774                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9775                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9776                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9777                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9778                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9779                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9780                         else
9781                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9782                 }
9783         }
9784         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9785             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9786                 if (rss_types & ETH_RSS_UDP) {
9787                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9788                                 dev_flow->hash_fields |=
9789                                                 IBV_RX_HASH_SRC_PORT_UDP;
9790                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9791                                 dev_flow->hash_fields |=
9792                                                 IBV_RX_HASH_DST_PORT_UDP;
9793                         else
9794                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9795                 }
9796         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9797                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9798                 if (rss_types & ETH_RSS_TCP) {
9799                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9800                                 dev_flow->hash_fields |=
9801                                                 IBV_RX_HASH_SRC_PORT_TCP;
9802                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9803                                 dev_flow->hash_fields |=
9804                                                 IBV_RX_HASH_DST_PORT_TCP;
9805                         else
9806                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9807                 }
9808         }
9809 }
9810
9811 /**
9812  * Prepare an Rx Hash queue.
9813  *
9814  * @param dev
9815  *   Pointer to Ethernet device.
9816  * @param[in] dev_flow
9817  *   Pointer to the mlx5_flow.
9818  * @param[in] rss_desc
9819  *   Pointer to the mlx5_flow_rss_desc.
9820  * @param[out] hrxq_idx
9821  *   Hash Rx queue index.
9822  *
9823  * @return
9824  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9825  */
9826 static struct mlx5_hrxq *
9827 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9828                      struct mlx5_flow *dev_flow,
9829                      struct mlx5_flow_rss_desc *rss_desc,
9830                      uint32_t *hrxq_idx)
9831 {
9832         struct mlx5_priv *priv = dev->data->dev_private;
9833         struct mlx5_flow_handle *dh = dev_flow->handle;
9834         struct mlx5_hrxq *hrxq;
9835
9836         MLX5_ASSERT(rss_desc->queue_num);
9837         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9838         rss_desc->hash_fields = dev_flow->hash_fields;
9839         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9840         rss_desc->shared_rss = 0;
9841         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9842         if (!*hrxq_idx)
9843                 return NULL;
9844         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9845                               *hrxq_idx);
9846         return hrxq;
9847 }
9848
9849 /**
9850  * Release sample sub action resource.
9851  *
9852  * @param[in, out] dev
9853  *   Pointer to rte_eth_dev structure.
9854  * @param[in] act_res
9855  *   Pointer to sample sub action resource.
9856  */
9857 static void
9858 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9859                                    struct mlx5_flow_sub_actions_idx *act_res)
9860 {
9861         if (act_res->rix_hrxq) {
9862                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9863                 act_res->rix_hrxq = 0;
9864         }
9865         if (act_res->rix_encap_decap) {
9866                 flow_dv_encap_decap_resource_release(dev,
9867                                                      act_res->rix_encap_decap);
9868                 act_res->rix_encap_decap = 0;
9869         }
9870         if (act_res->rix_port_id_action) {
9871                 flow_dv_port_id_action_resource_release(dev,
9872                                                 act_res->rix_port_id_action);
9873                 act_res->rix_port_id_action = 0;
9874         }
9875         if (act_res->rix_tag) {
9876                 flow_dv_tag_release(dev, act_res->rix_tag);
9877                 act_res->rix_tag = 0;
9878         }
9879         if (act_res->rix_jump) {
9880                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9881                 act_res->rix_jump = 0;
9882         }
9883 }
9884
9885 int
9886 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9887                         struct mlx5_cache_entry *entry, void *cb_ctx)
9888 {
9889         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9890         struct rte_eth_dev *dev = ctx->dev;
9891         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9892         struct mlx5_flow_dv_sample_resource *cache_resource =
9893                         container_of(entry, typeof(*cache_resource), entry);
9894
9895         if (resource->ratio == cache_resource->ratio &&
9896             resource->ft_type == cache_resource->ft_type &&
9897             resource->ft_id == cache_resource->ft_id &&
9898             resource->set_action == cache_resource->set_action &&
9899             !memcmp((void *)&resource->sample_act,
9900                     (void *)&cache_resource->sample_act,
9901                     sizeof(struct mlx5_flow_sub_actions_list))) {
9902                 /*
9903                  * Existing sample action should release the prepared
9904                  * sub-actions reference counter.
9905                  */
9906                 flow_dv_sample_sub_actions_release(dev,
9907                                                 &resource->sample_idx);
9908                 return 0;
9909         }
9910         return 1;
9911 }
9912
9913 struct mlx5_cache_entry *
9914 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9915                          struct mlx5_cache_entry *entry __rte_unused,
9916                          void *cb_ctx)
9917 {
9918         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9919         struct rte_eth_dev *dev = ctx->dev;
9920         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9921         void **sample_dv_actions = resource->sub_actions;
9922         struct mlx5_flow_dv_sample_resource *cache_resource;
9923         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9924         struct mlx5_priv *priv = dev->data->dev_private;
9925         struct mlx5_dev_ctx_shared *sh = priv->sh;
9926         struct mlx5_flow_tbl_resource *tbl;
9927         uint32_t idx = 0;
9928         const uint32_t next_ft_step = 1;
9929         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9930         uint8_t is_egress = 0;
9931         uint8_t is_transfer = 0;
9932         struct rte_flow_error *error = ctx->error;
9933
9934         /* Register new sample resource. */
9935         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9936         if (!cache_resource) {
9937                 rte_flow_error_set(error, ENOMEM,
9938                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9939                                           NULL,
9940                                           "cannot allocate resource memory");
9941                 return NULL;
9942         }
9943         *cache_resource = *resource;
9944         /* Create normal path table level */
9945         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9946                 is_transfer = 1;
9947         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9948                 is_egress = 1;
9949         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9950                                         is_egress, is_transfer,
9951                                         true, NULL, 0, 0, error);
9952         if (!tbl) {
9953                 rte_flow_error_set(error, ENOMEM,
9954                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9955                                           NULL,
9956                                           "fail to create normal path table "
9957                                           "for sample");
9958                 goto error;
9959         }
9960         cache_resource->normal_path_tbl = tbl;
9961         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9962                 if (!sh->default_miss_action) {
9963                         rte_flow_error_set(error, ENOMEM,
9964                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9965                                                 NULL,
9966                                                 "default miss action was not "
9967                                                 "created");
9968                         goto error;
9969                 }
9970                 sample_dv_actions[resource->sample_act.actions_num++] =
9971                                                 sh->default_miss_action;
9972         }
9973         /* Create a DR sample action */
9974         sampler_attr.sample_ratio = cache_resource->ratio;
9975         sampler_attr.default_next_table = tbl->obj;
9976         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9977         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9978                                                         &sample_dv_actions[0];
9979         sampler_attr.action = cache_resource->set_action;
9980         if (mlx5_os_flow_dr_create_flow_action_sampler
9981                         (&sampler_attr, &cache_resource->verbs_action)) {
9982                 rte_flow_error_set(error, ENOMEM,
9983                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9984                                         NULL, "cannot create sample action");
9985                 goto error;
9986         }
9987         cache_resource->idx = idx;
9988         cache_resource->dev = dev;
9989         return &cache_resource->entry;
9990 error:
9991         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9992                 flow_dv_sample_sub_actions_release(dev,
9993                                                    &cache_resource->sample_idx);
9994         if (cache_resource->normal_path_tbl)
9995                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9996                                 cache_resource->normal_path_tbl);
9997         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9998         return NULL;
9999
10000 }
10001
10002 /**
10003  * Find existing sample resource or create and register a new one.
10004  *
10005  * @param[in, out] dev
10006  *   Pointer to rte_eth_dev structure.
10007  * @param[in] resource
10008  *   Pointer to sample resource.
10009  * @parm[in, out] dev_flow
10010  *   Pointer to the dev_flow.
10011  * @param[out] error
10012  *   pointer to error structure.
10013  *
10014  * @return
10015  *   0 on success otherwise -errno and errno is set.
10016  */
10017 static int
10018 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10019                          struct mlx5_flow_dv_sample_resource *resource,
10020                          struct mlx5_flow *dev_flow,
10021                          struct rte_flow_error *error)
10022 {
10023         struct mlx5_flow_dv_sample_resource *cache_resource;
10024         struct mlx5_cache_entry *entry;
10025         struct mlx5_priv *priv = dev->data->dev_private;
10026         struct mlx5_flow_cb_ctx ctx = {
10027                 .dev = dev,
10028                 .error = error,
10029                 .data = resource,
10030         };
10031
10032         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10033         if (!entry)
10034                 return -rte_errno;
10035         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10036         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10037         dev_flow->dv.sample_res = cache_resource;
10038         return 0;
10039 }
10040
10041 int
10042 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10043                             struct mlx5_cache_entry *entry, void *cb_ctx)
10044 {
10045         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10046         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10047         struct rte_eth_dev *dev = ctx->dev;
10048         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10049                         container_of(entry, typeof(*cache_resource), entry);
10050         uint32_t idx = 0;
10051
10052         if (resource->num_of_dest == cache_resource->num_of_dest &&
10053             resource->ft_type == cache_resource->ft_type &&
10054             !memcmp((void *)cache_resource->sample_act,
10055                     (void *)resource->sample_act,
10056                    (resource->num_of_dest *
10057                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10058                 /*
10059                  * Existing sample action should release the prepared
10060                  * sub-actions reference counter.
10061                  */
10062                 for (idx = 0; idx < resource->num_of_dest; idx++)
10063                         flow_dv_sample_sub_actions_release(dev,
10064                                         &resource->sample_idx[idx]);
10065                 return 0;
10066         }
10067         return 1;
10068 }
10069
10070 struct mlx5_cache_entry *
10071 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10072                          struct mlx5_cache_entry *entry __rte_unused,
10073                          void *cb_ctx)
10074 {
10075         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10076         struct rte_eth_dev *dev = ctx->dev;
10077         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10078         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10079         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10080         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10081         struct mlx5_priv *priv = dev->data->dev_private;
10082         struct mlx5_dev_ctx_shared *sh = priv->sh;
10083         struct mlx5_flow_sub_actions_list *sample_act;
10084         struct mlx5dv_dr_domain *domain;
10085         uint32_t idx = 0, res_idx = 0;
10086         struct rte_flow_error *error = ctx->error;
10087         uint64_t action_flags;
10088         int ret;
10089
10090         /* Register new destination array resource. */
10091         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10092                                             &res_idx);
10093         if (!cache_resource) {
10094                 rte_flow_error_set(error, ENOMEM,
10095                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10096                                           NULL,
10097                                           "cannot allocate resource memory");
10098                 return NULL;
10099         }
10100         *cache_resource = *resource;
10101         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10102                 domain = sh->fdb_domain;
10103         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10104                 domain = sh->rx_domain;
10105         else
10106                 domain = sh->tx_domain;
10107         for (idx = 0; idx < resource->num_of_dest; idx++) {
10108                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10109                                  mlx5_malloc(MLX5_MEM_ZERO,
10110                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10111                                  0, SOCKET_ID_ANY);
10112                 if (!dest_attr[idx]) {
10113                         rte_flow_error_set(error, ENOMEM,
10114                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10115                                            NULL,
10116                                            "cannot allocate resource memory");
10117                         goto error;
10118                 }
10119                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10120                 sample_act = &resource->sample_act[idx];
10121                 action_flags = sample_act->action_flags;
10122                 switch (action_flags) {
10123                 case MLX5_FLOW_ACTION_QUEUE:
10124                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10125                         break;
10126                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10127                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10128                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10129                         dest_attr[idx]->dest_reformat->reformat =
10130                                         sample_act->dr_encap_action;
10131                         dest_attr[idx]->dest_reformat->dest =
10132                                         sample_act->dr_port_id_action;
10133                         break;
10134                 case MLX5_FLOW_ACTION_PORT_ID:
10135                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10136                         break;
10137                 case MLX5_FLOW_ACTION_JUMP:
10138                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10139                         break;
10140                 default:
10141                         rte_flow_error_set(error, EINVAL,
10142                                            RTE_FLOW_ERROR_TYPE_ACTION,
10143                                            NULL,
10144                                            "unsupported actions type");
10145                         goto error;
10146                 }
10147         }
10148         /* create a dest array actioin */
10149         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10150                                                 (domain,
10151                                                  cache_resource->num_of_dest,
10152                                                  dest_attr,
10153                                                  &cache_resource->action);
10154         if (ret) {
10155                 rte_flow_error_set(error, ENOMEM,
10156                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10157                                    NULL,
10158                                    "cannot create destination array action");
10159                 goto error;
10160         }
10161         cache_resource->idx = res_idx;
10162         cache_resource->dev = dev;
10163         for (idx = 0; idx < resource->num_of_dest; idx++)
10164                 mlx5_free(dest_attr[idx]);
10165         return &cache_resource->entry;
10166 error:
10167         for (idx = 0; idx < resource->num_of_dest; idx++) {
10168                 struct mlx5_flow_sub_actions_idx *act_res =
10169                                         &cache_resource->sample_idx[idx];
10170                 if (act_res->rix_hrxq &&
10171                     !mlx5_hrxq_release(dev,
10172                                 act_res->rix_hrxq))
10173                         act_res->rix_hrxq = 0;
10174                 if (act_res->rix_encap_decap &&
10175                         !flow_dv_encap_decap_resource_release(dev,
10176                                 act_res->rix_encap_decap))
10177                         act_res->rix_encap_decap = 0;
10178                 if (act_res->rix_port_id_action &&
10179                         !flow_dv_port_id_action_resource_release(dev,
10180                                 act_res->rix_port_id_action))
10181                         act_res->rix_port_id_action = 0;
10182                 if (act_res->rix_jump &&
10183                         !flow_dv_jump_tbl_resource_release(dev,
10184                                 act_res->rix_jump))
10185                         act_res->rix_jump = 0;
10186                 if (dest_attr[idx])
10187                         mlx5_free(dest_attr[idx]);
10188         }
10189
10190         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10191         return NULL;
10192 }
10193
10194 /**
10195  * Find existing destination array resource or create and register a new one.
10196  *
10197  * @param[in, out] dev
10198  *   Pointer to rte_eth_dev structure.
10199  * @param[in] resource
10200  *   Pointer to destination array resource.
10201  * @parm[in, out] dev_flow
10202  *   Pointer to the dev_flow.
10203  * @param[out] error
10204  *   pointer to error structure.
10205  *
10206  * @return
10207  *   0 on success otherwise -errno and errno is set.
10208  */
10209 static int
10210 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10211                          struct mlx5_flow_dv_dest_array_resource *resource,
10212                          struct mlx5_flow *dev_flow,
10213                          struct rte_flow_error *error)
10214 {
10215         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10216         struct mlx5_priv *priv = dev->data->dev_private;
10217         struct mlx5_cache_entry *entry;
10218         struct mlx5_flow_cb_ctx ctx = {
10219                 .dev = dev,
10220                 .error = error,
10221                 .data = resource,
10222         };
10223
10224         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10225         if (!entry)
10226                 return -rte_errno;
10227         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10228         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10229         dev_flow->dv.dest_array_res = cache_resource;
10230         return 0;
10231 }
10232
10233 /**
10234  * Convert Sample action to DV specification.
10235  *
10236  * @param[in] dev
10237  *   Pointer to rte_eth_dev structure.
10238  * @param[in] action
10239  *   Pointer to sample action structure.
10240  * @param[in, out] dev_flow
10241  *   Pointer to the mlx5_flow.
10242  * @param[in] attr
10243  *   Pointer to the flow attributes.
10244  * @param[in, out] num_of_dest
10245  *   Pointer to the num of destination.
10246  * @param[in, out] sample_actions
10247  *   Pointer to sample actions list.
10248  * @param[in, out] res
10249  *   Pointer to sample resource.
10250  * @param[out] error
10251  *   Pointer to the error structure.
10252  *
10253  * @return
10254  *   0 on success, a negative errno value otherwise and rte_errno is set.
10255  */
10256 static int
10257 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10258                                 const struct rte_flow_action_sample *action,
10259                                 struct mlx5_flow *dev_flow,
10260                                 const struct rte_flow_attr *attr,
10261                                 uint32_t *num_of_dest,
10262                                 void **sample_actions,
10263                                 struct mlx5_flow_dv_sample_resource *res,
10264                                 struct rte_flow_error *error)
10265 {
10266         struct mlx5_priv *priv = dev->data->dev_private;
10267         const struct rte_flow_action *sub_actions;
10268         struct mlx5_flow_sub_actions_list *sample_act;
10269         struct mlx5_flow_sub_actions_idx *sample_idx;
10270         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10271         struct rte_flow *flow = dev_flow->flow;
10272         struct mlx5_flow_rss_desc *rss_desc;
10273         uint64_t action_flags = 0;
10274
10275         MLX5_ASSERT(wks);
10276         rss_desc = &wks->rss_desc;
10277         sample_act = &res->sample_act;
10278         sample_idx = &res->sample_idx;
10279         res->ratio = action->ratio;
10280         sub_actions = action->actions;
10281         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10282                 int type = sub_actions->type;
10283                 uint32_t pre_rix = 0;
10284                 void *pre_r;
10285                 switch (type) {
10286                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10287                 {
10288                         const struct rte_flow_action_queue *queue;
10289                         struct mlx5_hrxq *hrxq;
10290                         uint32_t hrxq_idx;
10291
10292                         queue = sub_actions->conf;
10293                         rss_desc->queue_num = 1;
10294                         rss_desc->queue[0] = queue->index;
10295                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10296                                                     rss_desc, &hrxq_idx);
10297                         if (!hrxq)
10298                                 return rte_flow_error_set
10299                                         (error, rte_errno,
10300                                          RTE_FLOW_ERROR_TYPE_ACTION,
10301                                          NULL,
10302                                          "cannot create fate queue");
10303                         sample_act->dr_queue_action = hrxq->action;
10304                         sample_idx->rix_hrxq = hrxq_idx;
10305                         sample_actions[sample_act->actions_num++] =
10306                                                 hrxq->action;
10307                         (*num_of_dest)++;
10308                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10309                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10310                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10311                         dev_flow->handle->fate_action =
10312                                         MLX5_FLOW_FATE_QUEUE;
10313                         break;
10314                 }
10315                 case RTE_FLOW_ACTION_TYPE_RSS:
10316                 {
10317                         struct mlx5_hrxq *hrxq;
10318                         uint32_t hrxq_idx;
10319                         const struct rte_flow_action_rss *rss;
10320                         const uint8_t *rss_key;
10321
10322                         rss = sub_actions->conf;
10323                         memcpy(rss_desc->queue, rss->queue,
10324                                rss->queue_num * sizeof(uint16_t));
10325                         rss_desc->queue_num = rss->queue_num;
10326                         /* NULL RSS key indicates default RSS key. */
10327                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10328                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10329                         /*
10330                          * rss->level and rss.types should be set in advance
10331                          * when expanding items for RSS.
10332                          */
10333                         flow_dv_hashfields_set(dev_flow, rss_desc);
10334                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10335                                                     rss_desc, &hrxq_idx);
10336                         if (!hrxq)
10337                                 return rte_flow_error_set
10338                                         (error, rte_errno,
10339                                          RTE_FLOW_ERROR_TYPE_ACTION,
10340                                          NULL,
10341                                          "cannot create fate queue");
10342                         sample_act->dr_queue_action = hrxq->action;
10343                         sample_idx->rix_hrxq = hrxq_idx;
10344                         sample_actions[sample_act->actions_num++] =
10345                                                 hrxq->action;
10346                         (*num_of_dest)++;
10347                         action_flags |= MLX5_FLOW_ACTION_RSS;
10348                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10349                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10350                         dev_flow->handle->fate_action =
10351                                         MLX5_FLOW_FATE_QUEUE;
10352                         break;
10353                 }
10354                 case RTE_FLOW_ACTION_TYPE_MARK:
10355                 {
10356                         uint32_t tag_be = mlx5_flow_mark_set
10357                                 (((const struct rte_flow_action_mark *)
10358                                 (sub_actions->conf))->id);
10359
10360                         dev_flow->handle->mark = 1;
10361                         pre_rix = dev_flow->handle->dvh.rix_tag;
10362                         /* Save the mark resource before sample */
10363                         pre_r = dev_flow->dv.tag_resource;
10364                         if (flow_dv_tag_resource_register(dev, tag_be,
10365                                                   dev_flow, error))
10366                                 return -rte_errno;
10367                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10368                         sample_act->dr_tag_action =
10369                                 dev_flow->dv.tag_resource->action;
10370                         sample_idx->rix_tag =
10371                                 dev_flow->handle->dvh.rix_tag;
10372                         sample_actions[sample_act->actions_num++] =
10373                                                 sample_act->dr_tag_action;
10374                         /* Recover the mark resource after sample */
10375                         dev_flow->dv.tag_resource = pre_r;
10376                         dev_flow->handle->dvh.rix_tag = pre_rix;
10377                         action_flags |= MLX5_FLOW_ACTION_MARK;
10378                         break;
10379                 }
10380                 case RTE_FLOW_ACTION_TYPE_COUNT:
10381                 {
10382                         if (!flow->counter) {
10383                                 flow->counter =
10384                                         flow_dv_translate_create_counter(dev,
10385                                                 dev_flow, sub_actions->conf,
10386                                                 0);
10387                                 if (!flow->counter)
10388                                         return rte_flow_error_set
10389                                                 (error, rte_errno,
10390                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10391                                                 NULL,
10392                                                 "cannot create counter"
10393                                                 " object.");
10394                         }
10395                         sample_act->dr_cnt_action =
10396                                   (flow_dv_counter_get_by_idx(dev,
10397                                   flow->counter, NULL))->action;
10398                         sample_actions[sample_act->actions_num++] =
10399                                                 sample_act->dr_cnt_action;
10400                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10401                         break;
10402                 }
10403                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10404                 {
10405                         struct mlx5_flow_dv_port_id_action_resource
10406                                         port_id_resource;
10407                         uint32_t port_id = 0;
10408
10409                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10410                         /* Save the port id resource before sample */
10411                         pre_rix = dev_flow->handle->rix_port_id_action;
10412                         pre_r = dev_flow->dv.port_id_action;
10413                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10414                                                              &port_id, error))
10415                                 return -rte_errno;
10416                         port_id_resource.port_id = port_id;
10417                         if (flow_dv_port_id_action_resource_register
10418                             (dev, &port_id_resource, dev_flow, error))
10419                                 return -rte_errno;
10420                         sample_act->dr_port_id_action =
10421                                 dev_flow->dv.port_id_action->action;
10422                         sample_idx->rix_port_id_action =
10423                                 dev_flow->handle->rix_port_id_action;
10424                         sample_actions[sample_act->actions_num++] =
10425                                                 sample_act->dr_port_id_action;
10426                         /* Recover the port id resource after sample */
10427                         dev_flow->dv.port_id_action = pre_r;
10428                         dev_flow->handle->rix_port_id_action = pre_rix;
10429                         (*num_of_dest)++;
10430                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10431                         break;
10432                 }
10433                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10434                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10435                         /* Save the encap resource before sample */
10436                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10437                         pre_r = dev_flow->dv.encap_decap;
10438                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10439                                                            dev_flow,
10440                                                            attr->transfer,
10441                                                            error))
10442                                 return -rte_errno;
10443                         sample_act->dr_encap_action =
10444                                 dev_flow->dv.encap_decap->action;
10445                         sample_idx->rix_encap_decap =
10446                                 dev_flow->handle->dvh.rix_encap_decap;
10447                         sample_actions[sample_act->actions_num++] =
10448                                                 sample_act->dr_encap_action;
10449                         /* Recover the encap resource after sample */
10450                         dev_flow->dv.encap_decap = pre_r;
10451                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10452                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10453                         break;
10454                 default:
10455                         return rte_flow_error_set(error, EINVAL,
10456                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10457                                 NULL,
10458                                 "Not support for sampler action");
10459                 }
10460         }
10461         sample_act->action_flags = action_flags;
10462         res->ft_id = dev_flow->dv.group;
10463         if (attr->transfer) {
10464                 union {
10465                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10466                         uint64_t set_action;
10467                 } action_ctx = { .set_action = 0 };
10468
10469                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10470                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10471                          MLX5_MODIFICATION_TYPE_SET);
10472                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10473                          MLX5_MODI_META_REG_C_0);
10474                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10475                          priv->vport_meta_tag);
10476                 res->set_action = action_ctx.set_action;
10477         } else if (attr->ingress) {
10478                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10479         } else {
10480                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10481         }
10482         return 0;
10483 }
10484
10485 /**
10486  * Convert Sample action to DV specification.
10487  *
10488  * @param[in] dev
10489  *   Pointer to rte_eth_dev structure.
10490  * @param[in, out] dev_flow
10491  *   Pointer to the mlx5_flow.
10492  * @param[in] num_of_dest
10493  *   The num of destination.
10494  * @param[in, out] res
10495  *   Pointer to sample resource.
10496  * @param[in, out] mdest_res
10497  *   Pointer to destination array resource.
10498  * @param[in] sample_actions
10499  *   Pointer to sample path actions list.
10500  * @param[in] action_flags
10501  *   Holds the actions detected until now.
10502  * @param[out] error
10503  *   Pointer to the error structure.
10504  *
10505  * @return
10506  *   0 on success, a negative errno value otherwise and rte_errno is set.
10507  */
10508 static int
10509 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10510                              struct mlx5_flow *dev_flow,
10511                              uint32_t num_of_dest,
10512                              struct mlx5_flow_dv_sample_resource *res,
10513                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10514                              void **sample_actions,
10515                              uint64_t action_flags,
10516                              struct rte_flow_error *error)
10517 {
10518         /* update normal path action resource into last index of array */
10519         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10520         struct mlx5_flow_sub_actions_list *sample_act =
10521                                         &mdest_res->sample_act[dest_index];
10522         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10523         struct mlx5_flow_rss_desc *rss_desc;
10524         uint32_t normal_idx = 0;
10525         struct mlx5_hrxq *hrxq;
10526         uint32_t hrxq_idx;
10527
10528         MLX5_ASSERT(wks);
10529         rss_desc = &wks->rss_desc;
10530         if (num_of_dest > 1) {
10531                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10532                         /* Handle QP action for mirroring */
10533                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10534                                                     rss_desc, &hrxq_idx);
10535                         if (!hrxq)
10536                                 return rte_flow_error_set
10537                                      (error, rte_errno,
10538                                       RTE_FLOW_ERROR_TYPE_ACTION,
10539                                       NULL,
10540                                       "cannot create rx queue");
10541                         normal_idx++;
10542                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10543                         sample_act->dr_queue_action = hrxq->action;
10544                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10545                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10546                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10547                 }
10548                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10549                         normal_idx++;
10550                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10551                                 dev_flow->handle->dvh.rix_encap_decap;
10552                         sample_act->dr_encap_action =
10553                                 dev_flow->dv.encap_decap->action;
10554                 }
10555                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10556                         normal_idx++;
10557                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10558                                 dev_flow->handle->rix_port_id_action;
10559                         sample_act->dr_port_id_action =
10560                                 dev_flow->dv.port_id_action->action;
10561                 }
10562                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10563                         normal_idx++;
10564                         mdest_res->sample_idx[dest_index].rix_jump =
10565                                 dev_flow->handle->rix_jump;
10566                         sample_act->dr_jump_action =
10567                                 dev_flow->dv.jump->action;
10568                         dev_flow->handle->rix_jump = 0;
10569                 }
10570                 sample_act->actions_num = normal_idx;
10571                 /* update sample action resource into first index of array */
10572                 mdest_res->ft_type = res->ft_type;
10573                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10574                                 sizeof(struct mlx5_flow_sub_actions_idx));
10575                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10576                                 sizeof(struct mlx5_flow_sub_actions_list));
10577                 mdest_res->num_of_dest = num_of_dest;
10578                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10579                                                          dev_flow, error))
10580                         return rte_flow_error_set(error, EINVAL,
10581                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10582                                                   NULL, "can't create sample "
10583                                                   "action");
10584         } else {
10585                 res->sub_actions = sample_actions;
10586                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10587                         return rte_flow_error_set(error, EINVAL,
10588                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10589                                                   NULL,
10590                                                   "can't create sample action");
10591         }
10592         return 0;
10593 }
10594
10595 /**
10596  * Remove an ASO age action from age actions list.
10597  *
10598  * @param[in] dev
10599  *   Pointer to the Ethernet device structure.
10600  * @param[in] age
10601  *   Pointer to the aso age action handler.
10602  */
10603 static void
10604 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10605                                 struct mlx5_aso_age_action *age)
10606 {
10607         struct mlx5_age_info *age_info;
10608         struct mlx5_age_param *age_param = &age->age_params;
10609         struct mlx5_priv *priv = dev->data->dev_private;
10610         uint16_t expected = AGE_CANDIDATE;
10611
10612         age_info = GET_PORT_AGE_INFO(priv);
10613         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10614                                          AGE_FREE, false, __ATOMIC_RELAXED,
10615                                          __ATOMIC_RELAXED)) {
10616                 /**
10617                  * We need the lock even it is age timeout,
10618                  * since age action may still in process.
10619                  */
10620                 rte_spinlock_lock(&age_info->aged_sl);
10621                 LIST_REMOVE(age, next);
10622                 rte_spinlock_unlock(&age_info->aged_sl);
10623                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10624         }
10625 }
10626
10627 /**
10628  * Release an ASO age action.
10629  *
10630  * @param[in] dev
10631  *   Pointer to the Ethernet device structure.
10632  * @param[in] age_idx
10633  *   Index of ASO age action to release.
10634  * @param[in] flow
10635  *   True if the release operation is during flow destroy operation.
10636  *   False if the release operation is during action destroy operation.
10637  *
10638  * @return
10639  *   0 when age action was removed, otherwise the number of references.
10640  */
10641 static int
10642 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10643 {
10644         struct mlx5_priv *priv = dev->data->dev_private;
10645         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10646         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10647         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10648
10649         if (!ret) {
10650                 flow_dv_aso_age_remove_from_age(dev, age);
10651                 rte_spinlock_lock(&mng->free_sl);
10652                 LIST_INSERT_HEAD(&mng->free, age, next);
10653                 rte_spinlock_unlock(&mng->free_sl);
10654         }
10655         return ret;
10656 }
10657
10658 /**
10659  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10660  *
10661  * @param[in] dev
10662  *   Pointer to the Ethernet device structure.
10663  *
10664  * @return
10665  *   0 on success, otherwise negative errno value and rte_errno is set.
10666  */
10667 static int
10668 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10669 {
10670         struct mlx5_priv *priv = dev->data->dev_private;
10671         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10672         void *old_pools = mng->pools;
10673         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10674         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10675         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10676
10677         if (!pools) {
10678                 rte_errno = ENOMEM;
10679                 return -ENOMEM;
10680         }
10681         if (old_pools) {
10682                 memcpy(pools, old_pools,
10683                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10684                 mlx5_free(old_pools);
10685         } else {
10686                 /* First ASO flow hit allocation - starting ASO data-path. */
10687                 int ret = mlx5_aso_queue_start(priv->sh);
10688
10689                 if (ret) {
10690                         mlx5_free(pools);
10691                         return ret;
10692                 }
10693         }
10694         mng->n = resize;
10695         mng->pools = pools;
10696         return 0;
10697 }
10698
10699 /**
10700  * Create and initialize a new ASO aging pool.
10701  *
10702  * @param[in] dev
10703  *   Pointer to the Ethernet device structure.
10704  * @param[out] age_free
10705  *   Where to put the pointer of a new age action.
10706  *
10707  * @return
10708  *   The age actions pool pointer and @p age_free is set on success,
10709  *   NULL otherwise and rte_errno is set.
10710  */
10711 static struct mlx5_aso_age_pool *
10712 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10713                         struct mlx5_aso_age_action **age_free)
10714 {
10715         struct mlx5_priv *priv = dev->data->dev_private;
10716         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10717         struct mlx5_aso_age_pool *pool = NULL;
10718         struct mlx5_devx_obj *obj = NULL;
10719         uint32_t i;
10720
10721         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10722                                                     priv->sh->pdn);
10723         if (!obj) {
10724                 rte_errno = ENODATA;
10725                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10726                 return NULL;
10727         }
10728         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10729         if (!pool) {
10730                 claim_zero(mlx5_devx_cmd_destroy(obj));
10731                 rte_errno = ENOMEM;
10732                 return NULL;
10733         }
10734         pool->flow_hit_aso_obj = obj;
10735         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10736         rte_spinlock_lock(&mng->resize_sl);
10737         pool->index = mng->next;
10738         /* Resize pools array if there is no room for the new pool in it. */
10739         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10740                 claim_zero(mlx5_devx_cmd_destroy(obj));
10741                 mlx5_free(pool);
10742                 rte_spinlock_unlock(&mng->resize_sl);
10743                 return NULL;
10744         }
10745         mng->pools[pool->index] = pool;
10746         mng->next++;
10747         rte_spinlock_unlock(&mng->resize_sl);
10748         /* Assign the first action in the new pool, the rest go to free list. */
10749         *age_free = &pool->actions[0];
10750         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10751                 pool->actions[i].offset = i;
10752                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10753         }
10754         return pool;
10755 }
10756
10757 /**
10758  * Allocate a ASO aging bit.
10759  *
10760  * @param[in] dev
10761  *   Pointer to the Ethernet device structure.
10762  * @param[out] error
10763  *   Pointer to the error structure.
10764  *
10765  * @return
10766  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10767  */
10768 static uint32_t
10769 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10770 {
10771         struct mlx5_priv *priv = dev->data->dev_private;
10772         const struct mlx5_aso_age_pool *pool;
10773         struct mlx5_aso_age_action *age_free = NULL;
10774         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10775
10776         MLX5_ASSERT(mng);
10777         /* Try to get the next free age action bit. */
10778         rte_spinlock_lock(&mng->free_sl);
10779         age_free = LIST_FIRST(&mng->free);
10780         if (age_free) {
10781                 LIST_REMOVE(age_free, next);
10782         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10783                 rte_spinlock_unlock(&mng->free_sl);
10784                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10785                                    NULL, "failed to create ASO age pool");
10786                 return 0; /* 0 is an error. */
10787         }
10788         rte_spinlock_unlock(&mng->free_sl);
10789         pool = container_of
10790           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10791                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10792                                                                        actions);
10793         if (!age_free->dr_action) {
10794                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10795                                                  error);
10796
10797                 if (reg_c < 0) {
10798                         rte_flow_error_set(error, rte_errno,
10799                                            RTE_FLOW_ERROR_TYPE_ACTION,
10800                                            NULL, "failed to get reg_c "
10801                                            "for ASO flow hit");
10802                         return 0; /* 0 is an error. */
10803                 }
10804 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10805                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10806                                 (priv->sh->rx_domain,
10807                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10808                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10809                                  (reg_c - REG_C_0));
10810 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10811                 if (!age_free->dr_action) {
10812                         rte_errno = errno;
10813                         rte_spinlock_lock(&mng->free_sl);
10814                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10815                         rte_spinlock_unlock(&mng->free_sl);
10816                         rte_flow_error_set(error, rte_errno,
10817                                            RTE_FLOW_ERROR_TYPE_ACTION,
10818                                            NULL, "failed to create ASO "
10819                                            "flow hit action");
10820                         return 0; /* 0 is an error. */
10821                 }
10822         }
10823         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10824         return pool->index | ((age_free->offset + 1) << 16);
10825 }
10826
10827 /**
10828  * Create a age action using ASO mechanism.
10829  *
10830  * @param[in] dev
10831  *   Pointer to rte_eth_dev structure.
10832  * @param[in] age
10833  *   Pointer to the aging action configuration.
10834  * @param[out] error
10835  *   Pointer to the error structure.
10836  *
10837  * @return
10838  *   Index to flow counter on success, 0 otherwise.
10839  */
10840 static uint32_t
10841 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10842                                  const struct rte_flow_action_age *age,
10843                                  struct rte_flow_error *error)
10844 {
10845         uint32_t age_idx = 0;
10846         struct mlx5_aso_age_action *aso_age;
10847
10848         age_idx = flow_dv_aso_age_alloc(dev, error);
10849         if (!age_idx)
10850                 return 0;
10851         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10852         aso_age->age_params.context = age->context;
10853         aso_age->age_params.timeout = age->timeout;
10854         aso_age->age_params.port_id = dev->data->port_id;
10855         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10856                          __ATOMIC_RELAXED);
10857         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10858                          __ATOMIC_RELAXED);
10859         return age_idx;
10860 }
10861
10862 /**
10863  * Fill the flow with DV spec, lock free
10864  * (mutex should be acquired by caller).
10865  *
10866  * @param[in] dev
10867  *   Pointer to rte_eth_dev structure.
10868  * @param[in, out] dev_flow
10869  *   Pointer to the sub flow.
10870  * @param[in] attr
10871  *   Pointer to the flow attributes.
10872  * @param[in] items
10873  *   Pointer to the list of items.
10874  * @param[in] actions
10875  *   Pointer to the list of actions.
10876  * @param[out] error
10877  *   Pointer to the error structure.
10878  *
10879  * @return
10880  *   0 on success, a negative errno value otherwise and rte_errno is set.
10881  */
10882 static int
10883 flow_dv_translate(struct rte_eth_dev *dev,
10884                   struct mlx5_flow *dev_flow,
10885                   const struct rte_flow_attr *attr,
10886                   const struct rte_flow_item items[],
10887                   const struct rte_flow_action actions[],
10888                   struct rte_flow_error *error)
10889 {
10890         struct mlx5_priv *priv = dev->data->dev_private;
10891         struct mlx5_dev_config *dev_conf = &priv->config;
10892         struct rte_flow *flow = dev_flow->flow;
10893         struct mlx5_flow_handle *handle = dev_flow->handle;
10894         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10895         struct mlx5_flow_rss_desc *rss_desc;
10896         uint64_t item_flags = 0;
10897         uint64_t last_item = 0;
10898         uint64_t action_flags = 0;
10899         struct mlx5_flow_dv_matcher matcher = {
10900                 .mask = {
10901                         .size = sizeof(matcher.mask.buf) -
10902                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10903                 },
10904         };
10905         int actions_n = 0;
10906         bool actions_end = false;
10907         union {
10908                 struct mlx5_flow_dv_modify_hdr_resource res;
10909                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10910                             sizeof(struct mlx5_modification_cmd) *
10911                             (MLX5_MAX_MODIFY_NUM + 1)];
10912         } mhdr_dummy;
10913         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10914         const struct rte_flow_action_count *count = NULL;
10915         const struct rte_flow_action_age *age = NULL;
10916         union flow_dv_attr flow_attr = { .attr = 0 };
10917         uint32_t tag_be;
10918         union mlx5_flow_tbl_key tbl_key;
10919         uint32_t modify_action_position = UINT32_MAX;
10920         void *match_mask = matcher.mask.buf;
10921         void *match_value = dev_flow->dv.value.buf;
10922         uint8_t next_protocol = 0xff;
10923         struct rte_vlan_hdr vlan = { 0 };
10924         struct mlx5_flow_dv_dest_array_resource mdest_res;
10925         struct mlx5_flow_dv_sample_resource sample_res;
10926         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10927         const struct rte_flow_action_sample *sample = NULL;
10928         struct mlx5_flow_sub_actions_list *sample_act;
10929         uint32_t sample_act_pos = UINT32_MAX;
10930         uint32_t num_of_dest = 0;
10931         int tmp_actions_n = 0;
10932         uint32_t table;
10933         int ret = 0;
10934         const struct mlx5_flow_tunnel *tunnel;
10935         struct flow_grp_info grp_info = {
10936                 .external = !!dev_flow->external,
10937                 .transfer = !!attr->transfer,
10938                 .fdb_def_rule = !!priv->fdb_def_rule,
10939                 .skip_scale = dev_flow->skip_scale &
10940                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10941         };
10942
10943         if (!wks)
10944                 return rte_flow_error_set(error, ENOMEM,
10945                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10946                                           NULL,
10947                                           "failed to push flow workspace");
10948         rss_desc = &wks->rss_desc;
10949         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10950         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10951         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10952                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10953         /* update normal path action resource into last index of array */
10954         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10955         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10956                  flow_items_to_tunnel(items) :
10957                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10958                  flow_actions_to_tunnel(actions) :
10959                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10960         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10961                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10962         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10963                                 (dev, tunnel, attr, items, actions);
10964         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10965                                        &grp_info, error);
10966         if (ret)
10967                 return ret;
10968         dev_flow->dv.group = table;
10969         if (attr->transfer)
10970                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10971         /* number of actions must be set to 0 in case of dirty stack. */
10972         mhdr_res->actions_num = 0;
10973         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10974                 /*
10975                  * do not add decap action if match rule drops packet
10976                  * HW rejects rules with decap & drop
10977                  *
10978                  * if tunnel match rule was inserted before matching tunnel set
10979                  * rule flow table used in the match rule must be registered.
10980                  * current implementation handles that in the
10981                  * flow_dv_match_register() at the function end.
10982                  */
10983                 bool add_decap = true;
10984                 const struct rte_flow_action *ptr = actions;
10985
10986                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10987                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10988                                 add_decap = false;
10989                                 break;
10990                         }
10991                 }
10992                 if (add_decap) {
10993                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10994                                                            attr->transfer,
10995                                                            error))
10996                                 return -rte_errno;
10997                         dev_flow->dv.actions[actions_n++] =
10998                                         dev_flow->dv.encap_decap->action;
10999                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11000                 }
11001         }
11002         for (; !actions_end ; actions++) {
11003                 const struct rte_flow_action_queue *queue;
11004                 const struct rte_flow_action_rss *rss;
11005                 const struct rte_flow_action *action = actions;
11006                 const uint8_t *rss_key;
11007                 const struct rte_flow_action_meter *mtr;
11008                 struct mlx5_flow_tbl_resource *tbl;
11009                 struct mlx5_aso_age_action *age_act;
11010                 uint32_t port_id = 0;
11011                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11012                 int action_type = actions->type;
11013                 const struct rte_flow_action *found_action = NULL;
11014                 struct mlx5_flow_meter *fm = NULL;
11015                 uint32_t jump_group = 0;
11016
11017                 if (!mlx5_flow_os_action_supported(action_type))
11018                         return rte_flow_error_set(error, ENOTSUP,
11019                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11020                                                   actions,
11021                                                   "action not supported");
11022                 switch (action_type) {
11023                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11024                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11025                         break;
11026                 case RTE_FLOW_ACTION_TYPE_VOID:
11027                         break;
11028                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11029                         if (flow_dv_translate_action_port_id(dev, action,
11030                                                              &port_id, error))
11031                                 return -rte_errno;
11032                         port_id_resource.port_id = port_id;
11033                         MLX5_ASSERT(!handle->rix_port_id_action);
11034                         if (flow_dv_port_id_action_resource_register
11035                             (dev, &port_id_resource, dev_flow, error))
11036                                 return -rte_errno;
11037                         dev_flow->dv.actions[actions_n++] =
11038                                         dev_flow->dv.port_id_action->action;
11039                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11040                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11041                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11042                         num_of_dest++;
11043                         break;
11044                 case RTE_FLOW_ACTION_TYPE_FLAG:
11045                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11046                         dev_flow->handle->mark = 1;
11047                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11048                                 struct rte_flow_action_mark mark = {
11049                                         .id = MLX5_FLOW_MARK_DEFAULT,
11050                                 };
11051
11052                                 if (flow_dv_convert_action_mark(dev, &mark,
11053                                                                 mhdr_res,
11054                                                                 error))
11055                                         return -rte_errno;
11056                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11057                                 break;
11058                         }
11059                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11060                         /*
11061                          * Only one FLAG or MARK is supported per device flow
11062                          * right now. So the pointer to the tag resource must be
11063                          * zero before the register process.
11064                          */
11065                         MLX5_ASSERT(!handle->dvh.rix_tag);
11066                         if (flow_dv_tag_resource_register(dev, tag_be,
11067                                                           dev_flow, error))
11068                                 return -rte_errno;
11069                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11070                         dev_flow->dv.actions[actions_n++] =
11071                                         dev_flow->dv.tag_resource->action;
11072                         break;
11073                 case RTE_FLOW_ACTION_TYPE_MARK:
11074                         action_flags |= MLX5_FLOW_ACTION_MARK;
11075                         dev_flow->handle->mark = 1;
11076                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11077                                 const struct rte_flow_action_mark *mark =
11078                                         (const struct rte_flow_action_mark *)
11079                                                 actions->conf;
11080
11081                                 if (flow_dv_convert_action_mark(dev, mark,
11082                                                                 mhdr_res,
11083                                                                 error))
11084                                         return -rte_errno;
11085                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11086                                 break;
11087                         }
11088                         /* Fall-through */
11089                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11090                         /* Legacy (non-extensive) MARK action. */
11091                         tag_be = mlx5_flow_mark_set
11092                               (((const struct rte_flow_action_mark *)
11093                                (actions->conf))->id);
11094                         MLX5_ASSERT(!handle->dvh.rix_tag);
11095                         if (flow_dv_tag_resource_register(dev, tag_be,
11096                                                           dev_flow, error))
11097                                 return -rte_errno;
11098                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11099                         dev_flow->dv.actions[actions_n++] =
11100                                         dev_flow->dv.tag_resource->action;
11101                         break;
11102                 case RTE_FLOW_ACTION_TYPE_SET_META:
11103                         if (flow_dv_convert_action_set_meta
11104                                 (dev, mhdr_res, attr,
11105                                  (const struct rte_flow_action_set_meta *)
11106                                   actions->conf, error))
11107                                 return -rte_errno;
11108                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11109                         break;
11110                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11111                         if (flow_dv_convert_action_set_tag
11112                                 (dev, mhdr_res,
11113                                  (const struct rte_flow_action_set_tag *)
11114                                   actions->conf, error))
11115                                 return -rte_errno;
11116                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11117                         break;
11118                 case RTE_FLOW_ACTION_TYPE_DROP:
11119                         action_flags |= MLX5_FLOW_ACTION_DROP;
11120                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11121                         break;
11122                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11123                         queue = actions->conf;
11124                         rss_desc->queue_num = 1;
11125                         rss_desc->queue[0] = queue->index;
11126                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11127                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11128                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11129                         num_of_dest++;
11130                         break;
11131                 case RTE_FLOW_ACTION_TYPE_RSS:
11132                         rss = actions->conf;
11133                         memcpy(rss_desc->queue, rss->queue,
11134                                rss->queue_num * sizeof(uint16_t));
11135                         rss_desc->queue_num = rss->queue_num;
11136                         /* NULL RSS key indicates default RSS key. */
11137                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11138                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11139                         /*
11140                          * rss->level and rss.types should be set in advance
11141                          * when expanding items for RSS.
11142                          */
11143                         action_flags |= MLX5_FLOW_ACTION_RSS;
11144                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11145                                 MLX5_FLOW_FATE_SHARED_RSS :
11146                                 MLX5_FLOW_FATE_QUEUE;
11147                         break;
11148                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11149                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11150                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11151                         __atomic_fetch_add(&age_act->refcnt, 1,
11152                                            __ATOMIC_RELAXED);
11153                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11154                         action_flags |= MLX5_FLOW_ACTION_AGE;
11155                         break;
11156                 case RTE_FLOW_ACTION_TYPE_AGE:
11157                         if (priv->sh->flow_hit_aso_en && attr->group) {
11158                                 /*
11159                                  * Create one shared age action, to be used
11160                                  * by all sub-flows.
11161                                  */
11162                                 if (!flow->age) {
11163                                         flow->age =
11164                                                 flow_dv_translate_create_aso_age
11165                                                         (dev, action->conf,
11166                                                          error);
11167                                         if (!flow->age)
11168                                                 return rte_flow_error_set
11169                                                 (error, rte_errno,
11170                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11171                                                  NULL,
11172                                                  "can't create ASO age action");
11173                                 }
11174                                 dev_flow->dv.actions[actions_n++] =
11175                                           (flow_aso_age_get_by_idx
11176                                                 (dev, flow->age))->dr_action;
11177                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11178                                 break;
11179                         }
11180                         /* Fall-through */
11181                 case RTE_FLOW_ACTION_TYPE_COUNT:
11182                         if (!dev_conf->devx) {
11183                                 return rte_flow_error_set
11184                                               (error, ENOTSUP,
11185                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11186                                                NULL,
11187                                                "count action not supported");
11188                         }
11189                         /* Save information first, will apply later. */
11190                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11191                                 count = action->conf;
11192                         else
11193                                 age = action->conf;
11194                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11195                         break;
11196                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11197                         dev_flow->dv.actions[actions_n++] =
11198                                                 priv->sh->pop_vlan_action;
11199                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11200                         break;
11201                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11202                         if (!(action_flags &
11203                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11204                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11205                         vlan.eth_proto = rte_be_to_cpu_16
11206                              ((((const struct rte_flow_action_of_push_vlan *)
11207                                                    actions->conf)->ethertype));
11208                         found_action = mlx5_flow_find_action
11209                                         (actions + 1,
11210                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11211                         if (found_action)
11212                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11213                         found_action = mlx5_flow_find_action
11214                                         (actions + 1,
11215                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11216                         if (found_action)
11217                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11218                         if (flow_dv_create_action_push_vlan
11219                                             (dev, attr, &vlan, dev_flow, error))
11220                                 return -rte_errno;
11221                         dev_flow->dv.actions[actions_n++] =
11222                                         dev_flow->dv.push_vlan_res->action;
11223                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11224                         break;
11225                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11226                         /* of_vlan_push action handled this action */
11227                         MLX5_ASSERT(action_flags &
11228                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11229                         break;
11230                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11231                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11232                                 break;
11233                         flow_dev_get_vlan_info_from_items(items, &vlan);
11234                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11235                         /* If no VLAN push - this is a modify header action */
11236                         if (flow_dv_convert_action_modify_vlan_vid
11237                                                 (mhdr_res, actions, error))
11238                                 return -rte_errno;
11239                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11240                         break;
11241                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11242                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11243                         if (flow_dv_create_action_l2_encap(dev, actions,
11244                                                            dev_flow,
11245                                                            attr->transfer,
11246                                                            error))
11247                                 return -rte_errno;
11248                         dev_flow->dv.actions[actions_n++] =
11249                                         dev_flow->dv.encap_decap->action;
11250                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11251                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11252                                 sample_act->action_flags |=
11253                                                         MLX5_FLOW_ACTION_ENCAP;
11254                         break;
11255                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11256                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11257                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11258                                                            attr->transfer,
11259                                                            error))
11260                                 return -rte_errno;
11261                         dev_flow->dv.actions[actions_n++] =
11262                                         dev_flow->dv.encap_decap->action;
11263                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11264                         break;
11265                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11266                         /* Handle encap with preceding decap. */
11267                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11268                                 if (flow_dv_create_action_raw_encap
11269                                         (dev, actions, dev_flow, attr, error))
11270                                         return -rte_errno;
11271                                 dev_flow->dv.actions[actions_n++] =
11272                                         dev_flow->dv.encap_decap->action;
11273                         } else {
11274                                 /* Handle encap without preceding decap. */
11275                                 if (flow_dv_create_action_l2_encap
11276                                     (dev, actions, dev_flow, attr->transfer,
11277                                      error))
11278                                         return -rte_errno;
11279                                 dev_flow->dv.actions[actions_n++] =
11280                                         dev_flow->dv.encap_decap->action;
11281                         }
11282                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11283                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11284                                 sample_act->action_flags |=
11285                                                         MLX5_FLOW_ACTION_ENCAP;
11286                         break;
11287                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11288                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11289                                 ;
11290                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11291                                 if (flow_dv_create_action_l2_decap
11292                                     (dev, dev_flow, attr->transfer, error))
11293                                         return -rte_errno;
11294                                 dev_flow->dv.actions[actions_n++] =
11295                                         dev_flow->dv.encap_decap->action;
11296                         }
11297                         /* If decap is followed by encap, handle it at encap. */
11298                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11299                         break;
11300                 case RTE_FLOW_ACTION_TYPE_JUMP:
11301                         jump_group = ((const struct rte_flow_action_jump *)
11302                                                         action->conf)->group;
11303                         grp_info.std_tbl_fix = 0;
11304                         if (dev_flow->skip_scale &
11305                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11306                                 grp_info.skip_scale = 1;
11307                         else
11308                                 grp_info.skip_scale = 0;
11309                         ret = mlx5_flow_group_to_table(dev, tunnel,
11310                                                        jump_group,
11311                                                        &table,
11312                                                        &grp_info, error);
11313                         if (ret)
11314                                 return ret;
11315                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11316                                                        attr->transfer,
11317                                                        !!dev_flow->external,
11318                                                        tunnel, jump_group, 0,
11319                                                        error);
11320                         if (!tbl)
11321                                 return rte_flow_error_set
11322                                                 (error, errno,
11323                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11324                                                  NULL,
11325                                                  "cannot create jump action.");
11326                         if (flow_dv_jump_tbl_resource_register
11327                             (dev, tbl, dev_flow, error)) {
11328                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11329                                 return rte_flow_error_set
11330                                                 (error, errno,
11331                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11332                                                  NULL,
11333                                                  "cannot create jump action.");
11334                         }
11335                         dev_flow->dv.actions[actions_n++] =
11336                                         dev_flow->dv.jump->action;
11337                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11338                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11339                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11340                         num_of_dest++;
11341                         break;
11342                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11343                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11344                         if (flow_dv_convert_action_modify_mac
11345                                         (mhdr_res, actions, error))
11346                                 return -rte_errno;
11347                         action_flags |= actions->type ==
11348                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11349                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11350                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11351                         break;
11352                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11353                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11354                         if (flow_dv_convert_action_modify_ipv4
11355                                         (mhdr_res, actions, error))
11356                                 return -rte_errno;
11357                         action_flags |= actions->type ==
11358                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11359                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11360                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11361                         break;
11362                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11363                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11364                         if (flow_dv_convert_action_modify_ipv6
11365                                         (mhdr_res, actions, error))
11366                                 return -rte_errno;
11367                         action_flags |= actions->type ==
11368                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11369                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11370                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11371                         break;
11372                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11373                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11374                         if (flow_dv_convert_action_modify_tp
11375                                         (mhdr_res, actions, items,
11376                                          &flow_attr, dev_flow, !!(action_flags &
11377                                          MLX5_FLOW_ACTION_DECAP), error))
11378                                 return -rte_errno;
11379                         action_flags |= actions->type ==
11380                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11381                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11382                                         MLX5_FLOW_ACTION_SET_TP_DST;
11383                         break;
11384                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11385                         if (flow_dv_convert_action_modify_dec_ttl
11386                                         (mhdr_res, items, &flow_attr, dev_flow,
11387                                          !!(action_flags &
11388                                          MLX5_FLOW_ACTION_DECAP), error))
11389                                 return -rte_errno;
11390                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11391                         break;
11392                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11393                         if (flow_dv_convert_action_modify_ttl
11394                                         (mhdr_res, actions, items, &flow_attr,
11395                                          dev_flow, !!(action_flags &
11396                                          MLX5_FLOW_ACTION_DECAP), error))
11397                                 return -rte_errno;
11398                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11399                         break;
11400                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11401                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11402                         if (flow_dv_convert_action_modify_tcp_seq
11403                                         (mhdr_res, actions, error))
11404                                 return -rte_errno;
11405                         action_flags |= actions->type ==
11406                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11407                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11408                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11409                         break;
11410
11411                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11412                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11413                         if (flow_dv_convert_action_modify_tcp_ack
11414                                         (mhdr_res, actions, error))
11415                                 return -rte_errno;
11416                         action_flags |= actions->type ==
11417                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11418                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11419                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11420                         break;
11421                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11422                         if (flow_dv_convert_action_set_reg
11423                                         (mhdr_res, actions, error))
11424                                 return -rte_errno;
11425                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11426                         break;
11427                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11428                         if (flow_dv_convert_action_copy_mreg
11429                                         (dev, mhdr_res, actions, error))
11430                                 return -rte_errno;
11431                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11432                         break;
11433                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11434                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11435                         dev_flow->handle->fate_action =
11436                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11437                         break;
11438                 case RTE_FLOW_ACTION_TYPE_METER:
11439                         mtr = actions->conf;
11440                         if (!flow->meter) {
11441                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11442                                                             attr, error);
11443                                 if (!fm)
11444                                         return rte_flow_error_set(error,
11445                                                 rte_errno,
11446                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11447                                                 NULL,
11448                                                 "meter not found "
11449                                                 "or invalid parameters");
11450                                 flow->meter = fm->idx;
11451                         }
11452                         /* Set the meter action. */
11453                         if (!fm) {
11454                                 fm = mlx5_ipool_get(priv->sh->ipool
11455                                                 [MLX5_IPOOL_MTR], flow->meter);
11456                                 if (!fm)
11457                                         return rte_flow_error_set(error,
11458                                                 rte_errno,
11459                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11460                                                 NULL,
11461                                                 "meter not found "
11462                                                 "or invalid parameters");
11463                         }
11464                         dev_flow->dv.actions[actions_n++] =
11465                                 fm->mfts->meter_action;
11466                         action_flags |= MLX5_FLOW_ACTION_METER;
11467                         break;
11468                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11469                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11470                                                               actions, error))
11471                                 return -rte_errno;
11472                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11473                         break;
11474                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11475                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11476                                                               actions, error))
11477                                 return -rte_errno;
11478                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11479                         break;
11480                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11481                         sample_act_pos = actions_n;
11482                         sample = (const struct rte_flow_action_sample *)
11483                                  action->conf;
11484                         actions_n++;
11485                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11486                         /* put encap action into group if work with port id */
11487                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11488                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11489                                 sample_act->action_flags |=
11490                                                         MLX5_FLOW_ACTION_ENCAP;
11491                         break;
11492                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11493                         if (flow_dv_convert_action_modify_field
11494                                         (dev, mhdr_res, actions, attr, error))
11495                                 return -rte_errno;
11496                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11497                         break;
11498                 case RTE_FLOW_ACTION_TYPE_END:
11499                         actions_end = true;
11500                         if (mhdr_res->actions_num) {
11501                                 /* create modify action if needed. */
11502                                 if (flow_dv_modify_hdr_resource_register
11503                                         (dev, mhdr_res, dev_flow, error))
11504                                         return -rte_errno;
11505                                 dev_flow->dv.actions[modify_action_position] =
11506                                         handle->dvh.modify_hdr->action;
11507                         }
11508                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11509                                 /*
11510                                  * Create one count action, to be used
11511                                  * by all sub-flows.
11512                                  */
11513                                 if (!flow->counter) {
11514                                         flow->counter =
11515                                                 flow_dv_translate_create_counter
11516                                                         (dev, dev_flow, count,
11517                                                          age);
11518                                         if (!flow->counter)
11519                                                 return rte_flow_error_set
11520                                                 (error, rte_errno,
11521                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11522                                                  NULL, "cannot create counter"
11523                                                  " object.");
11524                                 }
11525                                 dev_flow->dv.actions[actions_n] =
11526                                           (flow_dv_counter_get_by_idx(dev,
11527                                           flow->counter, NULL))->action;
11528                                 actions_n++;
11529                         }
11530                 default:
11531                         break;
11532                 }
11533                 if (mhdr_res->actions_num &&
11534                     modify_action_position == UINT32_MAX)
11535                         modify_action_position = actions_n++;
11536         }
11537         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11538                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11539                 int item_type = items->type;
11540
11541                 if (!mlx5_flow_os_item_supported(item_type))
11542                         return rte_flow_error_set(error, ENOTSUP,
11543                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11544                                                   NULL, "item not supported");
11545                 switch (item_type) {
11546                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11547                         flow_dv_translate_item_port_id
11548                                 (dev, match_mask, match_value, items, attr);
11549                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11550                         break;
11551                 case RTE_FLOW_ITEM_TYPE_ETH:
11552                         flow_dv_translate_item_eth(match_mask, match_value,
11553                                                    items, tunnel,
11554                                                    dev_flow->dv.group);
11555                         matcher.priority = action_flags &
11556                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11557                                         !dev_flow->external ?
11558                                         MLX5_PRIORITY_MAP_L3 :
11559                                         MLX5_PRIORITY_MAP_L2;
11560                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11561                                              MLX5_FLOW_LAYER_OUTER_L2;
11562                         break;
11563                 case RTE_FLOW_ITEM_TYPE_VLAN:
11564                         flow_dv_translate_item_vlan(dev_flow,
11565                                                     match_mask, match_value,
11566                                                     items, tunnel,
11567                                                     dev_flow->dv.group);
11568                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11569                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11570                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11571                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11572                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11573                         break;
11574                 case RTE_FLOW_ITEM_TYPE_IPV4:
11575                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11576                                                   &item_flags, &tunnel);
11577                         flow_dv_translate_item_ipv4(match_mask, match_value,
11578                                                     items, tunnel,
11579                                                     dev_flow->dv.group);
11580                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11581                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11582                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11583                         if (items->mask != NULL &&
11584                             ((const struct rte_flow_item_ipv4 *)
11585                              items->mask)->hdr.next_proto_id) {
11586                                 next_protocol =
11587                                         ((const struct rte_flow_item_ipv4 *)
11588                                          (items->spec))->hdr.next_proto_id;
11589                                 next_protocol &=
11590                                         ((const struct rte_flow_item_ipv4 *)
11591                                          (items->mask))->hdr.next_proto_id;
11592                         } else {
11593                                 /* Reset for inner layer. */
11594                                 next_protocol = 0xff;
11595                         }
11596                         break;
11597                 case RTE_FLOW_ITEM_TYPE_IPV6:
11598                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11599                                                   &item_flags, &tunnel);
11600                         flow_dv_translate_item_ipv6(match_mask, match_value,
11601                                                     items, tunnel,
11602                                                     dev_flow->dv.group);
11603                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11604                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11605                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11606                         if (items->mask != NULL &&
11607                             ((const struct rte_flow_item_ipv6 *)
11608                              items->mask)->hdr.proto) {
11609                                 next_protocol =
11610                                         ((const struct rte_flow_item_ipv6 *)
11611                                          items->spec)->hdr.proto;
11612                                 next_protocol &=
11613                                         ((const struct rte_flow_item_ipv6 *)
11614                                          items->mask)->hdr.proto;
11615                         } else {
11616                                 /* Reset for inner layer. */
11617                                 next_protocol = 0xff;
11618                         }
11619                         break;
11620                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11621                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11622                                                              match_value,
11623                                                              items, tunnel);
11624                         last_item = tunnel ?
11625                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11626                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11627                         if (items->mask != NULL &&
11628                             ((const struct rte_flow_item_ipv6_frag_ext *)
11629                              items->mask)->hdr.next_header) {
11630                                 next_protocol =
11631                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11632                                  items->spec)->hdr.next_header;
11633                                 next_protocol &=
11634                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11635                                  items->mask)->hdr.next_header;
11636                         } else {
11637                                 /* Reset for inner layer. */
11638                                 next_protocol = 0xff;
11639                         }
11640                         break;
11641                 case RTE_FLOW_ITEM_TYPE_TCP:
11642                         flow_dv_translate_item_tcp(match_mask, match_value,
11643                                                    items, tunnel);
11644                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11645                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11646                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11647                         break;
11648                 case RTE_FLOW_ITEM_TYPE_UDP:
11649                         flow_dv_translate_item_udp(match_mask, match_value,
11650                                                    items, tunnel);
11651                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11652                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11653                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11654                         break;
11655                 case RTE_FLOW_ITEM_TYPE_GRE:
11656                         flow_dv_translate_item_gre(match_mask, match_value,
11657                                                    items, tunnel);
11658                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11659                         last_item = MLX5_FLOW_LAYER_GRE;
11660                         break;
11661                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11662                         flow_dv_translate_item_gre_key(match_mask,
11663                                                        match_value, items);
11664                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11665                         break;
11666                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11667                         flow_dv_translate_item_nvgre(match_mask, match_value,
11668                                                      items, tunnel);
11669                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11670                         last_item = MLX5_FLOW_LAYER_GRE;
11671                         break;
11672                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11673                         flow_dv_translate_item_vxlan(match_mask, match_value,
11674                                                      items, tunnel);
11675                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11676                         last_item = MLX5_FLOW_LAYER_VXLAN;
11677                         break;
11678                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11679                         flow_dv_translate_item_vxlan_gpe(match_mask,
11680                                                          match_value, items,
11681                                                          tunnel);
11682                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11683                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11684                         break;
11685                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11686                         flow_dv_translate_item_geneve(match_mask, match_value,
11687                                                       items, tunnel);
11688                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11689                         last_item = MLX5_FLOW_LAYER_GENEVE;
11690                         break;
11691                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11692                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11693                                                           match_value,
11694                                                           items, error);
11695                         if (ret)
11696                                 return rte_flow_error_set(error, -ret,
11697                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11698                                         "cannot create GENEVE TLV option");
11699                         flow->geneve_tlv_option = 1;
11700                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11701                         break;
11702                 case RTE_FLOW_ITEM_TYPE_MPLS:
11703                         flow_dv_translate_item_mpls(match_mask, match_value,
11704                                                     items, last_item, tunnel);
11705                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11706                         last_item = MLX5_FLOW_LAYER_MPLS;
11707                         break;
11708                 case RTE_FLOW_ITEM_TYPE_MARK:
11709                         flow_dv_translate_item_mark(dev, match_mask,
11710                                                     match_value, items);
11711                         last_item = MLX5_FLOW_ITEM_MARK;
11712                         break;
11713                 case RTE_FLOW_ITEM_TYPE_META:
11714                         flow_dv_translate_item_meta(dev, match_mask,
11715                                                     match_value, attr, items);
11716                         last_item = MLX5_FLOW_ITEM_METADATA;
11717                         break;
11718                 case RTE_FLOW_ITEM_TYPE_ICMP:
11719                         flow_dv_translate_item_icmp(match_mask, match_value,
11720                                                     items, tunnel);
11721                         last_item = MLX5_FLOW_LAYER_ICMP;
11722                         break;
11723                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11724                         flow_dv_translate_item_icmp6(match_mask, match_value,
11725                                                       items, tunnel);
11726                         last_item = MLX5_FLOW_LAYER_ICMP6;
11727                         break;
11728                 case RTE_FLOW_ITEM_TYPE_TAG:
11729                         flow_dv_translate_item_tag(dev, match_mask,
11730                                                    match_value, items);
11731                         last_item = MLX5_FLOW_ITEM_TAG;
11732                         break;
11733                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11734                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11735                                                         match_value, items);
11736                         last_item = MLX5_FLOW_ITEM_TAG;
11737                         break;
11738                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11739                         flow_dv_translate_item_tx_queue(dev, match_mask,
11740                                                         match_value,
11741                                                         items);
11742                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11743                         break;
11744                 case RTE_FLOW_ITEM_TYPE_GTP:
11745                         flow_dv_translate_item_gtp(match_mask, match_value,
11746                                                    items, tunnel);
11747                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11748                         last_item = MLX5_FLOW_LAYER_GTP;
11749                         break;
11750                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11751                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11752                                                           match_value,
11753                                                           items);
11754                         if (ret)
11755                                 return rte_flow_error_set(error, -ret,
11756                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11757                                         "cannot create GTP PSC item");
11758                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11759                         break;
11760                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11761                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11762                                 /* Create it only the first time to be used. */
11763                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11764                                 if (ret)
11765                                         return rte_flow_error_set
11766                                                 (error, -ret,
11767                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11768                                                 NULL,
11769                                                 "cannot create eCPRI parser");
11770                         }
11771                         /* Adjust the length matcher and device flow value. */
11772                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11773                         dev_flow->dv.value.size =
11774                                         MLX5_ST_SZ_BYTES(fte_match_param);
11775                         flow_dv_translate_item_ecpri(dev, match_mask,
11776                                                      match_value, items);
11777                         /* No other protocol should follow eCPRI layer. */
11778                         last_item = MLX5_FLOW_LAYER_ECPRI;
11779                         break;
11780                 default:
11781                         break;
11782                 }
11783                 item_flags |= last_item;
11784         }
11785         /*
11786          * When E-Switch mode is enabled, we have two cases where we need to
11787          * set the source port manually.
11788          * The first one, is in case of Nic steering rule, and the second is
11789          * E-Switch rule where no port_id item was found. In both cases
11790          * the source port is set according the current port in use.
11791          */
11792         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11793             (priv->representor || priv->master)) {
11794                 if (flow_dv_translate_item_port_id(dev, match_mask,
11795                                                    match_value, NULL, attr))
11796                         return -rte_errno;
11797         }
11798 #ifdef RTE_LIBRTE_MLX5_DEBUG
11799         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11800                                               dev_flow->dv.value.buf));
11801 #endif
11802         /*
11803          * Layers may be already initialized from prefix flow if this dev_flow
11804          * is the suffix flow.
11805          */
11806         handle->layers |= item_flags;
11807         if (action_flags & MLX5_FLOW_ACTION_RSS)
11808                 flow_dv_hashfields_set(dev_flow, rss_desc);
11809         /* If has RSS action in the sample action, the Sample/Mirror resource
11810          * should be registered after the hash filed be update.
11811          */
11812         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11813                 ret = flow_dv_translate_action_sample(dev,
11814                                                       sample,
11815                                                       dev_flow, attr,
11816                                                       &num_of_dest,
11817                                                       sample_actions,
11818                                                       &sample_res,
11819                                                       error);
11820                 if (ret < 0)
11821                         return ret;
11822                 ret = flow_dv_create_action_sample(dev,
11823                                                    dev_flow,
11824                                                    num_of_dest,
11825                                                    &sample_res,
11826                                                    &mdest_res,
11827                                                    sample_actions,
11828                                                    action_flags,
11829                                                    error);
11830                 if (ret < 0)
11831                         return rte_flow_error_set
11832                                                 (error, rte_errno,
11833                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11834                                                 NULL,
11835                                                 "cannot create sample action");
11836                 if (num_of_dest > 1) {
11837                         dev_flow->dv.actions[sample_act_pos] =
11838                         dev_flow->dv.dest_array_res->action;
11839                 } else {
11840                         dev_flow->dv.actions[sample_act_pos] =
11841                         dev_flow->dv.sample_res->verbs_action;
11842                 }
11843         }
11844         /*
11845          * For multiple destination (sample action with ratio=1), the encap
11846          * action and port id action will be combined into group action.
11847          * So need remove the original these actions in the flow and only
11848          * use the sample action instead of.
11849          */
11850         if (num_of_dest > 1 &&
11851             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11852                 int i;
11853                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11854
11855                 for (i = 0; i < actions_n; i++) {
11856                         if ((sample_act->dr_encap_action &&
11857                                 sample_act->dr_encap_action ==
11858                                 dev_flow->dv.actions[i]) ||
11859                                 (sample_act->dr_port_id_action &&
11860                                 sample_act->dr_port_id_action ==
11861                                 dev_flow->dv.actions[i]) ||
11862                                 (sample_act->dr_jump_action &&
11863                                 sample_act->dr_jump_action ==
11864                                 dev_flow->dv.actions[i]))
11865                                 continue;
11866                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11867                 }
11868                 memcpy((void *)dev_flow->dv.actions,
11869                                 (void *)temp_actions,
11870                                 tmp_actions_n * sizeof(void *));
11871                 actions_n = tmp_actions_n;
11872         }
11873         dev_flow->dv.actions_n = actions_n;
11874         dev_flow->act_flags = action_flags;
11875         /* Register matcher. */
11876         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11877                                     matcher.mask.size);
11878         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11879                                         matcher.priority);
11880         /* reserved field no needs to be set to 0 here. */
11881         tbl_key.domain = attr->transfer;
11882         tbl_key.direction = attr->egress;
11883         tbl_key.table_id = dev_flow->dv.group;
11884         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11885                                      tunnel, attr->group, error))
11886                 return -rte_errno;
11887         return 0;
11888 }
11889
11890 /**
11891  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11892  * and tunnel.
11893  *
11894  * @param[in, out] action
11895  *   Shred RSS action holding hash RX queue objects.
11896  * @param[in] hash_fields
11897  *   Defines combination of packet fields to participate in RX hash.
11898  * @param[in] tunnel
11899  *   Tunnel type
11900  * @param[in] hrxq_idx
11901  *   Hash RX queue index to set.
11902  *
11903  * @return
11904  *   0 on success, otherwise negative errno value.
11905  */
11906 static int
11907 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11908                               const uint64_t hash_fields,
11909                               uint32_t hrxq_idx)
11910 {
11911         uint32_t *hrxqs = action->hrxq;
11912
11913         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11914         case MLX5_RSS_HASH_IPV4:
11915                 /* fall-through. */
11916         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11917                 /* fall-through. */
11918         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11919                 hrxqs[0] = hrxq_idx;
11920                 return 0;
11921         case MLX5_RSS_HASH_IPV4_TCP:
11922                 /* fall-through. */
11923         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11924                 /* fall-through. */
11925         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11926                 hrxqs[1] = hrxq_idx;
11927                 return 0;
11928         case MLX5_RSS_HASH_IPV4_UDP:
11929                 /* fall-through. */
11930         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11931                 /* fall-through. */
11932         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11933                 hrxqs[2] = hrxq_idx;
11934                 return 0;
11935         case MLX5_RSS_HASH_IPV6:
11936                 /* fall-through. */
11937         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11938                 /* fall-through. */
11939         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11940                 hrxqs[3] = hrxq_idx;
11941                 return 0;
11942         case MLX5_RSS_HASH_IPV6_TCP:
11943                 /* fall-through. */
11944         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11945                 /* fall-through. */
11946         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11947                 hrxqs[4] = hrxq_idx;
11948                 return 0;
11949         case MLX5_RSS_HASH_IPV6_UDP:
11950                 /* fall-through. */
11951         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11952                 /* fall-through. */
11953         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11954                 hrxqs[5] = hrxq_idx;
11955                 return 0;
11956         case MLX5_RSS_HASH_NONE:
11957                 hrxqs[6] = hrxq_idx;
11958                 return 0;
11959         default:
11960                 return -1;
11961         }
11962 }
11963
11964 /**
11965  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11966  * and tunnel.
11967  *
11968  * @param[in] dev
11969  *   Pointer to the Ethernet device structure.
11970  * @param[in] idx
11971  *   Shared RSS action ID holding hash RX queue objects.
11972  * @param[in] hash_fields
11973  *   Defines combination of packet fields to participate in RX hash.
11974  * @param[in] tunnel
11975  *   Tunnel type
11976  *
11977  * @return
11978  *   Valid hash RX queue index, otherwise 0.
11979  */
11980 static uint32_t
11981 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11982                                  const uint64_t hash_fields)
11983 {
11984         struct mlx5_priv *priv = dev->data->dev_private;
11985         struct mlx5_shared_action_rss *shared_rss =
11986             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11987         const uint32_t *hrxqs = shared_rss->hrxq;
11988
11989         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11990         case MLX5_RSS_HASH_IPV4:
11991                 /* fall-through. */
11992         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11993                 /* fall-through. */
11994         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11995                 return hrxqs[0];
11996         case MLX5_RSS_HASH_IPV4_TCP:
11997                 /* fall-through. */
11998         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11999                 /* fall-through. */
12000         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12001                 return hrxqs[1];
12002         case MLX5_RSS_HASH_IPV4_UDP:
12003                 /* fall-through. */
12004         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12005                 /* fall-through. */
12006         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12007                 return hrxqs[2];
12008         case MLX5_RSS_HASH_IPV6:
12009                 /* fall-through. */
12010         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12011                 /* fall-through. */
12012         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12013                 return hrxqs[3];
12014         case MLX5_RSS_HASH_IPV6_TCP:
12015                 /* fall-through. */
12016         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12017                 /* fall-through. */
12018         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12019                 return hrxqs[4];
12020         case MLX5_RSS_HASH_IPV6_UDP:
12021                 /* fall-through. */
12022         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12023                 /* fall-through. */
12024         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12025                 return hrxqs[5];
12026         case MLX5_RSS_HASH_NONE:
12027                 return hrxqs[6];
12028         default:
12029                 return 0;
12030         }
12031
12032 }
12033
12034 /**
12035  * Apply the flow to the NIC, lock free,
12036  * (mutex should be acquired by caller).
12037  *
12038  * @param[in] dev
12039  *   Pointer to the Ethernet device structure.
12040  * @param[in, out] flow
12041  *   Pointer to flow structure.
12042  * @param[out] error
12043  *   Pointer to error structure.
12044  *
12045  * @return
12046  *   0 on success, a negative errno value otherwise and rte_errno is set.
12047  */
12048 static int
12049 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12050               struct rte_flow_error *error)
12051 {
12052         struct mlx5_flow_dv_workspace *dv;
12053         struct mlx5_flow_handle *dh;
12054         struct mlx5_flow_handle_dv *dv_h;
12055         struct mlx5_flow *dev_flow;
12056         struct mlx5_priv *priv = dev->data->dev_private;
12057         uint32_t handle_idx;
12058         int n;
12059         int err;
12060         int idx;
12061         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12062         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12063
12064         MLX5_ASSERT(wks);
12065         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12066                 dev_flow = &wks->flows[idx];
12067                 dv = &dev_flow->dv;
12068                 dh = dev_flow->handle;
12069                 dv_h = &dh->dvh;
12070                 n = dv->actions_n;
12071                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12072                         if (dv->transfer) {
12073                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12074                                 dv->actions[n++] = priv->sh->dr_drop_action;
12075                         } else {
12076 #ifdef HAVE_MLX5DV_DR
12077                                 /* DR supports drop action placeholder. */
12078                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12079                                 dv->actions[n++] = priv->sh->dr_drop_action;
12080 #else
12081                                 /* For DV we use the explicit drop queue. */
12082                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12083                                 dv->actions[n++] =
12084                                                 priv->drop_queue.hrxq->action;
12085 #endif
12086                         }
12087                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12088                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12089                         struct mlx5_hrxq *hrxq;
12090                         uint32_t hrxq_idx;
12091
12092                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12093                                                     &hrxq_idx);
12094                         if (!hrxq) {
12095                                 rte_flow_error_set
12096                                         (error, rte_errno,
12097                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12098                                          "cannot get hash queue");
12099                                 goto error;
12100                         }
12101                         dh->rix_hrxq = hrxq_idx;
12102                         dv->actions[n++] = hrxq->action;
12103                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12104                         struct mlx5_hrxq *hrxq = NULL;
12105                         uint32_t hrxq_idx;
12106
12107                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12108                                                 rss_desc->shared_rss,
12109                                                 dev_flow->hash_fields);
12110                         if (hrxq_idx)
12111                                 hrxq = mlx5_ipool_get
12112                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12113                                          hrxq_idx);
12114                         if (!hrxq) {
12115                                 rte_flow_error_set
12116                                         (error, rte_errno,
12117                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12118                                          "cannot get hash queue");
12119                                 goto error;
12120                         }
12121                         dh->rix_srss = rss_desc->shared_rss;
12122                         dv->actions[n++] = hrxq->action;
12123                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12124                         if (!priv->sh->default_miss_action) {
12125                                 rte_flow_error_set
12126                                         (error, rte_errno,
12127                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12128                                          "default miss action not be created.");
12129                                 goto error;
12130                         }
12131                         dv->actions[n++] = priv->sh->default_miss_action;
12132                 }
12133                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12134                                                (void *)&dv->value, n,
12135                                                dv->actions, &dh->drv_flow);
12136                 if (err) {
12137                         rte_flow_error_set(error, errno,
12138                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12139                                            NULL,
12140                                            "hardware refuses to create flow");
12141                         goto error;
12142                 }
12143                 if (priv->vmwa_context &&
12144                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12145                         /*
12146                          * The rule contains the VLAN pattern.
12147                          * For VF we are going to create VLAN
12148                          * interface to make hypervisor set correct
12149                          * e-Switch vport context.
12150                          */
12151                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12152                 }
12153         }
12154         return 0;
12155 error:
12156         err = rte_errno; /* Save rte_errno before cleanup. */
12157         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12158                        handle_idx, dh, next) {
12159                 /* hrxq is union, don't clear it if the flag is not set. */
12160                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12161                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12162                         dh->rix_hrxq = 0;
12163                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12164                         dh->rix_srss = 0;
12165                 }
12166                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12167                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12168         }
12169         rte_errno = err; /* Restore rte_errno. */
12170         return -rte_errno;
12171 }
12172
12173 void
12174 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12175                           struct mlx5_cache_entry *entry)
12176 {
12177         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12178                                                           entry);
12179
12180         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12181         mlx5_free(cache);
12182 }
12183
12184 /**
12185  * Release the flow matcher.
12186  *
12187  * @param dev
12188  *   Pointer to Ethernet device.
12189  * @param port_id
12190  *   Index to port ID action resource.
12191  *
12192  * @return
12193  *   1 while a reference on it exists, 0 when freed.
12194  */
12195 static int
12196 flow_dv_matcher_release(struct rte_eth_dev *dev,
12197                         struct mlx5_flow_handle *handle)
12198 {
12199         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12200         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12201                                                             typeof(*tbl), tbl);
12202         int ret;
12203
12204         MLX5_ASSERT(matcher->matcher_object);
12205         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12206         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12207         return ret;
12208 }
12209
12210 /**
12211  * Release encap_decap resource.
12212  *
12213  * @param list
12214  *   Pointer to the hash list.
12215  * @param entry
12216  *   Pointer to exist resource entry object.
12217  */
12218 void
12219 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12220                               struct mlx5_hlist_entry *entry)
12221 {
12222         struct mlx5_dev_ctx_shared *sh = list->ctx;
12223         struct mlx5_flow_dv_encap_decap_resource *res =
12224                 container_of(entry, typeof(*res), entry);
12225
12226         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12227         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12228 }
12229
12230 /**
12231  * Release an encap/decap resource.
12232  *
12233  * @param dev
12234  *   Pointer to Ethernet device.
12235  * @param encap_decap_idx
12236  *   Index of encap decap resource.
12237  *
12238  * @return
12239  *   1 while a reference on it exists, 0 when freed.
12240  */
12241 static int
12242 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12243                                      uint32_t encap_decap_idx)
12244 {
12245         struct mlx5_priv *priv = dev->data->dev_private;
12246         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12247
12248         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12249                                         encap_decap_idx);
12250         if (!cache_resource)
12251                 return 0;
12252         MLX5_ASSERT(cache_resource->action);
12253         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12254                                      &cache_resource->entry);
12255 }
12256
12257 /**
12258  * Release an jump to table action resource.
12259  *
12260  * @param dev
12261  *   Pointer to Ethernet device.
12262  * @param rix_jump
12263  *   Index to the jump action resource.
12264  *
12265  * @return
12266  *   1 while a reference on it exists, 0 when freed.
12267  */
12268 static int
12269 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12270                                   uint32_t rix_jump)
12271 {
12272         struct mlx5_priv *priv = dev->data->dev_private;
12273         struct mlx5_flow_tbl_data_entry *tbl_data;
12274
12275         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12276                                   rix_jump);
12277         if (!tbl_data)
12278                 return 0;
12279         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12280 }
12281
12282 void
12283 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12284                          struct mlx5_hlist_entry *entry)
12285 {
12286         struct mlx5_flow_dv_modify_hdr_resource *res =
12287                 container_of(entry, typeof(*res), entry);
12288
12289         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12290         mlx5_free(entry);
12291 }
12292
12293 /**
12294  * Release a modify-header resource.
12295  *
12296  * @param dev
12297  *   Pointer to Ethernet device.
12298  * @param handle
12299  *   Pointer to mlx5_flow_handle.
12300  *
12301  * @return
12302  *   1 while a reference on it exists, 0 when freed.
12303  */
12304 static int
12305 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12306                                     struct mlx5_flow_handle *handle)
12307 {
12308         struct mlx5_priv *priv = dev->data->dev_private;
12309         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12310
12311         MLX5_ASSERT(entry->action);
12312         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12313 }
12314
12315 void
12316 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12317                           struct mlx5_cache_entry *entry)
12318 {
12319         struct mlx5_dev_ctx_shared *sh = list->ctx;
12320         struct mlx5_flow_dv_port_id_action_resource *cache =
12321                         container_of(entry, typeof(*cache), entry);
12322
12323         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12324         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12325 }
12326
12327 /**
12328  * Release port ID action resource.
12329  *
12330  * @param dev
12331  *   Pointer to Ethernet device.
12332  * @param handle
12333  *   Pointer to mlx5_flow_handle.
12334  *
12335  * @return
12336  *   1 while a reference on it exists, 0 when freed.
12337  */
12338 static int
12339 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12340                                         uint32_t port_id)
12341 {
12342         struct mlx5_priv *priv = dev->data->dev_private;
12343         struct mlx5_flow_dv_port_id_action_resource *cache;
12344
12345         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12346         if (!cache)
12347                 return 0;
12348         MLX5_ASSERT(cache->action);
12349         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12350                                      &cache->entry);
12351 }
12352
12353 /**
12354  * Release shared RSS action resource.
12355  *
12356  * @param dev
12357  *   Pointer to Ethernet device.
12358  * @param srss
12359  *   Shared RSS action index.
12360  */
12361 static void
12362 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12363 {
12364         struct mlx5_priv *priv = dev->data->dev_private;
12365         struct mlx5_shared_action_rss *shared_rss;
12366
12367         shared_rss = mlx5_ipool_get
12368                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12369         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12370 }
12371
12372 void
12373 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12374                             struct mlx5_cache_entry *entry)
12375 {
12376         struct mlx5_dev_ctx_shared *sh = list->ctx;
12377         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12378                         container_of(entry, typeof(*cache), entry);
12379
12380         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12381         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12382 }
12383
12384 /**
12385  * Release push vlan action resource.
12386  *
12387  * @param dev
12388  *   Pointer to Ethernet device.
12389  * @param handle
12390  *   Pointer to mlx5_flow_handle.
12391  *
12392  * @return
12393  *   1 while a reference on it exists, 0 when freed.
12394  */
12395 static int
12396 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12397                                           struct mlx5_flow_handle *handle)
12398 {
12399         struct mlx5_priv *priv = dev->data->dev_private;
12400         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12401         uint32_t idx = handle->dvh.rix_push_vlan;
12402
12403         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12404         if (!cache)
12405                 return 0;
12406         MLX5_ASSERT(cache->action);
12407         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12408                                      &cache->entry);
12409 }
12410
12411 /**
12412  * Release the fate resource.
12413  *
12414  * @param dev
12415  *   Pointer to Ethernet device.
12416  * @param handle
12417  *   Pointer to mlx5_flow_handle.
12418  */
12419 static void
12420 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12421                                struct mlx5_flow_handle *handle)
12422 {
12423         if (!handle->rix_fate)
12424                 return;
12425         switch (handle->fate_action) {
12426         case MLX5_FLOW_FATE_QUEUE:
12427                 mlx5_hrxq_release(dev, handle->rix_hrxq);
12428                 break;
12429         case MLX5_FLOW_FATE_JUMP:
12430                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12431                 break;
12432         case MLX5_FLOW_FATE_PORT_ID:
12433                 flow_dv_port_id_action_resource_release(dev,
12434                                 handle->rix_port_id_action);
12435                 break;
12436         default:
12437                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12438                 break;
12439         }
12440         handle->rix_fate = 0;
12441 }
12442
12443 void
12444 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12445                          struct mlx5_cache_entry *entry)
12446 {
12447         struct mlx5_flow_dv_sample_resource *cache_resource =
12448                         container_of(entry, typeof(*cache_resource), entry);
12449         struct rte_eth_dev *dev = cache_resource->dev;
12450         struct mlx5_priv *priv = dev->data->dev_private;
12451
12452         if (cache_resource->verbs_action)
12453                 claim_zero(mlx5_flow_os_destroy_flow_action
12454                                 (cache_resource->verbs_action));
12455         if (cache_resource->normal_path_tbl)
12456                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12457                         cache_resource->normal_path_tbl);
12458         flow_dv_sample_sub_actions_release(dev,
12459                                 &cache_resource->sample_idx);
12460         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12461                         cache_resource->idx);
12462         DRV_LOG(DEBUG, "sample resource %p: removed",
12463                 (void *)cache_resource);
12464 }
12465
12466 /**
12467  * Release an sample resource.
12468  *
12469  * @param dev
12470  *   Pointer to Ethernet device.
12471  * @param handle
12472  *   Pointer to mlx5_flow_handle.
12473  *
12474  * @return
12475  *   1 while a reference on it exists, 0 when freed.
12476  */
12477 static int
12478 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12479                                      struct mlx5_flow_handle *handle)
12480 {
12481         struct mlx5_priv *priv = dev->data->dev_private;
12482         struct mlx5_flow_dv_sample_resource *cache_resource;
12483
12484         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12485                          handle->dvh.rix_sample);
12486         if (!cache_resource)
12487                 return 0;
12488         MLX5_ASSERT(cache_resource->verbs_action);
12489         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12490                                      &cache_resource->entry);
12491 }
12492
12493 void
12494 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12495                              struct mlx5_cache_entry *entry)
12496 {
12497         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12498                         container_of(entry, typeof(*cache_resource), entry);
12499         struct rte_eth_dev *dev = cache_resource->dev;
12500         struct mlx5_priv *priv = dev->data->dev_private;
12501         uint32_t i = 0;
12502
12503         MLX5_ASSERT(cache_resource->action);
12504         if (cache_resource->action)
12505                 claim_zero(mlx5_flow_os_destroy_flow_action
12506                                         (cache_resource->action));
12507         for (; i < cache_resource->num_of_dest; i++)
12508                 flow_dv_sample_sub_actions_release(dev,
12509                                 &cache_resource->sample_idx[i]);
12510         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12511                         cache_resource->idx);
12512         DRV_LOG(DEBUG, "destination array resource %p: removed",
12513                 (void *)cache_resource);
12514 }
12515
12516 /**
12517  * Release an destination array resource.
12518  *
12519  * @param dev
12520  *   Pointer to Ethernet device.
12521  * @param handle
12522  *   Pointer to mlx5_flow_handle.
12523  *
12524  * @return
12525  *   1 while a reference on it exists, 0 when freed.
12526  */
12527 static int
12528 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12529                                     struct mlx5_flow_handle *handle)
12530 {
12531         struct mlx5_priv *priv = dev->data->dev_private;
12532         struct mlx5_flow_dv_dest_array_resource *cache;
12533
12534         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12535                                handle->dvh.rix_dest_array);
12536         if (!cache)
12537                 return 0;
12538         MLX5_ASSERT(cache->action);
12539         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12540                                      &cache->entry);
12541 }
12542
12543 static void
12544 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12545 {
12546         struct mlx5_priv *priv = dev->data->dev_private;
12547         struct mlx5_dev_ctx_shared *sh = priv->sh;
12548         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12549                                 sh->geneve_tlv_option_resource;
12550         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12551         if (geneve_opt_resource) {
12552                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12553                                          __ATOMIC_RELAXED))) {
12554                         claim_zero(mlx5_devx_cmd_destroy
12555                                         (geneve_opt_resource->obj));
12556                         mlx5_free(sh->geneve_tlv_option_resource);
12557                         sh->geneve_tlv_option_resource = NULL;
12558                 }
12559         }
12560         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12561 }
12562
12563 /**
12564  * Remove the flow from the NIC but keeps it in memory.
12565  * Lock free, (mutex should be acquired by caller).
12566  *
12567  * @param[in] dev
12568  *   Pointer to Ethernet device.
12569  * @param[in, out] flow
12570  *   Pointer to flow structure.
12571  */
12572 static void
12573 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12574 {
12575         struct mlx5_flow_handle *dh;
12576         uint32_t handle_idx;
12577         struct mlx5_priv *priv = dev->data->dev_private;
12578
12579         if (!flow)
12580                 return;
12581         handle_idx = flow->dev_handles;
12582         while (handle_idx) {
12583                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12584                                     handle_idx);
12585                 if (!dh)
12586                         return;
12587                 if (dh->drv_flow) {
12588                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12589                         dh->drv_flow = NULL;
12590                 }
12591                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12592                         flow_dv_fate_resource_release(dev, dh);
12593                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12594                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12595                 handle_idx = dh->next.next;
12596         }
12597 }
12598
12599 /**
12600  * Remove the flow from the NIC and the memory.
12601  * Lock free, (mutex should be acquired by caller).
12602  *
12603  * @param[in] dev
12604  *   Pointer to the Ethernet device structure.
12605  * @param[in, out] flow
12606  *   Pointer to flow structure.
12607  */
12608 static void
12609 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12610 {
12611         struct mlx5_flow_handle *dev_handle;
12612         struct mlx5_priv *priv = dev->data->dev_private;
12613         uint32_t srss = 0;
12614
12615         if (!flow)
12616                 return;
12617         flow_dv_remove(dev, flow);
12618         if (flow->counter) {
12619                 flow_dv_counter_free(dev, flow->counter);
12620                 flow->counter = 0;
12621         }
12622         if (flow->meter) {
12623                 struct mlx5_flow_meter *fm;
12624
12625                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12626                                     flow->meter);
12627                 if (fm)
12628                         mlx5_flow_meter_detach(fm);
12629                 flow->meter = 0;
12630         }
12631         if (flow->age)
12632                 flow_dv_aso_age_release(dev, flow->age);
12633         if (flow->geneve_tlv_option) {
12634                 flow_dv_geneve_tlv_option_resource_release(dev);
12635                 flow->geneve_tlv_option = 0;
12636         }
12637         while (flow->dev_handles) {
12638                 uint32_t tmp_idx = flow->dev_handles;
12639
12640                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12641                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12642                 if (!dev_handle)
12643                         return;
12644                 flow->dev_handles = dev_handle->next.next;
12645                 if (dev_handle->dvh.matcher)
12646                         flow_dv_matcher_release(dev, dev_handle);
12647                 if (dev_handle->dvh.rix_sample)
12648                         flow_dv_sample_resource_release(dev, dev_handle);
12649                 if (dev_handle->dvh.rix_dest_array)
12650                         flow_dv_dest_array_resource_release(dev, dev_handle);
12651                 if (dev_handle->dvh.rix_encap_decap)
12652                         flow_dv_encap_decap_resource_release(dev,
12653                                 dev_handle->dvh.rix_encap_decap);
12654                 if (dev_handle->dvh.modify_hdr)
12655                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12656                 if (dev_handle->dvh.rix_push_vlan)
12657                         flow_dv_push_vlan_action_resource_release(dev,
12658                                                                   dev_handle);
12659                 if (dev_handle->dvh.rix_tag)
12660                         flow_dv_tag_release(dev,
12661                                             dev_handle->dvh.rix_tag);
12662                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12663                         flow_dv_fate_resource_release(dev, dev_handle);
12664                 else if (!srss)
12665                         srss = dev_handle->rix_srss;
12666                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12667                            tmp_idx);
12668         }
12669         if (srss)
12670                 flow_dv_shared_rss_action_release(dev, srss);
12671 }
12672
12673 /**
12674  * Release array of hash RX queue objects.
12675  * Helper function.
12676  *
12677  * @param[in] dev
12678  *   Pointer to the Ethernet device structure.
12679  * @param[in, out] hrxqs
12680  *   Array of hash RX queue objects.
12681  *
12682  * @return
12683  *   Total number of references to hash RX queue objects in *hrxqs* array
12684  *   after this operation.
12685  */
12686 static int
12687 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12688                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12689 {
12690         size_t i;
12691         int remaining = 0;
12692
12693         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12694                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12695
12696                 if (!ret)
12697                         (*hrxqs)[i] = 0;
12698                 remaining += ret;
12699         }
12700         return remaining;
12701 }
12702
12703 /**
12704  * Release all hash RX queue objects representing shared RSS action.
12705  *
12706  * @param[in] dev
12707  *   Pointer to the Ethernet device structure.
12708  * @param[in, out] action
12709  *   Shared RSS action to remove hash RX queue objects from.
12710  *
12711  * @return
12712  *   Total number of references to hash RX queue objects stored in *action*
12713  *   after this operation.
12714  *   Expected to be 0 if no external references held.
12715  */
12716 static int
12717 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12718                                  struct mlx5_shared_action_rss *shared_rss)
12719 {
12720         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12721 }
12722
12723 /**
12724  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12725  * user input.
12726  *
12727  * Only one hash value is available for one L3+L4 combination:
12728  * for example:
12729  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12730  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12731  * same slot in mlx5_rss_hash_fields.
12732  *
12733  * @param[in] rss
12734  *   Pointer to the shared action RSS conf.
12735  * @param[in, out] hash_field
12736  *   hash_field variable needed to be adjusted.
12737  *
12738  * @return
12739  *   void
12740  */
12741 static void
12742 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12743                                      uint64_t *hash_field)
12744 {
12745         uint64_t rss_types = rss->origin.types;
12746
12747         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12748         case MLX5_RSS_HASH_IPV4:
12749                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12750                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12751                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12752                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12753                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12754                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12755                         else
12756                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12757                 }
12758                 return;
12759         case MLX5_RSS_HASH_IPV6:
12760                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12761                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12762                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12763                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12764                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12765                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12766                         else
12767                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12768                 }
12769                 return;
12770         case MLX5_RSS_HASH_IPV4_UDP:
12771                 /* fall-through. */
12772         case MLX5_RSS_HASH_IPV6_UDP:
12773                 if (rss_types & ETH_RSS_UDP) {
12774                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12775                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12776                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12777                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12778                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12779                         else
12780                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12781                 }
12782                 return;
12783         case MLX5_RSS_HASH_IPV4_TCP:
12784                 /* fall-through. */
12785         case MLX5_RSS_HASH_IPV6_TCP:
12786                 if (rss_types & ETH_RSS_TCP) {
12787                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12788                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12789                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12790                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12791                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12792                         else
12793                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12794                 }
12795                 return;
12796         default:
12797                 return;
12798         }
12799 }
12800
12801 /**
12802  * Setup shared RSS action.
12803  * Prepare set of hash RX queue objects sufficient to handle all valid
12804  * hash_fields combinations (see enum ibv_rx_hash_fields).
12805  *
12806  * @param[in] dev
12807  *   Pointer to the Ethernet device structure.
12808  * @param[in] action_idx
12809  *   Shared RSS action ipool index.
12810  * @param[in, out] action
12811  *   Partially initialized shared RSS action.
12812  * @param[out] error
12813  *   Perform verbose error reporting if not NULL. Initialized in case of
12814  *   error only.
12815  *
12816  * @return
12817  *   0 on success, otherwise negative errno value.
12818  */
12819 static int
12820 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12821                            uint32_t action_idx,
12822                            struct mlx5_shared_action_rss *shared_rss,
12823                            struct rte_flow_error *error)
12824 {
12825         struct mlx5_flow_rss_desc rss_desc = { 0 };
12826         size_t i;
12827         int err;
12828
12829         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12830                 return rte_flow_error_set(error, rte_errno,
12831                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12832                                           "cannot setup indirection table");
12833         }
12834         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12835         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12836         rss_desc.const_q = shared_rss->origin.queue;
12837         rss_desc.queue_num = shared_rss->origin.queue_num;
12838         /* Set non-zero value to indicate a shared RSS. */
12839         rss_desc.shared_rss = action_idx;
12840         rss_desc.ind_tbl = shared_rss->ind_tbl;
12841         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12842                 uint32_t hrxq_idx;
12843                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12844                 int tunnel = 0;
12845
12846                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12847                 if (shared_rss->origin.level > 1) {
12848                         hash_fields |= IBV_RX_HASH_INNER;
12849                         tunnel = 1;
12850                 }
12851                 rss_desc.tunnel = tunnel;
12852                 rss_desc.hash_fields = hash_fields;
12853                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12854                 if (!hrxq_idx) {
12855                         rte_flow_error_set
12856                                 (error, rte_errno,
12857                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12858                                  "cannot get hash queue");
12859                         goto error_hrxq_new;
12860                 }
12861                 err = __flow_dv_action_rss_hrxq_set
12862                         (shared_rss, hash_fields, hrxq_idx);
12863                 MLX5_ASSERT(!err);
12864         }
12865         return 0;
12866 error_hrxq_new:
12867         err = rte_errno;
12868         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12869         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12870                 shared_rss->ind_tbl = NULL;
12871         rte_errno = err;
12872         return -rte_errno;
12873 }
12874
12875 /**
12876  * Create shared RSS action.
12877  *
12878  * @param[in] dev
12879  *   Pointer to the Ethernet device structure.
12880  * @param[in] conf
12881  *   Shared action configuration.
12882  * @param[in] rss
12883  *   RSS action specification used to create shared action.
12884  * @param[out] error
12885  *   Perform verbose error reporting if not NULL. Initialized in case of
12886  *   error only.
12887  *
12888  * @return
12889  *   A valid shared action ID in case of success, 0 otherwise and
12890  *   rte_errno is set.
12891  */
12892 static uint32_t
12893 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12894                             const struct rte_flow_shared_action_conf *conf,
12895                             const struct rte_flow_action_rss *rss,
12896                             struct rte_flow_error *error)
12897 {
12898         struct mlx5_priv *priv = dev->data->dev_private;
12899         struct mlx5_shared_action_rss *shared_rss = NULL;
12900         void *queue = NULL;
12901         struct rte_flow_action_rss *origin;
12902         const uint8_t *rss_key;
12903         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12904         uint32_t idx;
12905
12906         RTE_SET_USED(conf);
12907         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12908                             0, SOCKET_ID_ANY);
12909         shared_rss = mlx5_ipool_zmalloc
12910                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12911         if (!shared_rss || !queue) {
12912                 rte_flow_error_set(error, ENOMEM,
12913                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12914                                    "cannot allocate resource memory");
12915                 goto error_rss_init;
12916         }
12917         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12918                 rte_flow_error_set(error, E2BIG,
12919                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12920                                    "rss action number out of range");
12921                 goto error_rss_init;
12922         }
12923         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12924                                           sizeof(*shared_rss->ind_tbl),
12925                                           0, SOCKET_ID_ANY);
12926         if (!shared_rss->ind_tbl) {
12927                 rte_flow_error_set(error, ENOMEM,
12928                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12929                                    "cannot allocate resource memory");
12930                 goto error_rss_init;
12931         }
12932         memcpy(queue, rss->queue, queue_size);
12933         shared_rss->ind_tbl->queues = queue;
12934         shared_rss->ind_tbl->queues_n = rss->queue_num;
12935         origin = &shared_rss->origin;
12936         origin->func = rss->func;
12937         origin->level = rss->level;
12938         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12939         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12940         /* NULL RSS key indicates default RSS key. */
12941         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12942         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12943         origin->key = &shared_rss->key[0];
12944         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12945         origin->queue = queue;
12946         origin->queue_num = rss->queue_num;
12947         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12948                 goto error_rss_init;
12949         rte_spinlock_init(&shared_rss->action_rss_sl);
12950         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12951         rte_spinlock_lock(&priv->shared_act_sl);
12952         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12953                      &priv->rss_shared_actions, idx, shared_rss, next);
12954         rte_spinlock_unlock(&priv->shared_act_sl);
12955         return idx;
12956 error_rss_init:
12957         if (shared_rss) {
12958                 if (shared_rss->ind_tbl)
12959                         mlx5_free(shared_rss->ind_tbl);
12960                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12961                                 idx);
12962         }
12963         if (queue)
12964                 mlx5_free(queue);
12965         return 0;
12966 }
12967
12968 /**
12969  * Destroy the shared RSS action.
12970  * Release related hash RX queue objects.
12971  *
12972  * @param[in] dev
12973  *   Pointer to the Ethernet device structure.
12974  * @param[in] idx
12975  *   The shared RSS action object ID to be removed.
12976  * @param[out] error
12977  *   Perform verbose error reporting if not NULL. Initialized in case of
12978  *   error only.
12979  *
12980  * @return
12981  *   0 on success, otherwise negative errno value.
12982  */
12983 static int
12984 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12985                              struct rte_flow_error *error)
12986 {
12987         struct mlx5_priv *priv = dev->data->dev_private;
12988         struct mlx5_shared_action_rss *shared_rss =
12989             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12990         uint32_t old_refcnt = 1;
12991         int remaining;
12992         uint16_t *queue = NULL;
12993
12994         if (!shared_rss)
12995                 return rte_flow_error_set(error, EINVAL,
12996                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12997                                           "invalid shared action");
12998         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12999         if (remaining)
13000                 return rte_flow_error_set(error, EBUSY,
13001                                           RTE_FLOW_ERROR_TYPE_ACTION,
13002                                           NULL,
13003                                           "shared rss hrxq has references");
13004         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13005                                          0, 0, __ATOMIC_ACQUIRE,
13006                                          __ATOMIC_RELAXED))
13007                 return rte_flow_error_set(error, EBUSY,
13008                                           RTE_FLOW_ERROR_TYPE_ACTION,
13009                                           NULL,
13010                                           "shared rss has references");
13011         queue = shared_rss->ind_tbl->queues;
13012         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13013         if (remaining)
13014                 return rte_flow_error_set(error, EBUSY,
13015                                           RTE_FLOW_ERROR_TYPE_ACTION,
13016                                           NULL,
13017                                           "shared rss indirection table has"
13018                                           " references");
13019         mlx5_free(queue);
13020         rte_spinlock_lock(&priv->shared_act_sl);
13021         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13022                      &priv->rss_shared_actions, idx, shared_rss, next);
13023         rte_spinlock_unlock(&priv->shared_act_sl);
13024         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13025                         idx);
13026         return 0;
13027 }
13028
13029 /**
13030  * Create shared action, lock free,
13031  * (mutex should be acquired by caller).
13032  * Dispatcher for action type specific call.
13033  *
13034  * @param[in] dev
13035  *   Pointer to the Ethernet device structure.
13036  * @param[in] conf
13037  *   Shared action configuration.
13038  * @param[in] action
13039  *   Action specification used to create shared action.
13040  * @param[out] error
13041  *   Perform verbose error reporting if not NULL. Initialized in case of
13042  *   error only.
13043  *
13044  * @return
13045  *   A valid shared action handle in case of success, NULL otherwise and
13046  *   rte_errno is set.
13047  */
13048 static struct rte_flow_shared_action *
13049 flow_dv_action_create(struct rte_eth_dev *dev,
13050                       const struct rte_flow_shared_action_conf *conf,
13051                       const struct rte_flow_action *action,
13052                       struct rte_flow_error *err)
13053 {
13054         uint32_t idx = 0;
13055         uint32_t ret = 0;
13056
13057         switch (action->type) {
13058         case RTE_FLOW_ACTION_TYPE_RSS:
13059                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13060                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
13061                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13062                 break;
13063         case RTE_FLOW_ACTION_TYPE_AGE:
13064                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13065                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
13066                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13067                 if (ret) {
13068                         struct mlx5_aso_age_action *aso_age =
13069                                               flow_aso_age_get_by_idx(dev, ret);
13070
13071                         if (!aso_age->age_params.context)
13072                                 aso_age->age_params.context =
13073                                                          (void *)(uintptr_t)idx;
13074                 }
13075                 break;
13076         default:
13077                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13078                                    NULL, "action type not supported");
13079                 break;
13080         }
13081         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
13082 }
13083
13084 /**
13085  * Destroy the shared action.
13086  * Release action related resources on the NIC and the memory.
13087  * Lock free, (mutex should be acquired by caller).
13088  * Dispatcher for action type specific call.
13089  *
13090  * @param[in] dev
13091  *   Pointer to the Ethernet device structure.
13092  * @param[in] action
13093  *   The shared action object to be removed.
13094  * @param[out] error
13095  *   Perform verbose error reporting if not NULL. Initialized in case of
13096  *   error only.
13097  *
13098  * @return
13099  *   0 on success, otherwise negative errno value.
13100  */
13101 static int
13102 flow_dv_action_destroy(struct rte_eth_dev *dev,
13103                        struct rte_flow_shared_action *action,
13104                        struct rte_flow_error *error)
13105 {
13106         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13107         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13108         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13109         int ret;
13110
13111         switch (type) {
13112         case MLX5_SHARED_ACTION_TYPE_RSS:
13113                 return __flow_dv_action_rss_release(dev, idx, error);
13114         case MLX5_SHARED_ACTION_TYPE_AGE:
13115                 ret = flow_dv_aso_age_release(dev, idx);
13116                 if (ret)
13117                         /*
13118                          * In this case, the last flow has a reference will
13119                          * actually release the age action.
13120                          */
13121                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
13122                                 " released with references %d.", idx, ret);
13123                 return 0;
13124         default:
13125                 return rte_flow_error_set(error, ENOTSUP,
13126                                           RTE_FLOW_ERROR_TYPE_ACTION,
13127                                           NULL,
13128                                           "action type not supported");
13129         }
13130 }
13131
13132 /**
13133  * Updates in place shared RSS action configuration.
13134  *
13135  * @param[in] dev
13136  *   Pointer to the Ethernet device structure.
13137  * @param[in] idx
13138  *   The shared RSS action object ID to be updated.
13139  * @param[in] action_conf
13140  *   RSS action specification used to modify *shared_rss*.
13141  * @param[out] error
13142  *   Perform verbose error reporting if not NULL. Initialized in case of
13143  *   error only.
13144  *
13145  * @return
13146  *   0 on success, otherwise negative errno value.
13147  * @note: currently only support update of RSS queues.
13148  */
13149 static int
13150 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13151                             const struct rte_flow_action_rss *action_conf,
13152                             struct rte_flow_error *error)
13153 {
13154         struct mlx5_priv *priv = dev->data->dev_private;
13155         struct mlx5_shared_action_rss *shared_rss =
13156             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13157         int ret = 0;
13158         void *queue = NULL;
13159         uint16_t *queue_old = NULL;
13160         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13161
13162         if (!shared_rss)
13163                 return rte_flow_error_set(error, EINVAL,
13164                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13165                                           "invalid shared action to update");
13166         if (priv->obj_ops.ind_table_modify == NULL)
13167                 return rte_flow_error_set(error, ENOTSUP,
13168                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13169                                           "cannot modify indirection table");
13170         queue = mlx5_malloc(MLX5_MEM_ZERO,
13171                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13172                             0, SOCKET_ID_ANY);
13173         if (!queue)
13174                 return rte_flow_error_set(error, ENOMEM,
13175                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13176                                           NULL,
13177                                           "cannot allocate resource memory");
13178         memcpy(queue, action_conf->queue, queue_size);
13179         MLX5_ASSERT(shared_rss->ind_tbl);
13180         rte_spinlock_lock(&shared_rss->action_rss_sl);
13181         queue_old = shared_rss->ind_tbl->queues;
13182         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13183                                         queue, action_conf->queue_num, true);
13184         if (ret) {
13185                 mlx5_free(queue);
13186                 ret = rte_flow_error_set(error, rte_errno,
13187                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13188                                           "cannot update indirection table");
13189         } else {
13190                 mlx5_free(queue_old);
13191                 shared_rss->origin.queue = queue;
13192                 shared_rss->origin.queue_num = action_conf->queue_num;
13193         }
13194         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13195         return ret;
13196 }
13197
13198 /**
13199  * Updates in place shared action configuration, lock free,
13200  * (mutex should be acquired by caller).
13201  *
13202  * @param[in] dev
13203  *   Pointer to the Ethernet device structure.
13204  * @param[in] action
13205  *   The shared action object to be updated.
13206  * @param[in] action_conf
13207  *   Action specification used to modify *action*.
13208  *   *action_conf* should be of type correlating with type of the *action*,
13209  *   otherwise considered as invalid.
13210  * @param[out] error
13211  *   Perform verbose error reporting if not NULL. Initialized in case of
13212  *   error only.
13213  *
13214  * @return
13215  *   0 on success, otherwise negative errno value.
13216  */
13217 static int
13218 flow_dv_action_update(struct rte_eth_dev *dev,
13219                         struct rte_flow_shared_action *action,
13220                         const void *action_conf,
13221                         struct rte_flow_error *err)
13222 {
13223         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13224         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13225         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13226
13227         switch (type) {
13228         case MLX5_SHARED_ACTION_TYPE_RSS:
13229                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13230         default:
13231                 return rte_flow_error_set(err, ENOTSUP,
13232                                           RTE_FLOW_ERROR_TYPE_ACTION,
13233                                           NULL,
13234                                           "action type update not supported");
13235         }
13236 }
13237
13238 static int
13239 flow_dv_action_query(struct rte_eth_dev *dev,
13240                      const struct rte_flow_shared_action *action, void *data,
13241                      struct rte_flow_error *error)
13242 {
13243         struct mlx5_age_param *age_param;
13244         struct rte_flow_query_age *resp;
13245         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13246         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13247         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13248
13249         switch (type) {
13250         case MLX5_SHARED_ACTION_TYPE_AGE:
13251                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13252                 resp = data;
13253                 resp->aged = __atomic_load_n(&age_param->state,
13254                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13255                                                                           1 : 0;
13256                 resp->sec_since_last_hit_valid = !resp->aged;
13257                 if (resp->sec_since_last_hit_valid)
13258                         resp->sec_since_last_hit = __atomic_load_n
13259                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13260                 return 0;
13261         default:
13262                 return rte_flow_error_set(error, ENOTSUP,
13263                                           RTE_FLOW_ERROR_TYPE_ACTION,
13264                                           NULL,
13265                                           "action type query not supported");
13266         }
13267 }
13268
13269 /**
13270  * Query a dv flow  rule for its statistics via devx.
13271  *
13272  * @param[in] dev
13273  *   Pointer to Ethernet device.
13274  * @param[in] flow
13275  *   Pointer to the sub flow.
13276  * @param[out] data
13277  *   data retrieved by the query.
13278  * @param[out] error
13279  *   Perform verbose error reporting if not NULL.
13280  *
13281  * @return
13282  *   0 on success, a negative errno value otherwise and rte_errno is set.
13283  */
13284 static int
13285 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13286                     void *data, struct rte_flow_error *error)
13287 {
13288         struct mlx5_priv *priv = dev->data->dev_private;
13289         struct rte_flow_query_count *qc = data;
13290
13291         if (!priv->config.devx)
13292                 return rte_flow_error_set(error, ENOTSUP,
13293                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13294                                           NULL,
13295                                           "counters are not supported");
13296         if (flow->counter) {
13297                 uint64_t pkts, bytes;
13298                 struct mlx5_flow_counter *cnt;
13299
13300                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13301                                                  NULL);
13302                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13303                                                &bytes);
13304
13305                 if (err)
13306                         return rte_flow_error_set(error, -err,
13307                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13308                                         NULL, "cannot read counters");
13309                 qc->hits_set = 1;
13310                 qc->bytes_set = 1;
13311                 qc->hits = pkts - cnt->hits;
13312                 qc->bytes = bytes - cnt->bytes;
13313                 if (qc->reset) {
13314                         cnt->hits = pkts;
13315                         cnt->bytes = bytes;
13316                 }
13317                 return 0;
13318         }
13319         return rte_flow_error_set(error, EINVAL,
13320                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13321                                   NULL,
13322                                   "counters are not available");
13323 }
13324
13325 /**
13326  * Query a flow rule AGE action for aging information.
13327  *
13328  * @param[in] dev
13329  *   Pointer to Ethernet device.
13330  * @param[in] flow
13331  *   Pointer to the sub flow.
13332  * @param[out] data
13333  *   data retrieved by the query.
13334  * @param[out] error
13335  *   Perform verbose error reporting if not NULL.
13336  *
13337  * @return
13338  *   0 on success, a negative errno value otherwise and rte_errno is set.
13339  */
13340 static int
13341 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13342                   void *data, struct rte_flow_error *error)
13343 {
13344         struct rte_flow_query_age *resp = data;
13345         struct mlx5_age_param *age_param;
13346
13347         if (flow->age) {
13348                 struct mlx5_aso_age_action *act =
13349                                      flow_aso_age_get_by_idx(dev, flow->age);
13350
13351                 age_param = &act->age_params;
13352         } else if (flow->counter) {
13353                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13354
13355                 if (!age_param || !age_param->timeout)
13356                         return rte_flow_error_set
13357                                         (error, EINVAL,
13358                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13359                                          NULL, "cannot read age data");
13360         } else {
13361                 return rte_flow_error_set(error, EINVAL,
13362                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13363                                           NULL, "age data not available");
13364         }
13365         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13366                                      AGE_TMOUT ? 1 : 0;
13367         resp->sec_since_last_hit_valid = !resp->aged;
13368         if (resp->sec_since_last_hit_valid)
13369                 resp->sec_since_last_hit = __atomic_load_n
13370                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13371         return 0;
13372 }
13373
13374 /**
13375  * Query a flow.
13376  *
13377  * @see rte_flow_query()
13378  * @see rte_flow_ops
13379  */
13380 static int
13381 flow_dv_query(struct rte_eth_dev *dev,
13382               struct rte_flow *flow __rte_unused,
13383               const struct rte_flow_action *actions __rte_unused,
13384               void *data __rte_unused,
13385               struct rte_flow_error *error __rte_unused)
13386 {
13387         int ret = -EINVAL;
13388
13389         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13390                 switch (actions->type) {
13391                 case RTE_FLOW_ACTION_TYPE_VOID:
13392                         break;
13393                 case RTE_FLOW_ACTION_TYPE_COUNT:
13394                         ret = flow_dv_query_count(dev, flow, data, error);
13395                         break;
13396                 case RTE_FLOW_ACTION_TYPE_AGE:
13397                         ret = flow_dv_query_age(dev, flow, data, error);
13398                         break;
13399                 default:
13400                         return rte_flow_error_set(error, ENOTSUP,
13401                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13402                                                   actions,
13403                                                   "action not supported");
13404                 }
13405         }
13406         return ret;
13407 }
13408
13409 /**
13410  * Destroy the meter table set.
13411  * Lock free, (mutex should be acquired by caller).
13412  *
13413  * @param[in] dev
13414  *   Pointer to Ethernet device.
13415  * @param[in] tbl
13416  *   Pointer to the meter table set.
13417  *
13418  * @return
13419  *   Always 0.
13420  */
13421 static int
13422 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13423                         struct mlx5_meter_domains_infos *tbl)
13424 {
13425         struct mlx5_priv *priv = dev->data->dev_private;
13426         struct mlx5_meter_domains_infos *mtd =
13427                                 (struct mlx5_meter_domains_infos *)tbl;
13428
13429         if (!mtd || !priv->config.dv_flow_en)
13430                 return 0;
13431         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13432                 claim_zero(mlx5_flow_os_destroy_flow
13433                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13434         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13435                 claim_zero(mlx5_flow_os_destroy_flow
13436                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13437         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13438                 claim_zero(mlx5_flow_os_destroy_flow
13439                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13440         if (mtd->egress.color_matcher)
13441                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13442                            (mtd->egress.color_matcher));
13443         if (mtd->egress.any_matcher)
13444                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13445                            (mtd->egress.any_matcher));
13446         if (mtd->egress.tbl)
13447                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13448         if (mtd->egress.sfx_tbl)
13449                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13450         if (mtd->ingress.color_matcher)
13451                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13452                            (mtd->ingress.color_matcher));
13453         if (mtd->ingress.any_matcher)
13454                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13455                            (mtd->ingress.any_matcher));
13456         if (mtd->ingress.tbl)
13457                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13458         if (mtd->ingress.sfx_tbl)
13459                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13460                                              mtd->ingress.sfx_tbl);
13461         if (mtd->transfer.color_matcher)
13462                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13463                            (mtd->transfer.color_matcher));
13464         if (mtd->transfer.any_matcher)
13465                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13466                            (mtd->transfer.any_matcher));
13467         if (mtd->transfer.tbl)
13468                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13469         if (mtd->transfer.sfx_tbl)
13470                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13471                                              mtd->transfer.sfx_tbl);
13472         if (mtd->drop_actn)
13473                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13474         mlx5_free(mtd);
13475         return 0;
13476 }
13477
13478 /* Number of meter flow actions, count and jump or count and drop. */
13479 #define METER_ACTIONS 2
13480
13481 /**
13482  * Create specify domain meter table and suffix table.
13483  *
13484  * @param[in] dev
13485  *   Pointer to Ethernet device.
13486  * @param[in,out] mtb
13487  *   Pointer to DV meter table set.
13488  * @param[in] egress
13489  *   Table attribute.
13490  * @param[in] transfer
13491  *   Table attribute.
13492  * @param[in] color_reg_c_idx
13493  *   Reg C index for color match.
13494  *
13495  * @return
13496  *   0 on success, -1 otherwise and rte_errno is set.
13497  */
13498 static int
13499 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13500                            struct mlx5_meter_domains_infos *mtb,
13501                            uint8_t egress, uint8_t transfer,
13502                            uint32_t color_reg_c_idx)
13503 {
13504         struct mlx5_priv *priv = dev->data->dev_private;
13505         struct mlx5_dev_ctx_shared *sh = priv->sh;
13506         struct mlx5_flow_dv_match_params mask = {
13507                 .size = sizeof(mask.buf),
13508         };
13509         struct mlx5_flow_dv_match_params value = {
13510                 .size = sizeof(value.buf),
13511         };
13512         struct mlx5dv_flow_matcher_attr dv_attr = {
13513                 .type = IBV_FLOW_ATTR_NORMAL,
13514                 .priority = 0,
13515                 .match_criteria_enable = 0,
13516                 .match_mask = (void *)&mask,
13517         };
13518         void *actions[METER_ACTIONS];
13519         struct mlx5_meter_domain_info *dtb;
13520         struct rte_flow_error error;
13521         int i = 0;
13522         int ret;
13523
13524         if (transfer)
13525                 dtb = &mtb->transfer;
13526         else if (egress)
13527                 dtb = &mtb->egress;
13528         else
13529                 dtb = &mtb->ingress;
13530         /* Create the meter table with METER level. */
13531         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13532                                             egress, transfer, false, NULL, 0,
13533                                             0, &error);
13534         if (!dtb->tbl) {
13535                 DRV_LOG(ERR, "Failed to create meter policer table.");
13536                 return -1;
13537         }
13538         /* Create the meter suffix table with SUFFIX level. */
13539         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13540                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13541                                             egress, transfer, false, NULL, 0,
13542                                             0, &error);
13543         if (!dtb->sfx_tbl) {
13544                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13545                 return -1;
13546         }
13547         /* Create matchers, Any and Color. */
13548         dv_attr.priority = 3;
13549         dv_attr.match_criteria_enable = 0;
13550         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13551                                                &dtb->any_matcher);
13552         if (ret) {
13553                 DRV_LOG(ERR, "Failed to create meter"
13554                              " policer default matcher.");
13555                 goto error_exit;
13556         }
13557         dv_attr.priority = 0;
13558         dv_attr.match_criteria_enable =
13559                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13560         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13561                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13562         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13563                                                &dtb->color_matcher);
13564         if (ret) {
13565                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13566                 goto error_exit;
13567         }
13568         if (mtb->count_actns[RTE_MTR_DROPPED])
13569                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13570         actions[i++] = mtb->drop_actn;
13571         /* Default rule: lowest priority, match any, actions: drop. */
13572         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13573                                        actions,
13574                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13575         if (ret) {
13576                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13577                 goto error_exit;
13578         }
13579         return 0;
13580 error_exit:
13581         return -1;
13582 }
13583
13584 /**
13585  * Create the needed meter and suffix tables.
13586  * Lock free, (mutex should be acquired by caller).
13587  *
13588  * @param[in] dev
13589  *   Pointer to Ethernet device.
13590  * @param[in] fm
13591  *   Pointer to the flow meter.
13592  *
13593  * @return
13594  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13595  */
13596 static struct mlx5_meter_domains_infos *
13597 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13598                        const struct mlx5_flow_meter *fm)
13599 {
13600         struct mlx5_priv *priv = dev->data->dev_private;
13601         struct mlx5_meter_domains_infos *mtb;
13602         int ret;
13603         int i;
13604
13605         if (!priv->mtr_en) {
13606                 rte_errno = ENOTSUP;
13607                 return NULL;
13608         }
13609         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13610         if (!mtb) {
13611                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13612                 return NULL;
13613         }
13614         /* Create meter count actions */
13615         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13616                 struct mlx5_flow_counter *cnt;
13617                 if (!fm->policer_stats.cnt[i])
13618                         continue;
13619                 cnt = flow_dv_counter_get_by_idx(dev,
13620                       fm->policer_stats.cnt[i], NULL);
13621                 mtb->count_actns[i] = cnt->action;
13622         }
13623         /* Create drop action. */
13624         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13625         if (ret) {
13626                 DRV_LOG(ERR, "Failed to create drop action.");
13627                 goto error_exit;
13628         }
13629         /* Egress meter table. */
13630         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13631         if (ret) {
13632                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13633                 goto error_exit;
13634         }
13635         /* Ingress meter table. */
13636         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13637         if (ret) {
13638                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13639                 goto error_exit;
13640         }
13641         /* FDB meter table. */
13642         if (priv->config.dv_esw_en) {
13643                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13644                                                  priv->mtr_color_reg);
13645                 if (ret) {
13646                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13647                         goto error_exit;
13648                 }
13649         }
13650         return mtb;
13651 error_exit:
13652         flow_dv_destroy_mtr_tbl(dev, mtb);
13653         return NULL;
13654 }
13655
13656 /**
13657  * Destroy domain policer rule.
13658  *
13659  * @param[in] dt
13660  *   Pointer to domain table.
13661  */
13662 static void
13663 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13664 {
13665         int i;
13666
13667         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13668                 if (dt->policer_rules[i]) {
13669                         claim_zero(mlx5_flow_os_destroy_flow
13670                                    (dt->policer_rules[i]));
13671                         dt->policer_rules[i] = NULL;
13672                 }
13673         }
13674         if (dt->jump_actn) {
13675                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13676                 dt->jump_actn = NULL;
13677         }
13678 }
13679
13680 /**
13681  * Destroy policer rules.
13682  *
13683  * @param[in] dev
13684  *   Pointer to Ethernet device.
13685  * @param[in] fm
13686  *   Pointer to flow meter structure.
13687  * @param[in] attr
13688  *   Pointer to flow attributes.
13689  *
13690  * @return
13691  *   Always 0.
13692  */
13693 static int
13694 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13695                               const struct mlx5_flow_meter *fm,
13696                               const struct rte_flow_attr *attr)
13697 {
13698         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13699
13700         if (!mtb)
13701                 return 0;
13702         if (attr->egress)
13703                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13704         if (attr->ingress)
13705                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13706         if (attr->transfer)
13707                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13708         return 0;
13709 }
13710
13711 /**
13712  * Create specify domain meter policer rule.
13713  *
13714  * @param[in] fm
13715  *   Pointer to flow meter structure.
13716  * @param[in] mtb
13717  *   Pointer to DV meter table set.
13718  * @param[in] mtr_reg_c
13719  *   Color match REG_C.
13720  *
13721  * @return
13722  *   0 on success, -1 otherwise.
13723  */
13724 static int
13725 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13726                                     struct mlx5_meter_domain_info *dtb,
13727                                     uint8_t mtr_reg_c)
13728 {
13729         struct mlx5_flow_dv_match_params matcher = {
13730                 .size = sizeof(matcher.buf),
13731         };
13732         struct mlx5_flow_dv_match_params value = {
13733                 .size = sizeof(value.buf),
13734         };
13735         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13736         void *actions[METER_ACTIONS];
13737         int i;
13738         int ret = 0;
13739
13740         /* Create jump action. */
13741         if (!dtb->jump_actn)
13742                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13743                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13744         if (ret) {
13745                 DRV_LOG(ERR, "Failed to create policer jump action.");
13746                 goto error;
13747         }
13748         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13749                 int j = 0;
13750
13751                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13752                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13753                 if (mtb->count_actns[i])
13754                         actions[j++] = mtb->count_actns[i];
13755                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13756                         actions[j++] = mtb->drop_actn;
13757                 else
13758                         actions[j++] = dtb->jump_actn;
13759                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13760                                                (void *)&value, j, actions,
13761                                                &dtb->policer_rules[i]);
13762                 if (ret) {
13763                         DRV_LOG(ERR, "Failed to create policer rule.");
13764                         goto error;
13765                 }
13766         }
13767         return 0;
13768 error:
13769         rte_errno = errno;
13770         return -1;
13771 }
13772
13773 /**
13774  * Create policer rules.
13775  *
13776  * @param[in] dev
13777  *   Pointer to Ethernet device.
13778  * @param[in] fm
13779  *   Pointer to flow meter structure.
13780  * @param[in] attr
13781  *   Pointer to flow attributes.
13782  *
13783  * @return
13784  *   0 on success, -1 otherwise.
13785  */
13786 static int
13787 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13788                              struct mlx5_flow_meter *fm,
13789                              const struct rte_flow_attr *attr)
13790 {
13791         struct mlx5_priv *priv = dev->data->dev_private;
13792         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13793         int ret;
13794
13795         if (attr->egress) {
13796                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13797                                                 priv->mtr_color_reg);
13798                 if (ret) {
13799                         DRV_LOG(ERR, "Failed to create egress policer.");
13800                         goto error;
13801                 }
13802         }
13803         if (attr->ingress) {
13804                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13805                                                 priv->mtr_color_reg);
13806                 if (ret) {
13807                         DRV_LOG(ERR, "Failed to create ingress policer.");
13808                         goto error;
13809                 }
13810         }
13811         if (attr->transfer) {
13812                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13813                                                 priv->mtr_color_reg);
13814                 if (ret) {
13815                         DRV_LOG(ERR, "Failed to create transfer policer.");
13816                         goto error;
13817                 }
13818         }
13819         return 0;
13820 error:
13821         flow_dv_destroy_policer_rules(dev, fm, attr);
13822         return -1;
13823 }
13824
13825 /**
13826  * Validate the batch counter support in root table.
13827  *
13828  * Create a simple flow with invalid counter and drop action on root table to
13829  * validate if batch counter with offset on root table is supported or not.
13830  *
13831  * @param[in] dev
13832  *   Pointer to rte_eth_dev structure.
13833  *
13834  * @return
13835  *   0 on success, a negative errno value otherwise and rte_errno is set.
13836  */
13837 int
13838 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13839 {
13840         struct mlx5_priv *priv = dev->data->dev_private;
13841         struct mlx5_dev_ctx_shared *sh = priv->sh;
13842         struct mlx5_flow_dv_match_params mask = {
13843                 .size = sizeof(mask.buf),
13844         };
13845         struct mlx5_flow_dv_match_params value = {
13846                 .size = sizeof(value.buf),
13847         };
13848         struct mlx5dv_flow_matcher_attr dv_attr = {
13849                 .type = IBV_FLOW_ATTR_NORMAL,
13850                 .priority = 0,
13851                 .match_criteria_enable = 0,
13852                 .match_mask = (void *)&mask,
13853         };
13854         void *actions[2] = { 0 };
13855         struct mlx5_flow_tbl_resource *tbl = NULL;
13856         struct mlx5_devx_obj *dcs = NULL;
13857         void *matcher = NULL;
13858         void *flow = NULL;
13859         int ret = -1;
13860
13861         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13862         if (!tbl)
13863                 goto err;
13864         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13865         if (!dcs)
13866                 goto err;
13867         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13868                                                     &actions[0]);
13869         if (ret)
13870                 goto err;
13871         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13872                                           priv->drop_queue.hrxq->action;
13873         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13874         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13875                                                &matcher);
13876         if (ret)
13877                 goto err;
13878         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13879                                        actions, &flow);
13880 err:
13881         /*
13882          * If batch counter with offset is not supported, the driver will not
13883          * validate the invalid offset value, flow create should success.
13884          * In this case, it means batch counter is not supported in root table.
13885          *
13886          * Otherwise, if flow create is failed, counter offset is supported.
13887          */
13888         if (flow) {
13889                 DRV_LOG(INFO, "Batch counter is not supported in root "
13890                               "table. Switch to fallback mode.");
13891                 rte_errno = ENOTSUP;
13892                 ret = -rte_errno;
13893                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13894         } else {
13895                 /* Check matcher to make sure validate fail at flow create. */
13896                 if (!matcher || (matcher && errno != EINVAL))
13897                         DRV_LOG(ERR, "Unexpected error in counter offset "
13898                                      "support detection");
13899                 ret = 0;
13900         }
13901         if (actions[0])
13902                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13903         if (matcher)
13904                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13905         if (tbl)
13906                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13907         if (dcs)
13908                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13909         return ret;
13910 }
13911
13912 /**
13913  * Query a devx counter.
13914  *
13915  * @param[in] dev
13916  *   Pointer to the Ethernet device structure.
13917  * @param[in] cnt
13918  *   Index to the flow counter.
13919  * @param[in] clear
13920  *   Set to clear the counter statistics.
13921  * @param[out] pkts
13922  *   The statistics value of packets.
13923  * @param[out] bytes
13924  *   The statistics value of bytes.
13925  *
13926  * @return
13927  *   0 on success, otherwise return -1.
13928  */
13929 static int
13930 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13931                       uint64_t *pkts, uint64_t *bytes)
13932 {
13933         struct mlx5_priv *priv = dev->data->dev_private;
13934         struct mlx5_flow_counter *cnt;
13935         uint64_t inn_pkts, inn_bytes;
13936         int ret;
13937
13938         if (!priv->config.devx)
13939                 return -1;
13940
13941         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13942         if (ret)
13943                 return -1;
13944         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13945         *pkts = inn_pkts - cnt->hits;
13946         *bytes = inn_bytes - cnt->bytes;
13947         if (clear) {
13948                 cnt->hits = inn_pkts;
13949                 cnt->bytes = inn_bytes;
13950         }
13951         return 0;
13952 }
13953
13954 /**
13955  * Get aged-out flows.
13956  *
13957  * @param[in] dev
13958  *   Pointer to the Ethernet device structure.
13959  * @param[in] context
13960  *   The address of an array of pointers to the aged-out flows contexts.
13961  * @param[in] nb_contexts
13962  *   The length of context array pointers.
13963  * @param[out] error
13964  *   Perform verbose error reporting if not NULL. Initialized in case of
13965  *   error only.
13966  *
13967  * @return
13968  *   how many contexts get in success, otherwise negative errno value.
13969  *   if nb_contexts is 0, return the amount of all aged contexts.
13970  *   if nb_contexts is not 0 , return the amount of aged flows reported
13971  *   in the context array.
13972  * @note: only stub for now
13973  */
13974 static int
13975 flow_get_aged_flows(struct rte_eth_dev *dev,
13976                     void **context,
13977                     uint32_t nb_contexts,
13978                     struct rte_flow_error *error)
13979 {
13980         struct mlx5_priv *priv = dev->data->dev_private;
13981         struct mlx5_age_info *age_info;
13982         struct mlx5_age_param *age_param;
13983         struct mlx5_flow_counter *counter;
13984         struct mlx5_aso_age_action *act;
13985         int nb_flows = 0;
13986
13987         if (nb_contexts && !context)
13988                 return rte_flow_error_set(error, EINVAL,
13989                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13990                                           NULL, "empty context");
13991         age_info = GET_PORT_AGE_INFO(priv);
13992         rte_spinlock_lock(&age_info->aged_sl);
13993         LIST_FOREACH(act, &age_info->aged_aso, next) {
13994                 nb_flows++;
13995                 if (nb_contexts) {
13996                         context[nb_flows - 1] =
13997                                                 act->age_params.context;
13998                         if (!(--nb_contexts))
13999                                 break;
14000                 }
14001         }
14002         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
14003                 nb_flows++;
14004                 if (nb_contexts) {
14005                         age_param = MLX5_CNT_TO_AGE(counter);
14006                         context[nb_flows - 1] = age_param->context;
14007                         if (!(--nb_contexts))
14008                                 break;
14009                 }
14010         }
14011         rte_spinlock_unlock(&age_info->aged_sl);
14012         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14013         return nb_flows;
14014 }
14015
14016 /*
14017  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14018  */
14019 static uint32_t
14020 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14021 {
14022         return flow_dv_counter_alloc(dev, 0);
14023 }
14024
14025 /**
14026  * Validate shared action.
14027  * Dispatcher for action type specific validation.
14028  *
14029  * @param[in] dev
14030  *   Pointer to the Ethernet device structure.
14031  * @param[in] conf
14032  *   Shared action configuration.
14033  * @param[in] action
14034  *   The shared action object to validate.
14035  * @param[out] error
14036  *   Perform verbose error reporting if not NULL. Initialized in case of
14037  *   error only.
14038  *
14039  * @return
14040  *   0 on success, otherwise negative errno value.
14041  */
14042 static int
14043 flow_dv_action_validate(struct rte_eth_dev *dev,
14044                         const struct rte_flow_shared_action_conf *conf,
14045                         const struct rte_flow_action *action,
14046                         struct rte_flow_error *err)
14047 {
14048         struct mlx5_priv *priv = dev->data->dev_private;
14049
14050         RTE_SET_USED(conf);
14051         switch (action->type) {
14052         case RTE_FLOW_ACTION_TYPE_RSS:
14053                 /*
14054                  * priv->obj_ops is set according to driver capabilities.
14055                  * When DevX capabilities are
14056                  * sufficient, it is set to devx_obj_ops.
14057                  * Otherwise, it is set to ibv_obj_ops.
14058                  * ibv_obj_ops doesn't support ind_table_modify operation.
14059                  * In this case the shared RSS action can't be used.
14060                  */
14061                 if (priv->obj_ops.ind_table_modify == NULL)
14062                         return rte_flow_error_set
14063                                         (err, ENOTSUP,
14064                                          RTE_FLOW_ERROR_TYPE_ACTION,
14065                                          NULL,
14066                                          "shared RSS action not supported");
14067                 return mlx5_validate_action_rss(dev, action, err);
14068         case RTE_FLOW_ACTION_TYPE_AGE:
14069                 if (!priv->sh->aso_age_mng)
14070                         return rte_flow_error_set(err, ENOTSUP,
14071                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14072                                                 NULL,
14073                                              "shared age action not supported");
14074                 return flow_dv_validate_action_age(0, action, dev, err);
14075         default:
14076                 return rte_flow_error_set(err, ENOTSUP,
14077                                           RTE_FLOW_ERROR_TYPE_ACTION,
14078                                           NULL,
14079                                           "action type not supported");
14080         }
14081 }
14082
14083 static int
14084 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14085 {
14086         struct mlx5_priv *priv = dev->data->dev_private;
14087         int ret = 0;
14088
14089         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14090                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14091                                                 flags);
14092                 if (ret != 0)
14093                         return ret;
14094         }
14095         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14096                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14097                 if (ret != 0)
14098                         return ret;
14099         }
14100         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14101                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14102                 if (ret != 0)
14103                         return ret;
14104         }
14105         return 0;
14106 }
14107
14108 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14109         .validate = flow_dv_validate,
14110         .prepare = flow_dv_prepare,
14111         .translate = flow_dv_translate,
14112         .apply = flow_dv_apply,
14113         .remove = flow_dv_remove,
14114         .destroy = flow_dv_destroy,
14115         .query = flow_dv_query,
14116         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14117         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14118         .create_policer_rules = flow_dv_create_policer_rules,
14119         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14120         .counter_alloc = flow_dv_counter_allocate,
14121         .counter_free = flow_dv_counter_free,
14122         .counter_query = flow_dv_counter_query,
14123         .get_aged_flows = flow_get_aged_flows,
14124         .action_validate = flow_dv_action_validate,
14125         .action_create = flow_dv_action_create,
14126         .action_destroy = flow_dv_action_destroy,
14127         .action_update = flow_dv_action_update,
14128         .action_query = flow_dv_action_query,
14129         .sync_domain = flow_dv_sync_domain,
14130 };
14131
14132 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14133