1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
58 sizeof(struct rte_flow_item_ipv4))
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 * Initialize flow attributes structure according to flow items' types.
81 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
82 * mode. For tunnel mode, the items to be modified are the outermost ones.
85 * Pointer to item specification.
87 * Pointer to flow attributes structure.
90 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
92 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
94 case RTE_FLOW_ITEM_TYPE_IPV4:
98 case RTE_FLOW_ITEM_TYPE_IPV6:
102 case RTE_FLOW_ITEM_TYPE_UDP:
106 case RTE_FLOW_ITEM_TYPE_TCP:
118 * Convert rte_mtr_color to mlx5 color.
127 rte_col_2_mlx5_col(enum rte_color rcol)
130 case RTE_COLOR_GREEN:
131 return MLX5_FLOW_COLOR_GREEN;
132 case RTE_COLOR_YELLOW:
133 return MLX5_FLOW_COLOR_YELLOW;
135 return MLX5_FLOW_COLOR_RED;
139 return MLX5_FLOW_COLOR_UNDEFINED;
142 struct field_modify_info {
143 uint32_t size; /* Size of field in protocol header, in bytes. */
144 uint32_t offset; /* Offset of field in protocol header, in bytes. */
145 enum mlx5_modification_field id;
148 struct field_modify_info modify_eth[] = {
149 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
150 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
151 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
152 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
156 struct field_modify_info modify_vlan_out_first_vid[] = {
157 /* Size in bits !!! */
158 {12, 0, MLX5_MODI_OUT_FIRST_VID},
162 struct field_modify_info modify_ipv4[] = {
163 {1, 1, MLX5_MODI_OUT_IP_DSCP},
164 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
165 {4, 12, MLX5_MODI_OUT_SIPV4},
166 {4, 16, MLX5_MODI_OUT_DIPV4},
170 struct field_modify_info modify_ipv6[] = {
171 {1, 0, MLX5_MODI_OUT_IP_DSCP},
172 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
173 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
174 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
175 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
176 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
177 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
178 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
179 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
180 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
184 struct field_modify_info modify_udp[] = {
185 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
186 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
190 struct field_modify_info modify_tcp[] = {
191 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
192 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
193 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
194 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
199 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
200 uint8_t next_protocol, uint64_t *item_flags,
203 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
204 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
205 if (next_protocol == IPPROTO_IPIP) {
206 *item_flags |= MLX5_FLOW_LAYER_IPIP;
209 if (next_protocol == IPPROTO_IPV6) {
210 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
216 * Acquire the synchronizing object to protect multithreaded access
217 * to shared dv context. Lock occurs only if context is actually
218 * shared, i.e. we have multiport IB device and representors are
222 * Pointer to the rte_eth_dev structure.
225 flow_dv_shared_lock(struct rte_eth_dev *dev)
227 struct mlx5_priv *priv = dev->data->dev_private;
228 struct mlx5_ibv_shared *sh = priv->sh;
230 if (sh->dv_refcnt > 1) {
233 ret = pthread_mutex_lock(&sh->dv_mutex);
240 flow_dv_shared_unlock(struct rte_eth_dev *dev)
242 struct mlx5_priv *priv = dev->data->dev_private;
243 struct mlx5_ibv_shared *sh = priv->sh;
245 if (sh->dv_refcnt > 1) {
248 ret = pthread_mutex_unlock(&sh->dv_mutex);
254 /* Update VLAN's VID/PCP based on input rte_flow_action.
257 * Pointer to struct rte_flow_action.
259 * Pointer to struct rte_vlan_hdr.
262 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
263 struct rte_vlan_hdr *vlan)
266 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
268 ((const struct rte_flow_action_of_set_vlan_pcp *)
269 action->conf)->vlan_pcp;
270 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
271 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
272 vlan->vlan_tci |= vlan_tci;
273 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
274 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
275 vlan->vlan_tci |= rte_be_to_cpu_16
276 (((const struct rte_flow_action_of_set_vlan_vid *)
277 action->conf)->vlan_vid);
282 * Fetch 1, 2, 3 or 4 byte field from the byte array
283 * and return as unsigned integer in host-endian format.
286 * Pointer to data array.
288 * Size of field to extract.
291 * converted field in host endian format.
293 static inline uint32_t
294 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
303 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
306 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
307 ret = (ret << 8) | *(data + sizeof(uint16_t));
310 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
321 * Convert modify-header action to DV specification.
323 * Data length of each action is determined by provided field description
324 * and the item mask. Data bit offset and width of each action is determined
325 * by provided item mask.
328 * Pointer to item specification.
330 * Pointer to field modification information.
331 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
332 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
333 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
335 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
336 * Negative offset value sets the same offset as source offset.
337 * size field is ignored, value is taken from source field.
338 * @param[in,out] resource
339 * Pointer to the modify-header resource.
341 * Type of modification.
343 * Pointer to the error structure.
346 * 0 on success, a negative errno value otherwise and rte_errno is set.
349 flow_dv_convert_modify_action(struct rte_flow_item *item,
350 struct field_modify_info *field,
351 struct field_modify_info *dcopy,
352 struct mlx5_flow_dv_modify_hdr_resource *resource,
353 uint32_t type, struct rte_flow_error *error)
355 uint32_t i = resource->actions_num;
356 struct mlx5_modification_cmd *actions = resource->actions;
359 * The item and mask are provided in big-endian format.
360 * The fields should be presented as in big-endian format either.
361 * Mask must be always present, it defines the actual field width.
363 MLX5_ASSERT(item->mask);
364 MLX5_ASSERT(field->size);
371 if (i >= MLX5_MAX_MODIFY_NUM)
372 return rte_flow_error_set(error, EINVAL,
373 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
374 "too many items to modify");
375 /* Fetch variable byte size mask from the array. */
376 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
377 field->offset, field->size);
382 /* Deduce actual data width in bits from mask value. */
383 off_b = rte_bsf32(mask);
384 size_b = sizeof(uint32_t) * CHAR_BIT -
385 off_b - __builtin_clz(mask);
387 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
388 actions[i] = (struct mlx5_modification_cmd) {
394 /* Convert entire record to expected big-endian format. */
395 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
396 if (type == MLX5_MODIFICATION_TYPE_COPY) {
398 actions[i].dst_field = dcopy->id;
399 actions[i].dst_offset =
400 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
401 /* Convert entire record to big-endian format. */
402 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
404 MLX5_ASSERT(item->spec);
405 data = flow_dv_fetch_field((const uint8_t *)item->spec +
406 field->offset, field->size);
407 /* Shift out the trailing masked bits from data. */
408 data = (data & mask) >> off_b;
409 actions[i].data1 = rte_cpu_to_be_32(data);
413 } while (field->size);
414 if (resource->actions_num == i)
415 return rte_flow_error_set(error, EINVAL,
416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
417 "invalid modification flow item");
418 resource->actions_num = i;
423 * Convert modify-header set IPv4 address action to DV specification.
425 * @param[in,out] resource
426 * Pointer to the modify-header resource.
428 * Pointer to action specification.
430 * Pointer to the error structure.
433 * 0 on success, a negative errno value otherwise and rte_errno is set.
436 flow_dv_convert_action_modify_ipv4
437 (struct mlx5_flow_dv_modify_hdr_resource *resource,
438 const struct rte_flow_action *action,
439 struct rte_flow_error *error)
441 const struct rte_flow_action_set_ipv4 *conf =
442 (const struct rte_flow_action_set_ipv4 *)(action->conf);
443 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
444 struct rte_flow_item_ipv4 ipv4;
445 struct rte_flow_item_ipv4 ipv4_mask;
447 memset(&ipv4, 0, sizeof(ipv4));
448 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
449 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
450 ipv4.hdr.src_addr = conf->ipv4_addr;
451 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
453 ipv4.hdr.dst_addr = conf->ipv4_addr;
454 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
457 item.mask = &ipv4_mask;
458 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
459 MLX5_MODIFICATION_TYPE_SET, error);
463 * Convert modify-header set IPv6 address action to DV specification.
465 * @param[in,out] resource
466 * Pointer to the modify-header resource.
468 * Pointer to action specification.
470 * Pointer to the error structure.
473 * 0 on success, a negative errno value otherwise and rte_errno is set.
476 flow_dv_convert_action_modify_ipv6
477 (struct mlx5_flow_dv_modify_hdr_resource *resource,
478 const struct rte_flow_action *action,
479 struct rte_flow_error *error)
481 const struct rte_flow_action_set_ipv6 *conf =
482 (const struct rte_flow_action_set_ipv6 *)(action->conf);
483 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
484 struct rte_flow_item_ipv6 ipv6;
485 struct rte_flow_item_ipv6 ipv6_mask;
487 memset(&ipv6, 0, sizeof(ipv6));
488 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
489 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
490 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
491 sizeof(ipv6.hdr.src_addr));
492 memcpy(&ipv6_mask.hdr.src_addr,
493 &rte_flow_item_ipv6_mask.hdr.src_addr,
494 sizeof(ipv6.hdr.src_addr));
496 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
497 sizeof(ipv6.hdr.dst_addr));
498 memcpy(&ipv6_mask.hdr.dst_addr,
499 &rte_flow_item_ipv6_mask.hdr.dst_addr,
500 sizeof(ipv6.hdr.dst_addr));
503 item.mask = &ipv6_mask;
504 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
505 MLX5_MODIFICATION_TYPE_SET, error);
509 * Convert modify-header set MAC address action to DV specification.
511 * @param[in,out] resource
512 * Pointer to the modify-header resource.
514 * Pointer to action specification.
516 * Pointer to the error structure.
519 * 0 on success, a negative errno value otherwise and rte_errno is set.
522 flow_dv_convert_action_modify_mac
523 (struct mlx5_flow_dv_modify_hdr_resource *resource,
524 const struct rte_flow_action *action,
525 struct rte_flow_error *error)
527 const struct rte_flow_action_set_mac *conf =
528 (const struct rte_flow_action_set_mac *)(action->conf);
529 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
530 struct rte_flow_item_eth eth;
531 struct rte_flow_item_eth eth_mask;
533 memset(ð, 0, sizeof(eth));
534 memset(ð_mask, 0, sizeof(eth_mask));
535 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
536 memcpy(ð.src.addr_bytes, &conf->mac_addr,
537 sizeof(eth.src.addr_bytes));
538 memcpy(ð_mask.src.addr_bytes,
539 &rte_flow_item_eth_mask.src.addr_bytes,
540 sizeof(eth_mask.src.addr_bytes));
542 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
543 sizeof(eth.dst.addr_bytes));
544 memcpy(ð_mask.dst.addr_bytes,
545 &rte_flow_item_eth_mask.dst.addr_bytes,
546 sizeof(eth_mask.dst.addr_bytes));
549 item.mask = ð_mask;
550 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
551 MLX5_MODIFICATION_TYPE_SET, error);
555 * Convert modify-header set VLAN VID action to DV specification.
557 * @param[in,out] resource
558 * Pointer to the modify-header resource.
560 * Pointer to action specification.
562 * Pointer to the error structure.
565 * 0 on success, a negative errno value otherwise and rte_errno is set.
568 flow_dv_convert_action_modify_vlan_vid
569 (struct mlx5_flow_dv_modify_hdr_resource *resource,
570 const struct rte_flow_action *action,
571 struct rte_flow_error *error)
573 const struct rte_flow_action_of_set_vlan_vid *conf =
574 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
575 int i = resource->actions_num;
576 struct mlx5_modification_cmd *actions = resource->actions;
577 struct field_modify_info *field = modify_vlan_out_first_vid;
579 if (i >= MLX5_MAX_MODIFY_NUM)
580 return rte_flow_error_set(error, EINVAL,
581 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
582 "too many items to modify");
583 actions[i] = (struct mlx5_modification_cmd) {
584 .action_type = MLX5_MODIFICATION_TYPE_SET,
586 .length = field->size,
587 .offset = field->offset,
589 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
590 actions[i].data1 = conf->vlan_vid;
591 actions[i].data1 = actions[i].data1 << 16;
592 resource->actions_num = ++i;
597 * Convert modify-header set TP action to DV specification.
599 * @param[in,out] resource
600 * Pointer to the modify-header resource.
602 * Pointer to action specification.
604 * Pointer to rte_flow_item objects list.
606 * Pointer to flow attributes structure.
608 * Pointer to the error structure.
611 * 0 on success, a negative errno value otherwise and rte_errno is set.
614 flow_dv_convert_action_modify_tp
615 (struct mlx5_flow_dv_modify_hdr_resource *resource,
616 const struct rte_flow_action *action,
617 const struct rte_flow_item *items,
618 union flow_dv_attr *attr,
619 struct rte_flow_error *error)
621 const struct rte_flow_action_set_tp *conf =
622 (const struct rte_flow_action_set_tp *)(action->conf);
623 struct rte_flow_item item;
624 struct rte_flow_item_udp udp;
625 struct rte_flow_item_udp udp_mask;
626 struct rte_flow_item_tcp tcp;
627 struct rte_flow_item_tcp tcp_mask;
628 struct field_modify_info *field;
631 flow_dv_attr_init(items, attr);
633 memset(&udp, 0, sizeof(udp));
634 memset(&udp_mask, 0, sizeof(udp_mask));
635 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
636 udp.hdr.src_port = conf->port;
637 udp_mask.hdr.src_port =
638 rte_flow_item_udp_mask.hdr.src_port;
640 udp.hdr.dst_port = conf->port;
641 udp_mask.hdr.dst_port =
642 rte_flow_item_udp_mask.hdr.dst_port;
644 item.type = RTE_FLOW_ITEM_TYPE_UDP;
646 item.mask = &udp_mask;
650 memset(&tcp, 0, sizeof(tcp));
651 memset(&tcp_mask, 0, sizeof(tcp_mask));
652 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
653 tcp.hdr.src_port = conf->port;
654 tcp_mask.hdr.src_port =
655 rte_flow_item_tcp_mask.hdr.src_port;
657 tcp.hdr.dst_port = conf->port;
658 tcp_mask.hdr.dst_port =
659 rte_flow_item_tcp_mask.hdr.dst_port;
661 item.type = RTE_FLOW_ITEM_TYPE_TCP;
663 item.mask = &tcp_mask;
666 return flow_dv_convert_modify_action(&item, field, NULL, resource,
667 MLX5_MODIFICATION_TYPE_SET, error);
671 * Convert modify-header set TTL action to DV specification.
673 * @param[in,out] resource
674 * Pointer to the modify-header resource.
676 * Pointer to action specification.
678 * Pointer to rte_flow_item objects list.
680 * Pointer to flow attributes structure.
682 * Pointer to the error structure.
685 * 0 on success, a negative errno value otherwise and rte_errno is set.
688 flow_dv_convert_action_modify_ttl
689 (struct mlx5_flow_dv_modify_hdr_resource *resource,
690 const struct rte_flow_action *action,
691 const struct rte_flow_item *items,
692 union flow_dv_attr *attr,
693 struct rte_flow_error *error)
695 const struct rte_flow_action_set_ttl *conf =
696 (const struct rte_flow_action_set_ttl *)(action->conf);
697 struct rte_flow_item item;
698 struct rte_flow_item_ipv4 ipv4;
699 struct rte_flow_item_ipv4 ipv4_mask;
700 struct rte_flow_item_ipv6 ipv6;
701 struct rte_flow_item_ipv6 ipv6_mask;
702 struct field_modify_info *field;
705 flow_dv_attr_init(items, attr);
707 memset(&ipv4, 0, sizeof(ipv4));
708 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
709 ipv4.hdr.time_to_live = conf->ttl_value;
710 ipv4_mask.hdr.time_to_live = 0xFF;
711 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
713 item.mask = &ipv4_mask;
717 memset(&ipv6, 0, sizeof(ipv6));
718 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
719 ipv6.hdr.hop_limits = conf->ttl_value;
720 ipv6_mask.hdr.hop_limits = 0xFF;
721 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
723 item.mask = &ipv6_mask;
726 return flow_dv_convert_modify_action(&item, field, NULL, resource,
727 MLX5_MODIFICATION_TYPE_SET, error);
731 * Convert modify-header decrement TTL action to DV specification.
733 * @param[in,out] resource
734 * Pointer to the modify-header resource.
736 * Pointer to action specification.
738 * Pointer to rte_flow_item objects list.
740 * Pointer to flow attributes structure.
742 * Pointer to the error structure.
745 * 0 on success, a negative errno value otherwise and rte_errno is set.
748 flow_dv_convert_action_modify_dec_ttl
749 (struct mlx5_flow_dv_modify_hdr_resource *resource,
750 const struct rte_flow_item *items,
751 union flow_dv_attr *attr,
752 struct rte_flow_error *error)
754 struct rte_flow_item item;
755 struct rte_flow_item_ipv4 ipv4;
756 struct rte_flow_item_ipv4 ipv4_mask;
757 struct rte_flow_item_ipv6 ipv6;
758 struct rte_flow_item_ipv6 ipv6_mask;
759 struct field_modify_info *field;
762 flow_dv_attr_init(items, attr);
764 memset(&ipv4, 0, sizeof(ipv4));
765 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
766 ipv4.hdr.time_to_live = 0xFF;
767 ipv4_mask.hdr.time_to_live = 0xFF;
768 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
770 item.mask = &ipv4_mask;
774 memset(&ipv6, 0, sizeof(ipv6));
775 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
776 ipv6.hdr.hop_limits = 0xFF;
777 ipv6_mask.hdr.hop_limits = 0xFF;
778 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
780 item.mask = &ipv6_mask;
783 return flow_dv_convert_modify_action(&item, field, NULL, resource,
784 MLX5_MODIFICATION_TYPE_ADD, error);
788 * Convert modify-header increment/decrement TCP Sequence number
789 * to DV specification.
791 * @param[in,out] resource
792 * Pointer to the modify-header resource.
794 * Pointer to action specification.
796 * Pointer to the error structure.
799 * 0 on success, a negative errno value otherwise and rte_errno is set.
802 flow_dv_convert_action_modify_tcp_seq
803 (struct mlx5_flow_dv_modify_hdr_resource *resource,
804 const struct rte_flow_action *action,
805 struct rte_flow_error *error)
807 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
808 uint64_t value = rte_be_to_cpu_32(*conf);
809 struct rte_flow_item item;
810 struct rte_flow_item_tcp tcp;
811 struct rte_flow_item_tcp tcp_mask;
813 memset(&tcp, 0, sizeof(tcp));
814 memset(&tcp_mask, 0, sizeof(tcp_mask));
815 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
817 * The HW has no decrement operation, only increment operation.
818 * To simulate decrement X from Y using increment operation
819 * we need to add UINT32_MAX X times to Y.
820 * Each adding of UINT32_MAX decrements Y by 1.
823 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
824 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
825 item.type = RTE_FLOW_ITEM_TYPE_TCP;
827 item.mask = &tcp_mask;
828 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
829 MLX5_MODIFICATION_TYPE_ADD, error);
833 * Convert modify-header increment/decrement TCP Acknowledgment number
834 * to DV specification.
836 * @param[in,out] resource
837 * Pointer to the modify-header resource.
839 * Pointer to action specification.
841 * Pointer to the error structure.
844 * 0 on success, a negative errno value otherwise and rte_errno is set.
847 flow_dv_convert_action_modify_tcp_ack
848 (struct mlx5_flow_dv_modify_hdr_resource *resource,
849 const struct rte_flow_action *action,
850 struct rte_flow_error *error)
852 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
853 uint64_t value = rte_be_to_cpu_32(*conf);
854 struct rte_flow_item item;
855 struct rte_flow_item_tcp tcp;
856 struct rte_flow_item_tcp tcp_mask;
858 memset(&tcp, 0, sizeof(tcp));
859 memset(&tcp_mask, 0, sizeof(tcp_mask));
860 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
862 * The HW has no decrement operation, only increment operation.
863 * To simulate decrement X from Y using increment operation
864 * we need to add UINT32_MAX X times to Y.
865 * Each adding of UINT32_MAX decrements Y by 1.
868 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
869 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
870 item.type = RTE_FLOW_ITEM_TYPE_TCP;
872 item.mask = &tcp_mask;
873 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
874 MLX5_MODIFICATION_TYPE_ADD, error);
877 static enum mlx5_modification_field reg_to_field[] = {
878 [REG_NONE] = MLX5_MODI_OUT_NONE,
879 [REG_A] = MLX5_MODI_META_DATA_REG_A,
880 [REG_B] = MLX5_MODI_META_DATA_REG_B,
881 [REG_C_0] = MLX5_MODI_META_REG_C_0,
882 [REG_C_1] = MLX5_MODI_META_REG_C_1,
883 [REG_C_2] = MLX5_MODI_META_REG_C_2,
884 [REG_C_3] = MLX5_MODI_META_REG_C_3,
885 [REG_C_4] = MLX5_MODI_META_REG_C_4,
886 [REG_C_5] = MLX5_MODI_META_REG_C_5,
887 [REG_C_6] = MLX5_MODI_META_REG_C_6,
888 [REG_C_7] = MLX5_MODI_META_REG_C_7,
892 * Convert register set to DV specification.
894 * @param[in,out] resource
895 * Pointer to the modify-header resource.
897 * Pointer to action specification.
899 * Pointer to the error structure.
902 * 0 on success, a negative errno value otherwise and rte_errno is set.
905 flow_dv_convert_action_set_reg
906 (struct mlx5_flow_dv_modify_hdr_resource *resource,
907 const struct rte_flow_action *action,
908 struct rte_flow_error *error)
910 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
911 struct mlx5_modification_cmd *actions = resource->actions;
912 uint32_t i = resource->actions_num;
914 if (i >= MLX5_MAX_MODIFY_NUM)
915 return rte_flow_error_set(error, EINVAL,
916 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
917 "too many items to modify");
918 MLX5_ASSERT(conf->id != REG_NONE);
919 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
920 actions[i] = (struct mlx5_modification_cmd) {
921 .action_type = MLX5_MODIFICATION_TYPE_SET,
922 .field = reg_to_field[conf->id],
924 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
925 actions[i].data1 = rte_cpu_to_be_32(conf->data);
927 resource->actions_num = i;
932 * Convert SET_TAG action to DV specification.
935 * Pointer to the rte_eth_dev structure.
936 * @param[in,out] resource
937 * Pointer to the modify-header resource.
939 * Pointer to action specification.
941 * Pointer to the error structure.
944 * 0 on success, a negative errno value otherwise and rte_errno is set.
947 flow_dv_convert_action_set_tag
948 (struct rte_eth_dev *dev,
949 struct mlx5_flow_dv_modify_hdr_resource *resource,
950 const struct rte_flow_action_set_tag *conf,
951 struct rte_flow_error *error)
953 rte_be32_t data = rte_cpu_to_be_32(conf->data);
954 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
955 struct rte_flow_item item = {
959 struct field_modify_info reg_c_x[] = {
962 enum mlx5_modification_field reg_type;
965 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
968 MLX5_ASSERT(ret != REG_NONE);
969 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
970 reg_type = reg_to_field[ret];
971 MLX5_ASSERT(reg_type > 0);
972 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
973 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
974 MLX5_MODIFICATION_TYPE_SET, error);
978 * Convert internal COPY_REG action to DV specification.
981 * Pointer to the rte_eth_dev structure.
983 * Pointer to the modify-header resource.
985 * Pointer to action specification.
987 * Pointer to the error structure.
990 * 0 on success, a negative errno value otherwise and rte_errno is set.
993 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
994 struct mlx5_flow_dv_modify_hdr_resource *res,
995 const struct rte_flow_action *action,
996 struct rte_flow_error *error)
998 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
999 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1000 struct rte_flow_item item = {
1004 struct field_modify_info reg_src[] = {
1005 {4, 0, reg_to_field[conf->src]},
1008 struct field_modify_info reg_dst = {
1010 .id = reg_to_field[conf->dst],
1012 /* Adjust reg_c[0] usage according to reported mask. */
1013 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1014 struct mlx5_priv *priv = dev->data->dev_private;
1015 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1017 MLX5_ASSERT(reg_c0);
1018 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1019 if (conf->dst == REG_C_0) {
1020 /* Copy to reg_c[0], within mask only. */
1021 reg_dst.offset = rte_bsf32(reg_c0);
1023 * Mask is ignoring the enianness, because
1024 * there is no conversion in datapath.
1026 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1027 /* Copy from destination lower bits to reg_c[0]. */
1028 mask = reg_c0 >> reg_dst.offset;
1030 /* Copy from destination upper bits to reg_c[0]. */
1031 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1032 rte_fls_u32(reg_c0));
1035 mask = rte_cpu_to_be_32(reg_c0);
1036 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1037 /* Copy from reg_c[0] to destination lower bits. */
1040 /* Copy from reg_c[0] to destination upper bits. */
1041 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1042 (rte_fls_u32(reg_c0) -
1047 return flow_dv_convert_modify_action(&item,
1048 reg_src, ®_dst, res,
1049 MLX5_MODIFICATION_TYPE_COPY,
1054 * Convert MARK action to DV specification. This routine is used
1055 * in extensive metadata only and requires metadata register to be
1056 * handled. In legacy mode hardware tag resource is engaged.
1059 * Pointer to the rte_eth_dev structure.
1061 * Pointer to MARK action specification.
1062 * @param[in,out] resource
1063 * Pointer to the modify-header resource.
1065 * Pointer to the error structure.
1068 * 0 on success, a negative errno value otherwise and rte_errno is set.
1071 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1072 const struct rte_flow_action_mark *conf,
1073 struct mlx5_flow_dv_modify_hdr_resource *resource,
1074 struct rte_flow_error *error)
1076 struct mlx5_priv *priv = dev->data->dev_private;
1077 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1078 priv->sh->dv_mark_mask);
1079 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1080 struct rte_flow_item item = {
1084 struct field_modify_info reg_c_x[] = {
1085 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1091 return rte_flow_error_set(error, EINVAL,
1092 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1093 NULL, "zero mark action mask");
1094 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1097 MLX5_ASSERT(reg > 0);
1098 if (reg == REG_C_0) {
1099 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1100 uint32_t shl_c0 = rte_bsf32(msk_c0);
1102 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1103 mask = rte_cpu_to_be_32(mask) & msk_c0;
1104 mask = rte_cpu_to_be_32(mask << shl_c0);
1106 reg_c_x[0].id = reg_to_field[reg];
1107 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1108 MLX5_MODIFICATION_TYPE_SET, error);
1112 * Get metadata register index for specified steering domain.
1115 * Pointer to the rte_eth_dev structure.
1117 * Attributes of flow to determine steering domain.
1119 * Pointer to the error structure.
1122 * positive index on success, a negative errno value otherwise
1123 * and rte_errno is set.
1125 static enum modify_reg
1126 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1127 const struct rte_flow_attr *attr,
1128 struct rte_flow_error *error)
1131 mlx5_flow_get_reg_id(dev, attr->transfer ?
1135 MLX5_METADATA_RX, 0, error);
1137 return rte_flow_error_set(error,
1138 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1139 NULL, "unavailable "
1140 "metadata register");
1145 * Convert SET_META action to DV specification.
1148 * Pointer to the rte_eth_dev structure.
1149 * @param[in,out] resource
1150 * Pointer to the modify-header resource.
1152 * Attributes of flow that includes this item.
1154 * Pointer to action specification.
1156 * Pointer to the error structure.
1159 * 0 on success, a negative errno value otherwise and rte_errno is set.
1162 flow_dv_convert_action_set_meta
1163 (struct rte_eth_dev *dev,
1164 struct mlx5_flow_dv_modify_hdr_resource *resource,
1165 const struct rte_flow_attr *attr,
1166 const struct rte_flow_action_set_meta *conf,
1167 struct rte_flow_error *error)
1169 uint32_t data = conf->data;
1170 uint32_t mask = conf->mask;
1171 struct rte_flow_item item = {
1175 struct field_modify_info reg_c_x[] = {
1178 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1183 * In datapath code there is no endianness
1184 * coversions for perfromance reasons, all
1185 * pattern conversions are done in rte_flow.
1187 if (reg == REG_C_0) {
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1192 MLX5_ASSERT(msk_c0);
1193 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1194 shl_c0 = rte_bsf32(msk_c0);
1196 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1200 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1202 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1203 /* The routine expects parameters in memory as big-endian ones. */
1204 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1205 MLX5_MODIFICATION_TYPE_SET, error);
1209 * Convert modify-header set IPv4 DSCP action to DV specification.
1211 * @param[in,out] resource
1212 * Pointer to the modify-header resource.
1214 * Pointer to action specification.
1216 * Pointer to the error structure.
1219 * 0 on success, a negative errno value otherwise and rte_errno is set.
1222 flow_dv_convert_action_modify_ipv4_dscp
1223 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1224 const struct rte_flow_action *action,
1225 struct rte_flow_error *error)
1227 const struct rte_flow_action_set_dscp *conf =
1228 (const struct rte_flow_action_set_dscp *)(action->conf);
1229 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1230 struct rte_flow_item_ipv4 ipv4;
1231 struct rte_flow_item_ipv4 ipv4_mask;
1233 memset(&ipv4, 0, sizeof(ipv4));
1234 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1235 ipv4.hdr.type_of_service = conf->dscp;
1236 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1238 item.mask = &ipv4_mask;
1239 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1240 MLX5_MODIFICATION_TYPE_SET, error);
1244 * Convert modify-header set IPv6 DSCP action to DV specification.
1246 * @param[in,out] resource
1247 * Pointer to the modify-header resource.
1249 * Pointer to action specification.
1251 * Pointer to the error structure.
1254 * 0 on success, a negative errno value otherwise and rte_errno is set.
1257 flow_dv_convert_action_modify_ipv6_dscp
1258 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1259 const struct rte_flow_action *action,
1260 struct rte_flow_error *error)
1262 const struct rte_flow_action_set_dscp *conf =
1263 (const struct rte_flow_action_set_dscp *)(action->conf);
1264 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1265 struct rte_flow_item_ipv6 ipv6;
1266 struct rte_flow_item_ipv6 ipv6_mask;
1268 memset(&ipv6, 0, sizeof(ipv6));
1269 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1271 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1272 * rdma-core only accept the DSCP bits byte aligned start from
1273 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1274 * bits in IPv6 case as rdma-core requires byte aligned value.
1276 ipv6.hdr.vtc_flow = conf->dscp;
1277 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1279 item.mask = &ipv6_mask;
1280 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1281 MLX5_MODIFICATION_TYPE_SET, error);
1285 * Validate MARK item.
1288 * Pointer to the rte_eth_dev structure.
1290 * Item specification.
1292 * Attributes of flow that includes this item.
1294 * Pointer to error structure.
1297 * 0 on success, a negative errno value otherwise and rte_errno is set.
1300 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1301 const struct rte_flow_item *item,
1302 const struct rte_flow_attr *attr __rte_unused,
1303 struct rte_flow_error *error)
1305 struct mlx5_priv *priv = dev->data->dev_private;
1306 struct mlx5_dev_config *config = &priv->config;
1307 const struct rte_flow_item_mark *spec = item->spec;
1308 const struct rte_flow_item_mark *mask = item->mask;
1309 const struct rte_flow_item_mark nic_mask = {
1310 .id = priv->sh->dv_mark_mask,
1314 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1315 return rte_flow_error_set(error, ENOTSUP,
1316 RTE_FLOW_ERROR_TYPE_ITEM, item,
1317 "extended metadata feature"
1319 if (!mlx5_flow_ext_mreg_supported(dev))
1320 return rte_flow_error_set(error, ENOTSUP,
1321 RTE_FLOW_ERROR_TYPE_ITEM, item,
1322 "extended metadata register"
1323 " isn't supported");
1325 return rte_flow_error_set(error, ENOTSUP,
1326 RTE_FLOW_ERROR_TYPE_ITEM, item,
1327 "extended metadata register"
1328 " isn't available");
1329 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1333 return rte_flow_error_set(error, EINVAL,
1334 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1336 "data cannot be empty");
1337 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1338 return rte_flow_error_set(error, EINVAL,
1339 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1341 "mark id exceeds the limit");
1344 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1345 (const uint8_t *)&nic_mask,
1346 sizeof(struct rte_flow_item_mark),
1354 * Validate META item.
1357 * Pointer to the rte_eth_dev structure.
1359 * Item specification.
1361 * Attributes of flow that includes this item.
1363 * Pointer to error structure.
1366 * 0 on success, a negative errno value otherwise and rte_errno is set.
1369 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1370 const struct rte_flow_item *item,
1371 const struct rte_flow_attr *attr,
1372 struct rte_flow_error *error)
1374 struct mlx5_priv *priv = dev->data->dev_private;
1375 struct mlx5_dev_config *config = &priv->config;
1376 const struct rte_flow_item_meta *spec = item->spec;
1377 const struct rte_flow_item_meta *mask = item->mask;
1378 struct rte_flow_item_meta nic_mask = {
1385 return rte_flow_error_set(error, EINVAL,
1386 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1388 "data cannot be empty");
1390 return rte_flow_error_set(error, EINVAL,
1391 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1392 "data cannot be zero");
1393 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1394 if (!mlx5_flow_ext_mreg_supported(dev))
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1397 "extended metadata register"
1398 " isn't supported");
1399 reg = flow_dv_get_metadata_reg(dev, attr, error);
1403 return rte_flow_error_set(error, ENOTSUP,
1404 RTE_FLOW_ERROR_TYPE_ITEM, item,
1408 nic_mask.data = priv->sh->dv_meta_mask;
1411 mask = &rte_flow_item_meta_mask;
1412 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1413 (const uint8_t *)&nic_mask,
1414 sizeof(struct rte_flow_item_meta),
1420 * Validate TAG item.
1423 * Pointer to the rte_eth_dev structure.
1425 * Item specification.
1427 * Attributes of flow that includes this item.
1429 * Pointer to error structure.
1432 * 0 on success, a negative errno value otherwise and rte_errno is set.
1435 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1436 const struct rte_flow_item *item,
1437 const struct rte_flow_attr *attr __rte_unused,
1438 struct rte_flow_error *error)
1440 const struct rte_flow_item_tag *spec = item->spec;
1441 const struct rte_flow_item_tag *mask = item->mask;
1442 const struct rte_flow_item_tag nic_mask = {
1443 .data = RTE_BE32(UINT32_MAX),
1448 if (!mlx5_flow_ext_mreg_supported(dev))
1449 return rte_flow_error_set(error, ENOTSUP,
1450 RTE_FLOW_ERROR_TYPE_ITEM, item,
1451 "extensive metadata register"
1452 " isn't supported");
1454 return rte_flow_error_set(error, EINVAL,
1455 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1457 "data cannot be empty");
1459 mask = &rte_flow_item_tag_mask;
1460 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1461 (const uint8_t *)&nic_mask,
1462 sizeof(struct rte_flow_item_tag),
1466 if (mask->index != 0xff)
1467 return rte_flow_error_set(error, EINVAL,
1468 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1469 "partial mask for tag index"
1470 " is not supported");
1471 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1474 MLX5_ASSERT(ret != REG_NONE);
1479 * Validate vport item.
1482 * Pointer to the rte_eth_dev structure.
1484 * Item specification.
1486 * Attributes of flow that includes this item.
1487 * @param[in] item_flags
1488 * Bit-fields that holds the items detected until now.
1490 * Pointer to error structure.
1493 * 0 on success, a negative errno value otherwise and rte_errno is set.
1496 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1497 const struct rte_flow_item *item,
1498 const struct rte_flow_attr *attr,
1499 uint64_t item_flags,
1500 struct rte_flow_error *error)
1502 const struct rte_flow_item_port_id *spec = item->spec;
1503 const struct rte_flow_item_port_id *mask = item->mask;
1504 const struct rte_flow_item_port_id switch_mask = {
1507 struct mlx5_priv *esw_priv;
1508 struct mlx5_priv *dev_priv;
1511 if (!attr->transfer)
1512 return rte_flow_error_set(error, EINVAL,
1513 RTE_FLOW_ERROR_TYPE_ITEM,
1515 "match on port id is valid only"
1516 " when transfer flag is enabled");
1517 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1518 return rte_flow_error_set(error, ENOTSUP,
1519 RTE_FLOW_ERROR_TYPE_ITEM, item,
1520 "multiple source ports are not"
1523 mask = &switch_mask;
1524 if (mask->id != 0xffffffff)
1525 return rte_flow_error_set(error, ENOTSUP,
1526 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1528 "no support for partial mask on"
1530 ret = mlx5_flow_item_acceptable
1531 (item, (const uint8_t *)mask,
1532 (const uint8_t *)&rte_flow_item_port_id_mask,
1533 sizeof(struct rte_flow_item_port_id),
1539 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1541 return rte_flow_error_set(error, rte_errno,
1542 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1543 "failed to obtain E-Switch info for"
1545 dev_priv = mlx5_dev_to_eswitch_info(dev);
1547 return rte_flow_error_set(error, rte_errno,
1548 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1550 "failed to obtain E-Switch info");
1551 if (esw_priv->domain_id != dev_priv->domain_id)
1552 return rte_flow_error_set(error, EINVAL,
1553 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1554 "cannot match on a port from a"
1555 " different E-Switch");
1560 * Validate GTP item.
1563 * Pointer to the rte_eth_dev structure.
1565 * Item specification.
1566 * @param[in] item_flags
1567 * Bit-fields that holds the items detected until now.
1569 * Pointer to error structure.
1572 * 0 on success, a negative errno value otherwise and rte_errno is set.
1575 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1576 const struct rte_flow_item *item,
1577 uint64_t item_flags,
1578 struct rte_flow_error *error)
1580 struct mlx5_priv *priv = dev->data->dev_private;
1581 const struct rte_flow_item_gtp *mask = item->mask;
1582 const struct rte_flow_item_gtp nic_mask = {
1584 .teid = RTE_BE32(0xffffffff),
1587 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1588 return rte_flow_error_set(error, ENOTSUP,
1589 RTE_FLOW_ERROR_TYPE_ITEM, item,
1590 "GTP support is not enabled");
1591 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1592 return rte_flow_error_set(error, ENOTSUP,
1593 RTE_FLOW_ERROR_TYPE_ITEM, item,
1594 "multiple tunnel layers not"
1596 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1597 return rte_flow_error_set(error, EINVAL,
1598 RTE_FLOW_ERROR_TYPE_ITEM, item,
1599 "no outer UDP layer found");
1601 mask = &rte_flow_item_gtp_mask;
1602 return mlx5_flow_item_acceptable
1603 (item, (const uint8_t *)mask,
1604 (const uint8_t *)&nic_mask,
1605 sizeof(struct rte_flow_item_gtp),
1610 * Validate the pop VLAN action.
1613 * Pointer to the rte_eth_dev structure.
1614 * @param[in] action_flags
1615 * Holds the actions detected until now.
1617 * Pointer to the pop vlan action.
1618 * @param[in] item_flags
1619 * The items found in this flow rule.
1621 * Pointer to flow attributes.
1623 * Pointer to error structure.
1626 * 0 on success, a negative errno value otherwise and rte_errno is set.
1629 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1630 uint64_t action_flags,
1631 const struct rte_flow_action *action,
1632 uint64_t item_flags,
1633 const struct rte_flow_attr *attr,
1634 struct rte_flow_error *error)
1636 struct mlx5_priv *priv = dev->data->dev_private;
1640 if (!priv->sh->pop_vlan_action)
1641 return rte_flow_error_set(error, ENOTSUP,
1642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1644 "pop vlan action is not supported");
1646 return rte_flow_error_set(error, ENOTSUP,
1647 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1649 "pop vlan action not supported for "
1651 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1652 return rte_flow_error_set(error, ENOTSUP,
1653 RTE_FLOW_ERROR_TYPE_ACTION, action,
1654 "no support for multiple VLAN "
1656 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1657 return rte_flow_error_set(error, ENOTSUP,
1658 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1660 "cannot pop vlan without a "
1661 "match on (outer) vlan in the flow");
1662 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1663 return rte_flow_error_set(error, EINVAL,
1664 RTE_FLOW_ERROR_TYPE_ACTION, action,
1665 "wrong action order, port_id should "
1666 "be after pop VLAN action");
1671 * Get VLAN default info from vlan match info.
1674 * the list of item specifications.
1676 * pointer VLAN info to fill to.
1679 * 0 on success, a negative errno value otherwise and rte_errno is set.
1682 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1683 struct rte_vlan_hdr *vlan)
1685 const struct rte_flow_item_vlan nic_mask = {
1686 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1687 MLX5DV_FLOW_VLAN_VID_MASK),
1688 .inner_type = RTE_BE16(0xffff),
1693 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1694 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1696 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1697 const struct rte_flow_item_vlan *vlan_m = items->mask;
1698 const struct rte_flow_item_vlan *vlan_v = items->spec;
1702 /* Only full match values are accepted */
1703 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1704 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1705 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1707 rte_be_to_cpu_16(vlan_v->tci &
1708 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1710 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1711 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1712 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1714 rte_be_to_cpu_16(vlan_v->tci &
1715 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1717 if (vlan_m->inner_type == nic_mask.inner_type)
1718 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1719 vlan_m->inner_type);
1724 * Validate the push VLAN action.
1726 * @param[in] action_flags
1727 * Holds the actions detected until now.
1728 * @param[in] item_flags
1729 * The items found in this flow rule.
1731 * Pointer to the action structure.
1733 * Pointer to flow attributes
1735 * Pointer to error structure.
1738 * 0 on success, a negative errno value otherwise and rte_errno is set.
1741 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1742 uint64_t item_flags __rte_unused,
1743 const struct rte_flow_action *action,
1744 const struct rte_flow_attr *attr,
1745 struct rte_flow_error *error)
1747 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1749 if (!attr->transfer && attr->ingress)
1750 return rte_flow_error_set(error, ENOTSUP,
1751 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1753 "push VLAN action not supported for "
1755 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1756 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1757 return rte_flow_error_set(error, EINVAL,
1758 RTE_FLOW_ERROR_TYPE_ACTION, action,
1759 "invalid vlan ethertype");
1760 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1761 return rte_flow_error_set(error, ENOTSUP,
1762 RTE_FLOW_ERROR_TYPE_ACTION, action,
1763 "no support for multiple VLAN "
1765 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1766 return rte_flow_error_set(error, EINVAL,
1767 RTE_FLOW_ERROR_TYPE_ACTION, action,
1768 "wrong action order, port_id should "
1769 "be after push VLAN");
1775 * Validate the set VLAN PCP.
1777 * @param[in] action_flags
1778 * Holds the actions detected until now.
1779 * @param[in] actions
1780 * Pointer to the list of actions remaining in the flow rule.
1782 * Pointer to error structure.
1785 * 0 on success, a negative errno value otherwise and rte_errno is set.
1788 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1789 const struct rte_flow_action actions[],
1790 struct rte_flow_error *error)
1792 const struct rte_flow_action *action = actions;
1793 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1795 if (conf->vlan_pcp > 7)
1796 return rte_flow_error_set(error, EINVAL,
1797 RTE_FLOW_ERROR_TYPE_ACTION, action,
1798 "VLAN PCP value is too big");
1799 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1800 return rte_flow_error_set(error, ENOTSUP,
1801 RTE_FLOW_ERROR_TYPE_ACTION, action,
1802 "set VLAN PCP action must follow "
1803 "the push VLAN action");
1804 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1805 return rte_flow_error_set(error, ENOTSUP,
1806 RTE_FLOW_ERROR_TYPE_ACTION, action,
1807 "Multiple VLAN PCP modification are "
1809 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1810 return rte_flow_error_set(error, EINVAL,
1811 RTE_FLOW_ERROR_TYPE_ACTION, action,
1812 "wrong action order, port_id should "
1813 "be after set VLAN PCP");
1818 * Validate the set VLAN VID.
1820 * @param[in] item_flags
1821 * Holds the items detected in this rule.
1822 * @param[in] action_flags
1823 * Holds the actions detected until now.
1824 * @param[in] actions
1825 * Pointer to the list of actions remaining in the flow rule.
1827 * Pointer to error structure.
1830 * 0 on success, a negative errno value otherwise and rte_errno is set.
1833 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1834 uint64_t action_flags,
1835 const struct rte_flow_action actions[],
1836 struct rte_flow_error *error)
1838 const struct rte_flow_action *action = actions;
1839 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1841 if (conf->vlan_vid > RTE_BE16(0xFFE))
1842 return rte_flow_error_set(error, EINVAL,
1843 RTE_FLOW_ERROR_TYPE_ACTION, action,
1844 "VLAN VID value is too big");
1845 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1846 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_ACTION, action,
1849 "set VLAN VID action must follow push"
1850 " VLAN action or match on VLAN item");
1851 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1852 return rte_flow_error_set(error, ENOTSUP,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "Multiple VLAN VID modifications are "
1856 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1857 return rte_flow_error_set(error, EINVAL,
1858 RTE_FLOW_ERROR_TYPE_ACTION, action,
1859 "wrong action order, port_id should "
1860 "be after set VLAN VID");
1865 * Validate the FLAG action.
1868 * Pointer to the rte_eth_dev structure.
1869 * @param[in] action_flags
1870 * Holds the actions detected until now.
1872 * Pointer to flow attributes
1874 * Pointer to error structure.
1877 * 0 on success, a negative errno value otherwise and rte_errno is set.
1880 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1881 uint64_t action_flags,
1882 const struct rte_flow_attr *attr,
1883 struct rte_flow_error *error)
1885 struct mlx5_priv *priv = dev->data->dev_private;
1886 struct mlx5_dev_config *config = &priv->config;
1889 /* Fall back if no extended metadata register support. */
1890 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1891 return mlx5_flow_validate_action_flag(action_flags, attr,
1893 /* Extensive metadata mode requires registers. */
1894 if (!mlx5_flow_ext_mreg_supported(dev))
1895 return rte_flow_error_set(error, ENOTSUP,
1896 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1897 "no metadata registers "
1898 "to support flag action");
1899 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1900 return rte_flow_error_set(error, ENOTSUP,
1901 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1902 "extended metadata register"
1903 " isn't available");
1904 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1907 MLX5_ASSERT(ret > 0);
1908 if (action_flags & MLX5_FLOW_ACTION_MARK)
1909 return rte_flow_error_set(error, EINVAL,
1910 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1911 "can't mark and flag in same flow");
1912 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1913 return rte_flow_error_set(error, EINVAL,
1914 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1916 " actions in same flow");
1921 * Validate MARK action.
1924 * Pointer to the rte_eth_dev structure.
1926 * Pointer to action.
1927 * @param[in] action_flags
1928 * Holds the actions detected until now.
1930 * Pointer to flow attributes
1932 * Pointer to error structure.
1935 * 0 on success, a negative errno value otherwise and rte_errno is set.
1938 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1939 const struct rte_flow_action *action,
1940 uint64_t action_flags,
1941 const struct rte_flow_attr *attr,
1942 struct rte_flow_error *error)
1944 struct mlx5_priv *priv = dev->data->dev_private;
1945 struct mlx5_dev_config *config = &priv->config;
1946 const struct rte_flow_action_mark *mark = action->conf;
1949 /* Fall back if no extended metadata register support. */
1950 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1951 return mlx5_flow_validate_action_mark(action, action_flags,
1953 /* Extensive metadata mode requires registers. */
1954 if (!mlx5_flow_ext_mreg_supported(dev))
1955 return rte_flow_error_set(error, ENOTSUP,
1956 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1957 "no metadata registers "
1958 "to support mark action");
1959 if (!priv->sh->dv_mark_mask)
1960 return rte_flow_error_set(error, ENOTSUP,
1961 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1962 "extended metadata register"
1963 " isn't available");
1964 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1967 MLX5_ASSERT(ret > 0);
1969 return rte_flow_error_set(error, EINVAL,
1970 RTE_FLOW_ERROR_TYPE_ACTION, action,
1971 "configuration cannot be null");
1972 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1973 return rte_flow_error_set(error, EINVAL,
1974 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1976 "mark id exceeds the limit");
1977 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1978 return rte_flow_error_set(error, EINVAL,
1979 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1980 "can't flag and mark in same flow");
1981 if (action_flags & MLX5_FLOW_ACTION_MARK)
1982 return rte_flow_error_set(error, EINVAL,
1983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1984 "can't have 2 mark actions in same"
1990 * Validate SET_META action.
1993 * Pointer to the rte_eth_dev structure.
1995 * Pointer to the action structure.
1996 * @param[in] action_flags
1997 * Holds the actions detected until now.
1999 * Pointer to flow attributes
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2008 const struct rte_flow_action *action,
2009 uint64_t action_flags __rte_unused,
2010 const struct rte_flow_attr *attr,
2011 struct rte_flow_error *error)
2013 const struct rte_flow_action_set_meta *conf;
2014 uint32_t nic_mask = UINT32_MAX;
2017 if (!mlx5_flow_ext_mreg_supported(dev))
2018 return rte_flow_error_set(error, ENOTSUP,
2019 RTE_FLOW_ERROR_TYPE_ACTION, action,
2020 "extended metadata register"
2021 " isn't supported");
2022 reg = flow_dv_get_metadata_reg(dev, attr, error);
2025 if (reg != REG_A && reg != REG_B) {
2026 struct mlx5_priv *priv = dev->data->dev_private;
2028 nic_mask = priv->sh->dv_meta_mask;
2030 if (!(action->conf))
2031 return rte_flow_error_set(error, EINVAL,
2032 RTE_FLOW_ERROR_TYPE_ACTION, action,
2033 "configuration cannot be null");
2034 conf = (const struct rte_flow_action_set_meta *)action->conf;
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, action,
2038 "zero mask doesn't have any effect");
2039 if (conf->mask & ~nic_mask)
2040 return rte_flow_error_set(error, EINVAL,
2041 RTE_FLOW_ERROR_TYPE_ACTION, action,
2042 "meta data must be within reg C0");
2043 if (!(conf->data & conf->mask))
2044 return rte_flow_error_set(error, EINVAL,
2045 RTE_FLOW_ERROR_TYPE_ACTION, action,
2046 "zero value has no effect");
2051 * Validate SET_TAG action.
2054 * Pointer to the rte_eth_dev structure.
2056 * Pointer to the action structure.
2057 * @param[in] action_flags
2058 * Holds the actions detected until now.
2060 * Pointer to flow attributes
2062 * Pointer to error structure.
2065 * 0 on success, a negative errno value otherwise and rte_errno is set.
2068 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2069 const struct rte_flow_action *action,
2070 uint64_t action_flags,
2071 const struct rte_flow_attr *attr,
2072 struct rte_flow_error *error)
2074 const struct rte_flow_action_set_tag *conf;
2075 const uint64_t terminal_action_flags =
2076 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2077 MLX5_FLOW_ACTION_RSS;
2080 if (!mlx5_flow_ext_mreg_supported(dev))
2081 return rte_flow_error_set(error, ENOTSUP,
2082 RTE_FLOW_ERROR_TYPE_ACTION, action,
2083 "extensive metadata register"
2084 " isn't supported");
2085 if (!(action->conf))
2086 return rte_flow_error_set(error, EINVAL,
2087 RTE_FLOW_ERROR_TYPE_ACTION, action,
2088 "configuration cannot be null");
2089 conf = (const struct rte_flow_action_set_tag *)action->conf;
2091 return rte_flow_error_set(error, EINVAL,
2092 RTE_FLOW_ERROR_TYPE_ACTION, action,
2093 "zero mask doesn't have any effect");
2094 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2097 if (!attr->transfer && attr->ingress &&
2098 (action_flags & terminal_action_flags))
2099 return rte_flow_error_set(error, EINVAL,
2100 RTE_FLOW_ERROR_TYPE_ACTION, action,
2101 "set_tag has no effect"
2102 " with terminal actions");
2107 * Validate count action.
2110 * Pointer to rte_eth_dev structure.
2112 * Pointer to error structure.
2115 * 0 on success, a negative errno value otherwise and rte_errno is set.
2118 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2119 struct rte_flow_error *error)
2121 struct mlx5_priv *priv = dev->data->dev_private;
2123 if (!priv->config.devx)
2125 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2129 return rte_flow_error_set
2131 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2133 "count action not supported");
2137 * Validate the L2 encap action.
2139 * @param[in] action_flags
2140 * Holds the actions detected until now.
2142 * Pointer to the action structure.
2144 * Pointer to error structure.
2147 * 0 on success, a negative errno value otherwise and rte_errno is set.
2150 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2151 const struct rte_flow_action *action,
2152 struct rte_flow_error *error)
2154 if (!(action->conf))
2155 return rte_flow_error_set(error, EINVAL,
2156 RTE_FLOW_ERROR_TYPE_ACTION, action,
2157 "configuration cannot be null");
2158 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2159 return rte_flow_error_set(error, EINVAL,
2160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2161 "can only have a single encap action "
2167 * Validate a decap action.
2169 * @param[in] action_flags
2170 * Holds the actions detected until now.
2172 * Pointer to flow attributes
2174 * Pointer to error structure.
2177 * 0 on success, a negative errno value otherwise and rte_errno is set.
2180 flow_dv_validate_action_decap(uint64_t action_flags,
2181 const struct rte_flow_attr *attr,
2182 struct rte_flow_error *error)
2184 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2185 return rte_flow_error_set(error, ENOTSUP,
2186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 MLX5_FLOW_ACTION_DECAP ? "can only "
2189 "have a single decap action" : "decap "
2190 "after encap is not supported");
2191 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2192 return rte_flow_error_set(error, EINVAL,
2193 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2194 "can't have decap action after"
2197 return rte_flow_error_set(error, ENOTSUP,
2198 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2200 "decap action not supported for "
2205 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2208 * Validate the raw encap and decap actions.
2211 * Pointer to the decap action.
2213 * Pointer to the encap action.
2215 * Pointer to flow attributes
2216 * @param[in/out] action_flags
2217 * Holds the actions detected until now.
2218 * @param[out] actions_n
2219 * pointer to the number of actions counter.
2221 * Pointer to error structure.
2224 * 0 on success, a negative errno value otherwise and rte_errno is set.
2227 flow_dv_validate_action_raw_encap_decap
2228 (const struct rte_flow_action_raw_decap *decap,
2229 const struct rte_flow_action_raw_encap *encap,
2230 const struct rte_flow_attr *attr, uint64_t *action_flags,
2231 int *actions_n, struct rte_flow_error *error)
2235 if (encap && (!encap->size || !encap->data))
2236 return rte_flow_error_set(error, EINVAL,
2237 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2238 "raw encap data cannot be empty");
2239 if (decap && encap) {
2240 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2241 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2244 else if (encap->size <=
2245 MLX5_ENCAPSULATION_DECISION_SIZE &&
2247 MLX5_ENCAPSULATION_DECISION_SIZE)
2250 else if (encap->size >
2251 MLX5_ENCAPSULATION_DECISION_SIZE &&
2253 MLX5_ENCAPSULATION_DECISION_SIZE)
2254 /* 2 L2 actions: encap and decap. */
2257 return rte_flow_error_set(error,
2259 RTE_FLOW_ERROR_TYPE_ACTION,
2260 NULL, "unsupported too small "
2261 "raw decap and too small raw "
2262 "encap combination");
2265 ret = flow_dv_validate_action_decap(*action_flags, attr, error);
2268 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2272 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2273 return rte_flow_error_set(error, ENOTSUP,
2274 RTE_FLOW_ERROR_TYPE_ACTION,
2276 "small raw encap size");
2277 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2278 return rte_flow_error_set(error, EINVAL,
2279 RTE_FLOW_ERROR_TYPE_ACTION,
2281 "more than one encap action");
2282 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2289 * Find existing encap/decap resource or create and register a new one.
2291 * @param[in, out] dev
2292 * Pointer to rte_eth_dev structure.
2293 * @param[in, out] resource
2294 * Pointer to encap/decap resource.
2295 * @parm[in, out] dev_flow
2296 * Pointer to the dev_flow.
2298 * pointer to error structure.
2301 * 0 on success otherwise -errno and errno is set.
2304 flow_dv_encap_decap_resource_register
2305 (struct rte_eth_dev *dev,
2306 struct mlx5_flow_dv_encap_decap_resource *resource,
2307 struct mlx5_flow *dev_flow,
2308 struct rte_flow_error *error)
2310 struct mlx5_priv *priv = dev->data->dev_private;
2311 struct mlx5_ibv_shared *sh = priv->sh;
2312 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2313 struct mlx5dv_dr_domain *domain;
2315 resource->flags = dev_flow->group ? 0 : 1;
2316 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2317 domain = sh->fdb_domain;
2318 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2319 domain = sh->rx_domain;
2321 domain = sh->tx_domain;
2322 /* Lookup a matching resource from cache. */
2323 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2324 if (resource->reformat_type == cache_resource->reformat_type &&
2325 resource->ft_type == cache_resource->ft_type &&
2326 resource->flags == cache_resource->flags &&
2327 resource->size == cache_resource->size &&
2328 !memcmp((const void *)resource->buf,
2329 (const void *)cache_resource->buf,
2331 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2332 (void *)cache_resource,
2333 rte_atomic32_read(&cache_resource->refcnt));
2334 rte_atomic32_inc(&cache_resource->refcnt);
2335 dev_flow->dv.encap_decap = cache_resource;
2339 /* Register new encap/decap resource. */
2340 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2341 if (!cache_resource)
2342 return rte_flow_error_set(error, ENOMEM,
2343 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2344 "cannot allocate resource memory");
2345 *cache_resource = *resource;
2346 cache_resource->verbs_action =
2347 mlx5_glue->dv_create_flow_action_packet_reformat
2348 (sh->ctx, cache_resource->reformat_type,
2349 cache_resource->ft_type, domain, cache_resource->flags,
2350 cache_resource->size,
2351 (cache_resource->size ? cache_resource->buf : NULL));
2352 if (!cache_resource->verbs_action) {
2353 rte_free(cache_resource);
2354 return rte_flow_error_set(error, ENOMEM,
2355 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2356 NULL, "cannot create action");
2358 rte_atomic32_init(&cache_resource->refcnt);
2359 rte_atomic32_inc(&cache_resource->refcnt);
2360 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2361 dev_flow->dv.encap_decap = cache_resource;
2362 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2363 (void *)cache_resource,
2364 rte_atomic32_read(&cache_resource->refcnt));
2369 * Find existing table jump resource or create and register a new one.
2371 * @param[in, out] dev
2372 * Pointer to rte_eth_dev structure.
2373 * @param[in, out] tbl
2374 * Pointer to flow table resource.
2375 * @parm[in, out] dev_flow
2376 * Pointer to the dev_flow.
2378 * pointer to error structure.
2381 * 0 on success otherwise -errno and errno is set.
2384 flow_dv_jump_tbl_resource_register
2385 (struct rte_eth_dev *dev __rte_unused,
2386 struct mlx5_flow_tbl_resource *tbl,
2387 struct mlx5_flow *dev_flow,
2388 struct rte_flow_error *error)
2390 struct mlx5_flow_tbl_data_entry *tbl_data =
2391 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2395 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2397 tbl_data->jump.action =
2398 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2400 if (!tbl_data->jump.action)
2401 return rte_flow_error_set(error, ENOMEM,
2402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2403 NULL, "cannot create jump action");
2404 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2405 (void *)&tbl_data->jump, cnt);
2407 MLX5_ASSERT(tbl_data->jump.action);
2408 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2409 (void *)&tbl_data->jump, cnt);
2411 rte_atomic32_inc(&tbl_data->jump.refcnt);
2412 dev_flow->dv.jump = &tbl_data->jump;
2417 * Find existing table port ID resource or create and register a new one.
2419 * @param[in, out] dev
2420 * Pointer to rte_eth_dev structure.
2421 * @param[in, out] resource
2422 * Pointer to port ID action resource.
2423 * @parm[in, out] dev_flow
2424 * Pointer to the dev_flow.
2426 * pointer to error structure.
2429 * 0 on success otherwise -errno and errno is set.
2432 flow_dv_port_id_action_resource_register
2433 (struct rte_eth_dev *dev,
2434 struct mlx5_flow_dv_port_id_action_resource *resource,
2435 struct mlx5_flow *dev_flow,
2436 struct rte_flow_error *error)
2438 struct mlx5_priv *priv = dev->data->dev_private;
2439 struct mlx5_ibv_shared *sh = priv->sh;
2440 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2442 /* Lookup a matching resource from cache. */
2443 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2444 if (resource->port_id == cache_resource->port_id) {
2445 DRV_LOG(DEBUG, "port id action resource resource %p: "
2447 (void *)cache_resource,
2448 rte_atomic32_read(&cache_resource->refcnt));
2449 rte_atomic32_inc(&cache_resource->refcnt);
2450 dev_flow->dv.port_id_action = cache_resource;
2454 /* Register new port id action resource. */
2455 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2456 if (!cache_resource)
2457 return rte_flow_error_set(error, ENOMEM,
2458 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2459 "cannot allocate resource memory");
2460 *cache_resource = *resource;
2462 * Depending on rdma_core version the glue routine calls
2463 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2464 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2466 cache_resource->action =
2467 mlx5_glue->dr_create_flow_action_dest_port
2468 (priv->sh->fdb_domain, resource->port_id);
2469 if (!cache_resource->action) {
2470 rte_free(cache_resource);
2471 return rte_flow_error_set(error, ENOMEM,
2472 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2473 NULL, "cannot create action");
2475 rte_atomic32_init(&cache_resource->refcnt);
2476 rte_atomic32_inc(&cache_resource->refcnt);
2477 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2478 dev_flow->dv.port_id_action = cache_resource;
2479 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2480 (void *)cache_resource,
2481 rte_atomic32_read(&cache_resource->refcnt));
2486 * Find existing push vlan resource or create and register a new one.
2488 * @param [in, out] dev
2489 * Pointer to rte_eth_dev structure.
2490 * @param[in, out] resource
2491 * Pointer to port ID action resource.
2492 * @parm[in, out] dev_flow
2493 * Pointer to the dev_flow.
2495 * pointer to error structure.
2498 * 0 on success otherwise -errno and errno is set.
2501 flow_dv_push_vlan_action_resource_register
2502 (struct rte_eth_dev *dev,
2503 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2504 struct mlx5_flow *dev_flow,
2505 struct rte_flow_error *error)
2507 struct mlx5_priv *priv = dev->data->dev_private;
2508 struct mlx5_ibv_shared *sh = priv->sh;
2509 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2510 struct mlx5dv_dr_domain *domain;
2512 /* Lookup a matching resource from cache. */
2513 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2514 if (resource->vlan_tag == cache_resource->vlan_tag &&
2515 resource->ft_type == cache_resource->ft_type) {
2516 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2518 (void *)cache_resource,
2519 rte_atomic32_read(&cache_resource->refcnt));
2520 rte_atomic32_inc(&cache_resource->refcnt);
2521 dev_flow->dv.push_vlan_res = cache_resource;
2525 /* Register new push_vlan action resource. */
2526 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2527 if (!cache_resource)
2528 return rte_flow_error_set(error, ENOMEM,
2529 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2530 "cannot allocate resource memory");
2531 *cache_resource = *resource;
2532 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2533 domain = sh->fdb_domain;
2534 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2535 domain = sh->rx_domain;
2537 domain = sh->tx_domain;
2538 cache_resource->action =
2539 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2540 resource->vlan_tag);
2541 if (!cache_resource->action) {
2542 rte_free(cache_resource);
2543 return rte_flow_error_set(error, ENOMEM,
2544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2545 NULL, "cannot create action");
2547 rte_atomic32_init(&cache_resource->refcnt);
2548 rte_atomic32_inc(&cache_resource->refcnt);
2549 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2550 dev_flow->dv.push_vlan_res = cache_resource;
2551 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2552 (void *)cache_resource,
2553 rte_atomic32_read(&cache_resource->refcnt));
2557 * Get the size of specific rte_flow_item_type
2559 * @param[in] item_type
2560 * Tested rte_flow_item_type.
2563 * sizeof struct item_type, 0 if void or irrelevant.
2566 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2570 switch (item_type) {
2571 case RTE_FLOW_ITEM_TYPE_ETH:
2572 retval = sizeof(struct rte_flow_item_eth);
2574 case RTE_FLOW_ITEM_TYPE_VLAN:
2575 retval = sizeof(struct rte_flow_item_vlan);
2577 case RTE_FLOW_ITEM_TYPE_IPV4:
2578 retval = sizeof(struct rte_flow_item_ipv4);
2580 case RTE_FLOW_ITEM_TYPE_IPV6:
2581 retval = sizeof(struct rte_flow_item_ipv6);
2583 case RTE_FLOW_ITEM_TYPE_UDP:
2584 retval = sizeof(struct rte_flow_item_udp);
2586 case RTE_FLOW_ITEM_TYPE_TCP:
2587 retval = sizeof(struct rte_flow_item_tcp);
2589 case RTE_FLOW_ITEM_TYPE_VXLAN:
2590 retval = sizeof(struct rte_flow_item_vxlan);
2592 case RTE_FLOW_ITEM_TYPE_GRE:
2593 retval = sizeof(struct rte_flow_item_gre);
2595 case RTE_FLOW_ITEM_TYPE_NVGRE:
2596 retval = sizeof(struct rte_flow_item_nvgre);
2598 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2599 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2601 case RTE_FLOW_ITEM_TYPE_MPLS:
2602 retval = sizeof(struct rte_flow_item_mpls);
2604 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2612 #define MLX5_ENCAP_IPV4_VERSION 0x40
2613 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2614 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2615 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2616 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2617 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2618 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2621 * Convert the encap action data from list of rte_flow_item to raw buffer
2624 * Pointer to rte_flow_item objects list.
2626 * Pointer to the output buffer.
2628 * Pointer to the output buffer size.
2630 * Pointer to the error structure.
2633 * 0 on success, a negative errno value otherwise and rte_errno is set.
2636 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2637 size_t *size, struct rte_flow_error *error)
2639 struct rte_ether_hdr *eth = NULL;
2640 struct rte_vlan_hdr *vlan = NULL;
2641 struct rte_ipv4_hdr *ipv4 = NULL;
2642 struct rte_ipv6_hdr *ipv6 = NULL;
2643 struct rte_udp_hdr *udp = NULL;
2644 struct rte_vxlan_hdr *vxlan = NULL;
2645 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2646 struct rte_gre_hdr *gre = NULL;
2648 size_t temp_size = 0;
2651 return rte_flow_error_set(error, EINVAL,
2652 RTE_FLOW_ERROR_TYPE_ACTION,
2653 NULL, "invalid empty data");
2654 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2655 len = flow_dv_get_item_len(items->type);
2656 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2657 return rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ACTION,
2659 (void *)items->type,
2660 "items total size is too big"
2661 " for encap action");
2662 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2663 switch (items->type) {
2664 case RTE_FLOW_ITEM_TYPE_ETH:
2665 eth = (struct rte_ether_hdr *)&buf[temp_size];
2667 case RTE_FLOW_ITEM_TYPE_VLAN:
2668 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2670 return rte_flow_error_set(error, EINVAL,
2671 RTE_FLOW_ERROR_TYPE_ACTION,
2672 (void *)items->type,
2673 "eth header not found");
2674 if (!eth->ether_type)
2675 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2677 case RTE_FLOW_ITEM_TYPE_IPV4:
2678 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2680 return rte_flow_error_set(error, EINVAL,
2681 RTE_FLOW_ERROR_TYPE_ACTION,
2682 (void *)items->type,
2683 "neither eth nor vlan"
2685 if (vlan && !vlan->eth_proto)
2686 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2687 else if (eth && !eth->ether_type)
2688 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2689 if (!ipv4->version_ihl)
2690 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2691 MLX5_ENCAP_IPV4_IHL_MIN;
2692 if (!ipv4->time_to_live)
2693 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2695 case RTE_FLOW_ITEM_TYPE_IPV6:
2696 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2698 return rte_flow_error_set(error, EINVAL,
2699 RTE_FLOW_ERROR_TYPE_ACTION,
2700 (void *)items->type,
2701 "neither eth nor vlan"
2703 if (vlan && !vlan->eth_proto)
2704 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2705 else if (eth && !eth->ether_type)
2706 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2707 if (!ipv6->vtc_flow)
2709 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2710 if (!ipv6->hop_limits)
2711 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2713 case RTE_FLOW_ITEM_TYPE_UDP:
2714 udp = (struct rte_udp_hdr *)&buf[temp_size];
2716 return rte_flow_error_set(error, EINVAL,
2717 RTE_FLOW_ERROR_TYPE_ACTION,
2718 (void *)items->type,
2719 "ip header not found");
2720 if (ipv4 && !ipv4->next_proto_id)
2721 ipv4->next_proto_id = IPPROTO_UDP;
2722 else if (ipv6 && !ipv6->proto)
2723 ipv6->proto = IPPROTO_UDP;
2725 case RTE_FLOW_ITEM_TYPE_VXLAN:
2726 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2728 return rte_flow_error_set(error, EINVAL,
2729 RTE_FLOW_ERROR_TYPE_ACTION,
2730 (void *)items->type,
2731 "udp header not found");
2733 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2734 if (!vxlan->vx_flags)
2736 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2738 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2739 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2741 return rte_flow_error_set(error, EINVAL,
2742 RTE_FLOW_ERROR_TYPE_ACTION,
2743 (void *)items->type,
2744 "udp header not found");
2745 if (!vxlan_gpe->proto)
2746 return rte_flow_error_set(error, EINVAL,
2747 RTE_FLOW_ERROR_TYPE_ACTION,
2748 (void *)items->type,
2749 "next protocol not found");
2752 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2753 if (!vxlan_gpe->vx_flags)
2754 vxlan_gpe->vx_flags =
2755 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2757 case RTE_FLOW_ITEM_TYPE_GRE:
2758 case RTE_FLOW_ITEM_TYPE_NVGRE:
2759 gre = (struct rte_gre_hdr *)&buf[temp_size];
2761 return rte_flow_error_set(error, EINVAL,
2762 RTE_FLOW_ERROR_TYPE_ACTION,
2763 (void *)items->type,
2764 "next protocol not found");
2766 return rte_flow_error_set(error, EINVAL,
2767 RTE_FLOW_ERROR_TYPE_ACTION,
2768 (void *)items->type,
2769 "ip header not found");
2770 if (ipv4 && !ipv4->next_proto_id)
2771 ipv4->next_proto_id = IPPROTO_GRE;
2772 else if (ipv6 && !ipv6->proto)
2773 ipv6->proto = IPPROTO_GRE;
2775 case RTE_FLOW_ITEM_TYPE_VOID:
2778 return rte_flow_error_set(error, EINVAL,
2779 RTE_FLOW_ERROR_TYPE_ACTION,
2780 (void *)items->type,
2781 "unsupported item type");
2791 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2793 struct rte_ether_hdr *eth = NULL;
2794 struct rte_vlan_hdr *vlan = NULL;
2795 struct rte_ipv6_hdr *ipv6 = NULL;
2796 struct rte_udp_hdr *udp = NULL;
2800 eth = (struct rte_ether_hdr *)data;
2801 next_hdr = (char *)(eth + 1);
2802 proto = RTE_BE16(eth->ether_type);
2805 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2806 vlan = (struct rte_vlan_hdr *)next_hdr;
2807 proto = RTE_BE16(vlan->eth_proto);
2808 next_hdr += sizeof(struct rte_vlan_hdr);
2811 /* HW calculates IPv4 csum. no need to proceed */
2812 if (proto == RTE_ETHER_TYPE_IPV4)
2815 /* non IPv4/IPv6 header. not supported */
2816 if (proto != RTE_ETHER_TYPE_IPV6) {
2817 return rte_flow_error_set(error, ENOTSUP,
2818 RTE_FLOW_ERROR_TYPE_ACTION,
2819 NULL, "Cannot offload non IPv4/IPv6");
2822 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2824 /* ignore non UDP */
2825 if (ipv6->proto != IPPROTO_UDP)
2828 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2829 udp->dgram_cksum = 0;
2835 * Convert L2 encap action to DV specification.
2838 * Pointer to rte_eth_dev structure.
2840 * Pointer to action structure.
2841 * @param[in, out] dev_flow
2842 * Pointer to the mlx5_flow.
2843 * @param[in] transfer
2844 * Mark if the flow is E-Switch flow.
2846 * Pointer to the error structure.
2849 * 0 on success, a negative errno value otherwise and rte_errno is set.
2852 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2853 const struct rte_flow_action *action,
2854 struct mlx5_flow *dev_flow,
2856 struct rte_flow_error *error)
2858 const struct rte_flow_item *encap_data;
2859 const struct rte_flow_action_raw_encap *raw_encap_data;
2860 struct mlx5_flow_dv_encap_decap_resource res = {
2862 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2863 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2864 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2867 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2869 (const struct rte_flow_action_raw_encap *)action->conf;
2870 res.size = raw_encap_data->size;
2871 memcpy(res.buf, raw_encap_data->data, res.size);
2873 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2875 ((const struct rte_flow_action_vxlan_encap *)
2876 action->conf)->definition;
2879 ((const struct rte_flow_action_nvgre_encap *)
2880 action->conf)->definition;
2881 if (flow_dv_convert_encap_data(encap_data, res.buf,
2885 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2887 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2888 return rte_flow_error_set(error, EINVAL,
2889 RTE_FLOW_ERROR_TYPE_ACTION,
2890 NULL, "can't create L2 encap action");
2895 * Convert L2 decap action to DV specification.
2898 * Pointer to rte_eth_dev structure.
2899 * @param[in, out] dev_flow
2900 * Pointer to the mlx5_flow.
2901 * @param[in] transfer
2902 * Mark if the flow is E-Switch flow.
2904 * Pointer to the error structure.
2907 * 0 on success, a negative errno value otherwise and rte_errno is set.
2910 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2911 struct mlx5_flow *dev_flow,
2913 struct rte_flow_error *error)
2915 struct mlx5_flow_dv_encap_decap_resource res = {
2918 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2919 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2920 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2923 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2924 return rte_flow_error_set(error, EINVAL,
2925 RTE_FLOW_ERROR_TYPE_ACTION,
2926 NULL, "can't create L2 decap action");
2931 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2934 * Pointer to rte_eth_dev structure.
2936 * Pointer to action structure.
2937 * @param[in, out] dev_flow
2938 * Pointer to the mlx5_flow.
2940 * Pointer to the flow attributes.
2942 * Pointer to the error structure.
2945 * 0 on success, a negative errno value otherwise and rte_errno is set.
2948 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2949 const struct rte_flow_action *action,
2950 struct mlx5_flow *dev_flow,
2951 const struct rte_flow_attr *attr,
2952 struct rte_flow_error *error)
2954 const struct rte_flow_action_raw_encap *encap_data;
2955 struct mlx5_flow_dv_encap_decap_resource res;
2957 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2958 res.size = encap_data->size;
2959 memcpy(res.buf, encap_data->data, res.size);
2960 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
2961 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
2962 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
2964 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2966 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2967 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2968 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2969 return rte_flow_error_set(error, EINVAL,
2970 RTE_FLOW_ERROR_TYPE_ACTION,
2971 NULL, "can't create encap action");
2976 * Create action push VLAN.
2979 * Pointer to rte_eth_dev structure.
2981 * Pointer to the flow attributes.
2983 * Pointer to the vlan to push to the Ethernet header.
2984 * @param[in, out] dev_flow
2985 * Pointer to the mlx5_flow.
2987 * Pointer to the error structure.
2990 * 0 on success, a negative errno value otherwise and rte_errno is set.
2993 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2994 const struct rte_flow_attr *attr,
2995 const struct rte_vlan_hdr *vlan,
2996 struct mlx5_flow *dev_flow,
2997 struct rte_flow_error *error)
2999 struct mlx5_flow_dv_push_vlan_action_resource res;
3002 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3005 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3007 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3008 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3009 return flow_dv_push_vlan_action_resource_register
3010 (dev, &res, dev_flow, error);
3014 * Validate the modify-header actions.
3016 * @param[in] action_flags
3017 * Holds the actions detected until now.
3019 * Pointer to the modify action.
3021 * Pointer to error structure.
3024 * 0 on success, a negative errno value otherwise and rte_errno is set.
3027 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3028 const struct rte_flow_action *action,
3029 struct rte_flow_error *error)
3031 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3032 return rte_flow_error_set(error, EINVAL,
3033 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3034 NULL, "action configuration not set");
3035 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3036 return rte_flow_error_set(error, EINVAL,
3037 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3038 "can't have encap action before"
3044 * Validate the modify-header MAC address actions.
3046 * @param[in] action_flags
3047 * Holds the actions detected until now.
3049 * Pointer to the modify action.
3050 * @param[in] item_flags
3051 * Holds the items detected.
3053 * Pointer to error structure.
3056 * 0 on success, a negative errno value otherwise and rte_errno is set.
3059 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3060 const struct rte_flow_action *action,
3061 const uint64_t item_flags,
3062 struct rte_flow_error *error)
3066 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3068 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3069 return rte_flow_error_set(error, EINVAL,
3070 RTE_FLOW_ERROR_TYPE_ACTION,
3072 "no L2 item in pattern");
3078 * Validate the modify-header IPv4 address actions.
3080 * @param[in] action_flags
3081 * Holds the actions detected until now.
3083 * Pointer to the modify action.
3084 * @param[in] item_flags
3085 * Holds the items detected.
3087 * Pointer to error structure.
3090 * 0 on success, a negative errno value otherwise and rte_errno is set.
3093 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3094 const struct rte_flow_action *action,
3095 const uint64_t item_flags,
3096 struct rte_flow_error *error)
3101 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3103 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3104 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3105 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3106 if (!(item_flags & layer))
3107 return rte_flow_error_set(error, EINVAL,
3108 RTE_FLOW_ERROR_TYPE_ACTION,
3110 "no ipv4 item in pattern");
3116 * Validate the modify-header IPv6 address actions.
3118 * @param[in] action_flags
3119 * Holds the actions detected until now.
3121 * Pointer to the modify action.
3122 * @param[in] item_flags
3123 * Holds the items detected.
3125 * Pointer to error structure.
3128 * 0 on success, a negative errno value otherwise and rte_errno is set.
3131 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3132 const struct rte_flow_action *action,
3133 const uint64_t item_flags,
3134 struct rte_flow_error *error)
3139 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3141 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3142 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3143 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3144 if (!(item_flags & layer))
3145 return rte_flow_error_set(error, EINVAL,
3146 RTE_FLOW_ERROR_TYPE_ACTION,
3148 "no ipv6 item in pattern");
3154 * Validate the modify-header TP actions.
3156 * @param[in] action_flags
3157 * Holds the actions detected until now.
3159 * Pointer to the modify action.
3160 * @param[in] item_flags
3161 * Holds the items detected.
3163 * Pointer to error structure.
3166 * 0 on success, a negative errno value otherwise and rte_errno is set.
3169 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3170 const struct rte_flow_action *action,
3171 const uint64_t item_flags,
3172 struct rte_flow_error *error)
3177 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3179 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3180 MLX5_FLOW_LAYER_INNER_L4 :
3181 MLX5_FLOW_LAYER_OUTER_L4;
3182 if (!(item_flags & layer))
3183 return rte_flow_error_set(error, EINVAL,
3184 RTE_FLOW_ERROR_TYPE_ACTION,
3185 NULL, "no transport layer "
3192 * Validate the modify-header actions of increment/decrement
3193 * TCP Sequence-number.
3195 * @param[in] action_flags
3196 * Holds the actions detected until now.
3198 * Pointer to the modify action.
3199 * @param[in] item_flags
3200 * Holds the items detected.
3202 * Pointer to error structure.
3205 * 0 on success, a negative errno value otherwise and rte_errno is set.
3208 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3209 const struct rte_flow_action *action,
3210 const uint64_t item_flags,
3211 struct rte_flow_error *error)
3216 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3218 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3219 MLX5_FLOW_LAYER_INNER_L4_TCP :
3220 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3221 if (!(item_flags & layer))
3222 return rte_flow_error_set(error, EINVAL,
3223 RTE_FLOW_ERROR_TYPE_ACTION,
3224 NULL, "no TCP item in"
3226 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3227 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3228 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3229 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3230 return rte_flow_error_set(error, EINVAL,
3231 RTE_FLOW_ERROR_TYPE_ACTION,
3233 "cannot decrease and increase"
3234 " TCP sequence number"
3235 " at the same time");
3241 * Validate the modify-header actions of increment/decrement
3242 * TCP Acknowledgment number.
3244 * @param[in] action_flags
3245 * Holds the actions detected until now.
3247 * Pointer to the modify action.
3248 * @param[in] item_flags
3249 * Holds the items detected.
3251 * Pointer to error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3258 const struct rte_flow_action *action,
3259 const uint64_t item_flags,
3260 struct rte_flow_error *error)
3265 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3267 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3268 MLX5_FLOW_LAYER_INNER_L4_TCP :
3269 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3270 if (!(item_flags & layer))
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION,
3273 NULL, "no TCP item in"
3275 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3276 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3277 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3278 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION,
3282 "cannot decrease and increase"
3283 " TCP acknowledgment number"
3284 " at the same time");
3290 * Validate the modify-header TTL actions.
3292 * @param[in] action_flags
3293 * Holds the actions detected until now.
3295 * Pointer to the modify action.
3296 * @param[in] item_flags
3297 * Holds the items detected.
3299 * Pointer to error structure.
3302 * 0 on success, a negative errno value otherwise and rte_errno is set.
3305 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3306 const struct rte_flow_action *action,
3307 const uint64_t item_flags,
3308 struct rte_flow_error *error)
3313 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3315 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3316 MLX5_FLOW_LAYER_INNER_L3 :
3317 MLX5_FLOW_LAYER_OUTER_L3;
3318 if (!(item_flags & layer))
3319 return rte_flow_error_set(error, EINVAL,
3320 RTE_FLOW_ERROR_TYPE_ACTION,
3322 "no IP protocol in pattern");
3328 * Validate jump action.
3331 * Pointer to the jump action.
3332 * @param[in] action_flags
3333 * Holds the actions detected until now.
3334 * @param[in] attributes
3335 * Pointer to flow attributes
3336 * @param[in] external
3337 * Action belongs to flow rule created by request external to PMD.
3339 * Pointer to error structure.
3342 * 0 on success, a negative errno value otherwise and rte_errno is set.
3345 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3346 uint64_t action_flags,
3347 const struct rte_flow_attr *attributes,
3348 bool external, struct rte_flow_error *error)
3350 uint32_t target_group, table;
3353 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3354 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3355 return rte_flow_error_set(error, EINVAL,
3356 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3357 "can't have 2 fate actions in"
3359 if (action_flags & MLX5_FLOW_ACTION_METER)
3360 return rte_flow_error_set(error, ENOTSUP,
3361 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3362 "jump with meter not support");
3364 return rte_flow_error_set(error, EINVAL,
3365 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3366 NULL, "action configuration not set");
3368 ((const struct rte_flow_action_jump *)action->conf)->group;
3369 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3370 true, &table, error);
3373 if (attributes->group == target_group)
3374 return rte_flow_error_set(error, EINVAL,
3375 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3376 "target group must be other than"
3377 " the current flow group");
3382 * Validate the port_id action.
3385 * Pointer to rte_eth_dev structure.
3386 * @param[in] action_flags
3387 * Bit-fields that holds the actions detected until now.
3389 * Port_id RTE action structure.
3391 * Attributes of flow that includes this action.
3393 * Pointer to error structure.
3396 * 0 on success, a negative errno value otherwise and rte_errno is set.
3399 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3400 uint64_t action_flags,
3401 const struct rte_flow_action *action,
3402 const struct rte_flow_attr *attr,
3403 struct rte_flow_error *error)
3405 const struct rte_flow_action_port_id *port_id;
3406 struct mlx5_priv *act_priv;
3407 struct mlx5_priv *dev_priv;
3410 if (!attr->transfer)
3411 return rte_flow_error_set(error, ENOTSUP,
3412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3414 "port id action is valid in transfer"
3416 if (!action || !action->conf)
3417 return rte_flow_error_set(error, ENOTSUP,
3418 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3420 "port id action parameters must be"
3422 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3423 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3424 return rte_flow_error_set(error, EINVAL,
3425 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3426 "can have only one fate actions in"
3428 dev_priv = mlx5_dev_to_eswitch_info(dev);
3430 return rte_flow_error_set(error, rte_errno,
3431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3433 "failed to obtain E-Switch info");
3434 port_id = action->conf;
3435 port = port_id->original ? dev->data->port_id : port_id->id;
3436 act_priv = mlx5_port_to_eswitch_info(port, false);
3438 return rte_flow_error_set
3440 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3441 "failed to obtain E-Switch port id for port");
3442 if (act_priv->domain_id != dev_priv->domain_id)
3443 return rte_flow_error_set
3445 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3446 "port does not belong to"
3447 " E-Switch being configured");
3452 * Get the maximum number of modify header actions.
3455 * Pointer to rte_eth_dev structure.
3457 * Flags bits to check if root level.
3460 * Max number of modify header actions device can support.
3463 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3466 * There's no way to directly query the max cap. Although it has to be
3467 * acquried by iterative trial, it is a safe assumption that more
3468 * actions are supported by FW if extensive metadata register is
3469 * supported. (Only in the root table)
3471 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3472 return MLX5_MAX_MODIFY_NUM;
3474 return mlx5_flow_ext_mreg_supported(dev) ?
3475 MLX5_ROOT_TBL_MODIFY_NUM :
3476 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3480 * Validate the meter action.
3483 * Pointer to rte_eth_dev structure.
3484 * @param[in] action_flags
3485 * Bit-fields that holds the actions detected until now.
3487 * Pointer to the meter action.
3489 * Attributes of flow that includes this action.
3491 * Pointer to error structure.
3494 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3497 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3498 uint64_t action_flags,
3499 const struct rte_flow_action *action,
3500 const struct rte_flow_attr *attr,
3501 struct rte_flow_error *error)
3503 struct mlx5_priv *priv = dev->data->dev_private;
3504 const struct rte_flow_action_meter *am = action->conf;
3505 struct mlx5_flow_meter *fm;
3508 return rte_flow_error_set(error, EINVAL,
3509 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3510 "meter action conf is NULL");
3512 if (action_flags & MLX5_FLOW_ACTION_METER)
3513 return rte_flow_error_set(error, ENOTSUP,
3514 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3515 "meter chaining not support");
3516 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3517 return rte_flow_error_set(error, ENOTSUP,
3518 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3519 "meter with jump not support");
3521 return rte_flow_error_set(error, ENOTSUP,
3522 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3524 "meter action not supported");
3525 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3527 return rte_flow_error_set(error, EINVAL,
3528 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3530 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3531 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3532 (!fm->attr.egress && !attr->egress && attr->ingress))))
3533 return rte_flow_error_set(error, EINVAL,
3534 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3535 "Flow attributes are either invalid "
3536 "or have a conflict with current "
3537 "meter attributes");
3542 * Validate the modify-header IPv4 DSCP actions.
3544 * @param[in] action_flags
3545 * Holds the actions detected until now.
3547 * Pointer to the modify action.
3548 * @param[in] item_flags
3549 * Holds the items detected.
3551 * Pointer to error structure.
3554 * 0 on success, a negative errno value otherwise and rte_errno is set.
3557 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3558 const struct rte_flow_action *action,
3559 const uint64_t item_flags,
3560 struct rte_flow_error *error)
3564 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3566 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3567 return rte_flow_error_set(error, EINVAL,
3568 RTE_FLOW_ERROR_TYPE_ACTION,
3570 "no ipv4 item in pattern");
3576 * Validate the modify-header IPv6 DSCP actions.
3578 * @param[in] action_flags
3579 * Holds the actions detected until now.
3581 * Pointer to the modify action.
3582 * @param[in] item_flags
3583 * Holds the items detected.
3585 * Pointer to error structure.
3588 * 0 on success, a negative errno value otherwise and rte_errno is set.
3591 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3592 const struct rte_flow_action *action,
3593 const uint64_t item_flags,
3594 struct rte_flow_error *error)
3598 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3600 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3601 return rte_flow_error_set(error, EINVAL,
3602 RTE_FLOW_ERROR_TYPE_ACTION,
3604 "no ipv6 item in pattern");
3610 * Find existing modify-header resource or create and register a new one.
3612 * @param dev[in, out]
3613 * Pointer to rte_eth_dev structure.
3614 * @param[in, out] resource
3615 * Pointer to modify-header resource.
3616 * @parm[in, out] dev_flow
3617 * Pointer to the dev_flow.
3619 * pointer to error structure.
3622 * 0 on success otherwise -errno and errno is set.
3625 flow_dv_modify_hdr_resource_register
3626 (struct rte_eth_dev *dev,
3627 struct mlx5_flow_dv_modify_hdr_resource *resource,
3628 struct mlx5_flow *dev_flow,
3629 struct rte_flow_error *error)
3631 struct mlx5_priv *priv = dev->data->dev_private;
3632 struct mlx5_ibv_shared *sh = priv->sh;
3633 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3634 struct mlx5dv_dr_domain *ns;
3635 uint32_t actions_len;
3638 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3639 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3641 return rte_flow_error_set(error, EOVERFLOW,
3642 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3643 "too many modify header items");
3644 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3645 ns = sh->fdb_domain;
3646 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3650 /* Lookup a matching resource from cache. */
3651 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3652 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3653 if (resource->ft_type == cache_resource->ft_type &&
3654 resource->actions_num == cache_resource->actions_num &&
3655 resource->flags == cache_resource->flags &&
3656 !memcmp((const void *)resource->actions,
3657 (const void *)cache_resource->actions,
3659 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3660 (void *)cache_resource,
3661 rte_atomic32_read(&cache_resource->refcnt));
3662 rte_atomic32_inc(&cache_resource->refcnt);
3663 dev_flow->dv.modify_hdr = cache_resource;
3667 /* Register new modify-header resource. */
3668 cache_resource = rte_calloc(__func__, 1,
3669 sizeof(*cache_resource) + actions_len, 0);
3670 if (!cache_resource)
3671 return rte_flow_error_set(error, ENOMEM,
3672 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3673 "cannot allocate resource memory");
3674 *cache_resource = *resource;
3675 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3676 cache_resource->verbs_action =
3677 mlx5_glue->dv_create_flow_action_modify_header
3678 (sh->ctx, cache_resource->ft_type, ns,
3679 cache_resource->flags, actions_len,
3680 (uint64_t *)cache_resource->actions);
3681 if (!cache_resource->verbs_action) {
3682 rte_free(cache_resource);
3683 return rte_flow_error_set(error, ENOMEM,
3684 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3685 NULL, "cannot create action");
3687 rte_atomic32_init(&cache_resource->refcnt);
3688 rte_atomic32_inc(&cache_resource->refcnt);
3689 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3690 dev_flow->dv.modify_hdr = cache_resource;
3691 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3692 (void *)cache_resource,
3693 rte_atomic32_read(&cache_resource->refcnt));
3697 #define MLX5_CNT_CONTAINER_RESIZE 64
3700 * Get or create a flow counter.
3703 * Pointer to the Ethernet device structure.
3705 * Indicate if this counter is shared with other flows.
3707 * Counter identifier.
3710 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3712 static struct mlx5_flow_counter *
3713 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3716 struct mlx5_priv *priv = dev->data->dev_private;
3717 struct mlx5_flow_counter *cnt = NULL;
3718 struct mlx5_devx_obj *dcs = NULL;
3720 if (!priv->config.devx) {
3721 rte_errno = ENOTSUP;
3725 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3726 if (cnt->shared && cnt->id == id) {
3732 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3735 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3737 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3741 struct mlx5_flow_counter tmpl = {
3747 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3749 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3755 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3760 * Release a flow counter.
3763 * Pointer to the Ethernet device structure.
3764 * @param[in] counter
3765 * Pointer to the counter handler.
3768 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3769 struct mlx5_flow_counter *counter)
3771 struct mlx5_priv *priv = dev->data->dev_private;
3775 if (--counter->ref_cnt == 0) {
3776 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3777 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3783 * Query a devx flow counter.
3786 * Pointer to the Ethernet device structure.
3788 * Pointer to the flow counter.
3790 * The statistics value of packets.
3792 * The statistics value of bytes.
3795 * 0 on success, otherwise a negative errno value and rte_errno is set.
3798 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3799 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3802 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3807 * Get a pool by a counter.
3810 * Pointer to the counter.
3815 static struct mlx5_flow_counter_pool *
3816 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3819 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3820 return (struct mlx5_flow_counter_pool *)cnt - 1;
3826 * Get a pool by devx counter ID.
3829 * Pointer to the counter container.
3831 * The counter devx ID.
3834 * The counter pool pointer if exists, NULL otherwise,
3836 static struct mlx5_flow_counter_pool *
3837 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3839 struct mlx5_flow_counter_pool *pool;
3841 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3842 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3843 MLX5_COUNTERS_PER_POOL;
3845 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3852 * Allocate a new memory for the counter values wrapped by all the needed
3856 * Pointer to the Ethernet device structure.
3858 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3861 * The new memory management pointer on success, otherwise NULL and rte_errno
3864 static struct mlx5_counter_stats_mem_mng *
3865 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3867 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3868 (dev->data->dev_private))->sh;
3869 struct mlx5_devx_mkey_attr mkey_attr;
3870 struct mlx5_counter_stats_mem_mng *mem_mng;
3871 volatile struct flow_counter_stats *raw_data;
3872 int size = (sizeof(struct flow_counter_stats) *
3873 MLX5_COUNTERS_PER_POOL +
3874 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3875 sizeof(struct mlx5_counter_stats_mem_mng);
3876 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3883 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3884 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3885 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3886 IBV_ACCESS_LOCAL_WRITE);
3887 if (!mem_mng->umem) {
3892 mkey_attr.addr = (uintptr_t)mem;
3893 mkey_attr.size = size;
3894 mkey_attr.umem_id = mem_mng->umem->umem_id;
3895 mkey_attr.pd = sh->pdn;
3896 mkey_attr.log_entity_size = 0;
3897 mkey_attr.pg_access = 0;
3898 mkey_attr.klm_array = NULL;
3899 mkey_attr.klm_num = 0;
3900 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3902 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3907 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3908 raw_data = (volatile struct flow_counter_stats *)mem;
3909 for (i = 0; i < raws_n; ++i) {
3910 mem_mng->raws[i].mem_mng = mem_mng;
3911 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3913 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3918 * Resize a counter container.
3921 * Pointer to the Ethernet device structure.
3923 * Whether the pool is for counter that was allocated by batch command.
3926 * The new container pointer on success, otherwise NULL and rte_errno is set.
3928 static struct mlx5_pools_container *
3929 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3931 struct mlx5_priv *priv = dev->data->dev_private;
3932 struct mlx5_pools_container *cont =
3933 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3934 struct mlx5_pools_container *new_cont =
3935 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3936 struct mlx5_counter_stats_mem_mng *mem_mng;
3937 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3938 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3941 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3942 /* The last resize still hasn't detected by the host thread. */
3946 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3947 if (!new_cont->pools) {
3952 memcpy(new_cont->pools, cont->pools, cont->n *
3953 sizeof(struct mlx5_flow_counter_pool *));
3954 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3955 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3957 rte_free(new_cont->pools);
3960 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3961 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3962 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3964 new_cont->n = resize;
3965 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3966 TAILQ_INIT(&new_cont->pool_list);
3967 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3968 new_cont->init_mem_mng = mem_mng;
3970 /* Flip the master container. */
3971 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3976 * Query a devx flow counter.
3979 * Pointer to the Ethernet device structure.
3981 * Pointer to the flow counter.
3983 * The statistics value of packets.
3985 * The statistics value of bytes.
3988 * 0 on success, otherwise a negative errno value and rte_errno is set.
3991 _flow_dv_query_count(struct rte_eth_dev *dev,
3992 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3995 struct mlx5_priv *priv = dev->data->dev_private;
3996 struct mlx5_flow_counter_pool *pool =
3997 flow_dv_counter_pool_get(cnt);
3998 int offset = cnt - &pool->counters_raw[0];
4000 if (priv->counter_fallback)
4001 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4003 rte_spinlock_lock(&pool->sl);
4005 * The single counters allocation may allocate smaller ID than the
4006 * current allocated in parallel to the host reading.
4007 * In this case the new counter values must be reported as 0.
4009 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4013 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4014 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4016 rte_spinlock_unlock(&pool->sl);
4021 * Create and initialize a new counter pool.
4024 * Pointer to the Ethernet device structure.
4026 * The devX counter handle.
4028 * Whether the pool is for counter that was allocated by batch command.
4031 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4033 static struct mlx5_flow_counter_pool *
4034 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4037 struct mlx5_priv *priv = dev->data->dev_private;
4038 struct mlx5_flow_counter_pool *pool;
4039 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4041 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4044 if (cont->n == n_valid) {
4045 cont = flow_dv_container_resize(dev, batch);
4049 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4050 sizeof(struct mlx5_flow_counter);
4051 pool = rte_calloc(__func__, 1, size, 0);
4056 pool->min_dcs = dcs;
4057 pool->raw = cont->init_mem_mng->raws + n_valid %
4058 MLX5_CNT_CONTAINER_RESIZE;
4059 pool->raw_hw = NULL;
4060 rte_spinlock_init(&pool->sl);
4062 * The generation of the new allocated counters in this pool is 0, 2 in
4063 * the pool generation makes all the counters valid for allocation.
4065 rte_atomic64_set(&pool->query_gen, 0x2);
4066 TAILQ_INIT(&pool->counters);
4067 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4068 cont->pools[n_valid] = pool;
4069 /* Pool initialization must be updated before host thread access. */
4071 rte_atomic16_add(&cont->n_valid, 1);
4076 * Prepare a new counter and/or a new counter pool.
4079 * Pointer to the Ethernet device structure.
4080 * @param[out] cnt_free
4081 * Where to put the pointer of a new counter.
4083 * Whether the pool is for counter that was allocated by batch command.
4086 * The free counter pool pointer and @p cnt_free is set on success,
4087 * NULL otherwise and rte_errno is set.
4089 static struct mlx5_flow_counter_pool *
4090 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4091 struct mlx5_flow_counter **cnt_free,
4094 struct mlx5_priv *priv = dev->data->dev_private;
4095 struct mlx5_flow_counter_pool *pool;
4096 struct mlx5_devx_obj *dcs = NULL;
4097 struct mlx5_flow_counter *cnt;
4101 /* bulk_bitmap must be 0 for single counter allocation. */
4102 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4105 pool = flow_dv_find_pool_by_id
4106 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4108 pool = flow_dv_pool_create(dev, dcs, batch);
4110 mlx5_devx_cmd_destroy(dcs);
4113 } else if (dcs->id < pool->min_dcs->id) {
4114 rte_atomic64_set(&pool->a64_dcs,
4115 (int64_t)(uintptr_t)dcs);
4117 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4118 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4123 /* bulk_bitmap is in 128 counters units. */
4124 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4125 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4127 rte_errno = ENODATA;
4130 pool = flow_dv_pool_create(dev, dcs, batch);
4132 mlx5_devx_cmd_destroy(dcs);
4135 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4136 cnt = &pool->counters_raw[i];
4138 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4140 *cnt_free = &pool->counters_raw[0];
4145 * Search for existed shared counter.
4148 * Pointer to the relevant counter pool container.
4150 * The shared counter ID to search.
4153 * NULL if not existed, otherwise pointer to the shared counter.
4155 static struct mlx5_flow_counter *
4156 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4159 static struct mlx5_flow_counter *cnt;
4160 struct mlx5_flow_counter_pool *pool;
4163 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4164 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4165 cnt = &pool->counters_raw[i];
4166 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4174 * Allocate a flow counter.
4177 * Pointer to the Ethernet device structure.
4179 * Indicate if this counter is shared with other flows.
4181 * Counter identifier.
4183 * Counter flow group.
4186 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4188 static struct mlx5_flow_counter *
4189 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4192 struct mlx5_priv *priv = dev->data->dev_private;
4193 struct mlx5_flow_counter_pool *pool = NULL;
4194 struct mlx5_flow_counter *cnt_free = NULL;
4196 * Currently group 0 flow counter cannot be assigned to a flow if it is
4197 * not the first one in the batch counter allocation, so it is better
4198 * to allocate counters one by one for these flows in a separate
4200 * A counter can be shared between different groups so need to take
4201 * shared counters from the single container.
4203 uint32_t batch = (group && !shared) ? 1 : 0;
4204 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4207 if (priv->counter_fallback)
4208 return flow_dv_counter_alloc_fallback(dev, shared, id);
4209 if (!priv->config.devx) {
4210 rte_errno = ENOTSUP;
4214 cnt_free = flow_dv_counter_shared_search(cont, id);
4216 if (cnt_free->ref_cnt + 1 == 0) {
4220 cnt_free->ref_cnt++;
4224 /* Pools which has a free counters are in the start. */
4225 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4227 * The free counter reset values must be updated between the
4228 * counter release to the counter allocation, so, at least one
4229 * query must be done in this time. ensure it by saving the
4230 * query generation in the release time.
4231 * The free list is sorted according to the generation - so if
4232 * the first one is not updated, all the others are not
4235 cnt_free = TAILQ_FIRST(&pool->counters);
4236 if (cnt_free && cnt_free->query_gen + 1 <
4237 rte_atomic64_read(&pool->query_gen))
4242 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4246 cnt_free->batch = batch;
4247 /* Create a DV counter action only in the first time usage. */
4248 if (!cnt_free->action) {
4250 struct mlx5_devx_obj *dcs;
4253 offset = cnt_free - &pool->counters_raw[0];
4254 dcs = pool->min_dcs;
4257 dcs = cnt_free->dcs;
4259 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4261 if (!cnt_free->action) {
4266 /* Update the counter reset values. */
4267 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4270 cnt_free->shared = shared;
4271 cnt_free->ref_cnt = 1;
4273 if (!priv->sh->cmng.query_thread_on)
4274 /* Start the asynchronous batch query by the host thread. */
4275 mlx5_set_query_alarm(priv->sh);
4276 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4277 if (TAILQ_EMPTY(&pool->counters)) {
4278 /* Move the pool to the end of the container pool list. */
4279 TAILQ_REMOVE(&cont->pool_list, pool, next);
4280 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4286 * Release a flow counter.
4289 * Pointer to the Ethernet device structure.
4290 * @param[in] counter
4291 * Pointer to the counter handler.
4294 flow_dv_counter_release(struct rte_eth_dev *dev,
4295 struct mlx5_flow_counter *counter)
4297 struct mlx5_priv *priv = dev->data->dev_private;
4301 if (priv->counter_fallback) {
4302 flow_dv_counter_release_fallback(dev, counter);
4305 if (--counter->ref_cnt == 0) {
4306 struct mlx5_flow_counter_pool *pool =
4307 flow_dv_counter_pool_get(counter);
4309 /* Put the counter in the end - the last updated one. */
4310 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4311 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4316 * Verify the @p attributes will be correctly understood by the NIC and store
4317 * them in the @p flow if everything is correct.
4320 * Pointer to dev struct.
4321 * @param[in] attributes
4322 * Pointer to flow attributes
4323 * @param[in] external
4324 * This flow rule is created by request external to PMD.
4326 * Pointer to error structure.
4329 * 0 on success, a negative errno value otherwise and rte_errno is set.
4332 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4333 const struct rte_flow_attr *attributes,
4334 bool external __rte_unused,
4335 struct rte_flow_error *error)
4337 struct mlx5_priv *priv = dev->data->dev_private;
4338 uint32_t priority_max = priv->config.flow_prio - 1;
4340 #ifndef HAVE_MLX5DV_DR
4341 if (attributes->group)
4342 return rte_flow_error_set(error, ENOTSUP,
4343 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4345 "groups are not supported");
4350 ret = mlx5_flow_group_to_table(attributes, external,
4351 attributes->group, !!priv->fdb_def_rule,
4356 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4357 attributes->priority >= priority_max)
4358 return rte_flow_error_set(error, ENOTSUP,
4359 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4361 "priority out of range");
4362 if (attributes->transfer) {
4363 if (!priv->config.dv_esw_en)
4364 return rte_flow_error_set
4366 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4367 "E-Switch dr is not supported");
4368 if (!(priv->representor || priv->master))
4369 return rte_flow_error_set
4370 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4371 NULL, "E-Switch configuration can only be"
4372 " done by a master or a representor device");
4373 if (attributes->egress)
4374 return rte_flow_error_set
4376 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4377 "egress is not supported");
4379 if (!(attributes->egress ^ attributes->ingress))
4380 return rte_flow_error_set(error, ENOTSUP,
4381 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4382 "must specify exactly one of "
4383 "ingress or egress");
4388 * Internal validation function. For validating both actions and items.
4391 * Pointer to the rte_eth_dev structure.
4393 * Pointer to the flow attributes.
4395 * Pointer to the list of items.
4396 * @param[in] actions
4397 * Pointer to the list of actions.
4398 * @param[in] external
4399 * This flow rule is created by request external to PMD.
4401 * Pointer to the error structure.
4404 * 0 on success, a negative errno value otherwise and rte_errno is set.
4407 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4408 const struct rte_flow_item items[],
4409 const struct rte_flow_action actions[],
4410 bool external, struct rte_flow_error *error)
4413 uint64_t action_flags = 0;
4414 uint64_t item_flags = 0;
4415 uint64_t last_item = 0;
4416 uint8_t next_protocol = 0xff;
4417 uint16_t ether_type = 0;
4419 uint8_t item_ipv6_proto = 0;
4420 const struct rte_flow_item *gre_item = NULL;
4421 const struct rte_flow_action_raw_decap *decap;
4422 const struct rte_flow_action_raw_encap *encap;
4423 const struct rte_flow_action_rss *rss;
4424 struct rte_flow_item_tcp nic_tcp_mask = {
4427 .src_port = RTE_BE16(UINT16_MAX),
4428 .dst_port = RTE_BE16(UINT16_MAX),
4431 struct mlx5_priv *priv = dev->data->dev_private;
4432 struct mlx5_dev_config *dev_conf = &priv->config;
4433 uint16_t queue_index = 0xFFFF;
4437 ret = flow_dv_validate_attributes(dev, attr, external, error);
4440 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4441 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4442 int type = items->type;
4445 case RTE_FLOW_ITEM_TYPE_VOID:
4447 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4448 ret = flow_dv_validate_item_port_id
4449 (dev, items, attr, item_flags, error);
4452 last_item = MLX5_FLOW_ITEM_PORT_ID;
4454 case RTE_FLOW_ITEM_TYPE_ETH:
4455 ret = mlx5_flow_validate_item_eth(items, item_flags,
4459 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4460 MLX5_FLOW_LAYER_OUTER_L2;
4461 if (items->mask != NULL && items->spec != NULL) {
4463 ((const struct rte_flow_item_eth *)
4466 ((const struct rte_flow_item_eth *)
4468 ether_type = rte_be_to_cpu_16(ether_type);
4473 case RTE_FLOW_ITEM_TYPE_VLAN:
4474 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4478 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4479 MLX5_FLOW_LAYER_OUTER_VLAN;
4480 if (items->mask != NULL && items->spec != NULL) {
4482 ((const struct rte_flow_item_vlan *)
4483 items->spec)->inner_type;
4485 ((const struct rte_flow_item_vlan *)
4486 items->mask)->inner_type;
4487 ether_type = rte_be_to_cpu_16(ether_type);
4492 case RTE_FLOW_ITEM_TYPE_IPV4:
4493 mlx5_flow_tunnel_ip_check(items, next_protocol,
4494 &item_flags, &tunnel);
4495 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4501 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4502 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4503 if (items->mask != NULL &&
4504 ((const struct rte_flow_item_ipv4 *)
4505 items->mask)->hdr.next_proto_id) {
4507 ((const struct rte_flow_item_ipv4 *)
4508 (items->spec))->hdr.next_proto_id;
4510 ((const struct rte_flow_item_ipv4 *)
4511 (items->mask))->hdr.next_proto_id;
4513 /* Reset for inner layer. */
4514 next_protocol = 0xff;
4517 case RTE_FLOW_ITEM_TYPE_IPV6:
4518 mlx5_flow_tunnel_ip_check(items, next_protocol,
4519 &item_flags, &tunnel);
4520 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4526 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4527 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4528 if (items->mask != NULL &&
4529 ((const struct rte_flow_item_ipv6 *)
4530 items->mask)->hdr.proto) {
4532 ((const struct rte_flow_item_ipv6 *)
4533 items->spec)->hdr.proto;
4535 ((const struct rte_flow_item_ipv6 *)
4536 items->spec)->hdr.proto;
4538 ((const struct rte_flow_item_ipv6 *)
4539 items->mask)->hdr.proto;
4541 /* Reset for inner layer. */
4542 next_protocol = 0xff;
4545 case RTE_FLOW_ITEM_TYPE_TCP:
4546 ret = mlx5_flow_validate_item_tcp
4553 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4554 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4556 case RTE_FLOW_ITEM_TYPE_UDP:
4557 ret = mlx5_flow_validate_item_udp(items, item_flags,
4562 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4563 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4565 case RTE_FLOW_ITEM_TYPE_GRE:
4566 ret = mlx5_flow_validate_item_gre(items, item_flags,
4567 next_protocol, error);
4571 last_item = MLX5_FLOW_LAYER_GRE;
4573 case RTE_FLOW_ITEM_TYPE_NVGRE:
4574 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4579 last_item = MLX5_FLOW_LAYER_NVGRE;
4581 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4582 ret = mlx5_flow_validate_item_gre_key
4583 (items, item_flags, gre_item, error);
4586 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4588 case RTE_FLOW_ITEM_TYPE_VXLAN:
4589 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4593 last_item = MLX5_FLOW_LAYER_VXLAN;
4595 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4596 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4601 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4603 case RTE_FLOW_ITEM_TYPE_GENEVE:
4604 ret = mlx5_flow_validate_item_geneve(items,
4609 last_item = MLX5_FLOW_LAYER_GENEVE;
4611 case RTE_FLOW_ITEM_TYPE_MPLS:
4612 ret = mlx5_flow_validate_item_mpls(dev, items,
4617 last_item = MLX5_FLOW_LAYER_MPLS;
4620 case RTE_FLOW_ITEM_TYPE_MARK:
4621 ret = flow_dv_validate_item_mark(dev, items, attr,
4625 last_item = MLX5_FLOW_ITEM_MARK;
4627 case RTE_FLOW_ITEM_TYPE_META:
4628 ret = flow_dv_validate_item_meta(dev, items, attr,
4632 last_item = MLX5_FLOW_ITEM_METADATA;
4634 case RTE_FLOW_ITEM_TYPE_ICMP:
4635 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4640 last_item = MLX5_FLOW_LAYER_ICMP;
4642 case RTE_FLOW_ITEM_TYPE_ICMP6:
4643 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4648 item_ipv6_proto = IPPROTO_ICMPV6;
4649 last_item = MLX5_FLOW_LAYER_ICMP6;
4651 case RTE_FLOW_ITEM_TYPE_TAG:
4652 ret = flow_dv_validate_item_tag(dev, items,
4656 last_item = MLX5_FLOW_ITEM_TAG;
4658 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4659 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4661 case RTE_FLOW_ITEM_TYPE_GTP:
4662 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4666 last_item = MLX5_FLOW_LAYER_GTP;
4669 return rte_flow_error_set(error, ENOTSUP,
4670 RTE_FLOW_ERROR_TYPE_ITEM,
4671 NULL, "item not supported");
4673 item_flags |= last_item;
4675 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4676 int type = actions->type;
4677 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4678 return rte_flow_error_set(error, ENOTSUP,
4679 RTE_FLOW_ERROR_TYPE_ACTION,
4680 actions, "too many actions");
4682 case RTE_FLOW_ACTION_TYPE_VOID:
4684 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4685 ret = flow_dv_validate_action_port_id(dev,
4692 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4695 case RTE_FLOW_ACTION_TYPE_FLAG:
4696 ret = flow_dv_validate_action_flag(dev, action_flags,
4700 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4701 /* Count all modify-header actions as one. */
4702 if (!(action_flags &
4703 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4705 action_flags |= MLX5_FLOW_ACTION_FLAG |
4706 MLX5_FLOW_ACTION_MARK_EXT;
4708 action_flags |= MLX5_FLOW_ACTION_FLAG;
4712 case RTE_FLOW_ACTION_TYPE_MARK:
4713 ret = flow_dv_validate_action_mark(dev, actions,
4718 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4719 /* Count all modify-header actions as one. */
4720 if (!(action_flags &
4721 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4723 action_flags |= MLX5_FLOW_ACTION_MARK |
4724 MLX5_FLOW_ACTION_MARK_EXT;
4726 action_flags |= MLX5_FLOW_ACTION_MARK;
4730 case RTE_FLOW_ACTION_TYPE_SET_META:
4731 ret = flow_dv_validate_action_set_meta(dev, actions,
4736 /* Count all modify-header actions as one action. */
4737 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4739 action_flags |= MLX5_FLOW_ACTION_SET_META;
4741 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4742 ret = flow_dv_validate_action_set_tag(dev, actions,
4747 /* Count all modify-header actions as one action. */
4748 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4750 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4752 case RTE_FLOW_ACTION_TYPE_DROP:
4753 ret = mlx5_flow_validate_action_drop(action_flags,
4757 action_flags |= MLX5_FLOW_ACTION_DROP;
4760 case RTE_FLOW_ACTION_TYPE_QUEUE:
4761 ret = mlx5_flow_validate_action_queue(actions,
4766 queue_index = ((const struct rte_flow_action_queue *)
4767 (actions->conf))->index;
4768 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4771 case RTE_FLOW_ACTION_TYPE_RSS:
4772 rss = actions->conf;
4773 ret = mlx5_flow_validate_action_rss(actions,
4779 if (rss != NULL && rss->queue_num)
4780 queue_index = rss->queue[0];
4781 action_flags |= MLX5_FLOW_ACTION_RSS;
4784 case RTE_FLOW_ACTION_TYPE_COUNT:
4785 ret = flow_dv_validate_action_count(dev, error);
4788 action_flags |= MLX5_FLOW_ACTION_COUNT;
4791 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4792 if (flow_dv_validate_action_pop_vlan(dev,
4798 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4801 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4802 ret = flow_dv_validate_action_push_vlan(action_flags,
4808 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4811 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4812 ret = flow_dv_validate_action_set_vlan_pcp
4813 (action_flags, actions, error);
4816 /* Count PCP with push_vlan command. */
4817 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4819 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4820 ret = flow_dv_validate_action_set_vlan_vid
4821 (item_flags, action_flags,
4825 /* Count VID with push_vlan command. */
4826 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4828 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4829 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4830 ret = flow_dv_validate_action_l2_encap(action_flags,
4834 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4837 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4838 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4839 ret = flow_dv_validate_action_decap(action_flags, attr,
4843 action_flags |= MLX5_FLOW_ACTION_DECAP;
4846 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4847 ret = flow_dv_validate_action_raw_encap_decap
4848 (NULL, actions->conf, attr, &action_flags,
4853 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4854 decap = actions->conf;
4855 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
4857 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4861 encap = actions->conf;
4863 ret = flow_dv_validate_action_raw_encap_decap
4864 (decap ? decap : &empty_decap, encap,
4865 attr, &action_flags, &actions_n,
4870 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4871 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4872 ret = flow_dv_validate_action_modify_mac(action_flags,
4878 /* Count all modify-header actions as one action. */
4879 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4881 action_flags |= actions->type ==
4882 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4883 MLX5_FLOW_ACTION_SET_MAC_SRC :
4884 MLX5_FLOW_ACTION_SET_MAC_DST;
4887 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4888 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4889 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4895 /* Count all modify-header actions as one action. */
4896 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4898 action_flags |= actions->type ==
4899 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4900 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4901 MLX5_FLOW_ACTION_SET_IPV4_DST;
4903 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4904 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4905 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4911 if (item_ipv6_proto == IPPROTO_ICMPV6)
4912 return rte_flow_error_set(error, ENOTSUP,
4913 RTE_FLOW_ERROR_TYPE_ACTION,
4915 "Can't change header "
4916 "with ICMPv6 proto");
4917 /* Count all modify-header actions as one action. */
4918 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4920 action_flags |= actions->type ==
4921 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4922 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4923 MLX5_FLOW_ACTION_SET_IPV6_DST;
4925 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4926 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4927 ret = flow_dv_validate_action_modify_tp(action_flags,
4933 /* Count all modify-header actions as one action. */
4934 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4936 action_flags |= actions->type ==
4937 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4938 MLX5_FLOW_ACTION_SET_TP_SRC :
4939 MLX5_FLOW_ACTION_SET_TP_DST;
4941 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4942 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4943 ret = flow_dv_validate_action_modify_ttl(action_flags,
4949 /* Count all modify-header actions as one action. */
4950 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4952 action_flags |= actions->type ==
4953 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4954 MLX5_FLOW_ACTION_SET_TTL :
4955 MLX5_FLOW_ACTION_DEC_TTL;
4957 case RTE_FLOW_ACTION_TYPE_JUMP:
4958 ret = flow_dv_validate_action_jump(actions,
4965 action_flags |= MLX5_FLOW_ACTION_JUMP;
4967 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4968 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4969 ret = flow_dv_validate_action_modify_tcp_seq
4976 /* Count all modify-header actions as one action. */
4977 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4979 action_flags |= actions->type ==
4980 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4981 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4982 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4984 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4985 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4986 ret = flow_dv_validate_action_modify_tcp_ack
4993 /* Count all modify-header actions as one action. */
4994 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4996 action_flags |= actions->type ==
4997 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4998 MLX5_FLOW_ACTION_INC_TCP_ACK :
4999 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5001 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5002 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5003 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5005 case RTE_FLOW_ACTION_TYPE_METER:
5006 ret = mlx5_flow_validate_action_meter(dev,
5012 action_flags |= MLX5_FLOW_ACTION_METER;
5015 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5016 ret = flow_dv_validate_action_modify_ipv4_dscp
5023 /* Count all modify-header actions as one action. */
5024 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5026 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5028 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5029 ret = flow_dv_validate_action_modify_ipv6_dscp
5036 /* Count all modify-header actions as one action. */
5037 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5039 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5042 return rte_flow_error_set(error, ENOTSUP,
5043 RTE_FLOW_ERROR_TYPE_ACTION,
5045 "action not supported");
5049 * Validate the drop action mutual exclusion with other actions.
5050 * Drop action is mutually-exclusive with any other action, except for
5053 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5054 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5055 return rte_flow_error_set(error, EINVAL,
5056 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5057 "Drop action is mutually-exclusive "
5058 "with any other action, except for "
5060 /* Eswitch has few restrictions on using items and actions */
5061 if (attr->transfer) {
5062 if (!mlx5_flow_ext_mreg_supported(dev) &&
5063 action_flags & MLX5_FLOW_ACTION_FLAG)
5064 return rte_flow_error_set(error, ENOTSUP,
5065 RTE_FLOW_ERROR_TYPE_ACTION,
5067 "unsupported action FLAG");
5068 if (!mlx5_flow_ext_mreg_supported(dev) &&
5069 action_flags & MLX5_FLOW_ACTION_MARK)
5070 return rte_flow_error_set(error, ENOTSUP,
5071 RTE_FLOW_ERROR_TYPE_ACTION,
5073 "unsupported action MARK");
5074 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5075 return rte_flow_error_set(error, ENOTSUP,
5076 RTE_FLOW_ERROR_TYPE_ACTION,
5078 "unsupported action QUEUE");
5079 if (action_flags & MLX5_FLOW_ACTION_RSS)
5080 return rte_flow_error_set(error, ENOTSUP,
5081 RTE_FLOW_ERROR_TYPE_ACTION,
5083 "unsupported action RSS");
5084 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5085 return rte_flow_error_set(error, EINVAL,
5086 RTE_FLOW_ERROR_TYPE_ACTION,
5088 "no fate action is found");
5090 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5091 return rte_flow_error_set(error, EINVAL,
5092 RTE_FLOW_ERROR_TYPE_ACTION,
5094 "no fate action is found");
5096 /* Continue validation for Xcap actions.*/
5097 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5098 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5099 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5100 MLX5_FLOW_XCAP_ACTIONS)
5101 return rte_flow_error_set(error, ENOTSUP,
5102 RTE_FLOW_ERROR_TYPE_ACTION,
5103 NULL, "encap and decap "
5104 "combination aren't supported");
5105 if (!attr->transfer && attr->ingress && (action_flags &
5106 MLX5_FLOW_ACTION_ENCAP))
5107 return rte_flow_error_set(error, ENOTSUP,
5108 RTE_FLOW_ERROR_TYPE_ACTION,
5109 NULL, "encap is not supported"
5110 " for ingress traffic");
5116 * Internal preparation function. Allocates the DV flow size,
5117 * this size is constant.
5120 * Pointer to the flow attributes.
5122 * Pointer to the list of items.
5123 * @param[in] actions
5124 * Pointer to the list of actions.
5126 * Pointer to the error structure.
5129 * Pointer to mlx5_flow object on success,
5130 * otherwise NULL and rte_errno is set.
5132 static struct mlx5_flow *
5133 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5134 const struct rte_flow_item items[] __rte_unused,
5135 const struct rte_flow_action actions[] __rte_unused,
5136 struct rte_flow_error *error)
5138 size_t size = sizeof(struct mlx5_flow);
5139 struct mlx5_flow *dev_flow;
5141 dev_flow = rte_calloc(__func__, 1, size, 0);
5143 rte_flow_error_set(error, ENOMEM,
5144 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5145 "not enough memory to create flow");
5148 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5149 dev_flow->ingress = attr->ingress;
5150 dev_flow->transfer = attr->transfer;
5154 #ifdef RTE_LIBRTE_MLX5_DEBUG
5156 * Sanity check for match mask and value. Similar to check_valid_spec() in
5157 * kernel driver. If unmasked bit is present in value, it returns failure.
5160 * pointer to match mask buffer.
5161 * @param match_value
5162 * pointer to match value buffer.
5165 * 0 if valid, -EINVAL otherwise.
5168 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5170 uint8_t *m = match_mask;
5171 uint8_t *v = match_value;
5174 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5177 "match_value differs from match_criteria"
5178 " %p[%u] != %p[%u]",
5179 match_value, i, match_mask, i);
5188 * Add Ethernet item to matcher and to the value.
5190 * @param[in, out] matcher
5192 * @param[in, out] key
5193 * Flow matcher value.
5195 * Flow pattern to translate.
5197 * Item is inner pattern.
5200 flow_dv_translate_item_eth(void *matcher, void *key,
5201 const struct rte_flow_item *item, int inner)
5203 const struct rte_flow_item_eth *eth_m = item->mask;
5204 const struct rte_flow_item_eth *eth_v = item->spec;
5205 const struct rte_flow_item_eth nic_mask = {
5206 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5207 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5208 .type = RTE_BE16(0xffff),
5220 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5222 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5224 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5226 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5228 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5229 ð_m->dst, sizeof(eth_m->dst));
5230 /* The value must be in the range of the mask. */
5231 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5232 for (i = 0; i < sizeof(eth_m->dst); ++i)
5233 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5234 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5235 ð_m->src, sizeof(eth_m->src));
5236 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5237 /* The value must be in the range of the mask. */
5238 for (i = 0; i < sizeof(eth_m->dst); ++i)
5239 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5240 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5241 rte_be_to_cpu_16(eth_m->type));
5242 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5243 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5245 /* When ethertype is present set mask for tagged VLAN. */
5246 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5247 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5248 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5249 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ))
5250 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5256 * Add VLAN item to matcher and to the value.
5258 * @param[in, out] dev_flow
5260 * @param[in, out] matcher
5262 * @param[in, out] key
5263 * Flow matcher value.
5265 * Flow pattern to translate.
5267 * Item is inner pattern.
5270 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5271 void *matcher, void *key,
5272 const struct rte_flow_item *item,
5275 const struct rte_flow_item_vlan *vlan_m = item->mask;
5276 const struct rte_flow_item_vlan *vlan_v = item->spec;
5285 vlan_m = &rte_flow_item_vlan_mask;
5287 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5289 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5291 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5293 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5295 * This is workaround, masks are not supported,
5296 * and pre-validated.
5298 dev_flow->dv.vf_vlan.tag =
5299 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5301 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5302 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5303 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5304 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5305 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5306 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5307 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5308 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5309 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5310 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5311 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5312 rte_be_to_cpu_16(vlan_m->inner_type));
5313 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5314 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5318 * Add IPV4 item to matcher and to the value.
5320 * @param[in, out] matcher
5322 * @param[in, out] key
5323 * Flow matcher value.
5325 * Flow pattern to translate.
5327 * Item is inner pattern.
5329 * The group to insert the rule.
5332 flow_dv_translate_item_ipv4(void *matcher, void *key,
5333 const struct rte_flow_item *item,
5334 int inner, uint32_t group)
5336 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5337 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5338 const struct rte_flow_item_ipv4 nic_mask = {
5340 .src_addr = RTE_BE32(0xffffffff),
5341 .dst_addr = RTE_BE32(0xffffffff),
5342 .type_of_service = 0xff,
5343 .next_proto_id = 0xff,
5353 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5355 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5357 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5359 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5362 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5364 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5365 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5370 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5371 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5372 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5373 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5374 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5375 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5376 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5377 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5378 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5379 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5380 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5381 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5382 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5383 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5384 ipv4_m->hdr.type_of_service);
5385 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5386 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5387 ipv4_m->hdr.type_of_service >> 2);
5388 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5389 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5390 ipv4_m->hdr.next_proto_id);
5391 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5392 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5393 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5397 * Add IPV6 item to matcher and to the value.
5399 * @param[in, out] matcher
5401 * @param[in, out] key
5402 * Flow matcher value.
5404 * Flow pattern to translate.
5406 * Item is inner pattern.
5408 * The group to insert the rule.
5411 flow_dv_translate_item_ipv6(void *matcher, void *key,
5412 const struct rte_flow_item *item,
5413 int inner, uint32_t group)
5415 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5416 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5417 const struct rte_flow_item_ipv6 nic_mask = {
5420 "\xff\xff\xff\xff\xff\xff\xff\xff"
5421 "\xff\xff\xff\xff\xff\xff\xff\xff",
5423 "\xff\xff\xff\xff\xff\xff\xff\xff"
5424 "\xff\xff\xff\xff\xff\xff\xff\xff",
5425 .vtc_flow = RTE_BE32(0xffffffff),
5432 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5433 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5442 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5444 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5446 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5448 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5451 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5453 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5454 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5459 size = sizeof(ipv6_m->hdr.dst_addr);
5460 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5461 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5462 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5463 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5464 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5465 for (i = 0; i < size; ++i)
5466 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5467 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5468 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5469 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5470 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5471 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5472 for (i = 0; i < size; ++i)
5473 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5475 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5476 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5477 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5478 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5479 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5480 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5483 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5485 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5488 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5490 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5497 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5498 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5502 * Add TCP item to matcher and to the value.
5504 * @param[in, out] matcher
5506 * @param[in, out] key
5507 * Flow matcher value.
5509 * Flow pattern to translate.
5511 * Item is inner pattern.
5514 flow_dv_translate_item_tcp(void *matcher, void *key,
5515 const struct rte_flow_item *item,
5518 const struct rte_flow_item_tcp *tcp_m = item->mask;
5519 const struct rte_flow_item_tcp *tcp_v = item->spec;
5524 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5526 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5528 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5530 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5532 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5533 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5537 tcp_m = &rte_flow_item_tcp_mask;
5538 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5539 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5540 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5541 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5542 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5543 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5544 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5545 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5546 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5547 tcp_m->hdr.tcp_flags);
5548 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5549 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5553 * Add UDP item to matcher and to the value.
5555 * @param[in, out] matcher
5557 * @param[in, out] key
5558 * Flow matcher value.
5560 * Flow pattern to translate.
5562 * Item is inner pattern.
5565 flow_dv_translate_item_udp(void *matcher, void *key,
5566 const struct rte_flow_item *item,
5569 const struct rte_flow_item_udp *udp_m = item->mask;
5570 const struct rte_flow_item_udp *udp_v = item->spec;
5575 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5577 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5579 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5581 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5583 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5584 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5588 udp_m = &rte_flow_item_udp_mask;
5589 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5590 rte_be_to_cpu_16(udp_m->hdr.src_port));
5591 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5592 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5593 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5594 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5595 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5596 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5600 * Add GRE optional Key item to matcher and to the value.
5602 * @param[in, out] matcher
5604 * @param[in, out] key
5605 * Flow matcher value.
5607 * Flow pattern to translate.
5609 * Item is inner pattern.
5612 flow_dv_translate_item_gre_key(void *matcher, void *key,
5613 const struct rte_flow_item *item)
5615 const rte_be32_t *key_m = item->mask;
5616 const rte_be32_t *key_v = item->spec;
5617 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5618 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5619 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5621 /* GRE K bit must be on and should already be validated */
5622 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5623 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5627 key_m = &gre_key_default_mask;
5628 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5629 rte_be_to_cpu_32(*key_m) >> 8);
5630 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5631 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5632 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5633 rte_be_to_cpu_32(*key_m) & 0xFF);
5634 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5635 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5639 * Add GRE item to matcher and to the value.
5641 * @param[in, out] matcher
5643 * @param[in, out] key
5644 * Flow matcher value.
5646 * Flow pattern to translate.
5648 * Item is inner pattern.
5651 flow_dv_translate_item_gre(void *matcher, void *key,
5652 const struct rte_flow_item *item,
5655 const struct rte_flow_item_gre *gre_m = item->mask;
5656 const struct rte_flow_item_gre *gre_v = item->spec;
5659 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5660 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5667 uint16_t s_present:1;
5668 uint16_t k_present:1;
5669 uint16_t rsvd_bit1:1;
5670 uint16_t c_present:1;
5674 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5677 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5679 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5681 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5683 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5685 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5686 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5690 gre_m = &rte_flow_item_gre_mask;
5691 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5692 rte_be_to_cpu_16(gre_m->protocol));
5693 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5694 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5695 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5696 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5697 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5698 gre_crks_rsvd0_ver_m.c_present);
5699 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5700 gre_crks_rsvd0_ver_v.c_present &
5701 gre_crks_rsvd0_ver_m.c_present);
5702 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5703 gre_crks_rsvd0_ver_m.k_present);
5704 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5705 gre_crks_rsvd0_ver_v.k_present &
5706 gre_crks_rsvd0_ver_m.k_present);
5707 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5708 gre_crks_rsvd0_ver_m.s_present);
5709 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5710 gre_crks_rsvd0_ver_v.s_present &
5711 gre_crks_rsvd0_ver_m.s_present);
5715 * Add NVGRE item to matcher and to the value.
5717 * @param[in, out] matcher
5719 * @param[in, out] key
5720 * Flow matcher value.
5722 * Flow pattern to translate.
5724 * Item is inner pattern.
5727 flow_dv_translate_item_nvgre(void *matcher, void *key,
5728 const struct rte_flow_item *item,
5731 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5732 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5733 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5734 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5735 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5736 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5742 /* For NVGRE, GRE header fields must be set with defined values. */
5743 const struct rte_flow_item_gre gre_spec = {
5744 .c_rsvd0_ver = RTE_BE16(0x2000),
5745 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5747 const struct rte_flow_item_gre gre_mask = {
5748 .c_rsvd0_ver = RTE_BE16(0xB000),
5749 .protocol = RTE_BE16(UINT16_MAX),
5751 const struct rte_flow_item gre_item = {
5756 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5760 nvgre_m = &rte_flow_item_nvgre_mask;
5761 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5762 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5763 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5764 memcpy(gre_key_m, tni_flow_id_m, size);
5765 for (i = 0; i < size; ++i)
5766 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5770 * Add VXLAN item to matcher and to the value.
5772 * @param[in, out] matcher
5774 * @param[in, out] key
5775 * Flow matcher value.
5777 * Flow pattern to translate.
5779 * Item is inner pattern.
5782 flow_dv_translate_item_vxlan(void *matcher, void *key,
5783 const struct rte_flow_item *item,
5786 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5787 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5790 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5791 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5799 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5801 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5803 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5805 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5807 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5808 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5809 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5810 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5811 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5816 vxlan_m = &rte_flow_item_vxlan_mask;
5817 size = sizeof(vxlan_m->vni);
5818 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5819 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5820 memcpy(vni_m, vxlan_m->vni, size);
5821 for (i = 0; i < size; ++i)
5822 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5826 * Add VXLAN-GPE item to matcher and to the value.
5828 * @param[in, out] matcher
5830 * @param[in, out] key
5831 * Flow matcher value.
5833 * Flow pattern to translate.
5835 * Item is inner pattern.
5839 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
5840 const struct rte_flow_item *item, int inner)
5842 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
5843 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
5847 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
5849 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5855 uint8_t flags_m = 0xff;
5856 uint8_t flags_v = 0xc;
5859 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5861 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5863 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5865 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5867 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5868 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5869 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5870 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5871 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5876 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
5877 size = sizeof(vxlan_m->vni);
5878 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
5879 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
5880 memcpy(vni_m, vxlan_m->vni, size);
5881 for (i = 0; i < size; ++i)
5882 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5883 if (vxlan_m->flags) {
5884 flags_m = vxlan_m->flags;
5885 flags_v = vxlan_v->flags;
5887 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
5888 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
5889 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
5891 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
5896 * Add Geneve item to matcher and to the value.
5898 * @param[in, out] matcher
5900 * @param[in, out] key
5901 * Flow matcher value.
5903 * Flow pattern to translate.
5905 * Item is inner pattern.
5909 flow_dv_translate_item_geneve(void *matcher, void *key,
5910 const struct rte_flow_item *item, int inner)
5912 const struct rte_flow_item_geneve *geneve_m = item->mask;
5913 const struct rte_flow_item_geneve *geneve_v = item->spec;
5916 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5917 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5926 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5928 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5930 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5932 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5934 dport = MLX5_UDP_PORT_GENEVE;
5935 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5936 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5937 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5942 geneve_m = &rte_flow_item_geneve_mask;
5943 size = sizeof(geneve_m->vni);
5944 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5945 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5946 memcpy(vni_m, geneve_m->vni, size);
5947 for (i = 0; i < size; ++i)
5948 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5949 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5950 rte_be_to_cpu_16(geneve_m->protocol));
5951 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5952 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5953 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5954 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5955 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5956 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5957 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5958 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5959 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5960 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5961 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5962 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5963 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5967 * Add MPLS item to matcher and to the value.
5969 * @param[in, out] matcher
5971 * @param[in, out] key
5972 * Flow matcher value.
5974 * Flow pattern to translate.
5975 * @param[in] prev_layer
5976 * The protocol layer indicated in previous item.
5978 * Item is inner pattern.
5981 flow_dv_translate_item_mpls(void *matcher, void *key,
5982 const struct rte_flow_item *item,
5983 uint64_t prev_layer,
5986 const uint32_t *in_mpls_m = item->mask;
5987 const uint32_t *in_mpls_v = item->spec;
5988 uint32_t *out_mpls_m = 0;
5989 uint32_t *out_mpls_v = 0;
5990 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5991 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5992 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5994 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5995 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5996 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5998 switch (prev_layer) {
5999 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6000 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6001 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6002 MLX5_UDP_PORT_MPLS);
6004 case MLX5_FLOW_LAYER_GRE:
6005 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6006 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6007 RTE_ETHER_TYPE_MPLS);
6010 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6011 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6018 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6019 switch (prev_layer) {
6020 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6022 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6023 outer_first_mpls_over_udp);
6025 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6026 outer_first_mpls_over_udp);
6028 case MLX5_FLOW_LAYER_GRE:
6030 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6031 outer_first_mpls_over_gre);
6033 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6034 outer_first_mpls_over_gre);
6037 /* Inner MPLS not over GRE is not supported. */
6040 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6044 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6050 if (out_mpls_m && out_mpls_v) {
6051 *out_mpls_m = *in_mpls_m;
6052 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6057 * Add metadata register item to matcher
6059 * @param[in, out] matcher
6061 * @param[in, out] key
6062 * Flow matcher value.
6063 * @param[in] reg_type
6064 * Type of device metadata register
6071 flow_dv_match_meta_reg(void *matcher, void *key,
6072 enum modify_reg reg_type,
6073 uint32_t data, uint32_t mask)
6076 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6078 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6084 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6085 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6088 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6089 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6093 * The metadata register C0 field might be divided into
6094 * source vport index and META item value, we should set
6095 * this field according to specified mask, not as whole one.
6097 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6099 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6100 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6103 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6106 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6107 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6110 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6111 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6114 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6115 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6118 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6119 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6122 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6123 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6126 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6127 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6130 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6131 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6140 * Add MARK item to matcher
6143 * The device to configure through.
6144 * @param[in, out] matcher
6146 * @param[in, out] key
6147 * Flow matcher value.
6149 * Flow pattern to translate.
6152 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6153 void *matcher, void *key,
6154 const struct rte_flow_item *item)
6156 struct mlx5_priv *priv = dev->data->dev_private;
6157 const struct rte_flow_item_mark *mark;
6161 mark = item->mask ? (const void *)item->mask :
6162 &rte_flow_item_mark_mask;
6163 mask = mark->id & priv->sh->dv_mark_mask;
6164 mark = (const void *)item->spec;
6166 value = mark->id & priv->sh->dv_mark_mask & mask;
6168 enum modify_reg reg;
6170 /* Get the metadata register index for the mark. */
6171 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6172 MLX5_ASSERT(reg > 0);
6173 if (reg == REG_C_0) {
6174 struct mlx5_priv *priv = dev->data->dev_private;
6175 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6176 uint32_t shl_c0 = rte_bsf32(msk_c0);
6182 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6187 * Add META item to matcher
6190 * The devich to configure through.
6191 * @param[in, out] matcher
6193 * @param[in, out] key
6194 * Flow matcher value.
6196 * Attributes of flow that includes this item.
6198 * Flow pattern to translate.
6201 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6202 void *matcher, void *key,
6203 const struct rte_flow_attr *attr,
6204 const struct rte_flow_item *item)
6206 const struct rte_flow_item_meta *meta_m;
6207 const struct rte_flow_item_meta *meta_v;
6209 meta_m = (const void *)item->mask;
6211 meta_m = &rte_flow_item_meta_mask;
6212 meta_v = (const void *)item->spec;
6215 uint32_t value = meta_v->data;
6216 uint32_t mask = meta_m->data;
6218 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6222 * In datapath code there is no endianness
6223 * coversions for perfromance reasons, all
6224 * pattern conversions are done in rte_flow.
6226 value = rte_cpu_to_be_32(value);
6227 mask = rte_cpu_to_be_32(mask);
6228 if (reg == REG_C_0) {
6229 struct mlx5_priv *priv = dev->data->dev_private;
6230 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6231 uint32_t shl_c0 = rte_bsf32(msk_c0);
6232 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6233 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6240 MLX5_ASSERT(msk_c0);
6241 MLX5_ASSERT(!(~msk_c0 & mask));
6243 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6248 * Add vport metadata Reg C0 item to matcher
6250 * @param[in, out] matcher
6252 * @param[in, out] key
6253 * Flow matcher value.
6255 * Flow pattern to translate.
6258 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6259 uint32_t value, uint32_t mask)
6261 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6265 * Add tag item to matcher
6268 * The devich to configure through.
6269 * @param[in, out] matcher
6271 * @param[in, out] key
6272 * Flow matcher value.
6274 * Flow pattern to translate.
6277 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6278 void *matcher, void *key,
6279 const struct rte_flow_item *item)
6281 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6282 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6283 uint32_t mask, value;
6286 value = tag_v->data;
6287 mask = tag_m ? tag_m->data : UINT32_MAX;
6288 if (tag_v->id == REG_C_0) {
6289 struct mlx5_priv *priv = dev->data->dev_private;
6290 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6291 uint32_t shl_c0 = rte_bsf32(msk_c0);
6297 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6301 * Add TAG item to matcher
6304 * The devich to configure through.
6305 * @param[in, out] matcher
6307 * @param[in, out] key
6308 * Flow matcher value.
6310 * Flow pattern to translate.
6313 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6314 void *matcher, void *key,
6315 const struct rte_flow_item *item)
6317 const struct rte_flow_item_tag *tag_v = item->spec;
6318 const struct rte_flow_item_tag *tag_m = item->mask;
6319 enum modify_reg reg;
6322 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6323 /* Get the metadata register index for the tag. */
6324 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6325 MLX5_ASSERT(reg > 0);
6326 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6330 * Add source vport match to the specified matcher.
6332 * @param[in, out] matcher
6334 * @param[in, out] key
6335 * Flow matcher value.
6337 * Source vport value to match
6342 flow_dv_translate_item_source_vport(void *matcher, void *key,
6343 int16_t port, uint16_t mask)
6345 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6346 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6348 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6349 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6353 * Translate port-id item to eswitch match on port-id.
6356 * The devich to configure through.
6357 * @param[in, out] matcher
6359 * @param[in, out] key
6360 * Flow matcher value.
6362 * Flow pattern to translate.
6365 * 0 on success, a negative errno value otherwise.
6368 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6369 void *key, const struct rte_flow_item *item)
6371 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6372 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6373 struct mlx5_priv *priv;
6376 mask = pid_m ? pid_m->id : 0xffff;
6377 id = pid_v ? pid_v->id : dev->data->port_id;
6378 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6381 /* Translate to vport field or to metadata, depending on mode. */
6382 if (priv->vport_meta_mask)
6383 flow_dv_translate_item_meta_vport(matcher, key,
6384 priv->vport_meta_tag,
6385 priv->vport_meta_mask);
6387 flow_dv_translate_item_source_vport(matcher, key,
6388 priv->vport_id, mask);
6393 * Add ICMP6 item to matcher and to the value.
6395 * @param[in, out] matcher
6397 * @param[in, out] key
6398 * Flow matcher value.
6400 * Flow pattern to translate.
6402 * Item is inner pattern.
6405 flow_dv_translate_item_icmp6(void *matcher, void *key,
6406 const struct rte_flow_item *item,
6409 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6410 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6413 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6415 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6417 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6419 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6421 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6423 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6425 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6426 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6430 icmp6_m = &rte_flow_item_icmp6_mask;
6432 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6433 * If only the protocol is specified, no need to match the frag.
6435 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6436 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6437 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6438 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6439 icmp6_v->type & icmp6_m->type);
6440 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6441 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6442 icmp6_v->code & icmp6_m->code);
6446 * Add ICMP item to matcher and to the value.
6448 * @param[in, out] matcher
6450 * @param[in, out] key
6451 * Flow matcher value.
6453 * Flow pattern to translate.
6455 * Item is inner pattern.
6458 flow_dv_translate_item_icmp(void *matcher, void *key,
6459 const struct rte_flow_item *item,
6462 const struct rte_flow_item_icmp *icmp_m = item->mask;
6463 const struct rte_flow_item_icmp *icmp_v = item->spec;
6466 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6468 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6470 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6472 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6474 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6476 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6478 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6479 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6483 icmp_m = &rte_flow_item_icmp_mask;
6485 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6486 * If only the protocol is specified, no need to match the frag.
6488 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6490 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6491 icmp_m->hdr.icmp_type);
6492 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6493 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6494 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6495 icmp_m->hdr.icmp_code);
6496 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6497 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6501 * Add GTP item to matcher and to the value.
6503 * @param[in, out] matcher
6505 * @param[in, out] key
6506 * Flow matcher value.
6508 * Flow pattern to translate.
6510 * Item is inner pattern.
6513 flow_dv_translate_item_gtp(void *matcher, void *key,
6514 const struct rte_flow_item *item, int inner)
6516 const struct rte_flow_item_gtp *gtp_m = item->mask;
6517 const struct rte_flow_item_gtp *gtp_v = item->spec;
6520 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6522 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6523 uint16_t dport = RTE_GTPU_UDP_PORT;
6526 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6528 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6530 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6532 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6534 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6535 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6536 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6541 gtp_m = &rte_flow_item_gtp_mask;
6542 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6543 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6544 gtp_v->msg_type & gtp_m->msg_type);
6545 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6546 rte_be_to_cpu_32(gtp_m->teid));
6547 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6548 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6551 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6553 #define HEADER_IS_ZERO(match_criteria, headers) \
6554 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6555 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6558 * Calculate flow matcher enable bitmap.
6560 * @param match_criteria
6561 * Pointer to flow matcher criteria.
6564 * Bitmap of enabled fields.
6567 flow_dv_matcher_enable(uint32_t *match_criteria)
6569 uint8_t match_criteria_enable;
6571 match_criteria_enable =
6572 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6573 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6574 match_criteria_enable |=
6575 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6576 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6577 match_criteria_enable |=
6578 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6579 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6580 match_criteria_enable |=
6581 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6582 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6583 match_criteria_enable |=
6584 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6585 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6586 return match_criteria_enable;
6593 * @param[in, out] dev
6594 * Pointer to rte_eth_dev structure.
6595 * @param[in] table_id
6598 * Direction of the table.
6599 * @param[in] transfer
6600 * E-Switch or NIC flow.
6602 * pointer to error structure.
6605 * Returns tables resource based on the index, NULL in case of failed.
6607 static struct mlx5_flow_tbl_resource *
6608 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6609 uint32_t table_id, uint8_t egress,
6611 struct rte_flow_error *error)
6613 struct mlx5_priv *priv = dev->data->dev_private;
6614 struct mlx5_ibv_shared *sh = priv->sh;
6615 struct mlx5_flow_tbl_resource *tbl;
6616 union mlx5_flow_tbl_key table_key = {
6618 .table_id = table_id,
6620 .domain = !!transfer,
6621 .direction = !!egress,
6624 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6626 struct mlx5_flow_tbl_data_entry *tbl_data;
6631 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6633 tbl = &tbl_data->tbl;
6634 rte_atomic32_inc(&tbl->refcnt);
6637 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6639 rte_flow_error_set(error, ENOMEM,
6640 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6642 "cannot allocate flow table data entry");
6645 tbl = &tbl_data->tbl;
6646 pos = &tbl_data->entry;
6648 domain = sh->fdb_domain;
6650 domain = sh->tx_domain;
6652 domain = sh->rx_domain;
6653 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6655 rte_flow_error_set(error, ENOMEM,
6656 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6657 NULL, "cannot create flow table object");
6662 * No multi-threads now, but still better to initialize the reference
6663 * count before insert it into the hash list.
6665 rte_atomic32_init(&tbl->refcnt);
6666 /* Jump action reference count is initialized here. */
6667 rte_atomic32_init(&tbl_data->jump.refcnt);
6668 pos->key = table_key.v64;
6669 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6671 rte_flow_error_set(error, -ret,
6672 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6673 "cannot insert flow table data entry");
6674 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6677 rte_atomic32_inc(&tbl->refcnt);
6682 * Release a flow table.
6685 * Pointer to rte_eth_dev structure.
6687 * Table resource to be released.
6690 * Returns 0 if table was released, else return 1;
6693 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6694 struct mlx5_flow_tbl_resource *tbl)
6696 struct mlx5_priv *priv = dev->data->dev_private;
6697 struct mlx5_ibv_shared *sh = priv->sh;
6698 struct mlx5_flow_tbl_data_entry *tbl_data =
6699 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6703 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6704 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6706 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6708 /* remove the entry from the hash list and free memory. */
6709 mlx5_hlist_remove(sh->flow_tbls, pos);
6717 * Register the flow matcher.
6719 * @param[in, out] dev
6720 * Pointer to rte_eth_dev structure.
6721 * @param[in, out] matcher
6722 * Pointer to flow matcher.
6723 * @param[in, out] key
6724 * Pointer to flow table key.
6725 * @parm[in, out] dev_flow
6726 * Pointer to the dev_flow.
6728 * pointer to error structure.
6731 * 0 on success otherwise -errno and errno is set.
6734 flow_dv_matcher_register(struct rte_eth_dev *dev,
6735 struct mlx5_flow_dv_matcher *matcher,
6736 union mlx5_flow_tbl_key *key,
6737 struct mlx5_flow *dev_flow,
6738 struct rte_flow_error *error)
6740 struct mlx5_priv *priv = dev->data->dev_private;
6741 struct mlx5_ibv_shared *sh = priv->sh;
6742 struct mlx5_flow_dv_matcher *cache_matcher;
6743 struct mlx5dv_flow_matcher_attr dv_attr = {
6744 .type = IBV_FLOW_ATTR_NORMAL,
6745 .match_mask = (void *)&matcher->mask,
6747 struct mlx5_flow_tbl_resource *tbl;
6748 struct mlx5_flow_tbl_data_entry *tbl_data;
6750 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6751 key->domain, error);
6753 return -rte_errno; /* No need to refill the error info */
6754 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6755 /* Lookup from cache. */
6756 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6757 if (matcher->crc == cache_matcher->crc &&
6758 matcher->priority == cache_matcher->priority &&
6759 !memcmp((const void *)matcher->mask.buf,
6760 (const void *)cache_matcher->mask.buf,
6761 cache_matcher->mask.size)) {
6763 "%s group %u priority %hd use %s "
6764 "matcher %p: refcnt %d++",
6765 key->domain ? "FDB" : "NIC", key->table_id,
6766 cache_matcher->priority,
6767 key->direction ? "tx" : "rx",
6768 (void *)cache_matcher,
6769 rte_atomic32_read(&cache_matcher->refcnt));
6770 rte_atomic32_inc(&cache_matcher->refcnt);
6771 dev_flow->dv.matcher = cache_matcher;
6772 /* old matcher should not make the table ref++. */
6773 flow_dv_tbl_resource_release(dev, tbl);
6777 /* Register new matcher. */
6778 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6779 if (!cache_matcher) {
6780 flow_dv_tbl_resource_release(dev, tbl);
6781 return rte_flow_error_set(error, ENOMEM,
6782 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6783 "cannot allocate matcher memory");
6785 *cache_matcher = *matcher;
6786 dv_attr.match_criteria_enable =
6787 flow_dv_matcher_enable(cache_matcher->mask.buf);
6788 dv_attr.priority = matcher->priority;
6790 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6791 cache_matcher->matcher_object =
6792 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6793 if (!cache_matcher->matcher_object) {
6794 rte_free(cache_matcher);
6795 #ifdef HAVE_MLX5DV_DR
6796 flow_dv_tbl_resource_release(dev, tbl);
6798 return rte_flow_error_set(error, ENOMEM,
6799 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6800 NULL, "cannot create matcher");
6802 /* Save the table information */
6803 cache_matcher->tbl = tbl;
6804 rte_atomic32_init(&cache_matcher->refcnt);
6805 /* only matcher ref++, table ref++ already done above in get API. */
6806 rte_atomic32_inc(&cache_matcher->refcnt);
6807 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6808 dev_flow->dv.matcher = cache_matcher;
6809 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6810 key->domain ? "FDB" : "NIC", key->table_id,
6811 cache_matcher->priority,
6812 key->direction ? "tx" : "rx", (void *)cache_matcher,
6813 rte_atomic32_read(&cache_matcher->refcnt));
6818 * Find existing tag resource or create and register a new one.
6820 * @param dev[in, out]
6821 * Pointer to rte_eth_dev structure.
6822 * @param[in, out] tag_be24
6823 * Tag value in big endian then R-shift 8.
6824 * @parm[in, out] dev_flow
6825 * Pointer to the dev_flow.
6827 * pointer to error structure.
6830 * 0 on success otherwise -errno and errno is set.
6833 flow_dv_tag_resource_register
6834 (struct rte_eth_dev *dev,
6836 struct mlx5_flow *dev_flow,
6837 struct rte_flow_error *error)
6839 struct mlx5_priv *priv = dev->data->dev_private;
6840 struct mlx5_ibv_shared *sh = priv->sh;
6841 struct mlx5_flow_dv_tag_resource *cache_resource;
6842 struct mlx5_hlist_entry *entry;
6844 /* Lookup a matching resource from cache. */
6845 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6847 cache_resource = container_of
6848 (entry, struct mlx5_flow_dv_tag_resource, entry);
6849 rte_atomic32_inc(&cache_resource->refcnt);
6850 dev_flow->dv.tag_resource = cache_resource;
6851 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6852 (void *)cache_resource,
6853 rte_atomic32_read(&cache_resource->refcnt));
6856 /* Register new resource. */
6857 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6858 if (!cache_resource)
6859 return rte_flow_error_set(error, ENOMEM,
6860 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6861 "cannot allocate resource memory");
6862 cache_resource->entry.key = (uint64_t)tag_be24;
6863 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6864 if (!cache_resource->action) {
6865 rte_free(cache_resource);
6866 return rte_flow_error_set(error, ENOMEM,
6867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6868 NULL, "cannot create action");
6870 rte_atomic32_init(&cache_resource->refcnt);
6871 rte_atomic32_inc(&cache_resource->refcnt);
6872 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6873 mlx5_glue->destroy_flow_action(cache_resource->action);
6874 rte_free(cache_resource);
6875 return rte_flow_error_set(error, EEXIST,
6876 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6877 NULL, "cannot insert tag");
6879 dev_flow->dv.tag_resource = cache_resource;
6880 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6881 (void *)cache_resource,
6882 rte_atomic32_read(&cache_resource->refcnt));
6890 * Pointer to Ethernet device.
6892 * Pointer to mlx5_flow.
6895 * 1 while a reference on it exists, 0 when freed.
6898 flow_dv_tag_release(struct rte_eth_dev *dev,
6899 struct mlx5_flow_dv_tag_resource *tag)
6901 struct mlx5_priv *priv = dev->data->dev_private;
6902 struct mlx5_ibv_shared *sh = priv->sh;
6905 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6906 dev->data->port_id, (void *)tag,
6907 rte_atomic32_read(&tag->refcnt));
6908 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6909 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6910 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6911 DRV_LOG(DEBUG, "port %u tag %p: removed",
6912 dev->data->port_id, (void *)tag);
6920 * Translate port ID action to vport.
6923 * Pointer to rte_eth_dev structure.
6925 * Pointer to the port ID action.
6926 * @param[out] dst_port_id
6927 * The target port ID.
6929 * Pointer to the error structure.
6932 * 0 on success, a negative errno value otherwise and rte_errno is set.
6935 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6936 const struct rte_flow_action *action,
6937 uint32_t *dst_port_id,
6938 struct rte_flow_error *error)
6941 struct mlx5_priv *priv;
6942 const struct rte_flow_action_port_id *conf =
6943 (const struct rte_flow_action_port_id *)action->conf;
6945 port = conf->original ? dev->data->port_id : conf->id;
6946 priv = mlx5_port_to_eswitch_info(port, false);
6948 return rte_flow_error_set(error, -rte_errno,
6949 RTE_FLOW_ERROR_TYPE_ACTION,
6951 "No eswitch info was found for port");
6952 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6954 * This parameter is transferred to
6955 * mlx5dv_dr_action_create_dest_ib_port().
6957 *dst_port_id = priv->ibv_port;
6960 * Legacy mode, no LAG configurations is supported.
6961 * This parameter is transferred to
6962 * mlx5dv_dr_action_create_dest_vport().
6964 *dst_port_id = priv->vport_id;
6970 * Add Tx queue matcher
6973 * Pointer to the dev struct.
6974 * @param[in, out] matcher
6976 * @param[in, out] key
6977 * Flow matcher value.
6979 * Flow pattern to translate.
6981 * Item is inner pattern.
6984 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6985 void *matcher, void *key,
6986 const struct rte_flow_item *item)
6988 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6989 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6991 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6993 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6994 struct mlx5_txq_ctrl *txq;
6998 queue_m = (const void *)item->mask;
7001 queue_v = (const void *)item->spec;
7004 txq = mlx5_txq_get(dev, queue_v->queue);
7007 queue = txq->obj->sq->id;
7008 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7009 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7010 queue & queue_m->queue);
7011 mlx5_txq_release(dev, queue_v->queue);
7015 * Set the hash fields according to the @p flow information.
7017 * @param[in] dev_flow
7018 * Pointer to the mlx5_flow.
7021 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7023 struct rte_flow *flow = dev_flow->flow;
7024 uint64_t items = dev_flow->layers;
7026 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7028 dev_flow->hash_fields = 0;
7029 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7030 if (flow->rss.level >= 2) {
7031 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7035 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7036 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7037 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7038 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7039 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7040 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7041 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7043 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7045 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7046 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7047 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7048 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7049 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7050 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7051 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7053 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7056 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7057 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7058 if (rss_types & ETH_RSS_UDP) {
7059 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7060 dev_flow->hash_fields |=
7061 IBV_RX_HASH_SRC_PORT_UDP;
7062 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7063 dev_flow->hash_fields |=
7064 IBV_RX_HASH_DST_PORT_UDP;
7066 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7068 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7069 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7070 if (rss_types & ETH_RSS_TCP) {
7071 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7072 dev_flow->hash_fields |=
7073 IBV_RX_HASH_SRC_PORT_TCP;
7074 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7075 dev_flow->hash_fields |=
7076 IBV_RX_HASH_DST_PORT_TCP;
7078 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7084 * Fill the flow with DV spec, lock free
7085 * (mutex should be acquired by caller).
7088 * Pointer to rte_eth_dev structure.
7089 * @param[in, out] dev_flow
7090 * Pointer to the sub flow.
7092 * Pointer to the flow attributes.
7094 * Pointer to the list of items.
7095 * @param[in] actions
7096 * Pointer to the list of actions.
7098 * Pointer to the error structure.
7101 * 0 on success, a negative errno value otherwise and rte_errno is set.
7104 __flow_dv_translate(struct rte_eth_dev *dev,
7105 struct mlx5_flow *dev_flow,
7106 const struct rte_flow_attr *attr,
7107 const struct rte_flow_item items[],
7108 const struct rte_flow_action actions[],
7109 struct rte_flow_error *error)
7111 struct mlx5_priv *priv = dev->data->dev_private;
7112 struct mlx5_dev_config *dev_conf = &priv->config;
7113 struct rte_flow *flow = dev_flow->flow;
7114 uint64_t item_flags = 0;
7115 uint64_t last_item = 0;
7116 uint64_t action_flags = 0;
7117 uint64_t priority = attr->priority;
7118 struct mlx5_flow_dv_matcher matcher = {
7120 .size = sizeof(matcher.mask.buf),
7124 bool actions_end = false;
7126 struct mlx5_flow_dv_modify_hdr_resource res;
7127 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7128 sizeof(struct mlx5_modification_cmd) *
7129 (MLX5_MAX_MODIFY_NUM + 1)];
7131 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7132 union flow_dv_attr flow_attr = { .attr = 0 };
7134 union mlx5_flow_tbl_key tbl_key;
7135 uint32_t modify_action_position = UINT32_MAX;
7136 void *match_mask = matcher.mask.buf;
7137 void *match_value = dev_flow->dv.value.buf;
7138 uint8_t next_protocol = 0xff;
7139 struct rte_vlan_hdr vlan = { 0 };
7143 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7144 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7145 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7146 !!priv->fdb_def_rule, &table, error);
7149 dev_flow->group = table;
7151 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7152 if (priority == MLX5_FLOW_PRIO_RSVD)
7153 priority = dev_conf->flow_prio - 1;
7154 /* number of actions must be set to 0 in case of dirty stack. */
7155 mhdr_res->actions_num = 0;
7156 for (; !actions_end ; actions++) {
7157 const struct rte_flow_action_queue *queue;
7158 const struct rte_flow_action_rss *rss;
7159 const struct rte_flow_action *action = actions;
7160 const struct rte_flow_action_count *count = action->conf;
7161 const uint8_t *rss_key;
7162 const struct rte_flow_action_jump *jump_data;
7163 const struct rte_flow_action_meter *mtr;
7164 struct mlx5_flow_tbl_resource *tbl;
7165 uint32_t port_id = 0;
7166 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7167 int action_type = actions->type;
7168 const struct rte_flow_action *found_action = NULL;
7170 switch (action_type) {
7171 case RTE_FLOW_ACTION_TYPE_VOID:
7173 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7174 if (flow_dv_translate_action_port_id(dev, action,
7177 port_id_resource.port_id = port_id;
7178 if (flow_dv_port_id_action_resource_register
7179 (dev, &port_id_resource, dev_flow, error))
7181 dev_flow->dv.actions[actions_n++] =
7182 dev_flow->dv.port_id_action->action;
7183 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7185 case RTE_FLOW_ACTION_TYPE_FLAG:
7186 action_flags |= MLX5_FLOW_ACTION_FLAG;
7187 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7188 struct rte_flow_action_mark mark = {
7189 .id = MLX5_FLOW_MARK_DEFAULT,
7192 if (flow_dv_convert_action_mark(dev, &mark,
7196 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7199 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7200 if (!dev_flow->dv.tag_resource)
7201 if (flow_dv_tag_resource_register
7202 (dev, tag_be, dev_flow, error))
7204 dev_flow->dv.actions[actions_n++] =
7205 dev_flow->dv.tag_resource->action;
7207 case RTE_FLOW_ACTION_TYPE_MARK:
7208 action_flags |= MLX5_FLOW_ACTION_MARK;
7209 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7210 const struct rte_flow_action_mark *mark =
7211 (const struct rte_flow_action_mark *)
7214 if (flow_dv_convert_action_mark(dev, mark,
7218 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7222 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7223 /* Legacy (non-extensive) MARK action. */
7224 tag_be = mlx5_flow_mark_set
7225 (((const struct rte_flow_action_mark *)
7226 (actions->conf))->id);
7227 if (!dev_flow->dv.tag_resource)
7228 if (flow_dv_tag_resource_register
7229 (dev, tag_be, dev_flow, error))
7231 dev_flow->dv.actions[actions_n++] =
7232 dev_flow->dv.tag_resource->action;
7234 case RTE_FLOW_ACTION_TYPE_SET_META:
7235 if (flow_dv_convert_action_set_meta
7236 (dev, mhdr_res, attr,
7237 (const struct rte_flow_action_set_meta *)
7238 actions->conf, error))
7240 action_flags |= MLX5_FLOW_ACTION_SET_META;
7242 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7243 if (flow_dv_convert_action_set_tag
7245 (const struct rte_flow_action_set_tag *)
7246 actions->conf, error))
7248 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7250 case RTE_FLOW_ACTION_TYPE_DROP:
7251 action_flags |= MLX5_FLOW_ACTION_DROP;
7253 case RTE_FLOW_ACTION_TYPE_QUEUE:
7254 MLX5_ASSERT(flow->rss.queue);
7255 queue = actions->conf;
7256 flow->rss.queue_num = 1;
7257 (*flow->rss.queue)[0] = queue->index;
7258 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7260 case RTE_FLOW_ACTION_TYPE_RSS:
7261 MLX5_ASSERT(flow->rss.queue);
7262 rss = actions->conf;
7263 if (flow->rss.queue)
7264 memcpy((*flow->rss.queue), rss->queue,
7265 rss->queue_num * sizeof(uint16_t));
7266 flow->rss.queue_num = rss->queue_num;
7267 /* NULL RSS key indicates default RSS key. */
7268 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7269 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7271 * rss->level and rss.types should be set in advance
7272 * when expanding items for RSS.
7274 action_flags |= MLX5_FLOW_ACTION_RSS;
7276 case RTE_FLOW_ACTION_TYPE_COUNT:
7277 if (!dev_conf->devx) {
7278 rte_errno = ENOTSUP;
7281 flow->counter = flow_dv_counter_alloc(dev,
7285 if (flow->counter == NULL)
7287 dev_flow->dv.actions[actions_n++] =
7288 flow->counter->action;
7289 action_flags |= MLX5_FLOW_ACTION_COUNT;
7292 if (rte_errno == ENOTSUP)
7293 return rte_flow_error_set
7295 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7297 "count action not supported");
7299 return rte_flow_error_set
7301 RTE_FLOW_ERROR_TYPE_ACTION,
7303 "cannot create counter"
7306 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7307 dev_flow->dv.actions[actions_n++] =
7308 priv->sh->pop_vlan_action;
7309 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7311 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7312 flow_dev_get_vlan_info_from_items(items, &vlan);
7313 vlan.eth_proto = rte_be_to_cpu_16
7314 ((((const struct rte_flow_action_of_push_vlan *)
7315 actions->conf)->ethertype));
7316 found_action = mlx5_flow_find_action
7318 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7320 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7321 found_action = mlx5_flow_find_action
7323 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7325 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7326 if (flow_dv_create_action_push_vlan
7327 (dev, attr, &vlan, dev_flow, error))
7329 dev_flow->dv.actions[actions_n++] =
7330 dev_flow->dv.push_vlan_res->action;
7331 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7333 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7334 /* of_vlan_push action handled this action */
7335 MLX5_ASSERT(action_flags &
7336 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7338 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7339 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7341 flow_dev_get_vlan_info_from_items(items, &vlan);
7342 mlx5_update_vlan_vid_pcp(actions, &vlan);
7343 /* If no VLAN push - this is a modify header action */
7344 if (flow_dv_convert_action_modify_vlan_vid
7345 (mhdr_res, actions, error))
7347 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7349 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7350 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7351 if (flow_dv_create_action_l2_encap(dev, actions,
7356 dev_flow->dv.actions[actions_n++] =
7357 dev_flow->dv.encap_decap->verbs_action;
7358 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7360 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7361 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7362 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7366 dev_flow->dv.actions[actions_n++] =
7367 dev_flow->dv.encap_decap->verbs_action;
7368 action_flags |= MLX5_FLOW_ACTION_DECAP;
7370 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7371 /* Handle encap with preceding decap. */
7372 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7373 if (flow_dv_create_action_raw_encap
7374 (dev, actions, dev_flow, attr, error))
7376 dev_flow->dv.actions[actions_n++] =
7377 dev_flow->dv.encap_decap->verbs_action;
7379 /* Handle encap without preceding decap. */
7380 if (flow_dv_create_action_l2_encap
7381 (dev, actions, dev_flow, attr->transfer,
7384 dev_flow->dv.actions[actions_n++] =
7385 dev_flow->dv.encap_decap->verbs_action;
7387 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7389 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7390 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7392 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7393 if (flow_dv_create_action_l2_decap
7394 (dev, dev_flow, attr->transfer, error))
7396 dev_flow->dv.actions[actions_n++] =
7397 dev_flow->dv.encap_decap->verbs_action;
7399 /* If decap is followed by encap, handle it at encap. */
7400 action_flags |= MLX5_FLOW_ACTION_DECAP;
7402 case RTE_FLOW_ACTION_TYPE_JUMP:
7403 jump_data = action->conf;
7404 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7406 !!priv->fdb_def_rule,
7410 tbl = flow_dv_tbl_resource_get(dev, table,
7412 attr->transfer, error);
7414 return rte_flow_error_set
7416 RTE_FLOW_ERROR_TYPE_ACTION,
7418 "cannot create jump action.");
7419 if (flow_dv_jump_tbl_resource_register
7420 (dev, tbl, dev_flow, error)) {
7421 flow_dv_tbl_resource_release(dev, tbl);
7422 return rte_flow_error_set
7424 RTE_FLOW_ERROR_TYPE_ACTION,
7426 "cannot create jump action.");
7428 dev_flow->dv.actions[actions_n++] =
7429 dev_flow->dv.jump->action;
7430 action_flags |= MLX5_FLOW_ACTION_JUMP;
7432 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7433 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7434 if (flow_dv_convert_action_modify_mac
7435 (mhdr_res, actions, error))
7437 action_flags |= actions->type ==
7438 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7439 MLX5_FLOW_ACTION_SET_MAC_SRC :
7440 MLX5_FLOW_ACTION_SET_MAC_DST;
7442 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7443 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7444 if (flow_dv_convert_action_modify_ipv4
7445 (mhdr_res, actions, error))
7447 action_flags |= actions->type ==
7448 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7449 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7450 MLX5_FLOW_ACTION_SET_IPV4_DST;
7452 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7453 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7454 if (flow_dv_convert_action_modify_ipv6
7455 (mhdr_res, actions, error))
7457 action_flags |= actions->type ==
7458 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7459 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7460 MLX5_FLOW_ACTION_SET_IPV6_DST;
7462 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7463 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7464 if (flow_dv_convert_action_modify_tp
7465 (mhdr_res, actions, items,
7468 action_flags |= actions->type ==
7469 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7470 MLX5_FLOW_ACTION_SET_TP_SRC :
7471 MLX5_FLOW_ACTION_SET_TP_DST;
7473 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7474 if (flow_dv_convert_action_modify_dec_ttl
7475 (mhdr_res, items, &flow_attr, error))
7477 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7479 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7480 if (flow_dv_convert_action_modify_ttl
7481 (mhdr_res, actions, items,
7484 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7486 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7487 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7488 if (flow_dv_convert_action_modify_tcp_seq
7489 (mhdr_res, actions, error))
7491 action_flags |= actions->type ==
7492 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7493 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7494 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7497 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7498 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7499 if (flow_dv_convert_action_modify_tcp_ack
7500 (mhdr_res, actions, error))
7502 action_flags |= actions->type ==
7503 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7504 MLX5_FLOW_ACTION_INC_TCP_ACK :
7505 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7507 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7508 if (flow_dv_convert_action_set_reg
7509 (mhdr_res, actions, error))
7511 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7513 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7514 if (flow_dv_convert_action_copy_mreg
7515 (dev, mhdr_res, actions, error))
7517 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7519 case RTE_FLOW_ACTION_TYPE_METER:
7520 mtr = actions->conf;
7522 flow->meter = mlx5_flow_meter_attach(priv,
7526 return rte_flow_error_set(error,
7528 RTE_FLOW_ERROR_TYPE_ACTION,
7531 "or invalid parameters");
7533 /* Set the meter action. */
7534 dev_flow->dv.actions[actions_n++] =
7535 flow->meter->mfts->meter_action;
7536 action_flags |= MLX5_FLOW_ACTION_METER;
7538 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7539 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7542 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7544 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7545 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7548 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7550 case RTE_FLOW_ACTION_TYPE_END:
7552 if (mhdr_res->actions_num) {
7553 /* create modify action if needed. */
7554 if (flow_dv_modify_hdr_resource_register
7555 (dev, mhdr_res, dev_flow, error))
7557 dev_flow->dv.actions[modify_action_position] =
7558 dev_flow->dv.modify_hdr->verbs_action;
7564 if (mhdr_res->actions_num &&
7565 modify_action_position == UINT32_MAX)
7566 modify_action_position = actions_n++;
7568 dev_flow->dv.actions_n = actions_n;
7569 dev_flow->actions = action_flags;
7570 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7571 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7572 int item_type = items->type;
7574 switch (item_type) {
7575 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7576 flow_dv_translate_item_port_id(dev, match_mask,
7577 match_value, items);
7578 last_item = MLX5_FLOW_ITEM_PORT_ID;
7580 case RTE_FLOW_ITEM_TYPE_ETH:
7581 flow_dv_translate_item_eth(match_mask, match_value,
7583 matcher.priority = MLX5_PRIORITY_MAP_L2;
7584 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7585 MLX5_FLOW_LAYER_OUTER_L2;
7587 case RTE_FLOW_ITEM_TYPE_VLAN:
7588 flow_dv_translate_item_vlan(dev_flow,
7589 match_mask, match_value,
7591 matcher.priority = MLX5_PRIORITY_MAP_L2;
7592 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7593 MLX5_FLOW_LAYER_INNER_VLAN) :
7594 (MLX5_FLOW_LAYER_OUTER_L2 |
7595 MLX5_FLOW_LAYER_OUTER_VLAN);
7597 case RTE_FLOW_ITEM_TYPE_IPV4:
7598 mlx5_flow_tunnel_ip_check(items, next_protocol,
7599 &item_flags, &tunnel);
7600 flow_dv_translate_item_ipv4(match_mask, match_value,
7603 matcher.priority = MLX5_PRIORITY_MAP_L3;
7604 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7605 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7606 if (items->mask != NULL &&
7607 ((const struct rte_flow_item_ipv4 *)
7608 items->mask)->hdr.next_proto_id) {
7610 ((const struct rte_flow_item_ipv4 *)
7611 (items->spec))->hdr.next_proto_id;
7613 ((const struct rte_flow_item_ipv4 *)
7614 (items->mask))->hdr.next_proto_id;
7616 /* Reset for inner layer. */
7617 next_protocol = 0xff;
7620 case RTE_FLOW_ITEM_TYPE_IPV6:
7621 mlx5_flow_tunnel_ip_check(items, next_protocol,
7622 &item_flags, &tunnel);
7623 flow_dv_translate_item_ipv6(match_mask, match_value,
7626 matcher.priority = MLX5_PRIORITY_MAP_L3;
7627 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7628 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7629 if (items->mask != NULL &&
7630 ((const struct rte_flow_item_ipv6 *)
7631 items->mask)->hdr.proto) {
7633 ((const struct rte_flow_item_ipv6 *)
7634 items->spec)->hdr.proto;
7636 ((const struct rte_flow_item_ipv6 *)
7637 items->mask)->hdr.proto;
7639 /* Reset for inner layer. */
7640 next_protocol = 0xff;
7643 case RTE_FLOW_ITEM_TYPE_TCP:
7644 flow_dv_translate_item_tcp(match_mask, match_value,
7646 matcher.priority = MLX5_PRIORITY_MAP_L4;
7647 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7648 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7650 case RTE_FLOW_ITEM_TYPE_UDP:
7651 flow_dv_translate_item_udp(match_mask, match_value,
7653 matcher.priority = MLX5_PRIORITY_MAP_L4;
7654 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7655 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7657 case RTE_FLOW_ITEM_TYPE_GRE:
7658 flow_dv_translate_item_gre(match_mask, match_value,
7660 matcher.priority = flow->rss.level >= 2 ?
7661 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7662 last_item = MLX5_FLOW_LAYER_GRE;
7664 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7665 flow_dv_translate_item_gre_key(match_mask,
7666 match_value, items);
7667 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7669 case RTE_FLOW_ITEM_TYPE_NVGRE:
7670 flow_dv_translate_item_nvgre(match_mask, match_value,
7672 matcher.priority = flow->rss.level >= 2 ?
7673 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7674 last_item = MLX5_FLOW_LAYER_GRE;
7676 case RTE_FLOW_ITEM_TYPE_VXLAN:
7677 flow_dv_translate_item_vxlan(match_mask, match_value,
7679 matcher.priority = flow->rss.level >= 2 ?
7680 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7681 last_item = MLX5_FLOW_LAYER_VXLAN;
7683 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7684 flow_dv_translate_item_vxlan_gpe(match_mask,
7687 matcher.priority = flow->rss.level >= 2 ?
7688 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7689 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7691 case RTE_FLOW_ITEM_TYPE_GENEVE:
7692 flow_dv_translate_item_geneve(match_mask, match_value,
7694 matcher.priority = flow->rss.level >= 2 ?
7695 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7696 last_item = MLX5_FLOW_LAYER_GENEVE;
7698 case RTE_FLOW_ITEM_TYPE_MPLS:
7699 flow_dv_translate_item_mpls(match_mask, match_value,
7700 items, last_item, tunnel);
7701 matcher.priority = flow->rss.level >= 2 ?
7702 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7703 last_item = MLX5_FLOW_LAYER_MPLS;
7705 case RTE_FLOW_ITEM_TYPE_MARK:
7706 flow_dv_translate_item_mark(dev, match_mask,
7707 match_value, items);
7708 last_item = MLX5_FLOW_ITEM_MARK;
7710 case RTE_FLOW_ITEM_TYPE_META:
7711 flow_dv_translate_item_meta(dev, match_mask,
7712 match_value, attr, items);
7713 last_item = MLX5_FLOW_ITEM_METADATA;
7715 case RTE_FLOW_ITEM_TYPE_ICMP:
7716 flow_dv_translate_item_icmp(match_mask, match_value,
7718 last_item = MLX5_FLOW_LAYER_ICMP;
7720 case RTE_FLOW_ITEM_TYPE_ICMP6:
7721 flow_dv_translate_item_icmp6(match_mask, match_value,
7723 last_item = MLX5_FLOW_LAYER_ICMP6;
7725 case RTE_FLOW_ITEM_TYPE_TAG:
7726 flow_dv_translate_item_tag(dev, match_mask,
7727 match_value, items);
7728 last_item = MLX5_FLOW_ITEM_TAG;
7730 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7731 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7732 match_value, items);
7733 last_item = MLX5_FLOW_ITEM_TAG;
7735 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7736 flow_dv_translate_item_tx_queue(dev, match_mask,
7739 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7741 case RTE_FLOW_ITEM_TYPE_GTP:
7742 flow_dv_translate_item_gtp(match_mask, match_value,
7744 matcher.priority = flow->rss.level >= 2 ?
7745 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7746 last_item = MLX5_FLOW_LAYER_GTP;
7751 item_flags |= last_item;
7754 * When E-Switch mode is enabled, we have two cases where we need to
7755 * set the source port manually.
7756 * The first one, is in case of Nic steering rule, and the second is
7757 * E-Switch rule where no port_id item was found. In both cases
7758 * the source port is set according the current port in use.
7760 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7761 (priv->representor || priv->master)) {
7762 if (flow_dv_translate_item_port_id(dev, match_mask,
7766 #ifdef RTE_LIBRTE_MLX5_DEBUG
7767 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7768 dev_flow->dv.value.buf));
7770 dev_flow->layers = item_flags;
7771 if (action_flags & MLX5_FLOW_ACTION_RSS)
7772 flow_dv_hashfields_set(dev_flow);
7773 /* Register matcher. */
7774 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7776 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7778 /* reserved field no needs to be set to 0 here. */
7779 tbl_key.domain = attr->transfer;
7780 tbl_key.direction = attr->egress;
7781 tbl_key.table_id = dev_flow->group;
7782 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7788 * Apply the flow to the NIC, lock free,
7789 * (mutex should be acquired by caller).
7792 * Pointer to the Ethernet device structure.
7793 * @param[in, out] flow
7794 * Pointer to flow structure.
7796 * Pointer to error structure.
7799 * 0 on success, a negative errno value otherwise and rte_errno is set.
7802 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7803 struct rte_flow_error *error)
7805 struct mlx5_flow_dv *dv;
7806 struct mlx5_flow *dev_flow;
7807 struct mlx5_priv *priv = dev->data->dev_private;
7811 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7814 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7815 if (dev_flow->transfer) {
7816 dv->actions[n++] = priv->sh->esw_drop_action;
7818 dv->hrxq = mlx5_hrxq_drop_new(dev);
7822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7824 "cannot get drop hash queue");
7827 dv->actions[n++] = dv->hrxq->action;
7829 } else if (dev_flow->actions &
7830 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7831 struct mlx5_hrxq *hrxq;
7833 MLX5_ASSERT(flow->rss.queue);
7834 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7835 MLX5_RSS_HASH_KEY_LEN,
7836 dev_flow->hash_fields,
7838 flow->rss.queue_num);
7840 hrxq = mlx5_hrxq_new
7841 (dev, flow->rss.key,
7842 MLX5_RSS_HASH_KEY_LEN,
7843 dev_flow->hash_fields,
7845 flow->rss.queue_num,
7846 !!(dev_flow->layers &
7847 MLX5_FLOW_LAYER_TUNNEL));
7852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7853 "cannot get hash queue");
7857 dv->actions[n++] = dv->hrxq->action;
7860 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7861 (void *)&dv->value, n,
7864 rte_flow_error_set(error, errno,
7865 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7867 "hardware refuses to create flow");
7870 if (priv->vmwa_context &&
7871 dev_flow->dv.vf_vlan.tag &&
7872 !dev_flow->dv.vf_vlan.created) {
7874 * The rule contains the VLAN pattern.
7875 * For VF we are going to create VLAN
7876 * interface to make hypervisor set correct
7877 * e-Switch vport context.
7879 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7884 err = rte_errno; /* Save rte_errno before cleanup. */
7885 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7886 struct mlx5_flow_dv *dv = &dev_flow->dv;
7888 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7889 mlx5_hrxq_drop_release(dev);
7891 mlx5_hrxq_release(dev, dv->hrxq);
7894 if (dev_flow->dv.vf_vlan.tag &&
7895 dev_flow->dv.vf_vlan.created)
7896 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7898 rte_errno = err; /* Restore rte_errno. */
7903 * Release the flow matcher.
7906 * Pointer to Ethernet device.
7908 * Pointer to mlx5_flow.
7911 * 1 while a reference on it exists, 0 when freed.
7914 flow_dv_matcher_release(struct rte_eth_dev *dev,
7915 struct mlx5_flow *flow)
7917 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7919 MLX5_ASSERT(matcher->matcher_object);
7920 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7921 dev->data->port_id, (void *)matcher,
7922 rte_atomic32_read(&matcher->refcnt));
7923 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7924 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7925 (matcher->matcher_object));
7926 LIST_REMOVE(matcher, next);
7927 /* table ref-- in release interface. */
7928 flow_dv_tbl_resource_release(dev, matcher->tbl);
7930 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7931 dev->data->port_id, (void *)matcher);
7938 * Release an encap/decap resource.
7941 * Pointer to mlx5_flow.
7944 * 1 while a reference on it exists, 0 when freed.
7947 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7949 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7950 flow->dv.encap_decap;
7952 MLX5_ASSERT(cache_resource->verbs_action);
7953 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7954 (void *)cache_resource,
7955 rte_atomic32_read(&cache_resource->refcnt));
7956 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7957 claim_zero(mlx5_glue->destroy_flow_action
7958 (cache_resource->verbs_action));
7959 LIST_REMOVE(cache_resource, next);
7960 rte_free(cache_resource);
7961 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7962 (void *)cache_resource);
7969 * Release an jump to table action resource.
7972 * Pointer to Ethernet device.
7974 * Pointer to mlx5_flow.
7977 * 1 while a reference on it exists, 0 when freed.
7980 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7981 struct mlx5_flow *flow)
7983 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7984 struct mlx5_flow_tbl_data_entry *tbl_data =
7985 container_of(cache_resource,
7986 struct mlx5_flow_tbl_data_entry, jump);
7988 MLX5_ASSERT(cache_resource->action);
7989 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7990 (void *)cache_resource,
7991 rte_atomic32_read(&cache_resource->refcnt));
7992 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7993 claim_zero(mlx5_glue->destroy_flow_action
7994 (cache_resource->action));
7995 /* jump action memory free is inside the table release. */
7996 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7997 DRV_LOG(DEBUG, "jump table resource %p: removed",
7998 (void *)cache_resource);
8005 * Release a modify-header resource.
8008 * Pointer to mlx5_flow.
8011 * 1 while a reference on it exists, 0 when freed.
8014 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
8016 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8017 flow->dv.modify_hdr;
8019 MLX5_ASSERT(cache_resource->verbs_action);
8020 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8021 (void *)cache_resource,
8022 rte_atomic32_read(&cache_resource->refcnt));
8023 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8024 claim_zero(mlx5_glue->destroy_flow_action
8025 (cache_resource->verbs_action));
8026 LIST_REMOVE(cache_resource, next);
8027 rte_free(cache_resource);
8028 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8029 (void *)cache_resource);
8036 * Release port ID action resource.
8039 * Pointer to mlx5_flow.
8042 * 1 while a reference on it exists, 0 when freed.
8045 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8047 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8048 flow->dv.port_id_action;
8050 MLX5_ASSERT(cache_resource->action);
8051 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8052 (void *)cache_resource,
8053 rte_atomic32_read(&cache_resource->refcnt));
8054 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8055 claim_zero(mlx5_glue->destroy_flow_action
8056 (cache_resource->action));
8057 LIST_REMOVE(cache_resource, next);
8058 rte_free(cache_resource);
8059 DRV_LOG(DEBUG, "port id action resource %p: removed",
8060 (void *)cache_resource);
8067 * Release push vlan action resource.
8070 * Pointer to mlx5_flow.
8073 * 1 while a reference on it exists, 0 when freed.
8076 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8078 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8079 flow->dv.push_vlan_res;
8081 MLX5_ASSERT(cache_resource->action);
8082 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8083 (void *)cache_resource,
8084 rte_atomic32_read(&cache_resource->refcnt));
8085 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8086 claim_zero(mlx5_glue->destroy_flow_action
8087 (cache_resource->action));
8088 LIST_REMOVE(cache_resource, next);
8089 rte_free(cache_resource);
8090 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8091 (void *)cache_resource);
8098 * Remove the flow from the NIC but keeps it in memory.
8099 * Lock free, (mutex should be acquired by caller).
8102 * Pointer to Ethernet device.
8103 * @param[in, out] flow
8104 * Pointer to flow structure.
8107 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8109 struct mlx5_flow_dv *dv;
8110 struct mlx5_flow *dev_flow;
8114 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8117 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8121 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8122 mlx5_hrxq_drop_release(dev);
8124 mlx5_hrxq_release(dev, dv->hrxq);
8127 if (dev_flow->dv.vf_vlan.tag &&
8128 dev_flow->dv.vf_vlan.created)
8129 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8134 * Remove the flow from the NIC and the memory.
8135 * Lock free, (mutex should be acquired by caller).
8138 * Pointer to the Ethernet device structure.
8139 * @param[in, out] flow
8140 * Pointer to flow structure.
8143 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8145 struct mlx5_flow *dev_flow;
8149 __flow_dv_remove(dev, flow);
8150 if (flow->counter) {
8151 flow_dv_counter_release(dev, flow->counter);
8152 flow->counter = NULL;
8155 mlx5_flow_meter_detach(flow->meter);
8158 while (!LIST_EMPTY(&flow->dev_flows)) {
8159 dev_flow = LIST_FIRST(&flow->dev_flows);
8160 LIST_REMOVE(dev_flow, next);
8161 if (dev_flow->dv.matcher)
8162 flow_dv_matcher_release(dev, dev_flow);
8163 if (dev_flow->dv.encap_decap)
8164 flow_dv_encap_decap_resource_release(dev_flow);
8165 if (dev_flow->dv.modify_hdr)
8166 flow_dv_modify_hdr_resource_release(dev_flow);
8167 if (dev_flow->dv.jump)
8168 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8169 if (dev_flow->dv.port_id_action)
8170 flow_dv_port_id_action_resource_release(dev_flow);
8171 if (dev_flow->dv.push_vlan_res)
8172 flow_dv_push_vlan_action_resource_release(dev_flow);
8173 if (dev_flow->dv.tag_resource)
8174 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8180 * Query a dv flow rule for its statistics via devx.
8183 * Pointer to Ethernet device.
8185 * Pointer to the sub flow.
8187 * data retrieved by the query.
8189 * Perform verbose error reporting if not NULL.
8192 * 0 on success, a negative errno value otherwise and rte_errno is set.
8195 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8196 void *data, struct rte_flow_error *error)
8198 struct mlx5_priv *priv = dev->data->dev_private;
8199 struct rte_flow_query_count *qc = data;
8201 if (!priv->config.devx)
8202 return rte_flow_error_set(error, ENOTSUP,
8203 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8205 "counters are not supported");
8206 if (flow->counter) {
8207 uint64_t pkts, bytes;
8208 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8212 return rte_flow_error_set(error, -err,
8213 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8214 NULL, "cannot read counters");
8217 qc->hits = pkts - flow->counter->hits;
8218 qc->bytes = bytes - flow->counter->bytes;
8220 flow->counter->hits = pkts;
8221 flow->counter->bytes = bytes;
8225 return rte_flow_error_set(error, EINVAL,
8226 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8228 "counters are not available");
8234 * @see rte_flow_query()
8238 flow_dv_query(struct rte_eth_dev *dev,
8239 struct rte_flow *flow __rte_unused,
8240 const struct rte_flow_action *actions __rte_unused,
8241 void *data __rte_unused,
8242 struct rte_flow_error *error __rte_unused)
8246 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8247 switch (actions->type) {
8248 case RTE_FLOW_ACTION_TYPE_VOID:
8250 case RTE_FLOW_ACTION_TYPE_COUNT:
8251 ret = flow_dv_query_count(dev, flow, data, error);
8254 return rte_flow_error_set(error, ENOTSUP,
8255 RTE_FLOW_ERROR_TYPE_ACTION,
8257 "action not supported");
8264 * Destroy the meter table set.
8265 * Lock free, (mutex should be acquired by caller).
8268 * Pointer to Ethernet device.
8270 * Pointer to the meter table set.
8276 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8277 struct mlx5_meter_domains_infos *tbl)
8279 struct mlx5_priv *priv = dev->data->dev_private;
8280 struct mlx5_meter_domains_infos *mtd =
8281 (struct mlx5_meter_domains_infos *)tbl;
8283 if (!mtd || !priv->config.dv_flow_en)
8285 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8286 claim_zero(mlx5_glue->dv_destroy_flow
8287 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8288 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8289 claim_zero(mlx5_glue->dv_destroy_flow
8290 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8291 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8292 claim_zero(mlx5_glue->dv_destroy_flow
8293 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8294 if (mtd->egress.color_matcher)
8295 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8296 (mtd->egress.color_matcher));
8297 if (mtd->egress.any_matcher)
8298 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8299 (mtd->egress.any_matcher));
8300 if (mtd->egress.tbl)
8301 claim_zero(flow_dv_tbl_resource_release(dev,
8303 if (mtd->ingress.color_matcher)
8304 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8305 (mtd->ingress.color_matcher));
8306 if (mtd->ingress.any_matcher)
8307 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8308 (mtd->ingress.any_matcher));
8309 if (mtd->ingress.tbl)
8310 claim_zero(flow_dv_tbl_resource_release(dev,
8312 if (mtd->transfer.color_matcher)
8313 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8314 (mtd->transfer.color_matcher));
8315 if (mtd->transfer.any_matcher)
8316 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8317 (mtd->transfer.any_matcher));
8318 if (mtd->transfer.tbl)
8319 claim_zero(flow_dv_tbl_resource_release(dev,
8320 mtd->transfer.tbl));
8322 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8327 /* Number of meter flow actions, count and jump or count and drop. */
8328 #define METER_ACTIONS 2
8331 * Create specify domain meter table and suffix table.
8334 * Pointer to Ethernet device.
8335 * @param[in,out] mtb
8336 * Pointer to DV meter table set.
8339 * @param[in] transfer
8341 * @param[in] color_reg_c_idx
8342 * Reg C index for color match.
8345 * 0 on success, -1 otherwise and rte_errno is set.
8348 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8349 struct mlx5_meter_domains_infos *mtb,
8350 uint8_t egress, uint8_t transfer,
8351 uint32_t color_reg_c_idx)
8353 struct mlx5_priv *priv = dev->data->dev_private;
8354 struct mlx5_ibv_shared *sh = priv->sh;
8355 struct mlx5_flow_dv_match_params mask = {
8356 .size = sizeof(mask.buf),
8358 struct mlx5_flow_dv_match_params value = {
8359 .size = sizeof(value.buf),
8361 struct mlx5dv_flow_matcher_attr dv_attr = {
8362 .type = IBV_FLOW_ATTR_NORMAL,
8364 .match_criteria_enable = 0,
8365 .match_mask = (void *)&mask,
8367 void *actions[METER_ACTIONS];
8368 struct mlx5_flow_tbl_resource **sfx_tbl;
8369 struct mlx5_meter_domain_info *dtb;
8370 struct rte_flow_error error;
8374 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8375 dtb = &mtb->transfer;
8376 } else if (egress) {
8377 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8380 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8381 dtb = &mtb->ingress;
8383 /* If the suffix table in missing, create it. */
8385 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8386 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8387 egress, transfer, &error);
8389 DRV_LOG(ERR, "Failed to create meter suffix table.");
8393 /* Create the meter table with METER level. */
8394 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8395 egress, transfer, &error);
8397 DRV_LOG(ERR, "Failed to create meter policer table.");
8400 /* Create matchers, Any and Color. */
8401 dv_attr.priority = 3;
8402 dv_attr.match_criteria_enable = 0;
8403 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8406 if (!dtb->any_matcher) {
8407 DRV_LOG(ERR, "Failed to create meter"
8408 " policer default matcher.");
8411 dv_attr.priority = 0;
8412 dv_attr.match_criteria_enable =
8413 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8414 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8415 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8416 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8419 if (!dtb->color_matcher) {
8420 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8423 if (mtb->count_actns[RTE_MTR_DROPPED])
8424 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8425 actions[i++] = mtb->drop_actn;
8426 /* Default rule: lowest priority, match any, actions: drop. */
8427 dtb->policer_rules[RTE_MTR_DROPPED] =
8428 mlx5_glue->dv_create_flow(dtb->any_matcher,
8429 (void *)&value, i, actions);
8430 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8431 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8440 * Create the needed meter and suffix tables.
8441 * Lock free, (mutex should be acquired by caller).
8444 * Pointer to Ethernet device.
8446 * Pointer to the flow meter.
8449 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8451 static struct mlx5_meter_domains_infos *
8452 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8453 const struct mlx5_flow_meter *fm)
8455 struct mlx5_priv *priv = dev->data->dev_private;
8456 struct mlx5_meter_domains_infos *mtb;
8460 if (!priv->mtr_en) {
8461 rte_errno = ENOTSUP;
8464 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8466 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8469 /* Create meter count actions */
8470 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8471 if (!fm->policer_stats.cnt[i])
8473 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8475 /* Create drop action. */
8476 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8477 if (!mtb->drop_actn) {
8478 DRV_LOG(ERR, "Failed to create drop action.");
8481 /* Egress meter table. */
8482 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8484 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8487 /* Ingress meter table. */
8488 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8490 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8493 /* FDB meter table. */
8494 if (priv->config.dv_esw_en) {
8495 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8496 priv->mtr_color_reg);
8498 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8504 flow_dv_destroy_mtr_tbl(dev, mtb);
8509 * Destroy domain policer rule.
8512 * Pointer to domain table.
8515 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8519 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8520 if (dt->policer_rules[i]) {
8521 claim_zero(mlx5_glue->dv_destroy_flow
8522 (dt->policer_rules[i]));
8523 dt->policer_rules[i] = NULL;
8526 if (dt->jump_actn) {
8527 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8528 dt->jump_actn = NULL;
8533 * Destroy policer rules.
8536 * Pointer to Ethernet device.
8538 * Pointer to flow meter structure.
8540 * Pointer to flow attributes.
8546 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8547 const struct mlx5_flow_meter *fm,
8548 const struct rte_flow_attr *attr)
8550 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8555 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8557 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8559 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8564 * Create specify domain meter policer rule.
8567 * Pointer to flow meter structure.
8569 * Pointer to DV meter table set.
8571 * Pointer to suffix table.
8572 * @param[in] mtr_reg_c
8573 * Color match REG_C.
8576 * 0 on success, -1 otherwise.
8579 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8580 struct mlx5_meter_domain_info *dtb,
8581 struct mlx5_flow_tbl_resource *sfx_tb,
8584 struct mlx5_flow_dv_match_params matcher = {
8585 .size = sizeof(matcher.buf),
8587 struct mlx5_flow_dv_match_params value = {
8588 .size = sizeof(value.buf),
8590 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8591 void *actions[METER_ACTIONS];
8594 /* Create jump action. */
8597 if (!dtb->jump_actn)
8599 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8601 if (!dtb->jump_actn) {
8602 DRV_LOG(ERR, "Failed to create policer jump action.");
8605 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8608 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8609 rte_col_2_mlx5_col(i), UINT8_MAX);
8610 if (mtb->count_actns[i])
8611 actions[j++] = mtb->count_actns[i];
8612 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8613 actions[j++] = mtb->drop_actn;
8615 actions[j++] = dtb->jump_actn;
8616 dtb->policer_rules[i] =
8617 mlx5_glue->dv_create_flow(dtb->color_matcher,
8620 if (!dtb->policer_rules[i]) {
8621 DRV_LOG(ERR, "Failed to create policer rule.");
8632 * Create policer rules.
8635 * Pointer to Ethernet device.
8637 * Pointer to flow meter structure.
8639 * Pointer to flow attributes.
8642 * 0 on success, -1 otherwise.
8645 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8646 struct mlx5_flow_meter *fm,
8647 const struct rte_flow_attr *attr)
8649 struct mlx5_priv *priv = dev->data->dev_private;
8650 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8654 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8655 priv->sh->tx_mtr_sfx_tbl,
8656 priv->mtr_color_reg);
8658 DRV_LOG(ERR, "Failed to create egress policer.");
8662 if (attr->ingress) {
8663 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8664 priv->sh->rx_mtr_sfx_tbl,
8665 priv->mtr_color_reg);
8667 DRV_LOG(ERR, "Failed to create ingress policer.");
8671 if (attr->transfer) {
8672 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8673 priv->sh->fdb_mtr_sfx_tbl,
8674 priv->mtr_color_reg);
8676 DRV_LOG(ERR, "Failed to create transfer policer.");
8682 flow_dv_destroy_policer_rules(dev, fm, attr);
8687 * Query a devx counter.
8690 * Pointer to the Ethernet device structure.
8692 * Pointer to the flow counter.
8694 * Set to clear the counter statistics.
8696 * The statistics value of packets.
8698 * The statistics value of bytes.
8701 * 0 on success, otherwise return -1.
8704 flow_dv_counter_query(struct rte_eth_dev *dev,
8705 struct mlx5_flow_counter *cnt, bool clear,
8706 uint64_t *pkts, uint64_t *bytes)
8708 struct mlx5_priv *priv = dev->data->dev_private;
8709 uint64_t inn_pkts, inn_bytes;
8712 if (!priv->config.devx)
8714 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8717 *pkts = inn_pkts - cnt->hits;
8718 *bytes = inn_bytes - cnt->bytes;
8720 cnt->hits = inn_pkts;
8721 cnt->bytes = inn_bytes;
8727 * Mutex-protected thunk to lock-free __flow_dv_translate().
8730 flow_dv_translate(struct rte_eth_dev *dev,
8731 struct mlx5_flow *dev_flow,
8732 const struct rte_flow_attr *attr,
8733 const struct rte_flow_item items[],
8734 const struct rte_flow_action actions[],
8735 struct rte_flow_error *error)
8739 flow_dv_shared_lock(dev);
8740 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8741 flow_dv_shared_unlock(dev);
8746 * Mutex-protected thunk to lock-free __flow_dv_apply().
8749 flow_dv_apply(struct rte_eth_dev *dev,
8750 struct rte_flow *flow,
8751 struct rte_flow_error *error)
8755 flow_dv_shared_lock(dev);
8756 ret = __flow_dv_apply(dev, flow, error);
8757 flow_dv_shared_unlock(dev);
8762 * Mutex-protected thunk to lock-free __flow_dv_remove().
8765 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8767 flow_dv_shared_lock(dev);
8768 __flow_dv_remove(dev, flow);
8769 flow_dv_shared_unlock(dev);
8773 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8776 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8778 flow_dv_shared_lock(dev);
8779 __flow_dv_destroy(dev, flow);
8780 flow_dv_shared_unlock(dev);
8784 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8786 static struct mlx5_flow_counter *
8787 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8789 struct mlx5_flow_counter *cnt;
8791 flow_dv_shared_lock(dev);
8792 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8793 flow_dv_shared_unlock(dev);
8798 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8801 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8803 flow_dv_shared_lock(dev);
8804 flow_dv_counter_release(dev, cnt);
8805 flow_dv_shared_unlock(dev);
8808 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8809 .validate = flow_dv_validate,
8810 .prepare = flow_dv_prepare,
8811 .translate = flow_dv_translate,
8812 .apply = flow_dv_apply,
8813 .remove = flow_dv_remove,
8814 .destroy = flow_dv_destroy,
8815 .query = flow_dv_query,
8816 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8817 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8818 .create_policer_rules = flow_dv_create_policer_rules,
8819 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8820 .counter_alloc = flow_dv_counter_allocate,
8821 .counter_free = flow_dv_counter_free,
8822 .counter_query = flow_dv_counter_query,
8825 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */