1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_dv_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_dv_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_NONE] = MLX5_MODI_OUT_NONE,
836 [REG_A] = MLX5_MODI_META_DATA_REG_A,
837 [REG_B] = MLX5_MODI_META_DATA_REG_B,
838 [REG_C_0] = MLX5_MODI_META_REG_C_0,
839 [REG_C_1] = MLX5_MODI_META_REG_C_1,
840 [REG_C_2] = MLX5_MODI_META_REG_C_2,
841 [REG_C_3] = MLX5_MODI_META_REG_C_3,
842 [REG_C_4] = MLX5_MODI_META_REG_C_4,
843 [REG_C_5] = MLX5_MODI_META_REG_C_5,
844 [REG_C_6] = MLX5_MODI_META_REG_C_6,
845 [REG_C_7] = MLX5_MODI_META_REG_C_7,
849 * Convert register set to DV specification.
851 * @param[in,out] resource
852 * Pointer to the modify-header resource.
854 * Pointer to action specification.
856 * Pointer to the error structure.
859 * 0 on success, a negative errno value otherwise and rte_errno is set.
862 flow_dv_convert_action_set_reg
863 (struct mlx5_flow_dv_modify_hdr_resource *resource,
864 const struct rte_flow_action *action,
865 struct rte_flow_error *error)
867 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
868 struct mlx5_modification_cmd *actions = resource->actions;
869 uint32_t i = resource->actions_num;
871 if (i >= MLX5_MODIFY_NUM)
872 return rte_flow_error_set(error, EINVAL,
873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
874 "too many items to modify");
875 assert(conf->id != REG_NONE);
876 assert(conf->id < RTE_DIM(reg_to_field));
877 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
878 actions[i].field = reg_to_field[conf->id];
879 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
880 actions[i].data1 = rte_cpu_to_be_32(conf->data);
882 resource->actions_num = i;
883 if (!resource->actions_num)
884 return rte_flow_error_set(error, EINVAL,
885 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
886 "invalid modification flow item");
891 * Convert SET_TAG action to DV specification.
894 * Pointer to the rte_eth_dev structure.
895 * @param[in,out] resource
896 * Pointer to the modify-header resource.
898 * Pointer to action specification.
900 * Pointer to the error structure.
903 * 0 on success, a negative errno value otherwise and rte_errno is set.
906 flow_dv_convert_action_set_tag
907 (struct rte_eth_dev *dev,
908 struct mlx5_flow_dv_modify_hdr_resource *resource,
909 const struct rte_flow_action_set_tag *conf,
910 struct rte_flow_error *error)
912 rte_be32_t data = rte_cpu_to_be_32(conf->data);
913 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
914 struct rte_flow_item item = {
918 struct field_modify_info reg_c_x[] = {
921 enum mlx5_modification_field reg_type;
924 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
927 assert(ret != REG_NONE);
928 assert((unsigned int)ret < RTE_DIM(reg_to_field));
929 reg_type = reg_to_field[ret];
930 assert(reg_type > 0);
931 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
932 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
933 MLX5_MODIFICATION_TYPE_SET, error);
937 * Convert internal COPY_REG action to DV specification.
940 * Pointer to the rte_eth_dev structure.
942 * Pointer to the modify-header resource.
944 * Pointer to action specification.
946 * Pointer to the error structure.
949 * 0 on success, a negative errno value otherwise and rte_errno is set.
952 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
953 struct mlx5_flow_dv_modify_hdr_resource *res,
954 const struct rte_flow_action *action,
955 struct rte_flow_error *error)
957 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
958 rte_be32_t mask = RTE_BE32(UINT32_MAX);
959 struct rte_flow_item item = {
963 struct field_modify_info reg_src[] = {
964 {4, 0, reg_to_field[conf->src]},
967 struct field_modify_info reg_dst = {
969 .id = reg_to_field[conf->dst],
971 /* Adjust reg_c[0] usage according to reported mask. */
972 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
973 struct mlx5_priv *priv = dev->data->dev_private;
974 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
977 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
978 if (conf->dst == REG_C_0) {
979 /* Copy to reg_c[0], within mask only. */
980 reg_dst.offset = rte_bsf32(reg_c0);
982 * Mask is ignoring the enianness, because
983 * there is no conversion in datapath.
985 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
986 /* Copy from destination lower bits to reg_c[0]. */
987 mask = reg_c0 >> reg_dst.offset;
989 /* Copy from destination upper bits to reg_c[0]. */
990 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
991 rte_fls_u32(reg_c0));
994 mask = rte_cpu_to_be_32(reg_c0);
995 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
996 /* Copy from reg_c[0] to destination lower bits. */
999 /* Copy from reg_c[0] to destination upper bits. */
1000 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1001 (rte_fls_u32(reg_c0) -
1006 return flow_dv_convert_modify_action(&item,
1007 reg_src, ®_dst, res,
1008 MLX5_MODIFICATION_TYPE_COPY,
1013 * Validate META item.
1016 * Pointer to the rte_eth_dev structure.
1018 * Item specification.
1020 * Attributes of flow that includes this item.
1022 * Pointer to error structure.
1025 * 0 on success, a negative errno value otherwise and rte_errno is set.
1028 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1029 const struct rte_flow_item *item,
1030 const struct rte_flow_attr *attr,
1031 struct rte_flow_error *error)
1033 const struct rte_flow_item_meta *spec = item->spec;
1034 const struct rte_flow_item_meta *mask = item->mask;
1035 const struct rte_flow_item_meta nic_mask = {
1041 return rte_flow_error_set(error, EINVAL,
1042 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1044 "data cannot be empty");
1046 return rte_flow_error_set(error, EINVAL,
1047 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1049 "data cannot be zero");
1051 mask = &rte_flow_item_meta_mask;
1052 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1053 (const uint8_t *)&nic_mask,
1054 sizeof(struct rte_flow_item_meta),
1059 return rte_flow_error_set(error, ENOTSUP,
1060 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1062 "pattern not supported for ingress");
1067 * Validate TAG item.
1070 * Pointer to the rte_eth_dev structure.
1072 * Item specification.
1074 * Attributes of flow that includes this item.
1076 * Pointer to error structure.
1079 * 0 on success, a negative errno value otherwise and rte_errno is set.
1082 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1083 const struct rte_flow_item *item,
1084 const struct rte_flow_attr *attr __rte_unused,
1085 struct rte_flow_error *error)
1087 const struct rte_flow_item_tag *spec = item->spec;
1088 const struct rte_flow_item_tag *mask = item->mask;
1089 const struct rte_flow_item_tag nic_mask = {
1090 .data = RTE_BE32(UINT32_MAX),
1095 if (!mlx5_flow_ext_mreg_supported(dev))
1096 return rte_flow_error_set(error, ENOTSUP,
1097 RTE_FLOW_ERROR_TYPE_ITEM, item,
1098 "extensive metadata register"
1099 " isn't supported");
1101 return rte_flow_error_set(error, EINVAL,
1102 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1104 "data cannot be empty");
1106 mask = &rte_flow_item_tag_mask;
1107 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1108 (const uint8_t *)&nic_mask,
1109 sizeof(struct rte_flow_item_tag),
1113 if (mask->index != 0xff)
1114 return rte_flow_error_set(error, EINVAL,
1115 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1116 "partial mask for tag index"
1117 " is not supported");
1118 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1121 assert(ret != REG_NONE);
1126 * Validate vport item.
1129 * Pointer to the rte_eth_dev structure.
1131 * Item specification.
1133 * Attributes of flow that includes this item.
1134 * @param[in] item_flags
1135 * Bit-fields that holds the items detected until now.
1137 * Pointer to error structure.
1140 * 0 on success, a negative errno value otherwise and rte_errno is set.
1143 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1144 const struct rte_flow_item *item,
1145 const struct rte_flow_attr *attr,
1146 uint64_t item_flags,
1147 struct rte_flow_error *error)
1149 const struct rte_flow_item_port_id *spec = item->spec;
1150 const struct rte_flow_item_port_id *mask = item->mask;
1151 const struct rte_flow_item_port_id switch_mask = {
1154 struct mlx5_priv *esw_priv;
1155 struct mlx5_priv *dev_priv;
1158 if (!attr->transfer)
1159 return rte_flow_error_set(error, EINVAL,
1160 RTE_FLOW_ERROR_TYPE_ITEM,
1162 "match on port id is valid only"
1163 " when transfer flag is enabled");
1164 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1165 return rte_flow_error_set(error, ENOTSUP,
1166 RTE_FLOW_ERROR_TYPE_ITEM, item,
1167 "multiple source ports are not"
1170 mask = &switch_mask;
1171 if (mask->id != 0xffffffff)
1172 return rte_flow_error_set(error, ENOTSUP,
1173 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1175 "no support for partial mask on"
1177 ret = mlx5_flow_item_acceptable
1178 (item, (const uint8_t *)mask,
1179 (const uint8_t *)&rte_flow_item_port_id_mask,
1180 sizeof(struct rte_flow_item_port_id),
1186 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1188 return rte_flow_error_set(error, rte_errno,
1189 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1190 "failed to obtain E-Switch info for"
1192 dev_priv = mlx5_dev_to_eswitch_info(dev);
1194 return rte_flow_error_set(error, rte_errno,
1195 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1197 "failed to obtain E-Switch info");
1198 if (esw_priv->domain_id != dev_priv->domain_id)
1199 return rte_flow_error_set(error, EINVAL,
1200 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1201 "cannot match on a port from a"
1202 " different E-Switch");
1207 * Validate the pop VLAN action.
1210 * Pointer to the rte_eth_dev structure.
1211 * @param[in] action_flags
1212 * Holds the actions detected until now.
1214 * Pointer to the pop vlan action.
1215 * @param[in] item_flags
1216 * The items found in this flow rule.
1218 * Pointer to flow attributes.
1220 * Pointer to error structure.
1223 * 0 on success, a negative errno value otherwise and rte_errno is set.
1226 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1227 uint64_t action_flags,
1228 const struct rte_flow_action *action,
1229 uint64_t item_flags,
1230 const struct rte_flow_attr *attr,
1231 struct rte_flow_error *error)
1233 struct mlx5_priv *priv = dev->data->dev_private;
1237 if (!priv->sh->pop_vlan_action)
1238 return rte_flow_error_set(error, ENOTSUP,
1239 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1241 "pop vlan action is not supported");
1243 * Check for inconsistencies:
1244 * fail strip_vlan in a flow that matches packets without VLAN tags.
1245 * fail strip_vlan in a flow that matches packets without explicitly a
1246 * matching on VLAN tag ?
1248 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1249 return rte_flow_error_set(error, ENOTSUP,
1250 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1252 "no support for multiple vlan pop "
1254 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1255 return rte_flow_error_set(error, ENOTSUP,
1256 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1258 "cannot pop vlan without a "
1259 "match on (outer) vlan in the flow");
1260 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1261 return rte_flow_error_set(error, EINVAL,
1262 RTE_FLOW_ERROR_TYPE_ACTION, action,
1263 "wrong action order, port_id should "
1264 "be after pop VLAN action");
1269 * Get VLAN default info from vlan match info.
1272 * Pointer to the rte_eth_dev structure.
1274 * the list of item specifications.
1276 * pointer VLAN info to fill to.
1278 * Pointer to error structure.
1281 * 0 on success, a negative errno value otherwise and rte_errno is set.
1284 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1285 struct rte_vlan_hdr *vlan)
1287 const struct rte_flow_item_vlan nic_mask = {
1288 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1289 MLX5DV_FLOW_VLAN_VID_MASK),
1290 .inner_type = RTE_BE16(0xffff),
1295 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1296 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1298 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1299 const struct rte_flow_item_vlan *vlan_m = items->mask;
1300 const struct rte_flow_item_vlan *vlan_v = items->spec;
1304 /* Only full match values are accepted */
1305 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1306 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1307 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1309 rte_be_to_cpu_16(vlan_v->tci &
1310 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1312 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1313 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1314 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1316 rte_be_to_cpu_16(vlan_v->tci &
1317 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1319 if (vlan_m->inner_type == nic_mask.inner_type)
1320 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1321 vlan_m->inner_type);
1326 * Validate the push VLAN action.
1328 * @param[in] action_flags
1329 * Holds the actions detected until now.
1331 * Pointer to the encap action.
1333 * Pointer to flow attributes
1335 * Pointer to error structure.
1338 * 0 on success, a negative errno value otherwise and rte_errno is set.
1341 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1342 uint64_t item_flags,
1343 const struct rte_flow_action *action,
1344 const struct rte_flow_attr *attr,
1345 struct rte_flow_error *error)
1347 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1349 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1350 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1351 return rte_flow_error_set(error, EINVAL,
1352 RTE_FLOW_ERROR_TYPE_ACTION, action,
1353 "invalid vlan ethertype");
1355 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1356 return rte_flow_error_set(error, ENOTSUP,
1357 RTE_FLOW_ERROR_TYPE_ACTION, action,
1358 "no support for multiple VLAN "
1360 if (!mlx5_flow_find_action
1361 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1362 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1363 return rte_flow_error_set(error, ENOTSUP,
1364 RTE_FLOW_ERROR_TYPE_ACTION, action,
1365 "push VLAN needs to match on VLAN in order to "
1366 "get VLAN VID information because there is "
1367 "no followed set VLAN VID action");
1368 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1369 return rte_flow_error_set(error, EINVAL,
1370 RTE_FLOW_ERROR_TYPE_ACTION, action,
1371 "wrong action order, port_id should "
1372 "be after push VLAN");
1378 * Validate the set VLAN PCP.
1380 * @param[in] action_flags
1381 * Holds the actions detected until now.
1382 * @param[in] actions
1383 * Pointer to the list of actions remaining in the flow rule.
1385 * Pointer to flow attributes
1387 * Pointer to error structure.
1390 * 0 on success, a negative errno value otherwise and rte_errno is set.
1393 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1394 const struct rte_flow_action actions[],
1395 struct rte_flow_error *error)
1397 const struct rte_flow_action *action = actions;
1398 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1400 if (conf->vlan_pcp > 7)
1401 return rte_flow_error_set(error, EINVAL,
1402 RTE_FLOW_ERROR_TYPE_ACTION, action,
1403 "VLAN PCP value is too big");
1404 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1405 return rte_flow_error_set(error, ENOTSUP,
1406 RTE_FLOW_ERROR_TYPE_ACTION, action,
1407 "set VLAN PCP action must follow "
1408 "the push VLAN action");
1409 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1410 return rte_flow_error_set(error, ENOTSUP,
1411 RTE_FLOW_ERROR_TYPE_ACTION, action,
1412 "Multiple VLAN PCP modification are "
1414 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1415 return rte_flow_error_set(error, EINVAL,
1416 RTE_FLOW_ERROR_TYPE_ACTION, action,
1417 "wrong action order, port_id should "
1418 "be after set VLAN PCP");
1423 * Validate the set VLAN VID.
1425 * @param[in] item_flags
1426 * Holds the items detected in this rule.
1427 * @param[in] actions
1428 * Pointer to the list of actions remaining in the flow rule.
1430 * Pointer to flow attributes
1432 * Pointer to error structure.
1435 * 0 on success, a negative errno value otherwise and rte_errno is set.
1438 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1439 uint64_t action_flags,
1440 const struct rte_flow_action actions[],
1441 struct rte_flow_error *error)
1443 const struct rte_flow_action *action = actions;
1444 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1446 if (conf->vlan_vid > RTE_BE16(0xFFE))
1447 return rte_flow_error_set(error, EINVAL,
1448 RTE_FLOW_ERROR_TYPE_ACTION, action,
1449 "VLAN VID value is too big");
1450 /* there is an of_push_vlan action before us */
1451 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1452 if (mlx5_flow_find_action(actions + 1,
1453 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1454 return rte_flow_error_set(error, ENOTSUP,
1455 RTE_FLOW_ERROR_TYPE_ACTION, action,
1456 "Multiple VLAN VID modifications are "
1463 * Action is on an existing VLAN header:
1464 * Need to verify this is a single modify CID action.
1465 * Rule mast include a match on outer VLAN.
1467 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1468 return rte_flow_error_set(error, ENOTSUP,
1469 RTE_FLOW_ERROR_TYPE_ACTION, action,
1470 "Multiple VLAN VID modifications are "
1472 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1473 return rte_flow_error_set(error, EINVAL,
1474 RTE_FLOW_ERROR_TYPE_ACTION, action,
1475 "match on VLAN is required in order "
1477 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1478 return rte_flow_error_set(error, EINVAL,
1479 RTE_FLOW_ERROR_TYPE_ACTION, action,
1480 "wrong action order, port_id should "
1481 "be after set VLAN VID");
1486 * Validate SET_TAG action.
1489 * Pointer to the rte_eth_dev structure.
1491 * Pointer to the encap action.
1492 * @param[in] action_flags
1493 * Holds the actions detected until now.
1495 * Pointer to flow attributes
1497 * Pointer to error structure.
1500 * 0 on success, a negative errno value otherwise and rte_errno is set.
1503 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
1504 const struct rte_flow_action *action,
1505 uint64_t action_flags,
1506 const struct rte_flow_attr *attr,
1507 struct rte_flow_error *error)
1509 const struct rte_flow_action_set_tag *conf;
1510 const uint64_t terminal_action_flags =
1511 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
1512 MLX5_FLOW_ACTION_RSS;
1515 if (!mlx5_flow_ext_mreg_supported(dev))
1516 return rte_flow_error_set(error, ENOTSUP,
1517 RTE_FLOW_ERROR_TYPE_ACTION, action,
1518 "extensive metadata register"
1519 " isn't supported");
1520 if (!(action->conf))
1521 return rte_flow_error_set(error, EINVAL,
1522 RTE_FLOW_ERROR_TYPE_ACTION, action,
1523 "configuration cannot be null");
1524 conf = (const struct rte_flow_action_set_tag *)action->conf;
1526 return rte_flow_error_set(error, EINVAL,
1527 RTE_FLOW_ERROR_TYPE_ACTION, action,
1528 "zero mask doesn't have any effect");
1529 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1532 if (!attr->transfer && attr->ingress &&
1533 (action_flags & terminal_action_flags))
1534 return rte_flow_error_set(error, EINVAL,
1535 RTE_FLOW_ERROR_TYPE_ACTION, action,
1536 "set_tag has no effect"
1537 " with terminal actions");
1542 * Validate count action.
1547 * Pointer to error structure.
1550 * 0 on success, a negative errno value otherwise and rte_errno is set.
1553 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1554 struct rte_flow_error *error)
1556 struct mlx5_priv *priv = dev->data->dev_private;
1558 if (!priv->config.devx)
1560 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1564 return rte_flow_error_set
1566 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1568 "count action not supported");
1572 * Validate the L2 encap action.
1574 * @param[in] action_flags
1575 * Holds the actions detected until now.
1577 * Pointer to the encap action.
1579 * Pointer to flow attributes
1581 * Pointer to error structure.
1584 * 0 on success, a negative errno value otherwise and rte_errno is set.
1587 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1588 const struct rte_flow_action *action,
1589 const struct rte_flow_attr *attr,
1590 struct rte_flow_error *error)
1592 if (!(action->conf))
1593 return rte_flow_error_set(error, EINVAL,
1594 RTE_FLOW_ERROR_TYPE_ACTION, action,
1595 "configuration cannot be null");
1596 if (action_flags & MLX5_FLOW_ACTION_DROP)
1597 return rte_flow_error_set(error, EINVAL,
1598 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1599 "can't drop and encap in same flow");
1600 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1601 return rte_flow_error_set(error, EINVAL,
1602 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1603 "can only have a single encap or"
1604 " decap action in a flow");
1605 if (!attr->transfer && attr->ingress)
1606 return rte_flow_error_set(error, ENOTSUP,
1607 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1609 "encap action not supported for "
1615 * Validate the L2 decap action.
1617 * @param[in] action_flags
1618 * Holds the actions detected until now.
1620 * Pointer to flow attributes
1622 * Pointer to error structure.
1625 * 0 on success, a negative errno value otherwise and rte_errno is set.
1628 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1629 const struct rte_flow_attr *attr,
1630 struct rte_flow_error *error)
1632 if (action_flags & MLX5_FLOW_ACTION_DROP)
1633 return rte_flow_error_set(error, EINVAL,
1634 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1635 "can't drop and decap in same flow");
1636 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1637 return rte_flow_error_set(error, EINVAL,
1638 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1639 "can only have a single encap or"
1640 " decap action in a flow");
1641 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1642 return rte_flow_error_set(error, EINVAL,
1643 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1644 "can't have decap action after"
1647 return rte_flow_error_set(error, ENOTSUP,
1648 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1650 "decap action not supported for "
1656 * Validate the raw encap action.
1658 * @param[in] action_flags
1659 * Holds the actions detected until now.
1661 * Pointer to the encap action.
1663 * Pointer to flow attributes
1665 * Pointer to error structure.
1668 * 0 on success, a negative errno value otherwise and rte_errno is set.
1671 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1672 const struct rte_flow_action *action,
1673 const struct rte_flow_attr *attr,
1674 struct rte_flow_error *error)
1676 const struct rte_flow_action_raw_encap *raw_encap =
1677 (const struct rte_flow_action_raw_encap *)action->conf;
1678 if (!(action->conf))
1679 return rte_flow_error_set(error, EINVAL,
1680 RTE_FLOW_ERROR_TYPE_ACTION, action,
1681 "configuration cannot be null");
1682 if (action_flags & MLX5_FLOW_ACTION_DROP)
1683 return rte_flow_error_set(error, EINVAL,
1684 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1685 "can't drop and encap in same flow");
1686 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1687 return rte_flow_error_set(error, EINVAL,
1688 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1689 "can only have a single encap"
1690 " action in a flow");
1691 /* encap without preceding decap is not supported for ingress */
1692 if (!attr->transfer && attr->ingress &&
1693 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1694 return rte_flow_error_set(error, ENOTSUP,
1695 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1697 "encap action not supported for "
1699 if (!raw_encap->size || !raw_encap->data)
1700 return rte_flow_error_set(error, EINVAL,
1701 RTE_FLOW_ERROR_TYPE_ACTION, action,
1702 "raw encap data cannot be empty");
1707 * Validate the raw decap action.
1709 * @param[in] action_flags
1710 * Holds the actions detected until now.
1712 * Pointer to the encap action.
1714 * Pointer to flow attributes
1716 * Pointer to error structure.
1719 * 0 on success, a negative errno value otherwise and rte_errno is set.
1722 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1723 const struct rte_flow_action *action,
1724 const struct rte_flow_attr *attr,
1725 struct rte_flow_error *error)
1727 if (action_flags & MLX5_FLOW_ACTION_DROP)
1728 return rte_flow_error_set(error, EINVAL,
1729 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1730 "can't drop and decap in same flow");
1731 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1732 return rte_flow_error_set(error, EINVAL,
1733 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1734 "can't have encap action before"
1736 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1737 return rte_flow_error_set(error, EINVAL,
1738 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1739 "can only have a single decap"
1740 " action in a flow");
1741 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1742 return rte_flow_error_set(error, EINVAL,
1743 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1744 "can't have decap action after"
1746 /* decap action is valid on egress only if it is followed by encap */
1748 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1749 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1752 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1753 return rte_flow_error_set
1755 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1756 NULL, "decap action not supported"
1763 * Find existing encap/decap resource or create and register a new one.
1765 * @param dev[in, out]
1766 * Pointer to rte_eth_dev structure.
1767 * @param[in, out] resource
1768 * Pointer to encap/decap resource.
1769 * @parm[in, out] dev_flow
1770 * Pointer to the dev_flow.
1772 * pointer to error structure.
1775 * 0 on success otherwise -errno and errno is set.
1778 flow_dv_encap_decap_resource_register
1779 (struct rte_eth_dev *dev,
1780 struct mlx5_flow_dv_encap_decap_resource *resource,
1781 struct mlx5_flow *dev_flow,
1782 struct rte_flow_error *error)
1784 struct mlx5_priv *priv = dev->data->dev_private;
1785 struct mlx5_ibv_shared *sh = priv->sh;
1786 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1787 struct mlx5dv_dr_domain *domain;
1789 resource->flags = dev_flow->group ? 0 : 1;
1790 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1791 domain = sh->fdb_domain;
1792 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1793 domain = sh->rx_domain;
1795 domain = sh->tx_domain;
1797 /* Lookup a matching resource from cache. */
1798 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1799 if (resource->reformat_type == cache_resource->reformat_type &&
1800 resource->ft_type == cache_resource->ft_type &&
1801 resource->flags == cache_resource->flags &&
1802 resource->size == cache_resource->size &&
1803 !memcmp((const void *)resource->buf,
1804 (const void *)cache_resource->buf,
1806 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1807 (void *)cache_resource,
1808 rte_atomic32_read(&cache_resource->refcnt));
1809 rte_atomic32_inc(&cache_resource->refcnt);
1810 dev_flow->dv.encap_decap = cache_resource;
1814 /* Register new encap/decap resource. */
1815 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1816 if (!cache_resource)
1817 return rte_flow_error_set(error, ENOMEM,
1818 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1819 "cannot allocate resource memory");
1820 *cache_resource = *resource;
1821 cache_resource->verbs_action =
1822 mlx5_glue->dv_create_flow_action_packet_reformat
1823 (sh->ctx, cache_resource->reformat_type,
1824 cache_resource->ft_type, domain, cache_resource->flags,
1825 cache_resource->size,
1826 (cache_resource->size ? cache_resource->buf : NULL));
1827 if (!cache_resource->verbs_action) {
1828 rte_free(cache_resource);
1829 return rte_flow_error_set(error, ENOMEM,
1830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1831 NULL, "cannot create action");
1833 rte_atomic32_init(&cache_resource->refcnt);
1834 rte_atomic32_inc(&cache_resource->refcnt);
1835 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1836 dev_flow->dv.encap_decap = cache_resource;
1837 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1838 (void *)cache_resource,
1839 rte_atomic32_read(&cache_resource->refcnt));
1844 * Find existing table jump resource or create and register a new one.
1846 * @param dev[in, out]
1847 * Pointer to rte_eth_dev structure.
1848 * @param[in, out] resource
1849 * Pointer to jump table resource.
1850 * @parm[in, out] dev_flow
1851 * Pointer to the dev_flow.
1853 * pointer to error structure.
1856 * 0 on success otherwise -errno and errno is set.
1859 flow_dv_jump_tbl_resource_register
1860 (struct rte_eth_dev *dev,
1861 struct mlx5_flow_dv_jump_tbl_resource *resource,
1862 struct mlx5_flow *dev_flow,
1863 struct rte_flow_error *error)
1865 struct mlx5_priv *priv = dev->data->dev_private;
1866 struct mlx5_ibv_shared *sh = priv->sh;
1867 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1869 /* Lookup a matching resource from cache. */
1870 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1871 if (resource->tbl == cache_resource->tbl) {
1872 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1873 (void *)cache_resource,
1874 rte_atomic32_read(&cache_resource->refcnt));
1875 rte_atomic32_inc(&cache_resource->refcnt);
1876 dev_flow->dv.jump = cache_resource;
1880 /* Register new jump table resource. */
1881 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1882 if (!cache_resource)
1883 return rte_flow_error_set(error, ENOMEM,
1884 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1885 "cannot allocate resource memory");
1886 *cache_resource = *resource;
1887 cache_resource->action =
1888 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1889 (resource->tbl->obj);
1890 if (!cache_resource->action) {
1891 rte_free(cache_resource);
1892 return rte_flow_error_set(error, ENOMEM,
1893 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1894 NULL, "cannot create action");
1896 rte_atomic32_init(&cache_resource->refcnt);
1897 rte_atomic32_inc(&cache_resource->refcnt);
1898 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1899 dev_flow->dv.jump = cache_resource;
1900 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1901 (void *)cache_resource,
1902 rte_atomic32_read(&cache_resource->refcnt));
1907 * Find existing table port ID resource or create and register a new one.
1909 * @param dev[in, out]
1910 * Pointer to rte_eth_dev structure.
1911 * @param[in, out] resource
1912 * Pointer to port ID action resource.
1913 * @parm[in, out] dev_flow
1914 * Pointer to the dev_flow.
1916 * pointer to error structure.
1919 * 0 on success otherwise -errno and errno is set.
1922 flow_dv_port_id_action_resource_register
1923 (struct rte_eth_dev *dev,
1924 struct mlx5_flow_dv_port_id_action_resource *resource,
1925 struct mlx5_flow *dev_flow,
1926 struct rte_flow_error *error)
1928 struct mlx5_priv *priv = dev->data->dev_private;
1929 struct mlx5_ibv_shared *sh = priv->sh;
1930 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1932 /* Lookup a matching resource from cache. */
1933 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1934 if (resource->port_id == cache_resource->port_id) {
1935 DRV_LOG(DEBUG, "port id action resource resource %p: "
1937 (void *)cache_resource,
1938 rte_atomic32_read(&cache_resource->refcnt));
1939 rte_atomic32_inc(&cache_resource->refcnt);
1940 dev_flow->dv.port_id_action = cache_resource;
1944 /* Register new port id action resource. */
1945 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1946 if (!cache_resource)
1947 return rte_flow_error_set(error, ENOMEM,
1948 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1949 "cannot allocate resource memory");
1950 *cache_resource = *resource;
1951 cache_resource->action =
1952 mlx5_glue->dr_create_flow_action_dest_vport
1953 (priv->sh->fdb_domain, resource->port_id);
1954 if (!cache_resource->action) {
1955 rte_free(cache_resource);
1956 return rte_flow_error_set(error, ENOMEM,
1957 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1958 NULL, "cannot create action");
1960 rte_atomic32_init(&cache_resource->refcnt);
1961 rte_atomic32_inc(&cache_resource->refcnt);
1962 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1963 dev_flow->dv.port_id_action = cache_resource;
1964 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1965 (void *)cache_resource,
1966 rte_atomic32_read(&cache_resource->refcnt));
1971 * Find existing push vlan resource or create and register a new one.
1973 * @param dev[in, out]
1974 * Pointer to rte_eth_dev structure.
1975 * @param[in, out] resource
1976 * Pointer to port ID action resource.
1977 * @parm[in, out] dev_flow
1978 * Pointer to the dev_flow.
1980 * pointer to error structure.
1983 * 0 on success otherwise -errno and errno is set.
1986 flow_dv_push_vlan_action_resource_register
1987 (struct rte_eth_dev *dev,
1988 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1989 struct mlx5_flow *dev_flow,
1990 struct rte_flow_error *error)
1992 struct mlx5_priv *priv = dev->data->dev_private;
1993 struct mlx5_ibv_shared *sh = priv->sh;
1994 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1995 struct mlx5dv_dr_domain *domain;
1997 /* Lookup a matching resource from cache. */
1998 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1999 if (resource->vlan_tag == cache_resource->vlan_tag &&
2000 resource->ft_type == cache_resource->ft_type) {
2001 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2003 (void *)cache_resource,
2004 rte_atomic32_read(&cache_resource->refcnt));
2005 rte_atomic32_inc(&cache_resource->refcnt);
2006 dev_flow->dv.push_vlan_res = cache_resource;
2010 /* Register new push_vlan action resource. */
2011 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2012 if (!cache_resource)
2013 return rte_flow_error_set(error, ENOMEM,
2014 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2015 "cannot allocate resource memory");
2016 *cache_resource = *resource;
2017 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2018 domain = sh->fdb_domain;
2019 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2020 domain = sh->rx_domain;
2022 domain = sh->tx_domain;
2023 cache_resource->action =
2024 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2025 resource->vlan_tag);
2026 if (!cache_resource->action) {
2027 rte_free(cache_resource);
2028 return rte_flow_error_set(error, ENOMEM,
2029 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2030 NULL, "cannot create action");
2032 rte_atomic32_init(&cache_resource->refcnt);
2033 rte_atomic32_inc(&cache_resource->refcnt);
2034 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2035 dev_flow->dv.push_vlan_res = cache_resource;
2036 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2037 (void *)cache_resource,
2038 rte_atomic32_read(&cache_resource->refcnt));
2042 * Get the size of specific rte_flow_item_type
2044 * @param[in] item_type
2045 * Tested rte_flow_item_type.
2048 * sizeof struct item_type, 0 if void or irrelevant.
2051 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2055 switch (item_type) {
2056 case RTE_FLOW_ITEM_TYPE_ETH:
2057 retval = sizeof(struct rte_flow_item_eth);
2059 case RTE_FLOW_ITEM_TYPE_VLAN:
2060 retval = sizeof(struct rte_flow_item_vlan);
2062 case RTE_FLOW_ITEM_TYPE_IPV4:
2063 retval = sizeof(struct rte_flow_item_ipv4);
2065 case RTE_FLOW_ITEM_TYPE_IPV6:
2066 retval = sizeof(struct rte_flow_item_ipv6);
2068 case RTE_FLOW_ITEM_TYPE_UDP:
2069 retval = sizeof(struct rte_flow_item_udp);
2071 case RTE_FLOW_ITEM_TYPE_TCP:
2072 retval = sizeof(struct rte_flow_item_tcp);
2074 case RTE_FLOW_ITEM_TYPE_VXLAN:
2075 retval = sizeof(struct rte_flow_item_vxlan);
2077 case RTE_FLOW_ITEM_TYPE_GRE:
2078 retval = sizeof(struct rte_flow_item_gre);
2080 case RTE_FLOW_ITEM_TYPE_NVGRE:
2081 retval = sizeof(struct rte_flow_item_nvgre);
2083 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2084 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2086 case RTE_FLOW_ITEM_TYPE_MPLS:
2087 retval = sizeof(struct rte_flow_item_mpls);
2089 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2097 #define MLX5_ENCAP_IPV4_VERSION 0x40
2098 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2099 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2100 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2101 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2102 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2103 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2106 * Convert the encap action data from list of rte_flow_item to raw buffer
2109 * Pointer to rte_flow_item objects list.
2111 * Pointer to the output buffer.
2113 * Pointer to the output buffer size.
2115 * Pointer to the error structure.
2118 * 0 on success, a negative errno value otherwise and rte_errno is set.
2121 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2122 size_t *size, struct rte_flow_error *error)
2124 struct rte_ether_hdr *eth = NULL;
2125 struct rte_vlan_hdr *vlan = NULL;
2126 struct rte_ipv4_hdr *ipv4 = NULL;
2127 struct rte_ipv6_hdr *ipv6 = NULL;
2128 struct rte_udp_hdr *udp = NULL;
2129 struct rte_vxlan_hdr *vxlan = NULL;
2130 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2131 struct rte_gre_hdr *gre = NULL;
2133 size_t temp_size = 0;
2136 return rte_flow_error_set(error, EINVAL,
2137 RTE_FLOW_ERROR_TYPE_ACTION,
2138 NULL, "invalid empty data");
2139 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2140 len = flow_dv_get_item_len(items->type);
2141 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2142 return rte_flow_error_set(error, EINVAL,
2143 RTE_FLOW_ERROR_TYPE_ACTION,
2144 (void *)items->type,
2145 "items total size is too big"
2146 " for encap action");
2147 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2148 switch (items->type) {
2149 case RTE_FLOW_ITEM_TYPE_ETH:
2150 eth = (struct rte_ether_hdr *)&buf[temp_size];
2152 case RTE_FLOW_ITEM_TYPE_VLAN:
2153 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2155 return rte_flow_error_set(error, EINVAL,
2156 RTE_FLOW_ERROR_TYPE_ACTION,
2157 (void *)items->type,
2158 "eth header not found");
2159 if (!eth->ether_type)
2160 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2162 case RTE_FLOW_ITEM_TYPE_IPV4:
2163 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2165 return rte_flow_error_set(error, EINVAL,
2166 RTE_FLOW_ERROR_TYPE_ACTION,
2167 (void *)items->type,
2168 "neither eth nor vlan"
2170 if (vlan && !vlan->eth_proto)
2171 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2172 else if (eth && !eth->ether_type)
2173 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2174 if (!ipv4->version_ihl)
2175 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2176 MLX5_ENCAP_IPV4_IHL_MIN;
2177 if (!ipv4->time_to_live)
2178 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2180 case RTE_FLOW_ITEM_TYPE_IPV6:
2181 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2183 return rte_flow_error_set(error, EINVAL,
2184 RTE_FLOW_ERROR_TYPE_ACTION,
2185 (void *)items->type,
2186 "neither eth nor vlan"
2188 if (vlan && !vlan->eth_proto)
2189 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2190 else if (eth && !eth->ether_type)
2191 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2192 if (!ipv6->vtc_flow)
2194 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2195 if (!ipv6->hop_limits)
2196 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2198 case RTE_FLOW_ITEM_TYPE_UDP:
2199 udp = (struct rte_udp_hdr *)&buf[temp_size];
2201 return rte_flow_error_set(error, EINVAL,
2202 RTE_FLOW_ERROR_TYPE_ACTION,
2203 (void *)items->type,
2204 "ip header not found");
2205 if (ipv4 && !ipv4->next_proto_id)
2206 ipv4->next_proto_id = IPPROTO_UDP;
2207 else if (ipv6 && !ipv6->proto)
2208 ipv6->proto = IPPROTO_UDP;
2210 case RTE_FLOW_ITEM_TYPE_VXLAN:
2211 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2213 return rte_flow_error_set(error, EINVAL,
2214 RTE_FLOW_ERROR_TYPE_ACTION,
2215 (void *)items->type,
2216 "udp header not found");
2218 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2219 if (!vxlan->vx_flags)
2221 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2223 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2224 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2226 return rte_flow_error_set(error, EINVAL,
2227 RTE_FLOW_ERROR_TYPE_ACTION,
2228 (void *)items->type,
2229 "udp header not found");
2230 if (!vxlan_gpe->proto)
2231 return rte_flow_error_set(error, EINVAL,
2232 RTE_FLOW_ERROR_TYPE_ACTION,
2233 (void *)items->type,
2234 "next protocol not found");
2237 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2238 if (!vxlan_gpe->vx_flags)
2239 vxlan_gpe->vx_flags =
2240 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2242 case RTE_FLOW_ITEM_TYPE_GRE:
2243 case RTE_FLOW_ITEM_TYPE_NVGRE:
2244 gre = (struct rte_gre_hdr *)&buf[temp_size];
2246 return rte_flow_error_set(error, EINVAL,
2247 RTE_FLOW_ERROR_TYPE_ACTION,
2248 (void *)items->type,
2249 "next protocol not found");
2251 return rte_flow_error_set(error, EINVAL,
2252 RTE_FLOW_ERROR_TYPE_ACTION,
2253 (void *)items->type,
2254 "ip header not found");
2255 if (ipv4 && !ipv4->next_proto_id)
2256 ipv4->next_proto_id = IPPROTO_GRE;
2257 else if (ipv6 && !ipv6->proto)
2258 ipv6->proto = IPPROTO_GRE;
2260 case RTE_FLOW_ITEM_TYPE_VOID:
2263 return rte_flow_error_set(error, EINVAL,
2264 RTE_FLOW_ERROR_TYPE_ACTION,
2265 (void *)items->type,
2266 "unsupported item type");
2276 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2278 struct rte_ether_hdr *eth = NULL;
2279 struct rte_vlan_hdr *vlan = NULL;
2280 struct rte_ipv6_hdr *ipv6 = NULL;
2281 struct rte_udp_hdr *udp = NULL;
2285 eth = (struct rte_ether_hdr *)data;
2286 next_hdr = (char *)(eth + 1);
2287 proto = RTE_BE16(eth->ether_type);
2290 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2291 vlan = (struct rte_vlan_hdr *)next_hdr;
2292 proto = RTE_BE16(vlan->eth_proto);
2293 next_hdr += sizeof(struct rte_vlan_hdr);
2296 /* HW calculates IPv4 csum. no need to proceed */
2297 if (proto == RTE_ETHER_TYPE_IPV4)
2300 /* non IPv4/IPv6 header. not supported */
2301 if (proto != RTE_ETHER_TYPE_IPV6) {
2302 return rte_flow_error_set(error, ENOTSUP,
2303 RTE_FLOW_ERROR_TYPE_ACTION,
2304 NULL, "Cannot offload non IPv4/IPv6");
2307 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2309 /* ignore non UDP */
2310 if (ipv6->proto != IPPROTO_UDP)
2313 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2314 udp->dgram_cksum = 0;
2320 * Convert L2 encap action to DV specification.
2323 * Pointer to rte_eth_dev structure.
2325 * Pointer to action structure.
2326 * @param[in, out] dev_flow
2327 * Pointer to the mlx5_flow.
2328 * @param[in] transfer
2329 * Mark if the flow is E-Switch flow.
2331 * Pointer to the error structure.
2334 * 0 on success, a negative errno value otherwise and rte_errno is set.
2337 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2338 const struct rte_flow_action *action,
2339 struct mlx5_flow *dev_flow,
2341 struct rte_flow_error *error)
2343 const struct rte_flow_item *encap_data;
2344 const struct rte_flow_action_raw_encap *raw_encap_data;
2345 struct mlx5_flow_dv_encap_decap_resource res = {
2347 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2348 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2349 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2352 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2354 (const struct rte_flow_action_raw_encap *)action->conf;
2355 res.size = raw_encap_data->size;
2356 memcpy(res.buf, raw_encap_data->data, res.size);
2357 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2360 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2362 ((const struct rte_flow_action_vxlan_encap *)
2363 action->conf)->definition;
2366 ((const struct rte_flow_action_nvgre_encap *)
2367 action->conf)->definition;
2368 if (flow_dv_convert_encap_data(encap_data, res.buf,
2372 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2373 return rte_flow_error_set(error, EINVAL,
2374 RTE_FLOW_ERROR_TYPE_ACTION,
2375 NULL, "can't create L2 encap action");
2380 * Convert L2 decap action to DV specification.
2383 * Pointer to rte_eth_dev structure.
2384 * @param[in, out] dev_flow
2385 * Pointer to the mlx5_flow.
2386 * @param[in] transfer
2387 * Mark if the flow is E-Switch flow.
2389 * Pointer to the error structure.
2392 * 0 on success, a negative errno value otherwise and rte_errno is set.
2395 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2396 struct mlx5_flow *dev_flow,
2398 struct rte_flow_error *error)
2400 struct mlx5_flow_dv_encap_decap_resource res = {
2403 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2404 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2405 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2408 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2409 return rte_flow_error_set(error, EINVAL,
2410 RTE_FLOW_ERROR_TYPE_ACTION,
2411 NULL, "can't create L2 decap action");
2416 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2419 * Pointer to rte_eth_dev structure.
2421 * Pointer to action structure.
2422 * @param[in, out] dev_flow
2423 * Pointer to the mlx5_flow.
2425 * Pointer to the flow attributes.
2427 * Pointer to the error structure.
2430 * 0 on success, a negative errno value otherwise and rte_errno is set.
2433 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2434 const struct rte_flow_action *action,
2435 struct mlx5_flow *dev_flow,
2436 const struct rte_flow_attr *attr,
2437 struct rte_flow_error *error)
2439 const struct rte_flow_action_raw_encap *encap_data;
2440 struct mlx5_flow_dv_encap_decap_resource res;
2442 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2443 res.size = encap_data->size;
2444 memcpy(res.buf, encap_data->data, res.size);
2445 res.reformat_type = attr->egress ?
2446 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2447 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2449 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2451 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2452 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2453 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2454 return rte_flow_error_set(error, EINVAL,
2455 RTE_FLOW_ERROR_TYPE_ACTION,
2456 NULL, "can't create encap action");
2461 * Create action push VLAN.
2464 * Pointer to rte_eth_dev structure.
2465 * @param[in] vlan_tag
2466 * the vlan tag to push to the Ethernet header.
2467 * @param[in, out] dev_flow
2468 * Pointer to the mlx5_flow.
2470 * Pointer to the flow attributes.
2472 * Pointer to the error structure.
2475 * 0 on success, a negative errno value otherwise and rte_errno is set.
2478 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2479 const struct rte_flow_attr *attr,
2480 const struct rte_vlan_hdr *vlan,
2481 struct mlx5_flow *dev_flow,
2482 struct rte_flow_error *error)
2484 struct mlx5_flow_dv_push_vlan_action_resource res;
2487 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2490 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2492 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2493 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2494 return flow_dv_push_vlan_action_resource_register
2495 (dev, &res, dev_flow, error);
2499 * Validate the modify-header actions.
2501 * @param[in] action_flags
2502 * Holds the actions detected until now.
2504 * Pointer to the modify action.
2506 * Pointer to error structure.
2509 * 0 on success, a negative errno value otherwise and rte_errno is set.
2512 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2513 const struct rte_flow_action *action,
2514 struct rte_flow_error *error)
2516 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2517 return rte_flow_error_set(error, EINVAL,
2518 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2519 NULL, "action configuration not set");
2520 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2521 return rte_flow_error_set(error, EINVAL,
2522 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2523 "can't have encap action before"
2529 * Validate the modify-header MAC address actions.
2531 * @param[in] action_flags
2532 * Holds the actions detected until now.
2534 * Pointer to the modify action.
2535 * @param[in] item_flags
2536 * Holds the items detected.
2538 * Pointer to error structure.
2541 * 0 on success, a negative errno value otherwise and rte_errno is set.
2544 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2545 const struct rte_flow_action *action,
2546 const uint64_t item_flags,
2547 struct rte_flow_error *error)
2551 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2553 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2554 return rte_flow_error_set(error, EINVAL,
2555 RTE_FLOW_ERROR_TYPE_ACTION,
2557 "no L2 item in pattern");
2563 * Validate the modify-header IPv4 address actions.
2565 * @param[in] action_flags
2566 * Holds the actions detected until now.
2568 * Pointer to the modify action.
2569 * @param[in] item_flags
2570 * Holds the items detected.
2572 * Pointer to error structure.
2575 * 0 on success, a negative errno value otherwise and rte_errno is set.
2578 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2579 const struct rte_flow_action *action,
2580 const uint64_t item_flags,
2581 struct rte_flow_error *error)
2585 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2587 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2588 return rte_flow_error_set(error, EINVAL,
2589 RTE_FLOW_ERROR_TYPE_ACTION,
2591 "no ipv4 item in pattern");
2597 * Validate the modify-header IPv6 address actions.
2599 * @param[in] action_flags
2600 * Holds the actions detected until now.
2602 * Pointer to the modify action.
2603 * @param[in] item_flags
2604 * Holds the items detected.
2606 * Pointer to error structure.
2609 * 0 on success, a negative errno value otherwise and rte_errno is set.
2612 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2613 const struct rte_flow_action *action,
2614 const uint64_t item_flags,
2615 struct rte_flow_error *error)
2619 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2621 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2622 return rte_flow_error_set(error, EINVAL,
2623 RTE_FLOW_ERROR_TYPE_ACTION,
2625 "no ipv6 item in pattern");
2631 * Validate the modify-header TP actions.
2633 * @param[in] action_flags
2634 * Holds the actions detected until now.
2636 * Pointer to the modify action.
2637 * @param[in] item_flags
2638 * Holds the items detected.
2640 * Pointer to error structure.
2643 * 0 on success, a negative errno value otherwise and rte_errno is set.
2646 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2647 const struct rte_flow_action *action,
2648 const uint64_t item_flags,
2649 struct rte_flow_error *error)
2653 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2655 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2656 return rte_flow_error_set(error, EINVAL,
2657 RTE_FLOW_ERROR_TYPE_ACTION,
2658 NULL, "no transport layer "
2665 * Validate the modify-header actions of increment/decrement
2666 * TCP Sequence-number.
2668 * @param[in] action_flags
2669 * Holds the actions detected until now.
2671 * Pointer to the modify action.
2672 * @param[in] item_flags
2673 * Holds the items detected.
2675 * Pointer to error structure.
2678 * 0 on success, a negative errno value otherwise and rte_errno is set.
2681 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2682 const struct rte_flow_action *action,
2683 const uint64_t item_flags,
2684 struct rte_flow_error *error)
2688 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2690 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2691 return rte_flow_error_set(error, EINVAL,
2692 RTE_FLOW_ERROR_TYPE_ACTION,
2693 NULL, "no TCP item in"
2695 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2696 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2697 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2698 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2699 return rte_flow_error_set(error, EINVAL,
2700 RTE_FLOW_ERROR_TYPE_ACTION,
2702 "cannot decrease and increase"
2703 " TCP sequence number"
2704 " at the same time");
2710 * Validate the modify-header actions of increment/decrement
2711 * TCP Acknowledgment number.
2713 * @param[in] action_flags
2714 * Holds the actions detected until now.
2716 * Pointer to the modify action.
2717 * @param[in] item_flags
2718 * Holds the items detected.
2720 * Pointer to error structure.
2723 * 0 on success, a negative errno value otherwise and rte_errno is set.
2726 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2727 const struct rte_flow_action *action,
2728 const uint64_t item_flags,
2729 struct rte_flow_error *error)
2733 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2735 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2736 return rte_flow_error_set(error, EINVAL,
2737 RTE_FLOW_ERROR_TYPE_ACTION,
2738 NULL, "no TCP item in"
2740 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2741 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2742 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2743 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2744 return rte_flow_error_set(error, EINVAL,
2745 RTE_FLOW_ERROR_TYPE_ACTION,
2747 "cannot decrease and increase"
2748 " TCP acknowledgment number"
2749 " at the same time");
2755 * Validate the modify-header TTL actions.
2757 * @param[in] action_flags
2758 * Holds the actions detected until now.
2760 * Pointer to the modify action.
2761 * @param[in] item_flags
2762 * Holds the items detected.
2764 * Pointer to error structure.
2767 * 0 on success, a negative errno value otherwise and rte_errno is set.
2770 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2771 const struct rte_flow_action *action,
2772 const uint64_t item_flags,
2773 struct rte_flow_error *error)
2777 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2779 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2780 return rte_flow_error_set(error, EINVAL,
2781 RTE_FLOW_ERROR_TYPE_ACTION,
2783 "no IP protocol in pattern");
2789 * Validate jump action.
2792 * Pointer to the jump action.
2793 * @param[in] action_flags
2794 * Holds the actions detected until now.
2795 * @param[in] attributes
2796 * Pointer to flow attributes
2797 * @param[in] external
2798 * Action belongs to flow rule created by request external to PMD.
2800 * Pointer to error structure.
2803 * 0 on success, a negative errno value otherwise and rte_errno is set.
2806 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2807 uint64_t action_flags,
2808 const struct rte_flow_attr *attributes,
2809 bool external, struct rte_flow_error *error)
2811 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2813 uint32_t target_group, table;
2816 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2817 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2818 return rte_flow_error_set(error, EINVAL,
2819 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2820 "can't have 2 fate actions in"
2823 return rte_flow_error_set(error, EINVAL,
2824 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2825 NULL, "action configuration not set");
2827 ((const struct rte_flow_action_jump *)action->conf)->group;
2828 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2832 if (table >= max_group)
2833 return rte_flow_error_set(error, EINVAL,
2834 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2835 "target group index out of range");
2836 if (attributes->group >= target_group)
2837 return rte_flow_error_set(error, EINVAL,
2838 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2839 "target group must be higher than"
2840 " the current flow group");
2845 * Validate the port_id action.
2848 * Pointer to rte_eth_dev structure.
2849 * @param[in] action_flags
2850 * Bit-fields that holds the actions detected until now.
2852 * Port_id RTE action structure.
2854 * Attributes of flow that includes this action.
2856 * Pointer to error structure.
2859 * 0 on success, a negative errno value otherwise and rte_errno is set.
2862 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2863 uint64_t action_flags,
2864 const struct rte_flow_action *action,
2865 const struct rte_flow_attr *attr,
2866 struct rte_flow_error *error)
2868 const struct rte_flow_action_port_id *port_id;
2869 struct mlx5_priv *act_priv;
2870 struct mlx5_priv *dev_priv;
2873 if (!attr->transfer)
2874 return rte_flow_error_set(error, ENOTSUP,
2875 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2877 "port id action is valid in transfer"
2879 if (!action || !action->conf)
2880 return rte_flow_error_set(error, ENOTSUP,
2881 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2883 "port id action parameters must be"
2885 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2886 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2889 "can have only one fate actions in"
2891 dev_priv = mlx5_dev_to_eswitch_info(dev);
2893 return rte_flow_error_set(error, rte_errno,
2894 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2896 "failed to obtain E-Switch info");
2897 port_id = action->conf;
2898 port = port_id->original ? dev->data->port_id : port_id->id;
2899 act_priv = mlx5_port_to_eswitch_info(port, false);
2901 return rte_flow_error_set
2903 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2904 "failed to obtain E-Switch port id for port");
2905 if (act_priv->domain_id != dev_priv->domain_id)
2906 return rte_flow_error_set
2908 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2909 "port does not belong to"
2910 " E-Switch being configured");
2915 * Get the maximum number of modify header actions.
2918 * Pointer to rte_eth_dev structure.
2921 * Max number of modify header actions device can support.
2924 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev)
2927 * There's no way to directly query the max cap. Although it has to be
2928 * acquried by iterative trial, it is a safe assumption that more
2929 * actions are supported by FW if extensive metadata register is
2932 return mlx5_flow_ext_mreg_supported(dev) ? MLX5_MODIFY_NUM :
2933 MLX5_MODIFY_NUM_NO_MREG;
2936 * Find existing modify-header resource or create and register a new one.
2938 * @param dev[in, out]
2939 * Pointer to rte_eth_dev structure.
2940 * @param[in, out] resource
2941 * Pointer to modify-header resource.
2942 * @parm[in, out] dev_flow
2943 * Pointer to the dev_flow.
2945 * pointer to error structure.
2948 * 0 on success otherwise -errno and errno is set.
2951 flow_dv_modify_hdr_resource_register
2952 (struct rte_eth_dev *dev,
2953 struct mlx5_flow_dv_modify_hdr_resource *resource,
2954 struct mlx5_flow *dev_flow,
2955 struct rte_flow_error *error)
2957 struct mlx5_priv *priv = dev->data->dev_private;
2958 struct mlx5_ibv_shared *sh = priv->sh;
2959 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2960 struct mlx5dv_dr_domain *ns;
2962 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev))
2963 return rte_flow_error_set(error, EOVERFLOW,
2964 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2965 "too many modify header items");
2966 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2967 ns = sh->fdb_domain;
2968 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2973 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2974 /* Lookup a matching resource from cache. */
2975 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2976 if (resource->ft_type == cache_resource->ft_type &&
2977 resource->actions_num == cache_resource->actions_num &&
2978 resource->flags == cache_resource->flags &&
2979 !memcmp((const void *)resource->actions,
2980 (const void *)cache_resource->actions,
2981 (resource->actions_num *
2982 sizeof(resource->actions[0])))) {
2983 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2984 (void *)cache_resource,
2985 rte_atomic32_read(&cache_resource->refcnt));
2986 rte_atomic32_inc(&cache_resource->refcnt);
2987 dev_flow->dv.modify_hdr = cache_resource;
2991 /* Register new modify-header resource. */
2992 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2993 if (!cache_resource)
2994 return rte_flow_error_set(error, ENOMEM,
2995 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2996 "cannot allocate resource memory");
2997 *cache_resource = *resource;
2998 cache_resource->verbs_action =
2999 mlx5_glue->dv_create_flow_action_modify_header
3000 (sh->ctx, cache_resource->ft_type,
3001 ns, cache_resource->flags,
3002 cache_resource->actions_num *
3003 sizeof(cache_resource->actions[0]),
3004 (uint64_t *)cache_resource->actions);
3005 if (!cache_resource->verbs_action) {
3006 rte_free(cache_resource);
3007 return rte_flow_error_set(error, ENOMEM,
3008 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3009 NULL, "cannot create action");
3011 rte_atomic32_init(&cache_resource->refcnt);
3012 rte_atomic32_inc(&cache_resource->refcnt);
3013 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3014 dev_flow->dv.modify_hdr = cache_resource;
3015 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3016 (void *)cache_resource,
3017 rte_atomic32_read(&cache_resource->refcnt));
3021 #define MLX5_CNT_CONTAINER_RESIZE 64
3024 * Get or create a flow counter.
3027 * Pointer to the Ethernet device structure.
3029 * Indicate if this counter is shared with other flows.
3031 * Counter identifier.
3034 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3036 static struct mlx5_flow_counter *
3037 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3040 struct mlx5_priv *priv = dev->data->dev_private;
3041 struct mlx5_flow_counter *cnt = NULL;
3042 struct mlx5_devx_obj *dcs = NULL;
3044 if (!priv->config.devx) {
3045 rte_errno = ENOTSUP;
3049 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3050 if (cnt->shared && cnt->id == id) {
3056 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3059 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3061 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3065 struct mlx5_flow_counter tmpl = {
3071 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3073 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3079 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3084 * Release a flow counter.
3087 * Pointer to the Ethernet device structure.
3088 * @param[in] counter
3089 * Pointer to the counter handler.
3092 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3093 struct mlx5_flow_counter *counter)
3095 struct mlx5_priv *priv = dev->data->dev_private;
3099 if (--counter->ref_cnt == 0) {
3100 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3101 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3107 * Query a devx flow counter.
3110 * Pointer to the Ethernet device structure.
3112 * Pointer to the flow counter.
3114 * The statistics value of packets.
3116 * The statistics value of bytes.
3119 * 0 on success, otherwise a negative errno value and rte_errno is set.
3122 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3123 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3126 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3131 * Get a pool by a counter.
3134 * Pointer to the counter.
3139 static struct mlx5_flow_counter_pool *
3140 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3143 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3144 return (struct mlx5_flow_counter_pool *)cnt - 1;
3150 * Get a pool by devx counter ID.
3153 * Pointer to the counter container.
3155 * The counter devx ID.
3158 * The counter pool pointer if exists, NULL otherwise,
3160 static struct mlx5_flow_counter_pool *
3161 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3163 struct mlx5_flow_counter_pool *pool;
3165 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3166 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3167 MLX5_COUNTERS_PER_POOL;
3169 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3176 * Allocate a new memory for the counter values wrapped by all the needed
3180 * Pointer to the Ethernet device structure.
3182 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3185 * The new memory management pointer on success, otherwise NULL and rte_errno
3188 static struct mlx5_counter_stats_mem_mng *
3189 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3191 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3192 (dev->data->dev_private))->sh;
3193 struct mlx5_devx_mkey_attr mkey_attr;
3194 struct mlx5_counter_stats_mem_mng *mem_mng;
3195 volatile struct flow_counter_stats *raw_data;
3196 int size = (sizeof(struct flow_counter_stats) *
3197 MLX5_COUNTERS_PER_POOL +
3198 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3199 sizeof(struct mlx5_counter_stats_mem_mng);
3200 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3207 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3208 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3209 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3210 IBV_ACCESS_LOCAL_WRITE);
3211 if (!mem_mng->umem) {
3216 mkey_attr.addr = (uintptr_t)mem;
3217 mkey_attr.size = size;
3218 mkey_attr.umem_id = mem_mng->umem->umem_id;
3219 mkey_attr.pd = sh->pdn;
3220 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3222 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3227 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3228 raw_data = (volatile struct flow_counter_stats *)mem;
3229 for (i = 0; i < raws_n; ++i) {
3230 mem_mng->raws[i].mem_mng = mem_mng;
3231 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3233 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3238 * Resize a counter container.
3241 * Pointer to the Ethernet device structure.
3243 * Whether the pool is for counter that was allocated by batch command.
3246 * The new container pointer on success, otherwise NULL and rte_errno is set.
3248 static struct mlx5_pools_container *
3249 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3251 struct mlx5_priv *priv = dev->data->dev_private;
3252 struct mlx5_pools_container *cont =
3253 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3254 struct mlx5_pools_container *new_cont =
3255 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3256 struct mlx5_counter_stats_mem_mng *mem_mng;
3257 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3258 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3261 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3262 /* The last resize still hasn't detected by the host thread. */
3266 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3267 if (!new_cont->pools) {
3272 memcpy(new_cont->pools, cont->pools, cont->n *
3273 sizeof(struct mlx5_flow_counter_pool *));
3274 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3275 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3277 rte_free(new_cont->pools);
3280 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3281 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3282 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3284 new_cont->n = resize;
3285 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3286 TAILQ_INIT(&new_cont->pool_list);
3287 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3288 new_cont->init_mem_mng = mem_mng;
3290 /* Flip the master container. */
3291 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3296 * Query a devx flow counter.
3299 * Pointer to the Ethernet device structure.
3301 * Pointer to the flow counter.
3303 * The statistics value of packets.
3305 * The statistics value of bytes.
3308 * 0 on success, otherwise a negative errno value and rte_errno is set.
3311 _flow_dv_query_count(struct rte_eth_dev *dev,
3312 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3315 struct mlx5_priv *priv = dev->data->dev_private;
3316 struct mlx5_flow_counter_pool *pool =
3317 flow_dv_counter_pool_get(cnt);
3318 int offset = cnt - &pool->counters_raw[0];
3320 if (priv->counter_fallback)
3321 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3323 rte_spinlock_lock(&pool->sl);
3325 * The single counters allocation may allocate smaller ID than the
3326 * current allocated in parallel to the host reading.
3327 * In this case the new counter values must be reported as 0.
3329 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3333 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3334 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3336 rte_spinlock_unlock(&pool->sl);
3341 * Create and initialize a new counter pool.
3344 * Pointer to the Ethernet device structure.
3346 * The devX counter handle.
3348 * Whether the pool is for counter that was allocated by batch command.
3351 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3353 static struct mlx5_flow_counter_pool *
3354 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3357 struct mlx5_priv *priv = dev->data->dev_private;
3358 struct mlx5_flow_counter_pool *pool;
3359 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3361 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3364 if (cont->n == n_valid) {
3365 cont = flow_dv_container_resize(dev, batch);
3369 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3370 sizeof(struct mlx5_flow_counter);
3371 pool = rte_calloc(__func__, 1, size, 0);
3376 pool->min_dcs = dcs;
3377 pool->raw = cont->init_mem_mng->raws + n_valid %
3378 MLX5_CNT_CONTAINER_RESIZE;
3379 pool->raw_hw = NULL;
3380 rte_spinlock_init(&pool->sl);
3382 * The generation of the new allocated counters in this pool is 0, 2 in
3383 * the pool generation makes all the counters valid for allocation.
3385 rte_atomic64_set(&pool->query_gen, 0x2);
3386 TAILQ_INIT(&pool->counters);
3387 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3388 cont->pools[n_valid] = pool;
3389 /* Pool initialization must be updated before host thread access. */
3391 rte_atomic16_add(&cont->n_valid, 1);
3396 * Prepare a new counter and/or a new counter pool.
3399 * Pointer to the Ethernet device structure.
3400 * @param[out] cnt_free
3401 * Where to put the pointer of a new counter.
3403 * Whether the pool is for counter that was allocated by batch command.
3406 * The free counter pool pointer and @p cnt_free is set on success,
3407 * NULL otherwise and rte_errno is set.
3409 static struct mlx5_flow_counter_pool *
3410 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3411 struct mlx5_flow_counter **cnt_free,
3414 struct mlx5_priv *priv = dev->data->dev_private;
3415 struct mlx5_flow_counter_pool *pool;
3416 struct mlx5_devx_obj *dcs = NULL;
3417 struct mlx5_flow_counter *cnt;
3421 /* bulk_bitmap must be 0 for single counter allocation. */
3422 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3425 pool = flow_dv_find_pool_by_id
3426 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3428 pool = flow_dv_pool_create(dev, dcs, batch);
3430 mlx5_devx_cmd_destroy(dcs);
3433 } else if (dcs->id < pool->min_dcs->id) {
3434 rte_atomic64_set(&pool->a64_dcs,
3435 (int64_t)(uintptr_t)dcs);
3437 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3438 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3443 /* bulk_bitmap is in 128 counters units. */
3444 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3445 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3447 rte_errno = ENODATA;
3450 pool = flow_dv_pool_create(dev, dcs, batch);
3452 mlx5_devx_cmd_destroy(dcs);
3455 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3456 cnt = &pool->counters_raw[i];
3458 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3460 *cnt_free = &pool->counters_raw[0];
3465 * Search for existed shared counter.
3468 * Pointer to the relevant counter pool container.
3470 * The shared counter ID to search.
3473 * NULL if not existed, otherwise pointer to the shared counter.
3475 static struct mlx5_flow_counter *
3476 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3479 static struct mlx5_flow_counter *cnt;
3480 struct mlx5_flow_counter_pool *pool;
3483 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3484 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3485 cnt = &pool->counters_raw[i];
3486 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3494 * Allocate a flow counter.
3497 * Pointer to the Ethernet device structure.
3499 * Indicate if this counter is shared with other flows.
3501 * Counter identifier.
3503 * Counter flow group.
3506 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3508 static struct mlx5_flow_counter *
3509 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3512 struct mlx5_priv *priv = dev->data->dev_private;
3513 struct mlx5_flow_counter_pool *pool = NULL;
3514 struct mlx5_flow_counter *cnt_free = NULL;
3516 * Currently group 0 flow counter cannot be assigned to a flow if it is
3517 * not the first one in the batch counter allocation, so it is better
3518 * to allocate counters one by one for these flows in a separate
3520 * A counter can be shared between different groups so need to take
3521 * shared counters from the single container.
3523 uint32_t batch = (group && !shared) ? 1 : 0;
3524 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3527 if (priv->counter_fallback)
3528 return flow_dv_counter_alloc_fallback(dev, shared, id);
3529 if (!priv->config.devx) {
3530 rte_errno = ENOTSUP;
3534 cnt_free = flow_dv_counter_shared_search(cont, id);
3536 if (cnt_free->ref_cnt + 1 == 0) {
3540 cnt_free->ref_cnt++;
3544 /* Pools which has a free counters are in the start. */
3545 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3547 * The free counter reset values must be updated between the
3548 * counter release to the counter allocation, so, at least one
3549 * query must be done in this time. ensure it by saving the
3550 * query generation in the release time.
3551 * The free list is sorted according to the generation - so if
3552 * the first one is not updated, all the others are not
3555 cnt_free = TAILQ_FIRST(&pool->counters);
3556 if (cnt_free && cnt_free->query_gen + 1 <
3557 rte_atomic64_read(&pool->query_gen))
3562 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3566 cnt_free->batch = batch;
3567 /* Create a DV counter action only in the first time usage. */
3568 if (!cnt_free->action) {
3570 struct mlx5_devx_obj *dcs;
3573 offset = cnt_free - &pool->counters_raw[0];
3574 dcs = pool->min_dcs;
3577 dcs = cnt_free->dcs;
3579 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3581 if (!cnt_free->action) {
3586 /* Update the counter reset values. */
3587 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3590 cnt_free->shared = shared;
3591 cnt_free->ref_cnt = 1;
3593 if (!priv->sh->cmng.query_thread_on)
3594 /* Start the asynchronous batch query by the host thread. */
3595 mlx5_set_query_alarm(priv->sh);
3596 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3597 if (TAILQ_EMPTY(&pool->counters)) {
3598 /* Move the pool to the end of the container pool list. */
3599 TAILQ_REMOVE(&cont->pool_list, pool, next);
3600 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3606 * Release a flow counter.
3609 * Pointer to the Ethernet device structure.
3610 * @param[in] counter
3611 * Pointer to the counter handler.
3614 flow_dv_counter_release(struct rte_eth_dev *dev,
3615 struct mlx5_flow_counter *counter)
3617 struct mlx5_priv *priv = dev->data->dev_private;
3621 if (priv->counter_fallback) {
3622 flow_dv_counter_release_fallback(dev, counter);
3625 if (--counter->ref_cnt == 0) {
3626 struct mlx5_flow_counter_pool *pool =
3627 flow_dv_counter_pool_get(counter);
3629 /* Put the counter in the end - the last updated one. */
3630 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3631 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3636 * Verify the @p attributes will be correctly understood by the NIC and store
3637 * them in the @p flow if everything is correct.
3640 * Pointer to dev struct.
3641 * @param[in] attributes
3642 * Pointer to flow attributes
3643 * @param[in] external
3644 * This flow rule is created by request external to PMD.
3646 * Pointer to error structure.
3649 * 0 on success, a negative errno value otherwise and rte_errno is set.
3652 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3653 const struct rte_flow_attr *attributes,
3654 bool external __rte_unused,
3655 struct rte_flow_error *error)
3657 struct mlx5_priv *priv = dev->data->dev_private;
3658 uint32_t priority_max = priv->config.flow_prio - 1;
3660 #ifndef HAVE_MLX5DV_DR
3661 if (attributes->group)
3662 return rte_flow_error_set(error, ENOTSUP,
3663 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3665 "groups are not supported");
3667 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3672 ret = mlx5_flow_group_to_table(attributes, external,
3677 if (table >= max_group)
3678 return rte_flow_error_set(error, EINVAL,
3679 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3680 "group index out of range");
3682 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3683 attributes->priority >= priority_max)
3684 return rte_flow_error_set(error, ENOTSUP,
3685 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3687 "priority out of range");
3688 if (attributes->transfer) {
3689 if (!priv->config.dv_esw_en)
3690 return rte_flow_error_set
3692 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3693 "E-Switch dr is not supported");
3694 if (!(priv->representor || priv->master))
3695 return rte_flow_error_set
3696 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3697 NULL, "E-Switch configuration can only be"
3698 " done by a master or a representor device");
3699 if (attributes->egress)
3700 return rte_flow_error_set
3702 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3703 "egress is not supported");
3705 if (!(attributes->egress ^ attributes->ingress))
3706 return rte_flow_error_set(error, ENOTSUP,
3707 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3708 "must specify exactly one of "
3709 "ingress or egress");
3714 * Internal validation function. For validating both actions and items.
3717 * Pointer to the rte_eth_dev structure.
3719 * Pointer to the flow attributes.
3721 * Pointer to the list of items.
3722 * @param[in] actions
3723 * Pointer to the list of actions.
3724 * @param[in] external
3725 * This flow rule is created by request external to PMD.
3727 * Pointer to the error structure.
3730 * 0 on success, a negative errno value otherwise and rte_errno is set.
3733 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3734 const struct rte_flow_item items[],
3735 const struct rte_flow_action actions[],
3736 bool external, struct rte_flow_error *error)
3739 uint64_t action_flags = 0;
3740 uint64_t item_flags = 0;
3741 uint64_t last_item = 0;
3742 uint8_t next_protocol = 0xff;
3743 uint16_t ether_type = 0;
3745 const struct rte_flow_item *gre_item = NULL;
3746 struct rte_flow_item_tcp nic_tcp_mask = {
3749 .src_port = RTE_BE16(UINT16_MAX),
3750 .dst_port = RTE_BE16(UINT16_MAX),
3756 ret = flow_dv_validate_attributes(dev, attr, external, error);
3759 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3760 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3761 int type = items->type;
3764 case RTE_FLOW_ITEM_TYPE_VOID:
3766 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3767 ret = flow_dv_validate_item_port_id
3768 (dev, items, attr, item_flags, error);
3771 last_item = MLX5_FLOW_ITEM_PORT_ID;
3773 case RTE_FLOW_ITEM_TYPE_ETH:
3774 ret = mlx5_flow_validate_item_eth(items, item_flags,
3778 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3779 MLX5_FLOW_LAYER_OUTER_L2;
3780 if (items->mask != NULL && items->spec != NULL) {
3782 ((const struct rte_flow_item_eth *)
3785 ((const struct rte_flow_item_eth *)
3787 ether_type = rte_be_to_cpu_16(ether_type);
3792 case RTE_FLOW_ITEM_TYPE_VLAN:
3793 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3797 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3798 MLX5_FLOW_LAYER_OUTER_VLAN;
3799 if (items->mask != NULL && items->spec != NULL) {
3801 ((const struct rte_flow_item_vlan *)
3802 items->spec)->inner_type;
3804 ((const struct rte_flow_item_vlan *)
3805 items->mask)->inner_type;
3806 ether_type = rte_be_to_cpu_16(ether_type);
3811 case RTE_FLOW_ITEM_TYPE_IPV4:
3812 mlx5_flow_tunnel_ip_check(items, next_protocol,
3813 &item_flags, &tunnel);
3814 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3820 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3821 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3822 if (items->mask != NULL &&
3823 ((const struct rte_flow_item_ipv4 *)
3824 items->mask)->hdr.next_proto_id) {
3826 ((const struct rte_flow_item_ipv4 *)
3827 (items->spec))->hdr.next_proto_id;
3829 ((const struct rte_flow_item_ipv4 *)
3830 (items->mask))->hdr.next_proto_id;
3832 /* Reset for inner layer. */
3833 next_protocol = 0xff;
3836 case RTE_FLOW_ITEM_TYPE_IPV6:
3837 mlx5_flow_tunnel_ip_check(items, next_protocol,
3838 &item_flags, &tunnel);
3839 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3845 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3846 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3847 if (items->mask != NULL &&
3848 ((const struct rte_flow_item_ipv6 *)
3849 items->mask)->hdr.proto) {
3851 ((const struct rte_flow_item_ipv6 *)
3852 items->spec)->hdr.proto;
3854 ((const struct rte_flow_item_ipv6 *)
3855 items->mask)->hdr.proto;
3857 /* Reset for inner layer. */
3858 next_protocol = 0xff;
3861 case RTE_FLOW_ITEM_TYPE_TCP:
3862 ret = mlx5_flow_validate_item_tcp
3869 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3870 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3872 case RTE_FLOW_ITEM_TYPE_UDP:
3873 ret = mlx5_flow_validate_item_udp(items, item_flags,
3878 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3879 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3881 case RTE_FLOW_ITEM_TYPE_GRE:
3882 ret = mlx5_flow_validate_item_gre(items, item_flags,
3883 next_protocol, error);
3887 last_item = MLX5_FLOW_LAYER_GRE;
3889 case RTE_FLOW_ITEM_TYPE_NVGRE:
3890 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3895 last_item = MLX5_FLOW_LAYER_NVGRE;
3897 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3898 ret = mlx5_flow_validate_item_gre_key
3899 (items, item_flags, gre_item, error);
3902 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3904 case RTE_FLOW_ITEM_TYPE_VXLAN:
3905 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3909 last_item = MLX5_FLOW_LAYER_VXLAN;
3911 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3912 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3917 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3919 case RTE_FLOW_ITEM_TYPE_GENEVE:
3920 ret = mlx5_flow_validate_item_geneve(items,
3925 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3927 case RTE_FLOW_ITEM_TYPE_MPLS:
3928 ret = mlx5_flow_validate_item_mpls(dev, items,
3933 last_item = MLX5_FLOW_LAYER_MPLS;
3935 case RTE_FLOW_ITEM_TYPE_META:
3936 ret = flow_dv_validate_item_meta(dev, items, attr,
3940 last_item = MLX5_FLOW_ITEM_METADATA;
3942 case RTE_FLOW_ITEM_TYPE_ICMP:
3943 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3948 last_item = MLX5_FLOW_LAYER_ICMP;
3950 case RTE_FLOW_ITEM_TYPE_ICMP6:
3951 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3956 last_item = MLX5_FLOW_LAYER_ICMP6;
3958 case RTE_FLOW_ITEM_TYPE_TAG:
3959 ret = flow_dv_validate_item_tag(dev, items,
3963 last_item = MLX5_FLOW_ITEM_TAG;
3965 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3966 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3969 return rte_flow_error_set(error, ENOTSUP,
3970 RTE_FLOW_ERROR_TYPE_ITEM,
3971 NULL, "item not supported");
3973 item_flags |= last_item;
3975 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3976 int type = actions->type;
3977 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3978 return rte_flow_error_set(error, ENOTSUP,
3979 RTE_FLOW_ERROR_TYPE_ACTION,
3980 actions, "too many actions");
3982 case RTE_FLOW_ACTION_TYPE_VOID:
3984 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3985 ret = flow_dv_validate_action_port_id(dev,
3992 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3995 case RTE_FLOW_ACTION_TYPE_FLAG:
3996 ret = mlx5_flow_validate_action_flag(action_flags,
4000 action_flags |= MLX5_FLOW_ACTION_FLAG;
4003 case RTE_FLOW_ACTION_TYPE_MARK:
4004 ret = mlx5_flow_validate_action_mark(actions,
4009 action_flags |= MLX5_FLOW_ACTION_MARK;
4012 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4013 ret = flow_dv_validate_action_set_tag(dev, actions,
4018 /* Count all modify-header actions as one action. */
4019 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4021 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4023 case RTE_FLOW_ACTION_TYPE_DROP:
4024 ret = mlx5_flow_validate_action_drop(action_flags,
4028 action_flags |= MLX5_FLOW_ACTION_DROP;
4031 case RTE_FLOW_ACTION_TYPE_QUEUE:
4032 ret = mlx5_flow_validate_action_queue(actions,
4037 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4040 case RTE_FLOW_ACTION_TYPE_RSS:
4041 ret = mlx5_flow_validate_action_rss(actions,
4047 action_flags |= MLX5_FLOW_ACTION_RSS;
4050 case RTE_FLOW_ACTION_TYPE_COUNT:
4051 ret = flow_dv_validate_action_count(dev, error);
4054 action_flags |= MLX5_FLOW_ACTION_COUNT;
4057 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4058 if (flow_dv_validate_action_pop_vlan(dev,
4064 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4067 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4068 ret = flow_dv_validate_action_push_vlan(action_flags,
4074 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4077 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4078 ret = flow_dv_validate_action_set_vlan_pcp
4079 (action_flags, actions, error);
4082 /* Count PCP with push_vlan command. */
4083 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4085 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4086 ret = flow_dv_validate_action_set_vlan_vid
4087 (item_flags, action_flags,
4091 /* Count VID with push_vlan command. */
4092 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4094 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4095 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4096 ret = flow_dv_validate_action_l2_encap(action_flags,
4101 action_flags |= actions->type ==
4102 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4103 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4104 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4107 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4108 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4109 ret = flow_dv_validate_action_l2_decap(action_flags,
4113 action_flags |= actions->type ==
4114 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4115 MLX5_FLOW_ACTION_VXLAN_DECAP :
4116 MLX5_FLOW_ACTION_NVGRE_DECAP;
4119 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4120 ret = flow_dv_validate_action_raw_encap(action_flags,
4125 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4128 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4129 ret = flow_dv_validate_action_raw_decap(action_flags,
4134 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4137 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4138 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4139 ret = flow_dv_validate_action_modify_mac(action_flags,
4145 /* Count all modify-header actions as one action. */
4146 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4148 action_flags |= actions->type ==
4149 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4150 MLX5_FLOW_ACTION_SET_MAC_SRC :
4151 MLX5_FLOW_ACTION_SET_MAC_DST;
4154 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4155 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4156 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4162 /* Count all modify-header actions as one action. */
4163 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4165 action_flags |= actions->type ==
4166 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4167 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4168 MLX5_FLOW_ACTION_SET_IPV4_DST;
4170 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4171 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4172 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4178 /* Count all modify-header actions as one action. */
4179 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4181 action_flags |= actions->type ==
4182 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4183 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4184 MLX5_FLOW_ACTION_SET_IPV6_DST;
4186 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4187 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4188 ret = flow_dv_validate_action_modify_tp(action_flags,
4194 /* Count all modify-header actions as one action. */
4195 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4197 action_flags |= actions->type ==
4198 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4199 MLX5_FLOW_ACTION_SET_TP_SRC :
4200 MLX5_FLOW_ACTION_SET_TP_DST;
4202 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4203 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4204 ret = flow_dv_validate_action_modify_ttl(action_flags,
4210 /* Count all modify-header actions as one action. */
4211 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4213 action_flags |= actions->type ==
4214 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4215 MLX5_FLOW_ACTION_SET_TTL :
4216 MLX5_FLOW_ACTION_DEC_TTL;
4218 case RTE_FLOW_ACTION_TYPE_JUMP:
4219 ret = flow_dv_validate_action_jump(actions,
4226 action_flags |= MLX5_FLOW_ACTION_JUMP;
4228 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4229 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4230 ret = flow_dv_validate_action_modify_tcp_seq
4237 /* Count all modify-header actions as one action. */
4238 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4240 action_flags |= actions->type ==
4241 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4242 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4243 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4245 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4246 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4247 ret = flow_dv_validate_action_modify_tcp_ack
4254 /* Count all modify-header actions as one action. */
4255 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4257 action_flags |= actions->type ==
4258 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4259 MLX5_FLOW_ACTION_INC_TCP_ACK :
4260 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4262 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4263 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4266 return rte_flow_error_set(error, ENOTSUP,
4267 RTE_FLOW_ERROR_TYPE_ACTION,
4269 "action not supported");
4272 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4273 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4274 return rte_flow_error_set(error, ENOTSUP,
4275 RTE_FLOW_ERROR_TYPE_ACTION,
4277 "can't have vxlan and vlan"
4278 " actions in the same rule");
4279 /* Eswitch has few restrictions on using items and actions */
4280 if (attr->transfer) {
4281 if (action_flags & MLX5_FLOW_ACTION_FLAG)
4282 return rte_flow_error_set(error, ENOTSUP,
4283 RTE_FLOW_ERROR_TYPE_ACTION,
4285 "unsupported action FLAG");
4286 if (action_flags & MLX5_FLOW_ACTION_MARK)
4287 return rte_flow_error_set(error, ENOTSUP,
4288 RTE_FLOW_ERROR_TYPE_ACTION,
4290 "unsupported action MARK");
4291 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4292 return rte_flow_error_set(error, ENOTSUP,
4293 RTE_FLOW_ERROR_TYPE_ACTION,
4295 "unsupported action QUEUE");
4296 if (action_flags & MLX5_FLOW_ACTION_RSS)
4297 return rte_flow_error_set(error, ENOTSUP,
4298 RTE_FLOW_ERROR_TYPE_ACTION,
4300 "unsupported action RSS");
4301 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4302 return rte_flow_error_set(error, EINVAL,
4303 RTE_FLOW_ERROR_TYPE_ACTION,
4305 "no fate action is found");
4307 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4308 return rte_flow_error_set(error, EINVAL,
4309 RTE_FLOW_ERROR_TYPE_ACTION,
4311 "no fate action is found");
4317 * Internal preparation function. Allocates the DV flow size,
4318 * this size is constant.
4321 * Pointer to the flow attributes.
4323 * Pointer to the list of items.
4324 * @param[in] actions
4325 * Pointer to the list of actions.
4327 * Pointer to the error structure.
4330 * Pointer to mlx5_flow object on success,
4331 * otherwise NULL and rte_errno is set.
4333 static struct mlx5_flow *
4334 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4335 const struct rte_flow_item items[] __rte_unused,
4336 const struct rte_flow_action actions[] __rte_unused,
4337 struct rte_flow_error *error)
4339 size_t size = sizeof(struct mlx5_flow);
4340 struct mlx5_flow *dev_flow;
4342 dev_flow = rte_calloc(__func__, 1, size, 0);
4344 rte_flow_error_set(error, ENOMEM,
4345 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4346 "not enough memory to create flow");
4349 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4350 dev_flow->ingress = attr->ingress;
4351 dev_flow->transfer = attr->transfer;
4357 * Sanity check for match mask and value. Similar to check_valid_spec() in
4358 * kernel driver. If unmasked bit is present in value, it returns failure.
4361 * pointer to match mask buffer.
4362 * @param match_value
4363 * pointer to match value buffer.
4366 * 0 if valid, -EINVAL otherwise.
4369 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4371 uint8_t *m = match_mask;
4372 uint8_t *v = match_value;
4375 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4378 "match_value differs from match_criteria"
4379 " %p[%u] != %p[%u]",
4380 match_value, i, match_mask, i);
4389 * Add Ethernet item to matcher and to the value.
4391 * @param[in, out] matcher
4393 * @param[in, out] key
4394 * Flow matcher value.
4396 * Flow pattern to translate.
4398 * Item is inner pattern.
4401 flow_dv_translate_item_eth(void *matcher, void *key,
4402 const struct rte_flow_item *item, int inner)
4404 const struct rte_flow_item_eth *eth_m = item->mask;
4405 const struct rte_flow_item_eth *eth_v = item->spec;
4406 const struct rte_flow_item_eth nic_mask = {
4407 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4408 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4409 .type = RTE_BE16(0xffff),
4421 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4423 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4425 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4427 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4429 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4430 ð_m->dst, sizeof(eth_m->dst));
4431 /* The value must be in the range of the mask. */
4432 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4433 for (i = 0; i < sizeof(eth_m->dst); ++i)
4434 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4435 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4436 ð_m->src, sizeof(eth_m->src));
4437 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4438 /* The value must be in the range of the mask. */
4439 for (i = 0; i < sizeof(eth_m->dst); ++i)
4440 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4441 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4442 rte_be_to_cpu_16(eth_m->type));
4443 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4444 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4448 * Add VLAN item to matcher and to the value.
4450 * @param[in, out] dev_flow
4452 * @param[in, out] matcher
4454 * @param[in, out] key
4455 * Flow matcher value.
4457 * Flow pattern to translate.
4459 * Item is inner pattern.
4462 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4463 void *matcher, void *key,
4464 const struct rte_flow_item *item,
4467 const struct rte_flow_item_vlan *vlan_m = item->mask;
4468 const struct rte_flow_item_vlan *vlan_v = item->spec;
4477 vlan_m = &rte_flow_item_vlan_mask;
4479 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4481 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4483 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4485 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4487 * This is workaround, masks are not supported,
4488 * and pre-validated.
4490 dev_flow->dv.vf_vlan.tag =
4491 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4493 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4494 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4495 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4497 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4498 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4499 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4501 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4502 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4503 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4504 rte_be_to_cpu_16(vlan_m->inner_type));
4505 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4506 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4510 * Add IPV4 item to matcher and to the value.
4512 * @param[in, out] matcher
4514 * @param[in, out] key
4515 * Flow matcher value.
4517 * Flow pattern to translate.
4519 * Item is inner pattern.
4521 * The group to insert the rule.
4524 flow_dv_translate_item_ipv4(void *matcher, void *key,
4525 const struct rte_flow_item *item,
4526 int inner, uint32_t group)
4528 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4529 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4530 const struct rte_flow_item_ipv4 nic_mask = {
4532 .src_addr = RTE_BE32(0xffffffff),
4533 .dst_addr = RTE_BE32(0xffffffff),
4534 .type_of_service = 0xff,
4535 .next_proto_id = 0xff,
4545 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4547 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4549 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4551 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4554 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4556 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4557 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4562 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4563 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4564 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4565 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4566 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4567 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4568 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4569 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4570 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4571 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4572 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4573 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4574 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4575 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4576 ipv4_m->hdr.type_of_service);
4577 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4578 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4579 ipv4_m->hdr.type_of_service >> 2);
4580 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4581 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4582 ipv4_m->hdr.next_proto_id);
4583 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4584 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4588 * Add IPV6 item to matcher and to the value.
4590 * @param[in, out] matcher
4592 * @param[in, out] key
4593 * Flow matcher value.
4595 * Flow pattern to translate.
4597 * Item is inner pattern.
4599 * The group to insert the rule.
4602 flow_dv_translate_item_ipv6(void *matcher, void *key,
4603 const struct rte_flow_item *item,
4604 int inner, uint32_t group)
4606 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4607 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4608 const struct rte_flow_item_ipv6 nic_mask = {
4611 "\xff\xff\xff\xff\xff\xff\xff\xff"
4612 "\xff\xff\xff\xff\xff\xff\xff\xff",
4614 "\xff\xff\xff\xff\xff\xff\xff\xff"
4615 "\xff\xff\xff\xff\xff\xff\xff\xff",
4616 .vtc_flow = RTE_BE32(0xffffffff),
4623 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4624 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4633 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4635 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4637 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4639 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4642 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4644 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4645 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4650 size = sizeof(ipv6_m->hdr.dst_addr);
4651 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4652 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4653 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4654 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4655 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4656 for (i = 0; i < size; ++i)
4657 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4658 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4659 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4660 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4661 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4662 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4663 for (i = 0; i < size; ++i)
4664 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4666 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4667 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4668 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4670 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4674 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4676 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4679 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4681 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4685 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4687 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4688 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4692 * Add TCP item to matcher and to the value.
4694 * @param[in, out] matcher
4696 * @param[in, out] key
4697 * Flow matcher value.
4699 * Flow pattern to translate.
4701 * Item is inner pattern.
4704 flow_dv_translate_item_tcp(void *matcher, void *key,
4705 const struct rte_flow_item *item,
4708 const struct rte_flow_item_tcp *tcp_m = item->mask;
4709 const struct rte_flow_item_tcp *tcp_v = item->spec;
4714 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4716 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4718 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4720 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4722 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4723 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4727 tcp_m = &rte_flow_item_tcp_mask;
4728 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4729 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4730 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4731 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4732 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4733 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4734 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4735 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4736 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4737 tcp_m->hdr.tcp_flags);
4738 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4739 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4743 * Add UDP item to matcher and to the value.
4745 * @param[in, out] matcher
4747 * @param[in, out] key
4748 * Flow matcher value.
4750 * Flow pattern to translate.
4752 * Item is inner pattern.
4755 flow_dv_translate_item_udp(void *matcher, void *key,
4756 const struct rte_flow_item *item,
4759 const struct rte_flow_item_udp *udp_m = item->mask;
4760 const struct rte_flow_item_udp *udp_v = item->spec;
4765 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4767 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4769 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4771 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4773 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4774 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4778 udp_m = &rte_flow_item_udp_mask;
4779 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4780 rte_be_to_cpu_16(udp_m->hdr.src_port));
4781 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4782 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4783 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4784 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4785 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4786 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4790 * Add GRE optional Key item to matcher and to the value.
4792 * @param[in, out] matcher
4794 * @param[in, out] key
4795 * Flow matcher value.
4797 * Flow pattern to translate.
4799 * Item is inner pattern.
4802 flow_dv_translate_item_gre_key(void *matcher, void *key,
4803 const struct rte_flow_item *item)
4805 const rte_be32_t *key_m = item->mask;
4806 const rte_be32_t *key_v = item->spec;
4807 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4808 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4809 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4814 key_m = &gre_key_default_mask;
4815 /* GRE K bit must be on and should already be validated */
4816 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4817 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4818 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4819 rte_be_to_cpu_32(*key_m) >> 8);
4820 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4821 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4822 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4823 rte_be_to_cpu_32(*key_m) & 0xFF);
4824 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4825 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4829 * Add GRE item to matcher and to the value.
4831 * @param[in, out] matcher
4833 * @param[in, out] key
4834 * Flow matcher value.
4836 * Flow pattern to translate.
4838 * Item is inner pattern.
4841 flow_dv_translate_item_gre(void *matcher, void *key,
4842 const struct rte_flow_item *item,
4845 const struct rte_flow_item_gre *gre_m = item->mask;
4846 const struct rte_flow_item_gre *gre_v = item->spec;
4849 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4850 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4857 uint16_t s_present:1;
4858 uint16_t k_present:1;
4859 uint16_t rsvd_bit1:1;
4860 uint16_t c_present:1;
4864 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4867 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4869 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4871 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4873 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4875 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4876 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4880 gre_m = &rte_flow_item_gre_mask;
4881 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4882 rte_be_to_cpu_16(gre_m->protocol));
4883 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4884 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4885 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4886 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4887 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4888 gre_crks_rsvd0_ver_m.c_present);
4889 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4890 gre_crks_rsvd0_ver_v.c_present &
4891 gre_crks_rsvd0_ver_m.c_present);
4892 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4893 gre_crks_rsvd0_ver_m.k_present);
4894 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4895 gre_crks_rsvd0_ver_v.k_present &
4896 gre_crks_rsvd0_ver_m.k_present);
4897 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4898 gre_crks_rsvd0_ver_m.s_present);
4899 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4900 gre_crks_rsvd0_ver_v.s_present &
4901 gre_crks_rsvd0_ver_m.s_present);
4905 * Add NVGRE item to matcher and to the value.
4907 * @param[in, out] matcher
4909 * @param[in, out] key
4910 * Flow matcher value.
4912 * Flow pattern to translate.
4914 * Item is inner pattern.
4917 flow_dv_translate_item_nvgre(void *matcher, void *key,
4918 const struct rte_flow_item *item,
4921 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4922 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4923 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4924 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4925 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4926 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4932 /* For NVGRE, GRE header fields must be set with defined values. */
4933 const struct rte_flow_item_gre gre_spec = {
4934 .c_rsvd0_ver = RTE_BE16(0x2000),
4935 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4937 const struct rte_flow_item_gre gre_mask = {
4938 .c_rsvd0_ver = RTE_BE16(0xB000),
4939 .protocol = RTE_BE16(UINT16_MAX),
4941 const struct rte_flow_item gre_item = {
4946 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4950 nvgre_m = &rte_flow_item_nvgre_mask;
4951 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4952 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4953 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4954 memcpy(gre_key_m, tni_flow_id_m, size);
4955 for (i = 0; i < size; ++i)
4956 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4960 * Add VXLAN item to matcher and to the value.
4962 * @param[in, out] matcher
4964 * @param[in, out] key
4965 * Flow matcher value.
4967 * Flow pattern to translate.
4969 * Item is inner pattern.
4972 flow_dv_translate_item_vxlan(void *matcher, void *key,
4973 const struct rte_flow_item *item,
4976 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4977 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4980 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4981 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4989 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4991 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4993 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4995 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4997 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4998 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4999 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5000 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5001 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5006 vxlan_m = &rte_flow_item_vxlan_mask;
5007 size = sizeof(vxlan_m->vni);
5008 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5009 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5010 memcpy(vni_m, vxlan_m->vni, size);
5011 for (i = 0; i < size; ++i)
5012 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5016 * Add Geneve item to matcher and to the value.
5018 * @param[in, out] matcher
5020 * @param[in, out] key
5021 * Flow matcher value.
5023 * Flow pattern to translate.
5025 * Item is inner pattern.
5029 flow_dv_translate_item_geneve(void *matcher, void *key,
5030 const struct rte_flow_item *item, int inner)
5032 const struct rte_flow_item_geneve *geneve_m = item->mask;
5033 const struct rte_flow_item_geneve *geneve_v = item->spec;
5036 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5037 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5046 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5048 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5050 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5052 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5054 dport = MLX5_UDP_PORT_GENEVE;
5055 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5056 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5057 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5062 geneve_m = &rte_flow_item_geneve_mask;
5063 size = sizeof(geneve_m->vni);
5064 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5065 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5066 memcpy(vni_m, geneve_m->vni, size);
5067 for (i = 0; i < size; ++i)
5068 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5069 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5070 rte_be_to_cpu_16(geneve_m->protocol));
5071 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5072 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5073 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5074 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5075 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5076 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5077 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5078 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5079 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5080 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5081 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5082 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5083 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5087 * Add MPLS item to matcher and to the value.
5089 * @param[in, out] matcher
5091 * @param[in, out] key
5092 * Flow matcher value.
5094 * Flow pattern to translate.
5095 * @param[in] prev_layer
5096 * The protocol layer indicated in previous item.
5098 * Item is inner pattern.
5101 flow_dv_translate_item_mpls(void *matcher, void *key,
5102 const struct rte_flow_item *item,
5103 uint64_t prev_layer,
5106 const uint32_t *in_mpls_m = item->mask;
5107 const uint32_t *in_mpls_v = item->spec;
5108 uint32_t *out_mpls_m = 0;
5109 uint32_t *out_mpls_v = 0;
5110 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5111 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5112 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5114 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5115 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5116 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5118 switch (prev_layer) {
5119 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5120 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5121 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5122 MLX5_UDP_PORT_MPLS);
5124 case MLX5_FLOW_LAYER_GRE:
5125 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5126 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5127 RTE_ETHER_TYPE_MPLS);
5130 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5131 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5138 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5139 switch (prev_layer) {
5140 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5142 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5143 outer_first_mpls_over_udp);
5145 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5146 outer_first_mpls_over_udp);
5148 case MLX5_FLOW_LAYER_GRE:
5150 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5151 outer_first_mpls_over_gre);
5153 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5154 outer_first_mpls_over_gre);
5157 /* Inner MPLS not over GRE is not supported. */
5160 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5164 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5170 if (out_mpls_m && out_mpls_v) {
5171 *out_mpls_m = *in_mpls_m;
5172 *out_mpls_v = *in_mpls_v & *in_mpls_m;
5177 * Add metadata register item to matcher
5179 * @param[in, out] matcher
5181 * @param[in, out] key
5182 * Flow matcher value.
5183 * @param[in] reg_type
5184 * Type of device metadata register
5191 flow_dv_match_meta_reg(void *matcher, void *key,
5192 enum modify_reg reg_type,
5193 uint32_t data, uint32_t mask)
5196 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5198 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5203 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5204 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5207 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5208 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5211 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
5212 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
5215 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5216 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5219 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5220 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5223 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5224 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5227 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5228 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
5231 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
5232 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
5235 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
5236 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
5239 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
5240 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5249 * Add META item to matcher
5251 * @param[in, out] matcher
5253 * @param[in, out] key
5254 * Flow matcher value.
5256 * Flow pattern to translate.
5258 * Item is inner pattern.
5261 flow_dv_translate_item_meta(void *matcher, void *key,
5262 const struct rte_flow_item *item)
5264 const struct rte_flow_item_meta *meta_m;
5265 const struct rte_flow_item_meta *meta_v;
5267 meta_m = (const void *)item->mask;
5269 meta_m = &rte_flow_item_meta_mask;
5270 meta_v = (const void *)item->spec;
5272 flow_dv_match_meta_reg(matcher, key, REG_A,
5273 rte_cpu_to_be_32(meta_v->data),
5274 rte_cpu_to_be_32(meta_m->data));
5278 * Add vport metadata Reg C0 item to matcher
5280 * @param[in, out] matcher
5282 * @param[in, out] key
5283 * Flow matcher value.
5285 * Flow pattern to translate.
5288 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5289 uint32_t value, uint32_t mask)
5291 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5295 * Add tag item to matcher
5297 * @param[in, out] matcher
5299 * @param[in, out] key
5300 * Flow matcher value.
5302 * Flow pattern to translate.
5305 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5306 const struct rte_flow_item *item)
5308 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5309 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5312 flow_dv_match_meta_reg(matcher, key, tag_v->id, tag_v->data,
5313 tag_m ? tag_m->data : UINT32_MAX);
5317 * Add TAG item to matcher
5320 * The devich to configure through.
5321 * @param[in, out] matcher
5323 * @param[in, out] key
5324 * Flow matcher value.
5326 * Flow pattern to translate.
5329 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
5330 void *matcher, void *key,
5331 const struct rte_flow_item *item)
5333 const struct rte_flow_item_tag *tag_v = item->spec;
5334 const struct rte_flow_item_tag *tag_m = item->mask;
5335 enum modify_reg reg;
5338 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
5339 /* Get the metadata register index for the tag. */
5340 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
5342 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5346 * Add source vport match to the specified matcher.
5348 * @param[in, out] matcher
5350 * @param[in, out] key
5351 * Flow matcher value.
5353 * Source vport value to match
5358 flow_dv_translate_item_source_vport(void *matcher, void *key,
5359 int16_t port, uint16_t mask)
5361 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5362 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5364 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5365 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5369 * Translate port-id item to eswitch match on port-id.
5372 * The devich to configure through.
5373 * @param[in, out] matcher
5375 * @param[in, out] key
5376 * Flow matcher value.
5378 * Flow pattern to translate.
5381 * 0 on success, a negative errno value otherwise.
5384 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5385 void *key, const struct rte_flow_item *item)
5387 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5388 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5389 struct mlx5_priv *priv;
5392 mask = pid_m ? pid_m->id : 0xffff;
5393 id = pid_v ? pid_v->id : dev->data->port_id;
5394 priv = mlx5_port_to_eswitch_info(id, item == NULL);
5397 /* Translate to vport field or to metadata, depending on mode. */
5398 if (priv->vport_meta_mask)
5399 flow_dv_translate_item_meta_vport(matcher, key,
5400 priv->vport_meta_tag,
5401 priv->vport_meta_mask);
5403 flow_dv_translate_item_source_vport(matcher, key,
5404 priv->vport_id, mask);
5409 * Add ICMP6 item to matcher and to the value.
5411 * @param[in, out] matcher
5413 * @param[in, out] key
5414 * Flow matcher value.
5416 * Flow pattern to translate.
5418 * Item is inner pattern.
5421 flow_dv_translate_item_icmp6(void *matcher, void *key,
5422 const struct rte_flow_item *item,
5425 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5426 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5429 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5431 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5433 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5435 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5437 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5439 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5441 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5442 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5446 icmp6_m = &rte_flow_item_icmp6_mask;
5447 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5448 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5449 icmp6_v->type & icmp6_m->type);
5450 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5451 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5452 icmp6_v->code & icmp6_m->code);
5456 * Add ICMP item to matcher and to the value.
5458 * @param[in, out] matcher
5460 * @param[in, out] key
5461 * Flow matcher value.
5463 * Flow pattern to translate.
5465 * Item is inner pattern.
5468 flow_dv_translate_item_icmp(void *matcher, void *key,
5469 const struct rte_flow_item *item,
5472 const struct rte_flow_item_icmp *icmp_m = item->mask;
5473 const struct rte_flow_item_icmp *icmp_v = item->spec;
5476 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5478 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5480 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5482 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5484 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5486 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5488 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5493 icmp_m = &rte_flow_item_icmp_mask;
5494 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5495 icmp_m->hdr.icmp_type);
5496 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5497 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5498 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5499 icmp_m->hdr.icmp_code);
5500 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5501 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5504 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5506 #define HEADER_IS_ZERO(match_criteria, headers) \
5507 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5508 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5511 * Calculate flow matcher enable bitmap.
5513 * @param match_criteria
5514 * Pointer to flow matcher criteria.
5517 * Bitmap of enabled fields.
5520 flow_dv_matcher_enable(uint32_t *match_criteria)
5522 uint8_t match_criteria_enable;
5524 match_criteria_enable =
5525 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5526 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5527 match_criteria_enable |=
5528 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5529 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5530 match_criteria_enable |=
5531 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5532 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5533 match_criteria_enable |=
5534 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5535 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5536 match_criteria_enable |=
5537 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5538 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5539 return match_criteria_enable;
5546 * @param dev[in, out]
5547 * Pointer to rte_eth_dev structure.
5548 * @param[in] table_id
5551 * Direction of the table.
5552 * @param[in] transfer
5553 * E-Switch or NIC flow.
5555 * pointer to error structure.
5558 * Returns tables resource based on the index, NULL in case of failed.
5560 static struct mlx5_flow_tbl_resource *
5561 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5562 uint32_t table_id, uint8_t egress,
5564 struct rte_flow_error *error)
5566 struct mlx5_priv *priv = dev->data->dev_private;
5567 struct mlx5_ibv_shared *sh = priv->sh;
5568 struct mlx5_flow_tbl_resource *tbl;
5570 #ifdef HAVE_MLX5DV_DR
5572 tbl = &sh->fdb_tbl[table_id];
5574 tbl->obj = mlx5_glue->dr_create_flow_tbl
5575 (sh->fdb_domain, table_id);
5576 } else if (egress) {
5577 tbl = &sh->tx_tbl[table_id];
5579 tbl->obj = mlx5_glue->dr_create_flow_tbl
5580 (sh->tx_domain, table_id);
5582 tbl = &sh->rx_tbl[table_id];
5584 tbl->obj = mlx5_glue->dr_create_flow_tbl
5585 (sh->rx_domain, table_id);
5588 rte_flow_error_set(error, ENOMEM,
5589 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5590 NULL, "cannot create table");
5593 rte_atomic32_inc(&tbl->refcnt);
5599 return &sh->fdb_tbl[table_id];
5601 return &sh->tx_tbl[table_id];
5603 return &sh->rx_tbl[table_id];
5608 * Release a flow table.
5611 * Table resource to be released.
5614 * Returns 0 if table was released, else return 1;
5617 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5621 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5622 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5630 * Register the flow matcher.
5632 * @param dev[in, out]
5633 * Pointer to rte_eth_dev structure.
5634 * @param[in, out] matcher
5635 * Pointer to flow matcher.
5636 * @parm[in, out] dev_flow
5637 * Pointer to the dev_flow.
5639 * pointer to error structure.
5642 * 0 on success otherwise -errno and errno is set.
5645 flow_dv_matcher_register(struct rte_eth_dev *dev,
5646 struct mlx5_flow_dv_matcher *matcher,
5647 struct mlx5_flow *dev_flow,
5648 struct rte_flow_error *error)
5650 struct mlx5_priv *priv = dev->data->dev_private;
5651 struct mlx5_ibv_shared *sh = priv->sh;
5652 struct mlx5_flow_dv_matcher *cache_matcher;
5653 struct mlx5dv_flow_matcher_attr dv_attr = {
5654 .type = IBV_FLOW_ATTR_NORMAL,
5655 .match_mask = (void *)&matcher->mask,
5657 struct mlx5_flow_tbl_resource *tbl = NULL;
5659 /* Lookup from cache. */
5660 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5661 if (matcher->crc == cache_matcher->crc &&
5662 matcher->priority == cache_matcher->priority &&
5663 matcher->egress == cache_matcher->egress &&
5664 matcher->group == cache_matcher->group &&
5665 matcher->transfer == cache_matcher->transfer &&
5666 !memcmp((const void *)matcher->mask.buf,
5667 (const void *)cache_matcher->mask.buf,
5668 cache_matcher->mask.size)) {
5670 "priority %hd use %s matcher %p: refcnt %d++",
5671 cache_matcher->priority,
5672 cache_matcher->egress ? "tx" : "rx",
5673 (void *)cache_matcher,
5674 rte_atomic32_read(&cache_matcher->refcnt));
5675 rte_atomic32_inc(&cache_matcher->refcnt);
5676 dev_flow->dv.matcher = cache_matcher;
5680 /* Register new matcher. */
5681 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5683 return rte_flow_error_set(error, ENOMEM,
5684 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5685 "cannot allocate matcher memory");
5686 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5687 matcher->egress, matcher->transfer,
5690 rte_free(cache_matcher);
5691 return rte_flow_error_set(error, ENOMEM,
5692 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5693 NULL, "cannot create table");
5695 *cache_matcher = *matcher;
5696 dv_attr.match_criteria_enable =
5697 flow_dv_matcher_enable(cache_matcher->mask.buf);
5698 dv_attr.priority = matcher->priority;
5699 if (matcher->egress)
5700 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5701 cache_matcher->matcher_object =
5702 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5703 if (!cache_matcher->matcher_object) {
5704 rte_free(cache_matcher);
5705 #ifdef HAVE_MLX5DV_DR
5706 flow_dv_tbl_resource_release(tbl);
5708 return rte_flow_error_set(error, ENOMEM,
5709 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5710 NULL, "cannot create matcher");
5712 rte_atomic32_inc(&cache_matcher->refcnt);
5713 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5714 dev_flow->dv.matcher = cache_matcher;
5715 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5716 cache_matcher->priority,
5717 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5718 rte_atomic32_read(&cache_matcher->refcnt));
5719 rte_atomic32_inc(&tbl->refcnt);
5724 * Find existing tag resource or create and register a new one.
5726 * @param dev[in, out]
5727 * Pointer to rte_eth_dev structure.
5728 * @param[in, out] resource
5729 * Pointer to tag resource.
5730 * @parm[in, out] dev_flow
5731 * Pointer to the dev_flow.
5733 * pointer to error structure.
5736 * 0 on success otherwise -errno and errno is set.
5739 flow_dv_tag_resource_register
5740 (struct rte_eth_dev *dev,
5741 struct mlx5_flow_dv_tag_resource *resource,
5742 struct mlx5_flow *dev_flow,
5743 struct rte_flow_error *error)
5745 struct mlx5_priv *priv = dev->data->dev_private;
5746 struct mlx5_ibv_shared *sh = priv->sh;
5747 struct mlx5_flow_dv_tag_resource *cache_resource;
5749 /* Lookup a matching resource from cache. */
5750 LIST_FOREACH(cache_resource, &sh->tags, next) {
5751 if (resource->tag == cache_resource->tag) {
5752 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5753 (void *)cache_resource,
5754 rte_atomic32_read(&cache_resource->refcnt));
5755 rte_atomic32_inc(&cache_resource->refcnt);
5756 dev_flow->dv.tag_resource = cache_resource;
5760 /* Register new resource. */
5761 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5762 if (!cache_resource)
5763 return rte_flow_error_set(error, ENOMEM,
5764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5765 "cannot allocate resource memory");
5766 *cache_resource = *resource;
5767 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5769 if (!cache_resource->action) {
5770 rte_free(cache_resource);
5771 return rte_flow_error_set(error, ENOMEM,
5772 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5773 NULL, "cannot create action");
5775 rte_atomic32_init(&cache_resource->refcnt);
5776 rte_atomic32_inc(&cache_resource->refcnt);
5777 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5778 dev_flow->dv.tag_resource = cache_resource;
5779 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5780 (void *)cache_resource,
5781 rte_atomic32_read(&cache_resource->refcnt));
5789 * Pointer to Ethernet device.
5791 * Pointer to mlx5_flow.
5794 * 1 while a reference on it exists, 0 when freed.
5797 flow_dv_tag_release(struct rte_eth_dev *dev,
5798 struct mlx5_flow_dv_tag_resource *tag)
5801 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5802 dev->data->port_id, (void *)tag,
5803 rte_atomic32_read(&tag->refcnt));
5804 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5805 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5806 LIST_REMOVE(tag, next);
5807 DRV_LOG(DEBUG, "port %u tag %p: removed",
5808 dev->data->port_id, (void *)tag);
5816 * Translate port ID action to vport.
5819 * Pointer to rte_eth_dev structure.
5821 * Pointer to the port ID action.
5822 * @param[out] dst_port_id
5823 * The target port ID.
5825 * Pointer to the error structure.
5828 * 0 on success, a negative errno value otherwise and rte_errno is set.
5831 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5832 const struct rte_flow_action *action,
5833 uint32_t *dst_port_id,
5834 struct rte_flow_error *error)
5837 struct mlx5_priv *priv;
5838 const struct rte_flow_action_port_id *conf =
5839 (const struct rte_flow_action_port_id *)action->conf;
5841 port = conf->original ? dev->data->port_id : conf->id;
5842 priv = mlx5_port_to_eswitch_info(port, false);
5844 return rte_flow_error_set(error, -rte_errno,
5845 RTE_FLOW_ERROR_TYPE_ACTION,
5847 "No eswitch info was found for port");
5848 if (priv->vport_meta_mask)
5849 *dst_port_id = priv->vport_meta_tag;
5851 *dst_port_id = priv->vport_id;
5856 * Add Tx queue matcher
5859 * Pointer to the dev struct.
5860 * @param[in, out] matcher
5862 * @param[in, out] key
5863 * Flow matcher value.
5865 * Flow pattern to translate.
5867 * Item is inner pattern.
5870 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5871 void *matcher, void *key,
5872 const struct rte_flow_item *item)
5874 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5875 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5877 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5879 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5880 struct mlx5_txq_ctrl *txq;
5884 queue_m = (const void *)item->mask;
5887 queue_v = (const void *)item->spec;
5890 txq = mlx5_txq_get(dev, queue_v->queue);
5893 queue = txq->obj->sq->id;
5894 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5895 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5896 queue & queue_m->queue);
5897 mlx5_txq_release(dev, queue_v->queue);
5901 * Fill the flow with DV spec, lock free
5902 * (mutex should be acquired by caller).
5905 * Pointer to rte_eth_dev structure.
5906 * @param[in, out] dev_flow
5907 * Pointer to the sub flow.
5909 * Pointer to the flow attributes.
5911 * Pointer to the list of items.
5912 * @param[in] actions
5913 * Pointer to the list of actions.
5915 * Pointer to the error structure.
5918 * 0 on success, a negative errno value otherwise and rte_errno is set.
5921 __flow_dv_translate(struct rte_eth_dev *dev,
5922 struct mlx5_flow *dev_flow,
5923 const struct rte_flow_attr *attr,
5924 const struct rte_flow_item items[],
5925 const struct rte_flow_action actions[],
5926 struct rte_flow_error *error)
5928 struct mlx5_priv *priv = dev->data->dev_private;
5929 struct rte_flow *flow = dev_flow->flow;
5930 uint64_t item_flags = 0;
5931 uint64_t last_item = 0;
5932 uint64_t action_flags = 0;
5933 uint64_t priority = attr->priority;
5934 struct mlx5_flow_dv_matcher matcher = {
5936 .size = sizeof(matcher.mask.buf),
5940 bool actions_end = false;
5941 struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
5942 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5943 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5945 union flow_dv_attr flow_attr = { .attr = 0 };
5946 struct mlx5_flow_dv_tag_resource tag_resource;
5947 uint32_t modify_action_position = UINT32_MAX;
5948 void *match_mask = matcher.mask.buf;
5949 void *match_value = dev_flow->dv.value.buf;
5950 uint8_t next_protocol = 0xff;
5951 struct rte_vlan_hdr vlan = { 0 };
5955 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5959 dev_flow->group = table;
5961 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5962 if (priority == MLX5_FLOW_PRIO_RSVD)
5963 priority = priv->config.flow_prio - 1;
5964 for (; !actions_end ; actions++) {
5965 const struct rte_flow_action_queue *queue;
5966 const struct rte_flow_action_rss *rss;
5967 const struct rte_flow_action *action = actions;
5968 const struct rte_flow_action_count *count = action->conf;
5969 const uint8_t *rss_key;
5970 const struct rte_flow_action_jump *jump_data;
5971 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5972 struct mlx5_flow_tbl_resource *tbl;
5973 uint32_t port_id = 0;
5974 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5975 int action_type = actions->type;
5976 const struct rte_flow_action *found_action = NULL;
5978 switch (action_type) {
5979 case RTE_FLOW_ACTION_TYPE_VOID:
5981 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5982 if (flow_dv_translate_action_port_id(dev, action,
5985 port_id_resource.port_id = port_id;
5986 if (flow_dv_port_id_action_resource_register
5987 (dev, &port_id_resource, dev_flow, error))
5989 dev_flow->dv.actions[actions_n++] =
5990 dev_flow->dv.port_id_action->action;
5991 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5993 case RTE_FLOW_ACTION_TYPE_FLAG:
5995 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5996 if (!dev_flow->dv.tag_resource)
5997 if (flow_dv_tag_resource_register
5998 (dev, &tag_resource, dev_flow, error))
6000 dev_flow->dv.actions[actions_n++] =
6001 dev_flow->dv.tag_resource->action;
6002 action_flags |= MLX5_FLOW_ACTION_FLAG;
6004 case RTE_FLOW_ACTION_TYPE_MARK:
6005 tag_resource.tag = mlx5_flow_mark_set
6006 (((const struct rte_flow_action_mark *)
6007 (actions->conf))->id);
6008 if (!dev_flow->dv.tag_resource)
6009 if (flow_dv_tag_resource_register
6010 (dev, &tag_resource, dev_flow, error))
6012 dev_flow->dv.actions[actions_n++] =
6013 dev_flow->dv.tag_resource->action;
6014 action_flags |= MLX5_FLOW_ACTION_MARK;
6016 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6017 if (flow_dv_convert_action_set_tag
6019 (const struct rte_flow_action_set_tag *)
6020 actions->conf, error))
6022 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6024 case RTE_FLOW_ACTION_TYPE_DROP:
6025 action_flags |= MLX5_FLOW_ACTION_DROP;
6027 case RTE_FLOW_ACTION_TYPE_QUEUE:
6028 assert(flow->rss.queue);
6029 queue = actions->conf;
6030 flow->rss.queue_num = 1;
6031 (*flow->rss.queue)[0] = queue->index;
6032 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6034 case RTE_FLOW_ACTION_TYPE_RSS:
6035 assert(flow->rss.queue);
6036 rss = actions->conf;
6037 if (flow->rss.queue)
6038 memcpy((*flow->rss.queue), rss->queue,
6039 rss->queue_num * sizeof(uint16_t));
6040 flow->rss.queue_num = rss->queue_num;
6041 /* NULL RSS key indicates default RSS key. */
6042 rss_key = !rss->key ? rss_hash_default_key : rss->key;
6043 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
6045 * rss->level and rss.types should be set in advance
6046 * when expanding items for RSS.
6048 action_flags |= MLX5_FLOW_ACTION_RSS;
6050 case RTE_FLOW_ACTION_TYPE_COUNT:
6051 if (!priv->config.devx) {
6052 rte_errno = ENOTSUP;
6055 flow->counter = flow_dv_counter_alloc(dev,
6059 if (flow->counter == NULL)
6061 dev_flow->dv.actions[actions_n++] =
6062 flow->counter->action;
6063 action_flags |= MLX5_FLOW_ACTION_COUNT;
6066 if (rte_errno == ENOTSUP)
6067 return rte_flow_error_set
6069 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6071 "count action not supported");
6073 return rte_flow_error_set
6075 RTE_FLOW_ERROR_TYPE_ACTION,
6077 "cannot create counter"
6080 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6081 dev_flow->dv.actions[actions_n++] =
6082 priv->sh->pop_vlan_action;
6083 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6085 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6086 flow_dev_get_vlan_info_from_items(items, &vlan);
6087 vlan.eth_proto = rte_be_to_cpu_16
6088 ((((const struct rte_flow_action_of_push_vlan *)
6089 actions->conf)->ethertype));
6090 found_action = mlx5_flow_find_action
6092 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
6094 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6095 found_action = mlx5_flow_find_action
6097 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
6099 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6100 if (flow_dv_create_action_push_vlan
6101 (dev, attr, &vlan, dev_flow, error))
6103 dev_flow->dv.actions[actions_n++] =
6104 dev_flow->dv.push_vlan_res->action;
6105 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6107 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6108 /* of_vlan_push action handled this action */
6109 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
6111 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6112 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6114 flow_dev_get_vlan_info_from_items(items, &vlan);
6115 mlx5_update_vlan_vid_pcp(actions, &vlan);
6116 /* If no VLAN push - this is a modify header action */
6117 if (flow_dv_convert_action_modify_vlan_vid
6118 (&mhdr_res, actions, error))
6120 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6122 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6123 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6124 if (flow_dv_create_action_l2_encap(dev, actions,
6129 dev_flow->dv.actions[actions_n++] =
6130 dev_flow->dv.encap_decap->verbs_action;
6131 action_flags |= actions->type ==
6132 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
6133 MLX5_FLOW_ACTION_VXLAN_ENCAP :
6134 MLX5_FLOW_ACTION_NVGRE_ENCAP;
6136 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6137 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6138 if (flow_dv_create_action_l2_decap(dev, dev_flow,
6142 dev_flow->dv.actions[actions_n++] =
6143 dev_flow->dv.encap_decap->verbs_action;
6144 action_flags |= actions->type ==
6145 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
6146 MLX5_FLOW_ACTION_VXLAN_DECAP :
6147 MLX5_FLOW_ACTION_NVGRE_DECAP;
6149 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6150 /* Handle encap with preceding decap. */
6151 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
6152 if (flow_dv_create_action_raw_encap
6153 (dev, actions, dev_flow, attr, error))
6155 dev_flow->dv.actions[actions_n++] =
6156 dev_flow->dv.encap_decap->verbs_action;
6158 /* Handle encap without preceding decap. */
6159 if (flow_dv_create_action_l2_encap
6160 (dev, actions, dev_flow, attr->transfer,
6163 dev_flow->dv.actions[actions_n++] =
6164 dev_flow->dv.encap_decap->verbs_action;
6166 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
6168 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6169 /* Check if this decap is followed by encap. */
6170 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
6171 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
6174 /* Handle decap only if it isn't followed by encap. */
6175 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6176 if (flow_dv_create_action_l2_decap
6177 (dev, dev_flow, attr->transfer, error))
6179 dev_flow->dv.actions[actions_n++] =
6180 dev_flow->dv.encap_decap->verbs_action;
6182 /* If decap is followed by encap, handle it at encap. */
6183 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
6185 case RTE_FLOW_ACTION_TYPE_JUMP:
6186 jump_data = action->conf;
6187 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
6188 jump_data->group, &table,
6192 tbl = flow_dv_tbl_resource_get(dev, table,
6194 attr->transfer, error);
6196 return rte_flow_error_set
6198 RTE_FLOW_ERROR_TYPE_ACTION,
6200 "cannot create jump action.");
6201 jump_tbl_resource.tbl = tbl;
6202 if (flow_dv_jump_tbl_resource_register
6203 (dev, &jump_tbl_resource, dev_flow, error)) {
6204 flow_dv_tbl_resource_release(tbl);
6205 return rte_flow_error_set
6207 RTE_FLOW_ERROR_TYPE_ACTION,
6209 "cannot create jump action.");
6211 dev_flow->dv.actions[actions_n++] =
6212 dev_flow->dv.jump->action;
6213 action_flags |= MLX5_FLOW_ACTION_JUMP;
6215 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6216 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6217 if (flow_dv_convert_action_modify_mac
6218 (&mhdr_res, actions, error))
6220 action_flags |= actions->type ==
6221 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6222 MLX5_FLOW_ACTION_SET_MAC_SRC :
6223 MLX5_FLOW_ACTION_SET_MAC_DST;
6225 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6226 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6227 if (flow_dv_convert_action_modify_ipv4
6228 (&mhdr_res, actions, error))
6230 action_flags |= actions->type ==
6231 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6232 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6233 MLX5_FLOW_ACTION_SET_IPV4_DST;
6235 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6236 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6237 if (flow_dv_convert_action_modify_ipv6
6238 (&mhdr_res, actions, error))
6240 action_flags |= actions->type ==
6241 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6242 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6243 MLX5_FLOW_ACTION_SET_IPV6_DST;
6245 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6246 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6247 if (flow_dv_convert_action_modify_tp
6248 (&mhdr_res, actions, items,
6251 action_flags |= actions->type ==
6252 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6253 MLX5_FLOW_ACTION_SET_TP_SRC :
6254 MLX5_FLOW_ACTION_SET_TP_DST;
6256 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6257 if (flow_dv_convert_action_modify_dec_ttl
6258 (&mhdr_res, items, &flow_attr, error))
6260 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
6262 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6263 if (flow_dv_convert_action_modify_ttl
6264 (&mhdr_res, actions, items,
6267 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
6269 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6270 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6271 if (flow_dv_convert_action_modify_tcp_seq
6272 (&mhdr_res, actions, error))
6274 action_flags |= actions->type ==
6275 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6276 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6277 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6280 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6281 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6282 if (flow_dv_convert_action_modify_tcp_ack
6283 (&mhdr_res, actions, error))
6285 action_flags |= actions->type ==
6286 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6287 MLX5_FLOW_ACTION_INC_TCP_ACK :
6288 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6290 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6291 if (flow_dv_convert_action_set_reg
6292 (&mhdr_res, actions, error))
6294 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6296 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6297 if (flow_dv_convert_action_copy_mreg
6298 (dev, &mhdr_res, actions, error))
6300 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6302 case RTE_FLOW_ACTION_TYPE_END:
6304 if (mhdr_res.actions_num) {
6305 /* create modify action if needed. */
6306 if (flow_dv_modify_hdr_resource_register
6307 (dev, &mhdr_res, dev_flow, error))
6309 dev_flow->dv.actions[modify_action_position] =
6310 dev_flow->dv.modify_hdr->verbs_action;
6316 if (mhdr_res.actions_num &&
6317 modify_action_position == UINT32_MAX)
6318 modify_action_position = actions_n++;
6320 dev_flow->dv.actions_n = actions_n;
6321 dev_flow->actions = action_flags;
6322 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6323 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6324 int item_type = items->type;
6326 switch (item_type) {
6327 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6328 flow_dv_translate_item_port_id(dev, match_mask,
6329 match_value, items);
6330 last_item = MLX5_FLOW_ITEM_PORT_ID;
6332 case RTE_FLOW_ITEM_TYPE_ETH:
6333 flow_dv_translate_item_eth(match_mask, match_value,
6335 matcher.priority = MLX5_PRIORITY_MAP_L2;
6336 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6337 MLX5_FLOW_LAYER_OUTER_L2;
6339 case RTE_FLOW_ITEM_TYPE_VLAN:
6340 flow_dv_translate_item_vlan(dev_flow,
6341 match_mask, match_value,
6343 matcher.priority = MLX5_PRIORITY_MAP_L2;
6344 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6345 MLX5_FLOW_LAYER_INNER_VLAN) :
6346 (MLX5_FLOW_LAYER_OUTER_L2 |
6347 MLX5_FLOW_LAYER_OUTER_VLAN);
6349 case RTE_FLOW_ITEM_TYPE_IPV4:
6350 mlx5_flow_tunnel_ip_check(items, next_protocol,
6351 &item_flags, &tunnel);
6352 flow_dv_translate_item_ipv4(match_mask, match_value,
6355 matcher.priority = MLX5_PRIORITY_MAP_L3;
6356 dev_flow->hash_fields |=
6357 mlx5_flow_hashfields_adjust
6359 MLX5_IPV4_LAYER_TYPES,
6360 MLX5_IPV4_IBV_RX_HASH);
6361 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6362 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6363 if (items->mask != NULL &&
6364 ((const struct rte_flow_item_ipv4 *)
6365 items->mask)->hdr.next_proto_id) {
6367 ((const struct rte_flow_item_ipv4 *)
6368 (items->spec))->hdr.next_proto_id;
6370 ((const struct rte_flow_item_ipv4 *)
6371 (items->mask))->hdr.next_proto_id;
6373 /* Reset for inner layer. */
6374 next_protocol = 0xff;
6377 case RTE_FLOW_ITEM_TYPE_IPV6:
6378 mlx5_flow_tunnel_ip_check(items, next_protocol,
6379 &item_flags, &tunnel);
6380 flow_dv_translate_item_ipv6(match_mask, match_value,
6383 matcher.priority = MLX5_PRIORITY_MAP_L3;
6384 dev_flow->hash_fields |=
6385 mlx5_flow_hashfields_adjust
6387 MLX5_IPV6_LAYER_TYPES,
6388 MLX5_IPV6_IBV_RX_HASH);
6389 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6390 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6391 if (items->mask != NULL &&
6392 ((const struct rte_flow_item_ipv6 *)
6393 items->mask)->hdr.proto) {
6395 ((const struct rte_flow_item_ipv6 *)
6396 items->spec)->hdr.proto;
6398 ((const struct rte_flow_item_ipv6 *)
6399 items->mask)->hdr.proto;
6401 /* Reset for inner layer. */
6402 next_protocol = 0xff;
6405 case RTE_FLOW_ITEM_TYPE_TCP:
6406 flow_dv_translate_item_tcp(match_mask, match_value,
6408 matcher.priority = MLX5_PRIORITY_MAP_L4;
6409 dev_flow->hash_fields |=
6410 mlx5_flow_hashfields_adjust
6411 (dev_flow, tunnel, ETH_RSS_TCP,
6412 IBV_RX_HASH_SRC_PORT_TCP |
6413 IBV_RX_HASH_DST_PORT_TCP);
6414 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6415 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6417 case RTE_FLOW_ITEM_TYPE_UDP:
6418 flow_dv_translate_item_udp(match_mask, match_value,
6420 matcher.priority = MLX5_PRIORITY_MAP_L4;
6421 dev_flow->hash_fields |=
6422 mlx5_flow_hashfields_adjust
6423 (dev_flow, tunnel, ETH_RSS_UDP,
6424 IBV_RX_HASH_SRC_PORT_UDP |
6425 IBV_RX_HASH_DST_PORT_UDP);
6426 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6427 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6429 case RTE_FLOW_ITEM_TYPE_GRE:
6430 flow_dv_translate_item_gre(match_mask, match_value,
6432 last_item = MLX5_FLOW_LAYER_GRE;
6434 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6435 flow_dv_translate_item_gre_key(match_mask,
6436 match_value, items);
6437 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6439 case RTE_FLOW_ITEM_TYPE_NVGRE:
6440 flow_dv_translate_item_nvgre(match_mask, match_value,
6442 last_item = MLX5_FLOW_LAYER_GRE;
6444 case RTE_FLOW_ITEM_TYPE_VXLAN:
6445 flow_dv_translate_item_vxlan(match_mask, match_value,
6447 last_item = MLX5_FLOW_LAYER_VXLAN;
6449 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6450 flow_dv_translate_item_vxlan(match_mask, match_value,
6452 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6454 case RTE_FLOW_ITEM_TYPE_GENEVE:
6455 flow_dv_translate_item_geneve(match_mask, match_value,
6457 last_item = MLX5_FLOW_LAYER_GENEVE;
6459 case RTE_FLOW_ITEM_TYPE_MPLS:
6460 flow_dv_translate_item_mpls(match_mask, match_value,
6461 items, last_item, tunnel);
6462 last_item = MLX5_FLOW_LAYER_MPLS;
6464 case RTE_FLOW_ITEM_TYPE_META:
6465 flow_dv_translate_item_meta(match_mask, match_value,
6467 last_item = MLX5_FLOW_ITEM_METADATA;
6469 case RTE_FLOW_ITEM_TYPE_ICMP:
6470 flow_dv_translate_item_icmp(match_mask, match_value,
6472 last_item = MLX5_FLOW_LAYER_ICMP;
6474 case RTE_FLOW_ITEM_TYPE_ICMP6:
6475 flow_dv_translate_item_icmp6(match_mask, match_value,
6477 last_item = MLX5_FLOW_LAYER_ICMP6;
6479 case RTE_FLOW_ITEM_TYPE_TAG:
6480 flow_dv_translate_item_tag(dev, match_mask,
6481 match_value, items);
6482 last_item = MLX5_FLOW_ITEM_TAG;
6484 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6485 flow_dv_translate_mlx5_item_tag(match_mask,
6486 match_value, items);
6487 last_item = MLX5_FLOW_ITEM_TAG;
6489 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6490 flow_dv_translate_item_tx_queue(dev, match_mask,
6493 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6498 item_flags |= last_item;
6501 * In case of ingress traffic when E-Switch mode is enabled,
6502 * we have two cases where we need to set the source port manually.
6503 * The first one, is in case of Nic steering rule, and the second is
6504 * E-Switch rule where no port_id item was found. In both cases
6505 * the source port is set according the current port in use.
6507 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6508 (priv->representor || priv->master)) {
6509 if (flow_dv_translate_item_port_id(dev, match_mask,
6513 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6514 dev_flow->dv.value.buf));
6515 dev_flow->layers = item_flags;
6516 /* Register matcher. */
6517 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6519 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6521 matcher.egress = attr->egress;
6522 matcher.group = dev_flow->group;
6523 matcher.transfer = attr->transfer;
6524 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6530 * Apply the flow to the NIC, lock free,
6531 * (mutex should be acquired by caller).
6534 * Pointer to the Ethernet device structure.
6535 * @param[in, out] flow
6536 * Pointer to flow structure.
6538 * Pointer to error structure.
6541 * 0 on success, a negative errno value otherwise and rte_errno is set.
6544 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6545 struct rte_flow_error *error)
6547 struct mlx5_flow_dv *dv;
6548 struct mlx5_flow *dev_flow;
6549 struct mlx5_priv *priv = dev->data->dev_private;
6553 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6556 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6557 if (dev_flow->transfer) {
6558 dv->actions[n++] = priv->sh->esw_drop_action;
6560 dv->hrxq = mlx5_hrxq_drop_new(dev);
6564 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6566 "cannot get drop hash queue");
6569 dv->actions[n++] = dv->hrxq->action;
6571 } else if (dev_flow->actions &
6572 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6573 struct mlx5_hrxq *hrxq;
6575 assert(flow->rss.queue);
6576 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
6577 MLX5_RSS_HASH_KEY_LEN,
6578 dev_flow->hash_fields,
6580 flow->rss.queue_num);
6582 hrxq = mlx5_hrxq_new
6583 (dev, flow->rss.key,
6584 MLX5_RSS_HASH_KEY_LEN,
6585 dev_flow->hash_fields,
6587 flow->rss.queue_num,
6588 !!(dev_flow->layers &
6589 MLX5_FLOW_LAYER_TUNNEL));
6594 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6595 "cannot get hash queue");
6599 dv->actions[n++] = dv->hrxq->action;
6602 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6603 (void *)&dv->value, n,
6606 rte_flow_error_set(error, errno,
6607 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6609 "hardware refuses to create flow");
6612 if (priv->vmwa_context &&
6613 dev_flow->dv.vf_vlan.tag &&
6614 !dev_flow->dv.vf_vlan.created) {
6616 * The rule contains the VLAN pattern.
6617 * For VF we are going to create VLAN
6618 * interface to make hypervisor set correct
6619 * e-Switch vport context.
6621 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6626 err = rte_errno; /* Save rte_errno before cleanup. */
6627 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6628 struct mlx5_flow_dv *dv = &dev_flow->dv;
6630 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6631 mlx5_hrxq_drop_release(dev);
6633 mlx5_hrxq_release(dev, dv->hrxq);
6636 if (dev_flow->dv.vf_vlan.tag &&
6637 dev_flow->dv.vf_vlan.created)
6638 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6640 rte_errno = err; /* Restore rte_errno. */
6645 * Release the flow matcher.
6648 * Pointer to Ethernet device.
6650 * Pointer to mlx5_flow.
6653 * 1 while a reference on it exists, 0 when freed.
6656 flow_dv_matcher_release(struct rte_eth_dev *dev,
6657 struct mlx5_flow *flow)
6659 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6660 struct mlx5_priv *priv = dev->data->dev_private;
6661 struct mlx5_ibv_shared *sh = priv->sh;
6662 struct mlx5_flow_tbl_resource *tbl;
6664 assert(matcher->matcher_object);
6665 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6666 dev->data->port_id, (void *)matcher,
6667 rte_atomic32_read(&matcher->refcnt));
6668 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6669 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6670 (matcher->matcher_object));
6671 LIST_REMOVE(matcher, next);
6672 if (matcher->egress)
6673 tbl = &sh->tx_tbl[matcher->group];
6675 tbl = &sh->rx_tbl[matcher->group];
6676 flow_dv_tbl_resource_release(tbl);
6678 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6679 dev->data->port_id, (void *)matcher);
6686 * Release an encap/decap resource.
6689 * Pointer to mlx5_flow.
6692 * 1 while a reference on it exists, 0 when freed.
6695 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6697 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6698 flow->dv.encap_decap;
6700 assert(cache_resource->verbs_action);
6701 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6702 (void *)cache_resource,
6703 rte_atomic32_read(&cache_resource->refcnt));
6704 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6705 claim_zero(mlx5_glue->destroy_flow_action
6706 (cache_resource->verbs_action));
6707 LIST_REMOVE(cache_resource, next);
6708 rte_free(cache_resource);
6709 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6710 (void *)cache_resource);
6717 * Release an jump to table action resource.
6720 * Pointer to mlx5_flow.
6723 * 1 while a reference on it exists, 0 when freed.
6726 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6728 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6731 assert(cache_resource->action);
6732 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6733 (void *)cache_resource,
6734 rte_atomic32_read(&cache_resource->refcnt));
6735 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6736 claim_zero(mlx5_glue->destroy_flow_action
6737 (cache_resource->action));
6738 LIST_REMOVE(cache_resource, next);
6739 flow_dv_tbl_resource_release(cache_resource->tbl);
6740 rte_free(cache_resource);
6741 DRV_LOG(DEBUG, "jump table resource %p: removed",
6742 (void *)cache_resource);
6749 * Release a modify-header resource.
6752 * Pointer to mlx5_flow.
6755 * 1 while a reference on it exists, 0 when freed.
6758 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6760 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6761 flow->dv.modify_hdr;
6763 assert(cache_resource->verbs_action);
6764 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6765 (void *)cache_resource,
6766 rte_atomic32_read(&cache_resource->refcnt));
6767 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6768 claim_zero(mlx5_glue->destroy_flow_action
6769 (cache_resource->verbs_action));
6770 LIST_REMOVE(cache_resource, next);
6771 rte_free(cache_resource);
6772 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6773 (void *)cache_resource);
6780 * Release port ID action resource.
6783 * Pointer to mlx5_flow.
6786 * 1 while a reference on it exists, 0 when freed.
6789 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6791 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6792 flow->dv.port_id_action;
6794 assert(cache_resource->action);
6795 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6796 (void *)cache_resource,
6797 rte_atomic32_read(&cache_resource->refcnt));
6798 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6799 claim_zero(mlx5_glue->destroy_flow_action
6800 (cache_resource->action));
6801 LIST_REMOVE(cache_resource, next);
6802 rte_free(cache_resource);
6803 DRV_LOG(DEBUG, "port id action resource %p: removed",
6804 (void *)cache_resource);
6811 * Release push vlan action resource.
6814 * Pointer to mlx5_flow.
6817 * 1 while a reference on it exists, 0 when freed.
6820 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6822 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6823 flow->dv.push_vlan_res;
6825 assert(cache_resource->action);
6826 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6827 (void *)cache_resource,
6828 rte_atomic32_read(&cache_resource->refcnt));
6829 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6830 claim_zero(mlx5_glue->destroy_flow_action
6831 (cache_resource->action));
6832 LIST_REMOVE(cache_resource, next);
6833 rte_free(cache_resource);
6834 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6835 (void *)cache_resource);
6842 * Remove the flow from the NIC but keeps it in memory.
6843 * Lock free, (mutex should be acquired by caller).
6846 * Pointer to Ethernet device.
6847 * @param[in, out] flow
6848 * Pointer to flow structure.
6851 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6853 struct mlx5_flow_dv *dv;
6854 struct mlx5_flow *dev_flow;
6858 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6861 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6865 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6866 mlx5_hrxq_drop_release(dev);
6868 mlx5_hrxq_release(dev, dv->hrxq);
6871 if (dev_flow->dv.vf_vlan.tag &&
6872 dev_flow->dv.vf_vlan.created)
6873 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6878 * Remove the flow from the NIC and the memory.
6879 * Lock free, (mutex should be acquired by caller).
6882 * Pointer to the Ethernet device structure.
6883 * @param[in, out] flow
6884 * Pointer to flow structure.
6887 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6889 struct mlx5_flow *dev_flow;
6893 __flow_dv_remove(dev, flow);
6894 if (flow->counter) {
6895 flow_dv_counter_release(dev, flow->counter);
6896 flow->counter = NULL;
6898 while (!LIST_EMPTY(&flow->dev_flows)) {
6899 dev_flow = LIST_FIRST(&flow->dev_flows);
6900 LIST_REMOVE(dev_flow, next);
6901 if (dev_flow->dv.matcher)
6902 flow_dv_matcher_release(dev, dev_flow);
6903 if (dev_flow->dv.encap_decap)
6904 flow_dv_encap_decap_resource_release(dev_flow);
6905 if (dev_flow->dv.modify_hdr)
6906 flow_dv_modify_hdr_resource_release(dev_flow);
6907 if (dev_flow->dv.jump)
6908 flow_dv_jump_tbl_resource_release(dev_flow);
6909 if (dev_flow->dv.port_id_action)
6910 flow_dv_port_id_action_resource_release(dev_flow);
6911 if (dev_flow->dv.push_vlan_res)
6912 flow_dv_push_vlan_action_resource_release(dev_flow);
6913 if (dev_flow->dv.tag_resource)
6914 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
6920 * Query a dv flow rule for its statistics via devx.
6923 * Pointer to Ethernet device.
6925 * Pointer to the sub flow.
6927 * data retrieved by the query.
6929 * Perform verbose error reporting if not NULL.
6932 * 0 on success, a negative errno value otherwise and rte_errno is set.
6935 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6936 void *data, struct rte_flow_error *error)
6938 struct mlx5_priv *priv = dev->data->dev_private;
6939 struct rte_flow_query_count *qc = data;
6941 if (!priv->config.devx)
6942 return rte_flow_error_set(error, ENOTSUP,
6943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6945 "counters are not supported");
6946 if (flow->counter) {
6947 uint64_t pkts, bytes;
6948 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6952 return rte_flow_error_set(error, -err,
6953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6954 NULL, "cannot read counters");
6957 qc->hits = pkts - flow->counter->hits;
6958 qc->bytes = bytes - flow->counter->bytes;
6960 flow->counter->hits = pkts;
6961 flow->counter->bytes = bytes;
6965 return rte_flow_error_set(error, EINVAL,
6966 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6968 "counters are not available");
6974 * @see rte_flow_query()
6978 flow_dv_query(struct rte_eth_dev *dev,
6979 struct rte_flow *flow __rte_unused,
6980 const struct rte_flow_action *actions __rte_unused,
6981 void *data __rte_unused,
6982 struct rte_flow_error *error __rte_unused)
6986 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6987 switch (actions->type) {
6988 case RTE_FLOW_ACTION_TYPE_VOID:
6990 case RTE_FLOW_ACTION_TYPE_COUNT:
6991 ret = flow_dv_query_count(dev, flow, data, error);
6994 return rte_flow_error_set(error, ENOTSUP,
6995 RTE_FLOW_ERROR_TYPE_ACTION,
6997 "action not supported");
7004 * Mutex-protected thunk to lock-free __flow_dv_translate().
7007 flow_dv_translate(struct rte_eth_dev *dev,
7008 struct mlx5_flow *dev_flow,
7009 const struct rte_flow_attr *attr,
7010 const struct rte_flow_item items[],
7011 const struct rte_flow_action actions[],
7012 struct rte_flow_error *error)
7016 flow_dv_shared_lock(dev);
7017 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
7018 flow_dv_shared_unlock(dev);
7023 * Mutex-protected thunk to lock-free __flow_dv_apply().
7026 flow_dv_apply(struct rte_eth_dev *dev,
7027 struct rte_flow *flow,
7028 struct rte_flow_error *error)
7032 flow_dv_shared_lock(dev);
7033 ret = __flow_dv_apply(dev, flow, error);
7034 flow_dv_shared_unlock(dev);
7039 * Mutex-protected thunk to lock-free __flow_dv_remove().
7042 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7044 flow_dv_shared_lock(dev);
7045 __flow_dv_remove(dev, flow);
7046 flow_dv_shared_unlock(dev);
7050 * Mutex-protected thunk to lock-free __flow_dv_destroy().
7053 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
7055 flow_dv_shared_lock(dev);
7056 __flow_dv_destroy(dev, flow);
7057 flow_dv_shared_unlock(dev);
7060 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
7061 .validate = flow_dv_validate,
7062 .prepare = flow_dv_prepare,
7063 .translate = flow_dv_translate,
7064 .apply = flow_dv_apply,
7065 .remove = flow_dv_remove,
7066 .destroy = flow_dv_destroy,
7067 .query = flow_dv_query,
7070 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */