1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
31 #include "mlx5_defs.h"
32 #include "mlx5_glue.h"
33 #include "mlx5_flow.h"
35 #include "mlx5_rxtx.h"
37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
43 #ifndef HAVE_MLX5DV_DR_ESWITCH
44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
49 #ifndef HAVE_MLX5DV_DR
50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
65 #define MLX5_FLOW_IPV4_LRO (1 << 0)
66 #define MLX5_FLOW_IPV6_LRO (1 << 1)
69 * Initialize flow attributes structure according to flow items' types.
72 * Pointer to item specification.
74 * Pointer to flow attributes structure.
77 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
79 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
81 case RTE_FLOW_ITEM_TYPE_IPV4:
84 case RTE_FLOW_ITEM_TYPE_IPV6:
87 case RTE_FLOW_ITEM_TYPE_UDP:
90 case RTE_FLOW_ITEM_TYPE_TCP:
100 struct field_modify_info {
101 uint32_t size; /* Size of field in protocol header, in bytes. */
102 uint32_t offset; /* Offset of field in protocol header, in bytes. */
103 enum mlx5_modification_field id;
106 struct field_modify_info modify_eth[] = {
107 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
108 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
109 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
110 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
114 struct field_modify_info modify_ipv4[] = {
115 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
116 {4, 12, MLX5_MODI_OUT_SIPV4},
117 {4, 16, MLX5_MODI_OUT_DIPV4},
121 struct field_modify_info modify_ipv6[] = {
122 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
123 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
124 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
125 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
126 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
127 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
128 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
129 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
130 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
134 struct field_modify_info modify_udp[] = {
135 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
136 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
140 struct field_modify_info modify_tcp[] = {
141 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
142 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
143 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
144 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
149 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item, uint64_t *flags)
151 uint8_t next_protocol = 0xFF;
153 if (item->mask != NULL) {
154 switch (item->type) {
155 case RTE_FLOW_ITEM_TYPE_IPV4:
157 ((const struct rte_flow_item_ipv4 *)
158 (item->spec))->hdr.next_proto_id;
160 ((const struct rte_flow_item_ipv4 *)
161 (item->mask))->hdr.next_proto_id;
163 case RTE_FLOW_ITEM_TYPE_IPV6:
165 ((const struct rte_flow_item_ipv6 *)
166 (item->spec))->hdr.proto;
168 ((const struct rte_flow_item_ipv6 *)
169 (item->mask))->hdr.proto;
175 if (next_protocol == IPPROTO_IPIP)
176 *flags |= MLX5_FLOW_LAYER_IPIP;
177 if (next_protocol == IPPROTO_IPV6)
178 *flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
182 * Acquire the synchronizing object to protect multithreaded access
183 * to shared dv context. Lock occurs only if context is actually
184 * shared, i.e. we have multiport IB device and representors are
188 * Pointer to the rte_eth_dev structure.
191 flow_d_shared_lock(struct rte_eth_dev *dev)
193 struct mlx5_priv *priv = dev->data->dev_private;
194 struct mlx5_ibv_shared *sh = priv->sh;
196 if (sh->dv_refcnt > 1) {
199 ret = pthread_mutex_lock(&sh->dv_mutex);
206 flow_d_shared_unlock(struct rte_eth_dev *dev)
208 struct mlx5_priv *priv = dev->data->dev_private;
209 struct mlx5_ibv_shared *sh = priv->sh;
211 if (sh->dv_refcnt > 1) {
214 ret = pthread_mutex_unlock(&sh->dv_mutex);
221 * Convert modify-header action to DV specification.
224 * Pointer to item specification.
226 * Pointer to field modification information.
227 * @param[in,out] resource
228 * Pointer to the modify-header resource.
230 * Type of modification.
232 * Pointer to the error structure.
235 * 0 on success, a negative errno value otherwise and rte_errno is set.
238 flow_dv_convert_modify_action(struct rte_flow_item *item,
239 struct field_modify_info *field,
240 struct mlx5_flow_dv_modify_hdr_resource *resource,
242 struct rte_flow_error *error)
244 uint32_t i = resource->actions_num;
245 struct mlx5_modification_cmd *actions = resource->actions;
246 const uint8_t *spec = item->spec;
247 const uint8_t *mask = item->mask;
250 while (field->size) {
252 /* Generate modify command for each mask segment. */
253 memcpy(&set, &mask[field->offset], field->size);
255 if (i >= MLX5_MODIFY_NUM)
256 return rte_flow_error_set(error, EINVAL,
257 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
258 "too many items to modify");
259 actions[i].action_type = type;
260 actions[i].field = field->id;
261 actions[i].length = field->size ==
262 4 ? 0 : field->size * 8;
263 rte_memcpy(&actions[i].data[4 - field->size],
264 &spec[field->offset], field->size);
265 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
268 if (resource->actions_num != i)
269 resource->actions_num = i;
272 if (!resource->actions_num)
273 return rte_flow_error_set(error, EINVAL,
274 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
275 "invalid modification flow item");
280 * Convert modify-header set IPv4 address action to DV specification.
282 * @param[in,out] resource
283 * Pointer to the modify-header resource.
285 * Pointer to action specification.
287 * Pointer to the error structure.
290 * 0 on success, a negative errno value otherwise and rte_errno is set.
293 flow_dv_convert_action_modify_ipv4
294 (struct mlx5_flow_dv_modify_hdr_resource *resource,
295 const struct rte_flow_action *action,
296 struct rte_flow_error *error)
298 const struct rte_flow_action_set_ipv4 *conf =
299 (const struct rte_flow_action_set_ipv4 *)(action->conf);
300 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
301 struct rte_flow_item_ipv4 ipv4;
302 struct rte_flow_item_ipv4 ipv4_mask;
304 memset(&ipv4, 0, sizeof(ipv4));
305 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
306 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
307 ipv4.hdr.src_addr = conf->ipv4_addr;
308 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
310 ipv4.hdr.dst_addr = conf->ipv4_addr;
311 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
314 item.mask = &ipv4_mask;
315 return flow_dv_convert_modify_action(&item, modify_ipv4, resource,
316 MLX5_MODIFICATION_TYPE_SET, error);
320 * Convert modify-header set IPv6 address action to DV specification.
322 * @param[in,out] resource
323 * Pointer to the modify-header resource.
325 * Pointer to action specification.
327 * Pointer to the error structure.
330 * 0 on success, a negative errno value otherwise and rte_errno is set.
333 flow_dv_convert_action_modify_ipv6
334 (struct mlx5_flow_dv_modify_hdr_resource *resource,
335 const struct rte_flow_action *action,
336 struct rte_flow_error *error)
338 const struct rte_flow_action_set_ipv6 *conf =
339 (const struct rte_flow_action_set_ipv6 *)(action->conf);
340 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
341 struct rte_flow_item_ipv6 ipv6;
342 struct rte_flow_item_ipv6 ipv6_mask;
344 memset(&ipv6, 0, sizeof(ipv6));
345 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
346 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
347 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
348 sizeof(ipv6.hdr.src_addr));
349 memcpy(&ipv6_mask.hdr.src_addr,
350 &rte_flow_item_ipv6_mask.hdr.src_addr,
351 sizeof(ipv6.hdr.src_addr));
353 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
354 sizeof(ipv6.hdr.dst_addr));
355 memcpy(&ipv6_mask.hdr.dst_addr,
356 &rte_flow_item_ipv6_mask.hdr.dst_addr,
357 sizeof(ipv6.hdr.dst_addr));
360 item.mask = &ipv6_mask;
361 return flow_dv_convert_modify_action(&item, modify_ipv6, resource,
362 MLX5_MODIFICATION_TYPE_SET, error);
366 * Convert modify-header set MAC address action to DV specification.
368 * @param[in,out] resource
369 * Pointer to the modify-header resource.
371 * Pointer to action specification.
373 * Pointer to the error structure.
376 * 0 on success, a negative errno value otherwise and rte_errno is set.
379 flow_dv_convert_action_modify_mac
380 (struct mlx5_flow_dv_modify_hdr_resource *resource,
381 const struct rte_flow_action *action,
382 struct rte_flow_error *error)
384 const struct rte_flow_action_set_mac *conf =
385 (const struct rte_flow_action_set_mac *)(action->conf);
386 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
387 struct rte_flow_item_eth eth;
388 struct rte_flow_item_eth eth_mask;
390 memset(ð, 0, sizeof(eth));
391 memset(ð_mask, 0, sizeof(eth_mask));
392 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
393 memcpy(ð.src.addr_bytes, &conf->mac_addr,
394 sizeof(eth.src.addr_bytes));
395 memcpy(ð_mask.src.addr_bytes,
396 &rte_flow_item_eth_mask.src.addr_bytes,
397 sizeof(eth_mask.src.addr_bytes));
399 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
400 sizeof(eth.dst.addr_bytes));
401 memcpy(ð_mask.dst.addr_bytes,
402 &rte_flow_item_eth_mask.dst.addr_bytes,
403 sizeof(eth_mask.dst.addr_bytes));
406 item.mask = ð_mask;
407 return flow_dv_convert_modify_action(&item, modify_eth, resource,
408 MLX5_MODIFICATION_TYPE_SET, error);
412 * Convert modify-header set TP action to DV specification.
414 * @param[in,out] resource
415 * Pointer to the modify-header resource.
417 * Pointer to action specification.
419 * Pointer to rte_flow_item objects list.
421 * Pointer to flow attributes structure.
423 * Pointer to the error structure.
426 * 0 on success, a negative errno value otherwise and rte_errno is set.
429 flow_dv_convert_action_modify_tp
430 (struct mlx5_flow_dv_modify_hdr_resource *resource,
431 const struct rte_flow_action *action,
432 const struct rte_flow_item *items,
433 union flow_dv_attr *attr,
434 struct rte_flow_error *error)
436 const struct rte_flow_action_set_tp *conf =
437 (const struct rte_flow_action_set_tp *)(action->conf);
438 struct rte_flow_item item;
439 struct rte_flow_item_udp udp;
440 struct rte_flow_item_udp udp_mask;
441 struct rte_flow_item_tcp tcp;
442 struct rte_flow_item_tcp tcp_mask;
443 struct field_modify_info *field;
446 flow_dv_attr_init(items, attr);
448 memset(&udp, 0, sizeof(udp));
449 memset(&udp_mask, 0, sizeof(udp_mask));
450 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
451 udp.hdr.src_port = conf->port;
452 udp_mask.hdr.src_port =
453 rte_flow_item_udp_mask.hdr.src_port;
455 udp.hdr.dst_port = conf->port;
456 udp_mask.hdr.dst_port =
457 rte_flow_item_udp_mask.hdr.dst_port;
459 item.type = RTE_FLOW_ITEM_TYPE_UDP;
461 item.mask = &udp_mask;
465 memset(&tcp, 0, sizeof(tcp));
466 memset(&tcp_mask, 0, sizeof(tcp_mask));
467 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
468 tcp.hdr.src_port = conf->port;
469 tcp_mask.hdr.src_port =
470 rte_flow_item_tcp_mask.hdr.src_port;
472 tcp.hdr.dst_port = conf->port;
473 tcp_mask.hdr.dst_port =
474 rte_flow_item_tcp_mask.hdr.dst_port;
476 item.type = RTE_FLOW_ITEM_TYPE_TCP;
478 item.mask = &tcp_mask;
481 return flow_dv_convert_modify_action(&item, field, resource,
482 MLX5_MODIFICATION_TYPE_SET, error);
486 * Convert modify-header set TTL action to DV specification.
488 * @param[in,out] resource
489 * Pointer to the modify-header resource.
491 * Pointer to action specification.
493 * Pointer to rte_flow_item objects list.
495 * Pointer to flow attributes structure.
497 * Pointer to the error structure.
500 * 0 on success, a negative errno value otherwise and rte_errno is set.
503 flow_dv_convert_action_modify_ttl
504 (struct mlx5_flow_dv_modify_hdr_resource *resource,
505 const struct rte_flow_action *action,
506 const struct rte_flow_item *items,
507 union flow_dv_attr *attr,
508 struct rte_flow_error *error)
510 const struct rte_flow_action_set_ttl *conf =
511 (const struct rte_flow_action_set_ttl *)(action->conf);
512 struct rte_flow_item item;
513 struct rte_flow_item_ipv4 ipv4;
514 struct rte_flow_item_ipv4 ipv4_mask;
515 struct rte_flow_item_ipv6 ipv6;
516 struct rte_flow_item_ipv6 ipv6_mask;
517 struct field_modify_info *field;
520 flow_dv_attr_init(items, attr);
522 memset(&ipv4, 0, sizeof(ipv4));
523 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
524 ipv4.hdr.time_to_live = conf->ttl_value;
525 ipv4_mask.hdr.time_to_live = 0xFF;
526 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
528 item.mask = &ipv4_mask;
532 memset(&ipv6, 0, sizeof(ipv6));
533 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
534 ipv6.hdr.hop_limits = conf->ttl_value;
535 ipv6_mask.hdr.hop_limits = 0xFF;
536 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
538 item.mask = &ipv6_mask;
541 return flow_dv_convert_modify_action(&item, field, resource,
542 MLX5_MODIFICATION_TYPE_SET, error);
546 * Convert modify-header decrement TTL action to DV specification.
548 * @param[in,out] resource
549 * Pointer to the modify-header resource.
551 * Pointer to action specification.
553 * Pointer to rte_flow_item objects list.
555 * Pointer to flow attributes structure.
557 * Pointer to the error structure.
560 * 0 on success, a negative errno value otherwise and rte_errno is set.
563 flow_dv_convert_action_modify_dec_ttl
564 (struct mlx5_flow_dv_modify_hdr_resource *resource,
565 const struct rte_flow_item *items,
566 union flow_dv_attr *attr,
567 struct rte_flow_error *error)
569 struct rte_flow_item item;
570 struct rte_flow_item_ipv4 ipv4;
571 struct rte_flow_item_ipv4 ipv4_mask;
572 struct rte_flow_item_ipv6 ipv6;
573 struct rte_flow_item_ipv6 ipv6_mask;
574 struct field_modify_info *field;
577 flow_dv_attr_init(items, attr);
579 memset(&ipv4, 0, sizeof(ipv4));
580 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
581 ipv4.hdr.time_to_live = 0xFF;
582 ipv4_mask.hdr.time_to_live = 0xFF;
583 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
585 item.mask = &ipv4_mask;
589 memset(&ipv6, 0, sizeof(ipv6));
590 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
591 ipv6.hdr.hop_limits = 0xFF;
592 ipv6_mask.hdr.hop_limits = 0xFF;
593 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
595 item.mask = &ipv6_mask;
598 return flow_dv_convert_modify_action(&item, field, resource,
599 MLX5_MODIFICATION_TYPE_ADD, error);
603 * Convert modify-header increment/decrement TCP Sequence number
604 * to DV specification.
606 * @param[in,out] resource
607 * Pointer to the modify-header resource.
609 * Pointer to action specification.
611 * Pointer to the error structure.
614 * 0 on success, a negative errno value otherwise and rte_errno is set.
617 flow_dv_convert_action_modify_tcp_seq
618 (struct mlx5_flow_dv_modify_hdr_resource *resource,
619 const struct rte_flow_action *action,
620 struct rte_flow_error *error)
622 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
623 uint64_t value = rte_be_to_cpu_32(*conf);
624 struct rte_flow_item item;
625 struct rte_flow_item_tcp tcp;
626 struct rte_flow_item_tcp tcp_mask;
628 memset(&tcp, 0, sizeof(tcp));
629 memset(&tcp_mask, 0, sizeof(tcp_mask));
630 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
632 * The HW has no decrement operation, only increment operation.
633 * To simulate decrement X from Y using increment operation
634 * we need to add UINT32_MAX X times to Y.
635 * Each adding of UINT32_MAX decrements Y by 1.
638 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
639 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
640 item.type = RTE_FLOW_ITEM_TYPE_TCP;
642 item.mask = &tcp_mask;
643 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
644 MLX5_MODIFICATION_TYPE_ADD, error);
648 * Convert modify-header increment/decrement TCP Acknowledgment number
649 * to DV specification.
651 * @param[in,out] resource
652 * Pointer to the modify-header resource.
654 * Pointer to action specification.
656 * Pointer to the error structure.
659 * 0 on success, a negative errno value otherwise and rte_errno is set.
662 flow_dv_convert_action_modify_tcp_ack
663 (struct mlx5_flow_dv_modify_hdr_resource *resource,
664 const struct rte_flow_action *action,
665 struct rte_flow_error *error)
667 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
668 uint64_t value = rte_be_to_cpu_32(*conf);
669 struct rte_flow_item item;
670 struct rte_flow_item_tcp tcp;
671 struct rte_flow_item_tcp tcp_mask;
673 memset(&tcp, 0, sizeof(tcp));
674 memset(&tcp_mask, 0, sizeof(tcp_mask));
675 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
677 * The HW has no decrement operation, only increment operation.
678 * To simulate decrement X from Y using increment operation
679 * we need to add UINT32_MAX X times to Y.
680 * Each adding of UINT32_MAX decrements Y by 1.
683 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
684 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
685 item.type = RTE_FLOW_ITEM_TYPE_TCP;
687 item.mask = &tcp_mask;
688 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
689 MLX5_MODIFICATION_TYPE_ADD, error);
693 * Validate META item.
696 * Pointer to the rte_eth_dev structure.
698 * Item specification.
700 * Attributes of flow that includes this item.
702 * Pointer to error structure.
705 * 0 on success, a negative errno value otherwise and rte_errno is set.
708 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
709 const struct rte_flow_item *item,
710 const struct rte_flow_attr *attr,
711 struct rte_flow_error *error)
713 const struct rte_flow_item_meta *spec = item->spec;
714 const struct rte_flow_item_meta *mask = item->mask;
715 const struct rte_flow_item_meta nic_mask = {
716 .data = RTE_BE32(UINT32_MAX)
719 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
721 if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
722 return rte_flow_error_set(error, EPERM,
723 RTE_FLOW_ERROR_TYPE_ITEM,
725 "match on metadata offload "
726 "configuration is off for this port");
728 return rte_flow_error_set(error, EINVAL,
729 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
731 "data cannot be empty");
733 return rte_flow_error_set(error, EINVAL,
734 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
736 "data cannot be zero");
738 mask = &rte_flow_item_meta_mask;
739 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
740 (const uint8_t *)&nic_mask,
741 sizeof(struct rte_flow_item_meta),
746 return rte_flow_error_set(error, ENOTSUP,
747 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
749 "pattern not supported for ingress");
754 * Validate vport item.
757 * Pointer to the rte_eth_dev structure.
759 * Item specification.
761 * Attributes of flow that includes this item.
762 * @param[in] item_flags
763 * Bit-fields that holds the items detected until now.
765 * Pointer to error structure.
768 * 0 on success, a negative errno value otherwise and rte_errno is set.
771 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
772 const struct rte_flow_item *item,
773 const struct rte_flow_attr *attr,
775 struct rte_flow_error *error)
777 const struct rte_flow_item_port_id *spec = item->spec;
778 const struct rte_flow_item_port_id *mask = item->mask;
779 const struct rte_flow_item_port_id switch_mask = {
782 uint16_t esw_domain_id;
783 uint16_t item_port_esw_domain_id;
787 return rte_flow_error_set(error, EINVAL,
788 RTE_FLOW_ERROR_TYPE_ITEM,
790 "match on port id is valid only"
791 " when transfer flag is enabled");
792 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
793 return rte_flow_error_set(error, ENOTSUP,
794 RTE_FLOW_ERROR_TYPE_ITEM, item,
795 "multiple source ports are not"
799 if (mask->id != 0xffffffff)
800 return rte_flow_error_set(error, ENOTSUP,
801 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
803 "no support for partial mask on"
805 ret = mlx5_flow_item_acceptable
806 (item, (const uint8_t *)mask,
807 (const uint8_t *)&rte_flow_item_port_id_mask,
808 sizeof(struct rte_flow_item_port_id),
814 ret = mlx5_port_to_eswitch_info(spec->id, &item_port_esw_domain_id,
817 return rte_flow_error_set(error, -ret,
818 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
819 "failed to obtain E-Switch info for"
821 ret = mlx5_port_to_eswitch_info(dev->data->port_id,
822 &esw_domain_id, NULL);
824 return rte_flow_error_set(error, -ret,
825 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
827 "failed to obtain E-Switch info");
828 if (item_port_esw_domain_id != esw_domain_id)
829 return rte_flow_error_set(error, -ret,
830 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
831 "cannot match on a port from a"
832 " different E-Switch");
837 * Validate count action.
842 * Pointer to error structure.
845 * 0 on success, a negative errno value otherwise and rte_errno is set.
848 flow_dv_validate_action_count(struct rte_eth_dev *dev,
849 struct rte_flow_error *error)
851 struct mlx5_priv *priv = dev->data->dev_private;
853 if (!priv->config.devx)
855 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
859 return rte_flow_error_set
861 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
863 "count action not supported");
867 * Validate the L2 encap action.
869 * @param[in] action_flags
870 * Holds the actions detected until now.
872 * Pointer to the encap action.
874 * Pointer to flow attributes
876 * Pointer to error structure.
879 * 0 on success, a negative errno value otherwise and rte_errno is set.
882 flow_dv_validate_action_l2_encap(uint64_t action_flags,
883 const struct rte_flow_action *action,
884 const struct rte_flow_attr *attr,
885 struct rte_flow_error *error)
888 return rte_flow_error_set(error, EINVAL,
889 RTE_FLOW_ERROR_TYPE_ACTION, action,
890 "configuration cannot be null");
891 if (action_flags & MLX5_FLOW_ACTION_DROP)
892 return rte_flow_error_set(error, EINVAL,
893 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
894 "can't drop and encap in same flow");
895 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
896 return rte_flow_error_set(error, EINVAL,
897 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
898 "can only have a single encap or"
899 " decap action in a flow");
900 if (!attr->transfer && attr->ingress)
901 return rte_flow_error_set(error, ENOTSUP,
902 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
904 "encap action not supported for "
910 * Validate the L2 decap action.
912 * @param[in] action_flags
913 * Holds the actions detected until now.
915 * Pointer to flow attributes
917 * Pointer to error structure.
920 * 0 on success, a negative errno value otherwise and rte_errno is set.
923 flow_dv_validate_action_l2_decap(uint64_t action_flags,
924 const struct rte_flow_attr *attr,
925 struct rte_flow_error *error)
927 if (action_flags & MLX5_FLOW_ACTION_DROP)
928 return rte_flow_error_set(error, EINVAL,
929 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
930 "can't drop and decap in same flow");
931 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
932 return rte_flow_error_set(error, EINVAL,
933 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
934 "can only have a single encap or"
935 " decap action in a flow");
936 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
937 return rte_flow_error_set(error, EINVAL,
938 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
939 "can't have decap action after"
942 return rte_flow_error_set(error, ENOTSUP,
943 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
945 "decap action not supported for "
951 * Validate the raw encap action.
953 * @param[in] action_flags
954 * Holds the actions detected until now.
956 * Pointer to the encap action.
958 * Pointer to flow attributes
960 * Pointer to error structure.
963 * 0 on success, a negative errno value otherwise and rte_errno is set.
966 flow_dv_validate_action_raw_encap(uint64_t action_flags,
967 const struct rte_flow_action *action,
968 const struct rte_flow_attr *attr,
969 struct rte_flow_error *error)
972 return rte_flow_error_set(error, EINVAL,
973 RTE_FLOW_ERROR_TYPE_ACTION, action,
974 "configuration cannot be null");
975 if (action_flags & MLX5_FLOW_ACTION_DROP)
976 return rte_flow_error_set(error, EINVAL,
977 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
978 "can't drop and encap in same flow");
979 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
980 return rte_flow_error_set(error, EINVAL,
981 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
982 "can only have a single encap"
983 " action in a flow");
984 /* encap without preceding decap is not supported for ingress */
985 if (!attr->transfer && attr->ingress &&
986 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
987 return rte_flow_error_set(error, ENOTSUP,
988 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
990 "encap action not supported for "
996 * Validate the raw decap action.
998 * @param[in] action_flags
999 * Holds the actions detected until now.
1001 * Pointer to the encap action.
1003 * Pointer to flow attributes
1005 * Pointer to error structure.
1008 * 0 on success, a negative errno value otherwise and rte_errno is set.
1011 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1012 const struct rte_flow_action *action,
1013 const struct rte_flow_attr *attr,
1014 struct rte_flow_error *error)
1016 if (action_flags & MLX5_FLOW_ACTION_DROP)
1017 return rte_flow_error_set(error, EINVAL,
1018 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1019 "can't drop and decap in same flow");
1020 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1021 return rte_flow_error_set(error, EINVAL,
1022 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1023 "can't have encap action before"
1025 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1026 return rte_flow_error_set(error, EINVAL,
1027 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1028 "can only have a single decap"
1029 " action in a flow");
1030 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1031 return rte_flow_error_set(error, EINVAL,
1032 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1033 "can't have decap action after"
1035 /* decap action is valid on egress only if it is followed by encap */
1037 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1038 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1041 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1042 return rte_flow_error_set
1044 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1045 NULL, "decap action not supported"
1052 * Find existing encap/decap resource or create and register a new one.
1054 * @param dev[in, out]
1055 * Pointer to rte_eth_dev structure.
1056 * @param[in, out] resource
1057 * Pointer to encap/decap resource.
1058 * @parm[in, out] dev_flow
1059 * Pointer to the dev_flow.
1061 * pointer to error structure.
1064 * 0 on success otherwise -errno and errno is set.
1067 flow_dv_encap_decap_resource_register
1068 (struct rte_eth_dev *dev,
1069 struct mlx5_flow_dv_encap_decap_resource *resource,
1070 struct mlx5_flow *dev_flow,
1071 struct rte_flow_error *error)
1073 struct mlx5_priv *priv = dev->data->dev_private;
1074 struct mlx5_ibv_shared *sh = priv->sh;
1075 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1076 struct rte_flow *flow = dev_flow->flow;
1077 struct mlx5dv_dr_domain *domain;
1079 resource->flags = flow->group ? 0 : 1;
1080 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1081 domain = sh->fdb_domain;
1082 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1083 domain = sh->rx_domain;
1085 domain = sh->tx_domain;
1087 /* Lookup a matching resource from cache. */
1088 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1089 if (resource->reformat_type == cache_resource->reformat_type &&
1090 resource->ft_type == cache_resource->ft_type &&
1091 resource->flags == cache_resource->flags &&
1092 resource->size == cache_resource->size &&
1093 !memcmp((const void *)resource->buf,
1094 (const void *)cache_resource->buf,
1096 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1097 (void *)cache_resource,
1098 rte_atomic32_read(&cache_resource->refcnt));
1099 rte_atomic32_inc(&cache_resource->refcnt);
1100 dev_flow->dv.encap_decap = cache_resource;
1104 /* Register new encap/decap resource. */
1105 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1106 if (!cache_resource)
1107 return rte_flow_error_set(error, ENOMEM,
1108 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1109 "cannot allocate resource memory");
1110 *cache_resource = *resource;
1111 cache_resource->verbs_action =
1112 mlx5_glue->dv_create_flow_action_packet_reformat
1113 (sh->ctx, cache_resource->reformat_type,
1114 cache_resource->ft_type, domain, cache_resource->flags,
1115 cache_resource->size,
1116 (cache_resource->size ? cache_resource->buf : NULL));
1117 if (!cache_resource->verbs_action) {
1118 rte_free(cache_resource);
1119 return rte_flow_error_set(error, ENOMEM,
1120 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1121 NULL, "cannot create action");
1123 rte_atomic32_init(&cache_resource->refcnt);
1124 rte_atomic32_inc(&cache_resource->refcnt);
1125 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1126 dev_flow->dv.encap_decap = cache_resource;
1127 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1128 (void *)cache_resource,
1129 rte_atomic32_read(&cache_resource->refcnt));
1134 * Find existing table jump resource or create and register a new one.
1136 * @param dev[in, out]
1137 * Pointer to rte_eth_dev structure.
1138 * @param[in, out] resource
1139 * Pointer to jump table resource.
1140 * @parm[in, out] dev_flow
1141 * Pointer to the dev_flow.
1143 * pointer to error structure.
1146 * 0 on success otherwise -errno and errno is set.
1149 flow_dv_jump_tbl_resource_register
1150 (struct rte_eth_dev *dev,
1151 struct mlx5_flow_dv_jump_tbl_resource *resource,
1152 struct mlx5_flow *dev_flow,
1153 struct rte_flow_error *error)
1155 struct mlx5_priv *priv = dev->data->dev_private;
1156 struct mlx5_ibv_shared *sh = priv->sh;
1157 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1159 /* Lookup a matching resource from cache. */
1160 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1161 if (resource->tbl == cache_resource->tbl) {
1162 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1163 (void *)cache_resource,
1164 rte_atomic32_read(&cache_resource->refcnt));
1165 rte_atomic32_inc(&cache_resource->refcnt);
1166 dev_flow->dv.jump = cache_resource;
1170 /* Register new jump table resource. */
1171 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1172 if (!cache_resource)
1173 return rte_flow_error_set(error, ENOMEM,
1174 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1175 "cannot allocate resource memory");
1176 *cache_resource = *resource;
1177 cache_resource->action =
1178 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1179 (resource->tbl->obj);
1180 if (!cache_resource->action) {
1181 rte_free(cache_resource);
1182 return rte_flow_error_set(error, ENOMEM,
1183 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1184 NULL, "cannot create action");
1186 rte_atomic32_init(&cache_resource->refcnt);
1187 rte_atomic32_inc(&cache_resource->refcnt);
1188 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1189 dev_flow->dv.jump = cache_resource;
1190 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1191 (void *)cache_resource,
1192 rte_atomic32_read(&cache_resource->refcnt));
1197 * Find existing table port ID resource or create and register a new one.
1199 * @param dev[in, out]
1200 * Pointer to rte_eth_dev structure.
1201 * @param[in, out] resource
1202 * Pointer to port ID action resource.
1203 * @parm[in, out] dev_flow
1204 * Pointer to the dev_flow.
1206 * pointer to error structure.
1209 * 0 on success otherwise -errno and errno is set.
1212 flow_dv_port_id_action_resource_register
1213 (struct rte_eth_dev *dev,
1214 struct mlx5_flow_dv_port_id_action_resource *resource,
1215 struct mlx5_flow *dev_flow,
1216 struct rte_flow_error *error)
1218 struct mlx5_priv *priv = dev->data->dev_private;
1219 struct mlx5_ibv_shared *sh = priv->sh;
1220 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1222 /* Lookup a matching resource from cache. */
1223 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1224 if (resource->port_id == cache_resource->port_id) {
1225 DRV_LOG(DEBUG, "port id action resource resource %p: "
1227 (void *)cache_resource,
1228 rte_atomic32_read(&cache_resource->refcnt));
1229 rte_atomic32_inc(&cache_resource->refcnt);
1230 dev_flow->dv.port_id_action = cache_resource;
1234 /* Register new port id action resource. */
1235 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1236 if (!cache_resource)
1237 return rte_flow_error_set(error, ENOMEM,
1238 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1239 "cannot allocate resource memory");
1240 *cache_resource = *resource;
1241 cache_resource->action =
1242 mlx5_glue->dr_create_flow_action_dest_vport
1243 (priv->sh->fdb_domain, resource->port_id);
1244 if (!cache_resource->action) {
1245 rte_free(cache_resource);
1246 return rte_flow_error_set(error, ENOMEM,
1247 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1248 NULL, "cannot create action");
1250 rte_atomic32_init(&cache_resource->refcnt);
1251 rte_atomic32_inc(&cache_resource->refcnt);
1252 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1253 dev_flow->dv.port_id_action = cache_resource;
1254 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1255 (void *)cache_resource,
1256 rte_atomic32_read(&cache_resource->refcnt));
1261 * Get the size of specific rte_flow_item_type
1263 * @param[in] item_type
1264 * Tested rte_flow_item_type.
1267 * sizeof struct item_type, 0 if void or irrelevant.
1270 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1274 switch (item_type) {
1275 case RTE_FLOW_ITEM_TYPE_ETH:
1276 retval = sizeof(struct rte_flow_item_eth);
1278 case RTE_FLOW_ITEM_TYPE_VLAN:
1279 retval = sizeof(struct rte_flow_item_vlan);
1281 case RTE_FLOW_ITEM_TYPE_IPV4:
1282 retval = sizeof(struct rte_flow_item_ipv4);
1284 case RTE_FLOW_ITEM_TYPE_IPV6:
1285 retval = sizeof(struct rte_flow_item_ipv6);
1287 case RTE_FLOW_ITEM_TYPE_UDP:
1288 retval = sizeof(struct rte_flow_item_udp);
1290 case RTE_FLOW_ITEM_TYPE_TCP:
1291 retval = sizeof(struct rte_flow_item_tcp);
1293 case RTE_FLOW_ITEM_TYPE_VXLAN:
1294 retval = sizeof(struct rte_flow_item_vxlan);
1296 case RTE_FLOW_ITEM_TYPE_GRE:
1297 retval = sizeof(struct rte_flow_item_gre);
1299 case RTE_FLOW_ITEM_TYPE_NVGRE:
1300 retval = sizeof(struct rte_flow_item_nvgre);
1302 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1303 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1305 case RTE_FLOW_ITEM_TYPE_MPLS:
1306 retval = sizeof(struct rte_flow_item_mpls);
1308 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1316 #define MLX5_ENCAP_IPV4_VERSION 0x40
1317 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1318 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1319 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1320 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1321 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1322 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1325 * Convert the encap action data from list of rte_flow_item to raw buffer
1328 * Pointer to rte_flow_item objects list.
1330 * Pointer to the output buffer.
1332 * Pointer to the output buffer size.
1334 * Pointer to the error structure.
1337 * 0 on success, a negative errno value otherwise and rte_errno is set.
1340 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1341 size_t *size, struct rte_flow_error *error)
1343 struct rte_ether_hdr *eth = NULL;
1344 struct rte_vlan_hdr *vlan = NULL;
1345 struct rte_ipv4_hdr *ipv4 = NULL;
1346 struct rte_ipv6_hdr *ipv6 = NULL;
1347 struct rte_udp_hdr *udp = NULL;
1348 struct rte_vxlan_hdr *vxlan = NULL;
1349 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1350 struct rte_gre_hdr *gre = NULL;
1352 size_t temp_size = 0;
1355 return rte_flow_error_set(error, EINVAL,
1356 RTE_FLOW_ERROR_TYPE_ACTION,
1357 NULL, "invalid empty data");
1358 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1359 len = flow_dv_get_item_len(items->type);
1360 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1361 return rte_flow_error_set(error, EINVAL,
1362 RTE_FLOW_ERROR_TYPE_ACTION,
1363 (void *)items->type,
1364 "items total size is too big"
1365 " for encap action");
1366 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1367 switch (items->type) {
1368 case RTE_FLOW_ITEM_TYPE_ETH:
1369 eth = (struct rte_ether_hdr *)&buf[temp_size];
1371 case RTE_FLOW_ITEM_TYPE_VLAN:
1372 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1374 return rte_flow_error_set(error, EINVAL,
1375 RTE_FLOW_ERROR_TYPE_ACTION,
1376 (void *)items->type,
1377 "eth header not found");
1378 if (!eth->ether_type)
1379 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1381 case RTE_FLOW_ITEM_TYPE_IPV4:
1382 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1384 return rte_flow_error_set(error, EINVAL,
1385 RTE_FLOW_ERROR_TYPE_ACTION,
1386 (void *)items->type,
1387 "neither eth nor vlan"
1389 if (vlan && !vlan->eth_proto)
1390 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1391 else if (eth && !eth->ether_type)
1392 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1393 if (!ipv4->version_ihl)
1394 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1395 MLX5_ENCAP_IPV4_IHL_MIN;
1396 if (!ipv4->time_to_live)
1397 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1399 case RTE_FLOW_ITEM_TYPE_IPV6:
1400 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1402 return rte_flow_error_set(error, EINVAL,
1403 RTE_FLOW_ERROR_TYPE_ACTION,
1404 (void *)items->type,
1405 "neither eth nor vlan"
1407 if (vlan && !vlan->eth_proto)
1408 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1409 else if (eth && !eth->ether_type)
1410 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1411 if (!ipv6->vtc_flow)
1413 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1414 if (!ipv6->hop_limits)
1415 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1417 case RTE_FLOW_ITEM_TYPE_UDP:
1418 udp = (struct rte_udp_hdr *)&buf[temp_size];
1420 return rte_flow_error_set(error, EINVAL,
1421 RTE_FLOW_ERROR_TYPE_ACTION,
1422 (void *)items->type,
1423 "ip header not found");
1424 if (ipv4 && !ipv4->next_proto_id)
1425 ipv4->next_proto_id = IPPROTO_UDP;
1426 else if (ipv6 && !ipv6->proto)
1427 ipv6->proto = IPPROTO_UDP;
1429 case RTE_FLOW_ITEM_TYPE_VXLAN:
1430 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1432 return rte_flow_error_set(error, EINVAL,
1433 RTE_FLOW_ERROR_TYPE_ACTION,
1434 (void *)items->type,
1435 "udp header not found");
1437 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1438 if (!vxlan->vx_flags)
1440 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1442 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1443 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1445 return rte_flow_error_set(error, EINVAL,
1446 RTE_FLOW_ERROR_TYPE_ACTION,
1447 (void *)items->type,
1448 "udp header not found");
1449 if (!vxlan_gpe->proto)
1450 return rte_flow_error_set(error, EINVAL,
1451 RTE_FLOW_ERROR_TYPE_ACTION,
1452 (void *)items->type,
1453 "next protocol not found");
1456 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1457 if (!vxlan_gpe->vx_flags)
1458 vxlan_gpe->vx_flags =
1459 MLX5_ENCAP_VXLAN_GPE_FLAGS;
1461 case RTE_FLOW_ITEM_TYPE_GRE:
1462 case RTE_FLOW_ITEM_TYPE_NVGRE:
1463 gre = (struct rte_gre_hdr *)&buf[temp_size];
1465 return rte_flow_error_set(error, EINVAL,
1466 RTE_FLOW_ERROR_TYPE_ACTION,
1467 (void *)items->type,
1468 "next protocol not found");
1470 return rte_flow_error_set(error, EINVAL,
1471 RTE_FLOW_ERROR_TYPE_ACTION,
1472 (void *)items->type,
1473 "ip header not found");
1474 if (ipv4 && !ipv4->next_proto_id)
1475 ipv4->next_proto_id = IPPROTO_GRE;
1476 else if (ipv6 && !ipv6->proto)
1477 ipv6->proto = IPPROTO_GRE;
1479 case RTE_FLOW_ITEM_TYPE_VOID:
1482 return rte_flow_error_set(error, EINVAL,
1483 RTE_FLOW_ERROR_TYPE_ACTION,
1484 (void *)items->type,
1485 "unsupported item type");
1495 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
1497 struct rte_ether_hdr *eth = NULL;
1498 struct rte_vlan_hdr *vlan = NULL;
1499 struct rte_ipv6_hdr *ipv6 = NULL;
1500 struct rte_udp_hdr *udp = NULL;
1504 eth = (struct rte_ether_hdr *)data;
1505 next_hdr = (char *)(eth + 1);
1506 proto = RTE_BE16(eth->ether_type);
1509 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
1510 next_hdr += sizeof(struct rte_vlan_hdr);
1511 vlan = (struct rte_vlan_hdr *)next_hdr;
1512 proto = RTE_BE16(vlan->eth_proto);
1515 /* HW calculates IPv4 csum. no need to proceed */
1516 if (proto == RTE_ETHER_TYPE_IPV4)
1519 /* non IPv4/IPv6 header. not supported */
1520 if (proto != RTE_ETHER_TYPE_IPV6) {
1521 return rte_flow_error_set(error, ENOTSUP,
1522 RTE_FLOW_ERROR_TYPE_ACTION,
1523 NULL, "Cannot offload non IPv4/IPv6");
1526 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
1528 /* ignore non UDP */
1529 if (ipv6->proto != IPPROTO_UDP)
1532 udp = (struct rte_udp_hdr *)(ipv6 + 1);
1533 udp->dgram_cksum = 0;
1539 * Convert L2 encap action to DV specification.
1542 * Pointer to rte_eth_dev structure.
1544 * Pointer to action structure.
1545 * @param[in, out] dev_flow
1546 * Pointer to the mlx5_flow.
1547 * @param[in] transfer
1548 * Mark if the flow is E-Switch flow.
1550 * Pointer to the error structure.
1553 * 0 on success, a negative errno value otherwise and rte_errno is set.
1556 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
1557 const struct rte_flow_action *action,
1558 struct mlx5_flow *dev_flow,
1560 struct rte_flow_error *error)
1562 const struct rte_flow_item *encap_data;
1563 const struct rte_flow_action_raw_encap *raw_encap_data;
1564 struct mlx5_flow_dv_encap_decap_resource res = {
1566 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
1567 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1568 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
1571 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1573 (const struct rte_flow_action_raw_encap *)action->conf;
1574 res.size = raw_encap_data->size;
1575 memcpy(res.buf, raw_encap_data->data, res.size);
1576 if (flow_dv_zero_encap_udp_csum(res.buf, error))
1579 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
1581 ((const struct rte_flow_action_vxlan_encap *)
1582 action->conf)->definition;
1585 ((const struct rte_flow_action_nvgre_encap *)
1586 action->conf)->definition;
1587 if (flow_dv_convert_encap_data(encap_data, res.buf,
1591 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1592 return rte_flow_error_set(error, EINVAL,
1593 RTE_FLOW_ERROR_TYPE_ACTION,
1594 NULL, "can't create L2 encap action");
1599 * Convert L2 decap action to DV specification.
1602 * Pointer to rte_eth_dev structure.
1603 * @param[in, out] dev_flow
1604 * Pointer to the mlx5_flow.
1605 * @param[in] transfer
1606 * Mark if the flow is E-Switch flow.
1608 * Pointer to the error structure.
1611 * 0 on success, a negative errno value otherwise and rte_errno is set.
1614 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
1615 struct mlx5_flow *dev_flow,
1617 struct rte_flow_error *error)
1619 struct mlx5_flow_dv_encap_decap_resource res = {
1622 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
1623 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1624 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
1627 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1628 return rte_flow_error_set(error, EINVAL,
1629 RTE_FLOW_ERROR_TYPE_ACTION,
1630 NULL, "can't create L2 decap action");
1635 * Convert raw decap/encap (L3 tunnel) action to DV specification.
1638 * Pointer to rte_eth_dev structure.
1640 * Pointer to action structure.
1641 * @param[in, out] dev_flow
1642 * Pointer to the mlx5_flow.
1644 * Pointer to the flow attributes.
1646 * Pointer to the error structure.
1649 * 0 on success, a negative errno value otherwise and rte_errno is set.
1652 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
1653 const struct rte_flow_action *action,
1654 struct mlx5_flow *dev_flow,
1655 const struct rte_flow_attr *attr,
1656 struct rte_flow_error *error)
1658 const struct rte_flow_action_raw_encap *encap_data;
1659 struct mlx5_flow_dv_encap_decap_resource res;
1661 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
1662 res.size = encap_data->size;
1663 memcpy(res.buf, encap_data->data, res.size);
1664 res.reformat_type = attr->egress ?
1665 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
1666 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
1668 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
1670 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
1671 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
1672 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1673 return rte_flow_error_set(error, EINVAL,
1674 RTE_FLOW_ERROR_TYPE_ACTION,
1675 NULL, "can't create encap action");
1680 * Validate the modify-header actions.
1682 * @param[in] action_flags
1683 * Holds the actions detected until now.
1685 * Pointer to the modify action.
1687 * Pointer to error structure.
1690 * 0 on success, a negative errno value otherwise and rte_errno is set.
1693 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
1694 const struct rte_flow_action *action,
1695 struct rte_flow_error *error)
1697 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
1698 return rte_flow_error_set(error, EINVAL,
1699 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1700 NULL, "action configuration not set");
1701 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1702 return rte_flow_error_set(error, EINVAL,
1703 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1704 "can't have encap action before"
1710 * Validate the modify-header MAC address actions.
1712 * @param[in] action_flags
1713 * Holds the actions detected until now.
1715 * Pointer to the modify action.
1716 * @param[in] item_flags
1717 * Holds the items detected.
1719 * Pointer to error structure.
1722 * 0 on success, a negative errno value otherwise and rte_errno is set.
1725 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
1726 const struct rte_flow_action *action,
1727 const uint64_t item_flags,
1728 struct rte_flow_error *error)
1732 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1734 if (!(item_flags & MLX5_FLOW_LAYER_L2))
1735 return rte_flow_error_set(error, EINVAL,
1736 RTE_FLOW_ERROR_TYPE_ACTION,
1738 "no L2 item in pattern");
1744 * Validate the modify-header IPv4 address actions.
1746 * @param[in] action_flags
1747 * Holds the actions detected until now.
1749 * Pointer to the modify action.
1750 * @param[in] item_flags
1751 * Holds the items detected.
1753 * Pointer to error structure.
1756 * 0 on success, a negative errno value otherwise and rte_errno is set.
1759 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
1760 const struct rte_flow_action *action,
1761 const uint64_t item_flags,
1762 struct rte_flow_error *error)
1766 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1768 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
1769 return rte_flow_error_set(error, EINVAL,
1770 RTE_FLOW_ERROR_TYPE_ACTION,
1772 "no ipv4 item in pattern");
1778 * Validate the modify-header IPv6 address actions.
1780 * @param[in] action_flags
1781 * Holds the actions detected until now.
1783 * Pointer to the modify action.
1784 * @param[in] item_flags
1785 * Holds the items detected.
1787 * Pointer to error structure.
1790 * 0 on success, a negative errno value otherwise and rte_errno is set.
1793 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
1794 const struct rte_flow_action *action,
1795 const uint64_t item_flags,
1796 struct rte_flow_error *error)
1800 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1802 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
1803 return rte_flow_error_set(error, EINVAL,
1804 RTE_FLOW_ERROR_TYPE_ACTION,
1806 "no ipv6 item in pattern");
1812 * Validate the modify-header TP actions.
1814 * @param[in] action_flags
1815 * Holds the actions detected until now.
1817 * Pointer to the modify action.
1818 * @param[in] item_flags
1819 * Holds the items detected.
1821 * Pointer to error structure.
1824 * 0 on success, a negative errno value otherwise and rte_errno is set.
1827 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
1828 const struct rte_flow_action *action,
1829 const uint64_t item_flags,
1830 struct rte_flow_error *error)
1834 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1836 if (!(item_flags & MLX5_FLOW_LAYER_L4))
1837 return rte_flow_error_set(error, EINVAL,
1838 RTE_FLOW_ERROR_TYPE_ACTION,
1839 NULL, "no transport layer "
1846 * Validate the modify-header actions of increment/decrement
1847 * TCP Sequence-number.
1849 * @param[in] action_flags
1850 * Holds the actions detected until now.
1852 * Pointer to the modify action.
1853 * @param[in] item_flags
1854 * Holds the items detected.
1856 * Pointer to error structure.
1859 * 0 on success, a negative errno value otherwise and rte_errno is set.
1862 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
1863 const struct rte_flow_action *action,
1864 const uint64_t item_flags,
1865 struct rte_flow_error *error)
1869 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1871 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
1872 return rte_flow_error_set(error, EINVAL,
1873 RTE_FLOW_ERROR_TYPE_ACTION,
1874 NULL, "no TCP item in"
1876 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
1877 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
1878 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
1879 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
1880 return rte_flow_error_set(error, EINVAL,
1881 RTE_FLOW_ERROR_TYPE_ACTION,
1883 "cannot decrease and increase"
1884 " TCP sequence number"
1885 " at the same time");
1891 * Validate the modify-header actions of increment/decrement
1892 * TCP Acknowledgment number.
1894 * @param[in] action_flags
1895 * Holds the actions detected until now.
1897 * Pointer to the modify action.
1898 * @param[in] item_flags
1899 * Holds the items detected.
1901 * Pointer to error structure.
1904 * 0 on success, a negative errno value otherwise and rte_errno is set.
1907 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
1908 const struct rte_flow_action *action,
1909 const uint64_t item_flags,
1910 struct rte_flow_error *error)
1914 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1916 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
1917 return rte_flow_error_set(error, EINVAL,
1918 RTE_FLOW_ERROR_TYPE_ACTION,
1919 NULL, "no TCP item in"
1921 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
1922 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
1923 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
1924 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
1925 return rte_flow_error_set(error, EINVAL,
1926 RTE_FLOW_ERROR_TYPE_ACTION,
1928 "cannot decrease and increase"
1929 " TCP acknowledgment number"
1930 " at the same time");
1936 * Validate the modify-header TTL actions.
1938 * @param[in] action_flags
1939 * Holds the actions detected until now.
1941 * Pointer to the modify action.
1942 * @param[in] item_flags
1943 * Holds the items detected.
1945 * Pointer to error structure.
1948 * 0 on success, a negative errno value otherwise and rte_errno is set.
1951 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
1952 const struct rte_flow_action *action,
1953 const uint64_t item_flags,
1954 struct rte_flow_error *error)
1958 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
1960 if (!(item_flags & MLX5_FLOW_LAYER_L3))
1961 return rte_flow_error_set(error, EINVAL,
1962 RTE_FLOW_ERROR_TYPE_ACTION,
1964 "no IP protocol in pattern");
1970 * Validate jump action.
1973 * Pointer to the modify action.
1975 * The group of the current flow.
1977 * Pointer to error structure.
1980 * 0 on success, a negative errno value otherwise and rte_errno is set.
1983 flow_dv_validate_action_jump(const struct rte_flow_action *action,
1985 struct rte_flow_error *error)
1987 if (action->type != RTE_FLOW_ACTION_TYPE_JUMP && !action->conf)
1988 return rte_flow_error_set(error, EINVAL,
1989 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1990 NULL, "action configuration not set");
1991 if (group >= ((const struct rte_flow_action_jump *)action->conf)->group)
1992 return rte_flow_error_set(error, EINVAL,
1993 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1994 "target group must be higher then"
1995 " the current flow group");
2000 * Validate the port_id action.
2003 * Pointer to rte_eth_dev structure.
2004 * @param[in] action_flags
2005 * Bit-fields that holds the actions detected until now.
2007 * Port_id RTE action structure.
2009 * Attributes of flow that includes this action.
2011 * Pointer to error structure.
2014 * 0 on success, a negative errno value otherwise and rte_errno is set.
2017 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2018 uint64_t action_flags,
2019 const struct rte_flow_action *action,
2020 const struct rte_flow_attr *attr,
2021 struct rte_flow_error *error)
2023 const struct rte_flow_action_port_id *port_id;
2025 uint16_t esw_domain_id;
2026 uint16_t act_port_domain_id;
2029 if (!attr->transfer)
2030 return rte_flow_error_set(error, ENOTSUP,
2031 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2033 "port id action is valid in transfer"
2035 if (!action || !action->conf)
2036 return rte_flow_error_set(error, ENOTSUP,
2037 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2039 "port id action parameters must be"
2041 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2042 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2043 return rte_flow_error_set(error, EINVAL,
2044 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2045 "can have only one fate actions in"
2047 ret = mlx5_port_to_eswitch_info(dev->data->port_id,
2048 &esw_domain_id, NULL);
2050 return rte_flow_error_set(error, -ret,
2051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2053 "failed to obtain E-Switch info");
2054 port_id = action->conf;
2055 port = port_id->original ? dev->data->port_id : port_id->id;
2056 ret = mlx5_port_to_eswitch_info(port, &act_port_domain_id, NULL);
2058 return rte_flow_error_set
2060 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2061 "failed to obtain E-Switch port id for port");
2062 if (act_port_domain_id != esw_domain_id)
2063 return rte_flow_error_set
2065 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2066 "port does not belong to"
2067 " E-Switch being configured");
2072 * Find existing modify-header resource or create and register a new one.
2074 * @param dev[in, out]
2075 * Pointer to rte_eth_dev structure.
2076 * @param[in, out] resource
2077 * Pointer to modify-header resource.
2078 * @parm[in, out] dev_flow
2079 * Pointer to the dev_flow.
2081 * pointer to error structure.
2084 * 0 on success otherwise -errno and errno is set.
2087 flow_dv_modify_hdr_resource_register
2088 (struct rte_eth_dev *dev,
2089 struct mlx5_flow_dv_modify_hdr_resource *resource,
2090 struct mlx5_flow *dev_flow,
2091 struct rte_flow_error *error)
2093 struct mlx5_priv *priv = dev->data->dev_private;
2094 struct mlx5_ibv_shared *sh = priv->sh;
2095 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2096 struct mlx5dv_dr_domain *ns;
2098 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2099 ns = sh->fdb_domain;
2100 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2105 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2106 /* Lookup a matching resource from cache. */
2107 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2108 if (resource->ft_type == cache_resource->ft_type &&
2109 resource->actions_num == cache_resource->actions_num &&
2110 resource->flags == cache_resource->flags &&
2111 !memcmp((const void *)resource->actions,
2112 (const void *)cache_resource->actions,
2113 (resource->actions_num *
2114 sizeof(resource->actions[0])))) {
2115 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2116 (void *)cache_resource,
2117 rte_atomic32_read(&cache_resource->refcnt));
2118 rte_atomic32_inc(&cache_resource->refcnt);
2119 dev_flow->dv.modify_hdr = cache_resource;
2123 /* Register new modify-header resource. */
2124 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2125 if (!cache_resource)
2126 return rte_flow_error_set(error, ENOMEM,
2127 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2128 "cannot allocate resource memory");
2129 *cache_resource = *resource;
2130 cache_resource->verbs_action =
2131 mlx5_glue->dv_create_flow_action_modify_header
2132 (sh->ctx, cache_resource->ft_type,
2133 ns, cache_resource->flags,
2134 cache_resource->actions_num *
2135 sizeof(cache_resource->actions[0]),
2136 (uint64_t *)cache_resource->actions);
2137 if (!cache_resource->verbs_action) {
2138 rte_free(cache_resource);
2139 return rte_flow_error_set(error, ENOMEM,
2140 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2141 NULL, "cannot create action");
2143 rte_atomic32_init(&cache_resource->refcnt);
2144 rte_atomic32_inc(&cache_resource->refcnt);
2145 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2146 dev_flow->dv.modify_hdr = cache_resource;
2147 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2148 (void *)cache_resource,
2149 rte_atomic32_read(&cache_resource->refcnt));
2153 #define MLX5_CNT_CONTAINER_RESIZE 64
2156 * Get or create a flow counter.
2159 * Pointer to the Ethernet device structure.
2161 * Indicate if this counter is shared with other flows.
2163 * Counter identifier.
2166 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2168 static struct mlx5_flow_counter *
2169 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2172 struct mlx5_priv *priv = dev->data->dev_private;
2173 struct mlx5_flow_counter *cnt = NULL;
2174 struct mlx5_devx_obj *dcs = NULL;
2176 if (!priv->config.devx) {
2177 rte_errno = ENOTSUP;
2181 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2182 if (cnt->shared && cnt->id == id) {
2188 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2191 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2193 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2197 struct mlx5_flow_counter tmpl = {
2203 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2205 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2211 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2216 * Release a flow counter.
2219 * Pointer to the Ethernet device structure.
2220 * @param[in] counter
2221 * Pointer to the counter handler.
2224 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2225 struct mlx5_flow_counter *counter)
2227 struct mlx5_priv *priv = dev->data->dev_private;
2231 if (--counter->ref_cnt == 0) {
2232 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2233 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2239 * Query a devx flow counter.
2242 * Pointer to the Ethernet device structure.
2244 * Pointer to the flow counter.
2246 * The statistics value of packets.
2248 * The statistics value of bytes.
2251 * 0 on success, otherwise a negative errno value and rte_errno is set.
2254 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2255 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2258 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2263 * Get a pool by a counter.
2266 * Pointer to the counter.
2271 static struct mlx5_flow_counter_pool *
2272 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2275 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2276 return (struct mlx5_flow_counter_pool *)cnt - 1;
2282 * Get a pool by devx counter ID.
2285 * Pointer to the counter container.
2287 * The counter devx ID.
2290 * The counter pool pointer if exists, NULL otherwise,
2292 static struct mlx5_flow_counter_pool *
2293 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2295 struct mlx5_flow_counter_pool *pool;
2297 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2298 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2299 MLX5_COUNTERS_PER_POOL;
2301 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2308 * Allocate a new memory for the counter values wrapped by all the needed
2312 * Pointer to the Ethernet device structure.
2314 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2317 * The new memory management pointer on success, otherwise NULL and rte_errno
2320 static struct mlx5_counter_stats_mem_mng *
2321 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2323 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2324 (dev->data->dev_private))->sh;
2325 struct mlx5_devx_mkey_attr mkey_attr;
2326 struct mlx5_counter_stats_mem_mng *mem_mng;
2327 volatile struct flow_counter_stats *raw_data;
2328 int size = (sizeof(struct flow_counter_stats) *
2329 MLX5_COUNTERS_PER_POOL +
2330 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2331 sizeof(struct mlx5_counter_stats_mem_mng);
2332 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2339 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2340 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2341 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2342 IBV_ACCESS_LOCAL_WRITE);
2343 if (!mem_mng->umem) {
2348 mkey_attr.addr = (uintptr_t)mem;
2349 mkey_attr.size = size;
2350 mkey_attr.umem_id = mem_mng->umem->umem_id;
2351 mkey_attr.pd = sh->pdn;
2352 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2354 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2359 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2360 raw_data = (volatile struct flow_counter_stats *)mem;
2361 for (i = 0; i < raws_n; ++i) {
2362 mem_mng->raws[i].mem_mng = mem_mng;
2363 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2365 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2370 * Resize a counter container.
2373 * Pointer to the Ethernet device structure.
2375 * Whether the pool is for counter that was allocated by batch command.
2378 * The new container pointer on success, otherwise NULL and rte_errno is set.
2380 static struct mlx5_pools_container *
2381 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2383 struct mlx5_priv *priv = dev->data->dev_private;
2384 struct mlx5_pools_container *cont =
2385 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2386 struct mlx5_pools_container *new_cont =
2387 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2388 struct mlx5_counter_stats_mem_mng *mem_mng;
2389 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2390 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2393 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2394 /* The last resize still hasn't detected by the host thread. */
2398 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
2399 if (!new_cont->pools) {
2404 memcpy(new_cont->pools, cont->pools, cont->n *
2405 sizeof(struct mlx5_flow_counter_pool *));
2406 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
2407 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
2409 rte_free(new_cont->pools);
2412 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
2413 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
2414 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
2416 new_cont->n = resize;
2417 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
2418 TAILQ_INIT(&new_cont->pool_list);
2419 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
2420 new_cont->init_mem_mng = mem_mng;
2422 /* Flip the master container. */
2423 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
2428 * Query a devx flow counter.
2431 * Pointer to the Ethernet device structure.
2433 * Pointer to the flow counter.
2435 * The statistics value of packets.
2437 * The statistics value of bytes.
2440 * 0 on success, otherwise a negative errno value and rte_errno is set.
2443 _flow_dv_query_count(struct rte_eth_dev *dev,
2444 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2447 struct mlx5_priv *priv = dev->data->dev_private;
2448 struct mlx5_flow_counter_pool *pool =
2449 flow_dv_counter_pool_get(cnt);
2450 int offset = cnt - &pool->counters_raw[0];
2452 if (priv->counter_fallback)
2453 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
2455 rte_spinlock_lock(&pool->sl);
2457 * The single counters allocation may allocate smaller ID than the
2458 * current allocated in parallel to the host reading.
2459 * In this case the new counter values must be reported as 0.
2461 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
2465 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
2466 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
2468 rte_spinlock_unlock(&pool->sl);
2473 * Create and initialize a new counter pool.
2476 * Pointer to the Ethernet device structure.
2478 * The devX counter handle.
2480 * Whether the pool is for counter that was allocated by batch command.
2483 * A new pool pointer on success, NULL otherwise and rte_errno is set.
2485 static struct mlx5_flow_counter_pool *
2486 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
2489 struct mlx5_priv *priv = dev->data->dev_private;
2490 struct mlx5_flow_counter_pool *pool;
2491 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
2493 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
2496 if (cont->n == n_valid) {
2497 cont = flow_dv_container_resize(dev, batch);
2501 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
2502 sizeof(struct mlx5_flow_counter);
2503 pool = rte_calloc(__func__, 1, size, 0);
2508 pool->min_dcs = dcs;
2509 pool->raw = cont->init_mem_mng->raws + n_valid %
2510 MLX5_CNT_CONTAINER_RESIZE;
2511 pool->raw_hw = NULL;
2512 rte_spinlock_init(&pool->sl);
2514 * The generation of the new allocated counters in this pool is 0, 2 in
2515 * the pool generation makes all the counters valid for allocation.
2517 rte_atomic64_set(&pool->query_gen, 0x2);
2518 TAILQ_INIT(&pool->counters);
2519 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
2520 cont->pools[n_valid] = pool;
2521 /* Pool initialization must be updated before host thread access. */
2523 rte_atomic16_add(&cont->n_valid, 1);
2528 * Prepare a new counter and/or a new counter pool.
2531 * Pointer to the Ethernet device structure.
2532 * @param[out] cnt_free
2533 * Where to put the pointer of a new counter.
2535 * Whether the pool is for counter that was allocated by batch command.
2538 * The free counter pool pointer and @p cnt_free is set on success,
2539 * NULL otherwise and rte_errno is set.
2541 static struct mlx5_flow_counter_pool *
2542 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
2543 struct mlx5_flow_counter **cnt_free,
2546 struct mlx5_priv *priv = dev->data->dev_private;
2547 struct mlx5_flow_counter_pool *pool;
2548 struct mlx5_devx_obj *dcs = NULL;
2549 struct mlx5_flow_counter *cnt;
2553 /* bulk_bitmap must be 0 for single counter allocation. */
2554 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2557 pool = flow_dv_find_pool_by_id
2558 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
2560 pool = flow_dv_pool_create(dev, dcs, batch);
2562 mlx5_devx_cmd_destroy(dcs);
2565 } else if (dcs->id < pool->min_dcs->id) {
2566 rte_atomic64_set(&pool->a64_dcs,
2567 (int64_t)(uintptr_t)dcs);
2569 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
2570 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
2575 /* bulk_bitmap is in 128 counters units. */
2576 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
2577 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
2579 rte_errno = ENODATA;
2582 pool = flow_dv_pool_create(dev, dcs, batch);
2584 mlx5_devx_cmd_destroy(dcs);
2587 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
2588 cnt = &pool->counters_raw[i];
2590 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
2592 *cnt_free = &pool->counters_raw[0];
2597 * Search for existed shared counter.
2600 * Pointer to the relevant counter pool container.
2602 * The shared counter ID to search.
2605 * NULL if not existed, otherwise pointer to the shared counter.
2607 static struct mlx5_flow_counter *
2608 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
2611 static struct mlx5_flow_counter *cnt;
2612 struct mlx5_flow_counter_pool *pool;
2615 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2616 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
2617 cnt = &pool->counters_raw[i];
2618 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
2626 * Allocate a flow counter.
2629 * Pointer to the Ethernet device structure.
2631 * Indicate if this counter is shared with other flows.
2633 * Counter identifier.
2635 * Counter flow group.
2638 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2640 static struct mlx5_flow_counter *
2641 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
2644 struct mlx5_priv *priv = dev->data->dev_private;
2645 struct mlx5_flow_counter_pool *pool = NULL;
2646 struct mlx5_flow_counter *cnt_free = NULL;
2648 * Currently group 0 flow counter cannot be assigned to a flow if it is
2649 * not the first one in the batch counter allocation, so it is better
2650 * to allocate counters one by one for these flows in a separate
2652 * A counter can be shared between different groups so need to take
2653 * shared counters from the single container.
2655 uint32_t batch = (group && !shared) ? 1 : 0;
2656 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
2659 if (priv->counter_fallback)
2660 return flow_dv_counter_alloc_fallback(dev, shared, id);
2661 if (!priv->config.devx) {
2662 rte_errno = ENOTSUP;
2666 cnt_free = flow_dv_counter_shared_search(cont, id);
2668 if (cnt_free->ref_cnt + 1 == 0) {
2672 cnt_free->ref_cnt++;
2676 /* Pools which has a free counters are in the start. */
2677 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2679 * The free counter reset values must be updated between the
2680 * counter release to the counter allocation, so, at least one
2681 * query must be done in this time. ensure it by saving the
2682 * query generation in the release time.
2683 * The free list is sorted according to the generation - so if
2684 * the first one is not updated, all the others are not
2687 cnt_free = TAILQ_FIRST(&pool->counters);
2688 if (cnt_free && cnt_free->query_gen + 1 <
2689 rte_atomic64_read(&pool->query_gen))
2694 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
2698 cnt_free->batch = batch;
2699 /* Create a DV counter action only in the first time usage. */
2700 if (!cnt_free->action) {
2702 struct mlx5_devx_obj *dcs;
2705 offset = cnt_free - &pool->counters_raw[0];
2706 dcs = pool->min_dcs;
2709 dcs = cnt_free->dcs;
2711 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
2713 if (!cnt_free->action) {
2718 /* Update the counter reset values. */
2719 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
2722 cnt_free->shared = shared;
2723 cnt_free->ref_cnt = 1;
2725 if (!priv->sh->cmng.query_thread_on)
2726 /* Start the asynchronous batch query by the host thread. */
2727 mlx5_set_query_alarm(priv->sh);
2728 TAILQ_REMOVE(&pool->counters, cnt_free, next);
2729 if (TAILQ_EMPTY(&pool->counters)) {
2730 /* Move the pool to the end of the container pool list. */
2731 TAILQ_REMOVE(&cont->pool_list, pool, next);
2732 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
2738 * Release a flow counter.
2741 * Pointer to the Ethernet device structure.
2742 * @param[in] counter
2743 * Pointer to the counter handler.
2746 flow_dv_counter_release(struct rte_eth_dev *dev,
2747 struct mlx5_flow_counter *counter)
2749 struct mlx5_priv *priv = dev->data->dev_private;
2753 if (priv->counter_fallback) {
2754 flow_dv_counter_release_fallback(dev, counter);
2757 if (--counter->ref_cnt == 0) {
2758 struct mlx5_flow_counter_pool *pool =
2759 flow_dv_counter_pool_get(counter);
2761 /* Put the counter in the end - the last updated one. */
2762 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
2763 counter->query_gen = rte_atomic64_read(&pool->query_gen);
2768 * Verify the @p attributes will be correctly understood by the NIC and store
2769 * them in the @p flow if everything is correct.
2772 * Pointer to dev struct.
2773 * @param[in] attributes
2774 * Pointer to flow attributes
2776 * Pointer to error structure.
2779 * 0 on success, a negative errno value otherwise and rte_errno is set.
2782 flow_dv_validate_attributes(struct rte_eth_dev *dev,
2783 const struct rte_flow_attr *attributes,
2784 struct rte_flow_error *error)
2786 struct mlx5_priv *priv = dev->data->dev_private;
2787 uint32_t priority_max = priv->config.flow_prio - 1;
2789 #ifndef HAVE_MLX5DV_DR
2790 if (attributes->group)
2791 return rte_flow_error_set(error, ENOTSUP,
2792 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
2794 "groups is not supported");
2796 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
2797 attributes->priority >= priority_max)
2798 return rte_flow_error_set(error, ENOTSUP,
2799 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
2801 "priority out of range");
2802 if (attributes->transfer) {
2803 if (!priv->config.dv_esw_en)
2804 return rte_flow_error_set
2806 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2807 "E-Switch dr is not supported");
2808 if (!(priv->representor || priv->master))
2809 return rte_flow_error_set
2810 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2811 NULL, "E-Switch configurationd can only be"
2812 " done by a master or a representor device");
2813 if (attributes->egress)
2814 return rte_flow_error_set
2816 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
2817 "egress is not supported");
2818 if (attributes->group >= MLX5_MAX_TABLES_FDB)
2819 return rte_flow_error_set
2821 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
2822 NULL, "group must be smaller than "
2823 RTE_STR(MLX5_MAX_FDB_TABLES));
2825 if (!(attributes->egress ^ attributes->ingress))
2826 return rte_flow_error_set(error, ENOTSUP,
2827 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
2828 "must specify exactly one of "
2829 "ingress or egress");
2834 * Internal validation function. For validating both actions and items.
2837 * Pointer to the rte_eth_dev structure.
2839 * Pointer to the flow attributes.
2841 * Pointer to the list of items.
2842 * @param[in] actions
2843 * Pointer to the list of actions.
2845 * Pointer to the error structure.
2848 * 0 on success, a negative errno value otherwise and rte_errno is set.
2851 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
2852 const struct rte_flow_item items[],
2853 const struct rte_flow_action actions[],
2854 struct rte_flow_error *error)
2857 uint64_t action_flags = 0;
2858 uint64_t item_flags = 0;
2859 uint64_t last_item = 0;
2860 uint8_t next_protocol = 0xff;
2862 const struct rte_flow_item *gre_item = NULL;
2863 struct rte_flow_item_tcp nic_tcp_mask = {
2866 .src_port = RTE_BE16(UINT16_MAX),
2867 .dst_port = RTE_BE16(UINT16_MAX),
2873 ret = flow_dv_validate_attributes(dev, attr, error);
2876 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2877 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2878 switch (items->type) {
2879 case RTE_FLOW_ITEM_TYPE_VOID:
2881 case RTE_FLOW_ITEM_TYPE_PORT_ID:
2882 ret = flow_dv_validate_item_port_id
2883 (dev, items, attr, item_flags, error);
2886 last_item = MLX5_FLOW_ITEM_PORT_ID;
2888 case RTE_FLOW_ITEM_TYPE_ETH:
2889 ret = mlx5_flow_validate_item_eth(items, item_flags,
2893 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
2894 MLX5_FLOW_LAYER_OUTER_L2;
2896 case RTE_FLOW_ITEM_TYPE_VLAN:
2897 ret = mlx5_flow_validate_item_vlan(items, item_flags,
2901 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2902 MLX5_FLOW_LAYER_OUTER_VLAN;
2904 case RTE_FLOW_ITEM_TYPE_IPV4:
2905 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
2909 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
2910 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
2911 if (items->mask != NULL &&
2912 ((const struct rte_flow_item_ipv4 *)
2913 items->mask)->hdr.next_proto_id) {
2915 ((const struct rte_flow_item_ipv4 *)
2916 (items->spec))->hdr.next_proto_id;
2918 ((const struct rte_flow_item_ipv4 *)
2919 (items->mask))->hdr.next_proto_id;
2921 /* Reset for inner layer. */
2922 next_protocol = 0xff;
2924 mlx5_flow_tunnel_ip_check(items, &last_item);
2926 case RTE_FLOW_ITEM_TYPE_IPV6:
2927 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
2931 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
2932 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
2933 if (items->mask != NULL &&
2934 ((const struct rte_flow_item_ipv6 *)
2935 items->mask)->hdr.proto) {
2937 ((const struct rte_flow_item_ipv6 *)
2938 items->spec)->hdr.proto;
2940 ((const struct rte_flow_item_ipv6 *)
2941 items->mask)->hdr.proto;
2943 /* Reset for inner layer. */
2944 next_protocol = 0xff;
2946 mlx5_flow_tunnel_ip_check(items, &last_item);
2948 case RTE_FLOW_ITEM_TYPE_TCP:
2949 ret = mlx5_flow_validate_item_tcp
2956 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
2957 MLX5_FLOW_LAYER_OUTER_L4_TCP;
2959 case RTE_FLOW_ITEM_TYPE_UDP:
2960 ret = mlx5_flow_validate_item_udp(items, item_flags,
2965 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
2966 MLX5_FLOW_LAYER_OUTER_L4_UDP;
2968 case RTE_FLOW_ITEM_TYPE_GRE:
2969 ret = mlx5_flow_validate_item_gre(items, item_flags,
2970 next_protocol, error);
2974 last_item = MLX5_FLOW_LAYER_GRE;
2976 case RTE_FLOW_ITEM_TYPE_NVGRE:
2977 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
2982 last_item = MLX5_FLOW_LAYER_NVGRE;
2984 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
2985 ret = mlx5_flow_validate_item_gre_key
2986 (items, item_flags, gre_item, error);
2989 last_item = MLX5_FLOW_LAYER_GRE_KEY;
2991 case RTE_FLOW_ITEM_TYPE_VXLAN:
2992 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
2996 last_item = MLX5_FLOW_LAYER_VXLAN;
2998 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2999 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3004 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3006 case RTE_FLOW_ITEM_TYPE_MPLS:
3007 ret = mlx5_flow_validate_item_mpls(dev, items,
3012 last_item = MLX5_FLOW_LAYER_MPLS;
3014 case RTE_FLOW_ITEM_TYPE_META:
3015 ret = flow_dv_validate_item_meta(dev, items, attr,
3019 last_item = MLX5_FLOW_ITEM_METADATA;
3021 case RTE_FLOW_ITEM_TYPE_ICMP:
3022 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3027 last_item = MLX5_FLOW_LAYER_ICMP;
3029 case RTE_FLOW_ITEM_TYPE_ICMP6:
3030 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3035 last_item = MLX5_FLOW_LAYER_ICMP6;
3038 return rte_flow_error_set(error, ENOTSUP,
3039 RTE_FLOW_ERROR_TYPE_ITEM,
3040 NULL, "item not supported");
3042 item_flags |= last_item;
3044 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3045 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3046 return rte_flow_error_set(error, ENOTSUP,
3047 RTE_FLOW_ERROR_TYPE_ACTION,
3048 actions, "too many actions");
3049 switch (actions->type) {
3050 case RTE_FLOW_ACTION_TYPE_VOID:
3052 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3053 ret = flow_dv_validate_action_port_id(dev,
3060 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3063 case RTE_FLOW_ACTION_TYPE_FLAG:
3064 ret = mlx5_flow_validate_action_flag(action_flags,
3068 action_flags |= MLX5_FLOW_ACTION_FLAG;
3071 case RTE_FLOW_ACTION_TYPE_MARK:
3072 ret = mlx5_flow_validate_action_mark(actions,
3077 action_flags |= MLX5_FLOW_ACTION_MARK;
3080 case RTE_FLOW_ACTION_TYPE_DROP:
3081 ret = mlx5_flow_validate_action_drop(action_flags,
3085 action_flags |= MLX5_FLOW_ACTION_DROP;
3088 case RTE_FLOW_ACTION_TYPE_QUEUE:
3089 ret = mlx5_flow_validate_action_queue(actions,
3094 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3097 case RTE_FLOW_ACTION_TYPE_RSS:
3098 ret = mlx5_flow_validate_action_rss(actions,
3104 action_flags |= MLX5_FLOW_ACTION_RSS;
3107 case RTE_FLOW_ACTION_TYPE_COUNT:
3108 ret = flow_dv_validate_action_count(dev, error);
3111 action_flags |= MLX5_FLOW_ACTION_COUNT;
3114 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3115 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3116 ret = flow_dv_validate_action_l2_encap(action_flags,
3121 action_flags |= actions->type ==
3122 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3123 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3124 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3127 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3128 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3129 ret = flow_dv_validate_action_l2_decap(action_flags,
3133 action_flags |= actions->type ==
3134 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3135 MLX5_FLOW_ACTION_VXLAN_DECAP :
3136 MLX5_FLOW_ACTION_NVGRE_DECAP;
3139 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3140 ret = flow_dv_validate_action_raw_encap(action_flags,
3145 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3148 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3149 ret = flow_dv_validate_action_raw_decap(action_flags,
3154 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3157 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3158 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3159 ret = flow_dv_validate_action_modify_mac(action_flags,
3165 /* Count all modify-header actions as one action. */
3166 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3168 action_flags |= actions->type ==
3169 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3170 MLX5_FLOW_ACTION_SET_MAC_SRC :
3171 MLX5_FLOW_ACTION_SET_MAC_DST;
3174 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3175 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3176 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3182 /* Count all modify-header actions as one action. */
3183 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3185 action_flags |= actions->type ==
3186 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3187 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3188 MLX5_FLOW_ACTION_SET_IPV4_DST;
3190 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3191 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3192 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3198 /* Count all modify-header actions as one action. */
3199 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3201 action_flags |= actions->type ==
3202 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3203 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3204 MLX5_FLOW_ACTION_SET_IPV6_DST;
3206 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3207 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3208 ret = flow_dv_validate_action_modify_tp(action_flags,
3214 /* Count all modify-header actions as one action. */
3215 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3217 action_flags |= actions->type ==
3218 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3219 MLX5_FLOW_ACTION_SET_TP_SRC :
3220 MLX5_FLOW_ACTION_SET_TP_DST;
3222 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3223 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3224 ret = flow_dv_validate_action_modify_ttl(action_flags,
3230 /* Count all modify-header actions as one action. */
3231 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3233 action_flags |= actions->type ==
3234 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3235 MLX5_FLOW_ACTION_SET_TTL :
3236 MLX5_FLOW_ACTION_DEC_TTL;
3238 case RTE_FLOW_ACTION_TYPE_JUMP:
3239 ret = flow_dv_validate_action_jump(actions,
3240 attr->group, error);
3244 action_flags |= MLX5_FLOW_ACTION_JUMP;
3246 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3247 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3248 ret = flow_dv_validate_action_modify_tcp_seq
3255 /* Count all modify-header actions as one action. */
3256 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3258 action_flags |= actions->type ==
3259 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3260 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3261 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3263 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3264 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3265 ret = flow_dv_validate_action_modify_tcp_ack
3272 /* Count all modify-header actions as one action. */
3273 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3275 action_flags |= actions->type ==
3276 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3277 MLX5_FLOW_ACTION_INC_TCP_ACK :
3278 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3281 return rte_flow_error_set(error, ENOTSUP,
3282 RTE_FLOW_ERROR_TYPE_ACTION,
3284 "action not supported");
3287 /* Eswitch has few restrictions on using items and actions */
3288 if (attr->transfer) {
3289 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3290 return rte_flow_error_set(error, ENOTSUP,
3291 RTE_FLOW_ERROR_TYPE_ACTION,
3293 "unsupported action FLAG");
3294 if (action_flags & MLX5_FLOW_ACTION_MARK)
3295 return rte_flow_error_set(error, ENOTSUP,
3296 RTE_FLOW_ERROR_TYPE_ACTION,
3298 "unsupported action MARK");
3299 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
3300 return rte_flow_error_set(error, ENOTSUP,
3301 RTE_FLOW_ERROR_TYPE_ACTION,
3303 "unsupported action QUEUE");
3304 if (action_flags & MLX5_FLOW_ACTION_RSS)
3305 return rte_flow_error_set(error, ENOTSUP,
3306 RTE_FLOW_ERROR_TYPE_ACTION,
3308 "unsupported action RSS");
3309 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3310 return rte_flow_error_set(error, EINVAL,
3311 RTE_FLOW_ERROR_TYPE_ACTION,
3313 "no fate action is found");
3315 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION,
3319 "no fate action is found");
3325 * Internal preparation function. Allocates the DV flow size,
3326 * this size is constant.
3329 * Pointer to the flow attributes.
3331 * Pointer to the list of items.
3332 * @param[in] actions
3333 * Pointer to the list of actions.
3335 * Pointer to the error structure.
3338 * Pointer to mlx5_flow object on success,
3339 * otherwise NULL and rte_errno is set.
3341 static struct mlx5_flow *
3342 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
3343 const struct rte_flow_item items[] __rte_unused,
3344 const struct rte_flow_action actions[] __rte_unused,
3345 struct rte_flow_error *error)
3347 uint32_t size = sizeof(struct mlx5_flow);
3348 struct mlx5_flow *flow;
3350 flow = rte_calloc(__func__, 1, size, 0);
3352 rte_flow_error_set(error, ENOMEM,
3353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3354 "not enough memory to create flow");
3357 flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
3363 * Sanity check for match mask and value. Similar to check_valid_spec() in
3364 * kernel driver. If unmasked bit is present in value, it returns failure.
3367 * pointer to match mask buffer.
3368 * @param match_value
3369 * pointer to match value buffer.
3372 * 0 if valid, -EINVAL otherwise.
3375 flow_dv_check_valid_spec(void *match_mask, void *match_value)
3377 uint8_t *m = match_mask;
3378 uint8_t *v = match_value;
3381 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
3384 "match_value differs from match_criteria"
3385 " %p[%u] != %p[%u]",
3386 match_value, i, match_mask, i);
3395 * Add Ethernet item to matcher and to the value.
3397 * @param[in, out] matcher
3399 * @param[in, out] key
3400 * Flow matcher value.
3402 * Flow pattern to translate.
3404 * Item is inner pattern.
3407 flow_dv_translate_item_eth(void *matcher, void *key,
3408 const struct rte_flow_item *item, int inner)
3410 const struct rte_flow_item_eth *eth_m = item->mask;
3411 const struct rte_flow_item_eth *eth_v = item->spec;
3412 const struct rte_flow_item_eth nic_mask = {
3413 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3414 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3415 .type = RTE_BE16(0xffff),
3427 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3429 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3431 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3433 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3435 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
3436 ð_m->dst, sizeof(eth_m->dst));
3437 /* The value must be in the range of the mask. */
3438 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
3439 for (i = 0; i < sizeof(eth_m->dst); ++i)
3440 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
3441 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
3442 ð_m->src, sizeof(eth_m->src));
3443 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
3444 /* The value must be in the range of the mask. */
3445 for (i = 0; i < sizeof(eth_m->dst); ++i)
3446 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
3447 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
3448 rte_be_to_cpu_16(eth_m->type));
3449 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
3450 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
3454 * Add VLAN item to matcher and to the value.
3456 * @param[in, out] matcher
3458 * @param[in, out] key
3459 * Flow matcher value.
3461 * Flow pattern to translate.
3463 * Item is inner pattern.
3466 flow_dv_translate_item_vlan(void *matcher, void *key,
3467 const struct rte_flow_item *item,
3470 const struct rte_flow_item_vlan *vlan_m = item->mask;
3471 const struct rte_flow_item_vlan *vlan_v = item->spec;
3472 const struct rte_flow_item_vlan nic_mask = {
3473 .tci = RTE_BE16(0x0fff),
3474 .inner_type = RTE_BE16(0xffff),
3486 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3488 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3490 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3492 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3494 tci_m = rte_be_to_cpu_16(vlan_m->tci);
3495 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
3496 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
3497 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
3498 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
3499 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
3500 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
3501 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
3502 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
3503 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
3507 * Add IPV4 item to matcher and to the value.
3509 * @param[in, out] matcher
3511 * @param[in, out] key
3512 * Flow matcher value.
3514 * Flow pattern to translate.
3516 * Item is inner pattern.
3518 * The group to insert the rule.
3521 flow_dv_translate_item_ipv4(void *matcher, void *key,
3522 const struct rte_flow_item *item,
3523 int inner, uint32_t group)
3525 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
3526 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
3527 const struct rte_flow_item_ipv4 nic_mask = {
3529 .src_addr = RTE_BE32(0xffffffff),
3530 .dst_addr = RTE_BE32(0xffffffff),
3531 .type_of_service = 0xff,
3532 .next_proto_id = 0xff,
3542 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3544 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3546 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3548 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3551 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
3553 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
3554 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
3559 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3560 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3561 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3562 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3563 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
3564 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
3565 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3566 src_ipv4_src_ipv6.ipv4_layout.ipv4);
3567 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3568 src_ipv4_src_ipv6.ipv4_layout.ipv4);
3569 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
3570 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
3571 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
3572 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
3573 ipv4_m->hdr.type_of_service);
3574 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
3575 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
3576 ipv4_m->hdr.type_of_service >> 2);
3577 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
3578 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
3579 ipv4_m->hdr.next_proto_id);
3580 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
3581 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
3585 * Add IPV6 item to matcher and to the value.
3587 * @param[in, out] matcher
3589 * @param[in, out] key
3590 * Flow matcher value.
3592 * Flow pattern to translate.
3594 * Item is inner pattern.
3596 * The group to insert the rule.
3599 flow_dv_translate_item_ipv6(void *matcher, void *key,
3600 const struct rte_flow_item *item,
3601 int inner, uint32_t group)
3603 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
3604 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
3605 const struct rte_flow_item_ipv6 nic_mask = {
3608 "\xff\xff\xff\xff\xff\xff\xff\xff"
3609 "\xff\xff\xff\xff\xff\xff\xff\xff",
3611 "\xff\xff\xff\xff\xff\xff\xff\xff"
3612 "\xff\xff\xff\xff\xff\xff\xff\xff",
3613 .vtc_flow = RTE_BE32(0xffffffff),
3620 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3621 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3630 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3632 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3634 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3636 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3639 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
3641 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
3642 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
3647 size = sizeof(ipv6_m->hdr.dst_addr);
3648 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3649 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
3650 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3651 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
3652 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
3653 for (i = 0; i < size; ++i)
3654 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
3655 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
3656 src_ipv4_src_ipv6.ipv6_layout.ipv6);
3657 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3658 src_ipv4_src_ipv6.ipv6_layout.ipv6);
3659 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
3660 for (i = 0; i < size; ++i)
3661 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
3663 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
3664 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
3665 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
3666 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
3667 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
3668 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
3671 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
3673 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
3676 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
3678 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
3682 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
3684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
3685 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
3689 * Add TCP item to matcher and to the value.
3691 * @param[in, out] matcher
3693 * @param[in, out] key
3694 * Flow matcher value.
3696 * Flow pattern to translate.
3698 * Item is inner pattern.
3701 flow_dv_translate_item_tcp(void *matcher, void *key,
3702 const struct rte_flow_item *item,
3705 const struct rte_flow_item_tcp *tcp_m = item->mask;
3706 const struct rte_flow_item_tcp *tcp_v = item->spec;
3711 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3713 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3715 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3717 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3719 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
3720 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
3724 tcp_m = &rte_flow_item_tcp_mask;
3725 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
3726 rte_be_to_cpu_16(tcp_m->hdr.src_port));
3727 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
3728 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
3729 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
3730 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
3731 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
3732 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
3733 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
3734 tcp_m->hdr.tcp_flags);
3735 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
3736 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
3740 * Add UDP item to matcher and to the value.
3742 * @param[in, out] matcher
3744 * @param[in, out] key
3745 * Flow matcher value.
3747 * Flow pattern to translate.
3749 * Item is inner pattern.
3752 flow_dv_translate_item_udp(void *matcher, void *key,
3753 const struct rte_flow_item *item,
3756 const struct rte_flow_item_udp *udp_m = item->mask;
3757 const struct rte_flow_item_udp *udp_v = item->spec;
3762 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3764 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3766 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3768 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3770 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
3771 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
3775 udp_m = &rte_flow_item_udp_mask;
3776 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
3777 rte_be_to_cpu_16(udp_m->hdr.src_port));
3778 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
3779 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
3780 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
3781 rte_be_to_cpu_16(udp_m->hdr.dst_port));
3782 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
3783 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
3787 * Add GRE optional Key item to matcher and to the value.
3789 * @param[in, out] matcher
3791 * @param[in, out] key
3792 * Flow matcher value.
3794 * Flow pattern to translate.
3796 * Item is inner pattern.
3799 flow_dv_translate_item_gre_key(void *matcher, void *key,
3800 const struct rte_flow_item *item)
3802 const rte_be32_t *key_m = item->mask;
3803 const rte_be32_t *key_v = item->spec;
3804 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3805 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3806 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
3811 key_m = &gre_key_default_mask;
3812 /* GRE K bit must be on and should already be validated */
3813 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
3814 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
3815 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
3816 rte_be_to_cpu_32(*key_m) >> 8);
3817 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
3818 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
3819 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
3820 rte_be_to_cpu_32(*key_m) & 0xFF);
3821 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
3822 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
3826 * Add GRE item to matcher and to the value.
3828 * @param[in, out] matcher
3830 * @param[in, out] key
3831 * Flow matcher value.
3833 * Flow pattern to translate.
3835 * Item is inner pattern.
3838 flow_dv_translate_item_gre(void *matcher, void *key,
3839 const struct rte_flow_item *item,
3842 const struct rte_flow_item_gre *gre_m = item->mask;
3843 const struct rte_flow_item_gre *gre_v = item->spec;
3846 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3847 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3854 uint16_t s_present:1;
3855 uint16_t k_present:1;
3856 uint16_t rsvd_bit1:1;
3857 uint16_t c_present:1;
3861 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
3864 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3866 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3868 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3870 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3872 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
3873 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
3877 gre_m = &rte_flow_item_gre_mask;
3878 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
3879 rte_be_to_cpu_16(gre_m->protocol));
3880 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
3881 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
3882 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
3883 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
3884 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
3885 gre_crks_rsvd0_ver_m.c_present);
3886 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
3887 gre_crks_rsvd0_ver_v.c_present &
3888 gre_crks_rsvd0_ver_m.c_present);
3889 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
3890 gre_crks_rsvd0_ver_m.k_present);
3891 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
3892 gre_crks_rsvd0_ver_v.k_present &
3893 gre_crks_rsvd0_ver_m.k_present);
3894 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
3895 gre_crks_rsvd0_ver_m.s_present);
3896 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
3897 gre_crks_rsvd0_ver_v.s_present &
3898 gre_crks_rsvd0_ver_m.s_present);
3902 * Add NVGRE item to matcher and to the value.
3904 * @param[in, out] matcher
3906 * @param[in, out] key
3907 * Flow matcher value.
3909 * Flow pattern to translate.
3911 * Item is inner pattern.
3914 flow_dv_translate_item_nvgre(void *matcher, void *key,
3915 const struct rte_flow_item *item,
3918 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
3919 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
3920 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3921 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3922 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
3923 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
3929 /* For NVGRE, GRE header fields must be set with defined values. */
3930 const struct rte_flow_item_gre gre_spec = {
3931 .c_rsvd0_ver = RTE_BE16(0x2000),
3932 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
3934 const struct rte_flow_item_gre gre_mask = {
3935 .c_rsvd0_ver = RTE_BE16(0xB000),
3936 .protocol = RTE_BE16(UINT16_MAX),
3938 const struct rte_flow_item gre_item = {
3943 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
3947 nvgre_m = &rte_flow_item_nvgre_mask;
3948 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
3949 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
3950 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
3951 memcpy(gre_key_m, tni_flow_id_m, size);
3952 for (i = 0; i < size; ++i)
3953 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
3957 * Add VXLAN item to matcher and to the value.
3959 * @param[in, out] matcher
3961 * @param[in, out] key
3962 * Flow matcher value.
3964 * Flow pattern to translate.
3966 * Item is inner pattern.
3969 flow_dv_translate_item_vxlan(void *matcher, void *key,
3970 const struct rte_flow_item *item,
3973 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
3974 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
3977 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
3978 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
3986 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3988 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3990 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3992 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3994 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
3995 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
3996 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
3997 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
3998 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4003 vxlan_m = &rte_flow_item_vxlan_mask;
4004 size = sizeof(vxlan_m->vni);
4005 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4006 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4007 memcpy(vni_m, vxlan_m->vni, size);
4008 for (i = 0; i < size; ++i)
4009 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4013 * Add MPLS item to matcher and to the value.
4015 * @param[in, out] matcher
4017 * @param[in, out] key
4018 * Flow matcher value.
4020 * Flow pattern to translate.
4021 * @param[in] prev_layer
4022 * The protocol layer indicated in previous item.
4024 * Item is inner pattern.
4027 flow_dv_translate_item_mpls(void *matcher, void *key,
4028 const struct rte_flow_item *item,
4029 uint64_t prev_layer,
4032 const uint32_t *in_mpls_m = item->mask;
4033 const uint32_t *in_mpls_v = item->spec;
4034 uint32_t *out_mpls_m = 0;
4035 uint32_t *out_mpls_v = 0;
4036 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4037 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4038 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4040 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4041 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4042 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4044 switch (prev_layer) {
4045 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4046 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4047 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4048 MLX5_UDP_PORT_MPLS);
4050 case MLX5_FLOW_LAYER_GRE:
4051 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4052 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4053 RTE_ETHER_TYPE_MPLS);
4056 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4057 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4064 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4065 switch (prev_layer) {
4066 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4068 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4069 outer_first_mpls_over_udp);
4071 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4072 outer_first_mpls_over_udp);
4074 case MLX5_FLOW_LAYER_GRE:
4076 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4077 outer_first_mpls_over_gre);
4079 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4080 outer_first_mpls_over_gre);
4083 /* Inner MPLS not over GRE is not supported. */
4086 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4090 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4096 if (out_mpls_m && out_mpls_v) {
4097 *out_mpls_m = *in_mpls_m;
4098 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4103 * Add META item to matcher
4105 * @param[in, out] matcher
4107 * @param[in, out] key
4108 * Flow matcher value.
4110 * Flow pattern to translate.
4112 * Item is inner pattern.
4115 flow_dv_translate_item_meta(void *matcher, void *key,
4116 const struct rte_flow_item *item)
4118 const struct rte_flow_item_meta *meta_m;
4119 const struct rte_flow_item_meta *meta_v;
4121 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4123 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4125 meta_m = (const void *)item->mask;
4127 meta_m = &rte_flow_item_meta_mask;
4128 meta_v = (const void *)item->spec;
4130 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4131 rte_be_to_cpu_32(meta_m->data));
4132 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4133 rte_be_to_cpu_32(meta_v->data & meta_m->data));
4138 * Add source vport match to the specified matcher.
4140 * @param[in, out] matcher
4142 * @param[in, out] key
4143 * Flow matcher value.
4145 * Source vport value to match
4150 flow_dv_translate_item_source_vport(void *matcher, void *key,
4151 int16_t port, uint16_t mask)
4153 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4154 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4156 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
4157 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
4161 * Translate port-id item to eswitch match on port-id.
4164 * The devich to configure through.
4165 * @param[in, out] matcher
4167 * @param[in, out] key
4168 * Flow matcher value.
4170 * Flow pattern to translate.
4173 * 0 on success, a negative errno value otherwise.
4176 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
4177 void *key, const struct rte_flow_item *item)
4179 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
4180 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
4181 uint16_t mask, val, id;
4184 mask = pid_m ? pid_m->id : 0xffff;
4185 id = pid_v ? pid_v->id : dev->data->port_id;
4186 ret = mlx5_port_to_eswitch_info(id, NULL, &val);
4189 flow_dv_translate_item_source_vport(matcher, key, val, mask);
4194 * Add ICMP6 item to matcher and to the value.
4196 * @param[in, out] matcher
4198 * @param[in, out] key
4199 * Flow matcher value.
4201 * Flow pattern to translate.
4203 * Item is inner pattern.
4206 flow_dv_translate_item_icmp6(void *matcher, void *key,
4207 const struct rte_flow_item *item,
4210 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
4211 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
4214 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4216 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4218 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4220 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4222 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4224 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4226 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4227 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
4231 icmp6_m = &rte_flow_item_icmp6_mask;
4232 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
4233 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
4234 icmp6_v->type & icmp6_m->type);
4235 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
4236 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
4237 icmp6_v->code & icmp6_m->code);
4241 * Add ICMP item to matcher and to the value.
4243 * @param[in, out] matcher
4245 * @param[in, out] key
4246 * Flow matcher value.
4248 * Flow pattern to translate.
4250 * Item is inner pattern.
4253 flow_dv_translate_item_icmp(void *matcher, void *key,
4254 const struct rte_flow_item *item,
4257 const struct rte_flow_item_icmp *icmp_m = item->mask;
4258 const struct rte_flow_item_icmp *icmp_v = item->spec;
4261 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4263 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4265 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4267 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4269 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4271 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4273 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4274 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
4278 icmp_m = &rte_flow_item_icmp_mask;
4279 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
4280 icmp_m->hdr.icmp_type);
4281 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
4282 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
4283 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
4284 icmp_m->hdr.icmp_code);
4285 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
4286 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
4289 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
4291 #define HEADER_IS_ZERO(match_criteria, headers) \
4292 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
4293 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
4296 * Calculate flow matcher enable bitmap.
4298 * @param match_criteria
4299 * Pointer to flow matcher criteria.
4302 * Bitmap of enabled fields.
4305 flow_dv_matcher_enable(uint32_t *match_criteria)
4307 uint8_t match_criteria_enable;
4309 match_criteria_enable =
4310 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
4311 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
4312 match_criteria_enable |=
4313 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
4314 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
4315 match_criteria_enable |=
4316 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
4317 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
4318 match_criteria_enable |=
4319 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
4320 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
4321 #ifdef HAVE_MLX5DV_DR
4322 match_criteria_enable |=
4323 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
4324 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
4326 return match_criteria_enable;
4333 * @param dev[in, out]
4334 * Pointer to rte_eth_dev structure.
4335 * @param[in] table_id
4338 * Direction of the table.
4339 * @param[in] transfer
4340 * E-Switch or NIC flow.
4342 * pointer to error structure.
4345 * Returns tables resource based on the index, NULL in case of failed.
4347 static struct mlx5_flow_tbl_resource *
4348 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
4349 uint32_t table_id, uint8_t egress,
4351 struct rte_flow_error *error)
4353 struct mlx5_priv *priv = dev->data->dev_private;
4354 struct mlx5_ibv_shared *sh = priv->sh;
4355 struct mlx5_flow_tbl_resource *tbl;
4357 #ifdef HAVE_MLX5DV_DR
4359 tbl = &sh->fdb_tbl[table_id];
4361 tbl->obj = mlx5_glue->dr_create_flow_tbl
4362 (sh->fdb_domain, table_id);
4363 } else if (egress) {
4364 tbl = &sh->tx_tbl[table_id];
4366 tbl->obj = mlx5_glue->dr_create_flow_tbl
4367 (sh->tx_domain, table_id);
4369 tbl = &sh->rx_tbl[table_id];
4371 tbl->obj = mlx5_glue->dr_create_flow_tbl
4372 (sh->rx_domain, table_id);
4375 rte_flow_error_set(error, ENOMEM,
4376 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4377 NULL, "cannot create table");
4380 rte_atomic32_inc(&tbl->refcnt);
4386 return &sh->fdb_tbl[table_id];
4388 return &sh->tx_tbl[table_id];
4390 return &sh->rx_tbl[table_id];
4395 * Release a flow table.
4398 * Table resource to be released.
4401 * Returns 0 if table was released, else return 1;
4404 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
4408 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
4409 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
4417 * Register the flow matcher.
4419 * @param dev[in, out]
4420 * Pointer to rte_eth_dev structure.
4421 * @param[in, out] matcher
4422 * Pointer to flow matcher.
4423 * @parm[in, out] dev_flow
4424 * Pointer to the dev_flow.
4426 * pointer to error structure.
4429 * 0 on success otherwise -errno and errno is set.
4432 flow_dv_matcher_register(struct rte_eth_dev *dev,
4433 struct mlx5_flow_dv_matcher *matcher,
4434 struct mlx5_flow *dev_flow,
4435 struct rte_flow_error *error)
4437 struct mlx5_priv *priv = dev->data->dev_private;
4438 struct mlx5_ibv_shared *sh = priv->sh;
4439 struct mlx5_flow_dv_matcher *cache_matcher;
4440 struct mlx5dv_flow_matcher_attr dv_attr = {
4441 .type = IBV_FLOW_ATTR_NORMAL,
4442 .match_mask = (void *)&matcher->mask,
4444 struct mlx5_flow_tbl_resource *tbl = NULL;
4446 /* Lookup from cache. */
4447 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
4448 if (matcher->crc == cache_matcher->crc &&
4449 matcher->priority == cache_matcher->priority &&
4450 matcher->egress == cache_matcher->egress &&
4451 matcher->group == cache_matcher->group &&
4452 matcher->transfer == cache_matcher->transfer &&
4453 !memcmp((const void *)matcher->mask.buf,
4454 (const void *)cache_matcher->mask.buf,
4455 cache_matcher->mask.size)) {
4457 "priority %hd use %s matcher %p: refcnt %d++",
4458 cache_matcher->priority,
4459 cache_matcher->egress ? "tx" : "rx",
4460 (void *)cache_matcher,
4461 rte_atomic32_read(&cache_matcher->refcnt));
4462 rte_atomic32_inc(&cache_matcher->refcnt);
4463 dev_flow->dv.matcher = cache_matcher;
4467 /* Register new matcher. */
4468 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
4470 return rte_flow_error_set(error, ENOMEM,
4471 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4472 "cannot allocate matcher memory");
4473 tbl = flow_dv_tbl_resource_get(dev, matcher->group * MLX5_GROUP_FACTOR,
4474 matcher->egress, matcher->transfer,
4477 rte_free(cache_matcher);
4478 return rte_flow_error_set(error, ENOMEM,
4479 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4480 NULL, "cannot create table");
4482 *cache_matcher = *matcher;
4483 dv_attr.match_criteria_enable =
4484 flow_dv_matcher_enable(cache_matcher->mask.buf);
4485 dv_attr.priority = matcher->priority;
4486 if (matcher->egress)
4487 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
4488 cache_matcher->matcher_object =
4489 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
4490 if (!cache_matcher->matcher_object) {
4491 rte_free(cache_matcher);
4492 #ifdef HAVE_MLX5DV_DR
4493 flow_dv_tbl_resource_release(tbl);
4495 return rte_flow_error_set(error, ENOMEM,
4496 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4497 NULL, "cannot create matcher");
4499 rte_atomic32_inc(&cache_matcher->refcnt);
4500 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
4501 dev_flow->dv.matcher = cache_matcher;
4502 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
4503 cache_matcher->priority,
4504 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
4505 rte_atomic32_read(&cache_matcher->refcnt));
4506 rte_atomic32_inc(&tbl->refcnt);
4511 * Find existing tag resource or create and register a new one.
4513 * @param dev[in, out]
4514 * Pointer to rte_eth_dev structure.
4515 * @param[in, out] resource
4516 * Pointer to tag resource.
4517 * @parm[in, out] dev_flow
4518 * Pointer to the dev_flow.
4520 * pointer to error structure.
4523 * 0 on success otherwise -errno and errno is set.
4526 flow_dv_tag_resource_register
4527 (struct rte_eth_dev *dev,
4528 struct mlx5_flow_dv_tag_resource *resource,
4529 struct mlx5_flow *dev_flow,
4530 struct rte_flow_error *error)
4532 struct mlx5_priv *priv = dev->data->dev_private;
4533 struct mlx5_ibv_shared *sh = priv->sh;
4534 struct mlx5_flow_dv_tag_resource *cache_resource;
4536 /* Lookup a matching resource from cache. */
4537 LIST_FOREACH(cache_resource, &sh->tags, next) {
4538 if (resource->tag == cache_resource->tag) {
4539 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
4540 (void *)cache_resource,
4541 rte_atomic32_read(&cache_resource->refcnt));
4542 rte_atomic32_inc(&cache_resource->refcnt);
4543 dev_flow->flow->tag_resource = cache_resource;
4547 /* Register new resource. */
4548 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
4549 if (!cache_resource)
4550 return rte_flow_error_set(error, ENOMEM,
4551 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4552 "cannot allocate resource memory");
4553 *cache_resource = *resource;
4554 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
4556 if (!cache_resource->action) {
4557 rte_free(cache_resource);
4558 return rte_flow_error_set(error, ENOMEM,
4559 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4560 NULL, "cannot create action");
4562 rte_atomic32_init(&cache_resource->refcnt);
4563 rte_atomic32_inc(&cache_resource->refcnt);
4564 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
4565 dev_flow->flow->tag_resource = cache_resource;
4566 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
4567 (void *)cache_resource,
4568 rte_atomic32_read(&cache_resource->refcnt));
4576 * Pointer to Ethernet device.
4578 * Pointer to mlx5_flow.
4581 * 1 while a reference on it exists, 0 when freed.
4584 flow_dv_tag_release(struct rte_eth_dev *dev,
4585 struct mlx5_flow_dv_tag_resource *tag)
4588 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
4589 dev->data->port_id, (void *)tag,
4590 rte_atomic32_read(&tag->refcnt));
4591 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
4592 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
4593 LIST_REMOVE(tag, next);
4594 DRV_LOG(DEBUG, "port %u tag %p: removed",
4595 dev->data->port_id, (void *)tag);
4603 * Translate port ID action to vport.
4606 * Pointer to rte_eth_dev structure.
4608 * Pointer to the port ID action.
4609 * @param[out] dst_port_id
4610 * The target port ID.
4612 * Pointer to the error structure.
4615 * 0 on success, a negative errno value otherwise and rte_errno is set.
4618 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
4619 const struct rte_flow_action *action,
4620 uint32_t *dst_port_id,
4621 struct rte_flow_error *error)
4626 const struct rte_flow_action_port_id *conf =
4627 (const struct rte_flow_action_port_id *)action->conf;
4629 port = conf->original ? dev->data->port_id : conf->id;
4630 ret = mlx5_port_to_eswitch_info(port, NULL, &port_id);
4632 return rte_flow_error_set(error, -ret,
4633 RTE_FLOW_ERROR_TYPE_ACTION,
4635 "No eswitch info was found for port");
4636 *dst_port_id = port_id;
4641 * Fill the flow with DV spec.
4644 * Pointer to rte_eth_dev structure.
4645 * @param[in, out] dev_flow
4646 * Pointer to the sub flow.
4648 * Pointer to the flow attributes.
4650 * Pointer to the list of items.
4651 * @param[in] actions
4652 * Pointer to the list of actions.
4654 * Pointer to the error structure.
4657 * 0 on success, a negative errno value otherwise and rte_errno is set.
4660 flow_dv_translate(struct rte_eth_dev *dev,
4661 struct mlx5_flow *dev_flow,
4662 const struct rte_flow_attr *attr,
4663 const struct rte_flow_item items[],
4664 const struct rte_flow_action actions[],
4665 struct rte_flow_error *error)
4667 struct mlx5_priv *priv = dev->data->dev_private;
4668 struct rte_flow *flow = dev_flow->flow;
4669 uint64_t item_flags = 0;
4670 uint64_t last_item = 0;
4671 uint64_t action_flags = 0;
4672 uint64_t priority = attr->priority;
4673 struct mlx5_flow_dv_matcher matcher = {
4675 .size = sizeof(matcher.mask.buf),
4679 bool actions_end = false;
4680 struct mlx5_flow_dv_modify_hdr_resource res = {
4681 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4682 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
4684 union flow_dv_attr flow_attr = { .attr = 0 };
4685 struct mlx5_flow_dv_tag_resource tag_resource;
4686 uint32_t modify_action_position = UINT32_MAX;
4687 void *match_mask = matcher.mask.buf;
4688 void *match_value = dev_flow->dv.value.buf;
4690 flow->group = attr->group;
4692 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4693 if (priority == MLX5_FLOW_PRIO_RSVD)
4694 priority = priv->config.flow_prio - 1;
4695 for (; !actions_end ; actions++) {
4696 const struct rte_flow_action_queue *queue;
4697 const struct rte_flow_action_rss *rss;
4698 const struct rte_flow_action *action = actions;
4699 const struct rte_flow_action_count *count = action->conf;
4700 const uint8_t *rss_key;
4701 const struct rte_flow_action_jump *jump_data;
4702 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
4703 struct mlx5_flow_tbl_resource *tbl;
4704 uint32_t port_id = 0;
4705 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
4707 switch (actions->type) {
4708 case RTE_FLOW_ACTION_TYPE_VOID:
4710 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4711 if (flow_dv_translate_action_port_id(dev, action,
4714 port_id_resource.port_id = port_id;
4715 if (flow_dv_port_id_action_resource_register
4716 (dev, &port_id_resource, dev_flow, error))
4718 dev_flow->dv.actions[actions_n++] =
4719 dev_flow->dv.port_id_action->action;
4720 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4722 case RTE_FLOW_ACTION_TYPE_FLAG:
4724 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
4725 if (!flow->tag_resource)
4726 if (flow_dv_tag_resource_register
4727 (dev, &tag_resource, dev_flow, error))
4729 dev_flow->dv.actions[actions_n++] =
4730 flow->tag_resource->action;
4731 action_flags |= MLX5_FLOW_ACTION_FLAG;
4733 case RTE_FLOW_ACTION_TYPE_MARK:
4734 tag_resource.tag = mlx5_flow_mark_set
4735 (((const struct rte_flow_action_mark *)
4736 (actions->conf))->id);
4737 if (!flow->tag_resource)
4738 if (flow_dv_tag_resource_register
4739 (dev, &tag_resource, dev_flow, error))
4741 dev_flow->dv.actions[actions_n++] =
4742 flow->tag_resource->action;
4743 action_flags |= MLX5_FLOW_ACTION_MARK;
4745 case RTE_FLOW_ACTION_TYPE_DROP:
4746 action_flags |= MLX5_FLOW_ACTION_DROP;
4748 case RTE_FLOW_ACTION_TYPE_QUEUE:
4749 queue = actions->conf;
4750 flow->rss.queue_num = 1;
4751 (*flow->queue)[0] = queue->index;
4752 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4754 case RTE_FLOW_ACTION_TYPE_RSS:
4755 rss = actions->conf;
4757 memcpy((*flow->queue), rss->queue,
4758 rss->queue_num * sizeof(uint16_t));
4759 flow->rss.queue_num = rss->queue_num;
4760 /* NULL RSS key indicates default RSS key. */
4761 rss_key = !rss->key ? rss_hash_default_key : rss->key;
4762 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
4763 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
4764 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
4765 flow->rss.level = rss->level;
4766 action_flags |= MLX5_FLOW_ACTION_RSS;
4768 case RTE_FLOW_ACTION_TYPE_COUNT:
4769 if (!priv->config.devx) {
4770 rte_errno = ENOTSUP;
4773 flow->counter = flow_dv_counter_alloc(dev,
4777 if (flow->counter == NULL)
4779 dev_flow->dv.actions[actions_n++] =
4780 flow->counter->action;
4781 action_flags |= MLX5_FLOW_ACTION_COUNT;
4784 if (rte_errno == ENOTSUP)
4785 return rte_flow_error_set
4787 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4789 "count action not supported");
4791 return rte_flow_error_set
4793 RTE_FLOW_ERROR_TYPE_ACTION,
4795 "cannot create counter"
4797 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4798 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4799 if (flow_dv_create_action_l2_encap(dev, actions,
4804 dev_flow->dv.actions[actions_n++] =
4805 dev_flow->dv.encap_decap->verbs_action;
4806 action_flags |= actions->type ==
4807 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4808 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4809 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4811 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4812 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4813 if (flow_dv_create_action_l2_decap(dev, dev_flow,
4817 dev_flow->dv.actions[actions_n++] =
4818 dev_flow->dv.encap_decap->verbs_action;
4819 action_flags |= actions->type ==
4820 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4821 MLX5_FLOW_ACTION_VXLAN_DECAP :
4822 MLX5_FLOW_ACTION_NVGRE_DECAP;
4824 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4825 /* Handle encap with preceding decap. */
4826 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
4827 if (flow_dv_create_action_raw_encap
4828 (dev, actions, dev_flow, attr, error))
4830 dev_flow->dv.actions[actions_n++] =
4831 dev_flow->dv.encap_decap->verbs_action;
4833 /* Handle encap without preceding decap. */
4834 if (flow_dv_create_action_l2_encap
4835 (dev, actions, dev_flow, attr->transfer,
4838 dev_flow->dv.actions[actions_n++] =
4839 dev_flow->dv.encap_decap->verbs_action;
4841 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4843 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4844 /* Check if this decap is followed by encap. */
4845 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
4846 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
4849 /* Handle decap only if it isn't followed by encap. */
4850 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4851 if (flow_dv_create_action_l2_decap
4852 (dev, dev_flow, attr->transfer, error))
4854 dev_flow->dv.actions[actions_n++] =
4855 dev_flow->dv.encap_decap->verbs_action;
4857 /* If decap is followed by encap, handle it at encap. */
4858 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4860 case RTE_FLOW_ACTION_TYPE_JUMP:
4861 jump_data = action->conf;
4862 tbl = flow_dv_tbl_resource_get(dev, jump_data->group *
4865 attr->transfer, error);
4867 return rte_flow_error_set
4869 RTE_FLOW_ERROR_TYPE_ACTION,
4871 "cannot create jump action.");
4872 jump_tbl_resource.tbl = tbl;
4873 if (flow_dv_jump_tbl_resource_register
4874 (dev, &jump_tbl_resource, dev_flow, error)) {
4875 flow_dv_tbl_resource_release(tbl);
4876 return rte_flow_error_set
4878 RTE_FLOW_ERROR_TYPE_ACTION,
4880 "cannot create jump action.");
4882 dev_flow->dv.actions[actions_n++] =
4883 dev_flow->dv.jump->action;
4884 action_flags |= MLX5_FLOW_ACTION_JUMP;
4886 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4887 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4888 if (flow_dv_convert_action_modify_mac(&res, actions,
4891 action_flags |= actions->type ==
4892 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4893 MLX5_FLOW_ACTION_SET_MAC_SRC :
4894 MLX5_FLOW_ACTION_SET_MAC_DST;
4896 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4897 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4898 if (flow_dv_convert_action_modify_ipv4(&res, actions,
4901 action_flags |= actions->type ==
4902 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4903 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4904 MLX5_FLOW_ACTION_SET_IPV4_DST;
4906 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4907 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4908 if (flow_dv_convert_action_modify_ipv6(&res, actions,
4911 action_flags |= actions->type ==
4912 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4913 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4914 MLX5_FLOW_ACTION_SET_IPV6_DST;
4916 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4917 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4918 if (flow_dv_convert_action_modify_tp(&res, actions,
4922 action_flags |= actions->type ==
4923 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4924 MLX5_FLOW_ACTION_SET_TP_SRC :
4925 MLX5_FLOW_ACTION_SET_TP_DST;
4927 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4928 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
4932 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
4934 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4935 if (flow_dv_convert_action_modify_ttl(&res, actions,
4939 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
4941 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4942 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4943 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
4946 action_flags |= actions->type ==
4947 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4948 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4949 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4952 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4953 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4954 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
4957 action_flags |= actions->type ==
4958 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4959 MLX5_FLOW_ACTION_INC_TCP_ACK :
4960 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4962 case RTE_FLOW_ACTION_TYPE_END:
4964 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
4965 /* create modify action if needed. */
4966 if (flow_dv_modify_hdr_resource_register
4971 dev_flow->dv.actions[modify_action_position] =
4972 dev_flow->dv.modify_hdr->verbs_action;
4978 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
4979 modify_action_position == UINT32_MAX)
4980 modify_action_position = actions_n++;
4982 dev_flow->dv.actions_n = actions_n;
4983 flow->actions = action_flags;
4984 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4985 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4987 switch (items->type) {
4988 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4989 flow_dv_translate_item_port_id(dev, match_mask,
4990 match_value, items);
4991 last_item = MLX5_FLOW_ITEM_PORT_ID;
4993 case RTE_FLOW_ITEM_TYPE_ETH:
4994 flow_dv_translate_item_eth(match_mask, match_value,
4996 matcher.priority = MLX5_PRIORITY_MAP_L2;
4997 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4998 MLX5_FLOW_LAYER_OUTER_L2;
5000 case RTE_FLOW_ITEM_TYPE_VLAN:
5001 flow_dv_translate_item_vlan(match_mask, match_value,
5003 matcher.priority = MLX5_PRIORITY_MAP_L2;
5004 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
5005 MLX5_FLOW_LAYER_INNER_VLAN) :
5006 (MLX5_FLOW_LAYER_OUTER_L2 |
5007 MLX5_FLOW_LAYER_OUTER_VLAN);
5009 case RTE_FLOW_ITEM_TYPE_IPV4:
5010 flow_dv_translate_item_ipv4(match_mask, match_value,
5011 items, tunnel, attr->group);
5012 matcher.priority = MLX5_PRIORITY_MAP_L3;
5013 dev_flow->dv.hash_fields |=
5014 mlx5_flow_hashfields_adjust
5016 MLX5_IPV4_LAYER_TYPES,
5017 MLX5_IPV4_IBV_RX_HASH);
5018 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5019 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5020 mlx5_flow_tunnel_ip_check(items, &last_item);
5022 case RTE_FLOW_ITEM_TYPE_IPV6:
5023 flow_dv_translate_item_ipv6(match_mask, match_value,
5024 items, tunnel, attr->group);
5025 matcher.priority = MLX5_PRIORITY_MAP_L3;
5026 dev_flow->dv.hash_fields |=
5027 mlx5_flow_hashfields_adjust
5029 MLX5_IPV6_LAYER_TYPES,
5030 MLX5_IPV6_IBV_RX_HASH);
5031 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5032 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5033 mlx5_flow_tunnel_ip_check(items, &last_item);
5035 case RTE_FLOW_ITEM_TYPE_TCP:
5036 flow_dv_translate_item_tcp(match_mask, match_value,
5038 matcher.priority = MLX5_PRIORITY_MAP_L4;
5039 dev_flow->dv.hash_fields |=
5040 mlx5_flow_hashfields_adjust
5041 (dev_flow, tunnel, ETH_RSS_TCP,
5042 IBV_RX_HASH_SRC_PORT_TCP |
5043 IBV_RX_HASH_DST_PORT_TCP);
5044 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5045 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5047 case RTE_FLOW_ITEM_TYPE_UDP:
5048 flow_dv_translate_item_udp(match_mask, match_value,
5050 matcher.priority = MLX5_PRIORITY_MAP_L4;
5051 dev_flow->dv.hash_fields |=
5052 mlx5_flow_hashfields_adjust
5053 (dev_flow, tunnel, ETH_RSS_UDP,
5054 IBV_RX_HASH_SRC_PORT_UDP |
5055 IBV_RX_HASH_DST_PORT_UDP);
5056 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5057 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5059 case RTE_FLOW_ITEM_TYPE_GRE:
5060 flow_dv_translate_item_gre(match_mask, match_value,
5062 last_item = MLX5_FLOW_LAYER_GRE;
5064 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5065 flow_dv_translate_item_gre_key(match_mask,
5066 match_value, items);
5067 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5069 case RTE_FLOW_ITEM_TYPE_NVGRE:
5070 flow_dv_translate_item_nvgre(match_mask, match_value,
5072 last_item = MLX5_FLOW_LAYER_GRE;
5074 case RTE_FLOW_ITEM_TYPE_VXLAN:
5075 flow_dv_translate_item_vxlan(match_mask, match_value,
5077 last_item = MLX5_FLOW_LAYER_VXLAN;
5079 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5080 flow_dv_translate_item_vxlan(match_mask, match_value,
5082 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5084 case RTE_FLOW_ITEM_TYPE_MPLS:
5085 flow_dv_translate_item_mpls(match_mask, match_value,
5086 items, last_item, tunnel);
5087 last_item = MLX5_FLOW_LAYER_MPLS;
5089 case RTE_FLOW_ITEM_TYPE_META:
5090 flow_dv_translate_item_meta(match_mask, match_value,
5092 last_item = MLX5_FLOW_ITEM_METADATA;
5094 case RTE_FLOW_ITEM_TYPE_ICMP:
5095 flow_dv_translate_item_icmp(match_mask, match_value,
5097 last_item = MLX5_FLOW_LAYER_ICMP;
5099 case RTE_FLOW_ITEM_TYPE_ICMP6:
5100 flow_dv_translate_item_icmp6(match_mask, match_value,
5102 last_item = MLX5_FLOW_LAYER_ICMP6;
5107 item_flags |= last_item;
5110 * In case of ingress traffic when E-Switch mode is enabled,
5111 * we have two cases where we need to set the source port manually.
5112 * The first one, is in case of Nic steering rule, and the second is
5113 * E-Switch rule where no port_id item was found. In both cases
5114 * the source port is set according the current port in use.
5116 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
5117 (priv->representor || priv->master)) {
5118 if (flow_dv_translate_item_port_id(dev, match_mask,
5122 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
5123 dev_flow->dv.value.buf));
5124 dev_flow->layers = item_flags;
5125 /* Register matcher. */
5126 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
5128 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
5130 matcher.egress = attr->egress;
5131 matcher.group = attr->group;
5132 matcher.transfer = attr->transfer;
5133 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
5139 * Apply the flow to the NIC.
5142 * Pointer to the Ethernet device structure.
5143 * @param[in, out] flow
5144 * Pointer to flow structure.
5146 * Pointer to error structure.
5149 * 0 on success, a negative errno value otherwise and rte_errno is set.
5152 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
5153 struct rte_flow_error *error)
5155 struct mlx5_flow_dv *dv;
5156 struct mlx5_flow *dev_flow;
5157 struct mlx5_priv *priv = dev->data->dev_private;
5161 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5164 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
5165 if (flow->transfer) {
5166 dv->actions[n++] = priv->sh->esw_drop_action;
5168 dv->hrxq = mlx5_hrxq_drop_new(dev);
5172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5174 "cannot get drop hash queue");
5177 dv->actions[n++] = dv->hrxq->action;
5179 } else if (flow->actions &
5180 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
5181 struct mlx5_hrxq *hrxq;
5183 hrxq = mlx5_hrxq_get(dev, flow->key,
5184 MLX5_RSS_HASH_KEY_LEN,
5187 flow->rss.queue_num);
5191 if (mlx5_lro_on(dev)) {
5192 if ((dev_flow->layers &
5193 MLX5_FLOW_LAYER_IPV4_LRO)
5194 == MLX5_FLOW_LAYER_IPV4_LRO)
5195 lro = MLX5_FLOW_IPV4_LRO;
5196 else if ((dev_flow->layers &
5197 MLX5_FLOW_LAYER_IPV6_LRO)
5198 == MLX5_FLOW_LAYER_IPV6_LRO)
5199 lro = MLX5_FLOW_IPV6_LRO;
5201 hrxq = mlx5_hrxq_new
5202 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
5203 dv->hash_fields, (*flow->queue),
5204 flow->rss.queue_num,
5205 !!(dev_flow->layers &
5206 MLX5_FLOW_LAYER_TUNNEL), lro);
5212 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5213 "cannot get hash queue");
5217 dv->actions[n++] = dv->hrxq->action;
5220 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
5221 (void *)&dv->value, n,
5224 rte_flow_error_set(error, errno,
5225 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5227 "hardware refuses to create flow");
5233 err = rte_errno; /* Save rte_errno before cleanup. */
5234 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5235 struct mlx5_flow_dv *dv = &dev_flow->dv;
5237 if (flow->actions & MLX5_FLOW_ACTION_DROP)
5238 mlx5_hrxq_drop_release(dev);
5240 mlx5_hrxq_release(dev, dv->hrxq);
5244 rte_errno = err; /* Restore rte_errno. */
5249 * Release the flow matcher.
5252 * Pointer to Ethernet device.
5254 * Pointer to mlx5_flow.
5257 * 1 while a reference on it exists, 0 when freed.
5260 flow_dv_matcher_release(struct rte_eth_dev *dev,
5261 struct mlx5_flow *flow)
5263 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
5264 struct mlx5_priv *priv = dev->data->dev_private;
5265 struct mlx5_ibv_shared *sh = priv->sh;
5266 struct mlx5_flow_tbl_resource *tbl;
5268 assert(matcher->matcher_object);
5269 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
5270 dev->data->port_id, (void *)matcher,
5271 rte_atomic32_read(&matcher->refcnt));
5272 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
5273 claim_zero(mlx5_glue->dv_destroy_flow_matcher
5274 (matcher->matcher_object));
5275 LIST_REMOVE(matcher, next);
5276 if (matcher->egress)
5277 tbl = &sh->tx_tbl[matcher->group];
5279 tbl = &sh->rx_tbl[matcher->group];
5280 flow_dv_tbl_resource_release(tbl);
5282 DRV_LOG(DEBUG, "port %u matcher %p: removed",
5283 dev->data->port_id, (void *)matcher);
5290 * Release an encap/decap resource.
5293 * Pointer to mlx5_flow.
5296 * 1 while a reference on it exists, 0 when freed.
5299 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
5301 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
5302 flow->dv.encap_decap;
5304 assert(cache_resource->verbs_action);
5305 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
5306 (void *)cache_resource,
5307 rte_atomic32_read(&cache_resource->refcnt));
5308 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5309 claim_zero(mlx5_glue->destroy_flow_action
5310 (cache_resource->verbs_action));
5311 LIST_REMOVE(cache_resource, next);
5312 rte_free(cache_resource);
5313 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
5314 (void *)cache_resource);
5321 * Release an jump to table action resource.
5324 * Pointer to mlx5_flow.
5327 * 1 while a reference on it exists, 0 when freed.
5330 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
5332 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
5335 assert(cache_resource->action);
5336 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
5337 (void *)cache_resource,
5338 rte_atomic32_read(&cache_resource->refcnt));
5339 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5340 claim_zero(mlx5_glue->destroy_flow_action
5341 (cache_resource->action));
5342 LIST_REMOVE(cache_resource, next);
5343 flow_dv_tbl_resource_release(cache_resource->tbl);
5344 rte_free(cache_resource);
5345 DRV_LOG(DEBUG, "jump table resource %p: removed",
5346 (void *)cache_resource);
5353 * Release a modify-header resource.
5356 * Pointer to mlx5_flow.
5359 * 1 while a reference on it exists, 0 when freed.
5362 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
5364 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
5365 flow->dv.modify_hdr;
5367 assert(cache_resource->verbs_action);
5368 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
5369 (void *)cache_resource,
5370 rte_atomic32_read(&cache_resource->refcnt));
5371 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5372 claim_zero(mlx5_glue->destroy_flow_action
5373 (cache_resource->verbs_action));
5374 LIST_REMOVE(cache_resource, next);
5375 rte_free(cache_resource);
5376 DRV_LOG(DEBUG, "modify-header resource %p: removed",
5377 (void *)cache_resource);
5384 * Release port ID action resource.
5387 * Pointer to mlx5_flow.
5390 * 1 while a reference on it exists, 0 when freed.
5393 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
5395 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
5396 flow->dv.port_id_action;
5398 assert(cache_resource->action);
5399 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
5400 (void *)cache_resource,
5401 rte_atomic32_read(&cache_resource->refcnt));
5402 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
5403 claim_zero(mlx5_glue->destroy_flow_action
5404 (cache_resource->action));
5405 LIST_REMOVE(cache_resource, next);
5406 rte_free(cache_resource);
5407 DRV_LOG(DEBUG, "port id action resource %p: removed",
5408 (void *)cache_resource);
5415 * Remove the flow from the NIC but keeps it in memory.
5418 * Pointer to Ethernet device.
5419 * @param[in, out] flow
5420 * Pointer to flow structure.
5423 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
5425 struct mlx5_flow_dv *dv;
5426 struct mlx5_flow *dev_flow;
5430 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5433 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
5437 if (flow->actions & MLX5_FLOW_ACTION_DROP)
5438 mlx5_hrxq_drop_release(dev);
5440 mlx5_hrxq_release(dev, dv->hrxq);
5447 * Remove the flow from the NIC and the memory.
5450 * Pointer to the Ethernet device structure.
5451 * @param[in, out] flow
5452 * Pointer to flow structure.
5455 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
5457 struct mlx5_flow *dev_flow;
5461 flow_dv_remove(dev, flow);
5462 if (flow->counter) {
5463 flow_dv_counter_release(dev, flow->counter);
5464 flow->counter = NULL;
5466 if (flow->tag_resource) {
5467 flow_dv_tag_release(dev, flow->tag_resource);
5468 flow->tag_resource = NULL;
5470 while (!LIST_EMPTY(&flow->dev_flows)) {
5471 dev_flow = LIST_FIRST(&flow->dev_flows);
5472 LIST_REMOVE(dev_flow, next);
5473 if (dev_flow->dv.matcher)
5474 flow_dv_matcher_release(dev, dev_flow);
5475 if (dev_flow->dv.encap_decap)
5476 flow_dv_encap_decap_resource_release(dev_flow);
5477 if (dev_flow->dv.modify_hdr)
5478 flow_dv_modify_hdr_resource_release(dev_flow);
5479 if (dev_flow->dv.jump)
5480 flow_dv_jump_tbl_resource_release(dev_flow);
5481 if (dev_flow->dv.port_id_action)
5482 flow_dv_port_id_action_resource_release(dev_flow);
5488 * Query a dv flow rule for its statistics via devx.
5491 * Pointer to Ethernet device.
5493 * Pointer to the sub flow.
5495 * data retrieved by the query.
5497 * Perform verbose error reporting if not NULL.
5500 * 0 on success, a negative errno value otherwise and rte_errno is set.
5503 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
5504 void *data, struct rte_flow_error *error)
5506 struct mlx5_priv *priv = dev->data->dev_private;
5507 struct rte_flow_query_count *qc = data;
5509 if (!priv->config.devx)
5510 return rte_flow_error_set(error, ENOTSUP,
5511 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5513 "counters are not supported");
5514 if (flow->counter) {
5515 uint64_t pkts, bytes;
5516 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
5520 return rte_flow_error_set(error, -err,
5521 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5522 NULL, "cannot read counters");
5525 qc->hits = pkts - flow->counter->hits;
5526 qc->bytes = bytes - flow->counter->bytes;
5528 flow->counter->hits = pkts;
5529 flow->counter->bytes = bytes;
5533 return rte_flow_error_set(error, EINVAL,
5534 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5536 "counters are not available");
5542 * @see rte_flow_query()
5546 flow_dv_query(struct rte_eth_dev *dev,
5547 struct rte_flow *flow __rte_unused,
5548 const struct rte_flow_action *actions __rte_unused,
5549 void *data __rte_unused,
5550 struct rte_flow_error *error __rte_unused)
5554 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5555 switch (actions->type) {
5556 case RTE_FLOW_ACTION_TYPE_VOID:
5558 case RTE_FLOW_ACTION_TYPE_COUNT:
5559 ret = flow_dv_query_count(dev, flow, data, error);
5562 return rte_flow_error_set(error, ENOTSUP,
5563 RTE_FLOW_ERROR_TYPE_ACTION,
5565 "action not supported");
5572 * Mutex-protected thunk to flow_dv_translate().
5575 flow_d_translate(struct rte_eth_dev *dev,
5576 struct mlx5_flow *dev_flow,
5577 const struct rte_flow_attr *attr,
5578 const struct rte_flow_item items[],
5579 const struct rte_flow_action actions[],
5580 struct rte_flow_error *error)
5584 flow_d_shared_lock(dev);
5585 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
5586 flow_d_shared_unlock(dev);
5591 * Mutex-protected thunk to flow_dv_apply().
5594 flow_d_apply(struct rte_eth_dev *dev,
5595 struct rte_flow *flow,
5596 struct rte_flow_error *error)
5600 flow_d_shared_lock(dev);
5601 ret = flow_dv_apply(dev, flow, error);
5602 flow_d_shared_unlock(dev);
5607 * Mutex-protected thunk to flow_dv_remove().
5610 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
5612 flow_d_shared_lock(dev);
5613 flow_dv_remove(dev, flow);
5614 flow_d_shared_unlock(dev);
5618 * Mutex-protected thunk to flow_dv_destroy().
5621 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
5623 flow_d_shared_lock(dev);
5624 flow_dv_destroy(dev, flow);
5625 flow_d_shared_unlock(dev);
5628 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
5629 .validate = flow_dv_validate,
5630 .prepare = flow_dv_prepare,
5631 .translate = flow_d_translate,
5632 .apply = flow_d_apply,
5633 .remove = flow_d_remove,
5634 .destroy = flow_d_destroy,
5635 .query = flow_dv_query,
5638 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */