drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static void
1329 mlx5_flow_field_id_to_modify_info
1330                 (const struct rte_flow_action_modify_data *data,
1331                  struct field_modify_info *info,
1332                  uint32_t *mask, uint32_t *value, uint32_t width,
1333                  struct rte_eth_dev *dev,
1334                  const struct rte_flow_attr *attr,
1335                  struct rte_flow_error *error)
1336 {
1337         uint32_t idx = 0;
1338         switch (data->field) {
1339         case RTE_FLOW_FIELD_START:
1340                 /* not supported yet */
1341                 MLX5_ASSERT(false);
1342                 break;
1343         case RTE_FLOW_FIELD_MAC_DST:
1344                 if (mask) {
1345                         if (data->offset < 32) {
1346                                 info[idx] = (struct field_modify_info){4, 0,
1347                                                 MLX5_MODI_OUT_DMAC_47_16};
1348                                 if (width < 32) {
1349                                         mask[idx] =
1350                                                 rte_cpu_to_be_32(0xffffffff >>
1351                                                                  (32 - width));
1352                                         width = 0;
1353                                 } else {
1354                                         mask[idx] = RTE_BE32(0xffffffff);
1355                                         width -= 32;
1356                                 }
1357                                 if (!width)
1358                                         break;
1359                                 ++idx;
1360                         }
1361                         info[idx] = (struct field_modify_info){2, 4 * idx,
1362                                                 MLX5_MODI_OUT_DMAC_15_0};
1363                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1364                 } else {
1365                         if (data->offset < 32)
1366                                 info[idx++] = (struct field_modify_info){4, 0,
1367                                                 MLX5_MODI_OUT_DMAC_47_16};
1368                         info[idx] = (struct field_modify_info){2, 0,
1369                                                 MLX5_MODI_OUT_DMAC_15_0};
1370                 }
1371                 break;
1372         case RTE_FLOW_FIELD_MAC_SRC:
1373                 if (mask) {
1374                         if (data->offset < 32) {
1375                                 info[idx] = (struct field_modify_info){4, 0,
1376                                                 MLX5_MODI_OUT_SMAC_47_16};
1377                                 if (width < 32) {
1378                                         mask[idx] =
1379                                                 rte_cpu_to_be_32(0xffffffff >>
1380                                                                 (32 - width));
1381                                         width = 0;
1382                                 } else {
1383                                         mask[idx] = RTE_BE32(0xffffffff);
1384                                         width -= 32;
1385                                 }
1386                                 if (!width)
1387                                         break;
1388                                 ++idx;
1389                         }
1390                         info[idx] = (struct field_modify_info){2, 4 * idx,
1391                                                 MLX5_MODI_OUT_SMAC_15_0};
1392                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1393                 } else {
1394                         if (data->offset < 32)
1395                                 info[idx++] = (struct field_modify_info){4, 0,
1396                                                 MLX5_MODI_OUT_SMAC_47_16};
1397                         info[idx] = (struct field_modify_info){2, 0,
1398                                                 MLX5_MODI_OUT_SMAC_15_0};
1399                 }
1400                 break;
1401         case RTE_FLOW_FIELD_VLAN_TYPE:
1402                 /* not supported yet */
1403                 break;
1404         case RTE_FLOW_FIELD_VLAN_ID:
1405                 info[idx] = (struct field_modify_info){2, 0,
1406                                         MLX5_MODI_OUT_FIRST_VID};
1407                 if (mask)
1408                         mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1409                 break;
1410         case RTE_FLOW_FIELD_MAC_TYPE:
1411                 info[idx] = (struct field_modify_info){2, 0,
1412                                         MLX5_MODI_OUT_ETHERTYPE};
1413                 if (mask)
1414                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1415                 break;
1416         case RTE_FLOW_FIELD_IPV4_DSCP:
1417                 info[idx] = (struct field_modify_info){1, 0,
1418                                         MLX5_MODI_OUT_IP_DSCP};
1419                 if (mask)
1420                         mask[idx] = 0x3f >> (6 - width);
1421                 break;
1422         case RTE_FLOW_FIELD_IPV4_TTL:
1423                 info[idx] = (struct field_modify_info){1, 0,
1424                                         MLX5_MODI_OUT_IPV4_TTL};
1425                 if (mask)
1426                         mask[idx] = 0xff >> (8 - width);
1427                 break;
1428         case RTE_FLOW_FIELD_IPV4_SRC:
1429                 info[idx] = (struct field_modify_info){4, 0,
1430                                         MLX5_MODI_OUT_SIPV4};
1431                 if (mask)
1432                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1433                                                      (32 - width));
1434                 break;
1435         case RTE_FLOW_FIELD_IPV4_DST:
1436                 info[idx] = (struct field_modify_info){4, 0,
1437                                         MLX5_MODI_OUT_DIPV4};
1438                 if (mask)
1439                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1440                                                      (32 - width));
1441                 break;
1442         case RTE_FLOW_FIELD_IPV6_DSCP:
1443                 info[idx] = (struct field_modify_info){1, 0,
1444                                         MLX5_MODI_OUT_IP_DSCP};
1445                 if (mask)
1446                         mask[idx] = 0x3f >> (6 - width);
1447                 break;
1448         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1449                 info[idx] = (struct field_modify_info){1, 0,
1450                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1451                 if (mask)
1452                         mask[idx] = 0xff >> (8 - width);
1453                 break;
1454         case RTE_FLOW_FIELD_IPV6_SRC:
1455                 if (mask) {
1456                         if (data->offset < 32) {
1457                                 info[idx] = (struct field_modify_info){4,
1458                                                 4 * idx,
1459                                                 MLX5_MODI_OUT_SIPV6_31_0};
1460                                 if (width < 32) {
1461                                         mask[idx] =
1462                                                 rte_cpu_to_be_32(0xffffffff >>
1463                                                                  (32 - width));
1464                                         width = 0;
1465                                 } else {
1466                                         mask[idx] = RTE_BE32(0xffffffff);
1467                                         width -= 32;
1468                                 }
1469                                 if (!width)
1470                                         break;
1471                                 ++idx;
1472                         }
1473                         if (data->offset < 64) {
1474                                 info[idx] = (struct field_modify_info){4,
1475                                                 4 * idx,
1476                                                 MLX5_MODI_OUT_SIPV6_63_32};
1477                                 if (width < 32) {
1478                                         mask[idx] =
1479                                                 rte_cpu_to_be_32(0xffffffff >>
1480                                                                  (32 - width));
1481                                         width = 0;
1482                                 } else {
1483                                         mask[idx] = RTE_BE32(0xffffffff);
1484                                         width -= 32;
1485                                 }
1486                                 if (!width)
1487                                         break;
1488                                 ++idx;
1489                         }
1490                         if (data->offset < 96) {
1491                                 info[idx] = (struct field_modify_info){4,
1492                                                 4 * idx,
1493                                                 MLX5_MODI_OUT_SIPV6_95_64};
1494                                 if (width < 32) {
1495                                         mask[idx] =
1496                                                 rte_cpu_to_be_32(0xffffffff >>
1497                                                                  (32 - width));
1498                                         width = 0;
1499                                 } else {
1500                                         mask[idx] = RTE_BE32(0xffffffff);
1501                                         width -= 32;
1502                                 }
1503                                 if (!width)
1504                                         break;
1505                                 ++idx;
1506                         }
1507                         info[idx] = (struct field_modify_info){4, 4 * idx,
1508                                                 MLX5_MODI_OUT_SIPV6_127_96};
1509                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1510                                                      (32 - width));
1511                 } else {
1512                         if (data->offset < 32)
1513                                 info[idx++] = (struct field_modify_info){4, 0,
1514                                                 MLX5_MODI_OUT_SIPV6_31_0};
1515                         if (data->offset < 64)
1516                                 info[idx++] = (struct field_modify_info){4, 0,
1517                                                 MLX5_MODI_OUT_SIPV6_63_32};
1518                         if (data->offset < 96)
1519                                 info[idx++] = (struct field_modify_info){4, 0,
1520                                                 MLX5_MODI_OUT_SIPV6_95_64};
1521                         if (data->offset < 128)
1522                                 info[idx++] = (struct field_modify_info){4, 0,
1523                                                 MLX5_MODI_OUT_SIPV6_127_96};
1524                 }
1525                 break;
1526         case RTE_FLOW_FIELD_IPV6_DST:
1527                 if (mask) {
1528                         if (data->offset < 32) {
1529                                 info[idx] = (struct field_modify_info){4,
1530                                                 4 * idx,
1531                                                 MLX5_MODI_OUT_DIPV6_31_0};
1532                                 if (width < 32) {
1533                                         mask[idx] =
1534                                                 rte_cpu_to_be_32(0xffffffff >>
1535                                                                  (32 - width));
1536                                         width = 0;
1537                                 } else {
1538                                         mask[idx] = RTE_BE32(0xffffffff);
1539                                         width -= 32;
1540                                 }
1541                                 if (!width)
1542                                         break;
1543                                 ++idx;
1544                         }
1545                         if (data->offset < 64) {
1546                                 info[idx] = (struct field_modify_info){4,
1547                                                 4 * idx,
1548                                                 MLX5_MODI_OUT_DIPV6_63_32};
1549                                 if (width < 32) {
1550                                         mask[idx] =
1551                                                 rte_cpu_to_be_32(0xffffffff >>
1552                                                                  (32 - width));
1553                                         width = 0;
1554                                 } else {
1555                                         mask[idx] = RTE_BE32(0xffffffff);
1556                                         width -= 32;
1557                                 }
1558                                 if (!width)
1559                                         break;
1560                                 ++idx;
1561                         }
1562                         if (data->offset < 96) {
1563                                 info[idx] = (struct field_modify_info){4,
1564                                                 4 * idx,
1565                                                 MLX5_MODI_OUT_DIPV6_95_64};
1566                                 if (width < 32) {
1567                                         mask[idx] =
1568                                                 rte_cpu_to_be_32(0xffffffff >>
1569                                                                  (32 - width));
1570                                         width = 0;
1571                                 } else {
1572                                         mask[idx] = RTE_BE32(0xffffffff);
1573                                         width -= 32;
1574                                 }
1575                                 if (!width)
1576                                         break;
1577                                 ++idx;
1578                         }
1579                         info[idx] = (struct field_modify_info){4, 4 * idx,
1580                                                 MLX5_MODI_OUT_DIPV6_127_96};
1581                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1582                                                      (32 - width));
1583                 } else {
1584                         if (data->offset < 32)
1585                                 info[idx++] = (struct field_modify_info){4, 0,
1586                                                 MLX5_MODI_OUT_DIPV6_31_0};
1587                         if (data->offset < 64)
1588                                 info[idx++] = (struct field_modify_info){4, 0,
1589                                                 MLX5_MODI_OUT_DIPV6_63_32};
1590                         if (data->offset < 96)
1591                                 info[idx++] = (struct field_modify_info){4, 0,
1592                                                 MLX5_MODI_OUT_DIPV6_95_64};
1593                         if (data->offset < 128)
1594                                 info[idx++] = (struct field_modify_info){4, 0,
1595                                                 MLX5_MODI_OUT_DIPV6_127_96};
1596                 }
1597                 break;
1598         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1599                 info[idx] = (struct field_modify_info){2, 0,
1600                                         MLX5_MODI_OUT_TCP_SPORT};
1601                 if (mask)
1602                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1603                 break;
1604         case RTE_FLOW_FIELD_TCP_PORT_DST:
1605                 info[idx] = (struct field_modify_info){2, 0,
1606                                         MLX5_MODI_OUT_TCP_DPORT};
1607                 if (mask)
1608                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1609                 break;
1610         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1611                 info[idx] = (struct field_modify_info){4, 0,
1612                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1613                 if (mask)
1614                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1615                                                      (32 - width));
1616                 break;
1617         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1618                 info[idx] = (struct field_modify_info){4, 0,
1619                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1620                 if (mask)
1621                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1622                                                      (32 - width));
1623                 break;
1624         case RTE_FLOW_FIELD_TCP_FLAGS:
1625                 info[idx] = (struct field_modify_info){1, 0,
1626                                         MLX5_MODI_OUT_TCP_FLAGS};
1627                 if (mask)
1628                         mask[idx] = 0x3f >> (6 - width);
1629                 break;
1630         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1631                 info[idx] = (struct field_modify_info){2, 0,
1632                                         MLX5_MODI_OUT_UDP_SPORT};
1633                 if (mask)
1634                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1635                 break;
1636         case RTE_FLOW_FIELD_UDP_PORT_DST:
1637                 info[idx] = (struct field_modify_info){2, 0,
1638                                         MLX5_MODI_OUT_UDP_DPORT};
1639                 if (mask)
1640                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1641                 break;
1642         case RTE_FLOW_FIELD_VXLAN_VNI:
1643                 /* not supported yet */
1644                 break;
1645         case RTE_FLOW_FIELD_GENEVE_VNI:
1646                 /* not supported yet*/
1647                 break;
1648         case RTE_FLOW_FIELD_GTP_TEID:
1649                 info[idx] = (struct field_modify_info){4, 0,
1650                                         MLX5_MODI_GTP_TEID};
1651                 if (mask)
1652                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1653                                                      (32 - width));
1654                 break;
1655         case RTE_FLOW_FIELD_TAG:
1656                 {
1657                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1658                                                    data->level, error);
1659                         if (reg < 0)
1660                                 return;
1661                         MLX5_ASSERT(reg != REG_NON);
1662                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1663                         info[idx] = (struct field_modify_info){4, 0,
1664                                                 reg_to_field[reg]};
1665                         if (mask)
1666                                 mask[idx] =
1667                                         rte_cpu_to_be_32(0xffffffff >>
1668                                                          (32 - width));
1669                 }
1670                 break;
1671         case RTE_FLOW_FIELD_MARK:
1672                 {
1673                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1674                                                        0, error);
1675                         if (reg < 0)
1676                                 return;
1677                         MLX5_ASSERT(reg != REG_NON);
1678                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1679                         info[idx] = (struct field_modify_info){4, 0,
1680                                                 reg_to_field[reg]};
1681                         if (mask)
1682                                 mask[idx] =
1683                                         rte_cpu_to_be_32(0xffffffff >>
1684                                                          (32 - width));
1685                 }
1686                 break;
1687         case RTE_FLOW_FIELD_META:
1688                 {
1689                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1690                         if (reg < 0)
1691                                 return;
1692                         MLX5_ASSERT(reg != REG_NON);
1693                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1694                         info[idx] = (struct field_modify_info){4, 0,
1695                                                 reg_to_field[reg]};
1696                         if (mask)
1697                                 mask[idx] =
1698                                         rte_cpu_to_be_32(0xffffffff >>
1699                                                          (32 - width));
1700                 }
1701                 break;
1702         case RTE_FLOW_FIELD_POINTER:
1703                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1704                         if (mask[idx]) {
1705                                 memcpy(&value[idx],
1706                                         (void *)(uintptr_t)data->value, 32);
1707                                 value[idx] = rte_cpu_to_be_32(value[idx]);
1708                                 break;
1709                         }
1710                 }
1711                 break;
1712         case RTE_FLOW_FIELD_VALUE:
1713                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1714                         if (mask[idx]) {
1715                                 value[idx] =
1716                                         rte_cpu_to_be_32((uint32_t)data->value);
1717                                 break;
1718                         }
1719                 }
1720                 break;
1721         default:
1722                 MLX5_ASSERT(false);
1723                 break;
1724         }
1725 }
1726
1727 /**
1728  * Convert modify_field action to DV specification.
1729  *
1730  * @param[in] dev
1731  *   Pointer to the rte_eth_dev structure.
1732  * @param[in,out] resource
1733  *   Pointer to the modify-header resource.
1734  * @param[in] action
1735  *   Pointer to action specification.
1736  * @param[in] attr
1737  *   Attributes of flow that includes this item.
1738  * @param[out] error
1739  *   Pointer to the error structure.
1740  *
1741  * @return
1742  *   0 on success, a negative errno value otherwise and rte_errno is set.
1743  */
1744 static int
1745 flow_dv_convert_action_modify_field
1746                         (struct rte_eth_dev *dev,
1747                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1748                          const struct rte_flow_action *action,
1749                          const struct rte_flow_attr *attr,
1750                          struct rte_flow_error *error)
1751 {
1752         const struct rte_flow_action_modify_field *conf =
1753                 (const struct rte_flow_action_modify_field *)(action->conf);
1754         struct rte_flow_item item;
1755         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1756                                                                 {0, 0, 0} };
1757         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1758                                                                 {0, 0, 0} };
1759         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1760         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1761         uint32_t type;
1762
1763         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1764                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1765                 type = MLX5_MODIFICATION_TYPE_SET;
1766                 /** For SET fill the destination field (field) first. */
1767                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1768                                           value, conf->width, dev, attr, error);
1769                 /** Then copy immediate value from source as per mask. */
1770                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1771                                           value, conf->width, dev, attr, error);
1772                 item.spec = &value;
1773         } else {
1774                 type = MLX5_MODIFICATION_TYPE_COPY;
1775                 /** For COPY fill the destination field (dcopy) without mask. */
1776                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1777                                           value, conf->width, dev, attr, error);
1778                 /** Then construct the source field (field) with mask. */
1779                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1780                                           value, conf->width, dev, attr, error);
1781         }
1782         item.mask = &mask;
1783         return flow_dv_convert_modify_action(&item,
1784                         field, dcopy, resource, type, error);
1785 }
1786
1787 /**
1788  * Validate MARK item.
1789  *
1790  * @param[in] dev
1791  *   Pointer to the rte_eth_dev structure.
1792  * @param[in] item
1793  *   Item specification.
1794  * @param[in] attr
1795  *   Attributes of flow that includes this item.
1796  * @param[out] error
1797  *   Pointer to error structure.
1798  *
1799  * @return
1800  *   0 on success, a negative errno value otherwise and rte_errno is set.
1801  */
1802 static int
1803 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1804                            const struct rte_flow_item *item,
1805                            const struct rte_flow_attr *attr __rte_unused,
1806                            struct rte_flow_error *error)
1807 {
1808         struct mlx5_priv *priv = dev->data->dev_private;
1809         struct mlx5_dev_config *config = &priv->config;
1810         const struct rte_flow_item_mark *spec = item->spec;
1811         const struct rte_flow_item_mark *mask = item->mask;
1812         const struct rte_flow_item_mark nic_mask = {
1813                 .id = priv->sh->dv_mark_mask,
1814         };
1815         int ret;
1816
1817         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1818                 return rte_flow_error_set(error, ENOTSUP,
1819                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1820                                           "extended metadata feature"
1821                                           " isn't enabled");
1822         if (!mlx5_flow_ext_mreg_supported(dev))
1823                 return rte_flow_error_set(error, ENOTSUP,
1824                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1825                                           "extended metadata register"
1826                                           " isn't supported");
1827         if (!nic_mask.id)
1828                 return rte_flow_error_set(error, ENOTSUP,
1829                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1830                                           "extended metadata register"
1831                                           " isn't available");
1832         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1833         if (ret < 0)
1834                 return ret;
1835         if (!spec)
1836                 return rte_flow_error_set(error, EINVAL,
1837                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1838                                           item->spec,
1839                                           "data cannot be empty");
1840         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1841                 return rte_flow_error_set(error, EINVAL,
1842                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1843                                           &spec->id,
1844                                           "mark id exceeds the limit");
1845         if (!mask)
1846                 mask = &nic_mask;
1847         if (!mask->id)
1848                 return rte_flow_error_set(error, EINVAL,
1849                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1850                                         "mask cannot be zero");
1851
1852         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1853                                         (const uint8_t *)&nic_mask,
1854                                         sizeof(struct rte_flow_item_mark),
1855                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1856         if (ret < 0)
1857                 return ret;
1858         return 0;
1859 }
1860
1861 /**
1862  * Validate META item.
1863  *
1864  * @param[in] dev
1865  *   Pointer to the rte_eth_dev structure.
1866  * @param[in] item
1867  *   Item specification.
1868  * @param[in] attr
1869  *   Attributes of flow that includes this item.
1870  * @param[out] error
1871  *   Pointer to error structure.
1872  *
1873  * @return
1874  *   0 on success, a negative errno value otherwise and rte_errno is set.
1875  */
1876 static int
1877 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1878                            const struct rte_flow_item *item,
1879                            const struct rte_flow_attr *attr,
1880                            struct rte_flow_error *error)
1881 {
1882         struct mlx5_priv *priv = dev->data->dev_private;
1883         struct mlx5_dev_config *config = &priv->config;
1884         const struct rte_flow_item_meta *spec = item->spec;
1885         const struct rte_flow_item_meta *mask = item->mask;
1886         struct rte_flow_item_meta nic_mask = {
1887                 .data = UINT32_MAX
1888         };
1889         int reg;
1890         int ret;
1891
1892         if (!spec)
1893                 return rte_flow_error_set(error, EINVAL,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1895                                           item->spec,
1896                                           "data cannot be empty");
1897         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1898                 if (!mlx5_flow_ext_mreg_supported(dev))
1899                         return rte_flow_error_set(error, ENOTSUP,
1900                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1901                                           "extended metadata register"
1902                                           " isn't supported");
1903                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1904                 if (reg < 0)
1905                         return reg;
1906                 if (reg == REG_NON)
1907                         return rte_flow_error_set(error, ENOTSUP,
1908                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1909                                         "unavalable extended metadata register");
1910                 if (reg == REG_B)
1911                         return rte_flow_error_set(error, ENOTSUP,
1912                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1913                                           "match on reg_b "
1914                                           "isn't supported");
1915                 if (reg != REG_A)
1916                         nic_mask.data = priv->sh->dv_meta_mask;
1917         } else {
1918                 if (attr->transfer)
1919                         return rte_flow_error_set(error, ENOTSUP,
1920                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1921                                         "extended metadata feature "
1922                                         "should be enabled when "
1923                                         "meta item is requested "
1924                                         "with e-switch mode ");
1925                 if (attr->ingress)
1926                         return rte_flow_error_set(error, ENOTSUP,
1927                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1928                                         "match on metadata for ingress "
1929                                         "is not supported in legacy "
1930                                         "metadata mode");
1931         }
1932         if (!mask)
1933                 mask = &rte_flow_item_meta_mask;
1934         if (!mask->data)
1935                 return rte_flow_error_set(error, EINVAL,
1936                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1937                                         "mask cannot be zero");
1938
1939         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1940                                         (const uint8_t *)&nic_mask,
1941                                         sizeof(struct rte_flow_item_meta),
1942                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1943         return ret;
1944 }
1945
1946 /**
1947  * Validate TAG item.
1948  *
1949  * @param[in] dev
1950  *   Pointer to the rte_eth_dev structure.
1951  * @param[in] item
1952  *   Item specification.
1953  * @param[in] attr
1954  *   Attributes of flow that includes this item.
1955  * @param[out] error
1956  *   Pointer to error structure.
1957  *
1958  * @return
1959  *   0 on success, a negative errno value otherwise and rte_errno is set.
1960  */
1961 static int
1962 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1963                           const struct rte_flow_item *item,
1964                           const struct rte_flow_attr *attr __rte_unused,
1965                           struct rte_flow_error *error)
1966 {
1967         const struct rte_flow_item_tag *spec = item->spec;
1968         const struct rte_flow_item_tag *mask = item->mask;
1969         const struct rte_flow_item_tag nic_mask = {
1970                 .data = RTE_BE32(UINT32_MAX),
1971                 .index = 0xff,
1972         };
1973         int ret;
1974
1975         if (!mlx5_flow_ext_mreg_supported(dev))
1976                 return rte_flow_error_set(error, ENOTSUP,
1977                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1978                                           "extensive metadata register"
1979                                           " isn't supported");
1980         if (!spec)
1981                 return rte_flow_error_set(error, EINVAL,
1982                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1983                                           item->spec,
1984                                           "data cannot be empty");
1985         if (!mask)
1986                 mask = &rte_flow_item_tag_mask;
1987         if (!mask->data)
1988                 return rte_flow_error_set(error, EINVAL,
1989                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1990                                         "mask cannot be zero");
1991
1992         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1993                                         (const uint8_t *)&nic_mask,
1994                                         sizeof(struct rte_flow_item_tag),
1995                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1996         if (ret < 0)
1997                 return ret;
1998         if (mask->index != 0xff)
1999                 return rte_flow_error_set(error, EINVAL,
2000                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2001                                           "partial mask for tag index"
2002                                           " is not supported");
2003         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2004         if (ret < 0)
2005                 return ret;
2006         MLX5_ASSERT(ret != REG_NON);
2007         return 0;
2008 }
2009
2010 /**
2011  * Validate vport item.
2012  *
2013  * @param[in] dev
2014  *   Pointer to the rte_eth_dev structure.
2015  * @param[in] item
2016  *   Item specification.
2017  * @param[in] attr
2018  *   Attributes of flow that includes this item.
2019  * @param[in] item_flags
2020  *   Bit-fields that holds the items detected until now.
2021  * @param[out] error
2022  *   Pointer to error structure.
2023  *
2024  * @return
2025  *   0 on success, a negative errno value otherwise and rte_errno is set.
2026  */
2027 static int
2028 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2029                               const struct rte_flow_item *item,
2030                               const struct rte_flow_attr *attr,
2031                               uint64_t item_flags,
2032                               struct rte_flow_error *error)
2033 {
2034         const struct rte_flow_item_port_id *spec = item->spec;
2035         const struct rte_flow_item_port_id *mask = item->mask;
2036         const struct rte_flow_item_port_id switch_mask = {
2037                         .id = 0xffffffff,
2038         };
2039         struct mlx5_priv *esw_priv;
2040         struct mlx5_priv *dev_priv;
2041         int ret;
2042
2043         if (!attr->transfer)
2044                 return rte_flow_error_set(error, EINVAL,
2045                                           RTE_FLOW_ERROR_TYPE_ITEM,
2046                                           NULL,
2047                                           "match on port id is valid only"
2048                                           " when transfer flag is enabled");
2049         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2050                 return rte_flow_error_set(error, ENOTSUP,
2051                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2052                                           "multiple source ports are not"
2053                                           " supported");
2054         if (!mask)
2055                 mask = &switch_mask;
2056         if (mask->id != 0xffffffff)
2057                 return rte_flow_error_set(error, ENOTSUP,
2058                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2059                                            mask,
2060                                            "no support for partial mask on"
2061                                            " \"id\" field");
2062         ret = mlx5_flow_item_acceptable
2063                                 (item, (const uint8_t *)mask,
2064                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2065                                  sizeof(struct rte_flow_item_port_id),
2066                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2067         if (ret)
2068                 return ret;
2069         if (!spec)
2070                 return 0;
2071         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2072         if (!esw_priv)
2073                 return rte_flow_error_set(error, rte_errno,
2074                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2075                                           "failed to obtain E-Switch info for"
2076                                           " port");
2077         dev_priv = mlx5_dev_to_eswitch_info(dev);
2078         if (!dev_priv)
2079                 return rte_flow_error_set(error, rte_errno,
2080                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2081                                           NULL,
2082                                           "failed to obtain E-Switch info");
2083         if (esw_priv->domain_id != dev_priv->domain_id)
2084                 return rte_flow_error_set(error, EINVAL,
2085                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2086                                           "cannot match on a port from a"
2087                                           " different E-Switch");
2088         return 0;
2089 }
2090
2091 /**
2092  * Validate VLAN item.
2093  *
2094  * @param[in] item
2095  *   Item specification.
2096  * @param[in] item_flags
2097  *   Bit-fields that holds the items detected until now.
2098  * @param[in] dev
2099  *   Ethernet device flow is being created on.
2100  * @param[out] error
2101  *   Pointer to error structure.
2102  *
2103  * @return
2104  *   0 on success, a negative errno value otherwise and rte_errno is set.
2105  */
2106 static int
2107 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2108                            uint64_t item_flags,
2109                            struct rte_eth_dev *dev,
2110                            struct rte_flow_error *error)
2111 {
2112         const struct rte_flow_item_vlan *mask = item->mask;
2113         const struct rte_flow_item_vlan nic_mask = {
2114                 .tci = RTE_BE16(UINT16_MAX),
2115                 .inner_type = RTE_BE16(UINT16_MAX),
2116                 .has_more_vlan = 1,
2117         };
2118         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2119         int ret;
2120         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2121                                         MLX5_FLOW_LAYER_INNER_L4) :
2122                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2123                                         MLX5_FLOW_LAYER_OUTER_L4);
2124         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2125                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2126
2127         if (item_flags & vlanm)
2128                 return rte_flow_error_set(error, EINVAL,
2129                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2130                                           "multiple VLAN layers not supported");
2131         else if ((item_flags & l34m) != 0)
2132                 return rte_flow_error_set(error, EINVAL,
2133                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2134                                           "VLAN cannot follow L3/L4 layer");
2135         if (!mask)
2136                 mask = &rte_flow_item_vlan_mask;
2137         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2138                                         (const uint8_t *)&nic_mask,
2139                                         sizeof(struct rte_flow_item_vlan),
2140                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2141         if (ret)
2142                 return ret;
2143         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2144                 struct mlx5_priv *priv = dev->data->dev_private;
2145
2146                 if (priv->vmwa_context) {
2147                         /*
2148                          * Non-NULL context means we have a virtual machine
2149                          * and SR-IOV enabled, we have to create VLAN interface
2150                          * to make hypervisor to setup E-Switch vport
2151                          * context correctly. We avoid creating the multiple
2152                          * VLAN interfaces, so we cannot support VLAN tag mask.
2153                          */
2154                         return rte_flow_error_set(error, EINVAL,
2155                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2156                                                   item,
2157                                                   "VLAN tag mask is not"
2158                                                   " supported in virtual"
2159                                                   " environment");
2160                 }
2161         }
2162         return 0;
2163 }
2164
2165 /*
2166  * GTP flags are contained in 1 byte of the format:
2167  * -------------------------------------------
2168  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2169  * |-----------------------------------------|
2170  * | value | Version | PT | Res | E | S | PN |
2171  * -------------------------------------------
2172  *
2173  * Matching is supported only for GTP flags E, S, PN.
2174  */
2175 #define MLX5_GTP_FLAGS_MASK     0x07
2176
2177 /**
2178  * Validate GTP item.
2179  *
2180  * @param[in] dev
2181  *   Pointer to the rte_eth_dev structure.
2182  * @param[in] item
2183  *   Item specification.
2184  * @param[in] item_flags
2185  *   Bit-fields that holds the items detected until now.
2186  * @param[out] error
2187  *   Pointer to error structure.
2188  *
2189  * @return
2190  *   0 on success, a negative errno value otherwise and rte_errno is set.
2191  */
2192 static int
2193 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2194                           const struct rte_flow_item *item,
2195                           uint64_t item_flags,
2196                           struct rte_flow_error *error)
2197 {
2198         struct mlx5_priv *priv = dev->data->dev_private;
2199         const struct rte_flow_item_gtp *spec = item->spec;
2200         const struct rte_flow_item_gtp *mask = item->mask;
2201         const struct rte_flow_item_gtp nic_mask = {
2202                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2203                 .msg_type = 0xff,
2204                 .teid = RTE_BE32(0xffffffff),
2205         };
2206
2207         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2208                 return rte_flow_error_set(error, ENOTSUP,
2209                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2210                                           "GTP support is not enabled");
2211         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2212                 return rte_flow_error_set(error, ENOTSUP,
2213                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2214                                           "multiple tunnel layers not"
2215                                           " supported");
2216         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2217                 return rte_flow_error_set(error, EINVAL,
2218                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2219                                           "no outer UDP layer found");
2220         if (!mask)
2221                 mask = &rte_flow_item_gtp_mask;
2222         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2223                 return rte_flow_error_set(error, ENOTSUP,
2224                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2225                                           "Match is supported for GTP"
2226                                           " flags only");
2227         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2228                                          (const uint8_t *)&nic_mask,
2229                                          sizeof(struct rte_flow_item_gtp),
2230                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2231 }
2232
2233 /**
2234  * Validate GTP PSC item.
2235  *
2236  * @param[in] item
2237  *   Item specification.
2238  * @param[in] last_item
2239  *   Previous validated item in the pattern items.
2240  * @param[in] gtp_item
2241  *   Previous GTP item specification.
2242  * @param[in] attr
2243  *   Pointer to flow attributes.
2244  * @param[out] error
2245  *   Pointer to error structure.
2246  *
2247  * @return
2248  *   0 on success, a negative errno value otherwise and rte_errno is set.
2249  */
2250 static int
2251 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2252                               uint64_t last_item,
2253                               const struct rte_flow_item *gtp_item,
2254                               const struct rte_flow_attr *attr,
2255                               struct rte_flow_error *error)
2256 {
2257         const struct rte_flow_item_gtp *gtp_spec;
2258         const struct rte_flow_item_gtp *gtp_mask;
2259         const struct rte_flow_item_gtp_psc *spec;
2260         const struct rte_flow_item_gtp_psc *mask;
2261         const struct rte_flow_item_gtp_psc nic_mask = {
2262                 .pdu_type = 0xFF,
2263                 .qfi = 0xFF,
2264         };
2265
2266         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2267                 return rte_flow_error_set
2268                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2269                          "GTP PSC item must be preceded with GTP item");
2270         gtp_spec = gtp_item->spec;
2271         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2272         /* GTP spec and E flag is requested to match zero. */
2273         if (gtp_spec &&
2274                 (gtp_mask->v_pt_rsv_flags &
2275                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2276                 return rte_flow_error_set
2277                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2278                          "GTP E flag must be 1 to match GTP PSC");
2279         /* Check the flow is not created in group zero. */
2280         if (!attr->transfer && !attr->group)
2281                 return rte_flow_error_set
2282                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2283                          "GTP PSC is not supported for group 0");
2284         /* GTP spec is here and E flag is requested to match zero. */
2285         if (!item->spec)
2286                 return 0;
2287         spec = item->spec;
2288         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2289         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2290                 return rte_flow_error_set
2291                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2292                          "PDU type should be smaller than 16");
2293         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2294                                          (const uint8_t *)&nic_mask,
2295                                          sizeof(struct rte_flow_item_gtp_psc),
2296                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2297 }
2298
2299 /**
2300  * Validate IPV4 item.
2301  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2302  * add specific validation of fragment_offset field,
2303  *
2304  * @param[in] item
2305  *   Item specification.
2306  * @param[in] item_flags
2307  *   Bit-fields that holds the items detected until now.
2308  * @param[out] error
2309  *   Pointer to error structure.
2310  *
2311  * @return
2312  *   0 on success, a negative errno value otherwise and rte_errno is set.
2313  */
2314 static int
2315 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2316                            uint64_t item_flags,
2317                            uint64_t last_item,
2318                            uint16_t ether_type,
2319                            struct rte_flow_error *error)
2320 {
2321         int ret;
2322         const struct rte_flow_item_ipv4 *spec = item->spec;
2323         const struct rte_flow_item_ipv4 *last = item->last;
2324         const struct rte_flow_item_ipv4 *mask = item->mask;
2325         rte_be16_t fragment_offset_spec = 0;
2326         rte_be16_t fragment_offset_last = 0;
2327         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2328                 .hdr = {
2329                         .src_addr = RTE_BE32(0xffffffff),
2330                         .dst_addr = RTE_BE32(0xffffffff),
2331                         .type_of_service = 0xff,
2332                         .fragment_offset = RTE_BE16(0xffff),
2333                         .next_proto_id = 0xff,
2334                         .time_to_live = 0xff,
2335                 },
2336         };
2337
2338         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2339                                            ether_type, &nic_ipv4_mask,
2340                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2341         if (ret < 0)
2342                 return ret;
2343         if (spec && mask)
2344                 fragment_offset_spec = spec->hdr.fragment_offset &
2345                                        mask->hdr.fragment_offset;
2346         if (!fragment_offset_spec)
2347                 return 0;
2348         /*
2349          * spec and mask are valid, enforce using full mask to make sure the
2350          * complete value is used correctly.
2351          */
2352         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2353                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2354                 return rte_flow_error_set(error, EINVAL,
2355                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2356                                           item, "must use full mask for"
2357                                           " fragment_offset");
2358         /*
2359          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2360          * indicating this is 1st fragment of fragmented packet.
2361          * This is not yet supported in MLX5, return appropriate error message.
2362          */
2363         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2364                 return rte_flow_error_set(error, ENOTSUP,
2365                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2366                                           "match on first fragment not "
2367                                           "supported");
2368         if (fragment_offset_spec && !last)
2369                 return rte_flow_error_set(error, ENOTSUP,
2370                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2371                                           "specified value not supported");
2372         /* spec and last are valid, validate the specified range. */
2373         fragment_offset_last = last->hdr.fragment_offset &
2374                                mask->hdr.fragment_offset;
2375         /*
2376          * Match on fragment_offset spec 0x2001 and last 0x3fff
2377          * means MF is 1 and frag-offset is > 0.
2378          * This packet is fragment 2nd and onward, excluding last.
2379          * This is not yet supported in MLX5, return appropriate
2380          * error message.
2381          */
2382         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2383             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2384                 return rte_flow_error_set(error, ENOTSUP,
2385                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2386                                           last, "match on following "
2387                                           "fragments not supported");
2388         /*
2389          * Match on fragment_offset spec 0x0001 and last 0x1fff
2390          * means MF is 0 and frag-offset is > 0.
2391          * This packet is last fragment of fragmented packet.
2392          * This is not yet supported in MLX5, return appropriate
2393          * error message.
2394          */
2395         if (fragment_offset_spec == RTE_BE16(1) &&
2396             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2397                 return rte_flow_error_set(error, ENOTSUP,
2398                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2399                                           last, "match on last "
2400                                           "fragment not supported");
2401         /*
2402          * Match on fragment_offset spec 0x0001 and last 0x3fff
2403          * means MF and/or frag-offset is not 0.
2404          * This is a fragmented packet.
2405          * Other range values are invalid and rejected.
2406          */
2407         if (!(fragment_offset_spec == RTE_BE16(1) &&
2408               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2409                 return rte_flow_error_set(error, ENOTSUP,
2410                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2411                                           "specified range not supported");
2412         return 0;
2413 }
2414
2415 /**
2416  * Validate IPV6 fragment extension item.
2417  *
2418  * @param[in] item
2419  *   Item specification.
2420  * @param[in] item_flags
2421  *   Bit-fields that holds the items detected until now.
2422  * @param[out] error
2423  *   Pointer to error structure.
2424  *
2425  * @return
2426  *   0 on success, a negative errno value otherwise and rte_errno is set.
2427  */
2428 static int
2429 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2430                                     uint64_t item_flags,
2431                                     struct rte_flow_error *error)
2432 {
2433         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2434         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2435         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2436         rte_be16_t frag_data_spec = 0;
2437         rte_be16_t frag_data_last = 0;
2438         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2439         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2440                                       MLX5_FLOW_LAYER_OUTER_L4;
2441         int ret = 0;
2442         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2443                 .hdr = {
2444                         .next_header = 0xff,
2445                         .frag_data = RTE_BE16(0xffff),
2446                 },
2447         };
2448
2449         if (item_flags & l4m)
2450                 return rte_flow_error_set(error, EINVAL,
2451                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2452                                           "ipv6 fragment extension item cannot "
2453                                           "follow L4 item.");
2454         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2455             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2456                 return rte_flow_error_set(error, EINVAL,
2457                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2458                                           "ipv6 fragment extension item must "
2459                                           "follow ipv6 item");
2460         if (spec && mask)
2461                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2462         if (!frag_data_spec)
2463                 return 0;
2464         /*
2465          * spec and mask are valid, enforce using full mask to make sure the
2466          * complete value is used correctly.
2467          */
2468         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2469                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2470                 return rte_flow_error_set(error, EINVAL,
2471                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2472                                           item, "must use full mask for"
2473                                           " frag_data");
2474         /*
2475          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2476          * This is 1st fragment of fragmented packet.
2477          */
2478         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2479                 return rte_flow_error_set(error, ENOTSUP,
2480                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2481                                           "match on first fragment not "
2482                                           "supported");
2483         if (frag_data_spec && !last)
2484                 return rte_flow_error_set(error, EINVAL,
2485                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2486                                           "specified value not supported");
2487         ret = mlx5_flow_item_acceptable
2488                                 (item, (const uint8_t *)mask,
2489                                  (const uint8_t *)&nic_mask,
2490                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2491                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2492         if (ret)
2493                 return ret;
2494         /* spec and last are valid, validate the specified range. */
2495         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2496         /*
2497          * Match on frag_data spec 0x0009 and last 0xfff9
2498          * means M is 1 and frag-offset is > 0.
2499          * This packet is fragment 2nd and onward, excluding last.
2500          * This is not yet supported in MLX5, return appropriate
2501          * error message.
2502          */
2503         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2504                                        RTE_IPV6_EHDR_MF_MASK) &&
2505             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2506                 return rte_flow_error_set(error, ENOTSUP,
2507                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2508                                           last, "match on following "
2509                                           "fragments not supported");
2510         /*
2511          * Match on frag_data spec 0x0008 and last 0xfff8
2512          * means M is 0 and frag-offset is > 0.
2513          * This packet is last fragment of fragmented packet.
2514          * This is not yet supported in MLX5, return appropriate
2515          * error message.
2516          */
2517         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2518             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2519                 return rte_flow_error_set(error, ENOTSUP,
2520                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2521                                           last, "match on last "
2522                                           "fragment not supported");
2523         /* Other range values are invalid and rejected. */
2524         return rte_flow_error_set(error, EINVAL,
2525                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2526                                   "specified range not supported");
2527 }
2528
2529 /**
2530  * Validate the pop VLAN action.
2531  *
2532  * @param[in] dev
2533  *   Pointer to the rte_eth_dev structure.
2534  * @param[in] action_flags
2535  *   Holds the actions detected until now.
2536  * @param[in] action
2537  *   Pointer to the pop vlan action.
2538  * @param[in] item_flags
2539  *   The items found in this flow rule.
2540  * @param[in] attr
2541  *   Pointer to flow attributes.
2542  * @param[out] error
2543  *   Pointer to error structure.
2544  *
2545  * @return
2546  *   0 on success, a negative errno value otherwise and rte_errno is set.
2547  */
2548 static int
2549 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2550                                  uint64_t action_flags,
2551                                  const struct rte_flow_action *action,
2552                                  uint64_t item_flags,
2553                                  const struct rte_flow_attr *attr,
2554                                  struct rte_flow_error *error)
2555 {
2556         const struct mlx5_priv *priv = dev->data->dev_private;
2557
2558         (void)action;
2559         (void)attr;
2560         if (!priv->sh->pop_vlan_action)
2561                 return rte_flow_error_set(error, ENOTSUP,
2562                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2563                                           NULL,
2564                                           "pop vlan action is not supported");
2565         if (attr->egress)
2566                 return rte_flow_error_set(error, ENOTSUP,
2567                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2568                                           NULL,
2569                                           "pop vlan action not supported for "
2570                                           "egress");
2571         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2572                 return rte_flow_error_set(error, ENOTSUP,
2573                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2574                                           "no support for multiple VLAN "
2575                                           "actions");
2576         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2577         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2578             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2579                 return rte_flow_error_set(error, ENOTSUP,
2580                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2581                                           NULL,
2582                                           "cannot pop vlan after decap without "
2583                                           "match on inner vlan in the flow");
2584         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2585         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2586             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2587                 return rte_flow_error_set(error, ENOTSUP,
2588                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2589                                           NULL,
2590                                           "cannot pop vlan without a "
2591                                           "match on (outer) vlan in the flow");
2592         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2593                 return rte_flow_error_set(error, EINVAL,
2594                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2595                                           "wrong action order, port_id should "
2596                                           "be after pop VLAN action");
2597         if (!attr->transfer && priv->representor)
2598                 return rte_flow_error_set(error, ENOTSUP,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2600                                           "pop vlan action for VF representor "
2601                                           "not supported on NIC table");
2602         return 0;
2603 }
2604
2605 /**
2606  * Get VLAN default info from vlan match info.
2607  *
2608  * @param[in] items
2609  *   the list of item specifications.
2610  * @param[out] vlan
2611  *   pointer VLAN info to fill to.
2612  *
2613  * @return
2614  *   0 on success, a negative errno value otherwise and rte_errno is set.
2615  */
2616 static void
2617 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2618                                   struct rte_vlan_hdr *vlan)
2619 {
2620         const struct rte_flow_item_vlan nic_mask = {
2621                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2622                                 MLX5DV_FLOW_VLAN_VID_MASK),
2623                 .inner_type = RTE_BE16(0xffff),
2624         };
2625
2626         if (items == NULL)
2627                 return;
2628         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2629                 int type = items->type;
2630
2631                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2632                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2633                         break;
2634         }
2635         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2636                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2637                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2638
2639                 /* If VLAN item in pattern doesn't contain data, return here. */
2640                 if (!vlan_v)
2641                         return;
2642                 if (!vlan_m)
2643                         vlan_m = &nic_mask;
2644                 /* Only full match values are accepted */
2645                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2646                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2647                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2648                         vlan->vlan_tci |=
2649                                 rte_be_to_cpu_16(vlan_v->tci &
2650                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2651                 }
2652                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2653                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2654                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2655                         vlan->vlan_tci |=
2656                                 rte_be_to_cpu_16(vlan_v->tci &
2657                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2658                 }
2659                 if (vlan_m->inner_type == nic_mask.inner_type)
2660                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2661                                                            vlan_m->inner_type);
2662         }
2663 }
2664
2665 /**
2666  * Validate the push VLAN action.
2667  *
2668  * @param[in] dev
2669  *   Pointer to the rte_eth_dev structure.
2670  * @param[in] action_flags
2671  *   Holds the actions detected until now.
2672  * @param[in] item_flags
2673  *   The items found in this flow rule.
2674  * @param[in] action
2675  *   Pointer to the action structure.
2676  * @param[in] attr
2677  *   Pointer to flow attributes
2678  * @param[out] error
2679  *   Pointer to error structure.
2680  *
2681  * @return
2682  *   0 on success, a negative errno value otherwise and rte_errno is set.
2683  */
2684 static int
2685 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2686                                   uint64_t action_flags,
2687                                   const struct rte_flow_item_vlan *vlan_m,
2688                                   const struct rte_flow_action *action,
2689                                   const struct rte_flow_attr *attr,
2690                                   struct rte_flow_error *error)
2691 {
2692         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2693         const struct mlx5_priv *priv = dev->data->dev_private;
2694
2695         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2696             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2697                 return rte_flow_error_set(error, EINVAL,
2698                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2699                                           "invalid vlan ethertype");
2700         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2701                 return rte_flow_error_set(error, EINVAL,
2702                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2703                                           "wrong action order, port_id should "
2704                                           "be after push VLAN");
2705         if (!attr->transfer && priv->representor)
2706                 return rte_flow_error_set(error, ENOTSUP,
2707                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2708                                           "push vlan action for VF representor "
2709                                           "not supported on NIC table");
2710         if (vlan_m &&
2711             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2712             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2713                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2714             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2715             !(mlx5_flow_find_action
2716                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2717                 return rte_flow_error_set(error, EINVAL,
2718                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2719                                           "not full match mask on VLAN PCP and "
2720                                           "there is no of_set_vlan_pcp action, "
2721                                           "push VLAN action cannot figure out "
2722                                           "PCP value");
2723         if (vlan_m &&
2724             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2725             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2726                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2727             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2728             !(mlx5_flow_find_action
2729                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2730                 return rte_flow_error_set(error, EINVAL,
2731                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2732                                           "not full match mask on VLAN VID and "
2733                                           "there is no of_set_vlan_vid action, "
2734                                           "push VLAN action cannot figure out "
2735                                           "VID value");
2736         (void)attr;
2737         return 0;
2738 }
2739
2740 /**
2741  * Validate the set VLAN PCP.
2742  *
2743  * @param[in] action_flags
2744  *   Holds the actions detected until now.
2745  * @param[in] actions
2746  *   Pointer to the list of actions remaining in the flow rule.
2747  * @param[out] error
2748  *   Pointer to error structure.
2749  *
2750  * @return
2751  *   0 on success, a negative errno value otherwise and rte_errno is set.
2752  */
2753 static int
2754 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2755                                      const struct rte_flow_action actions[],
2756                                      struct rte_flow_error *error)
2757 {
2758         const struct rte_flow_action *action = actions;
2759         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2760
2761         if (conf->vlan_pcp > 7)
2762                 return rte_flow_error_set(error, EINVAL,
2763                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2764                                           "VLAN PCP value is too big");
2765         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2766                 return rte_flow_error_set(error, ENOTSUP,
2767                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2768                                           "set VLAN PCP action must follow "
2769                                           "the push VLAN action");
2770         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2771                 return rte_flow_error_set(error, ENOTSUP,
2772                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2773                                           "Multiple VLAN PCP modification are "
2774                                           "not supported");
2775         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2776                 return rte_flow_error_set(error, EINVAL,
2777                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2778                                           "wrong action order, port_id should "
2779                                           "be after set VLAN PCP");
2780         return 0;
2781 }
2782
2783 /**
2784  * Validate the set VLAN VID.
2785  *
2786  * @param[in] item_flags
2787  *   Holds the items detected in this rule.
2788  * @param[in] action_flags
2789  *   Holds the actions detected until now.
2790  * @param[in] actions
2791  *   Pointer to the list of actions remaining in the flow rule.
2792  * @param[out] error
2793  *   Pointer to error structure.
2794  *
2795  * @return
2796  *   0 on success, a negative errno value otherwise and rte_errno is set.
2797  */
2798 static int
2799 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2800                                      uint64_t action_flags,
2801                                      const struct rte_flow_action actions[],
2802                                      struct rte_flow_error *error)
2803 {
2804         const struct rte_flow_action *action = actions;
2805         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2806
2807         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2808                 return rte_flow_error_set(error, EINVAL,
2809                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2810                                           "VLAN VID value is too big");
2811         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2812             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2813                 return rte_flow_error_set(error, ENOTSUP,
2814                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2815                                           "set VLAN VID action must follow push"
2816                                           " VLAN action or match on VLAN item");
2817         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2818                 return rte_flow_error_set(error, ENOTSUP,
2819                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2820                                           "Multiple VLAN VID modifications are "
2821                                           "not supported");
2822         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2823                 return rte_flow_error_set(error, EINVAL,
2824                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2825                                           "wrong action order, port_id should "
2826                                           "be after set VLAN VID");
2827         return 0;
2828 }
2829
2830 /*
2831  * Validate the FLAG action.
2832  *
2833  * @param[in] dev
2834  *   Pointer to the rte_eth_dev structure.
2835  * @param[in] action_flags
2836  *   Holds the actions detected until now.
2837  * @param[in] attr
2838  *   Pointer to flow attributes
2839  * @param[out] error
2840  *   Pointer to error structure.
2841  *
2842  * @return
2843  *   0 on success, a negative errno value otherwise and rte_errno is set.
2844  */
2845 static int
2846 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2847                              uint64_t action_flags,
2848                              const struct rte_flow_attr *attr,
2849                              struct rte_flow_error *error)
2850 {
2851         struct mlx5_priv *priv = dev->data->dev_private;
2852         struct mlx5_dev_config *config = &priv->config;
2853         int ret;
2854
2855         /* Fall back if no extended metadata register support. */
2856         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2857                 return mlx5_flow_validate_action_flag(action_flags, attr,
2858                                                       error);
2859         /* Extensive metadata mode requires registers. */
2860         if (!mlx5_flow_ext_mreg_supported(dev))
2861                 return rte_flow_error_set(error, ENOTSUP,
2862                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2863                                           "no metadata registers "
2864                                           "to support flag action");
2865         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2866                 return rte_flow_error_set(error, ENOTSUP,
2867                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2868                                           "extended metadata register"
2869                                           " isn't available");
2870         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2871         if (ret < 0)
2872                 return ret;
2873         MLX5_ASSERT(ret > 0);
2874         if (action_flags & MLX5_FLOW_ACTION_MARK)
2875                 return rte_flow_error_set(error, EINVAL,
2876                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2877                                           "can't mark and flag in same flow");
2878         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2879                 return rte_flow_error_set(error, EINVAL,
2880                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2881                                           "can't have 2 flag"
2882                                           " actions in same flow");
2883         return 0;
2884 }
2885
2886 /**
2887  * Validate MARK action.
2888  *
2889  * @param[in] dev
2890  *   Pointer to the rte_eth_dev structure.
2891  * @param[in] action
2892  *   Pointer to action.
2893  * @param[in] action_flags
2894  *   Holds the actions detected until now.
2895  * @param[in] attr
2896  *   Pointer to flow attributes
2897  * @param[out] error
2898  *   Pointer to error structure.
2899  *
2900  * @return
2901  *   0 on success, a negative errno value otherwise and rte_errno is set.
2902  */
2903 static int
2904 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2905                              const struct rte_flow_action *action,
2906                              uint64_t action_flags,
2907                              const struct rte_flow_attr *attr,
2908                              struct rte_flow_error *error)
2909 {
2910         struct mlx5_priv *priv = dev->data->dev_private;
2911         struct mlx5_dev_config *config = &priv->config;
2912         const struct rte_flow_action_mark *mark = action->conf;
2913         int ret;
2914
2915         if (is_tunnel_offload_active(dev))
2916                 return rte_flow_error_set(error, ENOTSUP,
2917                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2918                                           "no mark action "
2919                                           "if tunnel offload active");
2920         /* Fall back if no extended metadata register support. */
2921         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2922                 return mlx5_flow_validate_action_mark(action, action_flags,
2923                                                       attr, error);
2924         /* Extensive metadata mode requires registers. */
2925         if (!mlx5_flow_ext_mreg_supported(dev))
2926                 return rte_flow_error_set(error, ENOTSUP,
2927                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2928                                           "no metadata registers "
2929                                           "to support mark action");
2930         if (!priv->sh->dv_mark_mask)
2931                 return rte_flow_error_set(error, ENOTSUP,
2932                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2933                                           "extended metadata register"
2934                                           " isn't available");
2935         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2936         if (ret < 0)
2937                 return ret;
2938         MLX5_ASSERT(ret > 0);
2939         if (!mark)
2940                 return rte_flow_error_set(error, EINVAL,
2941                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2942                                           "configuration cannot be null");
2943         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2944                 return rte_flow_error_set(error, EINVAL,
2945                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2946                                           &mark->id,
2947                                           "mark id exceeds the limit");
2948         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2949                 return rte_flow_error_set(error, EINVAL,
2950                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2951                                           "can't flag and mark in same flow");
2952         if (action_flags & MLX5_FLOW_ACTION_MARK)
2953                 return rte_flow_error_set(error, EINVAL,
2954                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2955                                           "can't have 2 mark actions in same"
2956                                           " flow");
2957         return 0;
2958 }
2959
2960 /**
2961  * Validate SET_META action.
2962  *
2963  * @param[in] dev
2964  *   Pointer to the rte_eth_dev structure.
2965  * @param[in] action
2966  *   Pointer to the action structure.
2967  * @param[in] action_flags
2968  *   Holds the actions detected until now.
2969  * @param[in] attr
2970  *   Pointer to flow attributes
2971  * @param[out] error
2972  *   Pointer to error structure.
2973  *
2974  * @return
2975  *   0 on success, a negative errno value otherwise and rte_errno is set.
2976  */
2977 static int
2978 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2979                                  const struct rte_flow_action *action,
2980                                  uint64_t action_flags __rte_unused,
2981                                  const struct rte_flow_attr *attr,
2982                                  struct rte_flow_error *error)
2983 {
2984         const struct rte_flow_action_set_meta *conf;
2985         uint32_t nic_mask = UINT32_MAX;
2986         int reg;
2987
2988         if (!mlx5_flow_ext_mreg_supported(dev))
2989                 return rte_flow_error_set(error, ENOTSUP,
2990                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2991                                           "extended metadata register"
2992                                           " isn't supported");
2993         reg = flow_dv_get_metadata_reg(dev, attr, error);
2994         if (reg < 0)
2995                 return reg;
2996         if (reg == REG_NON)
2997                 return rte_flow_error_set(error, ENOTSUP,
2998                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2999                                           "unavalable extended metadata register");
3000         if (reg != REG_A && reg != REG_B) {
3001                 struct mlx5_priv *priv = dev->data->dev_private;
3002
3003                 nic_mask = priv->sh->dv_meta_mask;
3004         }
3005         if (!(action->conf))
3006                 return rte_flow_error_set(error, EINVAL,
3007                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3008                                           "configuration cannot be null");
3009         conf = (const struct rte_flow_action_set_meta *)action->conf;
3010         if (!conf->mask)
3011                 return rte_flow_error_set(error, EINVAL,
3012                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3013                                           "zero mask doesn't have any effect");
3014         if (conf->mask & ~nic_mask)
3015                 return rte_flow_error_set(error, EINVAL,
3016                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3017                                           "meta data must be within reg C0");
3018         return 0;
3019 }
3020
3021 /**
3022  * Validate SET_TAG action.
3023  *
3024  * @param[in] dev
3025  *   Pointer to the rte_eth_dev structure.
3026  * @param[in] action
3027  *   Pointer to the action structure.
3028  * @param[in] action_flags
3029  *   Holds the actions detected until now.
3030  * @param[in] attr
3031  *   Pointer to flow attributes
3032  * @param[out] error
3033  *   Pointer to error structure.
3034  *
3035  * @return
3036  *   0 on success, a negative errno value otherwise and rte_errno is set.
3037  */
3038 static int
3039 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3040                                 const struct rte_flow_action *action,
3041                                 uint64_t action_flags,
3042                                 const struct rte_flow_attr *attr,
3043                                 struct rte_flow_error *error)
3044 {
3045         const struct rte_flow_action_set_tag *conf;
3046         const uint64_t terminal_action_flags =
3047                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3048                 MLX5_FLOW_ACTION_RSS;
3049         int ret;
3050
3051         if (!mlx5_flow_ext_mreg_supported(dev))
3052                 return rte_flow_error_set(error, ENOTSUP,
3053                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3054                                           "extensive metadata register"
3055                                           " isn't supported");
3056         if (!(action->conf))
3057                 return rte_flow_error_set(error, EINVAL,
3058                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3059                                           "configuration cannot be null");
3060         conf = (const struct rte_flow_action_set_tag *)action->conf;
3061         if (!conf->mask)
3062                 return rte_flow_error_set(error, EINVAL,
3063                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3064                                           "zero mask doesn't have any effect");
3065         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3066         if (ret < 0)
3067                 return ret;
3068         if (!attr->transfer && attr->ingress &&
3069             (action_flags & terminal_action_flags))
3070                 return rte_flow_error_set(error, EINVAL,
3071                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3072                                           "set_tag has no effect"
3073                                           " with terminal actions");
3074         return 0;
3075 }
3076
3077 /**
3078  * Validate count action.
3079  *
3080  * @param[in] dev
3081  *   Pointer to rte_eth_dev structure.
3082  * @param[in] action
3083  *   Pointer to the action structure.
3084  * @param[in] action_flags
3085  *   Holds the actions detected until now.
3086  * @param[out] error
3087  *   Pointer to error structure.
3088  *
3089  * @return
3090  *   0 on success, a negative errno value otherwise and rte_errno is set.
3091  */
3092 static int
3093 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3094                               const struct rte_flow_action *action,
3095                               uint64_t action_flags,
3096                               struct rte_flow_error *error)
3097 {
3098         struct mlx5_priv *priv = dev->data->dev_private;
3099         const struct rte_flow_action_count *count;
3100
3101         if (!priv->config.devx)
3102                 goto notsup_err;
3103         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3104                 return rte_flow_error_set(error, EINVAL,
3105                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3106                                           "duplicate count actions set");
3107         count = (const struct rte_flow_action_count *)action->conf;
3108         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3109             !priv->sh->flow_hit_aso_en)
3110                 return rte_flow_error_set(error, EINVAL,
3111                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3112                                           "old age and shared count combination is not supported");
3113 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3114         return 0;
3115 #endif
3116 notsup_err:
3117         return rte_flow_error_set
3118                       (error, ENOTSUP,
3119                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3120                        NULL,
3121                        "count action not supported");
3122 }
3123
3124 /**
3125  * Validate the L2 encap action.
3126  *
3127  * @param[in] dev
3128  *   Pointer to the rte_eth_dev structure.
3129  * @param[in] action_flags
3130  *   Holds the actions detected until now.
3131  * @param[in] action
3132  *   Pointer to the action structure.
3133  * @param[in] attr
3134  *   Pointer to flow attributes.
3135  * @param[out] error
3136  *   Pointer to error structure.
3137  *
3138  * @return
3139  *   0 on success, a negative errno value otherwise and rte_errno is set.
3140  */
3141 static int
3142 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3143                                  uint64_t action_flags,
3144                                  const struct rte_flow_action *action,
3145                                  const struct rte_flow_attr *attr,
3146                                  struct rte_flow_error *error)
3147 {
3148         const struct mlx5_priv *priv = dev->data->dev_private;
3149
3150         if (!(action->conf))
3151                 return rte_flow_error_set(error, EINVAL,
3152                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3153                                           "configuration cannot be null");
3154         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3155                 return rte_flow_error_set(error, EINVAL,
3156                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157                                           "can only have a single encap action "
3158                                           "in a flow");
3159         if (!attr->transfer && priv->representor)
3160                 return rte_flow_error_set(error, ENOTSUP,
3161                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3162                                           "encap action for VF representor "
3163                                           "not supported on NIC table");
3164         return 0;
3165 }
3166
3167 /**
3168  * Validate a decap action.
3169  *
3170  * @param[in] dev
3171  *   Pointer to the rte_eth_dev structure.
3172  * @param[in] action_flags
3173  *   Holds the actions detected until now.
3174  * @param[in] action
3175  *   Pointer to the action structure.
3176  * @param[in] item_flags
3177  *   Holds the items detected.
3178  * @param[in] attr
3179  *   Pointer to flow attributes
3180  * @param[out] error
3181  *   Pointer to error structure.
3182  *
3183  * @return
3184  *   0 on success, a negative errno value otherwise and rte_errno is set.
3185  */
3186 static int
3187 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3188                               uint64_t action_flags,
3189                               const struct rte_flow_action *action,
3190                               const uint64_t item_flags,
3191                               const struct rte_flow_attr *attr,
3192                               struct rte_flow_error *error)
3193 {
3194         const struct mlx5_priv *priv = dev->data->dev_private;
3195
3196         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3197             !priv->config.decap_en)
3198                 return rte_flow_error_set(error, ENOTSUP,
3199                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3200                                           "decap is not enabled");
3201         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3202                 return rte_flow_error_set(error, ENOTSUP,
3203                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3204                                           action_flags &
3205                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3206                                           "have a single decap action" : "decap "
3207                                           "after encap is not supported");
3208         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3209                 return rte_flow_error_set(error, EINVAL,
3210                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3211                                           "can't have decap action after"
3212                                           " modify action");
3213         if (attr->egress)
3214                 return rte_flow_error_set(error, ENOTSUP,
3215                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3216                                           NULL,
3217                                           "decap action not supported for "
3218                                           "egress");
3219         if (!attr->transfer && priv->representor)
3220                 return rte_flow_error_set(error, ENOTSUP,
3221                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3222                                           "decap action for VF representor "
3223                                           "not supported on NIC table");
3224         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3225             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3226                 return rte_flow_error_set(error, ENOTSUP,
3227                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3228                                 "VXLAN item should be present for VXLAN decap");
3229         return 0;
3230 }
3231
3232 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3233
3234 /**
3235  * Validate the raw encap and decap actions.
3236  *
3237  * @param[in] dev
3238  *   Pointer to the rte_eth_dev structure.
3239  * @param[in] decap
3240  *   Pointer to the decap action.
3241  * @param[in] encap
3242  *   Pointer to the encap action.
3243  * @param[in] attr
3244  *   Pointer to flow attributes
3245  * @param[in/out] action_flags
3246  *   Holds the actions detected until now.
3247  * @param[out] actions_n
3248  *   pointer to the number of actions counter.
3249  * @param[in] action
3250  *   Pointer to the action structure.
3251  * @param[in] item_flags
3252  *   Holds the items detected.
3253  * @param[out] error
3254  *   Pointer to error structure.
3255  *
3256  * @return
3257  *   0 on success, a negative errno value otherwise and rte_errno is set.
3258  */
3259 static int
3260 flow_dv_validate_action_raw_encap_decap
3261         (struct rte_eth_dev *dev,
3262          const struct rte_flow_action_raw_decap *decap,
3263          const struct rte_flow_action_raw_encap *encap,
3264          const struct rte_flow_attr *attr, uint64_t *action_flags,
3265          int *actions_n, const struct rte_flow_action *action,
3266          uint64_t item_flags, struct rte_flow_error *error)
3267 {
3268         const struct mlx5_priv *priv = dev->data->dev_private;
3269         int ret;
3270
3271         if (encap && (!encap->size || !encap->data))
3272                 return rte_flow_error_set(error, EINVAL,
3273                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3274                                           "raw encap data cannot be empty");
3275         if (decap && encap) {
3276                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3277                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3278                         /* L3 encap. */
3279                         decap = NULL;
3280                 else if (encap->size <=
3281                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3282                            decap->size >
3283                            MLX5_ENCAPSULATION_DECISION_SIZE)
3284                         /* L3 decap. */
3285                         encap = NULL;
3286                 else if (encap->size >
3287                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3288                            decap->size >
3289                            MLX5_ENCAPSULATION_DECISION_SIZE)
3290                         /* 2 L2 actions: encap and decap. */
3291                         ;
3292                 else
3293                         return rte_flow_error_set(error,
3294                                 ENOTSUP,
3295                                 RTE_FLOW_ERROR_TYPE_ACTION,
3296                                 NULL, "unsupported too small "
3297                                 "raw decap and too small raw "
3298                                 "encap combination");
3299         }
3300         if (decap) {
3301                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3302                                                     item_flags, attr, error);
3303                 if (ret < 0)
3304                         return ret;
3305                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3306                 ++(*actions_n);
3307         }
3308         if (encap) {
3309                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3310                         return rte_flow_error_set(error, ENOTSUP,
3311                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3312                                                   NULL,
3313                                                   "small raw encap size");
3314                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3315                         return rte_flow_error_set(error, EINVAL,
3316                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3317                                                   NULL,
3318                                                   "more than one encap action");
3319                 if (!attr->transfer && priv->representor)
3320                         return rte_flow_error_set
3321                                         (error, ENOTSUP,
3322                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3323                                          "encap action for VF representor "
3324                                          "not supported on NIC table");
3325                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3326                 ++(*actions_n);
3327         }
3328         return 0;
3329 }
3330
3331 /**
3332  * Match encap_decap resource.
3333  *
3334  * @param list
3335  *   Pointer to the hash list.
3336  * @param entry
3337  *   Pointer to exist resource entry object.
3338  * @param key
3339  *   Key of the new entry.
3340  * @param ctx_cb
3341  *   Pointer to new encap_decap resource.
3342  *
3343  * @return
3344  *   0 on matching, none-zero otherwise.
3345  */
3346 int
3347 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3348                              struct mlx5_hlist_entry *entry,
3349                              uint64_t key __rte_unused, void *cb_ctx)
3350 {
3351         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3352         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3353         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3354
3355         cache_resource = container_of(entry,
3356                                       struct mlx5_flow_dv_encap_decap_resource,
3357                                       entry);
3358         if (resource->reformat_type == cache_resource->reformat_type &&
3359             resource->ft_type == cache_resource->ft_type &&
3360             resource->flags == cache_resource->flags &&
3361             resource->size == cache_resource->size &&
3362             !memcmp((const void *)resource->buf,
3363                     (const void *)cache_resource->buf,
3364                     resource->size))
3365                 return 0;
3366         return -1;
3367 }
3368
3369 /**
3370  * Allocate encap_decap resource.
3371  *
3372  * @param list
3373  *   Pointer to the hash list.
3374  * @param entry
3375  *   Pointer to exist resource entry object.
3376  * @param ctx_cb
3377  *   Pointer to new encap_decap resource.
3378  *
3379  * @return
3380  *   0 on matching, none-zero otherwise.
3381  */
3382 struct mlx5_hlist_entry *
3383 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3384                               uint64_t key __rte_unused,
3385                               void *cb_ctx)
3386 {
3387         struct mlx5_dev_ctx_shared *sh = list->ctx;
3388         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3389         struct mlx5dv_dr_domain *domain;
3390         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3391         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3392         uint32_t idx;
3393         int ret;
3394
3395         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3396                 domain = sh->fdb_domain;
3397         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3398                 domain = sh->rx_domain;
3399         else
3400                 domain = sh->tx_domain;
3401         /* Register new encap/decap resource. */
3402         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3403                                        &idx);
3404         if (!cache_resource) {
3405                 rte_flow_error_set(ctx->error, ENOMEM,
3406                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3407                                    "cannot allocate resource memory");
3408                 return NULL;
3409         }
3410         *cache_resource = *resource;
3411         cache_resource->idx = idx;
3412         ret = mlx5_flow_os_create_flow_action_packet_reformat
3413                                         (sh->ctx, domain, cache_resource,
3414                                          &cache_resource->action);
3415         if (ret) {
3416                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3417                 rte_flow_error_set(ctx->error, ENOMEM,
3418                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3419                                    NULL, "cannot create action");
3420                 return NULL;
3421         }
3422
3423         return &cache_resource->entry;
3424 }
3425
3426 /**
3427  * Find existing encap/decap resource or create and register a new one.
3428  *
3429  * @param[in, out] dev
3430  *   Pointer to rte_eth_dev structure.
3431  * @param[in, out] resource
3432  *   Pointer to encap/decap resource.
3433  * @parm[in, out] dev_flow
3434  *   Pointer to the dev_flow.
3435  * @param[out] error
3436  *   pointer to error structure.
3437  *
3438  * @return
3439  *   0 on success otherwise -errno and errno is set.
3440  */
3441 static int
3442 flow_dv_encap_decap_resource_register
3443                         (struct rte_eth_dev *dev,
3444                          struct mlx5_flow_dv_encap_decap_resource *resource,
3445                          struct mlx5_flow *dev_flow,
3446                          struct rte_flow_error *error)
3447 {
3448         struct mlx5_priv *priv = dev->data->dev_private;
3449         struct mlx5_dev_ctx_shared *sh = priv->sh;
3450         struct mlx5_hlist_entry *entry;
3451         union {
3452                 struct {
3453                         uint32_t ft_type:8;
3454                         uint32_t refmt_type:8;
3455                         /*
3456                          * Header reformat actions can be shared between
3457                          * non-root tables. One bit to indicate non-root
3458                          * table or not.
3459                          */
3460                         uint32_t is_root:1;
3461                         uint32_t reserve:15;
3462                 };
3463                 uint32_t v32;
3464         } encap_decap_key = {
3465                 {
3466                         .ft_type = resource->ft_type,
3467                         .refmt_type = resource->reformat_type,
3468                         .is_root = !!dev_flow->dv.group,
3469                         .reserve = 0,
3470                 }
3471         };
3472         struct mlx5_flow_cb_ctx ctx = {
3473                 .error = error,
3474                 .data = resource,
3475         };
3476         uint64_t key64;
3477
3478         resource->flags = dev_flow->dv.group ? 0 : 1;
3479         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3480                                  sizeof(encap_decap_key.v32), 0);
3481         if (resource->reformat_type !=
3482             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3483             resource->size)
3484                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3485         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3486         if (!entry)
3487                 return -rte_errno;
3488         resource = container_of(entry, typeof(*resource), entry);
3489         dev_flow->dv.encap_decap = resource;
3490         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3491         return 0;
3492 }
3493
3494 /**
3495  * Find existing table jump resource or create and register a new one.
3496  *
3497  * @param[in, out] dev
3498  *   Pointer to rte_eth_dev structure.
3499  * @param[in, out] tbl
3500  *   Pointer to flow table resource.
3501  * @parm[in, out] dev_flow
3502  *   Pointer to the dev_flow.
3503  * @param[out] error
3504  *   pointer to error structure.
3505  *
3506  * @return
3507  *   0 on success otherwise -errno and errno is set.
3508  */
3509 static int
3510 flow_dv_jump_tbl_resource_register
3511                         (struct rte_eth_dev *dev __rte_unused,
3512                          struct mlx5_flow_tbl_resource *tbl,
3513                          struct mlx5_flow *dev_flow,
3514                          struct rte_flow_error *error __rte_unused)
3515 {
3516         struct mlx5_flow_tbl_data_entry *tbl_data =
3517                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3518
3519         MLX5_ASSERT(tbl);
3520         MLX5_ASSERT(tbl_data->jump.action);
3521         dev_flow->handle->rix_jump = tbl_data->idx;
3522         dev_flow->dv.jump = &tbl_data->jump;
3523         return 0;
3524 }
3525
3526 int
3527 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3528                          struct mlx5_cache_entry *entry, void *cb_ctx)
3529 {
3530         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3531         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3532         struct mlx5_flow_dv_port_id_action_resource *res =
3533                         container_of(entry, typeof(*res), entry);
3534
3535         return ref->port_id != res->port_id;
3536 }
3537
3538 struct mlx5_cache_entry *
3539 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3540                           struct mlx5_cache_entry *entry __rte_unused,
3541                           void *cb_ctx)
3542 {
3543         struct mlx5_dev_ctx_shared *sh = list->ctx;
3544         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3545         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3546         struct mlx5_flow_dv_port_id_action_resource *cache;
3547         uint32_t idx;
3548         int ret;
3549
3550         /* Register new port id action resource. */
3551         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3552         if (!cache) {
3553                 rte_flow_error_set(ctx->error, ENOMEM,
3554                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3555                                    "cannot allocate port_id action cache memory");
3556                 return NULL;
3557         }
3558         *cache = *ref;
3559         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3560                                                         ref->port_id,
3561                                                         &cache->action);
3562         if (ret) {
3563                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3564                 rte_flow_error_set(ctx->error, ENOMEM,
3565                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3566                                    "cannot create action");
3567                 return NULL;
3568         }
3569         cache->idx = idx;
3570         return &cache->entry;
3571 }
3572
3573 /**
3574  * Find existing table port ID resource or create and register a new one.
3575  *
3576  * @param[in, out] dev
3577  *   Pointer to rte_eth_dev structure.
3578  * @param[in, out] resource
3579  *   Pointer to port ID action resource.
3580  * @parm[in, out] dev_flow
3581  *   Pointer to the dev_flow.
3582  * @param[out] error
3583  *   pointer to error structure.
3584  *
3585  * @return
3586  *   0 on success otherwise -errno and errno is set.
3587  */
3588 static int
3589 flow_dv_port_id_action_resource_register
3590                         (struct rte_eth_dev *dev,
3591                          struct mlx5_flow_dv_port_id_action_resource *resource,
3592                          struct mlx5_flow *dev_flow,
3593                          struct rte_flow_error *error)
3594 {
3595         struct mlx5_priv *priv = dev->data->dev_private;
3596         struct mlx5_cache_entry *entry;
3597         struct mlx5_flow_dv_port_id_action_resource *cache;
3598         struct mlx5_flow_cb_ctx ctx = {
3599                 .error = error,
3600                 .data = resource,
3601         };
3602
3603         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3604         if (!entry)
3605                 return -rte_errno;
3606         cache = container_of(entry, typeof(*cache), entry);
3607         dev_flow->dv.port_id_action = cache;
3608         dev_flow->handle->rix_port_id_action = cache->idx;
3609         return 0;
3610 }
3611
3612 int
3613 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3614                          struct mlx5_cache_entry *entry, void *cb_ctx)
3615 {
3616         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3617         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3618         struct mlx5_flow_dv_push_vlan_action_resource *res =
3619                         container_of(entry, typeof(*res), entry);
3620
3621         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3622 }
3623
3624 struct mlx5_cache_entry *
3625 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3626                           struct mlx5_cache_entry *entry __rte_unused,
3627                           void *cb_ctx)
3628 {
3629         struct mlx5_dev_ctx_shared *sh = list->ctx;
3630         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3631         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3632         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3633         struct mlx5dv_dr_domain *domain;
3634         uint32_t idx;
3635         int ret;
3636
3637         /* Register new port id action resource. */
3638         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3639         if (!cache) {
3640                 rte_flow_error_set(ctx->error, ENOMEM,
3641                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3642                                    "cannot allocate push_vlan action cache memory");
3643                 return NULL;
3644         }
3645         *cache = *ref;
3646         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3647                 domain = sh->fdb_domain;
3648         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3649                 domain = sh->rx_domain;
3650         else
3651                 domain = sh->tx_domain;
3652         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3653                                                         &cache->action);
3654         if (ret) {
3655                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3656                 rte_flow_error_set(ctx->error, ENOMEM,
3657                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3658                                    "cannot create push vlan action");
3659                 return NULL;
3660         }
3661         cache->idx = idx;
3662         return &cache->entry;
3663 }
3664
3665 /**
3666  * Find existing push vlan resource or create and register a new one.
3667  *
3668  * @param [in, out] dev
3669  *   Pointer to rte_eth_dev structure.
3670  * @param[in, out] resource
3671  *   Pointer to port ID action resource.
3672  * @parm[in, out] dev_flow
3673  *   Pointer to the dev_flow.
3674  * @param[out] error
3675  *   pointer to error structure.
3676  *
3677  * @return
3678  *   0 on success otherwise -errno and errno is set.
3679  */
3680 static int
3681 flow_dv_push_vlan_action_resource_register
3682                        (struct rte_eth_dev *dev,
3683                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3684                         struct mlx5_flow *dev_flow,
3685                         struct rte_flow_error *error)
3686 {
3687         struct mlx5_priv *priv = dev->data->dev_private;
3688         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3689         struct mlx5_cache_entry *entry;
3690         struct mlx5_flow_cb_ctx ctx = {
3691                 .error = error,
3692                 .data = resource,
3693         };
3694
3695         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3696         if (!entry)
3697                 return -rte_errno;
3698         cache = container_of(entry, typeof(*cache), entry);
3699
3700         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3701         dev_flow->dv.push_vlan_res = cache;
3702         return 0;
3703 }
3704
3705 /**
3706  * Get the size of specific rte_flow_item_type hdr size
3707  *
3708  * @param[in] item_type
3709  *   Tested rte_flow_item_type.
3710  *
3711  * @return
3712  *   sizeof struct item_type, 0 if void or irrelevant.
3713  */
3714 static size_t
3715 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3716 {
3717         size_t retval;
3718
3719         switch (item_type) {
3720         case RTE_FLOW_ITEM_TYPE_ETH:
3721                 retval = sizeof(struct rte_ether_hdr);
3722                 break;
3723         case RTE_FLOW_ITEM_TYPE_VLAN:
3724                 retval = sizeof(struct rte_vlan_hdr);
3725                 break;
3726         case RTE_FLOW_ITEM_TYPE_IPV4:
3727                 retval = sizeof(struct rte_ipv4_hdr);
3728                 break;
3729         case RTE_FLOW_ITEM_TYPE_IPV6:
3730                 retval = sizeof(struct rte_ipv6_hdr);
3731                 break;
3732         case RTE_FLOW_ITEM_TYPE_UDP:
3733                 retval = sizeof(struct rte_udp_hdr);
3734                 break;
3735         case RTE_FLOW_ITEM_TYPE_TCP:
3736                 retval = sizeof(struct rte_tcp_hdr);
3737                 break;
3738         case RTE_FLOW_ITEM_TYPE_VXLAN:
3739         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3740                 retval = sizeof(struct rte_vxlan_hdr);
3741                 break;
3742         case RTE_FLOW_ITEM_TYPE_GRE:
3743         case RTE_FLOW_ITEM_TYPE_NVGRE:
3744                 retval = sizeof(struct rte_gre_hdr);
3745                 break;
3746         case RTE_FLOW_ITEM_TYPE_MPLS:
3747                 retval = sizeof(struct rte_mpls_hdr);
3748                 break;
3749         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3750         default:
3751                 retval = 0;
3752                 break;
3753         }
3754         return retval;
3755 }
3756
3757 #define MLX5_ENCAP_IPV4_VERSION         0x40
3758 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3759 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3760 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3761 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3762 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3763 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3764
3765 /**
3766  * Convert the encap action data from list of rte_flow_item to raw buffer
3767  *
3768  * @param[in] items
3769  *   Pointer to rte_flow_item objects list.
3770  * @param[out] buf
3771  *   Pointer to the output buffer.
3772  * @param[out] size
3773  *   Pointer to the output buffer size.
3774  * @param[out] error
3775  *   Pointer to the error structure.
3776  *
3777  * @return
3778  *   0 on success, a negative errno value otherwise and rte_errno is set.
3779  */
3780 static int
3781 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3782                            size_t *size, struct rte_flow_error *error)
3783 {
3784         struct rte_ether_hdr *eth = NULL;
3785         struct rte_vlan_hdr *vlan = NULL;
3786         struct rte_ipv4_hdr *ipv4 = NULL;
3787         struct rte_ipv6_hdr *ipv6 = NULL;
3788         struct rte_udp_hdr *udp = NULL;
3789         struct rte_vxlan_hdr *vxlan = NULL;
3790         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3791         struct rte_gre_hdr *gre = NULL;
3792         size_t len;
3793         size_t temp_size = 0;
3794
3795         if (!items)
3796                 return rte_flow_error_set(error, EINVAL,
3797                                           RTE_FLOW_ERROR_TYPE_ACTION,
3798                                           NULL, "invalid empty data");
3799         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3800                 len = flow_dv_get_item_hdr_len(items->type);
3801                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3802                         return rte_flow_error_set(error, EINVAL,
3803                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3804                                                   (void *)items->type,
3805                                                   "items total size is too big"
3806                                                   " for encap action");
3807                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3808                 switch (items->type) {
3809                 case RTE_FLOW_ITEM_TYPE_ETH:
3810                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3811                         break;
3812                 case RTE_FLOW_ITEM_TYPE_VLAN:
3813                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3814                         if (!eth)
3815                                 return rte_flow_error_set(error, EINVAL,
3816                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3817                                                 (void *)items->type,
3818                                                 "eth header not found");
3819                         if (!eth->ether_type)
3820                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3821                         break;
3822                 case RTE_FLOW_ITEM_TYPE_IPV4:
3823                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3824                         if (!vlan && !eth)
3825                                 return rte_flow_error_set(error, EINVAL,
3826                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3827                                                 (void *)items->type,
3828                                                 "neither eth nor vlan"
3829                                                 " header found");
3830                         if (vlan && !vlan->eth_proto)
3831                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3832                         else if (eth && !eth->ether_type)
3833                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3834                         if (!ipv4->version_ihl)
3835                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3836                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3837                         if (!ipv4->time_to_live)
3838                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3839                         break;
3840                 case RTE_FLOW_ITEM_TYPE_IPV6:
3841                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3842                         if (!vlan && !eth)
3843                                 return rte_flow_error_set(error, EINVAL,
3844                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3845                                                 (void *)items->type,
3846                                                 "neither eth nor vlan"
3847                                                 " header found");
3848                         if (vlan && !vlan->eth_proto)
3849                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3850                         else if (eth && !eth->ether_type)
3851                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3852                         if (!ipv6->vtc_flow)
3853                                 ipv6->vtc_flow =
3854                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3855                         if (!ipv6->hop_limits)
3856                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3857                         break;
3858                 case RTE_FLOW_ITEM_TYPE_UDP:
3859                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3860                         if (!ipv4 && !ipv6)
3861                                 return rte_flow_error_set(error, EINVAL,
3862                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3863                                                 (void *)items->type,
3864                                                 "ip header not found");
3865                         if (ipv4 && !ipv4->next_proto_id)
3866                                 ipv4->next_proto_id = IPPROTO_UDP;
3867                         else if (ipv6 && !ipv6->proto)
3868                                 ipv6->proto = IPPROTO_UDP;
3869                         break;
3870                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3871                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3872                         if (!udp)
3873                                 return rte_flow_error_set(error, EINVAL,
3874                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3875                                                 (void *)items->type,
3876                                                 "udp header not found");
3877                         if (!udp->dst_port)
3878                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3879                         if (!vxlan->vx_flags)
3880                                 vxlan->vx_flags =
3881                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3882                         break;
3883                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3884                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3885                         if (!udp)
3886                                 return rte_flow_error_set(error, EINVAL,
3887                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3888                                                 (void *)items->type,
3889                                                 "udp header not found");
3890                         if (!vxlan_gpe->proto)
3891                                 return rte_flow_error_set(error, EINVAL,
3892                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3893                                                 (void *)items->type,
3894                                                 "next protocol not found");
3895                         if (!udp->dst_port)
3896                                 udp->dst_port =
3897                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3898                         if (!vxlan_gpe->vx_flags)
3899                                 vxlan_gpe->vx_flags =
3900                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3901                         break;
3902                 case RTE_FLOW_ITEM_TYPE_GRE:
3903                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3904                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3905                         if (!gre->proto)
3906                                 return rte_flow_error_set(error, EINVAL,
3907                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3908                                                 (void *)items->type,
3909                                                 "next protocol not found");
3910                         if (!ipv4 && !ipv6)
3911                                 return rte_flow_error_set(error, EINVAL,
3912                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3913                                                 (void *)items->type,
3914                                                 "ip header not found");
3915                         if (ipv4 && !ipv4->next_proto_id)
3916                                 ipv4->next_proto_id = IPPROTO_GRE;
3917                         else if (ipv6 && !ipv6->proto)
3918                                 ipv6->proto = IPPROTO_GRE;
3919                         break;
3920                 case RTE_FLOW_ITEM_TYPE_VOID:
3921                         break;
3922                 default:
3923                         return rte_flow_error_set(error, EINVAL,
3924                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3925                                                   (void *)items->type,
3926                                                   "unsupported item type");
3927                         break;
3928                 }
3929                 temp_size += len;
3930         }
3931         *size = temp_size;
3932         return 0;
3933 }
3934
3935 static int
3936 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3937 {
3938         struct rte_ether_hdr *eth = NULL;
3939         struct rte_vlan_hdr *vlan = NULL;
3940         struct rte_ipv6_hdr *ipv6 = NULL;
3941         struct rte_udp_hdr *udp = NULL;
3942         char *next_hdr;
3943         uint16_t proto;
3944
3945         eth = (struct rte_ether_hdr *)data;
3946         next_hdr = (char *)(eth + 1);
3947         proto = RTE_BE16(eth->ether_type);
3948
3949         /* VLAN skipping */
3950         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3951                 vlan = (struct rte_vlan_hdr *)next_hdr;
3952                 proto = RTE_BE16(vlan->eth_proto);
3953                 next_hdr += sizeof(struct rte_vlan_hdr);
3954         }
3955
3956         /* HW calculates IPv4 csum. no need to proceed */
3957         if (proto == RTE_ETHER_TYPE_IPV4)
3958                 return 0;
3959
3960         /* non IPv4/IPv6 header. not supported */
3961         if (proto != RTE_ETHER_TYPE_IPV6) {
3962                 return rte_flow_error_set(error, ENOTSUP,
3963                                           RTE_FLOW_ERROR_TYPE_ACTION,
3964                                           NULL, "Cannot offload non IPv4/IPv6");
3965         }
3966
3967         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3968
3969         /* ignore non UDP */
3970         if (ipv6->proto != IPPROTO_UDP)
3971                 return 0;
3972
3973         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3974         udp->dgram_cksum = 0;
3975
3976         return 0;
3977 }
3978
3979 /**
3980  * Convert L2 encap action to DV specification.
3981  *
3982  * @param[in] dev
3983  *   Pointer to rte_eth_dev structure.
3984  * @param[in] action
3985  *   Pointer to action structure.
3986  * @param[in, out] dev_flow
3987  *   Pointer to the mlx5_flow.
3988  * @param[in] transfer
3989  *   Mark if the flow is E-Switch flow.
3990  * @param[out] error
3991  *   Pointer to the error structure.
3992  *
3993  * @return
3994  *   0 on success, a negative errno value otherwise and rte_errno is set.
3995  */
3996 static int
3997 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3998                                const struct rte_flow_action *action,
3999                                struct mlx5_flow *dev_flow,
4000                                uint8_t transfer,
4001                                struct rte_flow_error *error)
4002 {
4003         const struct rte_flow_item *encap_data;
4004         const struct rte_flow_action_raw_encap *raw_encap_data;
4005         struct mlx5_flow_dv_encap_decap_resource res = {
4006                 .reformat_type =
4007                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4008                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4009                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4010         };
4011
4012         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4013                 raw_encap_data =
4014                         (const struct rte_flow_action_raw_encap *)action->conf;
4015                 res.size = raw_encap_data->size;
4016                 memcpy(res.buf, raw_encap_data->data, res.size);
4017         } else {
4018                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4019                         encap_data =
4020                                 ((const struct rte_flow_action_vxlan_encap *)
4021                                                 action->conf)->definition;
4022                 else
4023                         encap_data =
4024                                 ((const struct rte_flow_action_nvgre_encap *)
4025                                                 action->conf)->definition;
4026                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4027                                                &res.size, error))
4028                         return -rte_errno;
4029         }
4030         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4031                 return -rte_errno;
4032         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4033                 return rte_flow_error_set(error, EINVAL,
4034                                           RTE_FLOW_ERROR_TYPE_ACTION,
4035                                           NULL, "can't create L2 encap action");
4036         return 0;
4037 }
4038
4039 /**
4040  * Convert L2 decap action to DV specification.
4041  *
4042  * @param[in] dev
4043  *   Pointer to rte_eth_dev structure.
4044  * @param[in, out] dev_flow
4045  *   Pointer to the mlx5_flow.
4046  * @param[in] transfer
4047  *   Mark if the flow is E-Switch flow.
4048  * @param[out] error
4049  *   Pointer to the error structure.
4050  *
4051  * @return
4052  *   0 on success, a negative errno value otherwise and rte_errno is set.
4053  */
4054 static int
4055 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4056                                struct mlx5_flow *dev_flow,
4057                                uint8_t transfer,
4058                                struct rte_flow_error *error)
4059 {
4060         struct mlx5_flow_dv_encap_decap_resource res = {
4061                 .size = 0,
4062                 .reformat_type =
4063                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4064                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4065                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4066         };
4067
4068         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4069                 return rte_flow_error_set(error, EINVAL,
4070                                           RTE_FLOW_ERROR_TYPE_ACTION,
4071                                           NULL, "can't create L2 decap action");
4072         return 0;
4073 }
4074
4075 /**
4076  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4077  *
4078  * @param[in] dev
4079  *   Pointer to rte_eth_dev structure.
4080  * @param[in] action
4081  *   Pointer to action structure.
4082  * @param[in, out] dev_flow
4083  *   Pointer to the mlx5_flow.
4084  * @param[in] attr
4085  *   Pointer to the flow attributes.
4086  * @param[out] error
4087  *   Pointer to the error structure.
4088  *
4089  * @return
4090  *   0 on success, a negative errno value otherwise and rte_errno is set.
4091  */
4092 static int
4093 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4094                                 const struct rte_flow_action *action,
4095                                 struct mlx5_flow *dev_flow,
4096                                 const struct rte_flow_attr *attr,
4097                                 struct rte_flow_error *error)
4098 {
4099         const struct rte_flow_action_raw_encap *encap_data;
4100         struct mlx5_flow_dv_encap_decap_resource res;
4101
4102         memset(&res, 0, sizeof(res));
4103         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4104         res.size = encap_data->size;
4105         memcpy(res.buf, encap_data->data, res.size);
4106         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4107                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4108                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4109         if (attr->transfer)
4110                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4111         else
4112                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4113                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4114         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4115                 return rte_flow_error_set(error, EINVAL,
4116                                           RTE_FLOW_ERROR_TYPE_ACTION,
4117                                           NULL, "can't create encap action");
4118         return 0;
4119 }
4120
4121 /**
4122  * Create action push VLAN.
4123  *
4124  * @param[in] dev
4125  *   Pointer to rte_eth_dev structure.
4126  * @param[in] attr
4127  *   Pointer to the flow attributes.
4128  * @param[in] vlan
4129  *   Pointer to the vlan to push to the Ethernet header.
4130  * @param[in, out] dev_flow
4131  *   Pointer to the mlx5_flow.
4132  * @param[out] error
4133  *   Pointer to the error structure.
4134  *
4135  * @return
4136  *   0 on success, a negative errno value otherwise and rte_errno is set.
4137  */
4138 static int
4139 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4140                                 const struct rte_flow_attr *attr,
4141                                 const struct rte_vlan_hdr *vlan,
4142                                 struct mlx5_flow *dev_flow,
4143                                 struct rte_flow_error *error)
4144 {
4145         struct mlx5_flow_dv_push_vlan_action_resource res;
4146
4147         memset(&res, 0, sizeof(res));
4148         res.vlan_tag =
4149                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4150                                  vlan->vlan_tci);
4151         if (attr->transfer)
4152                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4153         else
4154                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4155                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4156         return flow_dv_push_vlan_action_resource_register
4157                                             (dev, &res, dev_flow, error);
4158 }
4159
4160 /**
4161  * Validate the modify-header actions.
4162  *
4163  * @param[in] action_flags
4164  *   Holds the actions detected until now.
4165  * @param[in] action
4166  *   Pointer to the modify action.
4167  * @param[out] error
4168  *   Pointer to error structure.
4169  *
4170  * @return
4171  *   0 on success, a negative errno value otherwise and rte_errno is set.
4172  */
4173 static int
4174 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4175                                    const struct rte_flow_action *action,
4176                                    struct rte_flow_error *error)
4177 {
4178         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4179                 return rte_flow_error_set(error, EINVAL,
4180                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4181                                           NULL, "action configuration not set");
4182         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4183                 return rte_flow_error_set(error, EINVAL,
4184                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4185                                           "can't have encap action before"
4186                                           " modify action");
4187         return 0;
4188 }
4189
4190 /**
4191  * Validate the modify-header MAC address actions.
4192  *
4193  * @param[in] action_flags
4194  *   Holds the actions detected until now.
4195  * @param[in] action
4196  *   Pointer to the modify action.
4197  * @param[in] item_flags
4198  *   Holds the items detected.
4199  * @param[out] error
4200  *   Pointer to error structure.
4201  *
4202  * @return
4203  *   0 on success, a negative errno value otherwise and rte_errno is set.
4204  */
4205 static int
4206 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4207                                    const struct rte_flow_action *action,
4208                                    const uint64_t item_flags,
4209                                    struct rte_flow_error *error)
4210 {
4211         int ret = 0;
4212
4213         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4214         if (!ret) {
4215                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4216                         return rte_flow_error_set(error, EINVAL,
4217                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4218                                                   NULL,
4219                                                   "no L2 item in pattern");
4220         }
4221         return ret;
4222 }
4223
4224 /**
4225  * Validate the modify-header IPv4 address actions.
4226  *
4227  * @param[in] action_flags
4228  *   Holds the actions detected until now.
4229  * @param[in] action
4230  *   Pointer to the modify action.
4231  * @param[in] item_flags
4232  *   Holds the items detected.
4233  * @param[out] error
4234  *   Pointer to error structure.
4235  *
4236  * @return
4237  *   0 on success, a negative errno value otherwise and rte_errno is set.
4238  */
4239 static int
4240 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4241                                     const struct rte_flow_action *action,
4242                                     const uint64_t item_flags,
4243                                     struct rte_flow_error *error)
4244 {
4245         int ret = 0;
4246         uint64_t layer;
4247
4248         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4249         if (!ret) {
4250                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4251                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4252                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4253                 if (!(item_flags & layer))
4254                         return rte_flow_error_set(error, EINVAL,
4255                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4256                                                   NULL,
4257                                                   "no ipv4 item in pattern");
4258         }
4259         return ret;
4260 }
4261
4262 /**
4263  * Validate the modify-header IPv6 address actions.
4264  *
4265  * @param[in] action_flags
4266  *   Holds the actions detected until now.
4267  * @param[in] action
4268  *   Pointer to the modify action.
4269  * @param[in] item_flags
4270  *   Holds the items detected.
4271  * @param[out] error
4272  *   Pointer to error structure.
4273  *
4274  * @return
4275  *   0 on success, a negative errno value otherwise and rte_errno is set.
4276  */
4277 static int
4278 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4279                                     const struct rte_flow_action *action,
4280                                     const uint64_t item_flags,
4281                                     struct rte_flow_error *error)
4282 {
4283         int ret = 0;
4284         uint64_t layer;
4285
4286         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4287         if (!ret) {
4288                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4289                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4290                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4291                 if (!(item_flags & layer))
4292                         return rte_flow_error_set(error, EINVAL,
4293                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4294                                                   NULL,
4295                                                   "no ipv6 item in pattern");
4296         }
4297         return ret;
4298 }
4299
4300 /**
4301  * Validate the modify-header TP actions.
4302  *
4303  * @param[in] action_flags
4304  *   Holds the actions detected until now.
4305  * @param[in] action
4306  *   Pointer to the modify action.
4307  * @param[in] item_flags
4308  *   Holds the items detected.
4309  * @param[out] error
4310  *   Pointer to error structure.
4311  *
4312  * @return
4313  *   0 on success, a negative errno value otherwise and rte_errno is set.
4314  */
4315 static int
4316 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4317                                   const struct rte_flow_action *action,
4318                                   const uint64_t item_flags,
4319                                   struct rte_flow_error *error)
4320 {
4321         int ret = 0;
4322         uint64_t layer;
4323
4324         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4325         if (!ret) {
4326                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4327                                  MLX5_FLOW_LAYER_INNER_L4 :
4328                                  MLX5_FLOW_LAYER_OUTER_L4;
4329                 if (!(item_flags & layer))
4330                         return rte_flow_error_set(error, EINVAL,
4331                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4332                                                   NULL, "no transport layer "
4333                                                   "in pattern");
4334         }
4335         return ret;
4336 }
4337
4338 /**
4339  * Validate the modify-header actions of increment/decrement
4340  * TCP Sequence-number.
4341  *
4342  * @param[in] action_flags
4343  *   Holds the actions detected until now.
4344  * @param[in] action
4345  *   Pointer to the modify action.
4346  * @param[in] item_flags
4347  *   Holds the items detected.
4348  * @param[out] error
4349  *   Pointer to error structure.
4350  *
4351  * @return
4352  *   0 on success, a negative errno value otherwise and rte_errno is set.
4353  */
4354 static int
4355 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4356                                        const struct rte_flow_action *action,
4357                                        const uint64_t item_flags,
4358                                        struct rte_flow_error *error)
4359 {
4360         int ret = 0;
4361         uint64_t layer;
4362
4363         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4364         if (!ret) {
4365                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4366                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4367                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4368                 if (!(item_flags & layer))
4369                         return rte_flow_error_set(error, EINVAL,
4370                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4371                                                   NULL, "no TCP item in"
4372                                                   " pattern");
4373                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4374                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4375                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4376                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4377                         return rte_flow_error_set(error, EINVAL,
4378                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4379                                                   NULL,
4380                                                   "cannot decrease and increase"
4381                                                   " TCP sequence number"
4382                                                   " at the same time");
4383         }
4384         return ret;
4385 }
4386
4387 /**
4388  * Validate the modify-header actions of increment/decrement
4389  * TCP Acknowledgment number.
4390  *
4391  * @param[in] action_flags
4392  *   Holds the actions detected until now.
4393  * @param[in] action
4394  *   Pointer to the modify action.
4395  * @param[in] item_flags
4396  *   Holds the items detected.
4397  * @param[out] error
4398  *   Pointer to error structure.
4399  *
4400  * @return
4401  *   0 on success, a negative errno value otherwise and rte_errno is set.
4402  */
4403 static int
4404 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4405                                        const struct rte_flow_action *action,
4406                                        const uint64_t item_flags,
4407                                        struct rte_flow_error *error)
4408 {
4409         int ret = 0;
4410         uint64_t layer;
4411
4412         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4413         if (!ret) {
4414                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4415                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4416                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4417                 if (!(item_flags & layer))
4418                         return rte_flow_error_set(error, EINVAL,
4419                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4420                                                   NULL, "no TCP item in"
4421                                                   " pattern");
4422                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4423                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4424                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4425                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4426                         return rte_flow_error_set(error, EINVAL,
4427                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4428                                                   NULL,
4429                                                   "cannot decrease and increase"
4430                                                   " TCP acknowledgment number"
4431                                                   " at the same time");
4432         }
4433         return ret;
4434 }
4435
4436 /**
4437  * Validate the modify-header TTL actions.
4438  *
4439  * @param[in] action_flags
4440  *   Holds the actions detected until now.
4441  * @param[in] action
4442  *   Pointer to the modify action.
4443  * @param[in] item_flags
4444  *   Holds the items detected.
4445  * @param[out] error
4446  *   Pointer to error structure.
4447  *
4448  * @return
4449  *   0 on success, a negative errno value otherwise and rte_errno is set.
4450  */
4451 static int
4452 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4453                                    const struct rte_flow_action *action,
4454                                    const uint64_t item_flags,
4455                                    struct rte_flow_error *error)
4456 {
4457         int ret = 0;
4458         uint64_t layer;
4459
4460         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4461         if (!ret) {
4462                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4463                                  MLX5_FLOW_LAYER_INNER_L3 :
4464                                  MLX5_FLOW_LAYER_OUTER_L3;
4465                 if (!(item_flags & layer))
4466                         return rte_flow_error_set(error, EINVAL,
4467                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4468                                                   NULL,
4469                                                   "no IP protocol in pattern");
4470         }
4471         return ret;
4472 }
4473
4474 static int
4475 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4476 {
4477         switch (field) {
4478         case RTE_FLOW_FIELD_START:
4479                 return 32;
4480         case RTE_FLOW_FIELD_MAC_DST:
4481         case RTE_FLOW_FIELD_MAC_SRC:
4482                 return 48;
4483         case RTE_FLOW_FIELD_VLAN_TYPE:
4484                 return 16;
4485         case RTE_FLOW_FIELD_VLAN_ID:
4486                 return 12;
4487         case RTE_FLOW_FIELD_MAC_TYPE:
4488                 return 16;
4489         case RTE_FLOW_FIELD_IPV4_DSCP:
4490                 return 6;
4491         case RTE_FLOW_FIELD_IPV4_TTL:
4492                 return 8;
4493         case RTE_FLOW_FIELD_IPV4_SRC:
4494         case RTE_FLOW_FIELD_IPV4_DST:
4495                 return 32;
4496         case RTE_FLOW_FIELD_IPV6_DSCP:
4497                 return 6;
4498         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4499                 return 8;
4500         case RTE_FLOW_FIELD_IPV6_SRC:
4501         case RTE_FLOW_FIELD_IPV6_DST:
4502                 return 128;
4503         case RTE_FLOW_FIELD_TCP_PORT_SRC:
4504         case RTE_FLOW_FIELD_TCP_PORT_DST:
4505                 return 16;
4506         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4507         case RTE_FLOW_FIELD_TCP_ACK_NUM:
4508                 return 32;
4509         case RTE_FLOW_FIELD_TCP_FLAGS:
4510                 return 6;
4511         case RTE_FLOW_FIELD_UDP_PORT_SRC:
4512         case RTE_FLOW_FIELD_UDP_PORT_DST:
4513                 return 16;
4514         case RTE_FLOW_FIELD_VXLAN_VNI:
4515         case RTE_FLOW_FIELD_GENEVE_VNI:
4516                 return 24;
4517         case RTE_FLOW_FIELD_GTP_TEID:
4518         case RTE_FLOW_FIELD_TAG:
4519                 return 32;
4520         case RTE_FLOW_FIELD_MARK:
4521                 return 24;
4522         case RTE_FLOW_FIELD_META:
4523         case RTE_FLOW_FIELD_POINTER:
4524         case RTE_FLOW_FIELD_VALUE:
4525                 return 32;
4526         default:
4527                 MLX5_ASSERT(false);
4528         }
4529         return 0;
4530 }
4531
4532 /**
4533  * Validate the generic modify field actions.
4534  * @param[in] dev
4535  *   Pointer to the rte_eth_dev structure.
4536  * @param[in] action_flags
4537  *   Holds the actions detected until now.
4538  * @param[in] action
4539  *   Pointer to the modify action.
4540  * @param[in] attr
4541  *   Pointer to the flow attributes.
4542  * @param[out] error
4543  *   Pointer to error structure.
4544  *
4545  * @return
4546  *   Number of header fields to modify (0 or more) on success,
4547  *   a negative errno value otherwise and rte_errno is set.
4548  */
4549 static int
4550 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4551                                    const uint64_t action_flags,
4552                                    const struct rte_flow_action *action,
4553                                    const struct rte_flow_attr *attr,
4554                                    struct rte_flow_error *error)
4555 {
4556         int ret = 0;
4557         struct mlx5_priv *priv = dev->data->dev_private;
4558         struct mlx5_dev_config *config = &priv->config;
4559         const struct rte_flow_action_modify_field *action_modify_field =
4560                 action->conf;
4561         uint32_t dst_width =
4562                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4563         uint32_t src_width =
4564                 mlx5_flow_item_field_width(action_modify_field->src.field);
4565
4566         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4567         if (ret)
4568                 return ret;
4569
4570         if (action_modify_field->width == 0)
4571                 return rte_flow_error_set(error, EINVAL,
4572                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4573                                 "no bits are requested to be modified");
4574         else if (action_modify_field->width > dst_width ||
4575                  action_modify_field->width > src_width)
4576                 return rte_flow_error_set(error, EINVAL,
4577                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4578                                 "cannot modify more bits than"
4579                                 " the width of a field");
4580         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4581             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4582                 if ((action_modify_field->dst.offset +
4583                      action_modify_field->width > dst_width) ||
4584                     (action_modify_field->dst.offset % 32))
4585                         return rte_flow_error_set(error, EINVAL,
4586                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4587                                         "destination offset is too big"
4588                                         " or not aligned to 4 bytes");
4589                 if (action_modify_field->dst.level &&
4590                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4591                         return rte_flow_error_set(error, ENOTSUP,
4592                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4593                                         "inner header fields modification"
4594                                         " is not supported");
4595         }
4596         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4597             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4598                 if (!attr->transfer && !attr->group)
4599                         return rte_flow_error_set(error, ENOTSUP,
4600                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4601                                         "modify field action is not"
4602                                         " supported for group 0");
4603                 if ((action_modify_field->src.offset +
4604                      action_modify_field->width > src_width) ||
4605                     (action_modify_field->src.offset % 32))
4606                         return rte_flow_error_set(error, EINVAL,
4607                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4608                                         "source offset is too big"
4609                                         " or not aligned to 4 bytes");
4610                 if (action_modify_field->src.level &&
4611                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4612                         return rte_flow_error_set(error, ENOTSUP,
4613                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4614                                         "inner header fields modification"
4615                                         " is not supported");
4616         }
4617         if (action_modify_field->dst.field ==
4618             action_modify_field->src.field)
4619                 return rte_flow_error_set(error, EINVAL,
4620                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4621                                 "source and destination fields"
4622                                 " cannot be the same");
4623         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4624             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4625                 return rte_flow_error_set(error, EINVAL,
4626                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4627                                 "immediate value or a pointer to it"
4628                                 " cannot be used as a destination");
4629         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4630             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4631                 return rte_flow_error_set(error, ENOTSUP,
4632                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4633                                 "modifications of an arbitrary"
4634                                 " place in a packet is not supported");
4635         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4636             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4637                 return rte_flow_error_set(error, ENOTSUP,
4638                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4639                                 "modifications of the 802.1Q Tag"
4640                                 " Identifier is not supported");
4641         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4642             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4643                 return rte_flow_error_set(error, ENOTSUP,
4644                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4645                                 "modifications of the VXLAN Network"
4646                                 " Identifier is not supported");
4647         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4648             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4649                 return rte_flow_error_set(error, ENOTSUP,
4650                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4651                                 "modifications of the GENEVE Network"
4652                                 " Identifier is not supported");
4653         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4654             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4655             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4656             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4657                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4658                     !mlx5_flow_ext_mreg_supported(dev))
4659                         return rte_flow_error_set(error, ENOTSUP,
4660                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4661                                         "cannot modify mark or metadata without"
4662                                         " extended metadata register support");
4663         }
4664         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4665                 return rte_flow_error_set(error, ENOTSUP,
4666                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4667                                 "add and sub operations"
4668                                 " are not supported");
4669         return (action_modify_field->width / 32) +
4670                !!(action_modify_field->width % 32);
4671 }
4672
4673 /**
4674  * Validate jump action.
4675  *
4676  * @param[in] action
4677  *   Pointer to the jump action.
4678  * @param[in] action_flags
4679  *   Holds the actions detected until now.
4680  * @param[in] attributes
4681  *   Pointer to flow attributes
4682  * @param[in] external
4683  *   Action belongs to flow rule created by request external to PMD.
4684  * @param[out] error
4685  *   Pointer to error structure.
4686  *
4687  * @return
4688  *   0 on success, a negative errno value otherwise and rte_errno is set.
4689  */
4690 static int
4691 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4692                              const struct mlx5_flow_tunnel *tunnel,
4693                              const struct rte_flow_action *action,
4694                              uint64_t action_flags,
4695                              const struct rte_flow_attr *attributes,
4696                              bool external, struct rte_flow_error *error)
4697 {
4698         uint32_t target_group, table;
4699         int ret = 0;
4700         struct flow_grp_info grp_info = {
4701                 .external = !!external,
4702                 .transfer = !!attributes->transfer,
4703                 .fdb_def_rule = 1,
4704                 .std_tbl_fix = 0
4705         };
4706         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4707                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4708                 return rte_flow_error_set(error, EINVAL,
4709                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4710                                           "can't have 2 fate actions in"
4711                                           " same flow");
4712         if (action_flags & MLX5_FLOW_ACTION_METER)
4713                 return rte_flow_error_set(error, ENOTSUP,
4714                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4715                                           "jump with meter not support");
4716         if (!action->conf)
4717                 return rte_flow_error_set(error, EINVAL,
4718                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4719                                           NULL, "action configuration not set");
4720         target_group =
4721                 ((const struct rte_flow_action_jump *)action->conf)->group;
4722         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4723                                        &grp_info, error);
4724         if (ret)
4725                 return ret;
4726         if (attributes->group == target_group &&
4727             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4728                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4729                 return rte_flow_error_set(error, EINVAL,
4730                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4731                                           "target group must be other than"
4732                                           " the current flow group");
4733         return 0;
4734 }
4735
4736 /*
4737  * Validate the port_id action.
4738  *
4739  * @param[in] dev
4740  *   Pointer to rte_eth_dev structure.
4741  * @param[in] action_flags
4742  *   Bit-fields that holds the actions detected until now.
4743  * @param[in] action
4744  *   Port_id RTE action structure.
4745  * @param[in] attr
4746  *   Attributes of flow that includes this action.
4747  * @param[out] error
4748  *   Pointer to error structure.
4749  *
4750  * @return
4751  *   0 on success, a negative errno value otherwise and rte_errno is set.
4752  */
4753 static int
4754 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4755                                 uint64_t action_flags,
4756                                 const struct rte_flow_action *action,
4757                                 const struct rte_flow_attr *attr,
4758                                 struct rte_flow_error *error)
4759 {
4760         const struct rte_flow_action_port_id *port_id;
4761         struct mlx5_priv *act_priv;
4762         struct mlx5_priv *dev_priv;
4763         uint16_t port;
4764
4765         if (!attr->transfer)
4766                 return rte_flow_error_set(error, ENOTSUP,
4767                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4768                                           NULL,
4769                                           "port id action is valid in transfer"
4770                                           " mode only");
4771         if (!action || !action->conf)
4772                 return rte_flow_error_set(error, ENOTSUP,
4773                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4774                                           NULL,
4775                                           "port id action parameters must be"
4776                                           " specified");
4777         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4778                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4779                 return rte_flow_error_set(error, EINVAL,
4780                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4781                                           "can have only one fate actions in"
4782                                           " a flow");
4783         dev_priv = mlx5_dev_to_eswitch_info(dev);
4784         if (!dev_priv)
4785                 return rte_flow_error_set(error, rte_errno,
4786                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4787                                           NULL,
4788                                           "failed to obtain E-Switch info");
4789         port_id = action->conf;
4790         port = port_id->original ? dev->data->port_id : port_id->id;
4791         act_priv = mlx5_port_to_eswitch_info(port, false);
4792         if (!act_priv)
4793                 return rte_flow_error_set
4794                                 (error, rte_errno,
4795                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4796                                  "failed to obtain E-Switch port id for port");
4797         if (act_priv->domain_id != dev_priv->domain_id)
4798                 return rte_flow_error_set
4799                                 (error, EINVAL,
4800                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4801                                  "port does not belong to"
4802                                  " E-Switch being configured");
4803         return 0;
4804 }
4805
4806 /**
4807  * Get the maximum number of modify header actions.
4808  *
4809  * @param dev
4810  *   Pointer to rte_eth_dev structure.
4811  * @param flags
4812  *   Flags bits to check if root level.
4813  *
4814  * @return
4815  *   Max number of modify header actions device can support.
4816  */
4817 static inline unsigned int
4818 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4819                               uint64_t flags)
4820 {
4821         /*
4822          * There's no way to directly query the max capacity from FW.
4823          * The maximal value on root table should be assumed to be supported.
4824          */
4825         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4826                 return MLX5_MAX_MODIFY_NUM;
4827         else
4828                 return MLX5_ROOT_TBL_MODIFY_NUM;
4829 }
4830
4831 /**
4832  * Validate the meter action.
4833  *
4834  * @param[in] dev
4835  *   Pointer to rte_eth_dev structure.
4836  * @param[in] action_flags
4837  *   Bit-fields that holds the actions detected until now.
4838  * @param[in] action
4839  *   Pointer to the meter action.
4840  * @param[in] attr
4841  *   Attributes of flow that includes this action.
4842  * @param[out] error
4843  *   Pointer to error structure.
4844  *
4845  * @return
4846  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4847  */
4848 static int
4849 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4850                                 uint64_t action_flags,
4851                                 const struct rte_flow_action *action,
4852                                 const struct rte_flow_attr *attr,
4853                                 struct rte_flow_error *error)
4854 {
4855         struct mlx5_priv *priv = dev->data->dev_private;
4856         const struct rte_flow_action_meter *am = action->conf;
4857         struct mlx5_flow_meter *fm;
4858
4859         if (!am)
4860                 return rte_flow_error_set(error, EINVAL,
4861                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4862                                           "meter action conf is NULL");
4863
4864         if (action_flags & MLX5_FLOW_ACTION_METER)
4865                 return rte_flow_error_set(error, ENOTSUP,
4866                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4867                                           "meter chaining not support");
4868         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4869                 return rte_flow_error_set(error, ENOTSUP,
4870                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4871                                           "meter with jump not support");
4872         if (!priv->mtr_en)
4873                 return rte_flow_error_set(error, ENOTSUP,
4874                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4875                                           NULL,
4876                                           "meter action not supported");
4877         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4878         if (!fm)
4879                 return rte_flow_error_set(error, EINVAL,
4880                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4881                                           "Meter not found");
4882         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4883               (!fm->ingress && !attr->ingress && attr->egress) ||
4884               (!fm->egress && !attr->egress && attr->ingress))))
4885                 return rte_flow_error_set(error, EINVAL,
4886                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4887                                           "Flow attributes are either invalid "
4888                                           "or have a conflict with current "
4889                                           "meter attributes");
4890         return 0;
4891 }
4892
4893 /**
4894  * Validate the age action.
4895  *
4896  * @param[in] action_flags
4897  *   Holds the actions detected until now.
4898  * @param[in] action
4899  *   Pointer to the age action.
4900  * @param[in] dev
4901  *   Pointer to the Ethernet device structure.
4902  * @param[out] error
4903  *   Pointer to error structure.
4904  *
4905  * @return
4906  *   0 on success, a negative errno value otherwise and rte_errno is set.
4907  */
4908 static int
4909 flow_dv_validate_action_age(uint64_t action_flags,
4910                             const struct rte_flow_action *action,
4911                             struct rte_eth_dev *dev,
4912                             struct rte_flow_error *error)
4913 {
4914         struct mlx5_priv *priv = dev->data->dev_private;
4915         const struct rte_flow_action_age *age = action->conf;
4916
4917         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4918             !priv->sh->aso_age_mng))
4919                 return rte_flow_error_set(error, ENOTSUP,
4920                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4921                                           NULL,
4922                                           "age action not supported");
4923         if (!(action->conf))
4924                 return rte_flow_error_set(error, EINVAL,
4925                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4926                                           "configuration cannot be null");
4927         if (!(age->timeout))
4928                 return rte_flow_error_set(error, EINVAL,
4929                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4930                                           "invalid timeout value 0");
4931         if (action_flags & MLX5_FLOW_ACTION_AGE)
4932                 return rte_flow_error_set(error, EINVAL,
4933                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4934                                           "duplicate age actions set");
4935         return 0;
4936 }
4937
4938 /**
4939  * Validate the modify-header IPv4 DSCP actions.
4940  *
4941  * @param[in] action_flags
4942  *   Holds the actions detected until now.
4943  * @param[in] action
4944  *   Pointer to the modify action.
4945  * @param[in] item_flags
4946  *   Holds the items detected.
4947  * @param[out] error
4948  *   Pointer to error structure.
4949  *
4950  * @return
4951  *   0 on success, a negative errno value otherwise and rte_errno is set.
4952  */
4953 static int
4954 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4955                                          const struct rte_flow_action *action,
4956                                          const uint64_t item_flags,
4957                                          struct rte_flow_error *error)
4958 {
4959         int ret = 0;
4960
4961         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4962         if (!ret) {
4963                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4964                         return rte_flow_error_set(error, EINVAL,
4965                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4966                                                   NULL,
4967                                                   "no ipv4 item in pattern");
4968         }
4969         return ret;
4970 }
4971
4972 /**
4973  * Validate the modify-header IPv6 DSCP actions.
4974  *
4975  * @param[in] action_flags
4976  *   Holds the actions detected until now.
4977  * @param[in] action
4978  *   Pointer to the modify action.
4979  * @param[in] item_flags
4980  *   Holds the items detected.
4981  * @param[out] error
4982  *   Pointer to error structure.
4983  *
4984  * @return
4985  *   0 on success, a negative errno value otherwise and rte_errno is set.
4986  */
4987 static int
4988 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4989                                          const struct rte_flow_action *action,
4990                                          const uint64_t item_flags,
4991                                          struct rte_flow_error *error)
4992 {
4993         int ret = 0;
4994
4995         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4996         if (!ret) {
4997                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4998                         return rte_flow_error_set(error, EINVAL,
4999                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5000                                                   NULL,
5001                                                   "no ipv6 item in pattern");
5002         }
5003         return ret;
5004 }
5005
5006 /**
5007  * Match modify-header resource.
5008  *
5009  * @param list
5010  *   Pointer to the hash list.
5011  * @param entry
5012  *   Pointer to exist resource entry object.
5013  * @param key
5014  *   Key of the new entry.
5015  * @param ctx
5016  *   Pointer to new modify-header resource.
5017  *
5018  * @return
5019  *   0 on matching, non-zero otherwise.
5020  */
5021 int
5022 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5023                         struct mlx5_hlist_entry *entry,
5024                         uint64_t key __rte_unused, void *cb_ctx)
5025 {
5026         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5027         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5028         struct mlx5_flow_dv_modify_hdr_resource *resource =
5029                         container_of(entry, typeof(*resource), entry);
5030         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5031
5032         key_len += ref->actions_num * sizeof(ref->actions[0]);
5033         return ref->actions_num != resource->actions_num ||
5034                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5035 }
5036
5037 struct mlx5_hlist_entry *
5038 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5039                          void *cb_ctx)
5040 {
5041         struct mlx5_dev_ctx_shared *sh = list->ctx;
5042         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5043         struct mlx5dv_dr_domain *ns;
5044         struct mlx5_flow_dv_modify_hdr_resource *entry;
5045         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5046         int ret;
5047         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5048         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5049
5050         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5051                             SOCKET_ID_ANY);
5052         if (!entry) {
5053                 rte_flow_error_set(ctx->error, ENOMEM,
5054                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5055                                    "cannot allocate resource memory");
5056                 return NULL;
5057         }
5058         rte_memcpy(&entry->ft_type,
5059                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5060                    key_len + data_len);
5061         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5062                 ns = sh->fdb_domain;
5063         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5064                 ns = sh->tx_domain;
5065         else
5066                 ns = sh->rx_domain;
5067         ret = mlx5_flow_os_create_flow_action_modify_header
5068                                         (sh->ctx, ns, entry,
5069                                          data_len, &entry->action);
5070         if (ret) {
5071                 mlx5_free(entry);
5072                 rte_flow_error_set(ctx->error, ENOMEM,
5073                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5074                                    NULL, "cannot create modification action");
5075                 return NULL;
5076         }
5077         return &entry->entry;
5078 }
5079
5080 /**
5081  * Validate the sample action.
5082  *
5083  * @param[in, out] action_flags
5084  *   Holds the actions detected until now.
5085  * @param[in] action
5086  *   Pointer to the sample action.
5087  * @param[in] dev
5088  *   Pointer to the Ethernet device structure.
5089  * @param[in] attr
5090  *   Attributes of flow that includes this action.
5091  * @param[in] item_flags
5092  *   Holds the items detected.
5093  * @param[in] rss
5094  *   Pointer to the RSS action.
5095  * @param[out] sample_rss
5096  *   Pointer to the RSS action in sample action list.
5097  * @param[out] count
5098  *   Pointer to the COUNT action in sample action list.
5099  * @param[out] fdb_mirror_limit
5100  *   Pointer to the FDB mirror limitation flag.
5101  * @param[out] error
5102  *   Pointer to error structure.
5103  *
5104  * @return
5105  *   0 on success, a negative errno value otherwise and rte_errno is set.
5106  */
5107 static int
5108 flow_dv_validate_action_sample(uint64_t *action_flags,
5109                                const struct rte_flow_action *action,
5110                                struct rte_eth_dev *dev,
5111                                const struct rte_flow_attr *attr,
5112                                uint64_t item_flags,
5113                                const struct rte_flow_action_rss *rss,
5114                                const struct rte_flow_action_rss **sample_rss,
5115                                const struct rte_flow_action_count **count,
5116                                int *fdb_mirror_limit,
5117                                struct rte_flow_error *error)
5118 {
5119         struct mlx5_priv *priv = dev->data->dev_private;
5120         struct mlx5_dev_config *dev_conf = &priv->config;
5121         const struct rte_flow_action_sample *sample = action->conf;
5122         const struct rte_flow_action *act;
5123         uint64_t sub_action_flags = 0;
5124         uint16_t queue_index = 0xFFFF;
5125         int actions_n = 0;
5126         int ret;
5127
5128         if (!sample)
5129                 return rte_flow_error_set(error, EINVAL,
5130                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5131                                           "configuration cannot be NULL");
5132         if (sample->ratio == 0)
5133                 return rte_flow_error_set(error, EINVAL,
5134                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5135                                           "ratio value starts from 1");
5136         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5137                 return rte_flow_error_set(error, ENOTSUP,
5138                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5139                                           NULL,
5140                                           "sample action not supported");
5141         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5142                 return rte_flow_error_set(error, EINVAL,
5143                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5144                                           "Multiple sample actions not "
5145                                           "supported");
5146         if (*action_flags & MLX5_FLOW_ACTION_METER)
5147                 return rte_flow_error_set(error, EINVAL,
5148                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5149                                           "wrong action order, meter should "
5150                                           "be after sample action");
5151         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5152                 return rte_flow_error_set(error, EINVAL,
5153                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5154                                           "wrong action order, jump should "
5155                                           "be after sample action");
5156         act = sample->actions;
5157         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5158                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5159                         return rte_flow_error_set(error, ENOTSUP,
5160                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5161                                                   act, "too many actions");
5162                 switch (act->type) {
5163                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5164                         ret = mlx5_flow_validate_action_queue(act,
5165                                                               sub_action_flags,
5166                                                               dev,
5167                                                               attr, error);
5168                         if (ret < 0)
5169                                 return ret;
5170                         queue_index = ((const struct rte_flow_action_queue *)
5171                                                         (act->conf))->index;
5172                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5173                         ++actions_n;
5174                         break;
5175                 case RTE_FLOW_ACTION_TYPE_RSS:
5176                         *sample_rss = act->conf;
5177                         ret = mlx5_flow_validate_action_rss(act,
5178                                                             sub_action_flags,
5179                                                             dev, attr,
5180                                                             item_flags,
5181                                                             error);
5182                         if (ret < 0)
5183                                 return ret;
5184                         if (rss && *sample_rss &&
5185                             ((*sample_rss)->level != rss->level ||
5186                             (*sample_rss)->types != rss->types))
5187                                 return rte_flow_error_set(error, ENOTSUP,
5188                                         RTE_FLOW_ERROR_TYPE_ACTION,
5189                                         NULL,
5190                                         "Can't use the different RSS types "
5191                                         "or level in the same flow");
5192                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5193                                 queue_index = (*sample_rss)->queue[0];
5194                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5195                         ++actions_n;
5196                         break;
5197                 case RTE_FLOW_ACTION_TYPE_MARK:
5198                         ret = flow_dv_validate_action_mark(dev, act,
5199                                                            sub_action_flags,
5200                                                            attr, error);
5201                         if (ret < 0)
5202                                 return ret;
5203                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5204                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5205                                                 MLX5_FLOW_ACTION_MARK_EXT;
5206                         else
5207                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5208                         ++actions_n;
5209                         break;
5210                 case RTE_FLOW_ACTION_TYPE_COUNT:
5211                         ret = flow_dv_validate_action_count
5212                                 (dev, act,
5213                                  *action_flags | sub_action_flags,
5214                                  error);
5215                         if (ret < 0)
5216                                 return ret;
5217                         *count = act->conf;
5218                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5219                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5220                         ++actions_n;
5221                         break;
5222                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5223                         ret = flow_dv_validate_action_port_id(dev,
5224                                                               sub_action_flags,
5225                                                               act,
5226                                                               attr,
5227                                                               error);
5228                         if (ret)
5229                                 return ret;
5230                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5231                         ++actions_n;
5232                         break;
5233                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5234                         ret = flow_dv_validate_action_raw_encap_decap
5235                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5236                                  &actions_n, action, item_flags, error);
5237                         if (ret < 0)
5238                                 return ret;
5239                         ++actions_n;
5240                         break;
5241                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5242                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5243                         ret = flow_dv_validate_action_l2_encap(dev,
5244                                                                sub_action_flags,
5245                                                                act, attr,
5246                                                                error);
5247                         if (ret < 0)
5248                                 return ret;
5249                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5250                         ++actions_n;
5251                         break;
5252                 default:
5253                         return rte_flow_error_set(error, ENOTSUP,
5254                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5255                                                   NULL,
5256                                                   "Doesn't support optional "
5257                                                   "action");
5258                 }
5259         }
5260         if (attr->ingress && !attr->transfer) {
5261                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5262                                           MLX5_FLOW_ACTION_RSS)))
5263                         return rte_flow_error_set(error, EINVAL,
5264                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5265                                                   NULL,
5266                                                   "Ingress must has a dest "
5267                                                   "QUEUE for Sample");
5268         } else if (attr->egress && !attr->transfer) {
5269                 return rte_flow_error_set(error, ENOTSUP,
5270                                           RTE_FLOW_ERROR_TYPE_ACTION,
5271                                           NULL,
5272                                           "Sample Only support Ingress "
5273                                           "or E-Switch");
5274         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5275                 MLX5_ASSERT(attr->transfer);
5276                 if (sample->ratio > 1)
5277                         return rte_flow_error_set(error, ENOTSUP,
5278                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5279                                                   NULL,
5280                                                   "E-Switch doesn't support "
5281                                                   "any optional action "
5282                                                   "for sampling");
5283                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5284                         return rte_flow_error_set(error, ENOTSUP,
5285                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5286                                                   NULL,
5287                                                   "unsupported action QUEUE");
5288                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5289                         return rte_flow_error_set(error, ENOTSUP,
5290                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5291                                                   NULL,
5292                                                   "unsupported action QUEUE");
5293                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5294                         return rte_flow_error_set(error, EINVAL,
5295                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5296                                                   NULL,
5297                                                   "E-Switch must has a dest "
5298                                                   "port for mirroring");
5299                 if (!priv->config.hca_attr.reg_c_preserve &&
5300                      priv->representor_id != -1)
5301                         *fdb_mirror_limit = 1;
5302         }
5303         /* Continue validation for Xcap actions.*/
5304         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5305             (queue_index == 0xFFFF ||
5306              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5307                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5308                      MLX5_FLOW_XCAP_ACTIONS)
5309                         return rte_flow_error_set(error, ENOTSUP,
5310                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5311                                                   NULL, "encap and decap "
5312                                                   "combination aren't "
5313                                                   "supported");
5314                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5315                                                         MLX5_FLOW_ACTION_ENCAP))
5316                         return rte_flow_error_set(error, ENOTSUP,
5317                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5318                                                   NULL, "encap is not supported"
5319                                                   " for ingress traffic");
5320         }
5321         return 0;
5322 }
5323
5324 /**
5325  * Find existing modify-header resource or create and register a new one.
5326  *
5327  * @param dev[in, out]
5328  *   Pointer to rte_eth_dev structure.
5329  * @param[in, out] resource
5330  *   Pointer to modify-header resource.
5331  * @parm[in, out] dev_flow
5332  *   Pointer to the dev_flow.
5333  * @param[out] error
5334  *   pointer to error structure.
5335  *
5336  * @return
5337  *   0 on success otherwise -errno and errno is set.
5338  */
5339 static int
5340 flow_dv_modify_hdr_resource_register
5341                         (struct rte_eth_dev *dev,
5342                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5343                          struct mlx5_flow *dev_flow,
5344                          struct rte_flow_error *error)
5345 {
5346         struct mlx5_priv *priv = dev->data->dev_private;
5347         struct mlx5_dev_ctx_shared *sh = priv->sh;
5348         uint32_t key_len = sizeof(*resource) -
5349                            offsetof(typeof(*resource), ft_type) +
5350                            resource->actions_num * sizeof(resource->actions[0]);
5351         struct mlx5_hlist_entry *entry;
5352         struct mlx5_flow_cb_ctx ctx = {
5353                 .error = error,
5354                 .data = resource,
5355         };
5356         uint64_t key64;
5357
5358         resource->flags = dev_flow->dv.group ? 0 :
5359                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5360         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5361                                     resource->flags))
5362                 return rte_flow_error_set(error, EOVERFLOW,
5363                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5364                                           "too many modify header items");
5365         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5366         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5367         if (!entry)
5368                 return -rte_errno;
5369         resource = container_of(entry, typeof(*resource), entry);
5370         dev_flow->handle->dvh.modify_hdr = resource;
5371         return 0;
5372 }
5373
5374 /**
5375  * Get DV flow counter by index.
5376  *
5377  * @param[in] dev
5378  *   Pointer to the Ethernet device structure.
5379  * @param[in] idx
5380  *   mlx5 flow counter index in the container.
5381  * @param[out] ppool
5382  *   mlx5 flow counter pool in the container,
5383  *
5384  * @return
5385  *   Pointer to the counter, NULL otherwise.
5386  */
5387 static struct mlx5_flow_counter *
5388 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5389                            uint32_t idx,
5390                            struct mlx5_flow_counter_pool **ppool)
5391 {
5392         struct mlx5_priv *priv = dev->data->dev_private;
5393         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5394         struct mlx5_flow_counter_pool *pool;
5395
5396         /* Decrease to original index and clear shared bit. */
5397         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5398         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5399         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5400         MLX5_ASSERT(pool);
5401         if (ppool)
5402                 *ppool = pool;
5403         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5404 }
5405
5406 /**
5407  * Check the devx counter belongs to the pool.
5408  *
5409  * @param[in] pool
5410  *   Pointer to the counter pool.
5411  * @param[in] id
5412  *   The counter devx ID.
5413  *
5414  * @return
5415  *   True if counter belongs to the pool, false otherwise.
5416  */
5417 static bool
5418 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5419 {
5420         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5421                    MLX5_COUNTERS_PER_POOL;
5422
5423         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5424                 return true;
5425         return false;
5426 }
5427
5428 /**
5429  * Get a pool by devx counter ID.
5430  *
5431  * @param[in] cmng
5432  *   Pointer to the counter management.
5433  * @param[in] id
5434  *   The counter devx ID.
5435  *
5436  * @return
5437  *   The counter pool pointer if exists, NULL otherwise,
5438  */
5439 static struct mlx5_flow_counter_pool *
5440 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5441 {
5442         uint32_t i;
5443         struct mlx5_flow_counter_pool *pool = NULL;
5444
5445         rte_spinlock_lock(&cmng->pool_update_sl);
5446         /* Check last used pool. */
5447         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5448             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5449                 pool = cmng->pools[cmng->last_pool_idx];
5450                 goto out;
5451         }
5452         /* ID out of range means no suitable pool in the container. */
5453         if (id > cmng->max_id || id < cmng->min_id)
5454                 goto out;
5455         /*
5456          * Find the pool from the end of the container, since mostly counter
5457          * ID is sequence increasing, and the last pool should be the needed
5458          * one.
5459          */
5460         i = cmng->n_valid;
5461         while (i--) {
5462                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5463
5464                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5465                         pool = pool_tmp;
5466                         break;
5467                 }
5468         }
5469 out:
5470         rte_spinlock_unlock(&cmng->pool_update_sl);
5471         return pool;
5472 }
5473
5474 /**
5475  * Resize a counter container.
5476  *
5477  * @param[in] dev
5478  *   Pointer to the Ethernet device structure.
5479  *
5480  * @return
5481  *   0 on success, otherwise negative errno value and rte_errno is set.
5482  */
5483 static int
5484 flow_dv_container_resize(struct rte_eth_dev *dev)
5485 {
5486         struct mlx5_priv *priv = dev->data->dev_private;
5487         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5488         void *old_pools = cmng->pools;
5489         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5490         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5491         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5492
5493         if (!pools) {
5494                 rte_errno = ENOMEM;
5495                 return -ENOMEM;
5496         }
5497         if (old_pools)
5498                 memcpy(pools, old_pools, cmng->n *
5499                                        sizeof(struct mlx5_flow_counter_pool *));
5500         cmng->n = resize;
5501         cmng->pools = pools;
5502         if (old_pools)
5503                 mlx5_free(old_pools);
5504         return 0;
5505 }
5506
5507 /**
5508  * Query a devx flow counter.
5509  *
5510  * @param[in] dev
5511  *   Pointer to the Ethernet device structure.
5512  * @param[in] cnt
5513  *   Index to the flow counter.
5514  * @param[out] pkts
5515  *   The statistics value of packets.
5516  * @param[out] bytes
5517  *   The statistics value of bytes.
5518  *
5519  * @return
5520  *   0 on success, otherwise a negative errno value and rte_errno is set.
5521  */
5522 static inline int
5523 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5524                      uint64_t *bytes)
5525 {
5526         struct mlx5_priv *priv = dev->data->dev_private;
5527         struct mlx5_flow_counter_pool *pool = NULL;
5528         struct mlx5_flow_counter *cnt;
5529         int offset;
5530
5531         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5532         MLX5_ASSERT(pool);
5533         if (priv->sh->cmng.counter_fallback)
5534                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5535                                         0, pkts, bytes, 0, NULL, NULL, 0);
5536         rte_spinlock_lock(&pool->sl);
5537         if (!pool->raw) {
5538                 *pkts = 0;
5539                 *bytes = 0;
5540         } else {
5541                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5542                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5543                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5544         }
5545         rte_spinlock_unlock(&pool->sl);
5546         return 0;
5547 }
5548
5549 /**
5550  * Create and initialize a new counter pool.
5551  *
5552  * @param[in] dev
5553  *   Pointer to the Ethernet device structure.
5554  * @param[out] dcs
5555  *   The devX counter handle.
5556  * @param[in] age
5557  *   Whether the pool is for counter that was allocated for aging.
5558  * @param[in/out] cont_cur
5559  *   Pointer to the container pointer, it will be update in pool resize.
5560  *
5561  * @return
5562  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5563  */
5564 static struct mlx5_flow_counter_pool *
5565 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5566                     uint32_t age)
5567 {
5568         struct mlx5_priv *priv = dev->data->dev_private;
5569         struct mlx5_flow_counter_pool *pool;
5570         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5571         bool fallback = priv->sh->cmng.counter_fallback;
5572         uint32_t size = sizeof(*pool);
5573
5574         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5575         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5576         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5577         if (!pool) {
5578                 rte_errno = ENOMEM;
5579                 return NULL;
5580         }
5581         pool->raw = NULL;
5582         pool->is_aged = !!age;
5583         pool->query_gen = 0;
5584         pool->min_dcs = dcs;
5585         rte_spinlock_init(&pool->sl);
5586         rte_spinlock_init(&pool->csl);
5587         TAILQ_INIT(&pool->counters[0]);
5588         TAILQ_INIT(&pool->counters[1]);
5589         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5590         rte_spinlock_lock(&cmng->pool_update_sl);
5591         pool->index = cmng->n_valid;
5592         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5593                 mlx5_free(pool);
5594                 rte_spinlock_unlock(&cmng->pool_update_sl);
5595                 return NULL;
5596         }
5597         cmng->pools[pool->index] = pool;
5598         cmng->n_valid++;
5599         if (unlikely(fallback)) {
5600                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5601
5602                 if (base < cmng->min_id)
5603                         cmng->min_id = base;
5604                 if (base > cmng->max_id)
5605                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5606                 cmng->last_pool_idx = pool->index;
5607         }
5608         rte_spinlock_unlock(&cmng->pool_update_sl);
5609         return pool;
5610 }
5611
5612 /**
5613  * Prepare a new counter and/or a new counter pool.
5614  *
5615  * @param[in] dev
5616  *   Pointer to the Ethernet device structure.
5617  * @param[out] cnt_free
5618  *   Where to put the pointer of a new counter.
5619  * @param[in] age
5620  *   Whether the pool is for counter that was allocated for aging.
5621  *
5622  * @return
5623  *   The counter pool pointer and @p cnt_free is set on success,
5624  *   NULL otherwise and rte_errno is set.
5625  */
5626 static struct mlx5_flow_counter_pool *
5627 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5628                              struct mlx5_flow_counter **cnt_free,
5629                              uint32_t age)
5630 {
5631         struct mlx5_priv *priv = dev->data->dev_private;
5632         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5633         struct mlx5_flow_counter_pool *pool;
5634         struct mlx5_counters tmp_tq;
5635         struct mlx5_devx_obj *dcs = NULL;
5636         struct mlx5_flow_counter *cnt;
5637         enum mlx5_counter_type cnt_type =
5638                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5639         bool fallback = priv->sh->cmng.counter_fallback;
5640         uint32_t i;
5641
5642         if (fallback) {
5643                 /* bulk_bitmap must be 0 for single counter allocation. */
5644                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5645                 if (!dcs)
5646                         return NULL;
5647                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5648                 if (!pool) {
5649                         pool = flow_dv_pool_create(dev, dcs, age);
5650                         if (!pool) {
5651                                 mlx5_devx_cmd_destroy(dcs);
5652                                 return NULL;
5653                         }
5654                 }
5655                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5656                 cnt = MLX5_POOL_GET_CNT(pool, i);
5657                 cnt->pool = pool;
5658                 cnt->dcs_when_free = dcs;
5659                 *cnt_free = cnt;
5660                 return pool;
5661         }
5662         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5663         if (!dcs) {
5664                 rte_errno = ENODATA;
5665                 return NULL;
5666         }
5667         pool = flow_dv_pool_create(dev, dcs, age);
5668         if (!pool) {
5669                 mlx5_devx_cmd_destroy(dcs);
5670                 return NULL;
5671         }
5672         TAILQ_INIT(&tmp_tq);
5673         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5674                 cnt = MLX5_POOL_GET_CNT(pool, i);
5675                 cnt->pool = pool;
5676                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5677         }
5678         rte_spinlock_lock(&cmng->csl[cnt_type]);
5679         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5680         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5681         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5682         (*cnt_free)->pool = pool;
5683         return pool;
5684 }
5685
5686 /**
5687  * Allocate a flow counter.
5688  *
5689  * @param[in] dev
5690  *   Pointer to the Ethernet device structure.
5691  * @param[in] age
5692  *   Whether the counter was allocated for aging.
5693  *
5694  * @return
5695  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5696  */
5697 static uint32_t
5698 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5699 {
5700         struct mlx5_priv *priv = dev->data->dev_private;
5701         struct mlx5_flow_counter_pool *pool = NULL;
5702         struct mlx5_flow_counter *cnt_free = NULL;
5703         bool fallback = priv->sh->cmng.counter_fallback;
5704         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5705         enum mlx5_counter_type cnt_type =
5706                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5707         uint32_t cnt_idx;
5708
5709         if (!priv->config.devx) {
5710                 rte_errno = ENOTSUP;
5711                 return 0;
5712         }
5713         /* Get free counters from container. */
5714         rte_spinlock_lock(&cmng->csl[cnt_type]);
5715         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5716         if (cnt_free)
5717                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5718         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5719         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5720                 goto err;
5721         pool = cnt_free->pool;
5722         if (fallback)
5723                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5724         /* Create a DV counter action only in the first time usage. */
5725         if (!cnt_free->action) {
5726                 uint16_t offset;
5727                 struct mlx5_devx_obj *dcs;
5728                 int ret;
5729
5730                 if (!fallback) {
5731                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5732                         dcs = pool->min_dcs;
5733                 } else {
5734                         offset = 0;
5735                         dcs = cnt_free->dcs_when_free;
5736                 }
5737                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5738                                                             &cnt_free->action);
5739                 if (ret) {
5740                         rte_errno = errno;
5741                         goto err;
5742                 }
5743         }
5744         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5745                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5746         /* Update the counter reset values. */
5747         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5748                                  &cnt_free->bytes))
5749                 goto err;
5750         if (!fallback && !priv->sh->cmng.query_thread_on)
5751                 /* Start the asynchronous batch query by the host thread. */
5752                 mlx5_set_query_alarm(priv->sh);
5753         return cnt_idx;
5754 err:
5755         if (cnt_free) {
5756                 cnt_free->pool = pool;
5757                 if (fallback)
5758                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5759                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5760                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5761                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5762         }
5763         return 0;
5764 }
5765
5766 /**
5767  * Allocate a shared flow counter.
5768  *
5769  * @param[in] ctx
5770  *   Pointer to the shared counter configuration.
5771  * @param[in] data
5772  *   Pointer to save the allocated counter index.
5773  *
5774  * @return
5775  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5776  */
5777
5778 static int32_t
5779 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5780 {
5781         struct mlx5_shared_counter_conf *conf = ctx;
5782         struct rte_eth_dev *dev = conf->dev;
5783         struct mlx5_flow_counter *cnt;
5784
5785         data->dword = flow_dv_counter_alloc(dev, 0);
5786         data->dword |= MLX5_CNT_SHARED_OFFSET;
5787         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5788         cnt->shared_info.id = conf->id;
5789         return 0;
5790 }
5791
5792 /**
5793  * Get a shared flow counter.
5794  *
5795  * @param[in] dev
5796  *   Pointer to the Ethernet device structure.
5797  * @param[in] id
5798  *   Counter identifier.
5799  *
5800  * @return
5801  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5802  */
5803 static uint32_t
5804 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5805 {
5806         struct mlx5_priv *priv = dev->data->dev_private;
5807         struct mlx5_shared_counter_conf conf = {
5808                 .dev = dev,
5809                 .id = id,
5810         };
5811         union mlx5_l3t_data data = {
5812                 .dword = 0,
5813         };
5814
5815         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5816                                flow_dv_counter_alloc_shared_cb, &conf);
5817         return data.dword;
5818 }
5819
5820 /**
5821  * Get age param from counter index.
5822  *
5823  * @param[in] dev
5824  *   Pointer to the Ethernet device structure.
5825  * @param[in] counter
5826  *   Index to the counter handler.
5827  *
5828  * @return
5829  *   The aging parameter specified for the counter index.
5830  */
5831 static struct mlx5_age_param*
5832 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5833                                 uint32_t counter)
5834 {
5835         struct mlx5_flow_counter *cnt;
5836         struct mlx5_flow_counter_pool *pool = NULL;
5837
5838         flow_dv_counter_get_by_idx(dev, counter, &pool);
5839         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5840         cnt = MLX5_POOL_GET_CNT(pool, counter);
5841         return MLX5_CNT_TO_AGE(cnt);
5842 }
5843
5844 /**
5845  * Remove a flow counter from aged counter list.
5846  *
5847  * @param[in] dev
5848  *   Pointer to the Ethernet device structure.
5849  * @param[in] counter
5850  *   Index to the counter handler.
5851  * @param[in] cnt
5852  *   Pointer to the counter handler.
5853  */
5854 static void
5855 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5856                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5857 {
5858         struct mlx5_age_info *age_info;
5859         struct mlx5_age_param *age_param;
5860         struct mlx5_priv *priv = dev->data->dev_private;
5861         uint16_t expected = AGE_CANDIDATE;
5862
5863         age_info = GET_PORT_AGE_INFO(priv);
5864         age_param = flow_dv_counter_idx_get_age(dev, counter);
5865         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5866                                          AGE_FREE, false, __ATOMIC_RELAXED,
5867                                          __ATOMIC_RELAXED)) {
5868                 /**
5869                  * We need the lock even it is age timeout,
5870                  * since counter may still in process.
5871                  */
5872                 rte_spinlock_lock(&age_info->aged_sl);
5873                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5874                 rte_spinlock_unlock(&age_info->aged_sl);
5875                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5876         }
5877 }
5878
5879 /**
5880  * Release a flow counter.
5881  *
5882  * @param[in] dev
5883  *   Pointer to the Ethernet device structure.
5884  * @param[in] counter
5885  *   Index to the counter handler.
5886  */
5887 static void
5888 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5889 {
5890         struct mlx5_priv *priv = dev->data->dev_private;
5891         struct mlx5_flow_counter_pool *pool = NULL;
5892         struct mlx5_flow_counter *cnt;
5893         enum mlx5_counter_type cnt_type;
5894
5895         if (!counter)
5896                 return;
5897         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5898         MLX5_ASSERT(pool);
5899         if (IS_SHARED_CNT(counter) &&
5900             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5901                 return;
5902         if (pool->is_aged)
5903                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5904         cnt->pool = pool;
5905         /*
5906          * Put the counter back to list to be updated in none fallback mode.
5907          * Currently, we are using two list alternately, while one is in query,
5908          * add the freed counter to the other list based on the pool query_gen
5909          * value. After query finishes, add counter the list to the global
5910          * container counter list. The list changes while query starts. In
5911          * this case, lock will not be needed as query callback and release
5912          * function both operate with the different list.
5913          *
5914          */
5915         if (!priv->sh->cmng.counter_fallback) {
5916                 rte_spinlock_lock(&pool->csl);
5917                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5918                 rte_spinlock_unlock(&pool->csl);
5919         } else {
5920                 cnt->dcs_when_free = cnt->dcs_when_active;
5921                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5922                                            MLX5_COUNTER_TYPE_ORIGIN;
5923                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5924                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5925                                   cnt, next);
5926                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5927         }
5928 }
5929
5930 /**
5931  * Verify the @p attributes will be correctly understood by the NIC and store
5932  * them in the @p flow if everything is correct.
5933  *
5934  * @param[in] dev
5935  *   Pointer to dev struct.
5936  * @param[in] attributes
5937  *   Pointer to flow attributes
5938  * @param[in] external
5939  *   This flow rule is created by request external to PMD.
5940  * @param[out] error
5941  *   Pointer to error structure.
5942  *
5943  * @return
5944  *   - 0 on success and non root table.
5945  *   - 1 on success and root table.
5946  *   - a negative errno value otherwise and rte_errno is set.
5947  */
5948 static int
5949 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5950                             const struct mlx5_flow_tunnel *tunnel,
5951                             const struct rte_flow_attr *attributes,
5952                             const struct flow_grp_info *grp_info,
5953                             struct rte_flow_error *error)
5954 {
5955         struct mlx5_priv *priv = dev->data->dev_private;
5956         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5957         int ret = 0;
5958
5959 #ifndef HAVE_MLX5DV_DR
5960         RTE_SET_USED(tunnel);
5961         RTE_SET_USED(grp_info);
5962         if (attributes->group)
5963                 return rte_flow_error_set(error, ENOTSUP,
5964                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5965                                           NULL,
5966                                           "groups are not supported");
5967 #else
5968         uint32_t table = 0;
5969
5970         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5971                                        grp_info, error);
5972         if (ret)
5973                 return ret;
5974         if (!table)
5975                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5976 #endif
5977         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5978             attributes->priority > lowest_priority)
5979                 return rte_flow_error_set(error, ENOTSUP,
5980                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5981                                           NULL,
5982                                           "priority out of range");
5983         if (attributes->transfer) {
5984                 if (!priv->config.dv_esw_en)
5985                         return rte_flow_error_set
5986                                 (error, ENOTSUP,
5987                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5988                                  "E-Switch dr is not supported");
5989                 if (!(priv->representor || priv->master))
5990                         return rte_flow_error_set
5991                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5992                                  NULL, "E-Switch configuration can only be"
5993                                  " done by a master or a representor device");
5994                 if (attributes->egress)
5995                         return rte_flow_error_set
5996                                 (error, ENOTSUP,
5997                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5998                                  "egress is not supported");
5999         }
6000         if (!(attributes->egress ^ attributes->ingress))
6001                 return rte_flow_error_set(error, ENOTSUP,
6002                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6003                                           "must specify exactly one of "
6004                                           "ingress or egress");
6005         return ret;
6006 }
6007
6008 /**
6009  * Internal validation function. For validating both actions and items.
6010  *
6011  * @param[in] dev
6012  *   Pointer to the rte_eth_dev structure.
6013  * @param[in] attr
6014  *   Pointer to the flow attributes.
6015  * @param[in] items
6016  *   Pointer to the list of items.
6017  * @param[in] actions
6018  *   Pointer to the list of actions.
6019  * @param[in] external
6020  *   This flow rule is created by request external to PMD.
6021  * @param[in] hairpin
6022  *   Number of hairpin TX actions, 0 means classic flow.
6023  * @param[out] error
6024  *   Pointer to the error structure.
6025  *
6026  * @return
6027  *   0 on success, a negative errno value otherwise and rte_errno is set.
6028  */
6029 static int
6030 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6031                  const struct rte_flow_item items[],
6032                  const struct rte_flow_action actions[],
6033                  bool external, int hairpin, struct rte_flow_error *error)
6034 {
6035         int ret;
6036         uint64_t action_flags = 0;
6037         uint64_t item_flags = 0;
6038         uint64_t last_item = 0;
6039         uint8_t next_protocol = 0xff;
6040         uint16_t ether_type = 0;
6041         int actions_n = 0;
6042         uint8_t item_ipv6_proto = 0;
6043         int fdb_mirror_limit = 0;
6044         int modify_after_mirror = 0;
6045         const struct rte_flow_item *geneve_item = NULL;
6046         const struct rte_flow_item *gre_item = NULL;
6047         const struct rte_flow_item *gtp_item = NULL;
6048         const struct rte_flow_action_raw_decap *decap;
6049         const struct rte_flow_action_raw_encap *encap;
6050         const struct rte_flow_action_rss *rss = NULL;
6051         const struct rte_flow_action_rss *sample_rss = NULL;
6052         const struct rte_flow_action_count *count = NULL;
6053         const struct rte_flow_action_count *sample_count = NULL;
6054         const struct rte_flow_item_tcp nic_tcp_mask = {
6055                 .hdr = {
6056                         .tcp_flags = 0xFF,
6057                         .src_port = RTE_BE16(UINT16_MAX),
6058                         .dst_port = RTE_BE16(UINT16_MAX),
6059                 }
6060         };
6061         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6062                 .hdr = {
6063                         .src_addr =
6064                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6065                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6066                         .dst_addr =
6067                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6068                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6069                         .vtc_flow = RTE_BE32(0xffffffff),
6070                         .proto = 0xff,
6071                         .hop_limits = 0xff,
6072                 },
6073                 .has_frag_ext = 1,
6074         };
6075         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6076                 .hdr = {
6077                         .common = {
6078                                 .u32 =
6079                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6080                                         .type = 0xFF,
6081                                         }).u32),
6082                         },
6083                         .dummy[0] = 0xffffffff,
6084                 },
6085         };
6086         struct mlx5_priv *priv = dev->data->dev_private;
6087         struct mlx5_dev_config *dev_conf = &priv->config;
6088         uint16_t queue_index = 0xFFFF;
6089         const struct rte_flow_item_vlan *vlan_m = NULL;
6090         uint32_t rw_act_num = 0;
6091         uint64_t is_root;
6092         const struct mlx5_flow_tunnel *tunnel;
6093         struct flow_grp_info grp_info = {
6094                 .external = !!external,
6095                 .transfer = !!attr->transfer,
6096                 .fdb_def_rule = !!priv->fdb_def_rule,
6097         };
6098         const struct rte_eth_hairpin_conf *conf;
6099
6100         if (items == NULL)
6101                 return -1;
6102         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6103                 tunnel = flow_items_to_tunnel(items);
6104                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6105                                 MLX5_FLOW_ACTION_DECAP;
6106         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6107                 tunnel = flow_actions_to_tunnel(actions);
6108                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6109         } else {
6110                 tunnel = NULL;
6111         }
6112         if (tunnel && priv->representor)
6113                 return rte_flow_error_set(error, ENOTSUP,
6114                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6115                                           "decap not supported "
6116                                           "for VF representor");
6117         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6118                                 (dev, tunnel, attr, items, actions);
6119         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6120         if (ret < 0)
6121                 return ret;
6122         is_root = (uint64_t)ret;
6123         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6124                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6125                 int type = items->type;
6126
6127                 if (!mlx5_flow_os_item_supported(type))
6128                         return rte_flow_error_set(error, ENOTSUP,
6129                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6130                                                   NULL, "item not supported");
6131                 switch (type) {
6132                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6133                         if (items[0].type != (typeof(items[0].type))
6134                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6135                                 return rte_flow_error_set
6136                                                 (error, EINVAL,
6137                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6138                                                 NULL, "MLX5 private items "
6139                                                 "must be the first");
6140                         break;
6141                 case RTE_FLOW_ITEM_TYPE_VOID:
6142                         break;
6143                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6144                         ret = flow_dv_validate_item_port_id
6145                                         (dev, items, attr, item_flags, error);
6146                         if (ret < 0)
6147                                 return ret;
6148                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6149                         break;
6150                 case RTE_FLOW_ITEM_TYPE_ETH:
6151                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6152                                                           true, error);
6153                         if (ret < 0)
6154                                 return ret;
6155                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6156                                              MLX5_FLOW_LAYER_OUTER_L2;
6157                         if (items->mask != NULL && items->spec != NULL) {
6158                                 ether_type =
6159                                         ((const struct rte_flow_item_eth *)
6160                                          items->spec)->type;
6161                                 ether_type &=
6162                                         ((const struct rte_flow_item_eth *)
6163                                          items->mask)->type;
6164                                 ether_type = rte_be_to_cpu_16(ether_type);
6165                         } else {
6166                                 ether_type = 0;
6167                         }
6168                         break;
6169                 case RTE_FLOW_ITEM_TYPE_VLAN:
6170                         ret = flow_dv_validate_item_vlan(items, item_flags,
6171                                                          dev, error);
6172                         if (ret < 0)
6173                                 return ret;
6174                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6175                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6176                         if (items->mask != NULL && items->spec != NULL) {
6177                                 ether_type =
6178                                         ((const struct rte_flow_item_vlan *)
6179                                          items->spec)->inner_type;
6180                                 ether_type &=
6181                                         ((const struct rte_flow_item_vlan *)
6182                                          items->mask)->inner_type;
6183                                 ether_type = rte_be_to_cpu_16(ether_type);
6184                         } else {
6185                                 ether_type = 0;
6186                         }
6187                         /* Store outer VLAN mask for of_push_vlan action. */
6188                         if (!tunnel)
6189                                 vlan_m = items->mask;
6190                         break;
6191                 case RTE_FLOW_ITEM_TYPE_IPV4:
6192                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6193                                                   &item_flags, &tunnel);
6194                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6195                                                          last_item, ether_type,
6196                                                          error);
6197                         if (ret < 0)
6198                                 return ret;
6199                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6200                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6201                         if (items->mask != NULL &&
6202                             ((const struct rte_flow_item_ipv4 *)
6203                              items->mask)->hdr.next_proto_id) {
6204                                 next_protocol =
6205                                         ((const struct rte_flow_item_ipv4 *)
6206                                          (items->spec))->hdr.next_proto_id;
6207                                 next_protocol &=
6208                                         ((const struct rte_flow_item_ipv4 *)
6209                                          (items->mask))->hdr.next_proto_id;
6210                         } else {
6211                                 /* Reset for inner layer. */
6212                                 next_protocol = 0xff;
6213                         }
6214                         break;
6215                 case RTE_FLOW_ITEM_TYPE_IPV6:
6216                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6217                                                   &item_flags, &tunnel);
6218                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6219                                                            last_item,
6220                                                            ether_type,
6221                                                            &nic_ipv6_mask,
6222                                                            error);
6223                         if (ret < 0)
6224                                 return ret;
6225                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6226                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6227                         if (items->mask != NULL &&
6228                             ((const struct rte_flow_item_ipv6 *)
6229                              items->mask)->hdr.proto) {
6230                                 item_ipv6_proto =
6231                                         ((const struct rte_flow_item_ipv6 *)
6232                                          items->spec)->hdr.proto;
6233                                 next_protocol =
6234                                         ((const struct rte_flow_item_ipv6 *)
6235                                          items->spec)->hdr.proto;
6236                                 next_protocol &=
6237                                         ((const struct rte_flow_item_ipv6 *)
6238                                          items->mask)->hdr.proto;
6239                         } else {
6240                                 /* Reset for inner layer. */
6241                                 next_protocol = 0xff;
6242                         }
6243                         break;
6244                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6245                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6246                                                                   item_flags,
6247                                                                   error);
6248                         if (ret < 0)
6249                                 return ret;
6250                         last_item = tunnel ?
6251                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6252                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6253                         if (items->mask != NULL &&
6254                             ((const struct rte_flow_item_ipv6_frag_ext *)
6255                              items->mask)->hdr.next_header) {
6256                                 next_protocol =
6257                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6258                                  items->spec)->hdr.next_header;
6259                                 next_protocol &=
6260                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6261                                  items->mask)->hdr.next_header;
6262                         } else {
6263                                 /* Reset for inner layer. */
6264                                 next_protocol = 0xff;
6265                         }
6266                         break;
6267                 case RTE_FLOW_ITEM_TYPE_TCP:
6268                         ret = mlx5_flow_validate_item_tcp
6269                                                 (items, item_flags,
6270                                                  next_protocol,
6271                                                  &nic_tcp_mask,
6272                                                  error);
6273                         if (ret < 0)
6274                                 return ret;
6275                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6276                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6277                         break;
6278                 case RTE_FLOW_ITEM_TYPE_UDP:
6279                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6280                                                           next_protocol,
6281                                                           error);
6282                         if (ret < 0)
6283                                 return ret;
6284                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6285                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6286                         break;
6287                 case RTE_FLOW_ITEM_TYPE_GRE:
6288                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6289                                                           next_protocol, error);
6290                         if (ret < 0)
6291                                 return ret;
6292                         gre_item = items;
6293                         last_item = MLX5_FLOW_LAYER_GRE;
6294                         break;
6295                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6296                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6297                                                             next_protocol,
6298                                                             error);
6299                         if (ret < 0)
6300                                 return ret;
6301                         last_item = MLX5_FLOW_LAYER_NVGRE;
6302                         break;
6303                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6304                         ret = mlx5_flow_validate_item_gre_key
6305                                 (items, item_flags, gre_item, error);
6306                         if (ret < 0)
6307                                 return ret;
6308                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6309                         break;
6310                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6311                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6312                                                             error);
6313                         if (ret < 0)
6314                                 return ret;
6315                         last_item = MLX5_FLOW_LAYER_VXLAN;
6316                         break;
6317                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6318                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6319                                                                 item_flags, dev,
6320                                                                 error);
6321                         if (ret < 0)
6322                                 return ret;
6323                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6324                         break;
6325                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6326                         ret = mlx5_flow_validate_item_geneve(items,
6327                                                              item_flags, dev,
6328                                                              error);
6329                         if (ret < 0)
6330                                 return ret;
6331                         geneve_item = items;
6332                         last_item = MLX5_FLOW_LAYER_GENEVE;
6333                         break;
6334                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6335                         ret = mlx5_flow_validate_item_geneve_opt(items,
6336                                                                  last_item,
6337                                                                  geneve_item,
6338                                                                  dev,
6339                                                                  error);
6340                         if (ret < 0)
6341                                 return ret;
6342                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6343                         break;
6344                 case RTE_FLOW_ITEM_TYPE_MPLS:
6345                         ret = mlx5_flow_validate_item_mpls(dev, items,
6346                                                            item_flags,
6347                                                            last_item, error);
6348                         if (ret < 0)
6349                                 return ret;
6350                         last_item = MLX5_FLOW_LAYER_MPLS;
6351                         break;
6352
6353                 case RTE_FLOW_ITEM_TYPE_MARK:
6354                         ret = flow_dv_validate_item_mark(dev, items, attr,
6355                                                          error);
6356                         if (ret < 0)
6357                                 return ret;
6358                         last_item = MLX5_FLOW_ITEM_MARK;
6359                         break;
6360                 case RTE_FLOW_ITEM_TYPE_META:
6361                         ret = flow_dv_validate_item_meta(dev, items, attr,
6362                                                          error);
6363                         if (ret < 0)
6364                                 return ret;
6365                         last_item = MLX5_FLOW_ITEM_METADATA;
6366                         break;
6367                 case RTE_FLOW_ITEM_TYPE_ICMP:
6368                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6369                                                            next_protocol,
6370                                                            error);
6371                         if (ret < 0)
6372                                 return ret;
6373                         last_item = MLX5_FLOW_LAYER_ICMP;
6374                         break;
6375                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6376                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6377                                                             next_protocol,
6378                                                             error);
6379                         if (ret < 0)
6380                                 return ret;
6381                         item_ipv6_proto = IPPROTO_ICMPV6;
6382                         last_item = MLX5_FLOW_LAYER_ICMP6;
6383                         break;
6384                 case RTE_FLOW_ITEM_TYPE_TAG:
6385                         ret = flow_dv_validate_item_tag(dev, items,
6386                                                         attr, error);
6387                         if (ret < 0)
6388                                 return ret;
6389                         last_item = MLX5_FLOW_ITEM_TAG;
6390                         break;
6391                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6392                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6393                         break;
6394                 case RTE_FLOW_ITEM_TYPE_GTP:
6395                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6396                                                         error);
6397                         if (ret < 0)
6398                                 return ret;
6399                         gtp_item = items;
6400                         last_item = MLX5_FLOW_LAYER_GTP;
6401                         break;
6402                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6403                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6404                                                             gtp_item, attr,
6405                                                             error);
6406                         if (ret < 0)
6407                                 return ret;
6408                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6409                         break;
6410                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6411                         /* Capacity will be checked in the translate stage. */
6412                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6413                                                             last_item,
6414                                                             ether_type,
6415                                                             &nic_ecpri_mask,
6416                                                             error);
6417                         if (ret < 0)
6418                                 return ret;
6419                         last_item = MLX5_FLOW_LAYER_ECPRI;
6420                         break;
6421                 default:
6422                         return rte_flow_error_set(error, ENOTSUP,
6423                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6424                                                   NULL, "item not supported");
6425                 }
6426                 item_flags |= last_item;
6427         }
6428         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6429                 int type = actions->type;
6430
6431                 if (!mlx5_flow_os_action_supported(type))
6432                         return rte_flow_error_set(error, ENOTSUP,
6433                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6434                                                   actions,
6435                                                   "action not supported");
6436                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6437                         return rte_flow_error_set(error, ENOTSUP,
6438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6439                                                   actions, "too many actions");
6440                 switch (type) {
6441                 case RTE_FLOW_ACTION_TYPE_VOID:
6442                         break;
6443                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6444                         ret = flow_dv_validate_action_port_id(dev,
6445                                                               action_flags,
6446                                                               actions,
6447                                                               attr,
6448                                                               error);
6449                         if (ret)
6450                                 return ret;
6451                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6452                         ++actions_n;
6453                         break;
6454                 case RTE_FLOW_ACTION_TYPE_FLAG:
6455                         ret = flow_dv_validate_action_flag(dev, action_flags,
6456                                                            attr, error);
6457                         if (ret < 0)
6458                                 return ret;
6459                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6460                                 /* Count all modify-header actions as one. */
6461                                 if (!(action_flags &
6462                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6463                                         ++actions_n;
6464                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6465                                                 MLX5_FLOW_ACTION_MARK_EXT;
6466                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6467                                         modify_after_mirror = 1;
6468
6469                         } else {
6470                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6471                                 ++actions_n;
6472                         }
6473                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6474                         break;
6475                 case RTE_FLOW_ACTION_TYPE_MARK:
6476                         ret = flow_dv_validate_action_mark(dev, actions,
6477                                                            action_flags,
6478                                                            attr, error);
6479                         if (ret < 0)
6480                                 return ret;
6481                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6482                                 /* Count all modify-header actions as one. */
6483                                 if (!(action_flags &
6484                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6485                                         ++actions_n;
6486                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6487                                                 MLX5_FLOW_ACTION_MARK_EXT;
6488                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6489                                         modify_after_mirror = 1;
6490                         } else {
6491                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6492                                 ++actions_n;
6493                         }
6494                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6495                         break;
6496                 case RTE_FLOW_ACTION_TYPE_SET_META:
6497                         ret = flow_dv_validate_action_set_meta(dev, actions,
6498                                                                action_flags,
6499                                                                attr, error);
6500                         if (ret < 0)
6501                                 return ret;
6502                         /* Count all modify-header actions as one action. */
6503                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6504                                 ++actions_n;
6505                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6506                                 modify_after_mirror = 1;
6507                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6508                         rw_act_num += MLX5_ACT_NUM_SET_META;
6509                         break;
6510                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6511                         ret = flow_dv_validate_action_set_tag(dev, actions,
6512                                                               action_flags,
6513                                                               attr, error);
6514                         if (ret < 0)
6515                                 return ret;
6516                         /* Count all modify-header actions as one action. */
6517                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6518                                 ++actions_n;
6519                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6520                                 modify_after_mirror = 1;
6521                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6522                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6523                         break;
6524                 case RTE_FLOW_ACTION_TYPE_DROP:
6525                         ret = mlx5_flow_validate_action_drop(action_flags,
6526                                                              attr, error);
6527                         if (ret < 0)
6528                                 return ret;
6529                         action_flags |= MLX5_FLOW_ACTION_DROP;
6530                         ++actions_n;
6531                         break;
6532                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6533                         ret = mlx5_flow_validate_action_queue(actions,
6534                                                               action_flags, dev,
6535                                                               attr, error);
6536                         if (ret < 0)
6537                                 return ret;
6538                         queue_index = ((const struct rte_flow_action_queue *)
6539                                                         (actions->conf))->index;
6540                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6541                         ++actions_n;
6542                         break;
6543                 case RTE_FLOW_ACTION_TYPE_RSS:
6544                         rss = actions->conf;
6545                         ret = mlx5_flow_validate_action_rss(actions,
6546                                                             action_flags, dev,
6547                                                             attr, item_flags,
6548                                                             error);
6549                         if (ret < 0)
6550                                 return ret;
6551                         if (rss && sample_rss &&
6552                             (sample_rss->level != rss->level ||
6553                             sample_rss->types != rss->types))
6554                                 return rte_flow_error_set(error, ENOTSUP,
6555                                         RTE_FLOW_ERROR_TYPE_ACTION,
6556                                         NULL,
6557                                         "Can't use the different RSS types "
6558                                         "or level in the same flow");
6559                         if (rss != NULL && rss->queue_num)
6560                                 queue_index = rss->queue[0];
6561                         action_flags |= MLX5_FLOW_ACTION_RSS;
6562                         ++actions_n;
6563                         break;
6564                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6565                         ret =
6566                         mlx5_flow_validate_action_default_miss(action_flags,
6567                                         attr, error);
6568                         if (ret < 0)
6569                                 return ret;
6570                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6571                         ++actions_n;
6572                         break;
6573                 case RTE_FLOW_ACTION_TYPE_COUNT:
6574                         ret = flow_dv_validate_action_count(dev, actions,
6575                                                             action_flags,
6576                                                             error);
6577                         if (ret < 0)
6578                                 return ret;
6579                         count = actions->conf;
6580                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6581                         ++actions_n;
6582                         break;
6583                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6584                         if (flow_dv_validate_action_pop_vlan(dev,
6585                                                              action_flags,
6586                                                              actions,
6587                                                              item_flags, attr,
6588                                                              error))
6589                                 return -rte_errno;
6590                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6591                         ++actions_n;
6592                         break;
6593                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6594                         ret = flow_dv_validate_action_push_vlan(dev,
6595                                                                 action_flags,
6596                                                                 vlan_m,
6597                                                                 actions, attr,
6598                                                                 error);
6599                         if (ret < 0)
6600                                 return ret;
6601                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6602                         ++actions_n;
6603                         break;
6604                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6605                         ret = flow_dv_validate_action_set_vlan_pcp
6606                                                 (action_flags, actions, error);
6607                         if (ret < 0)
6608                                 return ret;
6609                         /* Count PCP with push_vlan command. */
6610                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6611                         break;
6612                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6613                         ret = flow_dv_validate_action_set_vlan_vid
6614                                                 (item_flags, action_flags,
6615                                                  actions, error);
6616                         if (ret < 0)
6617                                 return ret;
6618                         /* Count VID with push_vlan command. */
6619                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6620                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6621                         break;
6622                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6623                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6624                         ret = flow_dv_validate_action_l2_encap(dev,
6625                                                                action_flags,
6626                                                                actions, attr,
6627                                                                error);
6628                         if (ret < 0)
6629                                 return ret;
6630                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6631                         ++actions_n;
6632                         break;
6633                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6634                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6635                         ret = flow_dv_validate_action_decap(dev, action_flags,
6636                                                             actions, item_flags,
6637                                                             attr, error);
6638                         if (ret < 0)
6639                                 return ret;
6640                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6641                         ++actions_n;
6642                         break;
6643                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6644                         ret = flow_dv_validate_action_raw_encap_decap
6645                                 (dev, NULL, actions->conf, attr, &action_flags,
6646                                  &actions_n, actions, item_flags, error);
6647                         if (ret < 0)
6648                                 return ret;
6649                         break;
6650                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6651                         decap = actions->conf;
6652                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6653                                 ;
6654                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6655                                 encap = NULL;
6656                                 actions--;
6657                         } else {
6658                                 encap = actions->conf;
6659                         }
6660                         ret = flow_dv_validate_action_raw_encap_decap
6661                                            (dev,
6662                                             decap ? decap : &empty_decap, encap,
6663                                             attr, &action_flags, &actions_n,
6664                                             actions, item_flags, error);
6665                         if (ret < 0)
6666                                 return ret;
6667                         break;
6668                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6669                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6670                         ret = flow_dv_validate_action_modify_mac(action_flags,
6671                                                                  actions,
6672                                                                  item_flags,
6673                                                                  error);
6674                         if (ret < 0)
6675                                 return ret;
6676                         /* Count all modify-header actions as one action. */
6677                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6678                                 ++actions_n;
6679                         action_flags |= actions->type ==
6680                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6681                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6682                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6683                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6684                                 modify_after_mirror = 1;
6685                         /*
6686                          * Even if the source and destination MAC addresses have
6687                          * overlap in the header with 4B alignment, the convert
6688                          * function will handle them separately and 4 SW actions
6689                          * will be created. And 2 actions will be added each
6690                          * time no matter how many bytes of address will be set.
6691                          */
6692                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6693                         break;
6694                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6695                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6696                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6697                                                                   actions,
6698                                                                   item_flags,
6699                                                                   error);
6700                         if (ret < 0)
6701                                 return ret;
6702                         /* Count all modify-header actions as one action. */
6703                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6704                                 ++actions_n;
6705                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6706                                 modify_after_mirror = 1;
6707                         action_flags |= actions->type ==
6708                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6709                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6710                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6711                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6712                         break;
6713                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6714                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6715                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6716                                                                   actions,
6717                                                                   item_flags,
6718                                                                   error);
6719                         if (ret < 0)
6720                                 return ret;
6721                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6722                                 return rte_flow_error_set(error, ENOTSUP,
6723                                         RTE_FLOW_ERROR_TYPE_ACTION,
6724                                         actions,
6725                                         "Can't change header "
6726                                         "with ICMPv6 proto");
6727                         /* Count all modify-header actions as one action. */
6728                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6729                                 ++actions_n;
6730                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6731                                 modify_after_mirror = 1;
6732                         action_flags |= actions->type ==
6733                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6734                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6735                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6736                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6737                         break;
6738                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6739                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6740                         ret = flow_dv_validate_action_modify_tp(action_flags,
6741                                                                 actions,
6742                                                                 item_flags,
6743                                                                 error);
6744                         if (ret < 0)
6745                                 return ret;
6746                         /* Count all modify-header actions as one action. */
6747                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6748                                 ++actions_n;
6749                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6750                                 modify_after_mirror = 1;
6751                         action_flags |= actions->type ==
6752                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6753                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6754                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6755                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6756                         break;
6757                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6758                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6759                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6760                                                                  actions,
6761                                                                  item_flags,
6762                                                                  error);
6763                         if (ret < 0)
6764                                 return ret;
6765                         /* Count all modify-header actions as one action. */
6766                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6767                                 ++actions_n;
6768                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6769                                 modify_after_mirror = 1;
6770                         action_flags |= actions->type ==
6771                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6772                                                 MLX5_FLOW_ACTION_SET_TTL :
6773                                                 MLX5_FLOW_ACTION_DEC_TTL;
6774                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6775                         break;
6776                 case RTE_FLOW_ACTION_TYPE_JUMP:
6777                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6778                                                            action_flags,
6779                                                            attr, external,
6780                                                            error);
6781                         if (ret)
6782                                 return ret;
6783                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6784                             fdb_mirror_limit)
6785                                 return rte_flow_error_set(error, EINVAL,
6786                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6787                                                   NULL,
6788                                                   "sample and jump action combination is not supported");
6789                         ++actions_n;
6790                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6791                         break;
6792                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6793                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6794                         ret = flow_dv_validate_action_modify_tcp_seq
6795                                                                 (action_flags,
6796                                                                  actions,
6797                                                                  item_flags,
6798                                                                  error);
6799                         if (ret < 0)
6800                                 return ret;
6801                         /* Count all modify-header actions as one action. */
6802                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6803                                 ++actions_n;
6804                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6805                                 modify_after_mirror = 1;
6806                         action_flags |= actions->type ==
6807                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6808                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6809                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6810                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6811                         break;
6812                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6813                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6814                         ret = flow_dv_validate_action_modify_tcp_ack
6815                                                                 (action_flags,
6816                                                                  actions,
6817                                                                  item_flags,
6818                                                                  error);
6819                         if (ret < 0)
6820                                 return ret;
6821                         /* Count all modify-header actions as one action. */
6822                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6823                                 ++actions_n;
6824                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6825                                 modify_after_mirror = 1;
6826                         action_flags |= actions->type ==
6827                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6828                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6829                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6830                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6831                         break;
6832                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6833                         break;
6834                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6835                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6836                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6837                         break;
6838                 case RTE_FLOW_ACTION_TYPE_METER:
6839                         ret = mlx5_flow_validate_action_meter(dev,
6840                                                               action_flags,
6841                                                               actions, attr,
6842                                                               error);
6843                         if (ret < 0)
6844                                 return ret;
6845                         action_flags |= MLX5_FLOW_ACTION_METER;
6846                         ++actions_n;
6847                         /* Meter action will add one more TAG action. */
6848                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6849                         break;
6850                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6851                         if (!attr->transfer && !attr->group)
6852                                 return rte_flow_error_set(error, ENOTSUP,
6853                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6854                                                                            NULL,
6855                           "Shared ASO age action is not supported for group 0");
6856                         action_flags |= MLX5_FLOW_ACTION_AGE;
6857                         ++actions_n;
6858                         break;
6859                 case RTE_FLOW_ACTION_TYPE_AGE:
6860                         ret = flow_dv_validate_action_age(action_flags,
6861                                                           actions, dev,
6862                                                           error);
6863                         if (ret < 0)
6864                                 return ret;
6865                         /*
6866                          * Validate the regular AGE action (using counter)
6867                          * mutual exclusion with share counter actions.
6868                          */
6869                         if (!priv->sh->flow_hit_aso_en) {
6870                                 if (count && count->shared)
6871                                         return rte_flow_error_set
6872                                                 (error, EINVAL,
6873                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6874                                                 NULL,
6875                                                 "old age and shared count combination is not supported");
6876                                 if (sample_count)
6877                                         return rte_flow_error_set
6878                                                 (error, EINVAL,
6879                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6880                                                 NULL,
6881                                                 "old age action and count must be in the same sub flow");
6882                         }
6883                         action_flags |= MLX5_FLOW_ACTION_AGE;
6884                         ++actions_n;
6885                         break;
6886                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6887                         ret = flow_dv_validate_action_modify_ipv4_dscp
6888                                                          (action_flags,
6889                                                           actions,
6890                                                           item_flags,
6891                                                           error);
6892                         if (ret < 0)
6893                                 return ret;
6894                         /* Count all modify-header actions as one action. */
6895                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6896                                 ++actions_n;
6897                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6898                                 modify_after_mirror = 1;
6899                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6900                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6901                         break;
6902                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6903                         ret = flow_dv_validate_action_modify_ipv6_dscp
6904                                                                 (action_flags,
6905                                                                  actions,
6906                                                                  item_flags,
6907                                                                  error);
6908                         if (ret < 0)
6909                                 return ret;
6910                         /* Count all modify-header actions as one action. */
6911                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6912                                 ++actions_n;
6913                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6914                                 modify_after_mirror = 1;
6915                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6916                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6917                         break;
6918                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6919                         ret = flow_dv_validate_action_sample(&action_flags,
6920                                                              actions, dev,
6921                                                              attr, item_flags,
6922                                                              rss, &sample_rss,
6923                                                              &sample_count,
6924                                                              &fdb_mirror_limit,
6925                                                              error);
6926                         if (ret < 0)
6927                                 return ret;
6928                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6929                         ++actions_n;
6930                         break;
6931                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6932                         if (actions[0].type != (typeof(actions[0].type))
6933                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6934                                 return rte_flow_error_set
6935                                                 (error, EINVAL,
6936                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6937                                                 NULL, "MLX5 private action "
6938                                                 "must be the first");
6939
6940                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6941                         break;
6942                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6943                         ret = flow_dv_validate_action_modify_field(dev,
6944                                                                    action_flags,
6945                                                                    actions,
6946                                                                    attr,
6947                                                                    error);
6948                         if (ret < 0)
6949                                 return ret;
6950                         /* Count all modify-header actions as one action. */
6951                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6952                                 ++actions_n;
6953                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6954                         rw_act_num += ret;
6955                         break;
6956                 default:
6957                         return rte_flow_error_set(error, ENOTSUP,
6958                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6959                                                   actions,
6960                                                   "action not supported");
6961                 }
6962         }
6963         /*
6964          * Validate actions in flow rules
6965          * - Explicit decap action is prohibited by the tunnel offload API.
6966          * - Drop action in tunnel steer rule is prohibited by the API.
6967          * - Application cannot use MARK action because it's value can mask
6968          *   tunnel default miss nitification.
6969          * - JUMP in tunnel match rule has no support in current PMD
6970          *   implementation.
6971          * - TAG & META are reserved for future uses.
6972          */
6973         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6974                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6975                                             MLX5_FLOW_ACTION_MARK     |
6976                                             MLX5_FLOW_ACTION_SET_TAG  |
6977                                             MLX5_FLOW_ACTION_SET_META |
6978                                             MLX5_FLOW_ACTION_DROP;
6979
6980                 if (action_flags & bad_actions_mask)
6981                         return rte_flow_error_set
6982                                         (error, EINVAL,
6983                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6984                                         "Invalid RTE action in tunnel "
6985                                         "set decap rule");
6986                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6987                         return rte_flow_error_set
6988                                         (error, EINVAL,
6989                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6990                                         "tunnel set decap rule must terminate "
6991                                         "with JUMP");
6992                 if (!attr->ingress)
6993                         return rte_flow_error_set
6994                                         (error, EINVAL,
6995                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6996                                         "tunnel flows for ingress traffic only");
6997         }
6998         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6999                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7000                                             MLX5_FLOW_ACTION_MARK    |
7001                                             MLX5_FLOW_ACTION_SET_TAG |
7002                                             MLX5_FLOW_ACTION_SET_META;
7003
7004                 if (action_flags & bad_actions_mask)
7005                         return rte_flow_error_set
7006                                         (error, EINVAL,
7007                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7008                                         "Invalid RTE action in tunnel "
7009                                         "set match rule");
7010         }
7011         /*
7012          * Validate the drop action mutual exclusion with other actions.
7013          * Drop action is mutually-exclusive with any other action, except for
7014          * Count action.
7015          * Drop action compatibility with tunnel offload was already validated.
7016          */
7017         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7018                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7019         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7020             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7021                 return rte_flow_error_set(error, EINVAL,
7022                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7023                                           "Drop action is mutually-exclusive "
7024                                           "with any other action, except for "
7025                                           "Count action");
7026         /* Eswitch has few restrictions on using items and actions */
7027         if (attr->transfer) {
7028                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7029                     action_flags & MLX5_FLOW_ACTION_FLAG)
7030                         return rte_flow_error_set(error, ENOTSUP,
7031                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7032                                                   NULL,
7033                                                   "unsupported action FLAG");
7034                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7035                     action_flags & MLX5_FLOW_ACTION_MARK)
7036                         return rte_flow_error_set(error, ENOTSUP,
7037                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7038                                                   NULL,
7039                                                   "unsupported action MARK");
7040                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7041                         return rte_flow_error_set(error, ENOTSUP,
7042                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7043                                                   NULL,
7044                                                   "unsupported action QUEUE");
7045                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7046                         return rte_flow_error_set(error, ENOTSUP,
7047                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7048                                                   NULL,
7049                                                   "unsupported action RSS");
7050                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7051                         return rte_flow_error_set(error, EINVAL,
7052                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7053                                                   actions,
7054                                                   "no fate action is found");
7055         } else {
7056                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7057                         return rte_flow_error_set(error, EINVAL,
7058                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7059                                                   actions,
7060                                                   "no fate action is found");
7061         }
7062         /*
7063          * Continue validation for Xcap and VLAN actions.
7064          * If hairpin is working in explicit TX rule mode, there is no actions
7065          * splitting and the validation of hairpin ingress flow should be the
7066          * same as other standard flows.
7067          */
7068         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7069                              MLX5_FLOW_VLAN_ACTIONS)) &&
7070             (queue_index == 0xFFFF ||
7071              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7072              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7073              conf->tx_explicit != 0))) {
7074                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7075                     MLX5_FLOW_XCAP_ACTIONS)
7076                         return rte_flow_error_set(error, ENOTSUP,
7077                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7078                                                   NULL, "encap and decap "
7079                                                   "combination aren't supported");
7080                 if (!attr->transfer && attr->ingress) {
7081                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7082                                 return rte_flow_error_set
7083                                                 (error, ENOTSUP,
7084                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7085                                                  NULL, "encap is not supported"
7086                                                  " for ingress traffic");
7087                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7088                                 return rte_flow_error_set
7089                                                 (error, ENOTSUP,
7090                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7091                                                  NULL, "push VLAN action not "
7092                                                  "supported for ingress");
7093                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7094                                         MLX5_FLOW_VLAN_ACTIONS)
7095                                 return rte_flow_error_set
7096                                                 (error, ENOTSUP,
7097                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7098                                                  NULL, "no support for "
7099                                                  "multiple VLAN actions");
7100                 }
7101         }
7102         /*
7103          * Hairpin flow will add one more TAG action in TX implicit mode.
7104          * In TX explicit mode, there will be no hairpin flow ID.
7105          */
7106         if (hairpin > 0)
7107                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7108         /* extra metadata enabled: one more TAG action will be add. */
7109         if (dev_conf->dv_flow_en &&
7110             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7111             mlx5_flow_ext_mreg_supported(dev))
7112                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7113         if (rw_act_num >
7114                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7115                 return rte_flow_error_set(error, ENOTSUP,
7116                                           RTE_FLOW_ERROR_TYPE_ACTION,
7117                                           NULL, "too many header modify"
7118                                           " actions to support");
7119         }
7120         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7121         if (fdb_mirror_limit && modify_after_mirror)
7122                 return rte_flow_error_set(error, EINVAL,
7123                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7124                                 "sample before modify action is not supported");
7125         return 0;
7126 }
7127
7128 /**
7129  * Internal preparation function. Allocates the DV flow size,
7130  * this size is constant.
7131  *
7132  * @param[in] dev
7133  *   Pointer to the rte_eth_dev structure.
7134  * @param[in] attr
7135  *   Pointer to the flow attributes.
7136  * @param[in] items
7137  *   Pointer to the list of items.
7138  * @param[in] actions
7139  *   Pointer to the list of actions.
7140  * @param[out] error
7141  *   Pointer to the error structure.
7142  *
7143  * @return
7144  *   Pointer to mlx5_flow object on success,
7145  *   otherwise NULL and rte_errno is set.
7146  */
7147 static struct mlx5_flow *
7148 flow_dv_prepare(struct rte_eth_dev *dev,
7149                 const struct rte_flow_attr *attr __rte_unused,
7150                 const struct rte_flow_item items[] __rte_unused,
7151                 const struct rte_flow_action actions[] __rte_unused,
7152                 struct rte_flow_error *error)
7153 {
7154         uint32_t handle_idx = 0;
7155         struct mlx5_flow *dev_flow;
7156         struct mlx5_flow_handle *dev_handle;
7157         struct mlx5_priv *priv = dev->data->dev_private;
7158         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7159
7160         MLX5_ASSERT(wks);
7161         /* In case of corrupting the memory. */
7162         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7163                 rte_flow_error_set(error, ENOSPC,
7164                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7165                                    "not free temporary device flow");
7166                 return NULL;
7167         }
7168         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7169                                    &handle_idx);
7170         if (!dev_handle) {
7171                 rte_flow_error_set(error, ENOMEM,
7172                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7173                                    "not enough memory to create flow handle");
7174                 return NULL;
7175         }
7176         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7177         dev_flow = &wks->flows[wks->flow_idx++];
7178         memset(dev_flow, 0, sizeof(*dev_flow));
7179         dev_flow->handle = dev_handle;
7180         dev_flow->handle_idx = handle_idx;
7181         /*
7182          * In some old rdma-core releases, before continuing, a check of the
7183          * length of matching parameter will be done at first. It needs to use
7184          * the length without misc4 param. If the flow has misc4 support, then
7185          * the length needs to be adjusted accordingly. Each param member is
7186          * aligned with a 64B boundary naturally.
7187          */
7188         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7189                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7190         dev_flow->ingress = attr->ingress;
7191         dev_flow->dv.transfer = attr->transfer;
7192         return dev_flow;
7193 }
7194
7195 #ifdef RTE_LIBRTE_MLX5_DEBUG
7196 /**
7197  * Sanity check for match mask and value. Similar to check_valid_spec() in
7198  * kernel driver. If unmasked bit is present in value, it returns failure.
7199  *
7200  * @param match_mask
7201  *   pointer to match mask buffer.
7202  * @param match_value
7203  *   pointer to match value buffer.
7204  *
7205  * @return
7206  *   0 if valid, -EINVAL otherwise.
7207  */
7208 static int
7209 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7210 {
7211         uint8_t *m = match_mask;
7212         uint8_t *v = match_value;
7213         unsigned int i;
7214
7215         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7216                 if (v[i] & ~m[i]) {
7217                         DRV_LOG(ERR,
7218                                 "match_value differs from match_criteria"
7219                                 " %p[%u] != %p[%u]",
7220                                 match_value, i, match_mask, i);
7221                         return -EINVAL;
7222                 }
7223         }
7224         return 0;
7225 }
7226 #endif
7227
7228 /**
7229  * Add match of ip_version.
7230  *
7231  * @param[in] group
7232  *   Flow group.
7233  * @param[in] headers_v
7234  *   Values header pointer.
7235  * @param[in] headers_m
7236  *   Masks header pointer.
7237  * @param[in] ip_version
7238  *   The IP version to set.
7239  */
7240 static inline void
7241 flow_dv_set_match_ip_version(uint32_t group,
7242                              void *headers_v,
7243                              void *headers_m,
7244                              uint8_t ip_version)
7245 {
7246         if (group == 0)
7247                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7248         else
7249                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7250                          ip_version);
7251         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7252         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7253         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7254 }
7255
7256 /**
7257  * Add Ethernet item to matcher and to the value.
7258  *
7259  * @param[in, out] matcher
7260  *   Flow matcher.
7261  * @param[in, out] key
7262  *   Flow matcher value.
7263  * @param[in] item
7264  *   Flow pattern to translate.
7265  * @param[in] inner
7266  *   Item is inner pattern.
7267  */
7268 static void
7269 flow_dv_translate_item_eth(void *matcher, void *key,
7270                            const struct rte_flow_item *item, int inner,
7271                            uint32_t group)
7272 {
7273         const struct rte_flow_item_eth *eth_m = item->mask;
7274         const struct rte_flow_item_eth *eth_v = item->spec;
7275         const struct rte_flow_item_eth nic_mask = {
7276                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7277                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7278                 .type = RTE_BE16(0xffff),
7279                 .has_vlan = 0,
7280         };
7281         void *hdrs_m;
7282         void *hdrs_v;
7283         char *l24_v;
7284         unsigned int i;
7285
7286         if (!eth_v)
7287                 return;
7288         if (!eth_m)
7289                 eth_m = &nic_mask;
7290         if (inner) {
7291                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7292                                          inner_headers);
7293                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7294         } else {
7295                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7296                                          outer_headers);
7297                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7298         }
7299         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7300                &eth_m->dst, sizeof(eth_m->dst));
7301         /* The value must be in the range of the mask. */
7302         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7303         for (i = 0; i < sizeof(eth_m->dst); ++i)
7304                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7305         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7306                &eth_m->src, sizeof(eth_m->src));
7307         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7308         /* The value must be in the range of the mask. */
7309         for (i = 0; i < sizeof(eth_m->dst); ++i)
7310                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7311         /*
7312          * HW supports match on one Ethertype, the Ethertype following the last
7313          * VLAN tag of the packet (see PRM).
7314          * Set match on ethertype only if ETH header is not followed by VLAN.
7315          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7316          * ethertype, and use ip_version field instead.
7317          * eCPRI over Ether layer will use type value 0xAEFE.
7318          */
7319         if (eth_m->type == 0xFFFF) {
7320                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7321                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7322                 switch (eth_v->type) {
7323                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7324                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7325                         return;
7326                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7327                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7328                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7329                         return;
7330                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7331                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7332                         return;
7333                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7334                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7335                         return;
7336                 default:
7337                         break;
7338                 }
7339         }
7340         if (eth_m->has_vlan) {
7341                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7342                 if (eth_v->has_vlan) {
7343                         /*
7344                          * Here, when also has_more_vlan field in VLAN item is
7345                          * not set, only single-tagged packets will be matched.
7346                          */
7347                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7348                         return;
7349                 }
7350         }
7351         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7352                  rte_be_to_cpu_16(eth_m->type));
7353         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7354         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7355 }
7356
7357 /**
7358  * Add VLAN item to matcher and to the value.
7359  *
7360  * @param[in, out] dev_flow
7361  *   Flow descriptor.
7362  * @param[in, out] matcher
7363  *   Flow matcher.
7364  * @param[in, out] key
7365  *   Flow matcher value.
7366  * @param[in] item
7367  *   Flow pattern to translate.
7368  * @param[in] inner
7369  *   Item is inner pattern.
7370  */
7371 static void
7372 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7373                             void *matcher, void *key,
7374                             const struct rte_flow_item *item,
7375                             int inner, uint32_t group)
7376 {
7377         const struct rte_flow_item_vlan *vlan_m = item->mask;
7378         const struct rte_flow_item_vlan *vlan_v = item->spec;
7379         void *hdrs_m;
7380         void *hdrs_v;
7381         uint16_t tci_m;
7382         uint16_t tci_v;
7383
7384         if (inner) {
7385                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7386                                          inner_headers);
7387                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7388         } else {
7389                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7390                                          outer_headers);
7391                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7392                 /*
7393                  * This is workaround, masks are not supported,
7394                  * and pre-validated.
7395                  */
7396                 if (vlan_v)
7397                         dev_flow->handle->vf_vlan.tag =
7398                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7399         }
7400         /*
7401          * When VLAN item exists in flow, mark packet as tagged,
7402          * even if TCI is not specified.
7403          */
7404         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7405                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7406                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7407         }
7408         if (!vlan_v)
7409                 return;
7410         if (!vlan_m)
7411                 vlan_m = &rte_flow_item_vlan_mask;
7412         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7413         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7414         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7415         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7416         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7417         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7418         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7419         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7420         /*
7421          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7422          * ethertype, and use ip_version field instead.
7423          */
7424         if (vlan_m->inner_type == 0xFFFF) {
7425                 switch (vlan_v->inner_type) {
7426                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7427                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7428                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7429                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7430                         return;
7431                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7432                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7433                         return;
7434                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7435                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7436                         return;
7437                 default:
7438                         break;
7439                 }
7440         }
7441         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7442                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7443                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7444                 /* Only one vlan_tag bit can be set. */
7445                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7446                 return;
7447         }
7448         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7449                  rte_be_to_cpu_16(vlan_m->inner_type));
7450         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7451                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7452 }
7453
7454 /**
7455  * Add IPV4 item to matcher and to the value.
7456  *
7457  * @param[in, out] matcher
7458  *   Flow matcher.
7459  * @param[in, out] key
7460  *   Flow matcher value.
7461  * @param[in] item
7462  *   Flow pattern to translate.
7463  * @param[in] inner
7464  *   Item is inner pattern.
7465  * @param[in] group
7466  *   The group to insert the rule.
7467  */
7468 static void
7469 flow_dv_translate_item_ipv4(void *matcher, void *key,
7470                             const struct rte_flow_item *item,
7471                             int inner, uint32_t group)
7472 {
7473         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7474         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7475         const struct rte_flow_item_ipv4 nic_mask = {
7476                 .hdr = {
7477                         .src_addr = RTE_BE32(0xffffffff),
7478                         .dst_addr = RTE_BE32(0xffffffff),
7479                         .type_of_service = 0xff,
7480                         .next_proto_id = 0xff,
7481                         .time_to_live = 0xff,
7482                 },
7483         };
7484         void *headers_m;
7485         void *headers_v;
7486         char *l24_m;
7487         char *l24_v;
7488         uint8_t tos;
7489
7490         if (inner) {
7491                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7492                                          inner_headers);
7493                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7494         } else {
7495                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7496                                          outer_headers);
7497                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7498         }
7499         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7500         if (!ipv4_v)
7501                 return;
7502         if (!ipv4_m)
7503                 ipv4_m = &nic_mask;
7504         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7505                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7506         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7507                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7508         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7509         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7510         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7511                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7512         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7513                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7514         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7515         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7516         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7517         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7518                  ipv4_m->hdr.type_of_service);
7519         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7520         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7521                  ipv4_m->hdr.type_of_service >> 2);
7522         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7523         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7524                  ipv4_m->hdr.next_proto_id);
7525         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7526                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7527         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7528                  ipv4_m->hdr.time_to_live);
7529         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7530                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7531         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7532                  !!(ipv4_m->hdr.fragment_offset));
7533         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7534                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7535 }
7536
7537 /**
7538  * Add IPV6 item to matcher and to the value.
7539  *
7540  * @param[in, out] matcher
7541  *   Flow matcher.
7542  * @param[in, out] key
7543  *   Flow matcher value.
7544  * @param[in] item
7545  *   Flow pattern to translate.
7546  * @param[in] inner
7547  *   Item is inner pattern.
7548  * @param[in] group
7549  *   The group to insert the rule.
7550  */
7551 static void
7552 flow_dv_translate_item_ipv6(void *matcher, void *key,
7553                             const struct rte_flow_item *item,
7554                             int inner, uint32_t group)
7555 {
7556         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7557         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7558         const struct rte_flow_item_ipv6 nic_mask = {
7559                 .hdr = {
7560                         .src_addr =
7561                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7562                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7563                         .dst_addr =
7564                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7565                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7566                         .vtc_flow = RTE_BE32(0xffffffff),
7567                         .proto = 0xff,
7568                         .hop_limits = 0xff,
7569                 },
7570         };
7571         void *headers_m;
7572         void *headers_v;
7573         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7574         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7575         char *l24_m;
7576         char *l24_v;
7577         uint32_t vtc_m;
7578         uint32_t vtc_v;
7579         int i;
7580         int size;
7581
7582         if (inner) {
7583                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7584                                          inner_headers);
7585                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7586         } else {
7587                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7588                                          outer_headers);
7589                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7590         }
7591         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7592         if (!ipv6_v)
7593                 return;
7594         if (!ipv6_m)
7595                 ipv6_m = &nic_mask;
7596         size = sizeof(ipv6_m->hdr.dst_addr);
7597         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7598                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7599         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7600                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7601         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7602         for (i = 0; i < size; ++i)
7603                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7604         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7605                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7606         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7607                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7608         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7609         for (i = 0; i < size; ++i)
7610                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7611         /* TOS. */
7612         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7613         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7614         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7615         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7616         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7617         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7618         /* Label. */
7619         if (inner) {
7620                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7621                          vtc_m);
7622                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7623                          vtc_v);
7624         } else {
7625                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7626                          vtc_m);
7627                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7628                          vtc_v);
7629         }
7630         /* Protocol. */
7631         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7632                  ipv6_m->hdr.proto);
7633         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7634                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7635         /* Hop limit. */
7636         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7637                  ipv6_m->hdr.hop_limits);
7638         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7639                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7640         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7641                  !!(ipv6_m->has_frag_ext));
7642         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7643                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7644 }
7645
7646 /**
7647  * Add IPV6 fragment extension item to matcher and to the value.
7648  *
7649  * @param[in, out] matcher
7650  *   Flow matcher.
7651  * @param[in, out] key
7652  *   Flow matcher value.
7653  * @param[in] item
7654  *   Flow pattern to translate.
7655  * @param[in] inner
7656  *   Item is inner pattern.
7657  */
7658 static void
7659 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7660                                      const struct rte_flow_item *item,
7661                                      int inner)
7662 {
7663         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7664         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7665         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7666                 .hdr = {
7667                         .next_header = 0xff,
7668                         .frag_data = RTE_BE16(0xffff),
7669                 },
7670         };
7671         void *headers_m;
7672         void *headers_v;
7673
7674         if (inner) {
7675                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7676                                          inner_headers);
7677                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7678         } else {
7679                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7680                                          outer_headers);
7681                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7682         }
7683         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7684         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7685         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7686         if (!ipv6_frag_ext_v)
7687                 return;
7688         if (!ipv6_frag_ext_m)
7689                 ipv6_frag_ext_m = &nic_mask;
7690         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7691                  ipv6_frag_ext_m->hdr.next_header);
7692         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7693                  ipv6_frag_ext_v->hdr.next_header &
7694                  ipv6_frag_ext_m->hdr.next_header);
7695 }
7696
7697 /**
7698  * Add TCP item to matcher and to the value.
7699  *
7700  * @param[in, out] matcher
7701  *   Flow matcher.
7702  * @param[in, out] key
7703  *   Flow matcher value.
7704  * @param[in] item
7705  *   Flow pattern to translate.
7706  * @param[in] inner
7707  *   Item is inner pattern.
7708  */
7709 static void
7710 flow_dv_translate_item_tcp(void *matcher, void *key,
7711                            const struct rte_flow_item *item,
7712                            int inner)
7713 {
7714         const struct rte_flow_item_tcp *tcp_m = item->mask;
7715         const struct rte_flow_item_tcp *tcp_v = item->spec;
7716         void *headers_m;
7717         void *headers_v;
7718
7719         if (inner) {
7720                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7721                                          inner_headers);
7722                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7723         } else {
7724                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7725                                          outer_headers);
7726                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7727         }
7728         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7729         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7730         if (!tcp_v)
7731                 return;
7732         if (!tcp_m)
7733                 tcp_m = &rte_flow_item_tcp_mask;
7734         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7735                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7736         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7737                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7738         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7739                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7740         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7741                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7742         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7743                  tcp_m->hdr.tcp_flags);
7744         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7745                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7746 }
7747
7748 /**
7749  * Add UDP item to matcher and to the value.
7750  *
7751  * @param[in, out] matcher
7752  *   Flow matcher.
7753  * @param[in, out] key
7754  *   Flow matcher value.
7755  * @param[in] item
7756  *   Flow pattern to translate.
7757  * @param[in] inner
7758  *   Item is inner pattern.
7759  */
7760 static void
7761 flow_dv_translate_item_udp(void *matcher, void *key,
7762                            const struct rte_flow_item *item,
7763                            int inner)
7764 {
7765         const struct rte_flow_item_udp *udp_m = item->mask;
7766         const struct rte_flow_item_udp *udp_v = item->spec;
7767         void *headers_m;
7768         void *headers_v;
7769
7770         if (inner) {
7771                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7772                                          inner_headers);
7773                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7774         } else {
7775                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7776                                          outer_headers);
7777                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7778         }
7779         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7780         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7781         if (!udp_v)
7782                 return;
7783         if (!udp_m)
7784                 udp_m = &rte_flow_item_udp_mask;
7785         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7786                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7787         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7788                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7789         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7790                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7791         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7792                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7793 }
7794
7795 /**
7796  * Add GRE optional Key item to matcher and to the value.
7797  *
7798  * @param[in, out] matcher
7799  *   Flow matcher.
7800  * @param[in, out] key
7801  *   Flow matcher value.
7802  * @param[in] item
7803  *   Flow pattern to translate.
7804  * @param[in] inner
7805  *   Item is inner pattern.
7806  */
7807 static void
7808 flow_dv_translate_item_gre_key(void *matcher, void *key,
7809                                    const struct rte_flow_item *item)
7810 {
7811         const rte_be32_t *key_m = item->mask;
7812         const rte_be32_t *key_v = item->spec;
7813         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7814         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7815         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7816
7817         /* GRE K bit must be on and should already be validated */
7818         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7819         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7820         if (!key_v)
7821                 return;
7822         if (!key_m)
7823                 key_m = &gre_key_default_mask;
7824         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7825                  rte_be_to_cpu_32(*key_m) >> 8);
7826         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7827                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7828         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7829                  rte_be_to_cpu_32(*key_m) & 0xFF);
7830         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7831                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7832 }
7833
7834 /**
7835  * Add GRE item to matcher and to the value.
7836  *
7837  * @param[in, out] matcher
7838  *   Flow matcher.
7839  * @param[in, out] key
7840  *   Flow matcher value.
7841  * @param[in] item
7842  *   Flow pattern to translate.
7843  * @param[in] inner
7844  *   Item is inner pattern.
7845  */
7846 static void
7847 flow_dv_translate_item_gre(void *matcher, void *key,
7848                            const struct rte_flow_item *item,
7849                            int inner)
7850 {
7851         const struct rte_flow_item_gre *gre_m = item->mask;
7852         const struct rte_flow_item_gre *gre_v = item->spec;
7853         void *headers_m;
7854         void *headers_v;
7855         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7856         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7857         struct {
7858                 union {
7859                         __extension__
7860                         struct {
7861                                 uint16_t version:3;
7862                                 uint16_t rsvd0:9;
7863                                 uint16_t s_present:1;
7864                                 uint16_t k_present:1;
7865                                 uint16_t rsvd_bit1:1;
7866                                 uint16_t c_present:1;
7867                         };
7868                         uint16_t value;
7869                 };
7870         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7871
7872         if (inner) {
7873                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7874                                          inner_headers);
7875                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7876         } else {
7877                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7878                                          outer_headers);
7879                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7880         }
7881         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7882         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7883         if (!gre_v)
7884                 return;
7885         if (!gre_m)
7886                 gre_m = &rte_flow_item_gre_mask;
7887         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7888                  rte_be_to_cpu_16(gre_m->protocol));
7889         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7890                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7891         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7892         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7893         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7894                  gre_crks_rsvd0_ver_m.c_present);
7895         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7896                  gre_crks_rsvd0_ver_v.c_present &
7897                  gre_crks_rsvd0_ver_m.c_present);
7898         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7899                  gre_crks_rsvd0_ver_m.k_present);
7900         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7901                  gre_crks_rsvd0_ver_v.k_present &
7902                  gre_crks_rsvd0_ver_m.k_present);
7903         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7904                  gre_crks_rsvd0_ver_m.s_present);
7905         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7906                  gre_crks_rsvd0_ver_v.s_present &
7907                  gre_crks_rsvd0_ver_m.s_present);
7908 }
7909
7910 /**
7911  * Add NVGRE item to matcher and to the value.
7912  *
7913  * @param[in, out] matcher
7914  *   Flow matcher.
7915  * @param[in, out] key
7916  *   Flow matcher value.
7917  * @param[in] item
7918  *   Flow pattern to translate.
7919  * @param[in] inner
7920  *   Item is inner pattern.
7921  */
7922 static void
7923 flow_dv_translate_item_nvgre(void *matcher, void *key,
7924                              const struct rte_flow_item *item,
7925                              int inner)
7926 {
7927         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7928         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7929         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7930         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7931         const char *tni_flow_id_m;
7932         const char *tni_flow_id_v;
7933         char *gre_key_m;
7934         char *gre_key_v;
7935         int size;
7936         int i;
7937
7938         /* For NVGRE, GRE header fields must be set with defined values. */
7939         const struct rte_flow_item_gre gre_spec = {
7940                 .c_rsvd0_ver = RTE_BE16(0x2000),
7941                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7942         };
7943         const struct rte_flow_item_gre gre_mask = {
7944                 .c_rsvd0_ver = RTE_BE16(0xB000),
7945                 .protocol = RTE_BE16(UINT16_MAX),
7946         };
7947         const struct rte_flow_item gre_item = {
7948                 .spec = &gre_spec,
7949                 .mask = &gre_mask,
7950                 .last = NULL,
7951         };
7952         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7953         if (!nvgre_v)
7954                 return;
7955         if (!nvgre_m)
7956                 nvgre_m = &rte_flow_item_nvgre_mask;
7957         tni_flow_id_m = (const char *)nvgre_m->tni;
7958         tni_flow_id_v = (const char *)nvgre_v->tni;
7959         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7960         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7961         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7962         memcpy(gre_key_m, tni_flow_id_m, size);
7963         for (i = 0; i < size; ++i)
7964                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7965 }
7966
7967 /**
7968  * Add VXLAN item to matcher and to the value.
7969  *
7970  * @param[in, out] matcher
7971  *   Flow matcher.
7972  * @param[in, out] key
7973  *   Flow matcher value.
7974  * @param[in] item
7975  *   Flow pattern to translate.
7976  * @param[in] inner
7977  *   Item is inner pattern.
7978  */
7979 static void
7980 flow_dv_translate_item_vxlan(void *matcher, void *key,
7981                              const struct rte_flow_item *item,
7982                              int inner)
7983 {
7984         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7985         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7986         void *headers_m;
7987         void *headers_v;
7988         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7989         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7990         char *vni_m;
7991         char *vni_v;
7992         uint16_t dport;
7993         int size;
7994         int i;
7995
7996         if (inner) {
7997                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7998                                          inner_headers);
7999                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8000         } else {
8001                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8002                                          outer_headers);
8003                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8004         }
8005         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8006                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8007         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8008                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8009                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8010         }
8011         if (!vxlan_v)
8012                 return;
8013         if (!vxlan_m)
8014                 vxlan_m = &rte_flow_item_vxlan_mask;
8015         size = sizeof(vxlan_m->vni);
8016         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8017         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8018         memcpy(vni_m, vxlan_m->vni, size);
8019         for (i = 0; i < size; ++i)
8020                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8021 }
8022
8023 /**
8024  * Add VXLAN-GPE item to matcher and to the value.
8025  *
8026  * @param[in, out] matcher
8027  *   Flow matcher.
8028  * @param[in, out] key
8029  *   Flow matcher value.
8030  * @param[in] item
8031  *   Flow pattern to translate.
8032  * @param[in] inner
8033  *   Item is inner pattern.
8034  */
8035
8036 static void
8037 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8038                                  const struct rte_flow_item *item, int inner)
8039 {
8040         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8041         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8042         void *headers_m;
8043         void *headers_v;
8044         void *misc_m =
8045                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8046         void *misc_v =
8047                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8048         char *vni_m;
8049         char *vni_v;
8050         uint16_t dport;
8051         int size;
8052         int i;
8053         uint8_t flags_m = 0xff;
8054         uint8_t flags_v = 0xc;
8055
8056         if (inner) {
8057                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8058                                          inner_headers);
8059                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8060         } else {
8061                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8062                                          outer_headers);
8063                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8064         }
8065         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8066                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8067         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8068                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8069                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8070         }
8071         if (!vxlan_v)
8072                 return;
8073         if (!vxlan_m)
8074                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8075         size = sizeof(vxlan_m->vni);
8076         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8077         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8078         memcpy(vni_m, vxlan_m->vni, size);
8079         for (i = 0; i < size; ++i)
8080                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8081         if (vxlan_m->flags) {
8082                 flags_m = vxlan_m->flags;
8083                 flags_v = vxlan_v->flags;
8084         }
8085         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8086         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8087         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8088                  vxlan_m->protocol);
8089         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8090                  vxlan_v->protocol);
8091 }
8092
8093 /**
8094  * Add Geneve item to matcher and to the value.
8095  *
8096  * @param[in, out] matcher
8097  *   Flow matcher.
8098  * @param[in, out] key
8099  *   Flow matcher value.
8100  * @param[in] item
8101  *   Flow pattern to translate.
8102  * @param[in] inner
8103  *   Item is inner pattern.
8104  */
8105
8106 static void
8107 flow_dv_translate_item_geneve(void *matcher, void *key,
8108                               const struct rte_flow_item *item, int inner)
8109 {
8110         const struct rte_flow_item_geneve *geneve_m = item->mask;
8111         const struct rte_flow_item_geneve *geneve_v = item->spec;
8112         void *headers_m;
8113         void *headers_v;
8114         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8115         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8116         uint16_t dport;
8117         uint16_t gbhdr_m;
8118         uint16_t gbhdr_v;
8119         char *vni_m;
8120         char *vni_v;
8121         size_t size, i;
8122
8123         if (inner) {
8124                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8125                                          inner_headers);
8126                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8127         } else {
8128                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8129                                          outer_headers);
8130                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8131         }
8132         dport = MLX5_UDP_PORT_GENEVE;
8133         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8134                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8135                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8136         }
8137         if (!geneve_v)
8138                 return;
8139         if (!geneve_m)
8140                 geneve_m = &rte_flow_item_geneve_mask;
8141         size = sizeof(geneve_m->vni);
8142         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8143         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8144         memcpy(vni_m, geneve_m->vni, size);
8145         for (i = 0; i < size; ++i)
8146                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8147         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8148                  rte_be_to_cpu_16(geneve_m->protocol));
8149         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8150                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8151         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8152         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8153         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8154                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8155         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8156                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8157         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8158                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8159         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8160                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8161                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8162 }
8163
8164 /**
8165  * Create Geneve TLV option resource.
8166  *
8167  * @param dev[in, out]
8168  *   Pointer to rte_eth_dev structure.
8169  * @param[in, out] tag_be24
8170  *   Tag value in big endian then R-shift 8.
8171  * @parm[in, out] dev_flow
8172  *   Pointer to the dev_flow.
8173  * @param[out] error
8174  *   pointer to error structure.
8175  *
8176  * @return
8177  *   0 on success otherwise -errno and errno is set.
8178  */
8179
8180 int
8181 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8182                                              const struct rte_flow_item *item,
8183                                              struct rte_flow_error *error)
8184 {
8185         struct mlx5_priv *priv = dev->data->dev_private;
8186         struct mlx5_dev_ctx_shared *sh = priv->sh;
8187         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8188                         sh->geneve_tlv_option_resource;
8189         struct mlx5_devx_obj *obj;
8190         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8191         int ret = 0;
8192
8193         if (!geneve_opt_v)
8194                 return -1;
8195         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8196         if (geneve_opt_resource != NULL) {
8197                 if (geneve_opt_resource->option_class ==
8198                         geneve_opt_v->option_class &&
8199                         geneve_opt_resource->option_type ==
8200                         geneve_opt_v->option_type &&
8201                         geneve_opt_resource->length ==
8202                         geneve_opt_v->option_len) {
8203                         /* We already have GENVE TLV option obj allocated. */
8204                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8205                                            __ATOMIC_RELAXED);
8206                 } else {
8207                         ret = rte_flow_error_set(error, ENOMEM,
8208                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8209                                 "Only one GENEVE TLV option supported");
8210                         goto exit;
8211                 }
8212         } else {
8213                 /* Create a GENEVE TLV object and resource. */
8214                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8215                                 geneve_opt_v->option_class,
8216                                 geneve_opt_v->option_type,
8217                                 geneve_opt_v->option_len);
8218                 if (!obj) {
8219                         ret = rte_flow_error_set(error, ENODATA,
8220                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8221                                 "Failed to create GENEVE TLV Devx object");
8222                         goto exit;
8223                 }
8224                 sh->geneve_tlv_option_resource =
8225                                 mlx5_malloc(MLX5_MEM_ZERO,
8226                                                 sizeof(*geneve_opt_resource),
8227                                                 0, SOCKET_ID_ANY);
8228                 if (!sh->geneve_tlv_option_resource) {
8229                         claim_zero(mlx5_devx_cmd_destroy(obj));
8230                         ret = rte_flow_error_set(error, ENOMEM,
8231                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8232                                 "GENEVE TLV object memory allocation failed");
8233                         goto exit;
8234                 }
8235                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8236                 geneve_opt_resource->obj = obj;
8237                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8238                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8239                 geneve_opt_resource->length = geneve_opt_v->option_len;
8240                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8241                                 __ATOMIC_RELAXED);
8242         }
8243 exit:
8244         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8245         return ret;
8246 }
8247
8248 /**
8249  * Add Geneve TLV option item to matcher.
8250  *
8251  * @param[in, out] dev
8252  *   Pointer to rte_eth_dev structure.
8253  * @param[in, out] matcher
8254  *   Flow matcher.
8255  * @param[in, out] key
8256  *   Flow matcher value.
8257  * @param[in] item
8258  *   Flow pattern to translate.
8259  * @param[out] error
8260  *   Pointer to error structure.
8261  */
8262 static int
8263 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8264                                   void *key, const struct rte_flow_item *item,
8265                                   struct rte_flow_error *error)
8266 {
8267         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8268         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8269         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8270         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8271         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8272                         misc_parameters_3);
8273         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8274         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8275         int ret = 0;
8276
8277         if (!geneve_opt_v)
8278                 return -1;
8279         if (!geneve_opt_m)
8280                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8281         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8282                                                            error);
8283         if (ret) {
8284                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8285                 return ret;
8286         }
8287         /*
8288          * Set the option length in GENEVE header if not requested.
8289          * The GENEVE TLV option length is expressed by the option length field
8290          * in the GENEVE header.
8291          * If the option length was not requested but the GENEVE TLV option item
8292          * is present we set the option length field implicitly.
8293          */
8294         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8295                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8296                          MLX5_GENEVE_OPTLEN_MASK);
8297                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8298                          geneve_opt_v->option_len + 1);
8299         }
8300         /* Set the data. */
8301         if (geneve_opt_v->data) {
8302                 memcpy(&opt_data_key, geneve_opt_v->data,
8303                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8304                                 sizeof(opt_data_key)));
8305                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8306                                 sizeof(opt_data_key));
8307                 memcpy(&opt_data_mask, geneve_opt_m->data,
8308                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8309                                 sizeof(opt_data_mask)));
8310                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8311                                 sizeof(opt_data_mask));
8312                 MLX5_SET(fte_match_set_misc3, misc3_m,
8313                                 geneve_tlv_option_0_data,
8314                                 rte_be_to_cpu_32(opt_data_mask));
8315                 MLX5_SET(fte_match_set_misc3, misc3_v,
8316                                 geneve_tlv_option_0_data,
8317                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8318         }
8319         return ret;
8320 }
8321
8322 /**
8323  * Add MPLS item to matcher and to the value.
8324  *
8325  * @param[in, out] matcher
8326  *   Flow matcher.
8327  * @param[in, out] key
8328  *   Flow matcher value.
8329  * @param[in] item
8330  *   Flow pattern to translate.
8331  * @param[in] prev_layer
8332  *   The protocol layer indicated in previous item.
8333  * @param[in] inner
8334  *   Item is inner pattern.
8335  */
8336 static void
8337 flow_dv_translate_item_mpls(void *matcher, void *key,
8338                             const struct rte_flow_item *item,
8339                             uint64_t prev_layer,
8340                             int inner)
8341 {
8342         const uint32_t *in_mpls_m = item->mask;
8343         const uint32_t *in_mpls_v = item->spec;
8344         uint32_t *out_mpls_m = 0;
8345         uint32_t *out_mpls_v = 0;
8346         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8347         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8348         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8349                                      misc_parameters_2);
8350         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8351         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8352         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8353
8354         switch (prev_layer) {
8355         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8356                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8357                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8358                          MLX5_UDP_PORT_MPLS);
8359                 break;
8360         case MLX5_FLOW_LAYER_GRE:
8361                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8362                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8363                          RTE_ETHER_TYPE_MPLS);
8364                 break;
8365         default:
8366                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8367                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8368                          IPPROTO_MPLS);
8369                 break;
8370         }
8371         if (!in_mpls_v)
8372                 return;
8373         if (!in_mpls_m)
8374                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8375         switch (prev_layer) {
8376         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8377                 out_mpls_m =
8378                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8379                                                  outer_first_mpls_over_udp);
8380                 out_mpls_v =
8381                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8382                                                  outer_first_mpls_over_udp);
8383                 break;
8384         case MLX5_FLOW_LAYER_GRE:
8385                 out_mpls_m =
8386                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8387                                                  outer_first_mpls_over_gre);
8388                 out_mpls_v =
8389                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8390                                                  outer_first_mpls_over_gre);
8391                 break;
8392         default:
8393                 /* Inner MPLS not over GRE is not supported. */
8394                 if (!inner) {
8395                         out_mpls_m =
8396                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8397                                                          misc2_m,
8398                                                          outer_first_mpls);
8399                         out_mpls_v =
8400                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8401                                                          misc2_v,
8402                                                          outer_first_mpls);
8403                 }
8404                 break;
8405         }
8406         if (out_mpls_m && out_mpls_v) {
8407                 *out_mpls_m = *in_mpls_m;
8408                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8409         }
8410 }
8411
8412 /**
8413  * Add metadata register item to matcher
8414  *
8415  * @param[in, out] matcher
8416  *   Flow matcher.
8417  * @param[in, out] key
8418  *   Flow matcher value.
8419  * @param[in] reg_type
8420  *   Type of device metadata register
8421  * @param[in] value
8422  *   Register value
8423  * @param[in] mask
8424  *   Register mask
8425  */
8426 static void
8427 flow_dv_match_meta_reg(void *matcher, void *key,
8428                        enum modify_reg reg_type,
8429                        uint32_t data, uint32_t mask)
8430 {
8431         void *misc2_m =
8432                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8433         void *misc2_v =
8434                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8435         uint32_t temp;
8436
8437         data &= mask;
8438         switch (reg_type) {
8439         case REG_A:
8440                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8441                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8442                 break;
8443         case REG_B:
8444                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8445                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8446                 break;
8447         case REG_C_0:
8448                 /*
8449                  * The metadata register C0 field might be divided into
8450                  * source vport index and META item value, we should set
8451                  * this field according to specified mask, not as whole one.
8452                  */
8453                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8454                 temp |= mask;
8455                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8456                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8457                 temp &= ~mask;
8458                 temp |= data;
8459                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8460                 break;
8461         case REG_C_1:
8462                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8463                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8464                 break;
8465         case REG_C_2:
8466                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8467                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8468                 break;
8469         case REG_C_3:
8470                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8471                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8472                 break;
8473         case REG_C_4:
8474                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8475                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8476                 break;
8477         case REG_C_5:
8478                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8479                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8480                 break;
8481         case REG_C_6:
8482                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8483                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8484                 break;
8485         case REG_C_7:
8486                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8487                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8488                 break;
8489         default:
8490                 MLX5_ASSERT(false);
8491                 break;
8492         }
8493 }
8494
8495 /**
8496  * Add MARK item to matcher
8497  *
8498  * @param[in] dev
8499  *   The device to configure through.
8500  * @param[in, out] matcher
8501  *   Flow matcher.
8502  * @param[in, out] key
8503  *   Flow matcher value.
8504  * @param[in] item
8505  *   Flow pattern to translate.
8506  */
8507 static void
8508 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8509                             void *matcher, void *key,
8510                             const struct rte_flow_item *item)
8511 {
8512         struct mlx5_priv *priv = dev->data->dev_private;
8513         const struct rte_flow_item_mark *mark;
8514         uint32_t value;
8515         uint32_t mask;
8516
8517         mark = item->mask ? (const void *)item->mask :
8518                             &rte_flow_item_mark_mask;
8519         mask = mark->id & priv->sh->dv_mark_mask;
8520         mark = (const void *)item->spec;
8521         MLX5_ASSERT(mark);
8522         value = mark->id & priv->sh->dv_mark_mask & mask;
8523         if (mask) {
8524                 enum modify_reg reg;
8525
8526                 /* Get the metadata register index for the mark. */
8527                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8528                 MLX5_ASSERT(reg > 0);
8529                 if (reg == REG_C_0) {
8530                         struct mlx5_priv *priv = dev->data->dev_private;
8531                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8532                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8533
8534                         mask &= msk_c0;
8535                         mask <<= shl_c0;
8536                         value <<= shl_c0;
8537                 }
8538                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8539         }
8540 }
8541
8542 /**
8543  * Add META item to matcher
8544  *
8545  * @param[in] dev
8546  *   The devich to configure through.
8547  * @param[in, out] matcher
8548  *   Flow matcher.
8549  * @param[in, out] key
8550  *   Flow matcher value.
8551  * @param[in] attr
8552  *   Attributes of flow that includes this item.
8553  * @param[in] item
8554  *   Flow pattern to translate.
8555  */
8556 static void
8557 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8558                             void *matcher, void *key,
8559                             const struct rte_flow_attr *attr,
8560                             const struct rte_flow_item *item)
8561 {
8562         const struct rte_flow_item_meta *meta_m;
8563         const struct rte_flow_item_meta *meta_v;
8564
8565         meta_m = (const void *)item->mask;
8566         if (!meta_m)
8567                 meta_m = &rte_flow_item_meta_mask;
8568         meta_v = (const void *)item->spec;
8569         if (meta_v) {
8570                 int reg;
8571                 uint32_t value = meta_v->data;
8572                 uint32_t mask = meta_m->data;
8573
8574                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8575                 if (reg < 0)
8576                         return;
8577                 MLX5_ASSERT(reg != REG_NON);
8578                 /*
8579                  * In datapath code there is no endianness
8580                  * coversions for perfromance reasons, all
8581                  * pattern conversions are done in rte_flow.
8582                  */
8583                 value = rte_cpu_to_be_32(value);
8584                 mask = rte_cpu_to_be_32(mask);
8585                 if (reg == REG_C_0) {
8586                         struct mlx5_priv *priv = dev->data->dev_private;
8587                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8588                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8589 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8590                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8591
8592                         value >>= shr_c0;
8593                         mask >>= shr_c0;
8594 #endif
8595                         value <<= shl_c0;
8596                         mask <<= shl_c0;
8597                         MLX5_ASSERT(msk_c0);
8598                         MLX5_ASSERT(!(~msk_c0 & mask));
8599                 }
8600                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8601         }
8602 }
8603
8604 /**
8605  * Add vport metadata Reg C0 item to matcher
8606  *
8607  * @param[in, out] matcher
8608  *   Flow matcher.
8609  * @param[in, out] key
8610  *   Flow matcher value.
8611  * @param[in] reg
8612  *   Flow pattern to translate.
8613  */
8614 static void
8615 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8616                                   uint32_t value, uint32_t mask)
8617 {
8618         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8619 }
8620
8621 /**
8622  * Add tag item to matcher
8623  *
8624  * @param[in] dev
8625  *   The devich to configure through.
8626  * @param[in, out] matcher
8627  *   Flow matcher.
8628  * @param[in, out] key
8629  *   Flow matcher value.
8630  * @param[in] item
8631  *   Flow pattern to translate.
8632  */
8633 static void
8634 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8635                                 void *matcher, void *key,
8636                                 const struct rte_flow_item *item)
8637 {
8638         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8639         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8640         uint32_t mask, value;
8641
8642         MLX5_ASSERT(tag_v);
8643         value = tag_v->data;
8644         mask = tag_m ? tag_m->data : UINT32_MAX;
8645         if (tag_v->id == REG_C_0) {
8646                 struct mlx5_priv *priv = dev->data->dev_private;
8647                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8648                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8649
8650                 mask &= msk_c0;
8651                 mask <<= shl_c0;
8652                 value <<= shl_c0;
8653         }
8654         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8655 }
8656
8657 /**
8658  * Add TAG item to matcher
8659  *
8660  * @param[in] dev
8661  *   The devich to configure through.
8662  * @param[in, out] matcher
8663  *   Flow matcher.
8664  * @param[in, out] key
8665  *   Flow matcher value.
8666  * @param[in] item
8667  *   Flow pattern to translate.
8668  */
8669 static void
8670 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8671                            void *matcher, void *key,
8672                            const struct rte_flow_item *item)
8673 {
8674         const struct rte_flow_item_tag *tag_v = item->spec;
8675         const struct rte_flow_item_tag *tag_m = item->mask;
8676         enum modify_reg reg;
8677
8678         MLX5_ASSERT(tag_v);
8679         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8680         /* Get the metadata register index for the tag. */
8681         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8682         MLX5_ASSERT(reg > 0);
8683         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8684 }
8685
8686 /**
8687  * Add source vport match to the specified matcher.
8688  *
8689  * @param[in, out] matcher
8690  *   Flow matcher.
8691  * @param[in, out] key
8692  *   Flow matcher value.
8693  * @param[in] port
8694  *   Source vport value to match
8695  * @param[in] mask
8696  *   Mask
8697  */
8698 static void
8699 flow_dv_translate_item_source_vport(void *matcher, void *key,
8700                                     int16_t port, uint16_t mask)
8701 {
8702         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8703         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8704
8705         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8706         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8707 }
8708
8709 /**
8710  * Translate port-id item to eswitch match on  port-id.
8711  *
8712  * @param[in] dev
8713  *   The devich to configure through.
8714  * @param[in, out] matcher
8715  *   Flow matcher.
8716  * @param[in, out] key
8717  *   Flow matcher value.
8718  * @param[in] item
8719  *   Flow pattern to translate.
8720  * @param[in]
8721  *   Flow attributes.
8722  *
8723  * @return
8724  *   0 on success, a negative errno value otherwise.
8725  */
8726 static int
8727 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8728                                void *key, const struct rte_flow_item *item,
8729                                const struct rte_flow_attr *attr)
8730 {
8731         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8732         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8733         struct mlx5_priv *priv;
8734         uint16_t mask, id;
8735
8736         mask = pid_m ? pid_m->id : 0xffff;
8737         id = pid_v ? pid_v->id : dev->data->port_id;
8738         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8739         if (!priv)
8740                 return -rte_errno;
8741         /*
8742          * Translate to vport field or to metadata, depending on mode.
8743          * Kernel can use either misc.source_port or half of C0 metadata
8744          * register.
8745          */
8746         if (priv->vport_meta_mask) {
8747                 /*
8748                  * Provide the hint for SW steering library
8749                  * to insert the flow into ingress domain and
8750                  * save the extra vport match.
8751                  */
8752                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8753                     priv->pf_bond < 0 && attr->transfer)
8754                         flow_dv_translate_item_source_vport
8755                                 (matcher, key, priv->vport_id, mask);
8756                 /*
8757                  * We should always set the vport metadata register,
8758                  * otherwise the SW steering library can drop
8759                  * the rule if wire vport metadata value is not zero,
8760                  * it depends on kernel configuration.
8761                  */
8762                 flow_dv_translate_item_meta_vport(matcher, key,
8763                                                   priv->vport_meta_tag,
8764                                                   priv->vport_meta_mask);
8765         } else {
8766                 flow_dv_translate_item_source_vport(matcher, key,
8767                                                     priv->vport_id, mask);
8768         }
8769         return 0;
8770 }
8771
8772 /**
8773  * Add ICMP6 item to matcher and to the value.
8774  *
8775  * @param[in, out] matcher
8776  *   Flow matcher.
8777  * @param[in, out] key
8778  *   Flow matcher value.
8779  * @param[in] item
8780  *   Flow pattern to translate.
8781  * @param[in] inner
8782  *   Item is inner pattern.
8783  */
8784 static void
8785 flow_dv_translate_item_icmp6(void *matcher, void *key,
8786                               const struct rte_flow_item *item,
8787                               int inner)
8788 {
8789         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8790         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8791         void *headers_m;
8792         void *headers_v;
8793         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8794                                      misc_parameters_3);
8795         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8796         if (inner) {
8797                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8798                                          inner_headers);
8799                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8800         } else {
8801                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8802                                          outer_headers);
8803                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8804         }
8805         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8806         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8807         if (!icmp6_v)
8808                 return;
8809         if (!icmp6_m)
8810                 icmp6_m = &rte_flow_item_icmp6_mask;
8811         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8812         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8813                  icmp6_v->type & icmp6_m->type);
8814         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8815         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8816                  icmp6_v->code & icmp6_m->code);
8817 }
8818
8819 /**
8820  * Add ICMP item to matcher and to the value.
8821  *
8822  * @param[in, out] matcher
8823  *   Flow matcher.
8824  * @param[in, out] key
8825  *   Flow matcher value.
8826  * @param[in] item
8827  *   Flow pattern to translate.
8828  * @param[in] inner
8829  *   Item is inner pattern.
8830  */
8831 static void
8832 flow_dv_translate_item_icmp(void *matcher, void *key,
8833                             const struct rte_flow_item *item,
8834                             int inner)
8835 {
8836         const struct rte_flow_item_icmp *icmp_m = item->mask;
8837         const struct rte_flow_item_icmp *icmp_v = item->spec;
8838         uint32_t icmp_header_data_m = 0;
8839         uint32_t icmp_header_data_v = 0;
8840         void *headers_m;
8841         void *headers_v;
8842         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8843                                      misc_parameters_3);
8844         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8845         if (inner) {
8846                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8847                                          inner_headers);
8848                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8849         } else {
8850                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8851                                          outer_headers);
8852                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8853         }
8854         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8855         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8856         if (!icmp_v)
8857                 return;
8858         if (!icmp_m)
8859                 icmp_m = &rte_flow_item_icmp_mask;
8860         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8861                  icmp_m->hdr.icmp_type);
8862         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8863                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8864         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8865                  icmp_m->hdr.icmp_code);
8866         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8867                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8868         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8869         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8870         if (icmp_header_data_m) {
8871                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8872                 icmp_header_data_v |=
8873                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8874                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8875                          icmp_header_data_m);
8876                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8877                          icmp_header_data_v & icmp_header_data_m);
8878         }
8879 }
8880
8881 /**
8882  * Add GTP item to matcher and to the value.
8883  *
8884  * @param[in, out] matcher
8885  *   Flow matcher.
8886  * @param[in, out] key
8887  *   Flow matcher value.
8888  * @param[in] item
8889  *   Flow pattern to translate.
8890  * @param[in] inner
8891  *   Item is inner pattern.
8892  */
8893 static void
8894 flow_dv_translate_item_gtp(void *matcher, void *key,
8895                            const struct rte_flow_item *item, int inner)
8896 {
8897         const struct rte_flow_item_gtp *gtp_m = item->mask;
8898         const struct rte_flow_item_gtp *gtp_v = item->spec;
8899         void *headers_m;
8900         void *headers_v;
8901         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8902                                      misc_parameters_3);
8903         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8904         uint16_t dport = RTE_GTPU_UDP_PORT;
8905
8906         if (inner) {
8907                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8908                                          inner_headers);
8909                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8910         } else {
8911                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8912                                          outer_headers);
8913                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8914         }
8915         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8916                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8917                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8918         }
8919         if (!gtp_v)
8920                 return;
8921         if (!gtp_m)
8922                 gtp_m = &rte_flow_item_gtp_mask;
8923         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8924                  gtp_m->v_pt_rsv_flags);
8925         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8926                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8927         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8928         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8929                  gtp_v->msg_type & gtp_m->msg_type);
8930         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8931                  rte_be_to_cpu_32(gtp_m->teid));
8932         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8933                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8934 }
8935
8936 /**
8937  * Add GTP PSC item to matcher.
8938  *
8939  * @param[in, out] matcher
8940  *   Flow matcher.
8941  * @param[in, out] key
8942  *   Flow matcher value.
8943  * @param[in] item
8944  *   Flow pattern to translate.
8945  */
8946 static int
8947 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8948                                const struct rte_flow_item *item)
8949 {
8950         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8951         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8952         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8953                         misc_parameters_3);
8954         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8955         union {
8956                 uint32_t w32;
8957                 struct {
8958                         uint16_t seq_num;
8959                         uint8_t npdu_num;
8960                         uint8_t next_ext_header_type;
8961                 };
8962         } dw_2;
8963         uint8_t gtp_flags;
8964
8965         /* Always set E-flag match on one, regardless of GTP item settings. */
8966         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8967         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8968         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8969         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8970         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8971         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8972         /*Set next extension header type. */
8973         dw_2.seq_num = 0;
8974         dw_2.npdu_num = 0;
8975         dw_2.next_ext_header_type = 0xff;
8976         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8977                  rte_cpu_to_be_32(dw_2.w32));
8978         dw_2.seq_num = 0;
8979         dw_2.npdu_num = 0;
8980         dw_2.next_ext_header_type = 0x85;
8981         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8982                  rte_cpu_to_be_32(dw_2.w32));
8983         if (gtp_psc_v) {
8984                 union {
8985                         uint32_t w32;
8986                         struct {
8987                                 uint8_t len;
8988                                 uint8_t type_flags;
8989                                 uint8_t qfi;
8990                                 uint8_t reserved;
8991                         };
8992                 } dw_0;
8993
8994                 /*Set extension header PDU type and Qos. */
8995                 if (!gtp_psc_m)
8996                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8997                 dw_0.w32 = 0;
8998                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8999                 dw_0.qfi = gtp_psc_m->qfi;
9000                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9001                          rte_cpu_to_be_32(dw_0.w32));
9002                 dw_0.w32 = 0;
9003                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9004                                                         gtp_psc_m->pdu_type);
9005                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9006                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9007                          rte_cpu_to_be_32(dw_0.w32));
9008         }
9009         return 0;
9010 }
9011
9012 /**
9013  * Add eCPRI item to matcher and to the value.
9014  *
9015  * @param[in] dev
9016  *   The devich to configure through.
9017  * @param[in, out] matcher
9018  *   Flow matcher.
9019  * @param[in, out] key
9020  *   Flow matcher value.
9021  * @param[in] item
9022  *   Flow pattern to translate.
9023  * @param[in] samples
9024  *   Sample IDs to be used in the matching.
9025  */
9026 static void
9027 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9028                              void *key, const struct rte_flow_item *item)
9029 {
9030         struct mlx5_priv *priv = dev->data->dev_private;
9031         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9032         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9033         struct rte_ecpri_common_hdr common;
9034         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9035                                      misc_parameters_4);
9036         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9037         uint32_t *samples;
9038         void *dw_m;
9039         void *dw_v;
9040
9041         if (!ecpri_v)
9042                 return;
9043         if (!ecpri_m)
9044                 ecpri_m = &rte_flow_item_ecpri_mask;
9045         /*
9046          * Maximal four DW samples are supported in a single matching now.
9047          * Two are used now for a eCPRI matching:
9048          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9049          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9050          *    if any.
9051          */
9052         if (!ecpri_m->hdr.common.u32)
9053                 return;
9054         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9055         /* Need to take the whole DW as the mask to fill the entry. */
9056         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9057                             prog_sample_field_value_0);
9058         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9059                             prog_sample_field_value_0);
9060         /* Already big endian (network order) in the header. */
9061         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9062         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9063         /* Sample#0, used for matching type, offset 0. */
9064         MLX5_SET(fte_match_set_misc4, misc4_m,
9065                  prog_sample_field_id_0, samples[0]);
9066         /* It makes no sense to set the sample ID in the mask field. */
9067         MLX5_SET(fte_match_set_misc4, misc4_v,
9068                  prog_sample_field_id_0, samples[0]);
9069         /*
9070          * Checking if message body part needs to be matched.
9071          * Some wildcard rules only matching type field should be supported.
9072          */
9073         if (ecpri_m->hdr.dummy[0]) {
9074                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9075                 switch (common.type) {
9076                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9077                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9078                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9079                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9080                                             prog_sample_field_value_1);
9081                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9082                                             prog_sample_field_value_1);
9083                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9084                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9085                                             ecpri_m->hdr.dummy[0];
9086                         /* Sample#1, to match message body, offset 4. */
9087                         MLX5_SET(fte_match_set_misc4, misc4_m,
9088                                  prog_sample_field_id_1, samples[1]);
9089                         MLX5_SET(fte_match_set_misc4, misc4_v,
9090                                  prog_sample_field_id_1, samples[1]);
9091                         break;
9092                 default:
9093                         /* Others, do not match any sample ID. */
9094                         break;
9095                 }
9096         }
9097 }
9098
9099 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9100
9101 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9102         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9103                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9104
9105 /**
9106  * Calculate flow matcher enable bitmap.
9107  *
9108  * @param match_criteria
9109  *   Pointer to flow matcher criteria.
9110  *
9111  * @return
9112  *   Bitmap of enabled fields.
9113  */
9114 static uint8_t
9115 flow_dv_matcher_enable(uint32_t *match_criteria)
9116 {
9117         uint8_t match_criteria_enable;
9118
9119         match_criteria_enable =
9120                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9121                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9122         match_criteria_enable |=
9123                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9124                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9125         match_criteria_enable |=
9126                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9127                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9128         match_criteria_enable |=
9129                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9130                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9131         match_criteria_enable |=
9132                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9133                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9134         match_criteria_enable |=
9135                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9136                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9137         return match_criteria_enable;
9138 }
9139
9140 struct mlx5_hlist_entry *
9141 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9142 {
9143         struct mlx5_dev_ctx_shared *sh = list->ctx;
9144         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9145         struct rte_eth_dev *dev = ctx->dev;
9146         struct mlx5_flow_tbl_data_entry *tbl_data;
9147         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9148         struct rte_flow_error *error = ctx->error;
9149         union mlx5_flow_tbl_key key = { .v64 = key64 };
9150         struct mlx5_flow_tbl_resource *tbl;
9151         void *domain;
9152         uint32_t idx = 0;
9153         int ret;
9154
9155         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9156         if (!tbl_data) {
9157                 rte_flow_error_set(error, ENOMEM,
9158                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9159                                    NULL,
9160                                    "cannot allocate flow table data entry");
9161                 return NULL;
9162         }
9163         tbl_data->idx = idx;
9164         tbl_data->tunnel = tt_prm->tunnel;
9165         tbl_data->group_id = tt_prm->group_id;
9166         tbl_data->external = !!tt_prm->external;
9167         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9168         tbl_data->is_egress = !!key.direction;
9169         tbl_data->is_transfer = !!key.domain;
9170         tbl_data->dummy = !!key.dummy;
9171         tbl_data->table_id = key.table_id;
9172         tbl = &tbl_data->tbl;
9173         if (key.dummy)
9174                 return &tbl_data->entry;
9175         if (key.domain)
9176                 domain = sh->fdb_domain;
9177         else if (key.direction)
9178                 domain = sh->tx_domain;
9179         else
9180                 domain = sh->rx_domain;
9181         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9182         if (ret) {
9183                 rte_flow_error_set(error, ENOMEM,
9184                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9185                                    NULL, "cannot create flow table object");
9186                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9187                 return NULL;
9188         }
9189         if (key.table_id) {
9190                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9191                                         (tbl->obj, &tbl_data->jump.action);
9192                 if (ret) {
9193                         rte_flow_error_set(error, ENOMEM,
9194                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9195                                            NULL,
9196                                            "cannot create flow jump action");
9197                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9198                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9199                         return NULL;
9200                 }
9201         }
9202         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9203               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9204               key.table_id);
9205         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9206                              flow_dv_matcher_create_cb,
9207                              flow_dv_matcher_match_cb,
9208                              flow_dv_matcher_remove_cb);
9209         return &tbl_data->entry;
9210 }
9211
9212 int
9213 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9214                      struct mlx5_hlist_entry *entry, uint64_t key64,
9215                      void *cb_ctx __rte_unused)
9216 {
9217         struct mlx5_flow_tbl_data_entry *tbl_data =
9218                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9219         union mlx5_flow_tbl_key key = { .v64 = key64 };
9220
9221         return tbl_data->table_id != key.table_id ||
9222                tbl_data->dummy != key.dummy ||
9223                tbl_data->is_transfer != key.domain ||
9224                tbl_data->is_egress != key.direction;
9225 }
9226
9227 /**
9228  * Get a flow table.
9229  *
9230  * @param[in, out] dev
9231  *   Pointer to rte_eth_dev structure.
9232  * @param[in] table_id
9233  *   Table id to use.
9234  * @param[in] egress
9235  *   Direction of the table.
9236  * @param[in] transfer
9237  *   E-Switch or NIC flow.
9238  * @param[in] dummy
9239  *   Dummy entry for dv API.
9240  * @param[out] error
9241  *   pointer to error structure.
9242  *
9243  * @return
9244  *   Returns tables resource based on the index, NULL in case of failed.
9245  */
9246 struct mlx5_flow_tbl_resource *
9247 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9248                          uint32_t table_id, uint8_t egress,
9249                          uint8_t transfer,
9250                          bool external,
9251                          const struct mlx5_flow_tunnel *tunnel,
9252                          uint32_t group_id, uint8_t dummy,
9253                          struct rte_flow_error *error)
9254 {
9255         struct mlx5_priv *priv = dev->data->dev_private;
9256         union mlx5_flow_tbl_key table_key = {
9257                 {
9258                         .table_id = table_id,
9259                         .dummy = dummy,
9260                         .domain = !!transfer,
9261                         .direction = !!egress,
9262                 }
9263         };
9264         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9265                 .tunnel = tunnel,
9266                 .group_id = group_id,
9267                 .external = external,
9268         };
9269         struct mlx5_flow_cb_ctx ctx = {
9270                 .dev = dev,
9271                 .error = error,
9272                 .data = &tt_prm,
9273         };
9274         struct mlx5_hlist_entry *entry;
9275         struct mlx5_flow_tbl_data_entry *tbl_data;
9276
9277         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9278         if (!entry) {
9279                 rte_flow_error_set(error, ENOMEM,
9280                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9281                                    "cannot get table");
9282                 return NULL;
9283         }
9284         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9285                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9286         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9287         return &tbl_data->tbl;
9288 }
9289
9290 void
9291 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9292                       struct mlx5_hlist_entry *entry)
9293 {
9294         struct mlx5_dev_ctx_shared *sh = list->ctx;
9295         struct mlx5_flow_tbl_data_entry *tbl_data =
9296                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9297
9298         MLX5_ASSERT(entry && sh);
9299         if (tbl_data->jump.action)
9300                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9301         if (tbl_data->tbl.obj)
9302                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9303         if (tbl_data->tunnel_offload && tbl_data->external) {
9304                 struct mlx5_hlist_entry *he;
9305                 struct mlx5_hlist *tunnel_grp_hash;
9306                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9307                 union tunnel_tbl_key tunnel_key = {
9308                         .tunnel_id = tbl_data->tunnel ?
9309                                         tbl_data->tunnel->tunnel_id : 0,
9310                         .group = tbl_data->group_id
9311                 };
9312                 uint32_t table_id = tbl_data->table_id;
9313
9314                 tunnel_grp_hash = tbl_data->tunnel ?
9315                                         tbl_data->tunnel->groups :
9316                                         thub->groups;
9317                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9318                 if (he)
9319                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9320                 DRV_LOG(DEBUG,
9321                         "Table_id %u tunnel %u group %u released.",
9322                         table_id,
9323                         tbl_data->tunnel ?
9324                         tbl_data->tunnel->tunnel_id : 0,
9325                         tbl_data->group_id);
9326         }
9327         mlx5_cache_list_destroy(&tbl_data->matchers);
9328         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9329 }
9330
9331 /**
9332  * Release a flow table.
9333  *
9334  * @param[in] sh
9335  *   Pointer to device shared structure.
9336  * @param[in] tbl
9337  *   Table resource to be released.
9338  *
9339  * @return
9340  *   Returns 0 if table was released, else return 1;
9341  */
9342 static int
9343 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9344                              struct mlx5_flow_tbl_resource *tbl)
9345 {
9346         struct mlx5_flow_tbl_data_entry *tbl_data =
9347                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9348
9349         if (!tbl)
9350                 return 0;
9351         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9352 }
9353
9354 int
9355 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9356                          struct mlx5_cache_entry *entry, void *cb_ctx)
9357 {
9358         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9359         struct mlx5_flow_dv_matcher *ref = ctx->data;
9360         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9361                                                         entry);
9362
9363         return cur->crc != ref->crc ||
9364                cur->priority != ref->priority ||
9365                memcmp((const void *)cur->mask.buf,
9366                       (const void *)ref->mask.buf, ref->mask.size);
9367 }
9368
9369 struct mlx5_cache_entry *
9370 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9371                           struct mlx5_cache_entry *entry __rte_unused,
9372                           void *cb_ctx)
9373 {
9374         struct mlx5_dev_ctx_shared *sh = list->ctx;
9375         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9376         struct mlx5_flow_dv_matcher *ref = ctx->data;
9377         struct mlx5_flow_dv_matcher *cache;
9378         struct mlx5dv_flow_matcher_attr dv_attr = {
9379                 .type = IBV_FLOW_ATTR_NORMAL,
9380                 .match_mask = (void *)&ref->mask,
9381         };
9382         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9383                                                             typeof(*tbl), tbl);
9384         int ret;
9385
9386         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9387         if (!cache) {
9388                 rte_flow_error_set(ctx->error, ENOMEM,
9389                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9390                                    "cannot create matcher");
9391                 return NULL;
9392         }
9393         *cache = *ref;
9394         dv_attr.match_criteria_enable =
9395                 flow_dv_matcher_enable(cache->mask.buf);
9396         dv_attr.priority = ref->priority;
9397         if (tbl->is_egress)
9398                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9399         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9400                                                &cache->matcher_object);
9401         if (ret) {
9402                 mlx5_free(cache);
9403                 rte_flow_error_set(ctx->error, ENOMEM,
9404                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9405                                    "cannot create matcher");
9406                 return NULL;
9407         }
9408         return &cache->entry;
9409 }
9410
9411 /**
9412  * Register the flow matcher.
9413  *
9414  * @param[in, out] dev
9415  *   Pointer to rte_eth_dev structure.
9416  * @param[in, out] matcher
9417  *   Pointer to flow matcher.
9418  * @param[in, out] key
9419  *   Pointer to flow table key.
9420  * @parm[in, out] dev_flow
9421  *   Pointer to the dev_flow.
9422  * @param[out] error
9423  *   pointer to error structure.
9424  *
9425  * @return
9426  *   0 on success otherwise -errno and errno is set.
9427  */
9428 static int
9429 flow_dv_matcher_register(struct rte_eth_dev *dev,
9430                          struct mlx5_flow_dv_matcher *ref,
9431                          union mlx5_flow_tbl_key *key,
9432                          struct mlx5_flow *dev_flow,
9433                          const struct mlx5_flow_tunnel *tunnel,
9434                          uint32_t group_id,
9435                          struct rte_flow_error *error)
9436 {
9437         struct mlx5_cache_entry *entry;
9438         struct mlx5_flow_dv_matcher *cache;
9439         struct mlx5_flow_tbl_resource *tbl;
9440         struct mlx5_flow_tbl_data_entry *tbl_data;
9441         struct mlx5_flow_cb_ctx ctx = {
9442                 .error = error,
9443                 .data = ref,
9444         };
9445
9446         /**
9447          * tunnel offload API requires this registration for cases when
9448          * tunnel match rule was inserted before tunnel set rule.
9449          */
9450         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9451                                        key->direction, key->domain,
9452                                        dev_flow->external, tunnel,
9453                                        group_id, 0, error);
9454         if (!tbl)
9455                 return -rte_errno;      /* No need to refill the error info */
9456         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9457         ref->tbl = tbl;
9458         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9459         if (!entry) {
9460                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9461                 return rte_flow_error_set(error, ENOMEM,
9462                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9463                                           "cannot allocate ref memory");
9464         }
9465         cache = container_of(entry, typeof(*cache), entry);
9466         dev_flow->handle->dvh.matcher = cache;
9467         return 0;
9468 }
9469
9470 struct mlx5_hlist_entry *
9471 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9472 {
9473         struct mlx5_dev_ctx_shared *sh = list->ctx;
9474         struct rte_flow_error *error = ctx;
9475         struct mlx5_flow_dv_tag_resource *entry;
9476         uint32_t idx = 0;
9477         int ret;
9478
9479         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9480         if (!entry) {
9481                 rte_flow_error_set(error, ENOMEM,
9482                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9483                                    "cannot allocate resource memory");
9484                 return NULL;
9485         }
9486         entry->idx = idx;
9487         entry->tag_id = key;
9488         ret = mlx5_flow_os_create_flow_action_tag(key,
9489                                                   &entry->action);
9490         if (ret) {
9491                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9492                 rte_flow_error_set(error, ENOMEM,
9493                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9494                                    NULL, "cannot create action");
9495                 return NULL;
9496         }
9497         return &entry->entry;
9498 }
9499
9500 int
9501 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9502                      struct mlx5_hlist_entry *entry, uint64_t key,
9503                      void *cb_ctx __rte_unused)
9504 {
9505         struct mlx5_flow_dv_tag_resource *tag =
9506                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9507
9508         return key != tag->tag_id;
9509 }
9510
9511 /**
9512  * Find existing tag resource or create and register a new one.
9513  *
9514  * @param dev[in, out]
9515  *   Pointer to rte_eth_dev structure.
9516  * @param[in, out] tag_be24
9517  *   Tag value in big endian then R-shift 8.
9518  * @parm[in, out] dev_flow
9519  *   Pointer to the dev_flow.
9520  * @param[out] error
9521  *   pointer to error structure.
9522  *
9523  * @return
9524  *   0 on success otherwise -errno and errno is set.
9525  */
9526 static int
9527 flow_dv_tag_resource_register
9528                         (struct rte_eth_dev *dev,
9529                          uint32_t tag_be24,
9530                          struct mlx5_flow *dev_flow,
9531                          struct rte_flow_error *error)
9532 {
9533         struct mlx5_priv *priv = dev->data->dev_private;
9534         struct mlx5_flow_dv_tag_resource *cache_resource;
9535         struct mlx5_hlist_entry *entry;
9536
9537         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9538         if (entry) {
9539                 cache_resource = container_of
9540                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9541                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9542                 dev_flow->dv.tag_resource = cache_resource;
9543                 return 0;
9544         }
9545         return -rte_errno;
9546 }
9547
9548 void
9549 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9550                       struct mlx5_hlist_entry *entry)
9551 {
9552         struct mlx5_dev_ctx_shared *sh = list->ctx;
9553         struct mlx5_flow_dv_tag_resource *tag =
9554                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9555
9556         MLX5_ASSERT(tag && sh && tag->action);
9557         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9558         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9559         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9560 }
9561
9562 /**
9563  * Release the tag.
9564  *
9565  * @param dev
9566  *   Pointer to Ethernet device.
9567  * @param tag_idx
9568  *   Tag index.
9569  *
9570  * @return
9571  *   1 while a reference on it exists, 0 when freed.
9572  */
9573 static int
9574 flow_dv_tag_release(struct rte_eth_dev *dev,
9575                     uint32_t tag_idx)
9576 {
9577         struct mlx5_priv *priv = dev->data->dev_private;
9578         struct mlx5_flow_dv_tag_resource *tag;
9579
9580         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9581         if (!tag)
9582                 return 0;
9583         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9584                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9585         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9586 }
9587
9588 /**
9589  * Translate port ID action to vport.
9590  *
9591  * @param[in] dev
9592  *   Pointer to rte_eth_dev structure.
9593  * @param[in] action
9594  *   Pointer to the port ID action.
9595  * @param[out] dst_port_id
9596  *   The target port ID.
9597  * @param[out] error
9598  *   Pointer to the error structure.
9599  *
9600  * @return
9601  *   0 on success, a negative errno value otherwise and rte_errno is set.
9602  */
9603 static int
9604 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9605                                  const struct rte_flow_action *action,
9606                                  uint32_t *dst_port_id,
9607                                  struct rte_flow_error *error)
9608 {
9609         uint32_t port;
9610         struct mlx5_priv *priv;
9611         const struct rte_flow_action_port_id *conf =
9612                         (const struct rte_flow_action_port_id *)action->conf;
9613
9614         port = conf->original ? dev->data->port_id : conf->id;
9615         priv = mlx5_port_to_eswitch_info(port, false);
9616         if (!priv)
9617                 return rte_flow_error_set(error, -rte_errno,
9618                                           RTE_FLOW_ERROR_TYPE_ACTION,
9619                                           NULL,
9620                                           "No eswitch info was found for port");
9621 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9622         /*
9623          * This parameter is transferred to
9624          * mlx5dv_dr_action_create_dest_ib_port().
9625          */
9626         *dst_port_id = priv->dev_port;
9627 #else
9628         /*
9629          * Legacy mode, no LAG configurations is supported.
9630          * This parameter is transferred to
9631          * mlx5dv_dr_action_create_dest_vport().
9632          */
9633         *dst_port_id = priv->vport_id;
9634 #endif
9635         return 0;
9636 }
9637
9638 /**
9639  * Create a counter with aging configuration.
9640  *
9641  * @param[in] dev
9642  *   Pointer to rte_eth_dev structure.
9643  * @param[out] count
9644  *   Pointer to the counter action configuration.
9645  * @param[in] age
9646  *   Pointer to the aging action configuration.
9647  *
9648  * @return
9649  *   Index to flow counter on success, 0 otherwise.
9650  */
9651 static uint32_t
9652 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9653                                 struct mlx5_flow *dev_flow,
9654                                 const struct rte_flow_action_count *count,
9655                                 const struct rte_flow_action_age *age)
9656 {
9657         uint32_t counter;
9658         struct mlx5_age_param *age_param;
9659
9660         if (count && count->shared)
9661                 counter = flow_dv_counter_get_shared(dev, count->id);
9662         else
9663                 counter = flow_dv_counter_alloc(dev, !!age);
9664         if (!counter || age == NULL)
9665                 return counter;
9666         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9667         age_param->context = age->context ? age->context :
9668                 (void *)(uintptr_t)(dev_flow->flow_idx);
9669         age_param->timeout = age->timeout;
9670         age_param->port_id = dev->data->port_id;
9671         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9672         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9673         return counter;
9674 }
9675
9676 /**
9677  * Add Tx queue matcher
9678  *
9679  * @param[in] dev
9680  *   Pointer to the dev struct.
9681  * @param[in, out] matcher
9682  *   Flow matcher.
9683  * @param[in, out] key
9684  *   Flow matcher value.
9685  * @param[in] item
9686  *   Flow pattern to translate.
9687  * @param[in] inner
9688  *   Item is inner pattern.
9689  */
9690 static void
9691 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9692                                 void *matcher, void *key,
9693                                 const struct rte_flow_item *item)
9694 {
9695         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9696         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9697         void *misc_m =
9698                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9699         void *misc_v =
9700                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9701         struct mlx5_txq_ctrl *txq;
9702         uint32_t queue;
9703
9704
9705         queue_m = (const void *)item->mask;
9706         if (!queue_m)
9707                 return;
9708         queue_v = (const void *)item->spec;
9709         if (!queue_v)
9710                 return;
9711         txq = mlx5_txq_get(dev, queue_v->queue);
9712         if (!txq)
9713                 return;
9714         queue = txq->obj->sq->id;
9715         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9716         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9717                  queue & queue_m->queue);
9718         mlx5_txq_release(dev, queue_v->queue);
9719 }
9720
9721 /**
9722  * Set the hash fields according to the @p flow information.
9723  *
9724  * @param[in] dev_flow
9725  *   Pointer to the mlx5_flow.
9726  * @param[in] rss_desc
9727  *   Pointer to the mlx5_flow_rss_desc.
9728  */
9729 static void
9730 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9731                        struct mlx5_flow_rss_desc *rss_desc)
9732 {
9733         uint64_t items = dev_flow->handle->layers;
9734         int rss_inner = 0;
9735         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9736
9737         dev_flow->hash_fields = 0;
9738 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9739         if (rss_desc->level >= 2) {
9740                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9741                 rss_inner = 1;
9742         }
9743 #endif
9744         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9745             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9746                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9747                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9748                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9749                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9750                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9751                         else
9752                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9753                 }
9754         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9755                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9756                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9757                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9758                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9759                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9760                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9761                         else
9762                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9763                 }
9764         }
9765         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9766             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9767                 if (rss_types & ETH_RSS_UDP) {
9768                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9769                                 dev_flow->hash_fields |=
9770                                                 IBV_RX_HASH_SRC_PORT_UDP;
9771                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9772                                 dev_flow->hash_fields |=
9773                                                 IBV_RX_HASH_DST_PORT_UDP;
9774                         else
9775                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9776                 }
9777         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9778                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9779                 if (rss_types & ETH_RSS_TCP) {
9780                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9781                                 dev_flow->hash_fields |=
9782                                                 IBV_RX_HASH_SRC_PORT_TCP;
9783                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9784                                 dev_flow->hash_fields |=
9785                                                 IBV_RX_HASH_DST_PORT_TCP;
9786                         else
9787                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9788                 }
9789         }
9790 }
9791
9792 /**
9793  * Prepare an Rx Hash queue.
9794  *
9795  * @param dev
9796  *   Pointer to Ethernet device.
9797  * @param[in] dev_flow
9798  *   Pointer to the mlx5_flow.
9799  * @param[in] rss_desc
9800  *   Pointer to the mlx5_flow_rss_desc.
9801  * @param[out] hrxq_idx
9802  *   Hash Rx queue index.
9803  *
9804  * @return
9805  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9806  */
9807 static struct mlx5_hrxq *
9808 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9809                      struct mlx5_flow *dev_flow,
9810                      struct mlx5_flow_rss_desc *rss_desc,
9811                      uint32_t *hrxq_idx)
9812 {
9813         struct mlx5_priv *priv = dev->data->dev_private;
9814         struct mlx5_flow_handle *dh = dev_flow->handle;
9815         struct mlx5_hrxq *hrxq;
9816
9817         MLX5_ASSERT(rss_desc->queue_num);
9818         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9819         rss_desc->hash_fields = dev_flow->hash_fields;
9820         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9821         rss_desc->shared_rss = 0;
9822         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9823         if (!*hrxq_idx)
9824                 return NULL;
9825         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9826                               *hrxq_idx);
9827         return hrxq;
9828 }
9829
9830 /**
9831  * Release sample sub action resource.
9832  *
9833  * @param[in, out] dev
9834  *   Pointer to rte_eth_dev structure.
9835  * @param[in] act_res
9836  *   Pointer to sample sub action resource.
9837  */
9838 static void
9839 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9840                                    struct mlx5_flow_sub_actions_idx *act_res)
9841 {
9842         if (act_res->rix_hrxq) {
9843                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9844                 act_res->rix_hrxq = 0;
9845         }
9846         if (act_res->rix_encap_decap) {
9847                 flow_dv_encap_decap_resource_release(dev,
9848                                                      act_res->rix_encap_decap);
9849                 act_res->rix_encap_decap = 0;
9850         }
9851         if (act_res->rix_port_id_action) {
9852                 flow_dv_port_id_action_resource_release(dev,
9853                                                 act_res->rix_port_id_action);
9854                 act_res->rix_port_id_action = 0;
9855         }
9856         if (act_res->rix_tag) {
9857                 flow_dv_tag_release(dev, act_res->rix_tag);
9858                 act_res->rix_tag = 0;
9859         }
9860         if (act_res->rix_jump) {
9861                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9862                 act_res->rix_jump = 0;
9863         }
9864 }
9865
9866 int
9867 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9868                         struct mlx5_cache_entry *entry, void *cb_ctx)
9869 {
9870         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9871         struct rte_eth_dev *dev = ctx->dev;
9872         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9873         struct mlx5_flow_dv_sample_resource *cache_resource =
9874                         container_of(entry, typeof(*cache_resource), entry);
9875
9876         if (resource->ratio == cache_resource->ratio &&
9877             resource->ft_type == cache_resource->ft_type &&
9878             resource->ft_id == cache_resource->ft_id &&
9879             resource->set_action == cache_resource->set_action &&
9880             !memcmp((void *)&resource->sample_act,
9881                     (void *)&cache_resource->sample_act,
9882                     sizeof(struct mlx5_flow_sub_actions_list))) {
9883                 /*
9884                  * Existing sample action should release the prepared
9885                  * sub-actions reference counter.
9886                  */
9887                 flow_dv_sample_sub_actions_release(dev,
9888                                                 &resource->sample_idx);
9889                 return 0;
9890         }
9891         return 1;
9892 }
9893
9894 struct mlx5_cache_entry *
9895 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9896                          struct mlx5_cache_entry *entry __rte_unused,
9897                          void *cb_ctx)
9898 {
9899         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9900         struct rte_eth_dev *dev = ctx->dev;
9901         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9902         void **sample_dv_actions = resource->sub_actions;
9903         struct mlx5_flow_dv_sample_resource *cache_resource;
9904         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9905         struct mlx5_priv *priv = dev->data->dev_private;
9906         struct mlx5_dev_ctx_shared *sh = priv->sh;
9907         struct mlx5_flow_tbl_resource *tbl;
9908         uint32_t idx = 0;
9909         const uint32_t next_ft_step = 1;
9910         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9911         uint8_t is_egress = 0;
9912         uint8_t is_transfer = 0;
9913         struct rte_flow_error *error = ctx->error;
9914
9915         /* Register new sample resource. */
9916         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9917         if (!cache_resource) {
9918                 rte_flow_error_set(error, ENOMEM,
9919                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9920                                           NULL,
9921                                           "cannot allocate resource memory");
9922                 return NULL;
9923         }
9924         *cache_resource = *resource;
9925         /* Create normal path table level */
9926         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9927                 is_transfer = 1;
9928         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9929                 is_egress = 1;
9930         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9931                                         is_egress, is_transfer,
9932                                         true, NULL, 0, 0, error);
9933         if (!tbl) {
9934                 rte_flow_error_set(error, ENOMEM,
9935                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9936                                           NULL,
9937                                           "fail to create normal path table "
9938                                           "for sample");
9939                 goto error;
9940         }
9941         cache_resource->normal_path_tbl = tbl;
9942         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9943                 if (!sh->default_miss_action) {
9944                         rte_flow_error_set(error, ENOMEM,
9945                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9946                                                 NULL,
9947                                                 "default miss action was not "
9948                                                 "created");
9949                         goto error;
9950                 }
9951                 sample_dv_actions[resource->sample_act.actions_num++] =
9952                                                 sh->default_miss_action;
9953         }
9954         /* Create a DR sample action */
9955         sampler_attr.sample_ratio = cache_resource->ratio;
9956         sampler_attr.default_next_table = tbl->obj;
9957         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9958         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9959                                                         &sample_dv_actions[0];
9960         sampler_attr.action = cache_resource->set_action;
9961         if (mlx5_os_flow_dr_create_flow_action_sampler
9962                         (&sampler_attr, &cache_resource->verbs_action)) {
9963                 rte_flow_error_set(error, ENOMEM,
9964                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9965                                         NULL, "cannot create sample action");
9966                 goto error;
9967         }
9968         cache_resource->idx = idx;
9969         cache_resource->dev = dev;
9970         return &cache_resource->entry;
9971 error:
9972         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9973                 flow_dv_sample_sub_actions_release(dev,
9974                                                    &cache_resource->sample_idx);
9975         if (cache_resource->normal_path_tbl)
9976                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9977                                 cache_resource->normal_path_tbl);
9978         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9979         return NULL;
9980
9981 }
9982
9983 /**
9984  * Find existing sample resource or create and register a new one.
9985  *
9986  * @param[in, out] dev
9987  *   Pointer to rte_eth_dev structure.
9988  * @param[in] resource
9989  *   Pointer to sample resource.
9990  * @parm[in, out] dev_flow
9991  *   Pointer to the dev_flow.
9992  * @param[out] error
9993  *   pointer to error structure.
9994  *
9995  * @return
9996  *   0 on success otherwise -errno and errno is set.
9997  */
9998 static int
9999 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10000                          struct mlx5_flow_dv_sample_resource *resource,
10001                          struct mlx5_flow *dev_flow,
10002                          struct rte_flow_error *error)
10003 {
10004         struct mlx5_flow_dv_sample_resource *cache_resource;
10005         struct mlx5_cache_entry *entry;
10006         struct mlx5_priv *priv = dev->data->dev_private;
10007         struct mlx5_flow_cb_ctx ctx = {
10008                 .dev = dev,
10009                 .error = error,
10010                 .data = resource,
10011         };
10012
10013         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10014         if (!entry)
10015                 return -rte_errno;
10016         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10017         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10018         dev_flow->dv.sample_res = cache_resource;
10019         return 0;
10020 }
10021
10022 int
10023 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10024                             struct mlx5_cache_entry *entry, void *cb_ctx)
10025 {
10026         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10027         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10028         struct rte_eth_dev *dev = ctx->dev;
10029         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10030                         container_of(entry, typeof(*cache_resource), entry);
10031         uint32_t idx = 0;
10032
10033         if (resource->num_of_dest == cache_resource->num_of_dest &&
10034             resource->ft_type == cache_resource->ft_type &&
10035             !memcmp((void *)cache_resource->sample_act,
10036                     (void *)resource->sample_act,
10037                    (resource->num_of_dest *
10038                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10039                 /*
10040                  * Existing sample action should release the prepared
10041                  * sub-actions reference counter.
10042                  */
10043                 for (idx = 0; idx < resource->num_of_dest; idx++)
10044                         flow_dv_sample_sub_actions_release(dev,
10045                                         &resource->sample_idx[idx]);
10046                 return 0;
10047         }
10048         return 1;
10049 }
10050
10051 struct mlx5_cache_entry *
10052 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10053                          struct mlx5_cache_entry *entry __rte_unused,
10054                          void *cb_ctx)
10055 {
10056         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10057         struct rte_eth_dev *dev = ctx->dev;
10058         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10059         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10060         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10061         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10062         struct mlx5_priv *priv = dev->data->dev_private;
10063         struct mlx5_dev_ctx_shared *sh = priv->sh;
10064         struct mlx5_flow_sub_actions_list *sample_act;
10065         struct mlx5dv_dr_domain *domain;
10066         uint32_t idx = 0, res_idx = 0;
10067         struct rte_flow_error *error = ctx->error;
10068         uint64_t action_flags;
10069         int ret;
10070
10071         /* Register new destination array resource. */
10072         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10073                                             &res_idx);
10074         if (!cache_resource) {
10075                 rte_flow_error_set(error, ENOMEM,
10076                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10077                                           NULL,
10078                                           "cannot allocate resource memory");
10079                 return NULL;
10080         }
10081         *cache_resource = *resource;
10082         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10083                 domain = sh->fdb_domain;
10084         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10085                 domain = sh->rx_domain;
10086         else
10087                 domain = sh->tx_domain;
10088         for (idx = 0; idx < resource->num_of_dest; idx++) {
10089                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10090                                  mlx5_malloc(MLX5_MEM_ZERO,
10091                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10092                                  0, SOCKET_ID_ANY);
10093                 if (!dest_attr[idx]) {
10094                         rte_flow_error_set(error, ENOMEM,
10095                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10096                                            NULL,
10097                                            "cannot allocate resource memory");
10098                         goto error;
10099                 }
10100                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10101                 sample_act = &resource->sample_act[idx];
10102                 action_flags = sample_act->action_flags;
10103                 switch (action_flags) {
10104                 case MLX5_FLOW_ACTION_QUEUE:
10105                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10106                         break;
10107                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10108                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10109                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10110                         dest_attr[idx]->dest_reformat->reformat =
10111                                         sample_act->dr_encap_action;
10112                         dest_attr[idx]->dest_reformat->dest =
10113                                         sample_act->dr_port_id_action;
10114                         break;
10115                 case MLX5_FLOW_ACTION_PORT_ID:
10116                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10117                         break;
10118                 case MLX5_FLOW_ACTION_JUMP:
10119                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10120                         break;
10121                 default:
10122                         rte_flow_error_set(error, EINVAL,
10123                                            RTE_FLOW_ERROR_TYPE_ACTION,
10124                                            NULL,
10125                                            "unsupported actions type");
10126                         goto error;
10127                 }
10128         }
10129         /* create a dest array actioin */
10130         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10131                                                 (domain,
10132                                                  cache_resource->num_of_dest,
10133                                                  dest_attr,
10134                                                  &cache_resource->action);
10135         if (ret) {
10136                 rte_flow_error_set(error, ENOMEM,
10137                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10138                                    NULL,
10139                                    "cannot create destination array action");
10140                 goto error;
10141         }
10142         cache_resource->idx = res_idx;
10143         cache_resource->dev = dev;
10144         for (idx = 0; idx < resource->num_of_dest; idx++)
10145                 mlx5_free(dest_attr[idx]);
10146         return &cache_resource->entry;
10147 error:
10148         for (idx = 0; idx < resource->num_of_dest; idx++) {
10149                 struct mlx5_flow_sub_actions_idx *act_res =
10150                                         &cache_resource->sample_idx[idx];
10151                 if (act_res->rix_hrxq &&
10152                     !mlx5_hrxq_release(dev,
10153                                 act_res->rix_hrxq))
10154                         act_res->rix_hrxq = 0;
10155                 if (act_res->rix_encap_decap &&
10156                         !flow_dv_encap_decap_resource_release(dev,
10157                                 act_res->rix_encap_decap))
10158                         act_res->rix_encap_decap = 0;
10159                 if (act_res->rix_port_id_action &&
10160                         !flow_dv_port_id_action_resource_release(dev,
10161                                 act_res->rix_port_id_action))
10162                         act_res->rix_port_id_action = 0;
10163                 if (act_res->rix_jump &&
10164                         !flow_dv_jump_tbl_resource_release(dev,
10165                                 act_res->rix_jump))
10166                         act_res->rix_jump = 0;
10167                 if (dest_attr[idx])
10168                         mlx5_free(dest_attr[idx]);
10169         }
10170
10171         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10172         return NULL;
10173 }
10174
10175 /**
10176  * Find existing destination array resource or create and register a new one.
10177  *
10178  * @param[in, out] dev
10179  *   Pointer to rte_eth_dev structure.
10180  * @param[in] resource
10181  *   Pointer to destination array resource.
10182  * @parm[in, out] dev_flow
10183  *   Pointer to the dev_flow.
10184  * @param[out] error
10185  *   pointer to error structure.
10186  *
10187  * @return
10188  *   0 on success otherwise -errno and errno is set.
10189  */
10190 static int
10191 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10192                          struct mlx5_flow_dv_dest_array_resource *resource,
10193                          struct mlx5_flow *dev_flow,
10194                          struct rte_flow_error *error)
10195 {
10196         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10197         struct mlx5_priv *priv = dev->data->dev_private;
10198         struct mlx5_cache_entry *entry;
10199         struct mlx5_flow_cb_ctx ctx = {
10200                 .dev = dev,
10201                 .error = error,
10202                 .data = resource,
10203         };
10204
10205         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10206         if (!entry)
10207                 return -rte_errno;
10208         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10209         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10210         dev_flow->dv.dest_array_res = cache_resource;
10211         return 0;
10212 }
10213
10214 /**
10215  * Convert Sample action to DV specification.
10216  *
10217  * @param[in] dev
10218  *   Pointer to rte_eth_dev structure.
10219  * @param[in] action
10220  *   Pointer to sample action structure.
10221  * @param[in, out] dev_flow
10222  *   Pointer to the mlx5_flow.
10223  * @param[in] attr
10224  *   Pointer to the flow attributes.
10225  * @param[in, out] num_of_dest
10226  *   Pointer to the num of destination.
10227  * @param[in, out] sample_actions
10228  *   Pointer to sample actions list.
10229  * @param[in, out] res
10230  *   Pointer to sample resource.
10231  * @param[out] error
10232  *   Pointer to the error structure.
10233  *
10234  * @return
10235  *   0 on success, a negative errno value otherwise and rte_errno is set.
10236  */
10237 static int
10238 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10239                                 const struct rte_flow_action_sample *action,
10240                                 struct mlx5_flow *dev_flow,
10241                                 const struct rte_flow_attr *attr,
10242                                 uint32_t *num_of_dest,
10243                                 void **sample_actions,
10244                                 struct mlx5_flow_dv_sample_resource *res,
10245                                 struct rte_flow_error *error)
10246 {
10247         struct mlx5_priv *priv = dev->data->dev_private;
10248         const struct rte_flow_action *sub_actions;
10249         struct mlx5_flow_sub_actions_list *sample_act;
10250         struct mlx5_flow_sub_actions_idx *sample_idx;
10251         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10252         struct rte_flow *flow = dev_flow->flow;
10253         struct mlx5_flow_rss_desc *rss_desc;
10254         uint64_t action_flags = 0;
10255
10256         MLX5_ASSERT(wks);
10257         rss_desc = &wks->rss_desc;
10258         sample_act = &res->sample_act;
10259         sample_idx = &res->sample_idx;
10260         res->ratio = action->ratio;
10261         sub_actions = action->actions;
10262         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10263                 int type = sub_actions->type;
10264                 uint32_t pre_rix = 0;
10265                 void *pre_r;
10266                 switch (type) {
10267                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10268                 {
10269                         const struct rte_flow_action_queue *queue;
10270                         struct mlx5_hrxq *hrxq;
10271                         uint32_t hrxq_idx;
10272
10273                         queue = sub_actions->conf;
10274                         rss_desc->queue_num = 1;
10275                         rss_desc->queue[0] = queue->index;
10276                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10277                                                     rss_desc, &hrxq_idx);
10278                         if (!hrxq)
10279                                 return rte_flow_error_set
10280                                         (error, rte_errno,
10281                                          RTE_FLOW_ERROR_TYPE_ACTION,
10282                                          NULL,
10283                                          "cannot create fate queue");
10284                         sample_act->dr_queue_action = hrxq->action;
10285                         sample_idx->rix_hrxq = hrxq_idx;
10286                         sample_actions[sample_act->actions_num++] =
10287                                                 hrxq->action;
10288                         (*num_of_dest)++;
10289                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10290                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10291                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10292                         dev_flow->handle->fate_action =
10293                                         MLX5_FLOW_FATE_QUEUE;
10294                         break;
10295                 }
10296                 case RTE_FLOW_ACTION_TYPE_RSS:
10297                 {
10298                         struct mlx5_hrxq *hrxq;
10299                         uint32_t hrxq_idx;
10300                         const struct rte_flow_action_rss *rss;
10301                         const uint8_t *rss_key;
10302
10303                         rss = sub_actions->conf;
10304                         memcpy(rss_desc->queue, rss->queue,
10305                                rss->queue_num * sizeof(uint16_t));
10306                         rss_desc->queue_num = rss->queue_num;
10307                         /* NULL RSS key indicates default RSS key. */
10308                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10309                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10310                         /*
10311                          * rss->level and rss.types should be set in advance
10312                          * when expanding items for RSS.
10313                          */
10314                         flow_dv_hashfields_set(dev_flow, rss_desc);
10315                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10316                                                     rss_desc, &hrxq_idx);
10317                         if (!hrxq)
10318                                 return rte_flow_error_set
10319                                         (error, rte_errno,
10320                                          RTE_FLOW_ERROR_TYPE_ACTION,
10321                                          NULL,
10322                                          "cannot create fate queue");
10323                         sample_act->dr_queue_action = hrxq->action;
10324                         sample_idx->rix_hrxq = hrxq_idx;
10325                         sample_actions[sample_act->actions_num++] =
10326                                                 hrxq->action;
10327                         (*num_of_dest)++;
10328                         action_flags |= MLX5_FLOW_ACTION_RSS;
10329                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10330                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10331                         dev_flow->handle->fate_action =
10332                                         MLX5_FLOW_FATE_QUEUE;
10333                         break;
10334                 }
10335                 case RTE_FLOW_ACTION_TYPE_MARK:
10336                 {
10337                         uint32_t tag_be = mlx5_flow_mark_set
10338                                 (((const struct rte_flow_action_mark *)
10339                                 (sub_actions->conf))->id);
10340
10341                         dev_flow->handle->mark = 1;
10342                         pre_rix = dev_flow->handle->dvh.rix_tag;
10343                         /* Save the mark resource before sample */
10344                         pre_r = dev_flow->dv.tag_resource;
10345                         if (flow_dv_tag_resource_register(dev, tag_be,
10346                                                   dev_flow, error))
10347                                 return -rte_errno;
10348                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10349                         sample_act->dr_tag_action =
10350                                 dev_flow->dv.tag_resource->action;
10351                         sample_idx->rix_tag =
10352                                 dev_flow->handle->dvh.rix_tag;
10353                         sample_actions[sample_act->actions_num++] =
10354                                                 sample_act->dr_tag_action;
10355                         /* Recover the mark resource after sample */
10356                         dev_flow->dv.tag_resource = pre_r;
10357                         dev_flow->handle->dvh.rix_tag = pre_rix;
10358                         action_flags |= MLX5_FLOW_ACTION_MARK;
10359                         break;
10360                 }
10361                 case RTE_FLOW_ACTION_TYPE_COUNT:
10362                 {
10363                         if (!flow->counter) {
10364                                 flow->counter =
10365                                         flow_dv_translate_create_counter(dev,
10366                                                 dev_flow, sub_actions->conf,
10367                                                 0);
10368                                 if (!flow->counter)
10369                                         return rte_flow_error_set
10370                                                 (error, rte_errno,
10371                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10372                                                 NULL,
10373                                                 "cannot create counter"
10374                                                 " object.");
10375                         }
10376                         sample_act->dr_cnt_action =
10377                                   (flow_dv_counter_get_by_idx(dev,
10378                                   flow->counter, NULL))->action;
10379                         sample_actions[sample_act->actions_num++] =
10380                                                 sample_act->dr_cnt_action;
10381                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10382                         break;
10383                 }
10384                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10385                 {
10386                         struct mlx5_flow_dv_port_id_action_resource
10387                                         port_id_resource;
10388                         uint32_t port_id = 0;
10389
10390                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10391                         /* Save the port id resource before sample */
10392                         pre_rix = dev_flow->handle->rix_port_id_action;
10393                         pre_r = dev_flow->dv.port_id_action;
10394                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10395                                                              &port_id, error))
10396                                 return -rte_errno;
10397                         port_id_resource.port_id = port_id;
10398                         if (flow_dv_port_id_action_resource_register
10399                             (dev, &port_id_resource, dev_flow, error))
10400                                 return -rte_errno;
10401                         sample_act->dr_port_id_action =
10402                                 dev_flow->dv.port_id_action->action;
10403                         sample_idx->rix_port_id_action =
10404                                 dev_flow->handle->rix_port_id_action;
10405                         sample_actions[sample_act->actions_num++] =
10406                                                 sample_act->dr_port_id_action;
10407                         /* Recover the port id resource after sample */
10408                         dev_flow->dv.port_id_action = pre_r;
10409                         dev_flow->handle->rix_port_id_action = pre_rix;
10410                         (*num_of_dest)++;
10411                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10412                         break;
10413                 }
10414                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10415                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10416                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10417                         /* Save the encap resource before sample */
10418                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10419                         pre_r = dev_flow->dv.encap_decap;
10420                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10421                                                            dev_flow,
10422                                                            attr->transfer,
10423                                                            error))
10424                                 return -rte_errno;
10425                         sample_act->dr_encap_action =
10426                                 dev_flow->dv.encap_decap->action;
10427                         sample_idx->rix_encap_decap =
10428                                 dev_flow->handle->dvh.rix_encap_decap;
10429                         sample_actions[sample_act->actions_num++] =
10430                                                 sample_act->dr_encap_action;
10431                         /* Recover the encap resource after sample */
10432                         dev_flow->dv.encap_decap = pre_r;
10433                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10434                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10435                         break;
10436                 default:
10437                         return rte_flow_error_set(error, EINVAL,
10438                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10439                                 NULL,
10440                                 "Not support for sampler action");
10441                 }
10442         }
10443         sample_act->action_flags = action_flags;
10444         res->ft_id = dev_flow->dv.group;
10445         if (attr->transfer) {
10446                 union {
10447                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10448                         uint64_t set_action;
10449                 } action_ctx = { .set_action = 0 };
10450
10451                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10452                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10453                          MLX5_MODIFICATION_TYPE_SET);
10454                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10455                          MLX5_MODI_META_REG_C_0);
10456                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10457                          priv->vport_meta_tag);
10458                 res->set_action = action_ctx.set_action;
10459         } else if (attr->ingress) {
10460                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10461         } else {
10462                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10463         }
10464         return 0;
10465 }
10466
10467 /**
10468  * Convert Sample action to DV specification.
10469  *
10470  * @param[in] dev
10471  *   Pointer to rte_eth_dev structure.
10472  * @param[in, out] dev_flow
10473  *   Pointer to the mlx5_flow.
10474  * @param[in] num_of_dest
10475  *   The num of destination.
10476  * @param[in, out] res
10477  *   Pointer to sample resource.
10478  * @param[in, out] mdest_res
10479  *   Pointer to destination array resource.
10480  * @param[in] sample_actions
10481  *   Pointer to sample path actions list.
10482  * @param[in] action_flags
10483  *   Holds the actions detected until now.
10484  * @param[out] error
10485  *   Pointer to the error structure.
10486  *
10487  * @return
10488  *   0 on success, a negative errno value otherwise and rte_errno is set.
10489  */
10490 static int
10491 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10492                              struct mlx5_flow *dev_flow,
10493                              uint32_t num_of_dest,
10494                              struct mlx5_flow_dv_sample_resource *res,
10495                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10496                              void **sample_actions,
10497                              uint64_t action_flags,
10498                              struct rte_flow_error *error)
10499 {
10500         /* update normal path action resource into last index of array */
10501         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10502         struct mlx5_flow_sub_actions_list *sample_act =
10503                                         &mdest_res->sample_act[dest_index];
10504         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10505         struct mlx5_flow_rss_desc *rss_desc;
10506         uint32_t normal_idx = 0;
10507         struct mlx5_hrxq *hrxq;
10508         uint32_t hrxq_idx;
10509
10510         MLX5_ASSERT(wks);
10511         rss_desc = &wks->rss_desc;
10512         if (num_of_dest > 1) {
10513                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10514                         /* Handle QP action for mirroring */
10515                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10516                                                     rss_desc, &hrxq_idx);
10517                         if (!hrxq)
10518                                 return rte_flow_error_set
10519                                      (error, rte_errno,
10520                                       RTE_FLOW_ERROR_TYPE_ACTION,
10521                                       NULL,
10522                                       "cannot create rx queue");
10523                         normal_idx++;
10524                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10525                         sample_act->dr_queue_action = hrxq->action;
10526                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10527                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10528                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10529                 }
10530                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10531                         normal_idx++;
10532                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10533                                 dev_flow->handle->dvh.rix_encap_decap;
10534                         sample_act->dr_encap_action =
10535                                 dev_flow->dv.encap_decap->action;
10536                 }
10537                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10538                         normal_idx++;
10539                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10540                                 dev_flow->handle->rix_port_id_action;
10541                         sample_act->dr_port_id_action =
10542                                 dev_flow->dv.port_id_action->action;
10543                 }
10544                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10545                         normal_idx++;
10546                         mdest_res->sample_idx[dest_index].rix_jump =
10547                                 dev_flow->handle->rix_jump;
10548                         sample_act->dr_jump_action =
10549                                 dev_flow->dv.jump->action;
10550                         dev_flow->handle->rix_jump = 0;
10551                 }
10552                 sample_act->actions_num = normal_idx;
10553                 /* update sample action resource into first index of array */
10554                 mdest_res->ft_type = res->ft_type;
10555                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10556                                 sizeof(struct mlx5_flow_sub_actions_idx));
10557                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10558                                 sizeof(struct mlx5_flow_sub_actions_list));
10559                 mdest_res->num_of_dest = num_of_dest;
10560                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10561                                                          dev_flow, error))
10562                         return rte_flow_error_set(error, EINVAL,
10563                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10564                                                   NULL, "can't create sample "
10565                                                   "action");
10566         } else {
10567                 res->sub_actions = sample_actions;
10568                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10569                         return rte_flow_error_set(error, EINVAL,
10570                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10571                                                   NULL,
10572                                                   "can't create sample action");
10573         }
10574         return 0;
10575 }
10576
10577 /**
10578  * Remove an ASO age action from age actions list.
10579  *
10580  * @param[in] dev
10581  *   Pointer to the Ethernet device structure.
10582  * @param[in] age
10583  *   Pointer to the aso age action handler.
10584  */
10585 static void
10586 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10587                                 struct mlx5_aso_age_action *age)
10588 {
10589         struct mlx5_age_info *age_info;
10590         struct mlx5_age_param *age_param = &age->age_params;
10591         struct mlx5_priv *priv = dev->data->dev_private;
10592         uint16_t expected = AGE_CANDIDATE;
10593
10594         age_info = GET_PORT_AGE_INFO(priv);
10595         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10596                                          AGE_FREE, false, __ATOMIC_RELAXED,
10597                                          __ATOMIC_RELAXED)) {
10598                 /**
10599                  * We need the lock even it is age timeout,
10600                  * since age action may still in process.
10601                  */
10602                 rte_spinlock_lock(&age_info->aged_sl);
10603                 LIST_REMOVE(age, next);
10604                 rte_spinlock_unlock(&age_info->aged_sl);
10605                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10606         }
10607 }
10608
10609 /**
10610  * Release an ASO age action.
10611  *
10612  * @param[in] dev
10613  *   Pointer to the Ethernet device structure.
10614  * @param[in] age_idx
10615  *   Index of ASO age action to release.
10616  * @param[in] flow
10617  *   True if the release operation is during flow destroy operation.
10618  *   False if the release operation is during action destroy operation.
10619  *
10620  * @return
10621  *   0 when age action was removed, otherwise the number of references.
10622  */
10623 static int
10624 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10625 {
10626         struct mlx5_priv *priv = dev->data->dev_private;
10627         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10628         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10629         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10630
10631         if (!ret) {
10632                 flow_dv_aso_age_remove_from_age(dev, age);
10633                 rte_spinlock_lock(&mng->free_sl);
10634                 LIST_INSERT_HEAD(&mng->free, age, next);
10635                 rte_spinlock_unlock(&mng->free_sl);
10636         }
10637         return ret;
10638 }
10639
10640 /**
10641  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10642  *
10643  * @param[in] dev
10644  *   Pointer to the Ethernet device structure.
10645  *
10646  * @return
10647  *   0 on success, otherwise negative errno value and rte_errno is set.
10648  */
10649 static int
10650 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10651 {
10652         struct mlx5_priv *priv = dev->data->dev_private;
10653         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10654         void *old_pools = mng->pools;
10655         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10656         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10657         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10658
10659         if (!pools) {
10660                 rte_errno = ENOMEM;
10661                 return -ENOMEM;
10662         }
10663         if (old_pools) {
10664                 memcpy(pools, old_pools,
10665                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10666                 mlx5_free(old_pools);
10667         } else {
10668                 /* First ASO flow hit allocation - starting ASO data-path. */
10669                 int ret = mlx5_aso_queue_start(priv->sh);
10670
10671                 if (ret) {
10672                         mlx5_free(pools);
10673                         return ret;
10674                 }
10675         }
10676         mng->n = resize;
10677         mng->pools = pools;
10678         return 0;
10679 }
10680
10681 /**
10682  * Create and initialize a new ASO aging pool.
10683  *
10684  * @param[in] dev
10685  *   Pointer to the Ethernet device structure.
10686  * @param[out] age_free
10687  *   Where to put the pointer of a new age action.
10688  *
10689  * @return
10690  *   The age actions pool pointer and @p age_free is set on success,
10691  *   NULL otherwise and rte_errno is set.
10692  */
10693 static struct mlx5_aso_age_pool *
10694 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10695                         struct mlx5_aso_age_action **age_free)
10696 {
10697         struct mlx5_priv *priv = dev->data->dev_private;
10698         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10699         struct mlx5_aso_age_pool *pool = NULL;
10700         struct mlx5_devx_obj *obj = NULL;
10701         uint32_t i;
10702
10703         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10704                                                     priv->sh->pdn);
10705         if (!obj) {
10706                 rte_errno = ENODATA;
10707                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10708                 return NULL;
10709         }
10710         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10711         if (!pool) {
10712                 claim_zero(mlx5_devx_cmd_destroy(obj));
10713                 rte_errno = ENOMEM;
10714                 return NULL;
10715         }
10716         pool->flow_hit_aso_obj = obj;
10717         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10718         rte_spinlock_lock(&mng->resize_sl);
10719         pool->index = mng->next;
10720         /* Resize pools array if there is no room for the new pool in it. */
10721         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10722                 claim_zero(mlx5_devx_cmd_destroy(obj));
10723                 mlx5_free(pool);
10724                 rte_spinlock_unlock(&mng->resize_sl);
10725                 return NULL;
10726         }
10727         mng->pools[pool->index] = pool;
10728         mng->next++;
10729         rte_spinlock_unlock(&mng->resize_sl);
10730         /* Assign the first action in the new pool, the rest go to free list. */
10731         *age_free = &pool->actions[0];
10732         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10733                 pool->actions[i].offset = i;
10734                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10735         }
10736         return pool;
10737 }
10738
10739 /**
10740  * Allocate a ASO aging bit.
10741  *
10742  * @param[in] dev
10743  *   Pointer to the Ethernet device structure.
10744  * @param[out] error
10745  *   Pointer to the error structure.
10746  *
10747  * @return
10748  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10749  */
10750 static uint32_t
10751 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10752 {
10753         struct mlx5_priv *priv = dev->data->dev_private;
10754         const struct mlx5_aso_age_pool *pool;
10755         struct mlx5_aso_age_action *age_free = NULL;
10756         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10757
10758         MLX5_ASSERT(mng);
10759         /* Try to get the next free age action bit. */
10760         rte_spinlock_lock(&mng->free_sl);
10761         age_free = LIST_FIRST(&mng->free);
10762         if (age_free) {
10763                 LIST_REMOVE(age_free, next);
10764         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10765                 rte_spinlock_unlock(&mng->free_sl);
10766                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10767                                    NULL, "failed to create ASO age pool");
10768                 return 0; /* 0 is an error. */
10769         }
10770         rte_spinlock_unlock(&mng->free_sl);
10771         pool = container_of
10772           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10773                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10774                                                                        actions);
10775         if (!age_free->dr_action) {
10776                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10777                                                  error);
10778
10779                 if (reg_c < 0) {
10780                         rte_flow_error_set(error, rte_errno,
10781                                            RTE_FLOW_ERROR_TYPE_ACTION,
10782                                            NULL, "failed to get reg_c "
10783                                            "for ASO flow hit");
10784                         return 0; /* 0 is an error. */
10785                 }
10786 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10787                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10788                                 (priv->sh->rx_domain,
10789                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10790                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10791                                  (reg_c - REG_C_0));
10792 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10793                 if (!age_free->dr_action) {
10794                         rte_errno = errno;
10795                         rte_spinlock_lock(&mng->free_sl);
10796                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10797                         rte_spinlock_unlock(&mng->free_sl);
10798                         rte_flow_error_set(error, rte_errno,
10799                                            RTE_FLOW_ERROR_TYPE_ACTION,
10800                                            NULL, "failed to create ASO "
10801                                            "flow hit action");
10802                         return 0; /* 0 is an error. */
10803                 }
10804         }
10805         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10806         return pool->index | ((age_free->offset + 1) << 16);
10807 }
10808
10809 /**
10810  * Create a age action using ASO mechanism.
10811  *
10812  * @param[in] dev
10813  *   Pointer to rte_eth_dev structure.
10814  * @param[in] age
10815  *   Pointer to the aging action configuration.
10816  * @param[out] error
10817  *   Pointer to the error structure.
10818  *
10819  * @return
10820  *   Index to flow counter on success, 0 otherwise.
10821  */
10822 static uint32_t
10823 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10824                                  const struct rte_flow_action_age *age,
10825                                  struct rte_flow_error *error)
10826 {
10827         uint32_t age_idx = 0;
10828         struct mlx5_aso_age_action *aso_age;
10829
10830         age_idx = flow_dv_aso_age_alloc(dev, error);
10831         if (!age_idx)
10832                 return 0;
10833         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10834         aso_age->age_params.context = age->context;
10835         aso_age->age_params.timeout = age->timeout;
10836         aso_age->age_params.port_id = dev->data->port_id;
10837         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10838                          __ATOMIC_RELAXED);
10839         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10840                          __ATOMIC_RELAXED);
10841         return age_idx;
10842 }
10843
10844 /**
10845  * Fill the flow with DV spec, lock free
10846  * (mutex should be acquired by caller).
10847  *
10848  * @param[in] dev
10849  *   Pointer to rte_eth_dev structure.
10850  * @param[in, out] dev_flow
10851  *   Pointer to the sub flow.
10852  * @param[in] attr
10853  *   Pointer to the flow attributes.
10854  * @param[in] items
10855  *   Pointer to the list of items.
10856  * @param[in] actions
10857  *   Pointer to the list of actions.
10858  * @param[out] error
10859  *   Pointer to the error structure.
10860  *
10861  * @return
10862  *   0 on success, a negative errno value otherwise and rte_errno is set.
10863  */
10864 static int
10865 flow_dv_translate(struct rte_eth_dev *dev,
10866                   struct mlx5_flow *dev_flow,
10867                   const struct rte_flow_attr *attr,
10868                   const struct rte_flow_item items[],
10869                   const struct rte_flow_action actions[],
10870                   struct rte_flow_error *error)
10871 {
10872         struct mlx5_priv *priv = dev->data->dev_private;
10873         struct mlx5_dev_config *dev_conf = &priv->config;
10874         struct rte_flow *flow = dev_flow->flow;
10875         struct mlx5_flow_handle *handle = dev_flow->handle;
10876         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10877         struct mlx5_flow_rss_desc *rss_desc;
10878         uint64_t item_flags = 0;
10879         uint64_t last_item = 0;
10880         uint64_t action_flags = 0;
10881         struct mlx5_flow_dv_matcher matcher = {
10882                 .mask = {
10883                         .size = sizeof(matcher.mask.buf) -
10884                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10885                 },
10886         };
10887         int actions_n = 0;
10888         bool actions_end = false;
10889         union {
10890                 struct mlx5_flow_dv_modify_hdr_resource res;
10891                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10892                             sizeof(struct mlx5_modification_cmd) *
10893                             (MLX5_MAX_MODIFY_NUM + 1)];
10894         } mhdr_dummy;
10895         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10896         const struct rte_flow_action_count *count = NULL;
10897         const struct rte_flow_action_age *age = NULL;
10898         union flow_dv_attr flow_attr = { .attr = 0 };
10899         uint32_t tag_be;
10900         union mlx5_flow_tbl_key tbl_key;
10901         uint32_t modify_action_position = UINT32_MAX;
10902         void *match_mask = matcher.mask.buf;
10903         void *match_value = dev_flow->dv.value.buf;
10904         uint8_t next_protocol = 0xff;
10905         struct rte_vlan_hdr vlan = { 0 };
10906         struct mlx5_flow_dv_dest_array_resource mdest_res;
10907         struct mlx5_flow_dv_sample_resource sample_res;
10908         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10909         const struct rte_flow_action_sample *sample = NULL;
10910         struct mlx5_flow_sub_actions_list *sample_act;
10911         uint32_t sample_act_pos = UINT32_MAX;
10912         uint32_t num_of_dest = 0;
10913         int tmp_actions_n = 0;
10914         uint32_t table;
10915         int ret = 0;
10916         const struct mlx5_flow_tunnel *tunnel;
10917         struct flow_grp_info grp_info = {
10918                 .external = !!dev_flow->external,
10919                 .transfer = !!attr->transfer,
10920                 .fdb_def_rule = !!priv->fdb_def_rule,
10921                 .skip_scale = dev_flow->skip_scale &
10922                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10923         };
10924
10925         if (!wks)
10926                 return rte_flow_error_set(error, ENOMEM,
10927                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10928                                           NULL,
10929                                           "failed to push flow workspace");
10930         rss_desc = &wks->rss_desc;
10931         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10932         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10933         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10934                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10935         /* update normal path action resource into last index of array */
10936         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10937         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10938                  flow_items_to_tunnel(items) :
10939                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10940                  flow_actions_to_tunnel(actions) :
10941                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10942         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10943                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10944         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10945                                 (dev, tunnel, attr, items, actions);
10946         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10947                                        &grp_info, error);
10948         if (ret)
10949                 return ret;
10950         dev_flow->dv.group = table;
10951         if (attr->transfer)
10952                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10953         /* number of actions must be set to 0 in case of dirty stack. */
10954         mhdr_res->actions_num = 0;
10955         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10956                 /*
10957                  * do not add decap action if match rule drops packet
10958                  * HW rejects rules with decap & drop
10959                  *
10960                  * if tunnel match rule was inserted before matching tunnel set
10961                  * rule flow table used in the match rule must be registered.
10962                  * current implementation handles that in the
10963                  * flow_dv_match_register() at the function end.
10964                  */
10965                 bool add_decap = true;
10966                 const struct rte_flow_action *ptr = actions;
10967
10968                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10969                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10970                                 add_decap = false;
10971                                 break;
10972                         }
10973                 }
10974                 if (add_decap) {
10975                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10976                                                            attr->transfer,
10977                                                            error))
10978                                 return -rte_errno;
10979                         dev_flow->dv.actions[actions_n++] =
10980                                         dev_flow->dv.encap_decap->action;
10981                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10982                 }
10983         }
10984         for (; !actions_end ; actions++) {
10985                 const struct rte_flow_action_queue *queue;
10986                 const struct rte_flow_action_rss *rss;
10987                 const struct rte_flow_action *action = actions;
10988                 const uint8_t *rss_key;
10989                 const struct rte_flow_action_meter *mtr;
10990                 struct mlx5_flow_tbl_resource *tbl;
10991                 struct mlx5_aso_age_action *age_act;
10992                 uint32_t port_id = 0;
10993                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10994                 int action_type = actions->type;
10995                 const struct rte_flow_action *found_action = NULL;
10996                 struct mlx5_flow_meter *fm = NULL;
10997                 uint32_t jump_group = 0;
10998
10999                 if (!mlx5_flow_os_action_supported(action_type))
11000                         return rte_flow_error_set(error, ENOTSUP,
11001                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11002                                                   actions,
11003                                                   "action not supported");
11004                 switch (action_type) {
11005                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11006                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11007                         break;
11008                 case RTE_FLOW_ACTION_TYPE_VOID:
11009                         break;
11010                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11011                         if (flow_dv_translate_action_port_id(dev, action,
11012                                                              &port_id, error))
11013                                 return -rte_errno;
11014                         port_id_resource.port_id = port_id;
11015                         MLX5_ASSERT(!handle->rix_port_id_action);
11016                         if (flow_dv_port_id_action_resource_register
11017                             (dev, &port_id_resource, dev_flow, error))
11018                                 return -rte_errno;
11019                         dev_flow->dv.actions[actions_n++] =
11020                                         dev_flow->dv.port_id_action->action;
11021                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11022                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11023                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11024                         num_of_dest++;
11025                         break;
11026                 case RTE_FLOW_ACTION_TYPE_FLAG:
11027                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11028                         dev_flow->handle->mark = 1;
11029                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11030                                 struct rte_flow_action_mark mark = {
11031                                         .id = MLX5_FLOW_MARK_DEFAULT,
11032                                 };
11033
11034                                 if (flow_dv_convert_action_mark(dev, &mark,
11035                                                                 mhdr_res,
11036                                                                 error))
11037                                         return -rte_errno;
11038                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11039                                 break;
11040                         }
11041                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11042                         /*
11043                          * Only one FLAG or MARK is supported per device flow
11044                          * right now. So the pointer to the tag resource must be
11045                          * zero before the register process.
11046                          */
11047                         MLX5_ASSERT(!handle->dvh.rix_tag);
11048                         if (flow_dv_tag_resource_register(dev, tag_be,
11049                                                           dev_flow, error))
11050                                 return -rte_errno;
11051                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11052                         dev_flow->dv.actions[actions_n++] =
11053                                         dev_flow->dv.tag_resource->action;
11054                         break;
11055                 case RTE_FLOW_ACTION_TYPE_MARK:
11056                         action_flags |= MLX5_FLOW_ACTION_MARK;
11057                         dev_flow->handle->mark = 1;
11058                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11059                                 const struct rte_flow_action_mark *mark =
11060                                         (const struct rte_flow_action_mark *)
11061                                                 actions->conf;
11062
11063                                 if (flow_dv_convert_action_mark(dev, mark,
11064                                                                 mhdr_res,
11065                                                                 error))
11066                                         return -rte_errno;
11067                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11068                                 break;
11069                         }
11070                         /* Fall-through */
11071                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11072                         /* Legacy (non-extensive) MARK action. */
11073                         tag_be = mlx5_flow_mark_set
11074                               (((const struct rte_flow_action_mark *)
11075                                (actions->conf))->id);
11076                         MLX5_ASSERT(!handle->dvh.rix_tag);
11077                         if (flow_dv_tag_resource_register(dev, tag_be,
11078                                                           dev_flow, error))
11079                                 return -rte_errno;
11080                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11081                         dev_flow->dv.actions[actions_n++] =
11082                                         dev_flow->dv.tag_resource->action;
11083                         break;
11084                 case RTE_FLOW_ACTION_TYPE_SET_META:
11085                         if (flow_dv_convert_action_set_meta
11086                                 (dev, mhdr_res, attr,
11087                                  (const struct rte_flow_action_set_meta *)
11088                                   actions->conf, error))
11089                                 return -rte_errno;
11090                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11091                         break;
11092                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11093                         if (flow_dv_convert_action_set_tag
11094                                 (dev, mhdr_res,
11095                                  (const struct rte_flow_action_set_tag *)
11096                                   actions->conf, error))
11097                                 return -rte_errno;
11098                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11099                         break;
11100                 case RTE_FLOW_ACTION_TYPE_DROP:
11101                         action_flags |= MLX5_FLOW_ACTION_DROP;
11102                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11103                         break;
11104                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11105                         queue = actions->conf;
11106                         rss_desc->queue_num = 1;
11107                         rss_desc->queue[0] = queue->index;
11108                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11109                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11110                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11111                         num_of_dest++;
11112                         break;
11113                 case RTE_FLOW_ACTION_TYPE_RSS:
11114                         rss = actions->conf;
11115                         memcpy(rss_desc->queue, rss->queue,
11116                                rss->queue_num * sizeof(uint16_t));
11117                         rss_desc->queue_num = rss->queue_num;
11118                         /* NULL RSS key indicates default RSS key. */
11119                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11120                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11121                         /*
11122                          * rss->level and rss.types should be set in advance
11123                          * when expanding items for RSS.
11124                          */
11125                         action_flags |= MLX5_FLOW_ACTION_RSS;
11126                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11127                                 MLX5_FLOW_FATE_SHARED_RSS :
11128                                 MLX5_FLOW_FATE_QUEUE;
11129                         break;
11130                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11131                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11132                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11133                         __atomic_fetch_add(&age_act->refcnt, 1,
11134                                            __ATOMIC_RELAXED);
11135                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11136                         action_flags |= MLX5_FLOW_ACTION_AGE;
11137                         break;
11138                 case RTE_FLOW_ACTION_TYPE_AGE:
11139                         if (priv->sh->flow_hit_aso_en && attr->group) {
11140                                 /*
11141                                  * Create one shared age action, to be used
11142                                  * by all sub-flows.
11143                                  */
11144                                 if (!flow->age) {
11145                                         flow->age =
11146                                                 flow_dv_translate_create_aso_age
11147                                                         (dev, action->conf,
11148                                                          error);
11149                                         if (!flow->age)
11150                                                 return rte_flow_error_set
11151                                                 (error, rte_errno,
11152                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11153                                                  NULL,
11154                                                  "can't create ASO age action");
11155                                 }
11156                                 dev_flow->dv.actions[actions_n++] =
11157                                           (flow_aso_age_get_by_idx
11158                                                 (dev, flow->age))->dr_action;
11159                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11160                                 break;
11161                         }
11162                         /* Fall-through */
11163                 case RTE_FLOW_ACTION_TYPE_COUNT:
11164                         if (!dev_conf->devx) {
11165                                 return rte_flow_error_set
11166                                               (error, ENOTSUP,
11167                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11168                                                NULL,
11169                                                "count action not supported");
11170                         }
11171                         /* Save information first, will apply later. */
11172                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11173                                 count = action->conf;
11174                         else
11175                                 age = action->conf;
11176                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11177                         break;
11178                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11179                         dev_flow->dv.actions[actions_n++] =
11180                                                 priv->sh->pop_vlan_action;
11181                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11182                         break;
11183                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11184                         if (!(action_flags &
11185                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11186                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11187                         vlan.eth_proto = rte_be_to_cpu_16
11188                              ((((const struct rte_flow_action_of_push_vlan *)
11189                                                    actions->conf)->ethertype));
11190                         found_action = mlx5_flow_find_action
11191                                         (actions + 1,
11192                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11193                         if (found_action)
11194                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11195                         found_action = mlx5_flow_find_action
11196                                         (actions + 1,
11197                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11198                         if (found_action)
11199                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11200                         if (flow_dv_create_action_push_vlan
11201                                             (dev, attr, &vlan, dev_flow, error))
11202                                 return -rte_errno;
11203                         dev_flow->dv.actions[actions_n++] =
11204                                         dev_flow->dv.push_vlan_res->action;
11205                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11206                         break;
11207                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11208                         /* of_vlan_push action handled this action */
11209                         MLX5_ASSERT(action_flags &
11210                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11211                         break;
11212                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11213                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11214                                 break;
11215                         flow_dev_get_vlan_info_from_items(items, &vlan);
11216                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11217                         /* If no VLAN push - this is a modify header action */
11218                         if (flow_dv_convert_action_modify_vlan_vid
11219                                                 (mhdr_res, actions, error))
11220                                 return -rte_errno;
11221                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11222                         break;
11223                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11224                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11225                         if (flow_dv_create_action_l2_encap(dev, actions,
11226                                                            dev_flow,
11227                                                            attr->transfer,
11228                                                            error))
11229                                 return -rte_errno;
11230                         dev_flow->dv.actions[actions_n++] =
11231                                         dev_flow->dv.encap_decap->action;
11232                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11233                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11234                                 sample_act->action_flags |=
11235                                                         MLX5_FLOW_ACTION_ENCAP;
11236                         break;
11237                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11238                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11239                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11240                                                            attr->transfer,
11241                                                            error))
11242                                 return -rte_errno;
11243                         dev_flow->dv.actions[actions_n++] =
11244                                         dev_flow->dv.encap_decap->action;
11245                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11246                         break;
11247                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11248                         /* Handle encap with preceding decap. */
11249                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11250                                 if (flow_dv_create_action_raw_encap
11251                                         (dev, actions, dev_flow, attr, error))
11252                                         return -rte_errno;
11253                                 dev_flow->dv.actions[actions_n++] =
11254                                         dev_flow->dv.encap_decap->action;
11255                         } else {
11256                                 /* Handle encap without preceding decap. */
11257                                 if (flow_dv_create_action_l2_encap
11258                                     (dev, actions, dev_flow, attr->transfer,
11259                                      error))
11260                                         return -rte_errno;
11261                                 dev_flow->dv.actions[actions_n++] =
11262                                         dev_flow->dv.encap_decap->action;
11263                         }
11264                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11265                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11266                                 sample_act->action_flags |=
11267                                                         MLX5_FLOW_ACTION_ENCAP;
11268                         break;
11269                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11270                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11271                                 ;
11272                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11273                                 if (flow_dv_create_action_l2_decap
11274                                     (dev, dev_flow, attr->transfer, error))
11275                                         return -rte_errno;
11276                                 dev_flow->dv.actions[actions_n++] =
11277                                         dev_flow->dv.encap_decap->action;
11278                         }
11279                         /* If decap is followed by encap, handle it at encap. */
11280                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11281                         break;
11282                 case RTE_FLOW_ACTION_TYPE_JUMP:
11283                         jump_group = ((const struct rte_flow_action_jump *)
11284                                                         action->conf)->group;
11285                         grp_info.std_tbl_fix = 0;
11286                         if (dev_flow->skip_scale &
11287                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11288                                 grp_info.skip_scale = 1;
11289                         else
11290                                 grp_info.skip_scale = 0;
11291                         ret = mlx5_flow_group_to_table(dev, tunnel,
11292                                                        jump_group,
11293                                                        &table,
11294                                                        &grp_info, error);
11295                         if (ret)
11296                                 return ret;
11297                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11298                                                        attr->transfer,
11299                                                        !!dev_flow->external,
11300                                                        tunnel, jump_group, 0,
11301                                                        error);
11302                         if (!tbl)
11303                                 return rte_flow_error_set
11304                                                 (error, errno,
11305                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11306                                                  NULL,
11307                                                  "cannot create jump action.");
11308                         if (flow_dv_jump_tbl_resource_register
11309                             (dev, tbl, dev_flow, error)) {
11310                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11311                                 return rte_flow_error_set
11312                                                 (error, errno,
11313                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11314                                                  NULL,
11315                                                  "cannot create jump action.");
11316                         }
11317                         dev_flow->dv.actions[actions_n++] =
11318                                         dev_flow->dv.jump->action;
11319                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11320                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11321                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11322                         num_of_dest++;
11323                         break;
11324                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11325                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11326                         if (flow_dv_convert_action_modify_mac
11327                                         (mhdr_res, actions, error))
11328                                 return -rte_errno;
11329                         action_flags |= actions->type ==
11330                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11331                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11332                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11333                         break;
11334                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11335                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11336                         if (flow_dv_convert_action_modify_ipv4
11337                                         (mhdr_res, actions, error))
11338                                 return -rte_errno;
11339                         action_flags |= actions->type ==
11340                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11341                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11342                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11343                         break;
11344                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11345                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11346                         if (flow_dv_convert_action_modify_ipv6
11347                                         (mhdr_res, actions, error))
11348                                 return -rte_errno;
11349                         action_flags |= actions->type ==
11350                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11351                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11352                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11353                         break;
11354                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11355                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11356                         if (flow_dv_convert_action_modify_tp
11357                                         (mhdr_res, actions, items,
11358                                          &flow_attr, dev_flow, !!(action_flags &
11359                                          MLX5_FLOW_ACTION_DECAP), error))
11360                                 return -rte_errno;
11361                         action_flags |= actions->type ==
11362                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11363                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11364                                         MLX5_FLOW_ACTION_SET_TP_DST;
11365                         break;
11366                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11367                         if (flow_dv_convert_action_modify_dec_ttl
11368                                         (mhdr_res, items, &flow_attr, dev_flow,
11369                                          !!(action_flags &
11370                                          MLX5_FLOW_ACTION_DECAP), error))
11371                                 return -rte_errno;
11372                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11373                         break;
11374                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11375                         if (flow_dv_convert_action_modify_ttl
11376                                         (mhdr_res, actions, items, &flow_attr,
11377                                          dev_flow, !!(action_flags &
11378                                          MLX5_FLOW_ACTION_DECAP), error))
11379                                 return -rte_errno;
11380                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11381                         break;
11382                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11383                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11384                         if (flow_dv_convert_action_modify_tcp_seq
11385                                         (mhdr_res, actions, error))
11386                                 return -rte_errno;
11387                         action_flags |= actions->type ==
11388                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11389                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11390                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11391                         break;
11392
11393                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11394                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11395                         if (flow_dv_convert_action_modify_tcp_ack
11396                                         (mhdr_res, actions, error))
11397                                 return -rte_errno;
11398                         action_flags |= actions->type ==
11399                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11400                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11401                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11402                         break;
11403                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11404                         if (flow_dv_convert_action_set_reg
11405                                         (mhdr_res, actions, error))
11406                                 return -rte_errno;
11407                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11408                         break;
11409                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11410                         if (flow_dv_convert_action_copy_mreg
11411                                         (dev, mhdr_res, actions, error))
11412                                 return -rte_errno;
11413                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11414                         break;
11415                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11416                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11417                         dev_flow->handle->fate_action =
11418                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11419                         break;
11420                 case RTE_FLOW_ACTION_TYPE_METER:
11421                         mtr = actions->conf;
11422                         if (!flow->meter) {
11423                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11424                                                             attr, error);
11425                                 if (!fm)
11426                                         return rte_flow_error_set(error,
11427                                                 rte_errno,
11428                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11429                                                 NULL,
11430                                                 "meter not found "
11431                                                 "or invalid parameters");
11432                                 flow->meter = fm->idx;
11433                         }
11434                         /* Set the meter action. */
11435                         if (!fm) {
11436                                 fm = mlx5_ipool_get(priv->sh->ipool
11437                                                 [MLX5_IPOOL_MTR], flow->meter);
11438                                 if (!fm)
11439                                         return rte_flow_error_set(error,
11440                                                 rte_errno,
11441                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11442                                                 NULL,
11443                                                 "meter not found "
11444                                                 "or invalid parameters");
11445                         }
11446                         dev_flow->dv.actions[actions_n++] =
11447                                 fm->mfts->meter_action;
11448                         action_flags |= MLX5_FLOW_ACTION_METER;
11449                         break;
11450                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11451                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11452                                                               actions, error))
11453                                 return -rte_errno;
11454                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11455                         break;
11456                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11457                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11458                                                               actions, error))
11459                                 return -rte_errno;
11460                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11461                         break;
11462                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11463                         sample_act_pos = actions_n;
11464                         sample = (const struct rte_flow_action_sample *)
11465                                  action->conf;
11466                         actions_n++;
11467                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11468                         /* put encap action into group if work with port id */
11469                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11470                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11471                                 sample_act->action_flags |=
11472                                                         MLX5_FLOW_ACTION_ENCAP;
11473                         break;
11474                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11475                         if (flow_dv_convert_action_modify_field
11476                                         (dev, mhdr_res, actions, attr, error))
11477                                 return -rte_errno;
11478                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11479                         break;
11480                 case RTE_FLOW_ACTION_TYPE_END:
11481                         actions_end = true;
11482                         if (mhdr_res->actions_num) {
11483                                 /* create modify action if needed. */
11484                                 if (flow_dv_modify_hdr_resource_register
11485                                         (dev, mhdr_res, dev_flow, error))
11486                                         return -rte_errno;
11487                                 dev_flow->dv.actions[modify_action_position] =
11488                                         handle->dvh.modify_hdr->action;
11489                         }
11490                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11491                                 /*
11492                                  * Create one count action, to be used
11493                                  * by all sub-flows.
11494                                  */
11495                                 if (!flow->counter) {
11496                                         flow->counter =
11497                                                 flow_dv_translate_create_counter
11498                                                         (dev, dev_flow, count,
11499                                                          age);
11500                                         if (!flow->counter)
11501                                                 return rte_flow_error_set
11502                                                 (error, rte_errno,
11503                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11504                                                  NULL, "cannot create counter"
11505                                                  " object.");
11506                                 }
11507                                 dev_flow->dv.actions[actions_n] =
11508                                           (flow_dv_counter_get_by_idx(dev,
11509                                           flow->counter, NULL))->action;
11510                                 actions_n++;
11511                         }
11512                 default:
11513                         break;
11514                 }
11515                 if (mhdr_res->actions_num &&
11516                     modify_action_position == UINT32_MAX)
11517                         modify_action_position = actions_n++;
11518         }
11519         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11520                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11521                 int item_type = items->type;
11522
11523                 if (!mlx5_flow_os_item_supported(item_type))
11524                         return rte_flow_error_set(error, ENOTSUP,
11525                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11526                                                   NULL, "item not supported");
11527                 switch (item_type) {
11528                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11529                         flow_dv_translate_item_port_id
11530                                 (dev, match_mask, match_value, items, attr);
11531                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11532                         break;
11533                 case RTE_FLOW_ITEM_TYPE_ETH:
11534                         flow_dv_translate_item_eth(match_mask, match_value,
11535                                                    items, tunnel,
11536                                                    dev_flow->dv.group);
11537                         matcher.priority = action_flags &
11538                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11539                                         !dev_flow->external ?
11540                                         MLX5_PRIORITY_MAP_L3 :
11541                                         MLX5_PRIORITY_MAP_L2;
11542                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11543                                              MLX5_FLOW_LAYER_OUTER_L2;
11544                         break;
11545                 case RTE_FLOW_ITEM_TYPE_VLAN:
11546                         flow_dv_translate_item_vlan(dev_flow,
11547                                                     match_mask, match_value,
11548                                                     items, tunnel,
11549                                                     dev_flow->dv.group);
11550                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11551                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11552                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11553                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11554                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11555                         break;
11556                 case RTE_FLOW_ITEM_TYPE_IPV4:
11557                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11558                                                   &item_flags, &tunnel);
11559                         flow_dv_translate_item_ipv4(match_mask, match_value,
11560                                                     items, tunnel,
11561                                                     dev_flow->dv.group);
11562                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11563                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11564                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11565                         if (items->mask != NULL &&
11566                             ((const struct rte_flow_item_ipv4 *)
11567                              items->mask)->hdr.next_proto_id) {
11568                                 next_protocol =
11569                                         ((const struct rte_flow_item_ipv4 *)
11570                                          (items->spec))->hdr.next_proto_id;
11571                                 next_protocol &=
11572                                         ((const struct rte_flow_item_ipv4 *)
11573                                          (items->mask))->hdr.next_proto_id;
11574                         } else {
11575                                 /* Reset for inner layer. */
11576                                 next_protocol = 0xff;
11577                         }
11578                         break;
11579                 case RTE_FLOW_ITEM_TYPE_IPV6:
11580                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11581                                                   &item_flags, &tunnel);
11582                         flow_dv_translate_item_ipv6(match_mask, match_value,
11583                                                     items, tunnel,
11584                                                     dev_flow->dv.group);
11585                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11586                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11587                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11588                         if (items->mask != NULL &&
11589                             ((const struct rte_flow_item_ipv6 *)
11590                              items->mask)->hdr.proto) {
11591                                 next_protocol =
11592                                         ((const struct rte_flow_item_ipv6 *)
11593                                          items->spec)->hdr.proto;
11594                                 next_protocol &=
11595                                         ((const struct rte_flow_item_ipv6 *)
11596                                          items->mask)->hdr.proto;
11597                         } else {
11598                                 /* Reset for inner layer. */
11599                                 next_protocol = 0xff;
11600                         }
11601                         break;
11602                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11603                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11604                                                              match_value,
11605                                                              items, tunnel);
11606                         last_item = tunnel ?
11607                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11608                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11609                         if (items->mask != NULL &&
11610                             ((const struct rte_flow_item_ipv6_frag_ext *)
11611                              items->mask)->hdr.next_header) {
11612                                 next_protocol =
11613                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11614                                  items->spec)->hdr.next_header;
11615                                 next_protocol &=
11616                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11617                                  items->mask)->hdr.next_header;
11618                         } else {
11619                                 /* Reset for inner layer. */
11620                                 next_protocol = 0xff;
11621                         }
11622                         break;
11623                 case RTE_FLOW_ITEM_TYPE_TCP:
11624                         flow_dv_translate_item_tcp(match_mask, match_value,
11625                                                    items, tunnel);
11626                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11627                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11628                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11629                         break;
11630                 case RTE_FLOW_ITEM_TYPE_UDP:
11631                         flow_dv_translate_item_udp(match_mask, match_value,
11632                                                    items, tunnel);
11633                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11634                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11635                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11636                         break;
11637                 case RTE_FLOW_ITEM_TYPE_GRE:
11638                         flow_dv_translate_item_gre(match_mask, match_value,
11639                                                    items, tunnel);
11640                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11641                         last_item = MLX5_FLOW_LAYER_GRE;
11642                         break;
11643                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11644                         flow_dv_translate_item_gre_key(match_mask,
11645                                                        match_value, items);
11646                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11647                         break;
11648                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11649                         flow_dv_translate_item_nvgre(match_mask, match_value,
11650                                                      items, tunnel);
11651                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11652                         last_item = MLX5_FLOW_LAYER_GRE;
11653                         break;
11654                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11655                         flow_dv_translate_item_vxlan(match_mask, match_value,
11656                                                      items, tunnel);
11657                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11658                         last_item = MLX5_FLOW_LAYER_VXLAN;
11659                         break;
11660                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11661                         flow_dv_translate_item_vxlan_gpe(match_mask,
11662                                                          match_value, items,
11663                                                          tunnel);
11664                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11665                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11666                         break;
11667                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11668                         flow_dv_translate_item_geneve(match_mask, match_value,
11669                                                       items, tunnel);
11670                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11671                         last_item = MLX5_FLOW_LAYER_GENEVE;
11672                         break;
11673                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11674                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11675                                                           match_value,
11676                                                           items, error);
11677                         if (ret)
11678                                 return rte_flow_error_set(error, -ret,
11679                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11680                                         "cannot create GENEVE TLV option");
11681                         flow->geneve_tlv_option = 1;
11682                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11683                         break;
11684                 case RTE_FLOW_ITEM_TYPE_MPLS:
11685                         flow_dv_translate_item_mpls(match_mask, match_value,
11686                                                     items, last_item, tunnel);
11687                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11688                         last_item = MLX5_FLOW_LAYER_MPLS;
11689                         break;
11690                 case RTE_FLOW_ITEM_TYPE_MARK:
11691                         flow_dv_translate_item_mark(dev, match_mask,
11692                                                     match_value, items);
11693                         last_item = MLX5_FLOW_ITEM_MARK;
11694                         break;
11695                 case RTE_FLOW_ITEM_TYPE_META:
11696                         flow_dv_translate_item_meta(dev, match_mask,
11697                                                     match_value, attr, items);
11698                         last_item = MLX5_FLOW_ITEM_METADATA;
11699                         break;
11700                 case RTE_FLOW_ITEM_TYPE_ICMP:
11701                         flow_dv_translate_item_icmp(match_mask, match_value,
11702                                                     items, tunnel);
11703                         last_item = MLX5_FLOW_LAYER_ICMP;
11704                         break;
11705                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11706                         flow_dv_translate_item_icmp6(match_mask, match_value,
11707                                                       items, tunnel);
11708                         last_item = MLX5_FLOW_LAYER_ICMP6;
11709                         break;
11710                 case RTE_FLOW_ITEM_TYPE_TAG:
11711                         flow_dv_translate_item_tag(dev, match_mask,
11712                                                    match_value, items);
11713                         last_item = MLX5_FLOW_ITEM_TAG;
11714                         break;
11715                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11716                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11717                                                         match_value, items);
11718                         last_item = MLX5_FLOW_ITEM_TAG;
11719                         break;
11720                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11721                         flow_dv_translate_item_tx_queue(dev, match_mask,
11722                                                         match_value,
11723                                                         items);
11724                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11725                         break;
11726                 case RTE_FLOW_ITEM_TYPE_GTP:
11727                         flow_dv_translate_item_gtp(match_mask, match_value,
11728                                                    items, tunnel);
11729                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11730                         last_item = MLX5_FLOW_LAYER_GTP;
11731                         break;
11732                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11733                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11734                                                           match_value,
11735                                                           items);
11736                         if (ret)
11737                                 return rte_flow_error_set(error, -ret,
11738                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11739                                         "cannot create GTP PSC item");
11740                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11741                         break;
11742                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11743                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11744                                 /* Create it only the first time to be used. */
11745                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11746                                 if (ret)
11747                                         return rte_flow_error_set
11748                                                 (error, -ret,
11749                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11750                                                 NULL,
11751                                                 "cannot create eCPRI parser");
11752                         }
11753                         /* Adjust the length matcher and device flow value. */
11754                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11755                         dev_flow->dv.value.size =
11756                                         MLX5_ST_SZ_BYTES(fte_match_param);
11757                         flow_dv_translate_item_ecpri(dev, match_mask,
11758                                                      match_value, items);
11759                         /* No other protocol should follow eCPRI layer. */
11760                         last_item = MLX5_FLOW_LAYER_ECPRI;
11761                         break;
11762                 default:
11763                         break;
11764                 }
11765                 item_flags |= last_item;
11766         }
11767         /*
11768          * When E-Switch mode is enabled, we have two cases where we need to
11769          * set the source port manually.
11770          * The first one, is in case of Nic steering rule, and the second is
11771          * E-Switch rule where no port_id item was found. In both cases
11772          * the source port is set according the current port in use.
11773          */
11774         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11775             (priv->representor || priv->master)) {
11776                 if (flow_dv_translate_item_port_id(dev, match_mask,
11777                                                    match_value, NULL, attr))
11778                         return -rte_errno;
11779         }
11780 #ifdef RTE_LIBRTE_MLX5_DEBUG
11781         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11782                                               dev_flow->dv.value.buf));
11783 #endif
11784         /*
11785          * Layers may be already initialized from prefix flow if this dev_flow
11786          * is the suffix flow.
11787          */
11788         handle->layers |= item_flags;
11789         if (action_flags & MLX5_FLOW_ACTION_RSS)
11790                 flow_dv_hashfields_set(dev_flow, rss_desc);
11791         /* If has RSS action in the sample action, the Sample/Mirror resource
11792          * should be registered after the hash filed be update.
11793          */
11794         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11795                 ret = flow_dv_translate_action_sample(dev,
11796                                                       sample,
11797                                                       dev_flow, attr,
11798                                                       &num_of_dest,
11799                                                       sample_actions,
11800                                                       &sample_res,
11801                                                       error);
11802                 if (ret < 0)
11803                         return ret;
11804                 ret = flow_dv_create_action_sample(dev,
11805                                                    dev_flow,
11806                                                    num_of_dest,
11807                                                    &sample_res,
11808                                                    &mdest_res,
11809                                                    sample_actions,
11810                                                    action_flags,
11811                                                    error);
11812                 if (ret < 0)
11813                         return rte_flow_error_set
11814                                                 (error, rte_errno,
11815                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11816                                                 NULL,
11817                                                 "cannot create sample action");
11818                 if (num_of_dest > 1) {
11819                         dev_flow->dv.actions[sample_act_pos] =
11820                         dev_flow->dv.dest_array_res->action;
11821                 } else {
11822                         dev_flow->dv.actions[sample_act_pos] =
11823                         dev_flow->dv.sample_res->verbs_action;
11824                 }
11825         }
11826         /*
11827          * For multiple destination (sample action with ratio=1), the encap
11828          * action and port id action will be combined into group action.
11829          * So need remove the original these actions in the flow and only
11830          * use the sample action instead of.
11831          */
11832         if (num_of_dest > 1 &&
11833             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11834                 int i;
11835                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11836
11837                 for (i = 0; i < actions_n; i++) {
11838                         if ((sample_act->dr_encap_action &&
11839                                 sample_act->dr_encap_action ==
11840                                 dev_flow->dv.actions[i]) ||
11841                                 (sample_act->dr_port_id_action &&
11842                                 sample_act->dr_port_id_action ==
11843                                 dev_flow->dv.actions[i]) ||
11844                                 (sample_act->dr_jump_action &&
11845                                 sample_act->dr_jump_action ==
11846                                 dev_flow->dv.actions[i]))
11847                                 continue;
11848                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11849                 }
11850                 memcpy((void *)dev_flow->dv.actions,
11851                                 (void *)temp_actions,
11852                                 tmp_actions_n * sizeof(void *));
11853                 actions_n = tmp_actions_n;
11854         }
11855         dev_flow->dv.actions_n = actions_n;
11856         dev_flow->act_flags = action_flags;
11857         /* Register matcher. */
11858         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11859                                     matcher.mask.size);
11860         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11861                                         matcher.priority);
11862         /* reserved field no needs to be set to 0 here. */
11863         tbl_key.domain = attr->transfer;
11864         tbl_key.direction = attr->egress;
11865         tbl_key.table_id = dev_flow->dv.group;
11866         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11867                                      tunnel, attr->group, error))
11868                 return -rte_errno;
11869         return 0;
11870 }
11871
11872 /**
11873  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11874  * and tunnel.
11875  *
11876  * @param[in, out] action
11877  *   Shred RSS action holding hash RX queue objects.
11878  * @param[in] hash_fields
11879  *   Defines combination of packet fields to participate in RX hash.
11880  * @param[in] tunnel
11881  *   Tunnel type
11882  * @param[in] hrxq_idx
11883  *   Hash RX queue index to set.
11884  *
11885  * @return
11886  *   0 on success, otherwise negative errno value.
11887  */
11888 static int
11889 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11890                               const uint64_t hash_fields,
11891                               uint32_t hrxq_idx)
11892 {
11893         uint32_t *hrxqs = action->hrxq;
11894
11895         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11896         case MLX5_RSS_HASH_IPV4:
11897                 /* fall-through. */
11898         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11899                 /* fall-through. */
11900         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11901                 hrxqs[0] = hrxq_idx;
11902                 return 0;
11903         case MLX5_RSS_HASH_IPV4_TCP:
11904                 /* fall-through. */
11905         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11906                 /* fall-through. */
11907         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11908                 hrxqs[1] = hrxq_idx;
11909                 return 0;
11910         case MLX5_RSS_HASH_IPV4_UDP:
11911                 /* fall-through. */
11912         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11913                 /* fall-through. */
11914         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11915                 hrxqs[2] = hrxq_idx;
11916                 return 0;
11917         case MLX5_RSS_HASH_IPV6:
11918                 /* fall-through. */
11919         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11920                 /* fall-through. */
11921         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11922                 hrxqs[3] = hrxq_idx;
11923                 return 0;
11924         case MLX5_RSS_HASH_IPV6_TCP:
11925                 /* fall-through. */
11926         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11927                 /* fall-through. */
11928         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11929                 hrxqs[4] = hrxq_idx;
11930                 return 0;
11931         case MLX5_RSS_HASH_IPV6_UDP:
11932                 /* fall-through. */
11933         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11934                 /* fall-through. */
11935         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11936                 hrxqs[5] = hrxq_idx;
11937                 return 0;
11938         case MLX5_RSS_HASH_NONE:
11939                 hrxqs[6] = hrxq_idx;
11940                 return 0;
11941         default:
11942                 return -1;
11943         }
11944 }
11945
11946 /**
11947  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11948  * and tunnel.
11949  *
11950  * @param[in] dev
11951  *   Pointer to the Ethernet device structure.
11952  * @param[in] idx
11953  *   Shared RSS action ID holding hash RX queue objects.
11954  * @param[in] hash_fields
11955  *   Defines combination of packet fields to participate in RX hash.
11956  * @param[in] tunnel
11957  *   Tunnel type
11958  *
11959  * @return
11960  *   Valid hash RX queue index, otherwise 0.
11961  */
11962 static uint32_t
11963 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11964                                  const uint64_t hash_fields)
11965 {
11966         struct mlx5_priv *priv = dev->data->dev_private;
11967         struct mlx5_shared_action_rss *shared_rss =
11968             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11969         const uint32_t *hrxqs = shared_rss->hrxq;
11970
11971         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11972         case MLX5_RSS_HASH_IPV4:
11973                 /* fall-through. */
11974         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11975                 /* fall-through. */
11976         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11977                 return hrxqs[0];
11978         case MLX5_RSS_HASH_IPV4_TCP:
11979                 /* fall-through. */
11980         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11981                 /* fall-through. */
11982         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11983                 return hrxqs[1];
11984         case MLX5_RSS_HASH_IPV4_UDP:
11985                 /* fall-through. */
11986         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11987                 /* fall-through. */
11988         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11989                 return hrxqs[2];
11990         case MLX5_RSS_HASH_IPV6:
11991                 /* fall-through. */
11992         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11993                 /* fall-through. */
11994         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11995                 return hrxqs[3];
11996         case MLX5_RSS_HASH_IPV6_TCP:
11997                 /* fall-through. */
11998         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11999                 /* fall-through. */
12000         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12001                 return hrxqs[4];
12002         case MLX5_RSS_HASH_IPV6_UDP:
12003                 /* fall-through. */
12004         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12005                 /* fall-through. */
12006         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12007                 return hrxqs[5];
12008         case MLX5_RSS_HASH_NONE:
12009                 return hrxqs[6];
12010         default:
12011                 return 0;
12012         }
12013
12014 }
12015
12016 /**
12017  * Apply the flow to the NIC, lock free,
12018  * (mutex should be acquired by caller).
12019  *
12020  * @param[in] dev
12021  *   Pointer to the Ethernet device structure.
12022  * @param[in, out] flow
12023  *   Pointer to flow structure.
12024  * @param[out] error
12025  *   Pointer to error structure.
12026  *
12027  * @return
12028  *   0 on success, a negative errno value otherwise and rte_errno is set.
12029  */
12030 static int
12031 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12032               struct rte_flow_error *error)
12033 {
12034         struct mlx5_flow_dv_workspace *dv;
12035         struct mlx5_flow_handle *dh;
12036         struct mlx5_flow_handle_dv *dv_h;
12037         struct mlx5_flow *dev_flow;
12038         struct mlx5_priv *priv = dev->data->dev_private;
12039         uint32_t handle_idx;
12040         int n;
12041         int err;
12042         int idx;
12043         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12044         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12045
12046         MLX5_ASSERT(wks);
12047         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12048                 dev_flow = &wks->flows[idx];
12049                 dv = &dev_flow->dv;
12050                 dh = dev_flow->handle;
12051                 dv_h = &dh->dvh;
12052                 n = dv->actions_n;
12053                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12054                         if (dv->transfer) {
12055                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12056                                 dv->actions[n++] = priv->sh->dr_drop_action;
12057                         } else {
12058 #ifdef HAVE_MLX5DV_DR
12059                                 /* DR supports drop action placeholder. */
12060                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12061                                 dv->actions[n++] = priv->sh->dr_drop_action;
12062 #else
12063                                 /* For DV we use the explicit drop queue. */
12064                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12065                                 dv->actions[n++] =
12066                                                 priv->drop_queue.hrxq->action;
12067 #endif
12068                         }
12069                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12070                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12071                         struct mlx5_hrxq *hrxq;
12072                         uint32_t hrxq_idx;
12073
12074                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12075                                                     &hrxq_idx);
12076                         if (!hrxq) {
12077                                 rte_flow_error_set
12078                                         (error, rte_errno,
12079                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12080                                          "cannot get hash queue");
12081                                 goto error;
12082                         }
12083                         dh->rix_hrxq = hrxq_idx;
12084                         dv->actions[n++] = hrxq->action;
12085                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12086                         struct mlx5_hrxq *hrxq = NULL;
12087                         uint32_t hrxq_idx;
12088
12089                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12090                                                 rss_desc->shared_rss,
12091                                                 dev_flow->hash_fields);
12092                         if (hrxq_idx)
12093                                 hrxq = mlx5_ipool_get
12094                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12095                                          hrxq_idx);
12096                         if (!hrxq) {
12097                                 rte_flow_error_set
12098                                         (error, rte_errno,
12099                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12100                                          "cannot get hash queue");
12101                                 goto error;
12102                         }
12103                         dh->rix_srss = rss_desc->shared_rss;
12104                         dv->actions[n++] = hrxq->action;
12105                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12106                         if (!priv->sh->default_miss_action) {
12107                                 rte_flow_error_set
12108                                         (error, rte_errno,
12109                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12110                                          "default miss action not be created.");
12111                                 goto error;
12112                         }
12113                         dv->actions[n++] = priv->sh->default_miss_action;
12114                 }
12115                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12116                                                (void *)&dv->value, n,
12117                                                dv->actions, &dh->drv_flow);
12118                 if (err) {
12119                         rte_flow_error_set(error, errno,
12120                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12121                                            NULL,
12122                                            "hardware refuses to create flow");
12123                         goto error;
12124                 }
12125                 if (priv->vmwa_context &&
12126                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12127                         /*
12128                          * The rule contains the VLAN pattern.
12129                          * For VF we are going to create VLAN
12130                          * interface to make hypervisor set correct
12131                          * e-Switch vport context.
12132                          */
12133                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12134                 }
12135         }
12136         return 0;
12137 error:
12138         err = rte_errno; /* Save rte_errno before cleanup. */
12139         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12140                        handle_idx, dh, next) {
12141                 /* hrxq is union, don't clear it if the flag is not set. */
12142                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12143                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12144                         dh->rix_hrxq = 0;
12145                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12146                         dh->rix_srss = 0;
12147                 }
12148                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12149                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12150         }
12151         rte_errno = err; /* Restore rte_errno. */
12152         return -rte_errno;
12153 }
12154
12155 void
12156 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12157                           struct mlx5_cache_entry *entry)
12158 {
12159         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12160                                                           entry);
12161
12162         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12163         mlx5_free(cache);
12164 }
12165
12166 /**
12167  * Release the flow matcher.
12168  *
12169  * @param dev
12170  *   Pointer to Ethernet device.
12171  * @param port_id
12172  *   Index to port ID action resource.
12173  *
12174  * @return
12175  *   1 while a reference on it exists, 0 when freed.
12176  */
12177 static int
12178 flow_dv_matcher_release(struct rte_eth_dev *dev,
12179                         struct mlx5_flow_handle *handle)
12180 {
12181         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12182         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12183                                                             typeof(*tbl), tbl);
12184         int ret;
12185
12186         MLX5_ASSERT(matcher->matcher_object);
12187         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12188         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12189         return ret;
12190 }
12191
12192 /**
12193  * Release encap_decap resource.
12194  *
12195  * @param list
12196  *   Pointer to the hash list.
12197  * @param entry
12198  *   Pointer to exist resource entry object.
12199  */
12200 void
12201 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12202                               struct mlx5_hlist_entry *entry)
12203 {
12204         struct mlx5_dev_ctx_shared *sh = list->ctx;
12205         struct mlx5_flow_dv_encap_decap_resource *res =
12206                 container_of(entry, typeof(*res), entry);
12207
12208         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12209         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12210 }
12211
12212 /**
12213  * Release an encap/decap resource.
12214  *
12215  * @param dev
12216  *   Pointer to Ethernet device.
12217  * @param encap_decap_idx
12218  *   Index of encap decap resource.
12219  *
12220  * @return
12221  *   1 while a reference on it exists, 0 when freed.
12222  */
12223 static int
12224 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12225                                      uint32_t encap_decap_idx)
12226 {
12227         struct mlx5_priv *priv = dev->data->dev_private;
12228         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12229
12230         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12231                                         encap_decap_idx);
12232         if (!cache_resource)
12233                 return 0;
12234         MLX5_ASSERT(cache_resource->action);
12235         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12236                                      &cache_resource->entry);
12237 }
12238
12239 /**
12240  * Release an jump to table action resource.
12241  *
12242  * @param dev
12243  *   Pointer to Ethernet device.
12244  * @param rix_jump
12245  *   Index to the jump action resource.
12246  *
12247  * @return
12248  *   1 while a reference on it exists, 0 when freed.
12249  */
12250 static int
12251 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12252                                   uint32_t rix_jump)
12253 {
12254         struct mlx5_priv *priv = dev->data->dev_private;
12255         struct mlx5_flow_tbl_data_entry *tbl_data;
12256
12257         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12258                                   rix_jump);
12259         if (!tbl_data)
12260                 return 0;
12261         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12262 }
12263
12264 void
12265 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12266                          struct mlx5_hlist_entry *entry)
12267 {
12268         struct mlx5_flow_dv_modify_hdr_resource *res =
12269                 container_of(entry, typeof(*res), entry);
12270
12271         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12272         mlx5_free(entry);
12273 }
12274
12275 /**
12276  * Release a modify-header resource.
12277  *
12278  * @param dev
12279  *   Pointer to Ethernet device.
12280  * @param handle
12281  *   Pointer to mlx5_flow_handle.
12282  *
12283  * @return
12284  *   1 while a reference on it exists, 0 when freed.
12285  */
12286 static int
12287 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12288                                     struct mlx5_flow_handle *handle)
12289 {
12290         struct mlx5_priv *priv = dev->data->dev_private;
12291         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12292
12293         MLX5_ASSERT(entry->action);
12294         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12295 }
12296
12297 void
12298 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12299                           struct mlx5_cache_entry *entry)
12300 {
12301         struct mlx5_dev_ctx_shared *sh = list->ctx;
12302         struct mlx5_flow_dv_port_id_action_resource *cache =
12303                         container_of(entry, typeof(*cache), entry);
12304
12305         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12306         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12307 }
12308
12309 /**
12310  * Release port ID action resource.
12311  *
12312  * @param dev
12313  *   Pointer to Ethernet device.
12314  * @param handle
12315  *   Pointer to mlx5_flow_handle.
12316  *
12317  * @return
12318  *   1 while a reference on it exists, 0 when freed.
12319  */
12320 static int
12321 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12322                                         uint32_t port_id)
12323 {
12324         struct mlx5_priv *priv = dev->data->dev_private;
12325         struct mlx5_flow_dv_port_id_action_resource *cache;
12326
12327         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12328         if (!cache)
12329                 return 0;
12330         MLX5_ASSERT(cache->action);
12331         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12332                                      &cache->entry);
12333 }
12334
12335 /**
12336  * Release shared RSS action resource.
12337  *
12338  * @param dev
12339  *   Pointer to Ethernet device.
12340  * @param srss
12341  *   Shared RSS action index.
12342  */
12343 static void
12344 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12345 {
12346         struct mlx5_priv *priv = dev->data->dev_private;
12347         struct mlx5_shared_action_rss *shared_rss;
12348
12349         shared_rss = mlx5_ipool_get
12350                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12351         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12352 }
12353
12354 void
12355 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12356                             struct mlx5_cache_entry *entry)
12357 {
12358         struct mlx5_dev_ctx_shared *sh = list->ctx;
12359         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12360                         container_of(entry, typeof(*cache), entry);
12361
12362         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12363         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12364 }
12365
12366 /**
12367  * Release push vlan action resource.
12368  *
12369  * @param dev
12370  *   Pointer to Ethernet device.
12371  * @param handle
12372  *   Pointer to mlx5_flow_handle.
12373  *
12374  * @return
12375  *   1 while a reference on it exists, 0 when freed.
12376  */
12377 static int
12378 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12379                                           struct mlx5_flow_handle *handle)
12380 {
12381         struct mlx5_priv *priv = dev->data->dev_private;
12382         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12383         uint32_t idx = handle->dvh.rix_push_vlan;
12384
12385         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12386         if (!cache)
12387                 return 0;
12388         MLX5_ASSERT(cache->action);
12389         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12390                                      &cache->entry);
12391 }
12392
12393 /**
12394  * Release the fate resource.
12395  *
12396  * @param dev
12397  *   Pointer to Ethernet device.
12398  * @param handle
12399  *   Pointer to mlx5_flow_handle.
12400  */
12401 static void
12402 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12403                                struct mlx5_flow_handle *handle)
12404 {
12405         if (!handle->rix_fate)
12406                 return;
12407         switch (handle->fate_action) {
12408         case MLX5_FLOW_FATE_QUEUE:
12409                 mlx5_hrxq_release(dev, handle->rix_hrxq);
12410                 break;
12411         case MLX5_FLOW_FATE_JUMP:
12412                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12413                 break;
12414         case MLX5_FLOW_FATE_PORT_ID:
12415                 flow_dv_port_id_action_resource_release(dev,
12416                                 handle->rix_port_id_action);
12417                 break;
12418         default:
12419                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12420                 break;
12421         }
12422         handle->rix_fate = 0;
12423 }
12424
12425 void
12426 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12427                          struct mlx5_cache_entry *entry)
12428 {
12429         struct mlx5_flow_dv_sample_resource *cache_resource =
12430                         container_of(entry, typeof(*cache_resource), entry);
12431         struct rte_eth_dev *dev = cache_resource->dev;
12432         struct mlx5_priv *priv = dev->data->dev_private;
12433
12434         if (cache_resource->verbs_action)
12435                 claim_zero(mlx5_flow_os_destroy_flow_action
12436                                 (cache_resource->verbs_action));
12437         if (cache_resource->normal_path_tbl)
12438                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12439                         cache_resource->normal_path_tbl);
12440         flow_dv_sample_sub_actions_release(dev,
12441                                 &cache_resource->sample_idx);
12442         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12443                         cache_resource->idx);
12444         DRV_LOG(DEBUG, "sample resource %p: removed",
12445                 (void *)cache_resource);
12446 }
12447
12448 /**
12449  * Release an sample resource.
12450  *
12451  * @param dev
12452  *   Pointer to Ethernet device.
12453  * @param handle
12454  *   Pointer to mlx5_flow_handle.
12455  *
12456  * @return
12457  *   1 while a reference on it exists, 0 when freed.
12458  */
12459 static int
12460 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12461                                      struct mlx5_flow_handle *handle)
12462 {
12463         struct mlx5_priv *priv = dev->data->dev_private;
12464         struct mlx5_flow_dv_sample_resource *cache_resource;
12465
12466         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12467                          handle->dvh.rix_sample);
12468         if (!cache_resource)
12469                 return 0;
12470         MLX5_ASSERT(cache_resource->verbs_action);
12471         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12472                                      &cache_resource->entry);
12473 }
12474
12475 void
12476 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12477                              struct mlx5_cache_entry *entry)
12478 {
12479         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12480                         container_of(entry, typeof(*cache_resource), entry);
12481         struct rte_eth_dev *dev = cache_resource->dev;
12482         struct mlx5_priv *priv = dev->data->dev_private;
12483         uint32_t i = 0;
12484
12485         MLX5_ASSERT(cache_resource->action);
12486         if (cache_resource->action)
12487                 claim_zero(mlx5_flow_os_destroy_flow_action
12488                                         (cache_resource->action));
12489         for (; i < cache_resource->num_of_dest; i++)
12490                 flow_dv_sample_sub_actions_release(dev,
12491                                 &cache_resource->sample_idx[i]);
12492         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12493                         cache_resource->idx);
12494         DRV_LOG(DEBUG, "destination array resource %p: removed",
12495                 (void *)cache_resource);
12496 }
12497
12498 /**
12499  * Release an destination array resource.
12500  *
12501  * @param dev
12502  *   Pointer to Ethernet device.
12503  * @param handle
12504  *   Pointer to mlx5_flow_handle.
12505  *
12506  * @return
12507  *   1 while a reference on it exists, 0 when freed.
12508  */
12509 static int
12510 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12511                                     struct mlx5_flow_handle *handle)
12512 {
12513         struct mlx5_priv *priv = dev->data->dev_private;
12514         struct mlx5_flow_dv_dest_array_resource *cache;
12515
12516         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12517                                handle->dvh.rix_dest_array);
12518         if (!cache)
12519                 return 0;
12520         MLX5_ASSERT(cache->action);
12521         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12522                                      &cache->entry);
12523 }
12524
12525 static void
12526 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12527 {
12528         struct mlx5_priv *priv = dev->data->dev_private;
12529         struct mlx5_dev_ctx_shared *sh = priv->sh;
12530         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12531                                 sh->geneve_tlv_option_resource;
12532         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12533         if (geneve_opt_resource) {
12534                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12535                                          __ATOMIC_RELAXED))) {
12536                         claim_zero(mlx5_devx_cmd_destroy
12537                                         (geneve_opt_resource->obj));
12538                         mlx5_free(sh->geneve_tlv_option_resource);
12539                         sh->geneve_tlv_option_resource = NULL;
12540                 }
12541         }
12542         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12543 }
12544
12545 /**
12546  * Remove the flow from the NIC but keeps it in memory.
12547  * Lock free, (mutex should be acquired by caller).
12548  *
12549  * @param[in] dev
12550  *   Pointer to Ethernet device.
12551  * @param[in, out] flow
12552  *   Pointer to flow structure.
12553  */
12554 static void
12555 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12556 {
12557         struct mlx5_flow_handle *dh;
12558         uint32_t handle_idx;
12559         struct mlx5_priv *priv = dev->data->dev_private;
12560
12561         if (!flow)
12562                 return;
12563         handle_idx = flow->dev_handles;
12564         while (handle_idx) {
12565                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12566                                     handle_idx);
12567                 if (!dh)
12568                         return;
12569                 if (dh->drv_flow) {
12570                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12571                         dh->drv_flow = NULL;
12572                 }
12573                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12574                         flow_dv_fate_resource_release(dev, dh);
12575                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12576                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12577                 handle_idx = dh->next.next;
12578         }
12579 }
12580
12581 /**
12582  * Remove the flow from the NIC and the memory.
12583  * Lock free, (mutex should be acquired by caller).
12584  *
12585  * @param[in] dev
12586  *   Pointer to the Ethernet device structure.
12587  * @param[in, out] flow
12588  *   Pointer to flow structure.
12589  */
12590 static void
12591 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12592 {
12593         struct mlx5_flow_handle *dev_handle;
12594         struct mlx5_priv *priv = dev->data->dev_private;
12595         uint32_t srss = 0;
12596
12597         if (!flow)
12598                 return;
12599         flow_dv_remove(dev, flow);
12600         if (flow->counter) {
12601                 flow_dv_counter_free(dev, flow->counter);
12602                 flow->counter = 0;
12603         }
12604         if (flow->meter) {
12605                 struct mlx5_flow_meter *fm;
12606
12607                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12608                                     flow->meter);
12609                 if (fm)
12610                         mlx5_flow_meter_detach(fm);
12611                 flow->meter = 0;
12612         }
12613         if (flow->age)
12614                 flow_dv_aso_age_release(dev, flow->age);
12615         if (flow->geneve_tlv_option) {
12616                 flow_dv_geneve_tlv_option_resource_release(dev);
12617                 flow->geneve_tlv_option = 0;
12618         }
12619         while (flow->dev_handles) {
12620                 uint32_t tmp_idx = flow->dev_handles;
12621
12622                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12623                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12624                 if (!dev_handle)
12625                         return;
12626                 flow->dev_handles = dev_handle->next.next;
12627                 if (dev_handle->dvh.matcher)
12628                         flow_dv_matcher_release(dev, dev_handle);
12629                 if (dev_handle->dvh.rix_sample)
12630                         flow_dv_sample_resource_release(dev, dev_handle);
12631                 if (dev_handle->dvh.rix_dest_array)
12632                         flow_dv_dest_array_resource_release(dev, dev_handle);
12633                 if (dev_handle->dvh.rix_encap_decap)
12634                         flow_dv_encap_decap_resource_release(dev,
12635                                 dev_handle->dvh.rix_encap_decap);
12636                 if (dev_handle->dvh.modify_hdr)
12637                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12638                 if (dev_handle->dvh.rix_push_vlan)
12639                         flow_dv_push_vlan_action_resource_release(dev,
12640                                                                   dev_handle);
12641                 if (dev_handle->dvh.rix_tag)
12642                         flow_dv_tag_release(dev,
12643                                             dev_handle->dvh.rix_tag);
12644                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12645                         flow_dv_fate_resource_release(dev, dev_handle);
12646                 else if (!srss)
12647                         srss = dev_handle->rix_srss;
12648                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12649                            tmp_idx);
12650         }
12651         if (srss)
12652                 flow_dv_shared_rss_action_release(dev, srss);
12653 }
12654
12655 /**
12656  * Release array of hash RX queue objects.
12657  * Helper function.
12658  *
12659  * @param[in] dev
12660  *   Pointer to the Ethernet device structure.
12661  * @param[in, out] hrxqs
12662  *   Array of hash RX queue objects.
12663  *
12664  * @return
12665  *   Total number of references to hash RX queue objects in *hrxqs* array
12666  *   after this operation.
12667  */
12668 static int
12669 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12670                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12671 {
12672         size_t i;
12673         int remaining = 0;
12674
12675         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12676                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12677
12678                 if (!ret)
12679                         (*hrxqs)[i] = 0;
12680                 remaining += ret;
12681         }
12682         return remaining;
12683 }
12684
12685 /**
12686  * Release all hash RX queue objects representing shared RSS action.
12687  *
12688  * @param[in] dev
12689  *   Pointer to the Ethernet device structure.
12690  * @param[in, out] action
12691  *   Shared RSS action to remove hash RX queue objects from.
12692  *
12693  * @return
12694  *   Total number of references to hash RX queue objects stored in *action*
12695  *   after this operation.
12696  *   Expected to be 0 if no external references held.
12697  */
12698 static int
12699 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12700                                  struct mlx5_shared_action_rss *shared_rss)
12701 {
12702         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12703 }
12704
12705 /**
12706  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12707  * user input.
12708  *
12709  * Only one hash value is available for one L3+L4 combination:
12710  * for example:
12711  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12712  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12713  * same slot in mlx5_rss_hash_fields.
12714  *
12715  * @param[in] rss
12716  *   Pointer to the shared action RSS conf.
12717  * @param[in, out] hash_field
12718  *   hash_field variable needed to be adjusted.
12719  *
12720  * @return
12721  *   void
12722  */
12723 static void
12724 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12725                                      uint64_t *hash_field)
12726 {
12727         uint64_t rss_types = rss->origin.types;
12728
12729         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12730         case MLX5_RSS_HASH_IPV4:
12731                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12732                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12733                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12734                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12735                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12736                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12737                         else
12738                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12739                 }
12740                 return;
12741         case MLX5_RSS_HASH_IPV6:
12742                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12743                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12744                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12745                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12746                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12747                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12748                         else
12749                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12750                 }
12751                 return;
12752         case MLX5_RSS_HASH_IPV4_UDP:
12753                 /* fall-through. */
12754         case MLX5_RSS_HASH_IPV6_UDP:
12755                 if (rss_types & ETH_RSS_UDP) {
12756                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12757                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12758                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12759                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12760                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12761                         else
12762                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12763                 }
12764                 return;
12765         case MLX5_RSS_HASH_IPV4_TCP:
12766                 /* fall-through. */
12767         case MLX5_RSS_HASH_IPV6_TCP:
12768                 if (rss_types & ETH_RSS_TCP) {
12769                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12770                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12771                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12772                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12773                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12774                         else
12775                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12776                 }
12777                 return;
12778         default:
12779                 return;
12780         }
12781 }
12782
12783 /**
12784  * Setup shared RSS action.
12785  * Prepare set of hash RX queue objects sufficient to handle all valid
12786  * hash_fields combinations (see enum ibv_rx_hash_fields).
12787  *
12788  * @param[in] dev
12789  *   Pointer to the Ethernet device structure.
12790  * @param[in] action_idx
12791  *   Shared RSS action ipool index.
12792  * @param[in, out] action
12793  *   Partially initialized shared RSS action.
12794  * @param[out] error
12795  *   Perform verbose error reporting if not NULL. Initialized in case of
12796  *   error only.
12797  *
12798  * @return
12799  *   0 on success, otherwise negative errno value.
12800  */
12801 static int
12802 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12803                            uint32_t action_idx,
12804                            struct mlx5_shared_action_rss *shared_rss,
12805                            struct rte_flow_error *error)
12806 {
12807         struct mlx5_flow_rss_desc rss_desc = { 0 };
12808         size_t i;
12809         int err;
12810
12811         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12812                 return rte_flow_error_set(error, rte_errno,
12813                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12814                                           "cannot setup indirection table");
12815         }
12816         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12817         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12818         rss_desc.const_q = shared_rss->origin.queue;
12819         rss_desc.queue_num = shared_rss->origin.queue_num;
12820         /* Set non-zero value to indicate a shared RSS. */
12821         rss_desc.shared_rss = action_idx;
12822         rss_desc.ind_tbl = shared_rss->ind_tbl;
12823         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12824                 uint32_t hrxq_idx;
12825                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12826                 int tunnel = 0;
12827
12828                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12829                 if (shared_rss->origin.level > 1) {
12830                         hash_fields |= IBV_RX_HASH_INNER;
12831                         tunnel = 1;
12832                 }
12833                 rss_desc.tunnel = tunnel;
12834                 rss_desc.hash_fields = hash_fields;
12835                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12836                 if (!hrxq_idx) {
12837                         rte_flow_error_set
12838                                 (error, rte_errno,
12839                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12840                                  "cannot get hash queue");
12841                         goto error_hrxq_new;
12842                 }
12843                 err = __flow_dv_action_rss_hrxq_set
12844                         (shared_rss, hash_fields, hrxq_idx);
12845                 MLX5_ASSERT(!err);
12846         }
12847         return 0;
12848 error_hrxq_new:
12849         err = rte_errno;
12850         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12851         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12852                 shared_rss->ind_tbl = NULL;
12853         rte_errno = err;
12854         return -rte_errno;
12855 }
12856
12857 /**
12858  * Create shared RSS action.
12859  *
12860  * @param[in] dev
12861  *   Pointer to the Ethernet device structure.
12862  * @param[in] conf
12863  *   Shared action configuration.
12864  * @param[in] rss
12865  *   RSS action specification used to create shared action.
12866  * @param[out] error
12867  *   Perform verbose error reporting if not NULL. Initialized in case of
12868  *   error only.
12869  *
12870  * @return
12871  *   A valid shared action ID in case of success, 0 otherwise and
12872  *   rte_errno is set.
12873  */
12874 static uint32_t
12875 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12876                             const struct rte_flow_shared_action_conf *conf,
12877                             const struct rte_flow_action_rss *rss,
12878                             struct rte_flow_error *error)
12879 {
12880         struct mlx5_priv *priv = dev->data->dev_private;
12881         struct mlx5_shared_action_rss *shared_rss = NULL;
12882         void *queue = NULL;
12883         struct rte_flow_action_rss *origin;
12884         const uint8_t *rss_key;
12885         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12886         uint32_t idx;
12887
12888         RTE_SET_USED(conf);
12889         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12890                             0, SOCKET_ID_ANY);
12891         shared_rss = mlx5_ipool_zmalloc
12892                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12893         if (!shared_rss || !queue) {
12894                 rte_flow_error_set(error, ENOMEM,
12895                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12896                                    "cannot allocate resource memory");
12897                 goto error_rss_init;
12898         }
12899         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12900                 rte_flow_error_set(error, E2BIG,
12901                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12902                                    "rss action number out of range");
12903                 goto error_rss_init;
12904         }
12905         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12906                                           sizeof(*shared_rss->ind_tbl),
12907                                           0, SOCKET_ID_ANY);
12908         if (!shared_rss->ind_tbl) {
12909                 rte_flow_error_set(error, ENOMEM,
12910                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12911                                    "cannot allocate resource memory");
12912                 goto error_rss_init;
12913         }
12914         memcpy(queue, rss->queue, queue_size);
12915         shared_rss->ind_tbl->queues = queue;
12916         shared_rss->ind_tbl->queues_n = rss->queue_num;
12917         origin = &shared_rss->origin;
12918         origin->func = rss->func;
12919         origin->level = rss->level;
12920         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12921         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12922         /* NULL RSS key indicates default RSS key. */
12923         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12924         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12925         origin->key = &shared_rss->key[0];
12926         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12927         origin->queue = queue;
12928         origin->queue_num = rss->queue_num;
12929         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12930                 goto error_rss_init;
12931         rte_spinlock_init(&shared_rss->action_rss_sl);
12932         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12933         rte_spinlock_lock(&priv->shared_act_sl);
12934         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12935                      &priv->rss_shared_actions, idx, shared_rss, next);
12936         rte_spinlock_unlock(&priv->shared_act_sl);
12937         return idx;
12938 error_rss_init:
12939         if (shared_rss) {
12940                 if (shared_rss->ind_tbl)
12941                         mlx5_free(shared_rss->ind_tbl);
12942                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12943                                 idx);
12944         }
12945         if (queue)
12946                 mlx5_free(queue);
12947         return 0;
12948 }
12949
12950 /**
12951  * Destroy the shared RSS action.
12952  * Release related hash RX queue objects.
12953  *
12954  * @param[in] dev
12955  *   Pointer to the Ethernet device structure.
12956  * @param[in] idx
12957  *   The shared RSS action object ID to be removed.
12958  * @param[out] error
12959  *   Perform verbose error reporting if not NULL. Initialized in case of
12960  *   error only.
12961  *
12962  * @return
12963  *   0 on success, otherwise negative errno value.
12964  */
12965 static int
12966 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12967                              struct rte_flow_error *error)
12968 {
12969         struct mlx5_priv *priv = dev->data->dev_private;
12970         struct mlx5_shared_action_rss *shared_rss =
12971             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12972         uint32_t old_refcnt = 1;
12973         int remaining;
12974         uint16_t *queue = NULL;
12975
12976         if (!shared_rss)
12977                 return rte_flow_error_set(error, EINVAL,
12978                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12979                                           "invalid shared action");
12980         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12981         if (remaining)
12982                 return rte_flow_error_set(error, EBUSY,
12983                                           RTE_FLOW_ERROR_TYPE_ACTION,
12984                                           NULL,
12985                                           "shared rss hrxq has references");
12986         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12987                                          0, 0, __ATOMIC_ACQUIRE,
12988                                          __ATOMIC_RELAXED))
12989                 return rte_flow_error_set(error, EBUSY,
12990                                           RTE_FLOW_ERROR_TYPE_ACTION,
12991                                           NULL,
12992                                           "shared rss has references");
12993         queue = shared_rss->ind_tbl->queues;
12994         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12995         if (remaining)
12996                 return rte_flow_error_set(error, EBUSY,
12997                                           RTE_FLOW_ERROR_TYPE_ACTION,
12998                                           NULL,
12999                                           "shared rss indirection table has"
13000                                           " references");
13001         mlx5_free(queue);
13002         rte_spinlock_lock(&priv->shared_act_sl);
13003         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13004                      &priv->rss_shared_actions, idx, shared_rss, next);
13005         rte_spinlock_unlock(&priv->shared_act_sl);
13006         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13007                         idx);
13008         return 0;
13009 }
13010
13011 /**
13012  * Create shared action, lock free,
13013  * (mutex should be acquired by caller).
13014  * Dispatcher for action type specific call.
13015  *
13016  * @param[in] dev
13017  *   Pointer to the Ethernet device structure.
13018  * @param[in] conf
13019  *   Shared action configuration.
13020  * @param[in] action
13021  *   Action specification used to create shared action.
13022  * @param[out] error
13023  *   Perform verbose error reporting if not NULL. Initialized in case of
13024  *   error only.
13025  *
13026  * @return
13027  *   A valid shared action handle in case of success, NULL otherwise and
13028  *   rte_errno is set.
13029  */
13030 static struct rte_flow_shared_action *
13031 flow_dv_action_create(struct rte_eth_dev *dev,
13032                       const struct rte_flow_shared_action_conf *conf,
13033                       const struct rte_flow_action *action,
13034                       struct rte_flow_error *err)
13035 {
13036         uint32_t idx = 0;
13037         uint32_t ret = 0;
13038
13039         switch (action->type) {
13040         case RTE_FLOW_ACTION_TYPE_RSS:
13041                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13042                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
13043                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13044                 break;
13045         case RTE_FLOW_ACTION_TYPE_AGE:
13046                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13047                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
13048                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13049                 if (ret) {
13050                         struct mlx5_aso_age_action *aso_age =
13051                                               flow_aso_age_get_by_idx(dev, ret);
13052
13053                         if (!aso_age->age_params.context)
13054                                 aso_age->age_params.context =
13055                                                          (void *)(uintptr_t)idx;
13056                 }
13057                 break;
13058         default:
13059                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13060                                    NULL, "action type not supported");
13061                 break;
13062         }
13063         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
13064 }
13065
13066 /**
13067  * Destroy the shared action.
13068  * Release action related resources on the NIC and the memory.
13069  * Lock free, (mutex should be acquired by caller).
13070  * Dispatcher for action type specific call.
13071  *
13072  * @param[in] dev
13073  *   Pointer to the Ethernet device structure.
13074  * @param[in] action
13075  *   The shared action object to be removed.
13076  * @param[out] error
13077  *   Perform verbose error reporting if not NULL. Initialized in case of
13078  *   error only.
13079  *
13080  * @return
13081  *   0 on success, otherwise negative errno value.
13082  */
13083 static int
13084 flow_dv_action_destroy(struct rte_eth_dev *dev,
13085                        struct rte_flow_shared_action *action,
13086                        struct rte_flow_error *error)
13087 {
13088         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13089         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13090         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13091         int ret;
13092
13093         switch (type) {
13094         case MLX5_SHARED_ACTION_TYPE_RSS:
13095                 return __flow_dv_action_rss_release(dev, idx, error);
13096         case MLX5_SHARED_ACTION_TYPE_AGE:
13097                 ret = flow_dv_aso_age_release(dev, idx);
13098                 if (ret)
13099                         /*
13100                          * In this case, the last flow has a reference will
13101                          * actually release the age action.
13102                          */
13103                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
13104                                 " released with references %d.", idx, ret);
13105                 return 0;
13106         default:
13107                 return rte_flow_error_set(error, ENOTSUP,
13108                                           RTE_FLOW_ERROR_TYPE_ACTION,
13109                                           NULL,
13110                                           "action type not supported");
13111         }
13112 }
13113
13114 /**
13115  * Updates in place shared RSS action configuration.
13116  *
13117  * @param[in] dev
13118  *   Pointer to the Ethernet device structure.
13119  * @param[in] idx
13120  *   The shared RSS action object ID to be updated.
13121  * @param[in] action_conf
13122  *   RSS action specification used to modify *shared_rss*.
13123  * @param[out] error
13124  *   Perform verbose error reporting if not NULL. Initialized in case of
13125  *   error only.
13126  *
13127  * @return
13128  *   0 on success, otherwise negative errno value.
13129  * @note: currently only support update of RSS queues.
13130  */
13131 static int
13132 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13133                             const struct rte_flow_action_rss *action_conf,
13134                             struct rte_flow_error *error)
13135 {
13136         struct mlx5_priv *priv = dev->data->dev_private;
13137         struct mlx5_shared_action_rss *shared_rss =
13138             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13139         int ret = 0;
13140         void *queue = NULL;
13141         uint16_t *queue_old = NULL;
13142         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13143
13144         if (!shared_rss)
13145                 return rte_flow_error_set(error, EINVAL,
13146                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13147                                           "invalid shared action to update");
13148         if (priv->obj_ops.ind_table_modify == NULL)
13149                 return rte_flow_error_set(error, ENOTSUP,
13150                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13151                                           "cannot modify indirection table");
13152         queue = mlx5_malloc(MLX5_MEM_ZERO,
13153                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13154                             0, SOCKET_ID_ANY);
13155         if (!queue)
13156                 return rte_flow_error_set(error, ENOMEM,
13157                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13158                                           NULL,
13159                                           "cannot allocate resource memory");
13160         memcpy(queue, action_conf->queue, queue_size);
13161         MLX5_ASSERT(shared_rss->ind_tbl);
13162         rte_spinlock_lock(&shared_rss->action_rss_sl);
13163         queue_old = shared_rss->ind_tbl->queues;
13164         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13165                                         queue, action_conf->queue_num, true);
13166         if (ret) {
13167                 mlx5_free(queue);
13168                 ret = rte_flow_error_set(error, rte_errno,
13169                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13170                                           "cannot update indirection table");
13171         } else {
13172                 mlx5_free(queue_old);
13173                 shared_rss->origin.queue = queue;
13174                 shared_rss->origin.queue_num = action_conf->queue_num;
13175         }
13176         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13177         return ret;
13178 }
13179
13180 /**
13181  * Updates in place shared action configuration, lock free,
13182  * (mutex should be acquired by caller).
13183  *
13184  * @param[in] dev
13185  *   Pointer to the Ethernet device structure.
13186  * @param[in] action
13187  *   The shared action object to be updated.
13188  * @param[in] action_conf
13189  *   Action specification used to modify *action*.
13190  *   *action_conf* should be of type correlating with type of the *action*,
13191  *   otherwise considered as invalid.
13192  * @param[out] error
13193  *   Perform verbose error reporting if not NULL. Initialized in case of
13194  *   error only.
13195  *
13196  * @return
13197  *   0 on success, otherwise negative errno value.
13198  */
13199 static int
13200 flow_dv_action_update(struct rte_eth_dev *dev,
13201                         struct rte_flow_shared_action *action,
13202                         const void *action_conf,
13203                         struct rte_flow_error *err)
13204 {
13205         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13206         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13207         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13208
13209         switch (type) {
13210         case MLX5_SHARED_ACTION_TYPE_RSS:
13211                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13212         default:
13213                 return rte_flow_error_set(err, ENOTSUP,
13214                                           RTE_FLOW_ERROR_TYPE_ACTION,
13215                                           NULL,
13216                                           "action type update not supported");
13217         }
13218 }
13219
13220 static int
13221 flow_dv_action_query(struct rte_eth_dev *dev,
13222                      const struct rte_flow_shared_action *action, void *data,
13223                      struct rte_flow_error *error)
13224 {
13225         struct mlx5_age_param *age_param;
13226         struct rte_flow_query_age *resp;
13227         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13228         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13229         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13230
13231         switch (type) {
13232         case MLX5_SHARED_ACTION_TYPE_AGE:
13233                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13234                 resp = data;
13235                 resp->aged = __atomic_load_n(&age_param->state,
13236                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13237                                                                           1 : 0;
13238                 resp->sec_since_last_hit_valid = !resp->aged;
13239                 if (resp->sec_since_last_hit_valid)
13240                         resp->sec_since_last_hit = __atomic_load_n
13241                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13242                 return 0;
13243         default:
13244                 return rte_flow_error_set(error, ENOTSUP,
13245                                           RTE_FLOW_ERROR_TYPE_ACTION,
13246                                           NULL,
13247                                           "action type query not supported");
13248         }
13249 }
13250
13251 /**
13252  * Query a dv flow  rule for its statistics via devx.
13253  *
13254  * @param[in] dev
13255  *   Pointer to Ethernet device.
13256  * @param[in] flow
13257  *   Pointer to the sub flow.
13258  * @param[out] data
13259  *   data retrieved by the query.
13260  * @param[out] error
13261  *   Perform verbose error reporting if not NULL.
13262  *
13263  * @return
13264  *   0 on success, a negative errno value otherwise and rte_errno is set.
13265  */
13266 static int
13267 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13268                     void *data, struct rte_flow_error *error)
13269 {
13270         struct mlx5_priv *priv = dev->data->dev_private;
13271         struct rte_flow_query_count *qc = data;
13272
13273         if (!priv->config.devx)
13274                 return rte_flow_error_set(error, ENOTSUP,
13275                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13276                                           NULL,
13277                                           "counters are not supported");
13278         if (flow->counter) {
13279                 uint64_t pkts, bytes;
13280                 struct mlx5_flow_counter *cnt;
13281
13282                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13283                                                  NULL);
13284                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13285                                                &bytes);
13286
13287                 if (err)
13288                         return rte_flow_error_set(error, -err,
13289                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13290                                         NULL, "cannot read counters");
13291                 qc->hits_set = 1;
13292                 qc->bytes_set = 1;
13293                 qc->hits = pkts - cnt->hits;
13294                 qc->bytes = bytes - cnt->bytes;
13295                 if (qc->reset) {
13296                         cnt->hits = pkts;
13297                         cnt->bytes = bytes;
13298                 }
13299                 return 0;
13300         }
13301         return rte_flow_error_set(error, EINVAL,
13302                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13303                                   NULL,
13304                                   "counters are not available");
13305 }
13306
13307 /**
13308  * Query a flow rule AGE action for aging information.
13309  *
13310  * @param[in] dev
13311  *   Pointer to Ethernet device.
13312  * @param[in] flow
13313  *   Pointer to the sub flow.
13314  * @param[out] data
13315  *   data retrieved by the query.
13316  * @param[out] error
13317  *   Perform verbose error reporting if not NULL.
13318  *
13319  * @return
13320  *   0 on success, a negative errno value otherwise and rte_errno is set.
13321  */
13322 static int
13323 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13324                   void *data, struct rte_flow_error *error)
13325 {
13326         struct rte_flow_query_age *resp = data;
13327         struct mlx5_age_param *age_param;
13328
13329         if (flow->age) {
13330                 struct mlx5_aso_age_action *act =
13331                                      flow_aso_age_get_by_idx(dev, flow->age);
13332
13333                 age_param = &act->age_params;
13334         } else if (flow->counter) {
13335                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13336
13337                 if (!age_param || !age_param->timeout)
13338                         return rte_flow_error_set
13339                                         (error, EINVAL,
13340                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13341                                          NULL, "cannot read age data");
13342         } else {
13343                 return rte_flow_error_set(error, EINVAL,
13344                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13345                                           NULL, "age data not available");
13346         }
13347         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13348                                      AGE_TMOUT ? 1 : 0;
13349         resp->sec_since_last_hit_valid = !resp->aged;
13350         if (resp->sec_since_last_hit_valid)
13351                 resp->sec_since_last_hit = __atomic_load_n
13352                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13353         return 0;
13354 }
13355
13356 /**
13357  * Query a flow.
13358  *
13359  * @see rte_flow_query()
13360  * @see rte_flow_ops
13361  */
13362 static int
13363 flow_dv_query(struct rte_eth_dev *dev,
13364               struct rte_flow *flow __rte_unused,
13365               const struct rte_flow_action *actions __rte_unused,
13366               void *data __rte_unused,
13367               struct rte_flow_error *error __rte_unused)
13368 {
13369         int ret = -EINVAL;
13370
13371         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13372                 switch (actions->type) {
13373                 case RTE_FLOW_ACTION_TYPE_VOID:
13374                         break;
13375                 case RTE_FLOW_ACTION_TYPE_COUNT:
13376                         ret = flow_dv_query_count(dev, flow, data, error);
13377                         break;
13378                 case RTE_FLOW_ACTION_TYPE_AGE:
13379                         ret = flow_dv_query_age(dev, flow, data, error);
13380                         break;
13381                 default:
13382                         return rte_flow_error_set(error, ENOTSUP,
13383                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13384                                                   actions,
13385                                                   "action not supported");
13386                 }
13387         }
13388         return ret;
13389 }
13390
13391 /**
13392  * Destroy the meter table set.
13393  * Lock free, (mutex should be acquired by caller).
13394  *
13395  * @param[in] dev
13396  *   Pointer to Ethernet device.
13397  * @param[in] tbl
13398  *   Pointer to the meter table set.
13399  *
13400  * @return
13401  *   Always 0.
13402  */
13403 static int
13404 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13405                         struct mlx5_meter_domains_infos *tbl)
13406 {
13407         struct mlx5_priv *priv = dev->data->dev_private;
13408         struct mlx5_meter_domains_infos *mtd =
13409                                 (struct mlx5_meter_domains_infos *)tbl;
13410
13411         if (!mtd || !priv->config.dv_flow_en)
13412                 return 0;
13413         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13414                 claim_zero(mlx5_flow_os_destroy_flow
13415                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13416         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13417                 claim_zero(mlx5_flow_os_destroy_flow
13418                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13419         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13420                 claim_zero(mlx5_flow_os_destroy_flow
13421                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13422         if (mtd->egress.color_matcher)
13423                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13424                            (mtd->egress.color_matcher));
13425         if (mtd->egress.any_matcher)
13426                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13427                            (mtd->egress.any_matcher));
13428         if (mtd->egress.tbl)
13429                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13430         if (mtd->egress.sfx_tbl)
13431                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13432         if (mtd->ingress.color_matcher)
13433                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13434                            (mtd->ingress.color_matcher));
13435         if (mtd->ingress.any_matcher)
13436                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13437                            (mtd->ingress.any_matcher));
13438         if (mtd->ingress.tbl)
13439                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13440         if (mtd->ingress.sfx_tbl)
13441                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13442                                              mtd->ingress.sfx_tbl);
13443         if (mtd->transfer.color_matcher)
13444                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13445                            (mtd->transfer.color_matcher));
13446         if (mtd->transfer.any_matcher)
13447                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13448                            (mtd->transfer.any_matcher));
13449         if (mtd->transfer.tbl)
13450                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13451         if (mtd->transfer.sfx_tbl)
13452                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13453                                              mtd->transfer.sfx_tbl);
13454         if (mtd->drop_actn)
13455                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13456         mlx5_free(mtd);
13457         return 0;
13458 }
13459
13460 /* Number of meter flow actions, count and jump or count and drop. */
13461 #define METER_ACTIONS 2
13462
13463 /**
13464  * Create specify domain meter table and suffix table.
13465  *
13466  * @param[in] dev
13467  *   Pointer to Ethernet device.
13468  * @param[in,out] mtb
13469  *   Pointer to DV meter table set.
13470  * @param[in] egress
13471  *   Table attribute.
13472  * @param[in] transfer
13473  *   Table attribute.
13474  * @param[in] color_reg_c_idx
13475  *   Reg C index for color match.
13476  *
13477  * @return
13478  *   0 on success, -1 otherwise and rte_errno is set.
13479  */
13480 static int
13481 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13482                            struct mlx5_meter_domains_infos *mtb,
13483                            uint8_t egress, uint8_t transfer,
13484                            uint32_t color_reg_c_idx)
13485 {
13486         struct mlx5_priv *priv = dev->data->dev_private;
13487         struct mlx5_dev_ctx_shared *sh = priv->sh;
13488         struct mlx5_flow_dv_match_params mask = {
13489                 .size = sizeof(mask.buf),
13490         };
13491         struct mlx5_flow_dv_match_params value = {
13492                 .size = sizeof(value.buf),
13493         };
13494         struct mlx5dv_flow_matcher_attr dv_attr = {
13495                 .type = IBV_FLOW_ATTR_NORMAL,
13496                 .priority = 0,
13497                 .match_criteria_enable = 0,
13498                 .match_mask = (void *)&mask,
13499         };
13500         void *actions[METER_ACTIONS];
13501         struct mlx5_meter_domain_info *dtb;
13502         struct rte_flow_error error;
13503         int i = 0;
13504         int ret;
13505
13506         if (transfer)
13507                 dtb = &mtb->transfer;
13508         else if (egress)
13509                 dtb = &mtb->egress;
13510         else
13511                 dtb = &mtb->ingress;
13512         /* Create the meter table with METER level. */
13513         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13514                                             egress, transfer, false, NULL, 0,
13515                                             0, &error);
13516         if (!dtb->tbl) {
13517                 DRV_LOG(ERR, "Failed to create meter policer table.");
13518                 return -1;
13519         }
13520         /* Create the meter suffix table with SUFFIX level. */
13521         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13522                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13523                                             egress, transfer, false, NULL, 0,
13524                                             0, &error);
13525         if (!dtb->sfx_tbl) {
13526                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13527                 return -1;
13528         }
13529         /* Create matchers, Any and Color. */
13530         dv_attr.priority = 3;
13531         dv_attr.match_criteria_enable = 0;
13532         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13533                                                &dtb->any_matcher);
13534         if (ret) {
13535                 DRV_LOG(ERR, "Failed to create meter"
13536                              " policer default matcher.");
13537                 goto error_exit;
13538         }
13539         dv_attr.priority = 0;
13540         dv_attr.match_criteria_enable =
13541                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13542         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13543                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13544         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13545                                                &dtb->color_matcher);
13546         if (ret) {
13547                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13548                 goto error_exit;
13549         }
13550         if (mtb->count_actns[RTE_MTR_DROPPED])
13551                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13552         actions[i++] = mtb->drop_actn;
13553         /* Default rule: lowest priority, match any, actions: drop. */
13554         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13555                                        actions,
13556                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13557         if (ret) {
13558                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13559                 goto error_exit;
13560         }
13561         return 0;
13562 error_exit:
13563         return -1;
13564 }
13565
13566 /**
13567  * Create the needed meter and suffix tables.
13568  * Lock free, (mutex should be acquired by caller).
13569  *
13570  * @param[in] dev
13571  *   Pointer to Ethernet device.
13572  * @param[in] fm
13573  *   Pointer to the flow meter.
13574  *
13575  * @return
13576  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13577  */
13578 static struct mlx5_meter_domains_infos *
13579 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13580                        const struct mlx5_flow_meter *fm)
13581 {
13582         struct mlx5_priv *priv = dev->data->dev_private;
13583         struct mlx5_meter_domains_infos *mtb;
13584         int ret;
13585         int i;
13586
13587         if (!priv->mtr_en) {
13588                 rte_errno = ENOTSUP;
13589                 return NULL;
13590         }
13591         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13592         if (!mtb) {
13593                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13594                 return NULL;
13595         }
13596         /* Create meter count actions */
13597         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13598                 struct mlx5_flow_counter *cnt;
13599                 if (!fm->policer_stats.cnt[i])
13600                         continue;
13601                 cnt = flow_dv_counter_get_by_idx(dev,
13602                       fm->policer_stats.cnt[i], NULL);
13603                 mtb->count_actns[i] = cnt->action;
13604         }
13605         /* Create drop action. */
13606         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13607         if (ret) {
13608                 DRV_LOG(ERR, "Failed to create drop action.");
13609                 goto error_exit;
13610         }
13611         /* Egress meter table. */
13612         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13613         if (ret) {
13614                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13615                 goto error_exit;
13616         }
13617         /* Ingress meter table. */
13618         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13619         if (ret) {
13620                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13621                 goto error_exit;
13622         }
13623         /* FDB meter table. */
13624         if (priv->config.dv_esw_en) {
13625                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13626                                                  priv->mtr_color_reg);
13627                 if (ret) {
13628                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13629                         goto error_exit;
13630                 }
13631         }
13632         return mtb;
13633 error_exit:
13634         flow_dv_destroy_mtr_tbl(dev, mtb);
13635         return NULL;
13636 }
13637
13638 /**
13639  * Destroy domain policer rule.
13640  *
13641  * @param[in] dt
13642  *   Pointer to domain table.
13643  */
13644 static void
13645 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13646 {
13647         int i;
13648
13649         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13650                 if (dt->policer_rules[i]) {
13651                         claim_zero(mlx5_flow_os_destroy_flow
13652                                    (dt->policer_rules[i]));
13653                         dt->policer_rules[i] = NULL;
13654                 }
13655         }
13656         if (dt->jump_actn) {
13657                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13658                 dt->jump_actn = NULL;
13659         }
13660 }
13661
13662 /**
13663  * Destroy policer rules.
13664  *
13665  * @param[in] dev
13666  *   Pointer to Ethernet device.
13667  * @param[in] fm
13668  *   Pointer to flow meter structure.
13669  * @param[in] attr
13670  *   Pointer to flow attributes.
13671  *
13672  * @return
13673  *   Always 0.
13674  */
13675 static int
13676 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13677                               const struct mlx5_flow_meter *fm,
13678                               const struct rte_flow_attr *attr)
13679 {
13680         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13681
13682         if (!mtb)
13683                 return 0;
13684         if (attr->egress)
13685                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13686         if (attr->ingress)
13687                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13688         if (attr->transfer)
13689                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13690         return 0;
13691 }
13692
13693 /**
13694  * Create specify domain meter policer rule.
13695  *
13696  * @param[in] fm
13697  *   Pointer to flow meter structure.
13698  * @param[in] mtb
13699  *   Pointer to DV meter table set.
13700  * @param[in] mtr_reg_c
13701  *   Color match REG_C.
13702  *
13703  * @return
13704  *   0 on success, -1 otherwise.
13705  */
13706 static int
13707 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13708                                     struct mlx5_meter_domain_info *dtb,
13709                                     uint8_t mtr_reg_c)
13710 {
13711         struct mlx5_flow_dv_match_params matcher = {
13712                 .size = sizeof(matcher.buf),
13713         };
13714         struct mlx5_flow_dv_match_params value = {
13715                 .size = sizeof(value.buf),
13716         };
13717         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13718         void *actions[METER_ACTIONS];
13719         int i;
13720         int ret = 0;
13721
13722         /* Create jump action. */
13723         if (!dtb->jump_actn)
13724                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13725                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13726         if (ret) {
13727                 DRV_LOG(ERR, "Failed to create policer jump action.");
13728                 goto error;
13729         }
13730         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13731                 int j = 0;
13732
13733                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13734                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13735                 if (mtb->count_actns[i])
13736                         actions[j++] = mtb->count_actns[i];
13737                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13738                         actions[j++] = mtb->drop_actn;
13739                 else
13740                         actions[j++] = dtb->jump_actn;
13741                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13742                                                (void *)&value, j, actions,
13743                                                &dtb->policer_rules[i]);
13744                 if (ret) {
13745                         DRV_LOG(ERR, "Failed to create policer rule.");
13746                         goto error;
13747                 }
13748         }
13749         return 0;
13750 error:
13751         rte_errno = errno;
13752         return -1;
13753 }
13754
13755 /**
13756  * Create policer rules.
13757  *
13758  * @param[in] dev
13759  *   Pointer to Ethernet device.
13760  * @param[in] fm
13761  *   Pointer to flow meter structure.
13762  * @param[in] attr
13763  *   Pointer to flow attributes.
13764  *
13765  * @return
13766  *   0 on success, -1 otherwise.
13767  */
13768 static int
13769 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13770                              struct mlx5_flow_meter *fm,
13771                              const struct rte_flow_attr *attr)
13772 {
13773         struct mlx5_priv *priv = dev->data->dev_private;
13774         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13775         int ret;
13776
13777         if (attr->egress) {
13778                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13779                                                 priv->mtr_color_reg);
13780                 if (ret) {
13781                         DRV_LOG(ERR, "Failed to create egress policer.");
13782                         goto error;
13783                 }
13784         }
13785         if (attr->ingress) {
13786                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13787                                                 priv->mtr_color_reg);
13788                 if (ret) {
13789                         DRV_LOG(ERR, "Failed to create ingress policer.");
13790                         goto error;
13791                 }
13792         }
13793         if (attr->transfer) {
13794                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13795                                                 priv->mtr_color_reg);
13796                 if (ret) {
13797                         DRV_LOG(ERR, "Failed to create transfer policer.");
13798                         goto error;
13799                 }
13800         }
13801         return 0;
13802 error:
13803         flow_dv_destroy_policer_rules(dev, fm, attr);
13804         return -1;
13805 }
13806
13807 /**
13808  * Validate the batch counter support in root table.
13809  *
13810  * Create a simple flow with invalid counter and drop action on root table to
13811  * validate if batch counter with offset on root table is supported or not.
13812  *
13813  * @param[in] dev
13814  *   Pointer to rte_eth_dev structure.
13815  *
13816  * @return
13817  *   0 on success, a negative errno value otherwise and rte_errno is set.
13818  */
13819 int
13820 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13821 {
13822         struct mlx5_priv *priv = dev->data->dev_private;
13823         struct mlx5_dev_ctx_shared *sh = priv->sh;
13824         struct mlx5_flow_dv_match_params mask = {
13825                 .size = sizeof(mask.buf),
13826         };
13827         struct mlx5_flow_dv_match_params value = {
13828                 .size = sizeof(value.buf),
13829         };
13830         struct mlx5dv_flow_matcher_attr dv_attr = {
13831                 .type = IBV_FLOW_ATTR_NORMAL,
13832                 .priority = 0,
13833                 .match_criteria_enable = 0,
13834                 .match_mask = (void *)&mask,
13835         };
13836         void *actions[2] = { 0 };
13837         struct mlx5_flow_tbl_resource *tbl = NULL;
13838         struct mlx5_devx_obj *dcs = NULL;
13839         void *matcher = NULL;
13840         void *flow = NULL;
13841         int ret = -1;
13842
13843         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13844         if (!tbl)
13845                 goto err;
13846         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13847         if (!dcs)
13848                 goto err;
13849         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13850                                                     &actions[0]);
13851         if (ret)
13852                 goto err;
13853         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13854                                           priv->drop_queue.hrxq->action;
13855         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13856         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13857                                                &matcher);
13858         if (ret)
13859                 goto err;
13860         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13861                                        actions, &flow);
13862 err:
13863         /*
13864          * If batch counter with offset is not supported, the driver will not
13865          * validate the invalid offset value, flow create should success.
13866          * In this case, it means batch counter is not supported in root table.
13867          *
13868          * Otherwise, if flow create is failed, counter offset is supported.
13869          */
13870         if (flow) {
13871                 DRV_LOG(INFO, "Batch counter is not supported in root "
13872                               "table. Switch to fallback mode.");
13873                 rte_errno = ENOTSUP;
13874                 ret = -rte_errno;
13875                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13876         } else {
13877                 /* Check matcher to make sure validate fail at flow create. */
13878                 if (!matcher || (matcher && errno != EINVAL))
13879                         DRV_LOG(ERR, "Unexpected error in counter offset "
13880                                      "support detection");
13881                 ret = 0;
13882         }
13883         if (actions[0])
13884                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13885         if (matcher)
13886                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13887         if (tbl)
13888                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13889         if (dcs)
13890                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13891         return ret;
13892 }
13893
13894 /**
13895  * Query a devx counter.
13896  *
13897  * @param[in] dev
13898  *   Pointer to the Ethernet device structure.
13899  * @param[in] cnt
13900  *   Index to the flow counter.
13901  * @param[in] clear
13902  *   Set to clear the counter statistics.
13903  * @param[out] pkts
13904  *   The statistics value of packets.
13905  * @param[out] bytes
13906  *   The statistics value of bytes.
13907  *
13908  * @return
13909  *   0 on success, otherwise return -1.
13910  */
13911 static int
13912 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13913                       uint64_t *pkts, uint64_t *bytes)
13914 {
13915         struct mlx5_priv *priv = dev->data->dev_private;
13916         struct mlx5_flow_counter *cnt;
13917         uint64_t inn_pkts, inn_bytes;
13918         int ret;
13919
13920         if (!priv->config.devx)
13921                 return -1;
13922
13923         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13924         if (ret)
13925                 return -1;
13926         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13927         *pkts = inn_pkts - cnt->hits;
13928         *bytes = inn_bytes - cnt->bytes;
13929         if (clear) {
13930                 cnt->hits = inn_pkts;
13931                 cnt->bytes = inn_bytes;
13932         }
13933         return 0;
13934 }
13935
13936 /**
13937  * Get aged-out flows.
13938  *
13939  * @param[in] dev
13940  *   Pointer to the Ethernet device structure.
13941  * @param[in] context
13942  *   The address of an array of pointers to the aged-out flows contexts.
13943  * @param[in] nb_contexts
13944  *   The length of context array pointers.
13945  * @param[out] error
13946  *   Perform verbose error reporting if not NULL. Initialized in case of
13947  *   error only.
13948  *
13949  * @return
13950  *   how many contexts get in success, otherwise negative errno value.
13951  *   if nb_contexts is 0, return the amount of all aged contexts.
13952  *   if nb_contexts is not 0 , return the amount of aged flows reported
13953  *   in the context array.
13954  * @note: only stub for now
13955  */
13956 static int
13957 flow_get_aged_flows(struct rte_eth_dev *dev,
13958                     void **context,
13959                     uint32_t nb_contexts,
13960                     struct rte_flow_error *error)
13961 {
13962         struct mlx5_priv *priv = dev->data->dev_private;
13963         struct mlx5_age_info *age_info;
13964         struct mlx5_age_param *age_param;
13965         struct mlx5_flow_counter *counter;
13966         struct mlx5_aso_age_action *act;
13967         int nb_flows = 0;
13968
13969         if (nb_contexts && !context)
13970                 return rte_flow_error_set(error, EINVAL,
13971                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13972                                           NULL, "empty context");
13973         age_info = GET_PORT_AGE_INFO(priv);
13974         rte_spinlock_lock(&age_info->aged_sl);
13975         LIST_FOREACH(act, &age_info->aged_aso, next) {
13976                 nb_flows++;
13977                 if (nb_contexts) {
13978                         context[nb_flows - 1] =
13979                                                 act->age_params.context;
13980                         if (!(--nb_contexts))
13981                                 break;
13982                 }
13983         }
13984         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13985                 nb_flows++;
13986                 if (nb_contexts) {
13987                         age_param = MLX5_CNT_TO_AGE(counter);
13988                         context[nb_flows - 1] = age_param->context;
13989                         if (!(--nb_contexts))
13990                                 break;
13991                 }
13992         }
13993         rte_spinlock_unlock(&age_info->aged_sl);
13994         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13995         return nb_flows;
13996 }
13997
13998 /*
13999  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14000  */
14001 static uint32_t
14002 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14003 {
14004         return flow_dv_counter_alloc(dev, 0);
14005 }
14006
14007 /**
14008  * Validate shared action.
14009  * Dispatcher for action type specific validation.
14010  *
14011  * @param[in] dev
14012  *   Pointer to the Ethernet device structure.
14013  * @param[in] conf
14014  *   Shared action configuration.
14015  * @param[in] action
14016  *   The shared action object to validate.
14017  * @param[out] error
14018  *   Perform verbose error reporting if not NULL. Initialized in case of
14019  *   error only.
14020  *
14021  * @return
14022  *   0 on success, otherwise negative errno value.
14023  */
14024 static int
14025 flow_dv_action_validate(struct rte_eth_dev *dev,
14026                         const struct rte_flow_shared_action_conf *conf,
14027                         const struct rte_flow_action *action,
14028                         struct rte_flow_error *err)
14029 {
14030         struct mlx5_priv *priv = dev->data->dev_private;
14031
14032         RTE_SET_USED(conf);
14033         switch (action->type) {
14034         case RTE_FLOW_ACTION_TYPE_RSS:
14035                 /*
14036                  * priv->obj_ops is set according to driver capabilities.
14037                  * When DevX capabilities are
14038                  * sufficient, it is set to devx_obj_ops.
14039                  * Otherwise, it is set to ibv_obj_ops.
14040                  * ibv_obj_ops doesn't support ind_table_modify operation.
14041                  * In this case the shared RSS action can't be used.
14042                  */
14043                 if (priv->obj_ops.ind_table_modify == NULL)
14044                         return rte_flow_error_set
14045                                         (err, ENOTSUP,
14046                                          RTE_FLOW_ERROR_TYPE_ACTION,
14047                                          NULL,
14048                                          "shared RSS action not supported");
14049                 return mlx5_validate_action_rss(dev, action, err);
14050         case RTE_FLOW_ACTION_TYPE_AGE:
14051                 if (!priv->sh->aso_age_mng)
14052                         return rte_flow_error_set(err, ENOTSUP,
14053                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14054                                                 NULL,
14055                                              "shared age action not supported");
14056                 return flow_dv_validate_action_age(0, action, dev, err);
14057         default:
14058                 return rte_flow_error_set(err, ENOTSUP,
14059                                           RTE_FLOW_ERROR_TYPE_ACTION,
14060                                           NULL,
14061                                           "action type not supported");
14062         }
14063 }
14064
14065 static int
14066 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14067 {
14068         struct mlx5_priv *priv = dev->data->dev_private;
14069         int ret = 0;
14070
14071         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14072                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14073                                                 flags);
14074                 if (ret != 0)
14075                         return ret;
14076         }
14077         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14078                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14079                 if (ret != 0)
14080                         return ret;
14081         }
14082         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14083                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14084                 if (ret != 0)
14085                         return ret;
14086         }
14087         return 0;
14088 }
14089
14090 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14091         .validate = flow_dv_validate,
14092         .prepare = flow_dv_prepare,
14093         .translate = flow_dv_translate,
14094         .apply = flow_dv_apply,
14095         .remove = flow_dv_remove,
14096         .destroy = flow_dv_destroy,
14097         .query = flow_dv_query,
14098         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14099         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14100         .create_policer_rules = flow_dv_create_policer_rules,
14101         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14102         .counter_alloc = flow_dv_counter_allocate,
14103         .counter_free = flow_dv_counter_free,
14104         .counter_query = flow_dv_counter_query,
14105         .get_aged_flows = flow_get_aged_flows,
14106         .action_validate = flow_dv_action_validate,
14107         .action_create = flow_dv_action_create,
14108         .action_destroy = flow_dv_action_destroy,
14109         .action_update = flow_dv_action_update,
14110         .action_query = flow_dv_action_query,
14111         .sync_domain = flow_dv_sync_domain,
14112 };
14113
14114 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14115