1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* Get CQE owner bit. */
25 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
28 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
31 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
33 /* Get CQE solicited event. */
34 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
36 /* Invalidate a CQE. */
37 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
39 /* Maximum number of packets a multi-packet WQE can handle. */
40 #define MLX5_MPW_DSEG_MAX 5
43 #define MLX5_WQE_DWORD_SIZE 16
46 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
48 /* Max size of a WQE session. */
49 #define MLX5_WQE_SIZE_MAX 960U
51 /* Compute the number of DS. */
52 #define MLX5_WQE_DS(n) \
53 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
55 /* Room for inline data in multi-packet WQE. */
56 #define MLX5_MWQE64_INL_DATA 28
58 /* Default minimum number of Tx queues for inlining packets. */
59 #define MLX5_EMPW_MIN_TXQS 8
61 /* Default max packet length to be inlined. */
62 #define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
65 #define MLX5_OPC_MOD_ENHANCED_MPSW 0
66 #define MLX5_OPCODE_ENHANCED_MPSW 0x29
68 /* CQE value to inform that VLAN is stripped. */
69 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
72 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
75 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
78 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
81 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
84 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
86 /* IP is fragmented. */
87 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
89 /* L2 header is valid. */
90 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
92 /* L3 header is valid. */
93 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
95 /* L4 header is valid. */
96 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
98 /* Outer packet, 0 IPv4, 1 IPv6. */
99 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
101 /* Tunnel packet bit in the CQE. */
102 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
104 /* Inner L3 checksum offload (Tunneled packets only). */
105 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
107 /* Inner L4 checksum offload (Tunneled packets only). */
108 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
110 /* Outer L4 type is TCP. */
111 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
113 /* Outer L4 type is UDP. */
114 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
116 /* Outer L3 type is IPV4. */
117 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
119 /* Outer L3 type is IPV6. */
120 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
122 /* Inner L4 type is TCP. */
123 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
125 /* Inner L4 type is UDP. */
126 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
128 /* Inner L3 type is IPV4. */
129 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
131 /* Inner L3 type is IPV6. */
132 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
134 /* Is flow mark valid. */
135 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
136 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
138 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
141 /* INVALID is used by packets matching no flow rules. */
142 #define MLX5_FLOW_MARK_INVALID 0
144 /* Maximum allowed value to mark a packet. */
145 #define MLX5_FLOW_MARK_MAX 0xfffff0
147 /* Default mark value used when none is provided. */
148 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
150 /* Maximum number of DS in WQE. */
151 #define MLX5_DSEG_MAX 63
153 /* Subset of struct mlx5_wqe_eth_seg. */
154 struct mlx5_wqe_eth_seg_small {
160 uint16_t inline_hdr_sz;
161 uint8_t inline_hdr[2];
162 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
164 struct mlx5_wqe_inl_small {
167 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
169 struct mlx5_wqe_ctrl {
174 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
176 /* Small common part of the WQE. */
179 struct mlx5_wqe_eth_seg_small eseg;
182 /* Vectorize WQE header. */
192 } __rte_aligned(MLX5_WQE_SIZE);
198 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
201 /* MPW session status. */
202 enum mlx5_mpw_state {
203 MLX5_MPW_STATE_OPENED,
204 MLX5_MPW_INL_STATE_OPENED,
205 MLX5_MPW_ENHANCED_STATE_OPENED,
206 MLX5_MPW_STATE_CLOSED,
209 /* MPW session descriptor. */
211 enum mlx5_mpw_state state;
214 unsigned int total_len;
215 volatile struct mlx5_wqe *wqe;
217 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
218 volatile uint8_t *raw;
222 /* CQ element structure - should be equal to the cache line size */
224 #if (RTE_CACHE_LINE_SIZE == 128)
229 uint32_t rx_hash_res;
230 uint8_t rx_hash_type;
232 uint16_t hdr_type_etc;
237 uint32_t sop_drop_qpn;
238 uint16_t wqe_counter;
243 /* Adding direct verbs to data-path. */
245 /* CQ sequence number mask. */
246 #define MLX5_CQ_SQN_MASK 0x3
248 /* CQ sequence number index. */
249 #define MLX5_CQ_SQN_OFFSET 28
251 /* CQ doorbell index mask. */
252 #define MLX5_CI_MASK 0xffffff
254 /* CQ doorbell offset. */
255 #define MLX5_CQ_ARM_DB 1
257 /* CQ doorbell offset*/
258 #define MLX5_CQ_DOORBELL 0x20
260 /* CQE format value. */
261 #define MLX5_COMPRESSED 0x3
263 /* CQE format mask. */
264 #define MLX5E_CQE_FORMAT_MASK 0xc
267 #define MLX5_OPC_MOD_MPW 0x01
269 /* Compressed Rx CQE structure. */
270 struct mlx5_mini_cqe8 {
272 uint32_t rx_hash_result;
275 uint16_t wqe_counter;
276 uint8_t s_wqe_opcode;
284 * Convert a user mark to flow mark.
287 * Mark value to convert.
290 * Converted mark value.
292 static inline uint32_t
293 mlx5_flow_mark_set(uint32_t val)
298 * Add one to the user value to differentiate un-marked flows from
299 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
302 if (val != MLX5_FLOW_MARK_DEFAULT)
304 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
306 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
307 * word, byte-swapped by the kernel on little-endian systems. In this
308 * case, left-shifting the resulting big-endian value ensures the
309 * least significant 24 bits are retained when converting it back.
311 ret = rte_cpu_to_be_32(val) >> 8;
319 * Convert a mark to user mark.
322 * Mark value to convert.
325 * Converted mark value.
327 static inline uint32_t
328 mlx5_flow_mark_get(uint32_t val)
331 * Subtract one from the retrieved value. It was added by
332 * mlx5_flow_mark_set() to distinguish unmarked flows.
334 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
335 return (val >> 8) - 1;
341 #endif /* RTE_PMD_MLX5_PRM_H_ */