1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* Maximum number of packets a multi-packet WQE can handle. */
43 #define MLX5_MPW_DSEG_MAX 5
46 #define MLX5_WQE_DWORD_SIZE 16
49 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
51 /* Max size of a WQE session. */
52 #define MLX5_WQE_SIZE_MAX 960U
54 /* Compute the number of DS. */
55 #define MLX5_WQE_DS(n) \
56 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
58 /* Room for inline data in multi-packet WQE. */
59 #define MLX5_MWQE64_INL_DATA 28
61 /* Default minimum number of Tx queues for inlining packets. */
62 #define MLX5_EMPW_MIN_TXQS 8
64 /* Default max packet length to be inlined. */
65 #define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
68 #define MLX5_OPC_MOD_ENHANCED_MPSW 0
69 #define MLX5_OPCODE_ENHANCED_MPSW 0x29
71 /* CQE value to inform that VLAN is stripped. */
72 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
75 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
78 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
81 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
84 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
87 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
89 /* IP is fragmented. */
90 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
92 /* L2 header is valid. */
93 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
95 /* L3 header is valid. */
96 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
98 /* L4 header is valid. */
99 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
101 /* Outer packet, 0 IPv4, 1 IPv6. */
102 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
104 /* Tunnel packet bit in the CQE. */
105 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
107 /* Inner L3 checksum offload (Tunneled packets only). */
108 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
110 /* Inner L4 checksum offload (Tunneled packets only). */
111 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
113 /* Outer L4 type is TCP. */
114 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
116 /* Outer L4 type is UDP. */
117 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
119 /* Outer L3 type is IPV4. */
120 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
122 /* Outer L3 type is IPV6. */
123 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
125 /* Inner L4 type is TCP. */
126 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
128 /* Inner L4 type is UDP. */
129 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
131 /* Inner L3 type is IPV4. */
132 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
134 /* Inner L3 type is IPV6. */
135 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
137 /* Is flow mark valid. */
138 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
139 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
141 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
144 /* INVALID is used by packets matching no flow rules. */
145 #define MLX5_FLOW_MARK_INVALID 0
147 /* Maximum allowed value to mark a packet. */
148 #define MLX5_FLOW_MARK_MAX 0xfffff0
150 /* Default mark value used when none is provided. */
151 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
153 /* Maximum number of DS in WQE. */
154 #define MLX5_DSEG_MAX 63
156 /* Subset of struct mlx5_wqe_eth_seg. */
157 struct mlx5_wqe_eth_seg_small {
163 uint16_t inline_hdr_sz;
164 uint8_t inline_hdr[2];
165 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
167 struct mlx5_wqe_inl_small {
170 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
172 struct mlx5_wqe_ctrl {
177 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
179 /* Small common part of the WQE. */
182 struct mlx5_wqe_eth_seg_small eseg;
185 /* Vectorize WQE header. */
195 } __rte_aligned(MLX5_WQE_SIZE);
201 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
204 /* MPW session status. */
205 enum mlx5_mpw_state {
206 MLX5_MPW_STATE_OPENED,
207 MLX5_MPW_INL_STATE_OPENED,
208 MLX5_MPW_ENHANCED_STATE_OPENED,
209 MLX5_MPW_STATE_CLOSED,
212 /* MPW session descriptor. */
214 enum mlx5_mpw_state state;
217 unsigned int total_len;
218 volatile struct mlx5_wqe *wqe;
220 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
221 volatile uint8_t *raw;
225 /* WQE for Multi-Packet RQ. */
226 struct mlx5_wqe_mprq {
227 struct mlx5_wqe_srq_next_seg next_seg;
228 struct mlx5_wqe_data_seg dseg;
231 #define MLX5_MPRQ_LEN_MASK 0x000ffff
232 #define MLX5_MPRQ_LEN_SHIFT 0
233 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
234 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
235 #define MLX5_MPRQ_FILLER_MASK 0x80000000
236 #define MLX5_MPRQ_FILLER_SHIFT 31
238 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
240 /* CQ element structure - should be equal to the cache line size */
242 #if (RTE_CACHE_LINE_SIZE == 128)
249 uint32_t rx_hash_res;
250 uint8_t rx_hash_type;
252 uint16_t hdr_type_etc;
257 uint32_t sop_drop_qpn;
258 uint16_t wqe_counter;
263 /* Adding direct verbs to data-path. */
265 /* CQ sequence number mask. */
266 #define MLX5_CQ_SQN_MASK 0x3
268 /* CQ sequence number index. */
269 #define MLX5_CQ_SQN_OFFSET 28
271 /* CQ doorbell index mask. */
272 #define MLX5_CI_MASK 0xffffff
274 /* CQ doorbell offset. */
275 #define MLX5_CQ_ARM_DB 1
277 /* CQ doorbell offset*/
278 #define MLX5_CQ_DOORBELL 0x20
280 /* CQE format value. */
281 #define MLX5_COMPRESSED 0x3
283 /* CQE format mask. */
284 #define MLX5E_CQE_FORMAT_MASK 0xc
287 #define MLX5_OPC_MOD_MPW 0x01
289 /* Compressed Rx CQE structure. */
290 struct mlx5_mini_cqe8 {
292 uint32_t rx_hash_result;
298 uint16_t wqe_counter;
299 uint8_t s_wqe_opcode;
307 * Convert a user mark to flow mark.
310 * Mark value to convert.
313 * Converted mark value.
315 static inline uint32_t
316 mlx5_flow_mark_set(uint32_t val)
321 * Add one to the user value to differentiate un-marked flows from
322 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
325 if (val != MLX5_FLOW_MARK_DEFAULT)
327 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
329 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
330 * word, byte-swapped by the kernel on little-endian systems. In this
331 * case, left-shifting the resulting big-endian value ensures the
332 * least significant 24 bits are retained when converting it back.
334 ret = rte_cpu_to_be_32(val) >> 8;
342 * Convert a mark to user mark.
345 * Mark value to convert.
348 * Converted mark value.
350 static inline uint32_t
351 mlx5_flow_mark_get(uint32_t val)
354 * Subtract one from the retrieved value. It was added by
355 * mlx5_flow_mark_set() to distinguish unmarked flows.
357 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
358 return (val >> 8) - 1;
364 #endif /* RTE_PMD_MLX5_PRM_H_ */