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34 #ifndef RTE_PMD_MLX5_PRM_H_
35 #define RTE_PMD_MLX5_PRM_H_
38 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
40 #pragma GCC diagnostic ignored "-pedantic"
42 #include <infiniband/mlx5_hw.h>
44 #pragma GCC diagnostic error "-pedantic"
47 /* Get CQE owner bit. */
48 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
51 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
54 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
56 /* Get CQE solicited event. */
57 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
59 /* Invalidate a CQE. */
60 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
62 /* CQE value to inform that VLAN is stripped. */
63 #define MLX5_CQE_VLAN_STRIPPED 0x1
65 /* Maximum number of packets a multi-packet WQE can handle. */
66 #define MLX5_MPW_DSEG_MAX 5
68 /* Room for inline data in regular work queue element. */
69 #define MLX5_WQE64_INL_DATA 12
71 /* Room for inline data in multi-packet WQE. */
72 #define MLX5_MWQE64_INL_DATA 28
74 /* Subset of struct mlx5_wqe_eth_seg. */
75 struct mlx5_wqe_eth_seg_small {
81 uint16_t inline_hdr_sz;
85 struct mlx5_wqe_regular {
87 struct mlx5_wqe_ctrl_seg ctrl;
90 struct mlx5_wqe_eth_seg eseg;
91 struct mlx5_wqe_data_seg dseg;
97 struct mlx5_wqe_ctrl_seg ctrl;
100 struct mlx5_wqe_eth_seg eseg;
102 uint8_t data[MLX5_WQE64_INL_DATA];
105 /* Multi-packet WQE. */
106 struct mlx5_wqe_mpw {
108 struct mlx5_wqe_ctrl_seg ctrl;
111 struct mlx5_wqe_eth_seg_small eseg;
112 struct mlx5_wqe_data_seg dseg[2];
115 /* Multi-packet WQE with inline. */
116 struct mlx5_wqe_mpw_inl {
118 struct mlx5_wqe_ctrl_seg ctrl;
121 struct mlx5_wqe_eth_seg_small eseg;
123 uint8_t data[MLX5_MWQE64_INL_DATA];
126 /* Union of all WQE types. */
128 struct mlx5_wqe_regular wqe;
129 struct mlx5_wqe_inl inl;
130 struct mlx5_wqe_mpw mpw;
131 struct mlx5_wqe_mpw_inl mpw_inl;
135 /* MPW session status. */
136 enum mlx5_mpw_state {
137 MLX5_MPW_STATE_OPENED,
138 MLX5_MPW_INL_STATE_OPENED,
139 MLX5_MPW_STATE_CLOSED,
142 /* MPW session descriptor. */
144 enum mlx5_mpw_state state;
147 unsigned int total_len;
148 volatile union mlx5_wqe *wqe;
150 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
151 volatile uint8_t *raw;
155 /* CQ element structure - should be equal to the cache line size */
157 #if (RTE_CACHE_LINE_SIZE == 128)
160 struct mlx5_cqe64 cqe64;
163 #endif /* RTE_PMD_MLX5_PRM_H_ */