1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* Maximum number of packets a multi-packet WQE can handle. */
43 #define MLX5_MPW_DSEG_MAX 5
46 #define MLX5_WQE_DWORD_SIZE 16
49 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
51 /* Max size of a WQE session. */
52 #define MLX5_WQE_SIZE_MAX 960U
54 /* Compute the number of DS. */
55 #define MLX5_WQE_DS(n) \
56 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
58 /* Room for inline data in multi-packet WQE. */
59 #define MLX5_MWQE64_INL_DATA 28
61 /* Default minimum number of Tx queues for inlining packets. */
62 #define MLX5_EMPW_MIN_TXQS 8
64 /* Default max packet length to be inlined. */
65 #define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
68 #define MLX5_OPC_MOD_ENHANCED_MPSW 0
69 #define MLX5_OPCODE_ENHANCED_MPSW 0x29
71 /* CQE value to inform that VLAN is stripped. */
72 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
75 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
78 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
81 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
84 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
87 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
89 /* IP is fragmented. */
90 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
92 /* L2 header is valid. */
93 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
95 /* L3 header is valid. */
96 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
98 /* L4 header is valid. */
99 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
101 /* Outer packet, 0 IPv4, 1 IPv6. */
102 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
104 /* Tunnel packet bit in the CQE. */
105 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
107 /* Inner L3 checksum offload (Tunneled packets only). */
108 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
110 /* Inner L4 checksum offload (Tunneled packets only). */
111 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
113 /* Outer L4 type is TCP. */
114 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
116 /* Outer L4 type is UDP. */
117 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
119 /* Outer L3 type is IPV4. */
120 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
122 /* Outer L3 type is IPV6. */
123 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
125 /* Inner L4 type is TCP. */
126 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
128 /* Inner L4 type is UDP. */
129 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
131 /* Inner L3 type is IPV4. */
132 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
134 /* Inner L3 type is IPV6. */
135 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
137 /* Is flow mark valid. */
138 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
139 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
141 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
144 /* INVALID is used by packets matching no flow rules. */
145 #define MLX5_FLOW_MARK_INVALID 0
147 /* Maximum allowed value to mark a packet. */
148 #define MLX5_FLOW_MARK_MAX 0xfffff0
150 /* Default mark value used when none is provided. */
151 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
153 /* Maximum number of DS in WQE. */
154 #define MLX5_DSEG_MAX 63
156 /* Subset of struct mlx5_wqe_eth_seg. */
157 struct mlx5_wqe_eth_seg_small {
163 uint16_t inline_hdr_sz;
164 uint8_t inline_hdr[2];
165 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
167 struct mlx5_wqe_inl_small {
170 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
172 struct mlx5_wqe_ctrl {
177 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
179 /* Small common part of the WQE. */
182 struct mlx5_wqe_eth_seg_small eseg;
185 /* Vectorize WQE header. */
195 } __rte_aligned(MLX5_WQE_SIZE);
201 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
204 /* MPW session status. */
205 enum mlx5_mpw_state {
206 MLX5_MPW_STATE_OPENED,
207 MLX5_MPW_INL_STATE_OPENED,
208 MLX5_MPW_ENHANCED_STATE_OPENED,
209 MLX5_MPW_STATE_CLOSED,
212 /* MPW session descriptor. */
214 enum mlx5_mpw_state state;
217 unsigned int total_len;
218 volatile struct mlx5_wqe *wqe;
220 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
221 volatile uint8_t *raw;
225 /* WQE for Multi-Packet RQ. */
226 struct mlx5_wqe_mprq {
227 struct mlx5_wqe_srq_next_seg next_seg;
228 struct mlx5_wqe_data_seg dseg;
231 #define MLX5_MPRQ_LEN_MASK 0x000ffff
232 #define MLX5_MPRQ_LEN_SHIFT 0
233 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
234 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
235 #define MLX5_MPRQ_FILLER_MASK 0x80000000
236 #define MLX5_MPRQ_FILLER_SHIFT 31
238 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
240 /* CQ element structure - should be equal to the cache line size */
242 #if (RTE_CACHE_LINE_SIZE == 128)
249 uint32_t rx_hash_res;
250 uint8_t rx_hash_type;
252 uint16_t hdr_type_etc;
257 uint32_t sop_drop_qpn;
258 uint16_t wqe_counter;
263 /* Adding direct verbs to data-path. */
265 /* CQ sequence number mask. */
266 #define MLX5_CQ_SQN_MASK 0x3
268 /* CQ sequence number index. */
269 #define MLX5_CQ_SQN_OFFSET 28
271 /* CQ doorbell index mask. */
272 #define MLX5_CI_MASK 0xffffff
274 /* CQ doorbell offset. */
275 #define MLX5_CQ_ARM_DB 1
277 /* CQ doorbell offset*/
278 #define MLX5_CQ_DOORBELL 0x20
280 /* CQE format value. */
281 #define MLX5_COMPRESSED 0x3
283 /* The field of packet to be modified. */
284 enum mlx5_modificaiton_field {
285 MLX5_MODI_OUT_SMAC_47_16 = 1,
286 MLX5_MODI_OUT_SMAC_15_0,
287 MLX5_MODI_OUT_ETHERTYPE,
288 MLX5_MODI_OUT_DMAC_47_16,
289 MLX5_MODI_OUT_DMAC_15_0,
290 MLX5_MODI_OUT_IP_DSCP,
291 MLX5_MODI_OUT_TCP_FLAGS,
292 MLX5_MODI_OUT_TCP_SPORT,
293 MLX5_MODI_OUT_TCP_DPORT,
294 MLX5_MODI_OUT_IPV4_TTL,
295 MLX5_MODI_OUT_UDP_SPORT,
296 MLX5_MODI_OUT_UDP_DPORT,
297 MLX5_MODI_OUT_SIPV6_127_96,
298 MLX5_MODI_OUT_SIPV6_95_64,
299 MLX5_MODI_OUT_SIPV6_63_32,
300 MLX5_MODI_OUT_SIPV6_31_0,
301 MLX5_MODI_OUT_DIPV6_127_96,
302 MLX5_MODI_OUT_DIPV6_95_64,
303 MLX5_MODI_OUT_DIPV6_63_32,
304 MLX5_MODI_OUT_DIPV6_31_0,
307 MLX5_MODI_IN_SMAC_47_16 = 0x31,
308 MLX5_MODI_IN_SMAC_15_0,
309 MLX5_MODI_IN_ETHERTYPE,
310 MLX5_MODI_IN_DMAC_47_16,
311 MLX5_MODI_IN_DMAC_15_0,
312 MLX5_MODI_IN_IP_DSCP,
313 MLX5_MODI_IN_TCP_FLAGS,
314 MLX5_MODI_IN_TCP_SPORT,
315 MLX5_MODI_IN_TCP_DPORT,
316 MLX5_MODI_IN_IPV4_TTL,
317 MLX5_MODI_IN_UDP_SPORT,
318 MLX5_MODI_IN_UDP_DPORT,
319 MLX5_MODI_IN_SIPV6_127_96,
320 MLX5_MODI_IN_SIPV6_95_64,
321 MLX5_MODI_IN_SIPV6_63_32,
322 MLX5_MODI_IN_SIPV6_31_0,
323 MLX5_MODI_IN_DIPV6_127_96,
324 MLX5_MODI_IN_DIPV6_95_64,
325 MLX5_MODI_IN_DIPV6_63_32,
326 MLX5_MODI_IN_DIPV6_31_0,
329 MLX5_MODI_OUT_IPV6_HOPLIMIT,
330 MLX5_MODI_IN_IPV6_HOPLIMIT,
331 MLX5_MODI_META_DATA_REG_A,
332 MLX5_MODI_META_DATA_REG_B = 0x50,
335 /* Modification sub command. */
336 struct mlx5_modification_cmd {
341 unsigned int rsvd0:3;
342 unsigned int src_offset:5; /* Start bit offset. */
343 unsigned int rsvd1:3;
344 unsigned int src_field:12;
352 unsigned int rsvd2:8;
353 unsigned int dst_offset:8;
354 unsigned int dst_field:12;
355 unsigned int rsvd3:4;
360 typedef uint32_t u32;
361 typedef uint16_t u16;
364 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
365 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
366 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
367 (&(__mlx5_nullp(typ)->fld)))
368 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
369 (__mlx5_bit_off(typ, fld) & 0x1f))
370 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
371 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
372 __mlx5_dw_bit_off(typ, fld))
373 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
374 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
375 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
376 (__mlx5_bit_off(typ, fld) & 0xf))
377 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
378 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
379 #define MLX5_ST_SZ_DB(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
380 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
381 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
383 /* insert a value to a struct */
384 #define MLX5_SET(typ, p, fld, v) \
387 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
388 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
389 __mlx5_dw_off(typ, fld))) & \
390 (~__mlx5_dw_mask(typ, fld))) | \
391 (((_v) & __mlx5_mask(typ, fld)) << \
392 __mlx5_dw_bit_off(typ, fld))); \
394 #define MLX5_GET16(typ, p, fld) \
395 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
396 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
397 __mlx5_mask16(typ, fld))
398 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
400 struct mlx5_ifc_fte_match_set_misc_bits {
401 u8 reserved_at_0[0x8];
403 u8 reserved_at_20[0x10];
404 u8 source_port[0x10];
405 u8 outer_second_prio[0x3];
406 u8 outer_second_cfi[0x1];
407 u8 outer_second_vid[0xc];
408 u8 inner_second_prio[0x3];
409 u8 inner_second_cfi[0x1];
410 u8 inner_second_vid[0xc];
411 u8 outer_second_cvlan_tag[0x1];
412 u8 inner_second_cvlan_tag[0x1];
413 u8 outer_second_svlan_tag[0x1];
414 u8 inner_second_svlan_tag[0x1];
415 u8 reserved_at_64[0xc];
416 u8 gre_protocol[0x10];
420 u8 reserved_at_b8[0x8];
421 u8 reserved_at_c0[0x20];
422 u8 reserved_at_e0[0xc];
423 u8 outer_ipv6_flow_label[0x14];
424 u8 reserved_at_100[0xc];
425 u8 inner_ipv6_flow_label[0x14];
426 u8 reserved_at_120[0xe0];
429 struct mlx5_ifc_ipv4_layout_bits {
430 u8 reserved_at_0[0x60];
434 struct mlx5_ifc_ipv6_layout_bits {
438 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
439 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
440 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
441 u8 reserved_at_0[0x80];
444 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
463 u8 reserved_at_c0[0x20];
466 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
467 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
470 struct mlx5_ifc_fte_match_mpls_bits {
477 struct mlx5_ifc_fte_match_set_misc2_bits {
478 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
479 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
480 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
481 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
482 u8 reserved_at_80[0x100];
483 u8 metadata_reg_a[0x20];
484 u8 reserved_at_1a0[0x60];
488 struct mlx5_ifc_fte_match_param_bits {
489 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
490 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
491 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
492 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
493 u8 reserved_at_800[0x800];
497 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
498 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
499 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
500 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT
503 /* CQE format mask. */
504 #define MLX5E_CQE_FORMAT_MASK 0xc
507 #define MLX5_OPC_MOD_MPW 0x01
509 /* Compressed Rx CQE structure. */
510 struct mlx5_mini_cqe8 {
512 uint32_t rx_hash_result;
518 uint16_t wqe_counter;
519 uint8_t s_wqe_opcode;
527 * Convert a user mark to flow mark.
530 * Mark value to convert.
533 * Converted mark value.
535 static inline uint32_t
536 mlx5_flow_mark_set(uint32_t val)
541 * Add one to the user value to differentiate un-marked flows from
542 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
545 if (val != MLX5_FLOW_MARK_DEFAULT)
547 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
549 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
550 * word, byte-swapped by the kernel on little-endian systems. In this
551 * case, left-shifting the resulting big-endian value ensures the
552 * least significant 24 bits are retained when converting it back.
554 ret = rte_cpu_to_be_32(val) >> 8;
562 * Convert a mark to user mark.
565 * Mark value to convert.
568 * Converted mark value.
570 static inline uint32_t
571 mlx5_flow_mark_get(uint32_t val)
574 * Subtract one from the retrieved value. It was added by
575 * mlx5_flow_mark_set() to distinguish unmarked flows.
577 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
578 return (val >> 8) - 1;
584 #endif /* RTE_PMD_MLX5_PRM_H_ */