1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* WQE Segment sizes in bytes. */
43 #define MLX5_WSEG_SIZE 16u
44 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
45 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
46 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
48 /* WQE/WQEBB size in bytes. */
49 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
52 * Max size of a WQE session.
53 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
54 * the WQE size field in Control Segment is 6 bits wide.
56 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
59 * Default minimum number of Tx queues for inlining packets.
60 * If there are less queues as specified we assume we have
61 * no enough CPU resources (cycles) to perform inlining,
62 * the PCIe throughput is not supposed as bottleneck and
63 * inlining is disabled.
65 #define MLX5_INLINE_MAX_TXQS 8u
66 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
69 * Default packet length threshold to be inlined with
70 * enhanced MPW. If packet length exceeds the threshold
71 * the data are not inlined. Should be aligned in WQEBB
72 * boundary with accounting the title Control and Ethernet
75 #define MLX5_EMPW_DEF_INLINE_LEN (3U * MLX5_WQE_SIZE + \
76 MLX5_DSEG_MIN_INLINE_SIZE - \
79 * Maximal inline data length sent with enhanced MPW.
80 * Is based on maximal WQE size.
82 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
83 MLX5_WQE_CSEG_SIZE - \
84 MLX5_WQE_ESEG_SIZE - \
85 MLX5_WQE_DSEG_SIZE + \
86 MLX5_DSEG_MIN_INLINE_SIZE)
88 * Minimal amount of packets to be sent with EMPW.
89 * This limits the minimal required size of sent EMPW.
90 * If there are no enough resources to built minimal
91 * EMPW the sending loop exits.
93 #define MLX5_EMPW_MIN_PACKETS (2 + 3 * 4)
94 #define MLX5_EMPW_MAX_PACKETS ((MLX5_WQE_SIZE_MAX - \
95 MLX5_WQE_CSEG_SIZE - \
96 MLX5_WQE_ESEG_SIZE) / \
99 * Default packet length threshold to be inlined with
100 * ordinary SEND. Inlining saves the MR key search
101 * and extra PCIe data fetch transaction, but eats the
104 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
105 MLX5_ESEG_MIN_INLINE_SIZE - \
106 MLX5_WQE_CSEG_SIZE - \
107 MLX5_WQE_ESEG_SIZE - \
110 * Maximal inline data length sent with ordinary SEND.
111 * Is based on maximal WQE size.
113 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
114 MLX5_WQE_CSEG_SIZE - \
115 MLX5_WQE_ESEG_SIZE - \
116 MLX5_WQE_DSEG_SIZE + \
117 MLX5_ESEG_MIN_INLINE_SIZE)
119 /* Missed in mlv5dv.h, should define here. */
120 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
122 /* CQE value to inform that VLAN is stripped. */
123 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
126 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
129 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
132 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
135 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
138 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
140 /* IP is fragmented. */
141 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
143 /* L2 header is valid. */
144 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
146 /* L3 header is valid. */
147 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
149 /* L4 header is valid. */
150 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
152 /* Outer packet, 0 IPv4, 1 IPv6. */
153 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
155 /* Tunnel packet bit in the CQE. */
156 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
158 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
159 #define MLX5_CQE_LRO_PUSH_MASK 0x40
161 /* Mask for L4 type in the CQE hdr_type_etc field. */
162 #define MLX5_CQE_L4_TYPE_MASK 0x70
164 /* The bit index of L4 type in CQE hdr_type_etc field. */
165 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
167 /* L4 type to indicate TCP packet without acknowledgment. */
168 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
170 /* L4 type to indicate TCP packet with acknowledgment. */
171 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
173 /* Inner L3 checksum offload (Tunneled packets only). */
174 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
176 /* Inner L4 checksum offload (Tunneled packets only). */
177 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
179 /* Outer L4 type is TCP. */
180 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
182 /* Outer L4 type is UDP. */
183 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
185 /* Outer L3 type is IPV4. */
186 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
188 /* Outer L3 type is IPV6. */
189 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
191 /* Inner L4 type is TCP. */
192 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
194 /* Inner L4 type is UDP. */
195 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
197 /* Inner L3 type is IPV4. */
198 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
200 /* Inner L3 type is IPV6. */
201 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
203 /* VLAN insertion flag. */
204 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
206 /* Data inline segment flag. */
207 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
209 /* Is flow mark valid. */
210 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
211 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
213 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
216 /* INVALID is used by packets matching no flow rules. */
217 #define MLX5_FLOW_MARK_INVALID 0
219 /* Maximum allowed value to mark a packet. */
220 #define MLX5_FLOW_MARK_MAX 0xfffff0
222 /* Default mark value used when none is provided. */
223 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
225 /* Maximum number of DS in WQE. Limited by 6-bit field. */
226 #define MLX5_DSEG_MAX 63
228 /* The completion mode offset in the WQE control segment line 2. */
229 #define MLX5_COMP_MODE_OFFSET 2
231 /* Amount of data bytes in minimal inline data segment. */
232 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
234 /* Amount of data bytes in minimal inline eth segment. */
235 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
237 /* Amount of data bytes after eth data segment. */
238 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
240 /* The maximum log value of segments per RQ WQE. */
241 #define MLX5_MAX_LOG_RQ_SEGS 5u
243 /* Completion mode. */
244 enum mlx5_completion_mode {
245 MLX5_COMP_ONLY_ERR = 0x0,
246 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
247 MLX5_COMP_ALWAYS = 0x2,
248 MLX5_COMP_CQE_AND_EQE = 0x3,
255 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
258 /* WQE Control segment. */
259 struct mlx5_wqe_cseg {
264 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
266 /* Header of data segment. Minimal size Data Segment */
267 struct mlx5_wqe_dseg {
270 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
278 /* Subset of struct WQE Ethernet Segment. */
279 struct mlx5_wqe_eseg {
287 uint16_t inline_hdr_sz;
289 uint16_t inline_data;
296 uint32_t flow_metadata;
302 /* The title WQEBB, header of WQE. */
305 struct mlx5_wqe_cseg cseg;
308 struct mlx5_wqe_eseg eseg;
310 struct mlx5_wqe_dseg dseg[2];
311 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
315 /* WQE for Multi-Packet RQ. */
316 struct mlx5_wqe_mprq {
317 struct mlx5_wqe_srq_next_seg next_seg;
318 struct mlx5_wqe_data_seg dseg;
321 #define MLX5_MPRQ_LEN_MASK 0x000ffff
322 #define MLX5_MPRQ_LEN_SHIFT 0
323 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
324 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
325 #define MLX5_MPRQ_FILLER_MASK 0x80000000
326 #define MLX5_MPRQ_FILLER_SHIFT 31
328 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
330 /* CQ element structure - should be equal to the cache line size */
332 #if (RTE_CACHE_LINE_SIZE == 128)
338 uint8_t lro_tcppsh_abort_dupack;
340 uint16_t lro_tcp_win;
341 uint32_t lro_ack_seq_num;
342 uint32_t rx_hash_res;
343 uint8_t rx_hash_type;
347 uint16_t hdr_type_etc;
353 uint32_t sop_drop_qpn;
354 uint16_t wqe_counter;
359 /* Adding direct verbs to data-path. */
361 /* CQ sequence number mask. */
362 #define MLX5_CQ_SQN_MASK 0x3
364 /* CQ sequence number index. */
365 #define MLX5_CQ_SQN_OFFSET 28
367 /* CQ doorbell index mask. */
368 #define MLX5_CI_MASK 0xffffff
370 /* CQ doorbell offset. */
371 #define MLX5_CQ_ARM_DB 1
373 /* CQ doorbell offset*/
374 #define MLX5_CQ_DOORBELL 0x20
376 /* CQE format value. */
377 #define MLX5_COMPRESSED 0x3
379 /* Write a specific data value to a field. */
380 #define MLX5_MODIFICATION_TYPE_SET 1
382 /* Add a specific data value to a field. */
383 #define MLX5_MODIFICATION_TYPE_ADD 2
385 /* The field of packet to be modified. */
386 enum mlx5_modification_field {
387 MLX5_MODI_OUT_SMAC_47_16 = 1,
388 MLX5_MODI_OUT_SMAC_15_0,
389 MLX5_MODI_OUT_ETHERTYPE,
390 MLX5_MODI_OUT_DMAC_47_16,
391 MLX5_MODI_OUT_DMAC_15_0,
392 MLX5_MODI_OUT_IP_DSCP,
393 MLX5_MODI_OUT_TCP_FLAGS,
394 MLX5_MODI_OUT_TCP_SPORT,
395 MLX5_MODI_OUT_TCP_DPORT,
396 MLX5_MODI_OUT_IPV4_TTL,
397 MLX5_MODI_OUT_UDP_SPORT,
398 MLX5_MODI_OUT_UDP_DPORT,
399 MLX5_MODI_OUT_SIPV6_127_96,
400 MLX5_MODI_OUT_SIPV6_95_64,
401 MLX5_MODI_OUT_SIPV6_63_32,
402 MLX5_MODI_OUT_SIPV6_31_0,
403 MLX5_MODI_OUT_DIPV6_127_96,
404 MLX5_MODI_OUT_DIPV6_95_64,
405 MLX5_MODI_OUT_DIPV6_63_32,
406 MLX5_MODI_OUT_DIPV6_31_0,
409 MLX5_MODI_IN_SMAC_47_16 = 0x31,
410 MLX5_MODI_IN_SMAC_15_0,
411 MLX5_MODI_IN_ETHERTYPE,
412 MLX5_MODI_IN_DMAC_47_16,
413 MLX5_MODI_IN_DMAC_15_0,
414 MLX5_MODI_IN_IP_DSCP,
415 MLX5_MODI_IN_TCP_FLAGS,
416 MLX5_MODI_IN_TCP_SPORT,
417 MLX5_MODI_IN_TCP_DPORT,
418 MLX5_MODI_IN_IPV4_TTL,
419 MLX5_MODI_IN_UDP_SPORT,
420 MLX5_MODI_IN_UDP_DPORT,
421 MLX5_MODI_IN_SIPV6_127_96,
422 MLX5_MODI_IN_SIPV6_95_64,
423 MLX5_MODI_IN_SIPV6_63_32,
424 MLX5_MODI_IN_SIPV6_31_0,
425 MLX5_MODI_IN_DIPV6_127_96,
426 MLX5_MODI_IN_DIPV6_95_64,
427 MLX5_MODI_IN_DIPV6_63_32,
428 MLX5_MODI_IN_DIPV6_31_0,
431 MLX5_MODI_OUT_IPV6_HOPLIMIT,
432 MLX5_MODI_IN_IPV6_HOPLIMIT,
433 MLX5_MODI_META_DATA_REG_A,
434 MLX5_MODI_META_DATA_REG_B = 0x50,
435 MLX5_MODI_META_REG_C_0,
436 MLX5_MODI_META_REG_C_1,
437 MLX5_MODI_META_REG_C_2,
438 MLX5_MODI_META_REG_C_3,
439 MLX5_MODI_META_REG_C_4,
440 MLX5_MODI_META_REG_C_5,
441 MLX5_MODI_META_REG_C_6,
442 MLX5_MODI_META_REG_C_7,
443 MLX5_MODI_OUT_TCP_SEQ_NUM,
444 MLX5_MODI_IN_TCP_SEQ_NUM,
445 MLX5_MODI_OUT_TCP_ACK_NUM,
446 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
449 /* Modification sub command. */
450 struct mlx5_modification_cmd {
454 unsigned int length:5;
455 unsigned int rsvd0:3;
456 unsigned int offset:5;
457 unsigned int rsvd1:3;
458 unsigned int field:12;
459 unsigned int action_type:4;
468 typedef uint32_t u32;
469 typedef uint16_t u16;
472 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
473 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
474 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
475 (&(__mlx5_nullp(typ)->fld)))
476 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
477 (__mlx5_bit_off(typ, fld) & 0x1f))
478 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
479 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
480 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
481 __mlx5_dw_bit_off(typ, fld))
482 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
483 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
484 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
485 (__mlx5_bit_off(typ, fld) & 0xf))
486 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
487 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
488 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
489 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
490 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
492 /* insert a value to a struct */
493 #define MLX5_SET(typ, p, fld, v) \
496 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
497 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
498 __mlx5_dw_off(typ, fld))) & \
499 (~__mlx5_dw_mask(typ, fld))) | \
500 (((_v) & __mlx5_mask(typ, fld)) << \
501 __mlx5_dw_bit_off(typ, fld))); \
504 #define MLX5_SET64(typ, p, fld, v) \
506 assert(__mlx5_bit_sz(typ, fld) == 64); \
507 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
508 rte_cpu_to_be_64(v); \
511 #define MLX5_GET(typ, p, fld) \
512 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
513 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
514 __mlx5_mask(typ, fld))
515 #define MLX5_GET16(typ, p, fld) \
516 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
517 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
518 __mlx5_mask16(typ, fld))
519 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
520 __mlx5_64_off(typ, fld)))
521 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
523 struct mlx5_ifc_fte_match_set_misc_bits {
524 u8 gre_c_present[0x1];
525 u8 reserved_at_1[0x1];
526 u8 gre_k_present[0x1];
527 u8 gre_s_present[0x1];
528 u8 source_vhci_port[0x4];
530 u8 reserved_at_20[0x10];
531 u8 source_port[0x10];
532 u8 outer_second_prio[0x3];
533 u8 outer_second_cfi[0x1];
534 u8 outer_second_vid[0xc];
535 u8 inner_second_prio[0x3];
536 u8 inner_second_cfi[0x1];
537 u8 inner_second_vid[0xc];
538 u8 outer_second_cvlan_tag[0x1];
539 u8 inner_second_cvlan_tag[0x1];
540 u8 outer_second_svlan_tag[0x1];
541 u8 inner_second_svlan_tag[0x1];
542 u8 reserved_at_64[0xc];
543 u8 gre_protocol[0x10];
547 u8 reserved_at_b8[0x8];
548 u8 reserved_at_c0[0x20];
549 u8 reserved_at_e0[0xc];
550 u8 outer_ipv6_flow_label[0x14];
551 u8 reserved_at_100[0xc];
552 u8 inner_ipv6_flow_label[0x14];
553 u8 reserved_at_120[0xe0];
556 struct mlx5_ifc_ipv4_layout_bits {
557 u8 reserved_at_0[0x60];
561 struct mlx5_ifc_ipv6_layout_bits {
565 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
566 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
567 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
568 u8 reserved_at_0[0x80];
571 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
590 u8 reserved_at_c0[0x20];
593 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
594 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
597 struct mlx5_ifc_fte_match_mpls_bits {
604 struct mlx5_ifc_fte_match_set_misc2_bits {
605 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
606 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
607 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
608 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
609 u8 reserved_at_80[0x100];
610 u8 metadata_reg_a[0x20];
611 u8 reserved_at_1a0[0x60];
614 struct mlx5_ifc_fte_match_set_misc3_bits {
615 u8 inner_tcp_seq_num[0x20];
616 u8 outer_tcp_seq_num[0x20];
617 u8 inner_tcp_ack_num[0x20];
618 u8 outer_tcp_ack_num[0x20];
619 u8 reserved_at_auto1[0x8];
620 u8 outer_vxlan_gpe_vni[0x18];
621 u8 outer_vxlan_gpe_next_protocol[0x8];
622 u8 outer_vxlan_gpe_flags[0x8];
623 u8 reserved_at_a8[0x10];
624 u8 icmp_header_data[0x20];
625 u8 icmpv6_header_data[0x20];
630 u8 reserved_at_1a0[0xe0];
634 struct mlx5_ifc_fte_match_param_bits {
635 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
636 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
637 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
638 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
639 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
643 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
644 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
645 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
646 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
647 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
651 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
652 MLX5_CMD_OP_CREATE_MKEY = 0x200,
653 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
654 MLX5_CMD_OP_CREATE_TIR = 0x900,
655 MLX5_CMD_OP_CREATE_RQ = 0x908,
656 MLX5_CMD_OP_MODIFY_RQ = 0x909,
657 MLX5_CMD_OP_QUERY_TIS = 0x915,
658 MLX5_CMD_OP_CREATE_RQT = 0x916,
659 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
660 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
664 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
668 struct mlx5_ifc_alloc_flow_counter_out_bits {
670 u8 reserved_at_8[0x18];
672 u8 flow_counter_id[0x20];
673 u8 reserved_at_60[0x20];
676 struct mlx5_ifc_alloc_flow_counter_in_bits {
678 u8 reserved_at_10[0x10];
679 u8 reserved_at_20[0x10];
681 u8 flow_counter_id[0x20];
682 u8 reserved_at_40[0x18];
683 u8 flow_counter_bulk[0x8];
686 struct mlx5_ifc_dealloc_flow_counter_out_bits {
688 u8 reserved_at_8[0x18];
690 u8 reserved_at_40[0x40];
693 struct mlx5_ifc_dealloc_flow_counter_in_bits {
695 u8 reserved_at_10[0x10];
696 u8 reserved_at_20[0x10];
698 u8 flow_counter_id[0x20];
699 u8 reserved_at_60[0x20];
702 struct mlx5_ifc_traffic_counter_bits {
707 struct mlx5_ifc_query_flow_counter_out_bits {
709 u8 reserved_at_8[0x18];
711 u8 reserved_at_40[0x40];
712 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
715 struct mlx5_ifc_query_flow_counter_in_bits {
717 u8 reserved_at_10[0x10];
718 u8 reserved_at_20[0x10];
720 u8 reserved_at_40[0x20];
724 u8 dump_to_memory[0x1];
725 u8 num_of_counters[0x1e];
726 u8 flow_counter_id[0x20];
729 struct mlx5_ifc_mkc_bits {
730 u8 reserved_at_0[0x1];
732 u8 reserved_at_2[0x1];
733 u8 access_mode_4_2[0x3];
734 u8 reserved_at_6[0x7];
735 u8 relaxed_ordering_write[0x1];
736 u8 reserved_at_e[0x1];
737 u8 small_fence_on_rdma_read_response[0x1];
744 u8 access_mode_1_0[0x2];
745 u8 reserved_at_18[0x8];
750 u8 reserved_at_40[0x20];
755 u8 reserved_at_63[0x2];
756 u8 expected_sigerr_count[0x1];
757 u8 reserved_at_66[0x1];
765 u8 bsf_octword_size[0x20];
767 u8 reserved_at_120[0x80];
769 u8 translations_octword_size[0x20];
771 u8 reserved_at_1c0[0x1b];
772 u8 log_page_size[0x5];
774 u8 reserved_at_1e0[0x20];
777 struct mlx5_ifc_create_mkey_out_bits {
779 u8 reserved_at_8[0x18];
783 u8 reserved_at_40[0x8];
786 u8 reserved_at_60[0x20];
789 struct mlx5_ifc_create_mkey_in_bits {
791 u8 reserved_at_10[0x10];
793 u8 reserved_at_20[0x10];
796 u8 reserved_at_40[0x20];
799 u8 reserved_at_61[0x1f];
801 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
803 u8 reserved_at_280[0x80];
805 u8 translations_octword_actual_size[0x20];
807 u8 mkey_umem_id[0x20];
809 u8 mkey_umem_offset[0x40];
811 u8 reserved_at_380[0x500];
813 u8 klm_pas_mtt[][0x20];
817 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
818 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
819 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
823 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
824 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
828 MLX5_CAP_INLINE_MODE_L2,
829 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
830 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
834 MLX5_INLINE_MODE_NONE,
837 MLX5_INLINE_MODE_TCP_UDP,
838 MLX5_INLINE_MODE_RESERVED4,
839 MLX5_INLINE_MODE_INNER_L2,
840 MLX5_INLINE_MODE_INNER_IP,
841 MLX5_INLINE_MODE_INNER_TCP_UDP,
844 struct mlx5_ifc_cmd_hca_cap_bits {
845 u8 reserved_at_0[0x30];
847 u8 reserved_at_40[0x40];
848 u8 log_max_srq_sz[0x8];
849 u8 log_max_qp_sz[0x8];
850 u8 reserved_at_90[0xb];
852 u8 reserved_at_a0[0xb];
854 u8 reserved_at_b0[0x10];
855 u8 reserved_at_c0[0x8];
856 u8 log_max_cq_sz[0x8];
857 u8 reserved_at_d0[0xb];
859 u8 log_max_eq_sz[0x8];
860 u8 reserved_at_e8[0x2];
861 u8 log_max_mkey[0x6];
862 u8 reserved_at_f0[0x8];
863 u8 dump_fill_mkey[0x1];
864 u8 reserved_at_f9[0x3];
866 u8 max_indirection[0x8];
867 u8 fixed_buffer_size[0x1];
868 u8 log_max_mrw_sz[0x7];
869 u8 force_teardown[0x1];
870 u8 reserved_at_111[0x1];
871 u8 log_max_bsf_list_size[0x6];
872 u8 umr_extended_translation_offset[0x1];
874 u8 log_max_klm_list_size[0x6];
875 u8 reserved_at_120[0xa];
876 u8 log_max_ra_req_dc[0x6];
877 u8 reserved_at_130[0xa];
878 u8 log_max_ra_res_dc[0x6];
879 u8 reserved_at_140[0xa];
880 u8 log_max_ra_req_qp[0x6];
881 u8 reserved_at_150[0xa];
882 u8 log_max_ra_res_qp[0x6];
884 u8 cc_query_allowed[0x1];
885 u8 cc_modify_allowed[0x1];
887 u8 cache_line_128byte[0x1];
888 u8 reserved_at_165[0xa];
890 u8 gid_table_size[0x10];
891 u8 out_of_seq_cnt[0x1];
892 u8 vport_counters[0x1];
893 u8 retransmission_q_counters[0x1];
895 u8 modify_rq_counter_set_id[0x1];
896 u8 rq_delay_drop[0x1];
898 u8 pkey_table_size[0x10];
899 u8 vport_group_manager[0x1];
900 u8 vhca_group_manager[0x1];
903 u8 vnic_env_queue_counters[0x1];
905 u8 nic_flow_table[0x1];
906 u8 eswitch_manager[0x1];
907 u8 device_memory[0x1];
910 u8 local_ca_ack_delay[0x5];
911 u8 port_module_event[0x1];
912 u8 enhanced_error_q_counters[0x1];
914 u8 reserved_at_1b3[0x1];
915 u8 disable_link_up[0x1];
919 u8 reserved_at_1c0[0x1];
923 u8 reserved_at_1c8[0x4];
925 u8 temp_warn_event[0x1];
927 u8 general_notification_event[0x1];
928 u8 reserved_at_1d3[0x2];
932 u8 reserved_at_1d8[0x1];
940 u8 stat_rate_support[0x10];
941 u8 reserved_at_1f0[0xc];
943 u8 compact_address_vector[0x1];
945 u8 reserved_at_202[0x1];
946 u8 ipoib_enhanced_offloads[0x1];
947 u8 ipoib_basic_offloads[0x1];
948 u8 reserved_at_205[0x1];
949 u8 repeated_block_disabled[0x1];
950 u8 umr_modify_entity_size_disabled[0x1];
951 u8 umr_modify_atomic_disabled[0x1];
952 u8 umr_indirect_mkey_disabled[0x1];
954 u8 reserved_at_20c[0x3];
955 u8 drain_sigerr[0x1];
956 u8 cmdif_checksum[0x2];
958 u8 reserved_at_213[0x1];
959 u8 wq_signature[0x1];
960 u8 sctr_data_cqe[0x1];
961 u8 reserved_at_216[0x1];
967 u8 eth_net_offloads[0x1];
970 u8 reserved_at_21f[0x1];
973 u8 cq_moderation[0x1];
974 u8 reserved_at_223[0x3];
978 u8 reserved_at_229[0x1];
979 u8 scqe_break_moderation[0x1];
980 u8 cq_period_start_from_cqe[0x1];
982 u8 reserved_at_22d[0x1];
985 u8 umr_ptr_rlky[0x1];
987 u8 reserved_at_232[0x4];
990 u8 set_deth_sqpn[0x1];
991 u8 reserved_at_239[0x3];
997 u8 reserved_at_241[0x9];
999 u8 reserved_at_250[0x8];
1002 u8 driver_version[0x1];
1003 u8 pad_tx_eth_packet[0x1];
1004 u8 reserved_at_263[0x8];
1005 u8 log_bf_reg_size[0x5];
1006 u8 reserved_at_270[0xb];
1008 u8 num_lag_ports[0x4];
1009 u8 reserved_at_280[0x10];
1010 u8 max_wqe_sz_sq[0x10];
1011 u8 reserved_at_2a0[0x10];
1012 u8 max_wqe_sz_rq[0x10];
1013 u8 max_flow_counter_31_16[0x10];
1014 u8 max_wqe_sz_sq_dc[0x10];
1015 u8 reserved_at_2e0[0x7];
1016 u8 max_qp_mcg[0x19];
1017 u8 reserved_at_300[0x10];
1018 u8 flow_counter_bulk_alloc[0x08];
1019 u8 log_max_mcg[0x8];
1020 u8 reserved_at_320[0x3];
1021 u8 log_max_transport_domain[0x5];
1022 u8 reserved_at_328[0x3];
1024 u8 reserved_at_330[0xb];
1025 u8 log_max_xrcd[0x5];
1026 u8 nic_receive_steering_discard[0x1];
1027 u8 receive_discard_vport_down[0x1];
1028 u8 transmit_discard_vport_down[0x1];
1029 u8 reserved_at_343[0x5];
1030 u8 log_max_flow_counter_bulk[0x8];
1031 u8 max_flow_counter_15_0[0x10];
1033 u8 flow_counters_dump[0x1];
1034 u8 reserved_at_360[0x1];
1036 u8 reserved_at_368[0x3];
1038 u8 reserved_at_370[0x3];
1039 u8 log_max_tir[0x5];
1040 u8 reserved_at_378[0x3];
1041 u8 log_max_tis[0x5];
1042 u8 basic_cyclic_rcv_wqe[0x1];
1043 u8 reserved_at_381[0x2];
1044 u8 log_max_rmp[0x5];
1045 u8 reserved_at_388[0x3];
1046 u8 log_max_rqt[0x5];
1047 u8 reserved_at_390[0x3];
1048 u8 log_max_rqt_size[0x5];
1049 u8 reserved_at_398[0x3];
1050 u8 log_max_tis_per_sq[0x5];
1051 u8 ext_stride_num_range[0x1];
1052 u8 reserved_at_3a1[0x2];
1053 u8 log_max_stride_sz_rq[0x5];
1054 u8 reserved_at_3a8[0x3];
1055 u8 log_min_stride_sz_rq[0x5];
1056 u8 reserved_at_3b0[0x3];
1057 u8 log_max_stride_sz_sq[0x5];
1058 u8 reserved_at_3b8[0x3];
1059 u8 log_min_stride_sz_sq[0x5];
1061 u8 reserved_at_3c1[0x2];
1062 u8 log_max_hairpin_queues[0x5];
1063 u8 reserved_at_3c8[0x3];
1064 u8 log_max_hairpin_wq_data_sz[0x5];
1065 u8 reserved_at_3d0[0x3];
1066 u8 log_max_hairpin_num_packets[0x5];
1067 u8 reserved_at_3d8[0x3];
1068 u8 log_max_wq_sz[0x5];
1069 u8 nic_vport_change_event[0x1];
1070 u8 disable_local_lb_uc[0x1];
1071 u8 disable_local_lb_mc[0x1];
1072 u8 log_min_hairpin_wq_data_sz[0x5];
1073 u8 reserved_at_3e8[0x3];
1074 u8 log_max_vlan_list[0x5];
1075 u8 reserved_at_3f0[0x3];
1076 u8 log_max_current_mc_list[0x5];
1077 u8 reserved_at_3f8[0x3];
1078 u8 log_max_current_uc_list[0x5];
1079 u8 general_obj_types[0x40];
1080 u8 reserved_at_440[0x20];
1081 u8 reserved_at_460[0x10];
1082 u8 max_num_eqs[0x10];
1083 u8 reserved_at_480[0x3];
1084 u8 log_max_l2_table[0x5];
1085 u8 reserved_at_488[0x8];
1086 u8 log_uar_page_sz[0x10];
1087 u8 reserved_at_4a0[0x20];
1088 u8 device_frequency_mhz[0x20];
1089 u8 device_frequency_khz[0x20];
1090 u8 reserved_at_500[0x20];
1091 u8 num_of_uars_per_page[0x20];
1092 u8 flex_parser_protocols[0x20];
1093 u8 reserved_at_560[0x20];
1094 u8 reserved_at_580[0x3c];
1095 u8 mini_cqe_resp_stride_index[0x1];
1096 u8 cqe_128_always[0x1];
1097 u8 cqe_compression_128[0x1];
1098 u8 cqe_compression[0x1];
1099 u8 cqe_compression_timeout[0x10];
1100 u8 cqe_compression_max_num[0x10];
1101 u8 reserved_at_5e0[0x10];
1102 u8 tag_matching[0x1];
1103 u8 rndv_offload_rc[0x1];
1104 u8 rndv_offload_dc[0x1];
1105 u8 log_tag_matching_list_sz[0x5];
1106 u8 reserved_at_5f8[0x3];
1107 u8 log_max_xrq[0x5];
1108 u8 affiliate_nic_vport_criteria[0x8];
1109 u8 native_port_num[0x8];
1110 u8 num_vhca_ports[0x8];
1111 u8 reserved_at_618[0x6];
1112 u8 sw_owner_id[0x1];
1113 u8 reserved_at_61f[0x1e1];
1116 struct mlx5_ifc_qos_cap_bits {
1117 u8 packet_pacing[0x1];
1118 u8 esw_scheduling[0x1];
1119 u8 esw_bw_share[0x1];
1120 u8 esw_rate_limit[0x1];
1121 u8 reserved_at_4[0x1];
1122 u8 packet_pacing_burst_bound[0x1];
1123 u8 packet_pacing_typical_size[0x1];
1124 u8 flow_meter_srtcm[0x1];
1125 u8 reserved_at_8[0x8];
1126 u8 log_max_flow_meter[0x8];
1127 u8 flow_meter_reg_id[0x8];
1128 u8 reserved_at_25[0x20];
1129 u8 packet_pacing_max_rate[0x20];
1130 u8 packet_pacing_min_rate[0x20];
1131 u8 reserved_at_80[0x10];
1132 u8 packet_pacing_rate_table_size[0x10];
1133 u8 esw_element_type[0x10];
1134 u8 esw_tsar_type[0x10];
1135 u8 reserved_at_c0[0x10];
1136 u8 max_qos_para_vport[0x10];
1137 u8 max_tsar_bw_share[0x20];
1138 u8 reserved_at_100[0x6e8];
1141 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1145 u8 lro_psh_flag[0x1];
1146 u8 lro_time_stamp[0x1];
1147 u8 lro_max_msg_sz_mode[0x2];
1148 u8 wqe_vlan_insert[0x1];
1149 u8 self_lb_en_modifiable[0x1];
1152 u8 max_lso_cap[0x5];
1153 u8 multi_pkt_send_wqe[0x2];
1154 u8 wqe_inline_mode[0x2];
1155 u8 rss_ind_tbl_cap[0x4];
1157 u8 scatter_fcs[0x1];
1158 u8 enhanced_multi_pkt_send_wqe[0x1];
1159 u8 tunnel_lso_const_out_ip_id[0x1];
1160 u8 tunnel_lro_gre[0x1];
1161 u8 tunnel_lro_vxlan[0x1];
1162 u8 tunnel_stateless_gre[0x1];
1163 u8 tunnel_stateless_vxlan[0x1];
1167 u8 reserved_at_23[0xd];
1168 u8 max_vxlan_udp_ports[0x8];
1169 u8 reserved_at_38[0x6];
1170 u8 max_geneve_opt_len[0x1];
1171 u8 tunnel_stateless_geneve_rx[0x1];
1172 u8 reserved_at_40[0x10];
1173 u8 lro_min_mss_size[0x10];
1174 u8 reserved_at_60[0x120];
1175 u8 lro_timer_supported_periods[4][0x20];
1176 u8 reserved_at_200[0x600];
1179 union mlx5_ifc_hca_cap_union_bits {
1180 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1181 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1182 per_protocol_networking_offload_caps;
1183 struct mlx5_ifc_qos_cap_bits qos_cap;
1184 u8 reserved_at_0[0x8000];
1187 struct mlx5_ifc_query_hca_cap_out_bits {
1189 u8 reserved_at_8[0x18];
1191 u8 reserved_at_40[0x40];
1192 union mlx5_ifc_hca_cap_union_bits capability;
1195 struct mlx5_ifc_query_hca_cap_in_bits {
1197 u8 reserved_at_10[0x10];
1198 u8 reserved_at_20[0x10];
1200 u8 reserved_at_40[0x40];
1203 struct mlx5_ifc_mac_address_layout_bits {
1204 u8 reserved_at_0[0x10];
1205 u8 mac_addr_47_32[0x10];
1206 u8 mac_addr_31_0[0x20];
1209 struct mlx5_ifc_nic_vport_context_bits {
1210 u8 reserved_at_0[0x5];
1211 u8 min_wqe_inline_mode[0x3];
1212 u8 reserved_at_8[0x15];
1213 u8 disable_mc_local_lb[0x1];
1214 u8 disable_uc_local_lb[0x1];
1216 u8 arm_change_event[0x1];
1217 u8 reserved_at_21[0x1a];
1218 u8 event_on_mtu[0x1];
1219 u8 event_on_promisc_change[0x1];
1220 u8 event_on_vlan_change[0x1];
1221 u8 event_on_mc_address_change[0x1];
1222 u8 event_on_uc_address_change[0x1];
1223 u8 reserved_at_40[0xc];
1224 u8 affiliation_criteria[0x4];
1225 u8 affiliated_vhca_id[0x10];
1226 u8 reserved_at_60[0xd0];
1228 u8 system_image_guid[0x40];
1231 u8 reserved_at_200[0x140];
1232 u8 qkey_violation_counter[0x10];
1233 u8 reserved_at_350[0x430];
1236 u8 promisc_all[0x1];
1237 u8 reserved_at_783[0x2];
1238 u8 allowed_list_type[0x3];
1239 u8 reserved_at_788[0xc];
1240 u8 allowed_list_size[0xc];
1241 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1242 u8 reserved_at_7e0[0x20];
1245 struct mlx5_ifc_query_nic_vport_context_out_bits {
1247 u8 reserved_at_8[0x18];
1249 u8 reserved_at_40[0x40];
1250 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1253 struct mlx5_ifc_query_nic_vport_context_in_bits {
1255 u8 reserved_at_10[0x10];
1256 u8 reserved_at_20[0x10];
1258 u8 other_vport[0x1];
1259 u8 reserved_at_41[0xf];
1260 u8 vport_number[0x10];
1261 u8 reserved_at_60[0x5];
1262 u8 allowed_list_type[0x3];
1263 u8 reserved_at_68[0x18];
1266 struct mlx5_ifc_tisc_bits {
1267 u8 strict_lag_tx_port_affinity[0x1];
1268 u8 reserved_at_1[0x3];
1269 u8 lag_tx_port_affinity[0x04];
1270 u8 reserved_at_8[0x4];
1272 u8 reserved_at_10[0x10];
1273 u8 reserved_at_20[0x100];
1274 u8 reserved_at_120[0x8];
1275 u8 transport_domain[0x18];
1276 u8 reserved_at_140[0x8];
1277 u8 underlay_qpn[0x18];
1278 u8 reserved_at_160[0x3a0];
1281 struct mlx5_ifc_query_tis_out_bits {
1283 u8 reserved_at_8[0x18];
1285 u8 reserved_at_40[0x40];
1286 struct mlx5_ifc_tisc_bits tis_context;
1289 struct mlx5_ifc_query_tis_in_bits {
1291 u8 reserved_at_10[0x10];
1292 u8 reserved_at_20[0x10];
1294 u8 reserved_at_40[0x8];
1296 u8 reserved_at_60[0x20];
1300 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1301 MLX5_WQ_TYPE_CYCLIC = 0x1,
1302 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1303 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1307 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1308 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1311 struct mlx5_ifc_wq_bits {
1313 u8 wq_signature[0x1];
1314 u8 end_padding_mode[0x2];
1316 u8 reserved_at_8[0x18];
1317 u8 hds_skip_first_sge[0x1];
1318 u8 log2_hds_buf_size[0x3];
1319 u8 reserved_at_24[0x7];
1320 u8 page_offset[0x5];
1322 u8 reserved_at_40[0x8];
1324 u8 reserved_at_60[0x8];
1327 u8 hw_counter[0x20];
1328 u8 sw_counter[0x20];
1329 u8 reserved_at_100[0xc];
1330 u8 log_wq_stride[0x4];
1331 u8 reserved_at_110[0x3];
1332 u8 log_wq_pg_sz[0x5];
1333 u8 reserved_at_118[0x3];
1335 u8 dbr_umem_valid[0x1];
1336 u8 wq_umem_valid[0x1];
1337 u8 reserved_at_122[0x1];
1338 u8 log_hairpin_num_packets[0x5];
1339 u8 reserved_at_128[0x3];
1340 u8 log_hairpin_data_sz[0x5];
1341 u8 reserved_at_130[0x4];
1342 u8 single_wqe_log_num_of_strides[0x4];
1343 u8 two_byte_shift_en[0x1];
1344 u8 reserved_at_139[0x4];
1345 u8 single_stride_log_num_of_bytes[0x3];
1346 u8 dbr_umem_id[0x20];
1347 u8 wq_umem_id[0x20];
1348 u8 wq_umem_offset[0x40];
1349 u8 reserved_at_1c0[0x440];
1353 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1354 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1358 MLX5_RQC_STATE_RST = 0x0,
1359 MLX5_RQC_STATE_RDY = 0x1,
1360 MLX5_RQC_STATE_ERR = 0x3,
1363 struct mlx5_ifc_rqc_bits {
1365 u8 delay_drop_en[0x1];
1366 u8 scatter_fcs[0x1];
1368 u8 mem_rq_type[0x4];
1370 u8 reserved_at_c[0x1];
1371 u8 flush_in_error_en[0x1];
1373 u8 reserved_at_f[0x11];
1374 u8 reserved_at_20[0x8];
1375 u8 user_index[0x18];
1376 u8 reserved_at_40[0x8];
1378 u8 counter_set_id[0x8];
1379 u8 reserved_at_68[0x18];
1380 u8 reserved_at_80[0x8];
1382 u8 reserved_at_a0[0x8];
1383 u8 hairpin_peer_sq[0x18];
1384 u8 reserved_at_c0[0x10];
1385 u8 hairpin_peer_vhca[0x10];
1386 u8 reserved_at_e0[0xa0];
1387 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1390 struct mlx5_ifc_create_rq_out_bits {
1392 u8 reserved_at_8[0x18];
1394 u8 reserved_at_40[0x8];
1396 u8 reserved_at_60[0x20];
1399 struct mlx5_ifc_create_rq_in_bits {
1402 u8 reserved_at_20[0x10];
1404 u8 reserved_at_40[0xc0];
1405 struct mlx5_ifc_rqc_bits ctx;
1408 struct mlx5_ifc_modify_rq_out_bits {
1410 u8 reserved_at_8[0x18];
1412 u8 reserved_at_40[0x40];
1416 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1417 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1418 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1419 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1422 struct mlx5_ifc_modify_rq_in_bits {
1425 u8 reserved_at_20[0x10];
1428 u8 reserved_at_44[0x4];
1430 u8 reserved_at_60[0x20];
1431 u8 modify_bitmask[0x40];
1432 u8 reserved_at_c0[0x40];
1433 struct mlx5_ifc_rqc_bits ctx;
1437 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1438 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1439 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1440 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1441 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1444 struct mlx5_ifc_rx_hash_field_select_bits {
1445 u8 l3_prot_type[0x1];
1446 u8 l4_prot_type[0x1];
1447 u8 selected_fields[0x1e];
1451 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1452 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1456 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1457 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1461 MLX5_RX_HASH_FN_NONE = 0x0,
1462 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1463 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1467 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1468 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1472 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1473 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1476 struct mlx5_ifc_tirc_bits {
1477 u8 reserved_at_0[0x20];
1479 u8 reserved_at_24[0x1c];
1480 u8 reserved_at_40[0x40];
1481 u8 reserved_at_80[0x4];
1482 u8 lro_timeout_period_usecs[0x10];
1483 u8 lro_enable_mask[0x4];
1484 u8 lro_max_msg_sz[0x8];
1485 u8 reserved_at_a0[0x40];
1486 u8 reserved_at_e0[0x8];
1487 u8 inline_rqn[0x18];
1488 u8 rx_hash_symmetric[0x1];
1489 u8 reserved_at_101[0x1];
1490 u8 tunneled_offload_en[0x1];
1491 u8 reserved_at_103[0x5];
1492 u8 indirect_table[0x18];
1494 u8 reserved_at_124[0x2];
1495 u8 self_lb_block[0x2];
1496 u8 transport_domain[0x18];
1497 u8 rx_hash_toeplitz_key[10][0x20];
1498 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1499 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1500 u8 reserved_at_2c0[0x4c0];
1503 struct mlx5_ifc_create_tir_out_bits {
1505 u8 reserved_at_8[0x18];
1507 u8 reserved_at_40[0x8];
1509 u8 reserved_at_60[0x20];
1512 struct mlx5_ifc_create_tir_in_bits {
1515 u8 reserved_at_20[0x10];
1517 u8 reserved_at_40[0xc0];
1518 struct mlx5_ifc_tirc_bits ctx;
1521 struct mlx5_ifc_rq_num_bits {
1522 u8 reserved_at_0[0x8];
1526 struct mlx5_ifc_rqtc_bits {
1527 u8 reserved_at_0[0xa0];
1528 u8 reserved_at_a0[0x10];
1529 u8 rqt_max_size[0x10];
1530 u8 reserved_at_c0[0x10];
1531 u8 rqt_actual_size[0x10];
1532 u8 reserved_at_e0[0x6a0];
1533 struct mlx5_ifc_rq_num_bits rq_num[];
1536 struct mlx5_ifc_create_rqt_out_bits {
1538 u8 reserved_at_8[0x18];
1540 u8 reserved_at_40[0x8];
1542 u8 reserved_at_60[0x20];
1546 #pragma GCC diagnostic ignored "-Wpedantic"
1548 struct mlx5_ifc_create_rqt_in_bits {
1551 u8 reserved_at_20[0x10];
1553 u8 reserved_at_40[0xc0];
1554 struct mlx5_ifc_rqtc_bits rqt_context;
1557 #pragma GCC diagnostic error "-Wpedantic"
1560 /* CQE format mask. */
1561 #define MLX5E_CQE_FORMAT_MASK 0xc
1564 #define MLX5_OPC_MOD_MPW 0x01
1566 /* Compressed Rx CQE structure. */
1567 struct mlx5_mini_cqe8 {
1569 uint32_t rx_hash_result;
1572 uint16_t stride_idx;
1575 uint16_t wqe_counter;
1576 uint8_t s_wqe_opcode;
1584 * Convert a user mark to flow mark.
1587 * Mark value to convert.
1590 * Converted mark value.
1592 static inline uint32_t
1593 mlx5_flow_mark_set(uint32_t val)
1598 * Add one to the user value to differentiate un-marked flows from
1599 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
1600 * remains untouched.
1602 if (val != MLX5_FLOW_MARK_DEFAULT)
1604 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1606 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
1607 * word, byte-swapped by the kernel on little-endian systems. In this
1608 * case, left-shifting the resulting big-endian value ensures the
1609 * least significant 24 bits are retained when converting it back.
1611 ret = rte_cpu_to_be_32(val) >> 8;
1619 * Convert a mark to user mark.
1622 * Mark value to convert.
1625 * Converted mark value.
1627 static inline uint32_t
1628 mlx5_flow_mark_get(uint32_t val)
1631 * Subtract one from the retrieved value. It was added by
1632 * mlx5_flow_mark_set() to distinguish unmarked flows.
1634 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1635 return (val >> 8) - 1;
1641 #endif /* RTE_PMD_MLX5_PRM_H_ */