4 * Copyright 2016 6WIND S.A.
5 * Copyright 2016 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef RTE_PMD_MLX5_PRM_H_
35 #define RTE_PMD_MLX5_PRM_H_
38 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
40 #pragma GCC diagnostic ignored "-Wpedantic"
42 #include <infiniband/mlx5_hw.h>
44 #pragma GCC diagnostic error "-Wpedantic"
47 #include "mlx5_autoconf.h"
49 /* Get CQE owner bit. */
50 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
53 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
56 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
58 /* Get CQE solicited event. */
59 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
61 /* Invalidate a CQE. */
62 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
64 /* CQE value to inform that VLAN is stripped. */
65 #define MLX5_CQE_VLAN_STRIPPED 0x1
67 /* Maximum number of packets a multi-packet WQE can handle. */
68 #define MLX5_MPW_DSEG_MAX 5
71 #define MLX5_WQE_DWORD_SIZE 16
74 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
76 /* Compute the number of DS. */
77 #define MLX5_WQE_DS(n) \
78 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
80 /* Room for inline data in multi-packet WQE. */
81 #define MLX5_MWQE64_INL_DATA 28
83 #ifndef HAVE_VERBS_MLX5_OPCODE_TSO
84 #define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */
88 #define MLX5_CQE_RX_IPV4_PACKET (1u << 2)
91 #define MLX5_CQE_RX_IPV6_PACKET (1u << 3)
93 /* Outer IPv4 packet. */
94 #define MLX5_CQE_RX_OUTER_IPV4_PACKET (1u << 7)
96 /* Outer IPv6 packet. */
97 #define MLX5_CQE_RX_OUTER_IPV6_PACKET (1u << 8)
99 /* Tunnel packet bit in the CQE. */
100 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 4)
102 /* Outer IP checksum OK. */
103 #define MLX5_CQE_RX_OUTER_IP_CSUM_OK (1u << 5)
105 /* Outer UDP header and checksum OK. */
106 #define MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK (1u << 6)
108 /* Subset of struct mlx5_wqe_eth_seg. */
109 struct mlx5_wqe_eth_seg_small {
115 uint16_t inline_hdr_sz;
116 uint8_t inline_hdr[2];
119 struct mlx5_wqe_inl_small {
124 /* Small common part of the WQE. */
127 struct mlx5_wqe_eth_seg_small eseg;
136 /* MPW session status. */
137 enum mlx5_mpw_state {
138 MLX5_MPW_STATE_OPENED,
139 MLX5_MPW_INL_STATE_OPENED,
140 MLX5_MPW_STATE_CLOSED,
143 /* MPW session descriptor. */
145 enum mlx5_mpw_state state;
148 unsigned int total_len;
149 volatile struct mlx5_wqe *wqe;
151 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
152 volatile uint8_t *raw;
156 /* CQ element structure - should be equal to the cache line size */
158 #if (RTE_CACHE_LINE_SIZE == 128)
163 uint32_t rx_hash_res;
164 uint8_t rx_hash_type;
167 uint8_t l4_hdr_type_etc;
173 uint16_t wqe_counter;
178 #endif /* RTE_PMD_MLX5_PRM_H_ */