1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox.
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* Get CQE owner bit. */
25 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
28 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
31 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
33 /* Get CQE solicited event. */
34 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
36 /* Invalidate a CQE. */
37 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
39 /* Maximum number of packets a multi-packet WQE can handle. */
40 #define MLX5_MPW_DSEG_MAX 5
43 #define MLX5_WQE_DWORD_SIZE 16
46 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
48 /* Max size of a WQE session. */
49 #define MLX5_WQE_SIZE_MAX 960U
51 /* Compute the number of DS. */
52 #define MLX5_WQE_DS(n) \
53 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
55 /* Room for inline data in multi-packet WQE. */
56 #define MLX5_MWQE64_INL_DATA 28
58 /* Default minimum number of Tx queues for inlining packets. */
59 #define MLX5_EMPW_MIN_TXQS 8
61 /* Default max packet length to be inlined. */
62 #define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
65 #define MLX5_OPC_MOD_ENHANCED_MPSW 0
66 #define MLX5_OPCODE_ENHANCED_MPSW 0x29
68 /* CQE value to inform that VLAN is stripped. */
69 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
72 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
75 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
78 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
81 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
84 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
86 /* IP is fragmented. */
87 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
89 /* L2 header is valid. */
90 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
92 /* L3 header is valid. */
93 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
95 /* L4 header is valid. */
96 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
98 /* Outer packet, 0 IPv4, 1 IPv6. */
99 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
101 /* Tunnel packet bit in the CQE. */
102 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
104 /* Inner L3 checksum offload (Tunneled packets only). */
105 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
107 /* Inner L4 checksum offload (Tunneled packets only). */
108 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
110 /* Is flow mark valid. */
111 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
112 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
114 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
117 /* INVALID is used by packets matching no flow rules. */
118 #define MLX5_FLOW_MARK_INVALID 0
120 /* Maximum allowed value to mark a packet. */
121 #define MLX5_FLOW_MARK_MAX 0xfffff0
123 /* Default mark value used when none is provided. */
124 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
126 /* Maximum number of DS in WQE. */
127 #define MLX5_DSEG_MAX 63
129 /* Subset of struct mlx5_wqe_eth_seg. */
130 struct mlx5_wqe_eth_seg_small {
136 uint16_t inline_hdr_sz;
137 uint8_t inline_hdr[2];
138 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
140 struct mlx5_wqe_inl_small {
143 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
145 struct mlx5_wqe_ctrl {
150 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
152 /* Small common part of the WQE. */
155 struct mlx5_wqe_eth_seg_small eseg;
158 /* Vectorize WQE header. */
168 } __rte_aligned(MLX5_WQE_SIZE);
174 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
177 /* MPW session status. */
178 enum mlx5_mpw_state {
179 MLX5_MPW_STATE_OPENED,
180 MLX5_MPW_INL_STATE_OPENED,
181 MLX5_MPW_ENHANCED_STATE_OPENED,
182 MLX5_MPW_STATE_CLOSED,
185 /* MPW session descriptor. */
187 enum mlx5_mpw_state state;
190 unsigned int total_len;
191 volatile struct mlx5_wqe *wqe;
193 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
194 volatile uint8_t *raw;
198 /* CQ element structure - should be equal to the cache line size */
200 #if (RTE_CACHE_LINE_SIZE == 128)
205 uint32_t rx_hash_res;
206 uint8_t rx_hash_type;
208 uint16_t hdr_type_etc;
213 uint32_t sop_drop_qpn;
214 uint16_t wqe_counter;
219 /* Adding direct verbs to data-path. */
221 /* CQ sequence number mask. */
222 #define MLX5_CQ_SQN_MASK 0x3
224 /* CQ sequence number index. */
225 #define MLX5_CQ_SQN_OFFSET 28
227 /* CQ doorbell index mask. */
228 #define MLX5_CI_MASK 0xffffff
230 /* CQ doorbell offset. */
231 #define MLX5_CQ_ARM_DB 1
233 /* CQ doorbell offset*/
234 #define MLX5_CQ_DOORBELL 0x20
236 /* CQE format value. */
237 #define MLX5_COMPRESSED 0x3
239 /* CQE format mask. */
240 #define MLX5E_CQE_FORMAT_MASK 0xc
243 #define MLX5_OPC_MOD_MPW 0x01
245 /* Compressed Rx CQE structure. */
246 struct mlx5_mini_cqe8 {
248 uint32_t rx_hash_result;
251 uint16_t wqe_counter;
252 uint8_t s_wqe_opcode;
260 * Convert a user mark to flow mark.
263 * Mark value to convert.
266 * Converted mark value.
268 static inline uint32_t
269 mlx5_flow_mark_set(uint32_t val)
274 * Add one to the user value to differentiate un-marked flows from
275 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
278 if (val != MLX5_FLOW_MARK_DEFAULT)
280 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
282 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
283 * word, byte-swapped by the kernel on little-endian systems. In this
284 * case, left-shifting the resulting big-endian value ensures the
285 * least significant 24 bits are retained when converting it back.
287 ret = rte_cpu_to_be_32(val) >> 8;
295 * Convert a mark to user mark.
298 * Mark value to convert.
301 * Converted mark value.
303 static inline uint32_t
304 mlx5_flow_mark_get(uint32_t val)
307 * Subtract one from the retrieved value. It was added by
308 * mlx5_flow_mark_set() to distinguish unmarked flows.
310 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
311 return (val >> 8) - 1;
317 #endif /* RTE_PMD_MLX5_PRM_H_ */