1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* WQE Segment sizes in bytes. */
43 #define MLX5_WSEG_SIZE 16u
44 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
45 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
46 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
48 /* WQE/WQEBB size in bytes. */
49 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
52 * Max size of a WQE session.
53 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
54 * the WQE size field in Control Segment is 6 bits wide.
56 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
59 * Default minimum number of Tx queues for inlining packets.
60 * If there are less queues as specified we assume we have
61 * no enough CPU resources (cycles) to perform inlining,
62 * the PCIe throughput is not supposed as bottleneck and
63 * inlining is disabled.
65 #define MLX5_INLINE_MAX_TXQS 8u
66 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
69 * Default packet length threshold to be inlined with
70 * enhanced MPW. If packet length exceeds the threshold
71 * the data are not inlined. Should be aligned in WQEBB
72 * boundary with accounting the title Control and Ethernet
75 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
76 MLX5_DSEG_MIN_INLINE_SIZE)
78 * Maximal inline data length sent with enhanced MPW.
79 * Is based on maximal WQE size.
81 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
82 MLX5_WQE_CSEG_SIZE - \
83 MLX5_WQE_ESEG_SIZE - \
84 MLX5_WQE_DSEG_SIZE + \
85 MLX5_DSEG_MIN_INLINE_SIZE)
87 * Minimal amount of packets to be sent with EMPW.
88 * This limits the minimal required size of sent EMPW.
89 * If there are no enough resources to built minimal
90 * EMPW the sending loop exits.
92 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
94 * Maximal amount of packets to be sent with EMPW.
95 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
96 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
97 * without CQE generation request, being multiplied by
98 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
99 * in tx burst routine at the moment of freeing multiple mbufs.
101 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
102 #define MLX5_MPW_MAX_PACKETS 6
103 #define MLX5_MPW_INLINE_MAX_PACKETS 2
106 * Default packet length threshold to be inlined with
107 * ordinary SEND. Inlining saves the MR key search
108 * and extra PCIe data fetch transaction, but eats the
111 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
112 MLX5_ESEG_MIN_INLINE_SIZE - \
113 MLX5_WQE_CSEG_SIZE - \
114 MLX5_WQE_ESEG_SIZE - \
117 * Maximal inline data length sent with ordinary SEND.
118 * Is based on maximal WQE size.
120 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
121 MLX5_WQE_CSEG_SIZE - \
122 MLX5_WQE_ESEG_SIZE - \
123 MLX5_WQE_DSEG_SIZE + \
124 MLX5_ESEG_MIN_INLINE_SIZE)
126 /* Missed in mlv5dv.h, should define here. */
127 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
129 /* CQE value to inform that VLAN is stripped. */
130 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
133 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
136 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
139 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
142 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
145 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
147 /* IP is fragmented. */
148 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
150 /* L2 header is valid. */
151 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
153 /* L3 header is valid. */
154 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
156 /* L4 header is valid. */
157 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
159 /* Outer packet, 0 IPv4, 1 IPv6. */
160 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
162 /* Tunnel packet bit in the CQE. */
163 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
165 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
166 #define MLX5_CQE_LRO_PUSH_MASK 0x40
168 /* Mask for L4 type in the CQE hdr_type_etc field. */
169 #define MLX5_CQE_L4_TYPE_MASK 0x70
171 /* The bit index of L4 type in CQE hdr_type_etc field. */
172 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
174 /* L4 type to indicate TCP packet without acknowledgment. */
175 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
177 /* L4 type to indicate TCP packet with acknowledgment. */
178 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
180 /* Inner L3 checksum offload (Tunneled packets only). */
181 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
183 /* Inner L4 checksum offload (Tunneled packets only). */
184 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
186 /* Outer L4 type is TCP. */
187 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
189 /* Outer L4 type is UDP. */
190 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
192 /* Outer L3 type is IPV4. */
193 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
195 /* Outer L3 type is IPV6. */
196 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
198 /* Inner L4 type is TCP. */
199 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
201 /* Inner L4 type is UDP. */
202 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
204 /* Inner L3 type is IPV4. */
205 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
207 /* Inner L3 type is IPV6. */
208 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
210 /* VLAN insertion flag. */
211 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
213 /* Data inline segment flag. */
214 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
216 /* Is flow mark valid. */
217 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
218 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
220 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
223 /* INVALID is used by packets matching no flow rules. */
224 #define MLX5_FLOW_MARK_INVALID 0
226 /* Maximum allowed value to mark a packet. */
227 #define MLX5_FLOW_MARK_MAX 0xfffff0
229 /* Default mark value used when none is provided. */
230 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
232 /* Default mark mask for metadata legacy mode. */
233 #define MLX5_FLOW_MARK_MASK 0xffffff
235 /* Maximum number of DS in WQE. Limited by 6-bit field. */
236 #define MLX5_DSEG_MAX 63
238 /* The completion mode offset in the WQE control segment line 2. */
239 #define MLX5_COMP_MODE_OFFSET 2
241 /* Amount of data bytes in minimal inline data segment. */
242 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
244 /* Amount of data bytes in minimal inline eth segment. */
245 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
247 /* Amount of data bytes after eth data segment. */
248 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
250 /* The maximum log value of segments per RQ WQE. */
251 #define MLX5_MAX_LOG_RQ_SEGS 5u
253 /* The alignment needed for WQ buffer. */
254 #define MLX5_WQE_BUF_ALIGNMENT 512
256 /* Completion mode. */
257 enum mlx5_completion_mode {
258 MLX5_COMP_ONLY_ERR = 0x0,
259 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
260 MLX5_COMP_ALWAYS = 0x2,
261 MLX5_COMP_CQE_AND_EQE = 0x3,
268 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
271 /* WQE Control segment. */
272 struct mlx5_wqe_cseg {
277 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
279 /* Header of data segment. Minimal size Data Segment */
280 struct mlx5_wqe_dseg {
283 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
291 /* Subset of struct WQE Ethernet Segment. */
292 struct mlx5_wqe_eseg {
300 uint16_t inline_hdr_sz;
302 uint16_t inline_data;
309 uint32_t flow_metadata;
315 /* The title WQEBB, header of WQE. */
318 struct mlx5_wqe_cseg cseg;
321 struct mlx5_wqe_eseg eseg;
323 struct mlx5_wqe_dseg dseg[2];
324 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
328 /* WQE for Multi-Packet RQ. */
329 struct mlx5_wqe_mprq {
330 struct mlx5_wqe_srq_next_seg next_seg;
331 struct mlx5_wqe_data_seg dseg;
334 #define MLX5_MPRQ_LEN_MASK 0x000ffff
335 #define MLX5_MPRQ_LEN_SHIFT 0
336 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
337 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
338 #define MLX5_MPRQ_FILLER_MASK 0x80000000
339 #define MLX5_MPRQ_FILLER_SHIFT 31
341 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
343 /* CQ element structure - should be equal to the cache line size */
345 #if (RTE_CACHE_LINE_SIZE == 128)
351 uint8_t lro_tcppsh_abort_dupack;
353 uint16_t lro_tcp_win;
354 uint32_t lro_ack_seq_num;
355 uint32_t rx_hash_res;
356 uint8_t rx_hash_type;
360 uint16_t hdr_type_etc;
364 uint32_t flow_table_metadata;
368 uint32_t sop_drop_qpn;
369 uint16_t wqe_counter;
374 /* Adding direct verbs to data-path. */
376 /* CQ sequence number mask. */
377 #define MLX5_CQ_SQN_MASK 0x3
379 /* CQ sequence number index. */
380 #define MLX5_CQ_SQN_OFFSET 28
382 /* CQ doorbell index mask. */
383 #define MLX5_CI_MASK 0xffffff
385 /* CQ doorbell offset. */
386 #define MLX5_CQ_ARM_DB 1
388 /* CQ doorbell offset*/
389 #define MLX5_CQ_DOORBELL 0x20
391 /* CQE format value. */
392 #define MLX5_COMPRESSED 0x3
394 /* Action type of header modification. */
396 MLX5_MODIFICATION_TYPE_SET = 0x1,
397 MLX5_MODIFICATION_TYPE_ADD = 0x2,
398 MLX5_MODIFICATION_TYPE_COPY = 0x3,
401 /* The field of packet to be modified. */
402 enum mlx5_modification_field {
403 MLX5_MODI_OUT_NONE = -1,
404 MLX5_MODI_OUT_SMAC_47_16 = 1,
405 MLX5_MODI_OUT_SMAC_15_0,
406 MLX5_MODI_OUT_ETHERTYPE,
407 MLX5_MODI_OUT_DMAC_47_16,
408 MLX5_MODI_OUT_DMAC_15_0,
409 MLX5_MODI_OUT_IP_DSCP,
410 MLX5_MODI_OUT_TCP_FLAGS,
411 MLX5_MODI_OUT_TCP_SPORT,
412 MLX5_MODI_OUT_TCP_DPORT,
413 MLX5_MODI_OUT_IPV4_TTL,
414 MLX5_MODI_OUT_UDP_SPORT,
415 MLX5_MODI_OUT_UDP_DPORT,
416 MLX5_MODI_OUT_SIPV6_127_96,
417 MLX5_MODI_OUT_SIPV6_95_64,
418 MLX5_MODI_OUT_SIPV6_63_32,
419 MLX5_MODI_OUT_SIPV6_31_0,
420 MLX5_MODI_OUT_DIPV6_127_96,
421 MLX5_MODI_OUT_DIPV6_95_64,
422 MLX5_MODI_OUT_DIPV6_63_32,
423 MLX5_MODI_OUT_DIPV6_31_0,
426 MLX5_MODI_OUT_FIRST_VID,
427 MLX5_MODI_IN_SMAC_47_16 = 0x31,
428 MLX5_MODI_IN_SMAC_15_0,
429 MLX5_MODI_IN_ETHERTYPE,
430 MLX5_MODI_IN_DMAC_47_16,
431 MLX5_MODI_IN_DMAC_15_0,
432 MLX5_MODI_IN_IP_DSCP,
433 MLX5_MODI_IN_TCP_FLAGS,
434 MLX5_MODI_IN_TCP_SPORT,
435 MLX5_MODI_IN_TCP_DPORT,
436 MLX5_MODI_IN_IPV4_TTL,
437 MLX5_MODI_IN_UDP_SPORT,
438 MLX5_MODI_IN_UDP_DPORT,
439 MLX5_MODI_IN_SIPV6_127_96,
440 MLX5_MODI_IN_SIPV6_95_64,
441 MLX5_MODI_IN_SIPV6_63_32,
442 MLX5_MODI_IN_SIPV6_31_0,
443 MLX5_MODI_IN_DIPV6_127_96,
444 MLX5_MODI_IN_DIPV6_95_64,
445 MLX5_MODI_IN_DIPV6_63_32,
446 MLX5_MODI_IN_DIPV6_31_0,
449 MLX5_MODI_OUT_IPV6_HOPLIMIT,
450 MLX5_MODI_IN_IPV6_HOPLIMIT,
451 MLX5_MODI_META_DATA_REG_A,
452 MLX5_MODI_META_DATA_REG_B = 0x50,
453 MLX5_MODI_META_REG_C_0,
454 MLX5_MODI_META_REG_C_1,
455 MLX5_MODI_META_REG_C_2,
456 MLX5_MODI_META_REG_C_3,
457 MLX5_MODI_META_REG_C_4,
458 MLX5_MODI_META_REG_C_5,
459 MLX5_MODI_META_REG_C_6,
460 MLX5_MODI_META_REG_C_7,
461 MLX5_MODI_OUT_TCP_SEQ_NUM,
462 MLX5_MODI_IN_TCP_SEQ_NUM,
463 MLX5_MODI_OUT_TCP_ACK_NUM,
464 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
467 /* Total number of metadata reg_c's. */
468 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
484 /* Modification sub command. */
485 struct mlx5_modification_cmd {
489 unsigned int length:5;
490 unsigned int rsvd0:3;
491 unsigned int offset:5;
492 unsigned int rsvd1:3;
493 unsigned int field:12;
494 unsigned int action_type:4;
501 unsigned int rsvd2:8;
502 unsigned int dst_offset:5;
503 unsigned int rsvd3:3;
504 unsigned int dst_field:12;
505 unsigned int rsvd4:4;
510 typedef uint32_t u32;
511 typedef uint16_t u16;
514 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
515 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
516 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
517 (&(__mlx5_nullp(typ)->fld)))
518 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
519 (__mlx5_bit_off(typ, fld) & 0x1f))
520 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
521 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
522 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
523 __mlx5_dw_bit_off(typ, fld))
524 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
525 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
526 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
527 (__mlx5_bit_off(typ, fld) & 0xf))
528 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
529 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
530 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
531 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
532 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
534 /* insert a value to a struct */
535 #define MLX5_SET(typ, p, fld, v) \
538 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
539 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
540 __mlx5_dw_off(typ, fld))) & \
541 (~__mlx5_dw_mask(typ, fld))) | \
542 (((_v) & __mlx5_mask(typ, fld)) << \
543 __mlx5_dw_bit_off(typ, fld))); \
546 #define MLX5_SET64(typ, p, fld, v) \
548 assert(__mlx5_bit_sz(typ, fld) == 64); \
549 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
550 rte_cpu_to_be_64(v); \
553 #define MLX5_GET(typ, p, fld) \
554 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
555 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
556 __mlx5_mask(typ, fld))
557 #define MLX5_GET16(typ, p, fld) \
558 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
559 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
560 __mlx5_mask16(typ, fld))
561 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
562 __mlx5_64_off(typ, fld)))
563 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
565 struct mlx5_ifc_fte_match_set_misc_bits {
566 u8 gre_c_present[0x1];
567 u8 reserved_at_1[0x1];
568 u8 gre_k_present[0x1];
569 u8 gre_s_present[0x1];
570 u8 source_vhci_port[0x4];
572 u8 reserved_at_20[0x10];
573 u8 source_port[0x10];
574 u8 outer_second_prio[0x3];
575 u8 outer_second_cfi[0x1];
576 u8 outer_second_vid[0xc];
577 u8 inner_second_prio[0x3];
578 u8 inner_second_cfi[0x1];
579 u8 inner_second_vid[0xc];
580 u8 outer_second_cvlan_tag[0x1];
581 u8 inner_second_cvlan_tag[0x1];
582 u8 outer_second_svlan_tag[0x1];
583 u8 inner_second_svlan_tag[0x1];
584 u8 reserved_at_64[0xc];
585 u8 gre_protocol[0x10];
589 u8 reserved_at_b8[0x8];
591 u8 reserved_at_e4[0x7];
593 u8 reserved_at_e0[0xc];
594 u8 outer_ipv6_flow_label[0x14];
595 u8 reserved_at_100[0xc];
596 u8 inner_ipv6_flow_label[0x14];
597 u8 reserved_at_120[0xa];
598 u8 geneve_opt_len[0x6];
599 u8 geneve_protocol_type[0x10];
600 u8 reserved_at_140[0xc0];
603 struct mlx5_ifc_ipv4_layout_bits {
604 u8 reserved_at_0[0x60];
608 struct mlx5_ifc_ipv6_layout_bits {
612 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
613 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
614 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
615 u8 reserved_at_0[0x80];
618 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
637 u8 reserved_at_c0[0x20];
640 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
641 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
644 struct mlx5_ifc_fte_match_mpls_bits {
651 struct mlx5_ifc_fte_match_set_misc2_bits {
652 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
653 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
654 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
655 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
656 u8 metadata_reg_c_7[0x20];
657 u8 metadata_reg_c_6[0x20];
658 u8 metadata_reg_c_5[0x20];
659 u8 metadata_reg_c_4[0x20];
660 u8 metadata_reg_c_3[0x20];
661 u8 metadata_reg_c_2[0x20];
662 u8 metadata_reg_c_1[0x20];
663 u8 metadata_reg_c_0[0x20];
664 u8 metadata_reg_a[0x20];
665 u8 metadata_reg_b[0x20];
666 u8 reserved_at_1c0[0x40];
669 struct mlx5_ifc_fte_match_set_misc3_bits {
670 u8 inner_tcp_seq_num[0x20];
671 u8 outer_tcp_seq_num[0x20];
672 u8 inner_tcp_ack_num[0x20];
673 u8 outer_tcp_ack_num[0x20];
674 u8 reserved_at_auto1[0x8];
675 u8 outer_vxlan_gpe_vni[0x18];
676 u8 outer_vxlan_gpe_next_protocol[0x8];
677 u8 outer_vxlan_gpe_flags[0x8];
678 u8 reserved_at_a8[0x10];
679 u8 icmp_header_data[0x20];
680 u8 icmpv6_header_data[0x20];
685 u8 reserved_at_1a0[0xe0];
689 struct mlx5_ifc_fte_match_param_bits {
690 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
691 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
692 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
693 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
694 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
698 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
699 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
700 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
701 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
702 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
706 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
707 MLX5_CMD_OP_CREATE_MKEY = 0x200,
708 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
709 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
710 MLX5_CMD_OP_CREATE_TIR = 0x900,
711 MLX5_CMD_OP_CREATE_SQ = 0X904,
712 MLX5_CMD_OP_MODIFY_SQ = 0X905,
713 MLX5_CMD_OP_CREATE_RQ = 0x908,
714 MLX5_CMD_OP_MODIFY_RQ = 0x909,
715 MLX5_CMD_OP_CREATE_TIS = 0x912,
716 MLX5_CMD_OP_QUERY_TIS = 0x915,
717 MLX5_CMD_OP_CREATE_RQT = 0x916,
718 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
719 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
723 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
727 struct mlx5_ifc_alloc_flow_counter_out_bits {
729 u8 reserved_at_8[0x18];
731 u8 flow_counter_id[0x20];
732 u8 reserved_at_60[0x20];
735 struct mlx5_ifc_alloc_flow_counter_in_bits {
737 u8 reserved_at_10[0x10];
738 u8 reserved_at_20[0x10];
740 u8 flow_counter_id[0x20];
741 u8 reserved_at_40[0x18];
742 u8 flow_counter_bulk[0x8];
745 struct mlx5_ifc_dealloc_flow_counter_out_bits {
747 u8 reserved_at_8[0x18];
749 u8 reserved_at_40[0x40];
752 struct mlx5_ifc_dealloc_flow_counter_in_bits {
754 u8 reserved_at_10[0x10];
755 u8 reserved_at_20[0x10];
757 u8 flow_counter_id[0x20];
758 u8 reserved_at_60[0x20];
761 struct mlx5_ifc_traffic_counter_bits {
766 struct mlx5_ifc_query_flow_counter_out_bits {
768 u8 reserved_at_8[0x18];
770 u8 reserved_at_40[0x40];
771 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
774 struct mlx5_ifc_query_flow_counter_in_bits {
776 u8 reserved_at_10[0x10];
777 u8 reserved_at_20[0x10];
779 u8 reserved_at_40[0x20];
783 u8 dump_to_memory[0x1];
784 u8 num_of_counters[0x1e];
785 u8 flow_counter_id[0x20];
788 struct mlx5_ifc_mkc_bits {
789 u8 reserved_at_0[0x1];
791 u8 reserved_at_2[0x1];
792 u8 access_mode_4_2[0x3];
793 u8 reserved_at_6[0x7];
794 u8 relaxed_ordering_write[0x1];
795 u8 reserved_at_e[0x1];
796 u8 small_fence_on_rdma_read_response[0x1];
803 u8 access_mode_1_0[0x2];
804 u8 reserved_at_18[0x8];
809 u8 reserved_at_40[0x20];
814 u8 reserved_at_63[0x2];
815 u8 expected_sigerr_count[0x1];
816 u8 reserved_at_66[0x1];
824 u8 bsf_octword_size[0x20];
826 u8 reserved_at_120[0x80];
828 u8 translations_octword_size[0x20];
830 u8 reserved_at_1c0[0x1b];
831 u8 log_page_size[0x5];
833 u8 reserved_at_1e0[0x20];
836 struct mlx5_ifc_create_mkey_out_bits {
838 u8 reserved_at_8[0x18];
842 u8 reserved_at_40[0x8];
845 u8 reserved_at_60[0x20];
848 struct mlx5_ifc_create_mkey_in_bits {
850 u8 reserved_at_10[0x10];
852 u8 reserved_at_20[0x10];
855 u8 reserved_at_40[0x20];
858 u8 reserved_at_61[0x1f];
860 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
862 u8 reserved_at_280[0x80];
864 u8 translations_octword_actual_size[0x20];
866 u8 mkey_umem_id[0x20];
868 u8 mkey_umem_offset[0x40];
870 u8 reserved_at_380[0x500];
872 u8 klm_pas_mtt[][0x20];
876 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
877 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
878 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
882 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
883 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
887 MLX5_CAP_INLINE_MODE_L2,
888 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
889 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
893 MLX5_INLINE_MODE_NONE,
896 MLX5_INLINE_MODE_TCP_UDP,
897 MLX5_INLINE_MODE_RESERVED4,
898 MLX5_INLINE_MODE_INNER_L2,
899 MLX5_INLINE_MODE_INNER_IP,
900 MLX5_INLINE_MODE_INNER_TCP_UDP,
903 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
904 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
905 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
906 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
907 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
908 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
909 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
910 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
911 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
912 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
913 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
915 struct mlx5_ifc_cmd_hca_cap_bits {
916 u8 reserved_at_0[0x30];
918 u8 reserved_at_40[0x40];
919 u8 log_max_srq_sz[0x8];
920 u8 log_max_qp_sz[0x8];
921 u8 reserved_at_90[0xb];
923 u8 reserved_at_a0[0xb];
925 u8 reserved_at_b0[0x10];
926 u8 reserved_at_c0[0x8];
927 u8 log_max_cq_sz[0x8];
928 u8 reserved_at_d0[0xb];
930 u8 log_max_eq_sz[0x8];
931 u8 reserved_at_e8[0x2];
932 u8 log_max_mkey[0x6];
933 u8 reserved_at_f0[0x8];
934 u8 dump_fill_mkey[0x1];
935 u8 reserved_at_f9[0x3];
937 u8 max_indirection[0x8];
938 u8 fixed_buffer_size[0x1];
939 u8 log_max_mrw_sz[0x7];
940 u8 force_teardown[0x1];
941 u8 reserved_at_111[0x1];
942 u8 log_max_bsf_list_size[0x6];
943 u8 umr_extended_translation_offset[0x1];
945 u8 log_max_klm_list_size[0x6];
946 u8 reserved_at_120[0xa];
947 u8 log_max_ra_req_dc[0x6];
948 u8 reserved_at_130[0xa];
949 u8 log_max_ra_res_dc[0x6];
950 u8 reserved_at_140[0xa];
951 u8 log_max_ra_req_qp[0x6];
952 u8 reserved_at_150[0xa];
953 u8 log_max_ra_res_qp[0x6];
955 u8 cc_query_allowed[0x1];
956 u8 cc_modify_allowed[0x1];
958 u8 cache_line_128byte[0x1];
959 u8 reserved_at_165[0xa];
961 u8 gid_table_size[0x10];
962 u8 out_of_seq_cnt[0x1];
963 u8 vport_counters[0x1];
964 u8 retransmission_q_counters[0x1];
966 u8 modify_rq_counter_set_id[0x1];
967 u8 rq_delay_drop[0x1];
969 u8 pkey_table_size[0x10];
970 u8 vport_group_manager[0x1];
971 u8 vhca_group_manager[0x1];
974 u8 vnic_env_queue_counters[0x1];
976 u8 nic_flow_table[0x1];
977 u8 eswitch_manager[0x1];
978 u8 device_memory[0x1];
981 u8 local_ca_ack_delay[0x5];
982 u8 port_module_event[0x1];
983 u8 enhanced_error_q_counters[0x1];
985 u8 reserved_at_1b3[0x1];
986 u8 disable_link_up[0x1];
990 u8 reserved_at_1c0[0x1];
994 u8 reserved_at_1c8[0x4];
996 u8 temp_warn_event[0x1];
998 u8 general_notification_event[0x1];
999 u8 reserved_at_1d3[0x2];
1003 u8 reserved_at_1d8[0x1];
1011 u8 stat_rate_support[0x10];
1012 u8 reserved_at_1f0[0xc];
1013 u8 cqe_version[0x4];
1014 u8 compact_address_vector[0x1];
1015 u8 striding_rq[0x1];
1016 u8 reserved_at_202[0x1];
1017 u8 ipoib_enhanced_offloads[0x1];
1018 u8 ipoib_basic_offloads[0x1];
1019 u8 reserved_at_205[0x1];
1020 u8 repeated_block_disabled[0x1];
1021 u8 umr_modify_entity_size_disabled[0x1];
1022 u8 umr_modify_atomic_disabled[0x1];
1023 u8 umr_indirect_mkey_disabled[0x1];
1025 u8 reserved_at_20c[0x3];
1026 u8 drain_sigerr[0x1];
1027 u8 cmdif_checksum[0x2];
1029 u8 reserved_at_213[0x1];
1030 u8 wq_signature[0x1];
1031 u8 sctr_data_cqe[0x1];
1032 u8 reserved_at_216[0x1];
1038 u8 eth_net_offloads[0x1];
1041 u8 reserved_at_21f[0x1];
1044 u8 cq_moderation[0x1];
1045 u8 reserved_at_223[0x3];
1046 u8 cq_eq_remap[0x1];
1048 u8 block_lb_mc[0x1];
1049 u8 reserved_at_229[0x1];
1050 u8 scqe_break_moderation[0x1];
1051 u8 cq_period_start_from_cqe[0x1];
1053 u8 reserved_at_22d[0x1];
1055 u8 vector_calc[0x1];
1056 u8 umr_ptr_rlky[0x1];
1058 u8 reserved_at_232[0x4];
1061 u8 set_deth_sqpn[0x1];
1062 u8 reserved_at_239[0x3];
1068 u8 reserved_at_241[0x9];
1070 u8 reserved_at_250[0x8];
1073 u8 driver_version[0x1];
1074 u8 pad_tx_eth_packet[0x1];
1075 u8 reserved_at_263[0x8];
1076 u8 log_bf_reg_size[0x5];
1077 u8 reserved_at_270[0xb];
1079 u8 num_lag_ports[0x4];
1080 u8 reserved_at_280[0x10];
1081 u8 max_wqe_sz_sq[0x10];
1082 u8 reserved_at_2a0[0x10];
1083 u8 max_wqe_sz_rq[0x10];
1084 u8 max_flow_counter_31_16[0x10];
1085 u8 max_wqe_sz_sq_dc[0x10];
1086 u8 reserved_at_2e0[0x7];
1087 u8 max_qp_mcg[0x19];
1088 u8 reserved_at_300[0x10];
1089 u8 flow_counter_bulk_alloc[0x08];
1090 u8 log_max_mcg[0x8];
1091 u8 reserved_at_320[0x3];
1092 u8 log_max_transport_domain[0x5];
1093 u8 reserved_at_328[0x3];
1095 u8 reserved_at_330[0xb];
1096 u8 log_max_xrcd[0x5];
1097 u8 nic_receive_steering_discard[0x1];
1098 u8 receive_discard_vport_down[0x1];
1099 u8 transmit_discard_vport_down[0x1];
1100 u8 reserved_at_343[0x5];
1101 u8 log_max_flow_counter_bulk[0x8];
1102 u8 max_flow_counter_15_0[0x10];
1104 u8 flow_counters_dump[0x1];
1105 u8 reserved_at_360[0x1];
1107 u8 reserved_at_368[0x3];
1109 u8 reserved_at_370[0x3];
1110 u8 log_max_tir[0x5];
1111 u8 reserved_at_378[0x3];
1112 u8 log_max_tis[0x5];
1113 u8 basic_cyclic_rcv_wqe[0x1];
1114 u8 reserved_at_381[0x2];
1115 u8 log_max_rmp[0x5];
1116 u8 reserved_at_388[0x3];
1117 u8 log_max_rqt[0x5];
1118 u8 reserved_at_390[0x3];
1119 u8 log_max_rqt_size[0x5];
1120 u8 reserved_at_398[0x3];
1121 u8 log_max_tis_per_sq[0x5];
1122 u8 ext_stride_num_range[0x1];
1123 u8 reserved_at_3a1[0x2];
1124 u8 log_max_stride_sz_rq[0x5];
1125 u8 reserved_at_3a8[0x3];
1126 u8 log_min_stride_sz_rq[0x5];
1127 u8 reserved_at_3b0[0x3];
1128 u8 log_max_stride_sz_sq[0x5];
1129 u8 reserved_at_3b8[0x3];
1130 u8 log_min_stride_sz_sq[0x5];
1132 u8 reserved_at_3c1[0x2];
1133 u8 log_max_hairpin_queues[0x5];
1134 u8 reserved_at_3c8[0x3];
1135 u8 log_max_hairpin_wq_data_sz[0x5];
1136 u8 reserved_at_3d0[0x3];
1137 u8 log_max_hairpin_num_packets[0x5];
1138 u8 reserved_at_3d8[0x3];
1139 u8 log_max_wq_sz[0x5];
1140 u8 nic_vport_change_event[0x1];
1141 u8 disable_local_lb_uc[0x1];
1142 u8 disable_local_lb_mc[0x1];
1143 u8 log_min_hairpin_wq_data_sz[0x5];
1144 u8 reserved_at_3e8[0x3];
1145 u8 log_max_vlan_list[0x5];
1146 u8 reserved_at_3f0[0x3];
1147 u8 log_max_current_mc_list[0x5];
1148 u8 reserved_at_3f8[0x3];
1149 u8 log_max_current_uc_list[0x5];
1150 u8 general_obj_types[0x40];
1151 u8 reserved_at_440[0x20];
1152 u8 reserved_at_460[0x10];
1153 u8 max_num_eqs[0x10];
1154 u8 reserved_at_480[0x3];
1155 u8 log_max_l2_table[0x5];
1156 u8 reserved_at_488[0x8];
1157 u8 log_uar_page_sz[0x10];
1158 u8 reserved_at_4a0[0x20];
1159 u8 device_frequency_mhz[0x20];
1160 u8 device_frequency_khz[0x20];
1161 u8 reserved_at_500[0x20];
1162 u8 num_of_uars_per_page[0x20];
1163 u8 flex_parser_protocols[0x20];
1164 u8 reserved_at_560[0x20];
1165 u8 reserved_at_580[0x3c];
1166 u8 mini_cqe_resp_stride_index[0x1];
1167 u8 cqe_128_always[0x1];
1168 u8 cqe_compression_128[0x1];
1169 u8 cqe_compression[0x1];
1170 u8 cqe_compression_timeout[0x10];
1171 u8 cqe_compression_max_num[0x10];
1172 u8 reserved_at_5e0[0x10];
1173 u8 tag_matching[0x1];
1174 u8 rndv_offload_rc[0x1];
1175 u8 rndv_offload_dc[0x1];
1176 u8 log_tag_matching_list_sz[0x5];
1177 u8 reserved_at_5f8[0x3];
1178 u8 log_max_xrq[0x5];
1179 u8 affiliate_nic_vport_criteria[0x8];
1180 u8 native_port_num[0x8];
1181 u8 num_vhca_ports[0x8];
1182 u8 reserved_at_618[0x6];
1183 u8 sw_owner_id[0x1];
1184 u8 reserved_at_61f[0x1e1];
1187 struct mlx5_ifc_qos_cap_bits {
1188 u8 packet_pacing[0x1];
1189 u8 esw_scheduling[0x1];
1190 u8 esw_bw_share[0x1];
1191 u8 esw_rate_limit[0x1];
1192 u8 reserved_at_4[0x1];
1193 u8 packet_pacing_burst_bound[0x1];
1194 u8 packet_pacing_typical_size[0x1];
1195 u8 flow_meter_srtcm[0x1];
1196 u8 reserved_at_8[0x8];
1197 u8 log_max_flow_meter[0x8];
1198 u8 flow_meter_reg_id[0x8];
1199 u8 reserved_at_25[0x20];
1200 u8 packet_pacing_max_rate[0x20];
1201 u8 packet_pacing_min_rate[0x20];
1202 u8 reserved_at_80[0x10];
1203 u8 packet_pacing_rate_table_size[0x10];
1204 u8 esw_element_type[0x10];
1205 u8 esw_tsar_type[0x10];
1206 u8 reserved_at_c0[0x10];
1207 u8 max_qos_para_vport[0x10];
1208 u8 max_tsar_bw_share[0x20];
1209 u8 reserved_at_100[0x6e8];
1212 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1216 u8 lro_psh_flag[0x1];
1217 u8 lro_time_stamp[0x1];
1218 u8 lro_max_msg_sz_mode[0x2];
1219 u8 wqe_vlan_insert[0x1];
1220 u8 self_lb_en_modifiable[0x1];
1223 u8 max_lso_cap[0x5];
1224 u8 multi_pkt_send_wqe[0x2];
1225 u8 wqe_inline_mode[0x2];
1226 u8 rss_ind_tbl_cap[0x4];
1228 u8 scatter_fcs[0x1];
1229 u8 enhanced_multi_pkt_send_wqe[0x1];
1230 u8 tunnel_lso_const_out_ip_id[0x1];
1231 u8 tunnel_lro_gre[0x1];
1232 u8 tunnel_lro_vxlan[0x1];
1233 u8 tunnel_stateless_gre[0x1];
1234 u8 tunnel_stateless_vxlan[0x1];
1238 u8 reserved_at_23[0xd];
1239 u8 max_vxlan_udp_ports[0x8];
1240 u8 reserved_at_38[0x6];
1241 u8 max_geneve_opt_len[0x1];
1242 u8 tunnel_stateless_geneve_rx[0x1];
1243 u8 reserved_at_40[0x10];
1244 u8 lro_min_mss_size[0x10];
1245 u8 reserved_at_60[0x120];
1246 u8 lro_timer_supported_periods[4][0x20];
1247 u8 reserved_at_200[0x600];
1250 union mlx5_ifc_hca_cap_union_bits {
1251 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1252 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1253 per_protocol_networking_offload_caps;
1254 struct mlx5_ifc_qos_cap_bits qos_cap;
1255 u8 reserved_at_0[0x8000];
1258 struct mlx5_ifc_query_hca_cap_out_bits {
1260 u8 reserved_at_8[0x18];
1262 u8 reserved_at_40[0x40];
1263 union mlx5_ifc_hca_cap_union_bits capability;
1266 struct mlx5_ifc_query_hca_cap_in_bits {
1268 u8 reserved_at_10[0x10];
1269 u8 reserved_at_20[0x10];
1271 u8 reserved_at_40[0x40];
1274 struct mlx5_ifc_mac_address_layout_bits {
1275 u8 reserved_at_0[0x10];
1276 u8 mac_addr_47_32[0x10];
1277 u8 mac_addr_31_0[0x20];
1280 struct mlx5_ifc_nic_vport_context_bits {
1281 u8 reserved_at_0[0x5];
1282 u8 min_wqe_inline_mode[0x3];
1283 u8 reserved_at_8[0x15];
1284 u8 disable_mc_local_lb[0x1];
1285 u8 disable_uc_local_lb[0x1];
1287 u8 arm_change_event[0x1];
1288 u8 reserved_at_21[0x1a];
1289 u8 event_on_mtu[0x1];
1290 u8 event_on_promisc_change[0x1];
1291 u8 event_on_vlan_change[0x1];
1292 u8 event_on_mc_address_change[0x1];
1293 u8 event_on_uc_address_change[0x1];
1294 u8 reserved_at_40[0xc];
1295 u8 affiliation_criteria[0x4];
1296 u8 affiliated_vhca_id[0x10];
1297 u8 reserved_at_60[0xd0];
1299 u8 system_image_guid[0x40];
1302 u8 reserved_at_200[0x140];
1303 u8 qkey_violation_counter[0x10];
1304 u8 reserved_at_350[0x430];
1307 u8 promisc_all[0x1];
1308 u8 reserved_at_783[0x2];
1309 u8 allowed_list_type[0x3];
1310 u8 reserved_at_788[0xc];
1311 u8 allowed_list_size[0xc];
1312 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1313 u8 reserved_at_7e0[0x20];
1316 struct mlx5_ifc_query_nic_vport_context_out_bits {
1318 u8 reserved_at_8[0x18];
1320 u8 reserved_at_40[0x40];
1321 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1324 struct mlx5_ifc_query_nic_vport_context_in_bits {
1326 u8 reserved_at_10[0x10];
1327 u8 reserved_at_20[0x10];
1329 u8 other_vport[0x1];
1330 u8 reserved_at_41[0xf];
1331 u8 vport_number[0x10];
1332 u8 reserved_at_60[0x5];
1333 u8 allowed_list_type[0x3];
1334 u8 reserved_at_68[0x18];
1337 struct mlx5_ifc_tisc_bits {
1338 u8 strict_lag_tx_port_affinity[0x1];
1339 u8 reserved_at_1[0x3];
1340 u8 lag_tx_port_affinity[0x04];
1341 u8 reserved_at_8[0x4];
1343 u8 reserved_at_10[0x10];
1344 u8 reserved_at_20[0x100];
1345 u8 reserved_at_120[0x8];
1346 u8 transport_domain[0x18];
1347 u8 reserved_at_140[0x8];
1348 u8 underlay_qpn[0x18];
1349 u8 reserved_at_160[0x3a0];
1352 struct mlx5_ifc_query_tis_out_bits {
1354 u8 reserved_at_8[0x18];
1356 u8 reserved_at_40[0x40];
1357 struct mlx5_ifc_tisc_bits tis_context;
1360 struct mlx5_ifc_query_tis_in_bits {
1362 u8 reserved_at_10[0x10];
1363 u8 reserved_at_20[0x10];
1365 u8 reserved_at_40[0x8];
1367 u8 reserved_at_60[0x20];
1370 struct mlx5_ifc_alloc_transport_domain_out_bits {
1372 u8 reserved_at_8[0x18];
1374 u8 reserved_at_40[0x8];
1375 u8 transport_domain[0x18];
1376 u8 reserved_at_60[0x20];
1379 struct mlx5_ifc_alloc_transport_domain_in_bits {
1381 u8 reserved_at_10[0x10];
1382 u8 reserved_at_20[0x10];
1384 u8 reserved_at_40[0x40];
1388 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1389 MLX5_WQ_TYPE_CYCLIC = 0x1,
1390 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1391 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1395 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1396 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1399 struct mlx5_ifc_wq_bits {
1401 u8 wq_signature[0x1];
1402 u8 end_padding_mode[0x2];
1404 u8 reserved_at_8[0x18];
1405 u8 hds_skip_first_sge[0x1];
1406 u8 log2_hds_buf_size[0x3];
1407 u8 reserved_at_24[0x7];
1408 u8 page_offset[0x5];
1410 u8 reserved_at_40[0x8];
1412 u8 reserved_at_60[0x8];
1415 u8 hw_counter[0x20];
1416 u8 sw_counter[0x20];
1417 u8 reserved_at_100[0xc];
1418 u8 log_wq_stride[0x4];
1419 u8 reserved_at_110[0x3];
1420 u8 log_wq_pg_sz[0x5];
1421 u8 reserved_at_118[0x3];
1423 u8 dbr_umem_valid[0x1];
1424 u8 wq_umem_valid[0x1];
1425 u8 reserved_at_122[0x1];
1426 u8 log_hairpin_num_packets[0x5];
1427 u8 reserved_at_128[0x3];
1428 u8 log_hairpin_data_sz[0x5];
1429 u8 reserved_at_130[0x4];
1430 u8 single_wqe_log_num_of_strides[0x4];
1431 u8 two_byte_shift_en[0x1];
1432 u8 reserved_at_139[0x4];
1433 u8 single_stride_log_num_of_bytes[0x3];
1434 u8 dbr_umem_id[0x20];
1435 u8 wq_umem_id[0x20];
1436 u8 wq_umem_offset[0x40];
1437 u8 reserved_at_1c0[0x440];
1441 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1442 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1446 MLX5_RQC_STATE_RST = 0x0,
1447 MLX5_RQC_STATE_RDY = 0x1,
1448 MLX5_RQC_STATE_ERR = 0x3,
1451 struct mlx5_ifc_rqc_bits {
1453 u8 delay_drop_en[0x1];
1454 u8 scatter_fcs[0x1];
1456 u8 mem_rq_type[0x4];
1458 u8 reserved_at_c[0x1];
1459 u8 flush_in_error_en[0x1];
1461 u8 reserved_at_f[0x11];
1462 u8 reserved_at_20[0x8];
1463 u8 user_index[0x18];
1464 u8 reserved_at_40[0x8];
1466 u8 counter_set_id[0x8];
1467 u8 reserved_at_68[0x18];
1468 u8 reserved_at_80[0x8];
1470 u8 reserved_at_a0[0x8];
1471 u8 hairpin_peer_sq[0x18];
1472 u8 reserved_at_c0[0x10];
1473 u8 hairpin_peer_vhca[0x10];
1474 u8 reserved_at_e0[0xa0];
1475 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1478 struct mlx5_ifc_create_rq_out_bits {
1480 u8 reserved_at_8[0x18];
1482 u8 reserved_at_40[0x8];
1484 u8 reserved_at_60[0x20];
1487 struct mlx5_ifc_create_rq_in_bits {
1490 u8 reserved_at_20[0x10];
1492 u8 reserved_at_40[0xc0];
1493 struct mlx5_ifc_rqc_bits ctx;
1496 struct mlx5_ifc_modify_rq_out_bits {
1498 u8 reserved_at_8[0x18];
1500 u8 reserved_at_40[0x40];
1503 struct mlx5_ifc_create_tis_out_bits {
1505 u8 reserved_at_8[0x18];
1507 u8 reserved_at_40[0x8];
1509 u8 reserved_at_60[0x20];
1512 struct mlx5_ifc_create_tis_in_bits {
1515 u8 reserved_at_20[0x10];
1517 u8 reserved_at_40[0xc0];
1518 struct mlx5_ifc_tisc_bits ctx;
1522 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1523 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1524 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1525 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1528 struct mlx5_ifc_modify_rq_in_bits {
1531 u8 reserved_at_20[0x10];
1534 u8 reserved_at_44[0x4];
1536 u8 reserved_at_60[0x20];
1537 u8 modify_bitmask[0x40];
1538 u8 reserved_at_c0[0x40];
1539 struct mlx5_ifc_rqc_bits ctx;
1543 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1544 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1545 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1546 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1547 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1550 struct mlx5_ifc_rx_hash_field_select_bits {
1551 u8 l3_prot_type[0x1];
1552 u8 l4_prot_type[0x1];
1553 u8 selected_fields[0x1e];
1557 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1558 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1562 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1563 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1567 MLX5_RX_HASH_FN_NONE = 0x0,
1568 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1569 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1573 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1574 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1578 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1579 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1582 struct mlx5_ifc_tirc_bits {
1583 u8 reserved_at_0[0x20];
1585 u8 reserved_at_24[0x1c];
1586 u8 reserved_at_40[0x40];
1587 u8 reserved_at_80[0x4];
1588 u8 lro_timeout_period_usecs[0x10];
1589 u8 lro_enable_mask[0x4];
1590 u8 lro_max_msg_sz[0x8];
1591 u8 reserved_at_a0[0x40];
1592 u8 reserved_at_e0[0x8];
1593 u8 inline_rqn[0x18];
1594 u8 rx_hash_symmetric[0x1];
1595 u8 reserved_at_101[0x1];
1596 u8 tunneled_offload_en[0x1];
1597 u8 reserved_at_103[0x5];
1598 u8 indirect_table[0x18];
1600 u8 reserved_at_124[0x2];
1601 u8 self_lb_block[0x2];
1602 u8 transport_domain[0x18];
1603 u8 rx_hash_toeplitz_key[10][0x20];
1604 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1605 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1606 u8 reserved_at_2c0[0x4c0];
1609 struct mlx5_ifc_create_tir_out_bits {
1611 u8 reserved_at_8[0x18];
1613 u8 reserved_at_40[0x8];
1615 u8 reserved_at_60[0x20];
1618 struct mlx5_ifc_create_tir_in_bits {
1621 u8 reserved_at_20[0x10];
1623 u8 reserved_at_40[0xc0];
1624 struct mlx5_ifc_tirc_bits ctx;
1627 struct mlx5_ifc_rq_num_bits {
1628 u8 reserved_at_0[0x8];
1632 struct mlx5_ifc_rqtc_bits {
1633 u8 reserved_at_0[0xa0];
1634 u8 reserved_at_a0[0x10];
1635 u8 rqt_max_size[0x10];
1636 u8 reserved_at_c0[0x10];
1637 u8 rqt_actual_size[0x10];
1638 u8 reserved_at_e0[0x6a0];
1639 struct mlx5_ifc_rq_num_bits rq_num[];
1642 struct mlx5_ifc_create_rqt_out_bits {
1644 u8 reserved_at_8[0x18];
1646 u8 reserved_at_40[0x8];
1648 u8 reserved_at_60[0x20];
1652 #pragma GCC diagnostic ignored "-Wpedantic"
1654 struct mlx5_ifc_create_rqt_in_bits {
1657 u8 reserved_at_20[0x10];
1659 u8 reserved_at_40[0xc0];
1660 struct mlx5_ifc_rqtc_bits rqt_context;
1663 #pragma GCC diagnostic error "-Wpedantic"
1667 MLX5_SQC_STATE_RST = 0x0,
1668 MLX5_SQC_STATE_RDY = 0x1,
1669 MLX5_SQC_STATE_ERR = 0x3,
1672 struct mlx5_ifc_sqc_bits {
1676 u8 flush_in_error_en[0x1];
1677 u8 allow_multi_pkt_send_wqe[0x1];
1678 u8 min_wqe_inline_mode[0x3];
1683 u8 reserved_at_f[0x11];
1684 u8 reserved_at_20[0x8];
1685 u8 user_index[0x18];
1686 u8 reserved_at_40[0x8];
1688 u8 reserved_at_60[0x8];
1689 u8 hairpin_peer_rq[0x18];
1690 u8 reserved_at_80[0x10];
1691 u8 hairpin_peer_vhca[0x10];
1692 u8 reserved_at_a0[0x50];
1693 u8 packet_pacing_rate_limit_index[0x10];
1694 u8 tis_lst_sz[0x10];
1695 u8 reserved_at_110[0x10];
1696 u8 reserved_at_120[0x40];
1697 u8 reserved_at_160[0x8];
1699 struct mlx5_ifc_wq_bits wq;
1702 struct mlx5_ifc_query_sq_in_bits {
1704 u8 reserved_at_10[0x10];
1705 u8 reserved_at_20[0x10];
1707 u8 reserved_at_40[0x8];
1709 u8 reserved_at_60[0x20];
1712 struct mlx5_ifc_modify_sq_out_bits {
1714 u8 reserved_at_8[0x18];
1716 u8 reserved_at_40[0x40];
1719 struct mlx5_ifc_modify_sq_in_bits {
1722 u8 reserved_at_20[0x10];
1725 u8 reserved_at_44[0x4];
1727 u8 reserved_at_60[0x20];
1728 u8 modify_bitmask[0x40];
1729 u8 reserved_at_c0[0x40];
1730 struct mlx5_ifc_sqc_bits ctx;
1733 struct mlx5_ifc_create_sq_out_bits {
1735 u8 reserved_at_8[0x18];
1737 u8 reserved_at_40[0x8];
1739 u8 reserved_at_60[0x20];
1742 struct mlx5_ifc_create_sq_in_bits {
1745 u8 reserved_at_20[0x10];
1747 u8 reserved_at_40[0xc0];
1748 struct mlx5_ifc_sqc_bits ctx;
1752 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
1753 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
1754 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
1755 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
1756 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
1759 struct mlx5_ifc_flow_meter_parameters_bits {
1760 u8 valid[0x1]; // 00h
1761 u8 bucket_overflow[0x1];
1762 u8 start_color[0x2];
1763 u8 both_buckets_on_green[0x1];
1765 u8 reserved_at_1[0x19];
1766 u8 reserved_at_2[0x20]; //04h
1767 u8 reserved_at_3[0x3];
1768 u8 cbs_exponent[0x5]; // 08h
1769 u8 cbs_mantissa[0x8];
1770 u8 reserved_at_4[0x3];
1771 u8 cir_exponent[0x5];
1772 u8 cir_mantissa[0x8];
1773 u8 reserved_at_5[0x20]; // 0Ch
1774 u8 reserved_at_6[0x3];
1775 u8 ebs_exponent[0x5]; // 10h
1776 u8 ebs_mantissa[0x8];
1777 u8 reserved_at_7[0x3];
1778 u8 eir_exponent[0x5];
1779 u8 eir_mantissa[0x8];
1780 u8 reserved_at_8[0x60]; // 14h-1Ch
1783 /* CQE format mask. */
1784 #define MLX5E_CQE_FORMAT_MASK 0xc
1787 #define MLX5_OPC_MOD_MPW 0x01
1789 /* Compressed Rx CQE structure. */
1790 struct mlx5_mini_cqe8 {
1792 uint32_t rx_hash_result;
1795 uint16_t stride_idx;
1798 uint16_t wqe_counter;
1799 uint8_t s_wqe_opcode;
1806 /* srTCM PRM flow meter parameters. */
1808 MLX5_FLOW_COLOR_RED = 0,
1809 MLX5_FLOW_COLOR_YELLOW,
1810 MLX5_FLOW_COLOR_GREEN,
1811 MLX5_FLOW_COLOR_UNDEFINED,
1814 /* Maximum value of srTCM metering parameters. */
1815 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
1816 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
1817 #define MLX5_SRTCM_EBS_MAX 0
1820 * Convert a user mark to flow mark.
1823 * Mark value to convert.
1826 * Converted mark value.
1828 static inline uint32_t
1829 mlx5_flow_mark_set(uint32_t val)
1834 * Add one to the user value to differentiate un-marked flows from
1835 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
1836 * remains untouched.
1838 if (val != MLX5_FLOW_MARK_DEFAULT)
1840 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1842 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
1843 * word, byte-swapped by the kernel on little-endian systems. In this
1844 * case, left-shifting the resulting big-endian value ensures the
1845 * least significant 24 bits are retained when converting it back.
1847 ret = rte_cpu_to_be_32(val) >> 8;
1855 * Convert a mark to user mark.
1858 * Mark value to convert.
1861 * Converted mark value.
1863 static inline uint32_t
1864 mlx5_flow_mark_get(uint32_t val)
1867 * Subtract one from the retrieved value. It was added by
1868 * mlx5_flow_mark_set() to distinguish unmarked flows.
1870 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1871 return (val >> 8) - 1;
1877 #endif /* RTE_PMD_MLX5_PRM_H_ */