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34 #ifndef RTE_PMD_MLX5_PRM_H_
35 #define RTE_PMD_MLX5_PRM_H_
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/mlx5_hw.h>
46 #pragma GCC diagnostic error "-Wpedantic"
49 #include "mlx5_autoconf.h"
51 /* Get CQE owner bit. */
52 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
55 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
58 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
60 /* Get CQE solicited event. */
61 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
63 /* Invalidate a CQE. */
64 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
66 /* CQE value to inform that VLAN is stripped. */
67 #define MLX5_CQE_VLAN_STRIPPED 0x1
69 /* Maximum number of packets a multi-packet WQE can handle. */
70 #define MLX5_MPW_DSEG_MAX 5
73 #define MLX5_WQE_DWORD_SIZE 16
76 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
78 /* Compute the number of DS. */
79 #define MLX5_WQE_DS(n) \
80 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
82 /* Room for inline data in multi-packet WQE. */
83 #define MLX5_MWQE64_INL_DATA 28
85 #ifndef HAVE_VERBS_MLX5_OPCODE_TSO
86 #define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */
90 #define MLX5_CQE_RX_IPV4_PACKET (1u << 2)
93 #define MLX5_CQE_RX_IPV6_PACKET (1u << 3)
95 /* Outer IPv4 packet. */
96 #define MLX5_CQE_RX_OUTER_IPV4_PACKET (1u << 7)
98 /* Outer IPv6 packet. */
99 #define MLX5_CQE_RX_OUTER_IPV6_PACKET (1u << 8)
101 /* Tunnel packet bit in the CQE. */
102 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 4)
104 /* Outer IP checksum OK. */
105 #define MLX5_CQE_RX_OUTER_IP_CSUM_OK (1u << 5)
107 /* Outer UDP header and checksum OK. */
108 #define MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK (1u << 6)
110 /* INVALID is used by packets matching no flow rules. */
111 #define MLX5_FLOW_MARK_INVALID 0
113 /* Maximum allowed value to mark a packet. */
114 #define MLX5_FLOW_MARK_MAX 0xfffff0
116 /* Default mark value used when none is provided. */
117 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
119 /* Subset of struct mlx5_wqe_eth_seg. */
120 struct mlx5_wqe_eth_seg_small {
126 uint16_t inline_hdr_sz;
127 uint8_t inline_hdr[2];
130 struct mlx5_wqe_inl_small {
135 /* Small common part of the WQE. */
138 struct mlx5_wqe_eth_seg_small eseg;
147 /* MPW session status. */
148 enum mlx5_mpw_state {
149 MLX5_MPW_STATE_OPENED,
150 MLX5_MPW_INL_STATE_OPENED,
151 MLX5_MPW_STATE_CLOSED,
154 /* MPW session descriptor. */
156 enum mlx5_mpw_state state;
159 unsigned int total_len;
160 volatile struct mlx5_wqe *wqe;
162 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
163 volatile uint8_t *raw;
167 /* CQ element structure - should be equal to the cache line size */
169 #if (RTE_CACHE_LINE_SIZE == 128)
174 uint32_t rx_hash_res;
175 uint8_t rx_hash_type;
178 uint8_t l4_hdr_type_etc;
183 uint32_t sop_drop_qpn;
184 uint16_t wqe_counter;
190 * Convert a user mark to flow mark.
193 * Mark value to convert.
196 * Converted mark value.
198 static inline uint32_t
199 mlx5_flow_mark_set(uint32_t val)
204 * Add one to the user value to differentiate un-marked flows from
208 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
210 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
211 * word, byte-swapped by the kernel on little-endian systems. In this
212 * case, left-shifting the resulting big-endian value ensures the
213 * least significant 24 bits are retained when converting it back.
215 ret = rte_cpu_to_be_32(val) >> 8;
219 assert(ret <= MLX5_FLOW_MARK_MAX);
224 * Convert a mark to user mark.
227 * Mark value to convert.
230 * Converted mark value.
232 static inline uint32_t
233 mlx5_flow_mark_get(uint32_t val)
236 * Subtract one from the retrieved value. It was added by
237 * mlx5_flow_mark_set() to distinguish unmarked flows.
239 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
240 return (val >> 8) - 1;
246 #endif /* RTE_PMD_MLX5_PRM_H_ */