1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* WQE Segment sizes in bytes. */
43 #define MLX5_WSEG_SIZE 16u
44 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
45 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
46 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
48 /* WQE/WQEBB size in bytes. */
49 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
52 * Max size of a WQE session.
53 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
54 * the WQE size field in Control Segment is 6 bits wide.
56 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
59 * Default minimum number of Tx queues for inlining packets.
60 * If there are less queues as specified we assume we have
61 * no enough CPU resources (cycles) to perform inlining,
62 * the PCIe throughput is not supposed as bottleneck and
63 * inlining is disabled.
65 #define MLX5_INLINE_MAX_TXQS 8u
66 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
69 * Default packet length threshold to be inlined with
70 * enhanced MPW. If packet length exceeds the threshold
71 * the data are not inlined. Should be aligned in WQEBB
72 * boundary with accounting the title Control and Ethernet
75 #define MLX5_EMPW_DEF_INLINE_LEN (3U * MLX5_WQE_SIZE + \
76 MLX5_DSEG_MIN_INLINE_SIZE - \
79 * Maximal inline data length sent with enhanced MPW.
80 * Is based on maximal WQE size.
82 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
83 MLX5_WQE_CSEG_SIZE - \
84 MLX5_WQE_ESEG_SIZE - \
85 MLX5_WQE_DSEG_SIZE + \
86 MLX5_DSEG_MIN_INLINE_SIZE)
88 * Minimal amount of packets to be sent with EMPW.
89 * This limits the minimal required size of sent EMPW.
90 * If there are no enough resources to built minimal
91 * EMPW the sending loop exits.
93 #define MLX5_EMPW_MIN_PACKETS (2 + 3 * 4)
94 #define MLX5_EMPW_MAX_PACKETS ((MLX5_WQE_SIZE_MAX - \
95 MLX5_WQE_CSEG_SIZE - \
96 MLX5_WQE_ESEG_SIZE) / \
99 * Default packet length threshold to be inlined with
100 * ordinary SEND. Inlining saves the MR key search
101 * and extra PCIe data fetch transaction, but eats the
104 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
105 MLX5_ESEG_MIN_INLINE_SIZE - \
106 MLX5_WQE_CSEG_SIZE - \
107 MLX5_WQE_ESEG_SIZE - \
110 * Maximal inline data length sent with ordinary SEND.
111 * Is based on maximal WQE size.
113 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
114 MLX5_WQE_CSEG_SIZE - \
115 MLX5_WQE_ESEG_SIZE - \
116 MLX5_WQE_DSEG_SIZE + \
117 MLX5_ESEG_MIN_INLINE_SIZE)
119 /* Missed in mlv5dv.h, should define here. */
120 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
122 /* CQE value to inform that VLAN is stripped. */
123 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
126 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
129 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
132 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
135 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
138 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
140 /* IP is fragmented. */
141 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
143 /* L2 header is valid. */
144 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
146 /* L3 header is valid. */
147 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
149 /* L4 header is valid. */
150 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
152 /* Outer packet, 0 IPv4, 1 IPv6. */
153 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
155 /* Tunnel packet bit in the CQE. */
156 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
158 /* Inner L3 checksum offload (Tunneled packets only). */
159 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
161 /* Inner L4 checksum offload (Tunneled packets only). */
162 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
164 /* Outer L4 type is TCP. */
165 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
167 /* Outer L4 type is UDP. */
168 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
170 /* Outer L3 type is IPV4. */
171 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
173 /* Outer L3 type is IPV6. */
174 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
176 /* Inner L4 type is TCP. */
177 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
179 /* Inner L4 type is UDP. */
180 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
182 /* Inner L3 type is IPV4. */
183 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
185 /* Inner L3 type is IPV6. */
186 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
188 /* VLAN insertion flag. */
189 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
191 /* Data inline segment flag. */
192 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
194 /* Is flow mark valid. */
195 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
196 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
198 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
201 /* INVALID is used by packets matching no flow rules. */
202 #define MLX5_FLOW_MARK_INVALID 0
204 /* Maximum allowed value to mark a packet. */
205 #define MLX5_FLOW_MARK_MAX 0xfffff0
207 /* Default mark value used when none is provided. */
208 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
210 /* Maximum number of DS in WQE. Limited by 6-bit field. */
211 #define MLX5_DSEG_MAX 63
213 /* The completion mode offset in the WQE control segment line 2. */
214 #define MLX5_COMP_MODE_OFFSET 2
216 /* Amount of data bytes in minimal inline data segment. */
217 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
219 /* Amount of data bytes in minimal inline eth segment. */
220 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
222 /* Amount of data bytes after eth data segment. */
223 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
225 /* Completion mode. */
226 enum mlx5_completion_mode {
227 MLX5_COMP_ONLY_ERR = 0x0,
228 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
229 MLX5_COMP_ALWAYS = 0x2,
230 MLX5_COMP_CQE_AND_EQE = 0x3,
237 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
240 /* WQE Control segment. */
241 struct mlx5_wqe_cseg {
246 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
248 /* Header of data segment. Minimal size Data Segment */
249 struct mlx5_wqe_dseg {
252 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
260 /* Subset of struct WQE Ethernet Segment. */
261 struct mlx5_wqe_eseg {
269 uint16_t inline_hdr_sz;
271 uint16_t inline_data;
278 uint32_t flow_metadata;
284 /* The title WQEBB, header of WQE. */
287 struct mlx5_wqe_cseg cseg;
290 struct mlx5_wqe_eseg eseg;
292 struct mlx5_wqe_dseg dseg[2];
293 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
297 /* WQE for Multi-Packet RQ. */
298 struct mlx5_wqe_mprq {
299 struct mlx5_wqe_srq_next_seg next_seg;
300 struct mlx5_wqe_data_seg dseg;
303 #define MLX5_MPRQ_LEN_MASK 0x000ffff
304 #define MLX5_MPRQ_LEN_SHIFT 0
305 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
306 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
307 #define MLX5_MPRQ_FILLER_MASK 0x80000000
308 #define MLX5_MPRQ_FILLER_SHIFT 31
310 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
312 /* CQ element structure - should be equal to the cache line size */
314 #if (RTE_CACHE_LINE_SIZE == 128)
321 uint32_t rx_hash_res;
322 uint8_t rx_hash_type;
324 uint16_t hdr_type_etc;
329 uint32_t sop_drop_qpn;
330 uint16_t wqe_counter;
335 /* Adding direct verbs to data-path. */
337 /* CQ sequence number mask. */
338 #define MLX5_CQ_SQN_MASK 0x3
340 /* CQ sequence number index. */
341 #define MLX5_CQ_SQN_OFFSET 28
343 /* CQ doorbell index mask. */
344 #define MLX5_CI_MASK 0xffffff
346 /* CQ doorbell offset. */
347 #define MLX5_CQ_ARM_DB 1
349 /* CQ doorbell offset*/
350 #define MLX5_CQ_DOORBELL 0x20
352 /* CQE format value. */
353 #define MLX5_COMPRESSED 0x3
355 /* Write a specific data value to a field. */
356 #define MLX5_MODIFICATION_TYPE_SET 1
358 /* Add a specific data value to a field. */
359 #define MLX5_MODIFICATION_TYPE_ADD 2
361 /* The field of packet to be modified. */
362 enum mlx5_modification_field {
363 MLX5_MODI_OUT_SMAC_47_16 = 1,
364 MLX5_MODI_OUT_SMAC_15_0,
365 MLX5_MODI_OUT_ETHERTYPE,
366 MLX5_MODI_OUT_DMAC_47_16,
367 MLX5_MODI_OUT_DMAC_15_0,
368 MLX5_MODI_OUT_IP_DSCP,
369 MLX5_MODI_OUT_TCP_FLAGS,
370 MLX5_MODI_OUT_TCP_SPORT,
371 MLX5_MODI_OUT_TCP_DPORT,
372 MLX5_MODI_OUT_IPV4_TTL,
373 MLX5_MODI_OUT_UDP_SPORT,
374 MLX5_MODI_OUT_UDP_DPORT,
375 MLX5_MODI_OUT_SIPV6_127_96,
376 MLX5_MODI_OUT_SIPV6_95_64,
377 MLX5_MODI_OUT_SIPV6_63_32,
378 MLX5_MODI_OUT_SIPV6_31_0,
379 MLX5_MODI_OUT_DIPV6_127_96,
380 MLX5_MODI_OUT_DIPV6_95_64,
381 MLX5_MODI_OUT_DIPV6_63_32,
382 MLX5_MODI_OUT_DIPV6_31_0,
385 MLX5_MODI_IN_SMAC_47_16 = 0x31,
386 MLX5_MODI_IN_SMAC_15_0,
387 MLX5_MODI_IN_ETHERTYPE,
388 MLX5_MODI_IN_DMAC_47_16,
389 MLX5_MODI_IN_DMAC_15_0,
390 MLX5_MODI_IN_IP_DSCP,
391 MLX5_MODI_IN_TCP_FLAGS,
392 MLX5_MODI_IN_TCP_SPORT,
393 MLX5_MODI_IN_TCP_DPORT,
394 MLX5_MODI_IN_IPV4_TTL,
395 MLX5_MODI_IN_UDP_SPORT,
396 MLX5_MODI_IN_UDP_DPORT,
397 MLX5_MODI_IN_SIPV6_127_96,
398 MLX5_MODI_IN_SIPV6_95_64,
399 MLX5_MODI_IN_SIPV6_63_32,
400 MLX5_MODI_IN_SIPV6_31_0,
401 MLX5_MODI_IN_DIPV6_127_96,
402 MLX5_MODI_IN_DIPV6_95_64,
403 MLX5_MODI_IN_DIPV6_63_32,
404 MLX5_MODI_IN_DIPV6_31_0,
407 MLX5_MODI_OUT_IPV6_HOPLIMIT,
408 MLX5_MODI_IN_IPV6_HOPLIMIT,
409 MLX5_MODI_META_DATA_REG_A,
410 MLX5_MODI_META_DATA_REG_B = 0x50,
411 MLX5_MODI_META_REG_C_0,
412 MLX5_MODI_META_REG_C_1,
413 MLX5_MODI_META_REG_C_2,
414 MLX5_MODI_META_REG_C_3,
415 MLX5_MODI_META_REG_C_4,
416 MLX5_MODI_META_REG_C_5,
417 MLX5_MODI_META_REG_C_6,
418 MLX5_MODI_META_REG_C_7,
419 MLX5_MODI_OUT_TCP_SEQ_NUM,
420 MLX5_MODI_IN_TCP_SEQ_NUM,
421 MLX5_MODI_OUT_TCP_ACK_NUM,
422 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
425 /* Modification sub command. */
426 struct mlx5_modification_cmd {
430 unsigned int length:5;
431 unsigned int rsvd0:3;
432 unsigned int offset:5;
433 unsigned int rsvd1:3;
434 unsigned int field:12;
435 unsigned int action_type:4;
444 typedef uint32_t u32;
445 typedef uint16_t u16;
448 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
449 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
450 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
451 (&(__mlx5_nullp(typ)->fld)))
452 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
453 (__mlx5_bit_off(typ, fld) & 0x1f))
454 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
455 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
456 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
457 __mlx5_dw_bit_off(typ, fld))
458 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
459 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
460 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
461 (__mlx5_bit_off(typ, fld) & 0xf))
462 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
463 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
464 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
465 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
466 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
468 /* insert a value to a struct */
469 #define MLX5_SET(typ, p, fld, v) \
472 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
473 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
474 __mlx5_dw_off(typ, fld))) & \
475 (~__mlx5_dw_mask(typ, fld))) | \
476 (((_v) & __mlx5_mask(typ, fld)) << \
477 __mlx5_dw_bit_off(typ, fld))); \
480 #define MLX5_SET64(typ, p, fld, v) \
482 assert(__mlx5_bit_sz(typ, fld) == 64); \
483 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
484 rte_cpu_to_be_64(v); \
487 #define MLX5_GET(typ, p, fld) \
488 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
489 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
490 __mlx5_mask(typ, fld))
491 #define MLX5_GET16(typ, p, fld) \
492 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
493 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
494 __mlx5_mask16(typ, fld))
495 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
496 __mlx5_64_off(typ, fld)))
497 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
499 struct mlx5_ifc_fte_match_set_misc_bits {
500 u8 gre_c_present[0x1];
501 u8 reserved_at_1[0x1];
502 u8 gre_k_present[0x1];
503 u8 gre_s_present[0x1];
504 u8 source_vhci_port[0x4];
506 u8 reserved_at_20[0x10];
507 u8 source_port[0x10];
508 u8 outer_second_prio[0x3];
509 u8 outer_second_cfi[0x1];
510 u8 outer_second_vid[0xc];
511 u8 inner_second_prio[0x3];
512 u8 inner_second_cfi[0x1];
513 u8 inner_second_vid[0xc];
514 u8 outer_second_cvlan_tag[0x1];
515 u8 inner_second_cvlan_tag[0x1];
516 u8 outer_second_svlan_tag[0x1];
517 u8 inner_second_svlan_tag[0x1];
518 u8 reserved_at_64[0xc];
519 u8 gre_protocol[0x10];
523 u8 reserved_at_b8[0x8];
524 u8 reserved_at_c0[0x20];
525 u8 reserved_at_e0[0xc];
526 u8 outer_ipv6_flow_label[0x14];
527 u8 reserved_at_100[0xc];
528 u8 inner_ipv6_flow_label[0x14];
529 u8 reserved_at_120[0xe0];
532 struct mlx5_ifc_ipv4_layout_bits {
533 u8 reserved_at_0[0x60];
537 struct mlx5_ifc_ipv6_layout_bits {
541 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
542 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
543 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
544 u8 reserved_at_0[0x80];
547 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
566 u8 reserved_at_c0[0x20];
569 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
570 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
573 struct mlx5_ifc_fte_match_mpls_bits {
580 struct mlx5_ifc_fte_match_set_misc2_bits {
581 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
582 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
583 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
584 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
585 u8 reserved_at_80[0x100];
586 u8 metadata_reg_a[0x20];
587 u8 reserved_at_1a0[0x60];
590 struct mlx5_ifc_fte_match_set_misc3_bits {
591 u8 inner_tcp_seq_num[0x20];
592 u8 outer_tcp_seq_num[0x20];
593 u8 inner_tcp_ack_num[0x20];
594 u8 outer_tcp_ack_num[0x20];
595 u8 reserved_at_auto1[0x8];
596 u8 outer_vxlan_gpe_vni[0x18];
597 u8 outer_vxlan_gpe_next_protocol[0x8];
598 u8 outer_vxlan_gpe_flags[0x8];
599 u8 reserved_at_a8[0x10];
600 u8 icmp_header_data[0x20];
601 u8 icmpv6_header_data[0x20];
606 u8 reserved_at_1a0[0xe0];
610 struct mlx5_ifc_fte_match_param_bits {
611 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
612 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
613 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
614 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
615 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
619 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
620 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
621 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
622 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
623 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
627 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
628 MLX5_CMD_OP_CREATE_MKEY = 0x200,
629 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
630 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
631 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
635 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
639 struct mlx5_ifc_alloc_flow_counter_out_bits {
641 u8 reserved_at_8[0x18];
643 u8 flow_counter_id[0x20];
644 u8 reserved_at_60[0x20];
647 struct mlx5_ifc_alloc_flow_counter_in_bits {
649 u8 reserved_at_10[0x10];
650 u8 reserved_at_20[0x10];
652 u8 flow_counter_id[0x20];
653 u8 reserved_at_40[0x18];
654 u8 flow_counter_bulk[0x8];
657 struct mlx5_ifc_dealloc_flow_counter_out_bits {
659 u8 reserved_at_8[0x18];
661 u8 reserved_at_40[0x40];
664 struct mlx5_ifc_dealloc_flow_counter_in_bits {
666 u8 reserved_at_10[0x10];
667 u8 reserved_at_20[0x10];
669 u8 flow_counter_id[0x20];
670 u8 reserved_at_60[0x20];
673 struct mlx5_ifc_traffic_counter_bits {
678 struct mlx5_ifc_query_flow_counter_out_bits {
680 u8 reserved_at_8[0x18];
682 u8 reserved_at_40[0x40];
683 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
686 struct mlx5_ifc_query_flow_counter_in_bits {
688 u8 reserved_at_10[0x10];
689 u8 reserved_at_20[0x10];
691 u8 reserved_at_40[0x20];
695 u8 dump_to_memory[0x1];
696 u8 num_of_counters[0x1e];
697 u8 flow_counter_id[0x20];
700 struct mlx5_ifc_mkc_bits {
701 u8 reserved_at_0[0x1];
703 u8 reserved_at_2[0x1];
704 u8 access_mode_4_2[0x3];
705 u8 reserved_at_6[0x7];
706 u8 relaxed_ordering_write[0x1];
707 u8 reserved_at_e[0x1];
708 u8 small_fence_on_rdma_read_response[0x1];
715 u8 access_mode_1_0[0x2];
716 u8 reserved_at_18[0x8];
721 u8 reserved_at_40[0x20];
726 u8 reserved_at_63[0x2];
727 u8 expected_sigerr_count[0x1];
728 u8 reserved_at_66[0x1];
736 u8 bsf_octword_size[0x20];
738 u8 reserved_at_120[0x80];
740 u8 translations_octword_size[0x20];
742 u8 reserved_at_1c0[0x1b];
743 u8 log_page_size[0x5];
745 u8 reserved_at_1e0[0x20];
748 struct mlx5_ifc_create_mkey_out_bits {
750 u8 reserved_at_8[0x18];
754 u8 reserved_at_40[0x8];
757 u8 reserved_at_60[0x20];
760 struct mlx5_ifc_create_mkey_in_bits {
762 u8 reserved_at_10[0x10];
764 u8 reserved_at_20[0x10];
767 u8 reserved_at_40[0x20];
770 u8 reserved_at_61[0x1f];
772 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
774 u8 reserved_at_280[0x80];
776 u8 translations_octword_actual_size[0x20];
778 u8 mkey_umem_id[0x20];
780 u8 mkey_umem_offset[0x40];
782 u8 reserved_at_380[0x500];
784 u8 klm_pas_mtt[][0x20];
788 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
789 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
790 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
794 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
795 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
799 MLX5_CAP_INLINE_MODE_L2,
800 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
801 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
805 MLX5_INLINE_MODE_NONE,
808 MLX5_INLINE_MODE_TCP_UDP,
809 MLX5_INLINE_MODE_RESERVED4,
810 MLX5_INLINE_MODE_INNER_L2,
811 MLX5_INLINE_MODE_INNER_IP,
812 MLX5_INLINE_MODE_INNER_TCP_UDP,
815 struct mlx5_ifc_cmd_hca_cap_bits {
816 u8 reserved_at_0[0x30];
818 u8 reserved_at_40[0x40];
819 u8 log_max_srq_sz[0x8];
820 u8 log_max_qp_sz[0x8];
821 u8 reserved_at_90[0xb];
823 u8 reserved_at_a0[0xb];
825 u8 reserved_at_b0[0x10];
826 u8 reserved_at_c0[0x8];
827 u8 log_max_cq_sz[0x8];
828 u8 reserved_at_d0[0xb];
830 u8 log_max_eq_sz[0x8];
831 u8 reserved_at_e8[0x2];
832 u8 log_max_mkey[0x6];
833 u8 reserved_at_f0[0x8];
834 u8 dump_fill_mkey[0x1];
835 u8 reserved_at_f9[0x3];
837 u8 max_indirection[0x8];
838 u8 fixed_buffer_size[0x1];
839 u8 log_max_mrw_sz[0x7];
840 u8 force_teardown[0x1];
841 u8 reserved_at_111[0x1];
842 u8 log_max_bsf_list_size[0x6];
843 u8 umr_extended_translation_offset[0x1];
845 u8 log_max_klm_list_size[0x6];
846 u8 reserved_at_120[0xa];
847 u8 log_max_ra_req_dc[0x6];
848 u8 reserved_at_130[0xa];
849 u8 log_max_ra_res_dc[0x6];
850 u8 reserved_at_140[0xa];
851 u8 log_max_ra_req_qp[0x6];
852 u8 reserved_at_150[0xa];
853 u8 log_max_ra_res_qp[0x6];
855 u8 cc_query_allowed[0x1];
856 u8 cc_modify_allowed[0x1];
858 u8 cache_line_128byte[0x1];
859 u8 reserved_at_165[0xa];
861 u8 gid_table_size[0x10];
862 u8 out_of_seq_cnt[0x1];
863 u8 vport_counters[0x1];
864 u8 retransmission_q_counters[0x1];
866 u8 modify_rq_counter_set_id[0x1];
867 u8 rq_delay_drop[0x1];
869 u8 pkey_table_size[0x10];
870 u8 vport_group_manager[0x1];
871 u8 vhca_group_manager[0x1];
874 u8 vnic_env_queue_counters[0x1];
876 u8 nic_flow_table[0x1];
877 u8 eswitch_manager[0x1];
878 u8 device_memory[0x1];
881 u8 local_ca_ack_delay[0x5];
882 u8 port_module_event[0x1];
883 u8 enhanced_error_q_counters[0x1];
885 u8 reserved_at_1b3[0x1];
886 u8 disable_link_up[0x1];
890 u8 reserved_at_1c0[0x1];
894 u8 reserved_at_1c8[0x4];
896 u8 temp_warn_event[0x1];
898 u8 general_notification_event[0x1];
899 u8 reserved_at_1d3[0x2];
903 u8 reserved_at_1d8[0x1];
911 u8 stat_rate_support[0x10];
912 u8 reserved_at_1f0[0xc];
914 u8 compact_address_vector[0x1];
916 u8 reserved_at_202[0x1];
917 u8 ipoib_enhanced_offloads[0x1];
918 u8 ipoib_basic_offloads[0x1];
919 u8 reserved_at_205[0x1];
920 u8 repeated_block_disabled[0x1];
921 u8 umr_modify_entity_size_disabled[0x1];
922 u8 umr_modify_atomic_disabled[0x1];
923 u8 umr_indirect_mkey_disabled[0x1];
925 u8 reserved_at_20c[0x3];
926 u8 drain_sigerr[0x1];
927 u8 cmdif_checksum[0x2];
929 u8 reserved_at_213[0x1];
930 u8 wq_signature[0x1];
931 u8 sctr_data_cqe[0x1];
932 u8 reserved_at_216[0x1];
938 u8 eth_net_offloads[0x1];
941 u8 reserved_at_21f[0x1];
944 u8 cq_moderation[0x1];
945 u8 reserved_at_223[0x3];
949 u8 reserved_at_229[0x1];
950 u8 scqe_break_moderation[0x1];
951 u8 cq_period_start_from_cqe[0x1];
953 u8 reserved_at_22d[0x1];
956 u8 umr_ptr_rlky[0x1];
958 u8 reserved_at_232[0x4];
961 u8 set_deth_sqpn[0x1];
962 u8 reserved_at_239[0x3];
968 u8 reserved_at_241[0x9];
970 u8 reserved_at_250[0x8];
973 u8 driver_version[0x1];
974 u8 pad_tx_eth_packet[0x1];
975 u8 reserved_at_263[0x8];
976 u8 log_bf_reg_size[0x5];
977 u8 reserved_at_270[0xb];
979 u8 num_lag_ports[0x4];
980 u8 reserved_at_280[0x10];
981 u8 max_wqe_sz_sq[0x10];
982 u8 reserved_at_2a0[0x10];
983 u8 max_wqe_sz_rq[0x10];
984 u8 max_flow_counter_31_16[0x10];
985 u8 max_wqe_sz_sq_dc[0x10];
986 u8 reserved_at_2e0[0x7];
988 u8 reserved_at_300[0x10];
989 u8 flow_counter_bulk_alloc[0x08];
991 u8 reserved_at_320[0x3];
992 u8 log_max_transport_domain[0x5];
993 u8 reserved_at_328[0x3];
995 u8 reserved_at_330[0xb];
996 u8 log_max_xrcd[0x5];
997 u8 nic_receive_steering_discard[0x1];
998 u8 receive_discard_vport_down[0x1];
999 u8 transmit_discard_vport_down[0x1];
1000 u8 reserved_at_343[0x5];
1001 u8 log_max_flow_counter_bulk[0x8];
1002 u8 max_flow_counter_15_0[0x10];
1004 u8 flow_counters_dump[0x1];
1005 u8 reserved_at_360[0x1];
1007 u8 reserved_at_368[0x3];
1009 u8 reserved_at_370[0x3];
1010 u8 log_max_tir[0x5];
1011 u8 reserved_at_378[0x3];
1012 u8 log_max_tis[0x5];
1013 u8 basic_cyclic_rcv_wqe[0x1];
1014 u8 reserved_at_381[0x2];
1015 u8 log_max_rmp[0x5];
1016 u8 reserved_at_388[0x3];
1017 u8 log_max_rqt[0x5];
1018 u8 reserved_at_390[0x3];
1019 u8 log_max_rqt_size[0x5];
1020 u8 reserved_at_398[0x3];
1021 u8 log_max_tis_per_sq[0x5];
1022 u8 ext_stride_num_range[0x1];
1023 u8 reserved_at_3a1[0x2];
1024 u8 log_max_stride_sz_rq[0x5];
1025 u8 reserved_at_3a8[0x3];
1026 u8 log_min_stride_sz_rq[0x5];
1027 u8 reserved_at_3b0[0x3];
1028 u8 log_max_stride_sz_sq[0x5];
1029 u8 reserved_at_3b8[0x3];
1030 u8 log_min_stride_sz_sq[0x5];
1032 u8 reserved_at_3c1[0x2];
1033 u8 log_max_hairpin_queues[0x5];
1034 u8 reserved_at_3c8[0x3];
1035 u8 log_max_hairpin_wq_data_sz[0x5];
1036 u8 reserved_at_3d0[0x3];
1037 u8 log_max_hairpin_num_packets[0x5];
1038 u8 reserved_at_3d8[0x3];
1039 u8 log_max_wq_sz[0x5];
1040 u8 nic_vport_change_event[0x1];
1041 u8 disable_local_lb_uc[0x1];
1042 u8 disable_local_lb_mc[0x1];
1043 u8 log_min_hairpin_wq_data_sz[0x5];
1044 u8 reserved_at_3e8[0x3];
1045 u8 log_max_vlan_list[0x5];
1046 u8 reserved_at_3f0[0x3];
1047 u8 log_max_current_mc_list[0x5];
1048 u8 reserved_at_3f8[0x3];
1049 u8 log_max_current_uc_list[0x5];
1050 u8 general_obj_types[0x40];
1051 u8 reserved_at_440[0x20];
1052 u8 reserved_at_460[0x10];
1053 u8 max_num_eqs[0x10];
1054 u8 reserved_at_480[0x3];
1055 u8 log_max_l2_table[0x5];
1056 u8 reserved_at_488[0x8];
1057 u8 log_uar_page_sz[0x10];
1058 u8 reserved_at_4a0[0x20];
1059 u8 device_frequency_mhz[0x20];
1060 u8 device_frequency_khz[0x20];
1061 u8 reserved_at_500[0x20];
1062 u8 num_of_uars_per_page[0x20];
1063 u8 flex_parser_protocols[0x20];
1064 u8 reserved_at_560[0x20];
1065 u8 reserved_at_580[0x3c];
1066 u8 mini_cqe_resp_stride_index[0x1];
1067 u8 cqe_128_always[0x1];
1068 u8 cqe_compression_128[0x1];
1069 u8 cqe_compression[0x1];
1070 u8 cqe_compression_timeout[0x10];
1071 u8 cqe_compression_max_num[0x10];
1072 u8 reserved_at_5e0[0x10];
1073 u8 tag_matching[0x1];
1074 u8 rndv_offload_rc[0x1];
1075 u8 rndv_offload_dc[0x1];
1076 u8 log_tag_matching_list_sz[0x5];
1077 u8 reserved_at_5f8[0x3];
1078 u8 log_max_xrq[0x5];
1079 u8 affiliate_nic_vport_criteria[0x8];
1080 u8 native_port_num[0x8];
1081 u8 num_vhca_ports[0x8];
1082 u8 reserved_at_618[0x6];
1083 u8 sw_owner_id[0x1];
1084 u8 reserved_at_61f[0x1e1];
1087 struct mlx5_ifc_qos_cap_bits {
1088 u8 packet_pacing[0x1];
1089 u8 esw_scheduling[0x1];
1090 u8 esw_bw_share[0x1];
1091 u8 esw_rate_limit[0x1];
1092 u8 reserved_at_4[0x1];
1093 u8 packet_pacing_burst_bound[0x1];
1094 u8 packet_pacing_typical_size[0x1];
1095 u8 flow_meter_srtcm[0x1];
1096 u8 reserved_at_8[0x8];
1097 u8 log_max_flow_meter[0x8];
1098 u8 flow_meter_reg_id[0x8];
1099 u8 reserved_at_25[0x20];
1100 u8 packet_pacing_max_rate[0x20];
1101 u8 packet_pacing_min_rate[0x20];
1102 u8 reserved_at_80[0x10];
1103 u8 packet_pacing_rate_table_size[0x10];
1104 u8 esw_element_type[0x10];
1105 u8 esw_tsar_type[0x10];
1106 u8 reserved_at_c0[0x10];
1107 u8 max_qos_para_vport[0x10];
1108 u8 max_tsar_bw_share[0x20];
1109 u8 reserved_at_100[0x6e8];
1112 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1116 u8 lro_psh_flag[0x1];
1117 u8 lro_time_stamp[0x1];
1118 u8 lro_max_msg_sz_mode[0x2];
1119 u8 wqe_vlan_insert[0x1];
1120 u8 self_lb_en_modifiable[0x1];
1123 u8 max_lso_cap[0x5];
1124 u8 multi_pkt_send_wqe[0x2];
1125 u8 wqe_inline_mode[0x2];
1126 u8 rss_ind_tbl_cap[0x4];
1128 u8 scatter_fcs[0x1];
1129 u8 enhanced_multi_pkt_send_wqe[0x1];
1130 u8 tunnel_lso_const_out_ip_id[0x1];
1131 u8 tunnel_lro_gre[0x1];
1132 u8 tunnel_lro_vxlan[0x1];
1133 u8 tunnel_stateless_gre[0x1];
1134 u8 tunnel_stateless_vxlan[0x1];
1138 u8 reserved_at_23[0xd];
1139 u8 max_vxlan_udp_ports[0x8];
1140 u8 reserved_at_38[0x6];
1141 u8 max_geneve_opt_len[0x1];
1142 u8 tunnel_stateless_geneve_rx[0x1];
1143 u8 reserved_at_40[0x10];
1144 u8 lro_min_mss_size[0x10];
1145 u8 reserved_at_60[0x120];
1146 u8 lro_timer_supported_periods[4][0x20];
1147 u8 reserved_at_200[0x600];
1150 union mlx5_ifc_hca_cap_union_bits {
1151 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1152 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1153 per_protocol_networking_offload_caps;
1154 struct mlx5_ifc_qos_cap_bits qos_cap;
1155 u8 reserved_at_0[0x8000];
1158 struct mlx5_ifc_query_hca_cap_out_bits {
1160 u8 reserved_at_8[0x18];
1162 u8 reserved_at_40[0x40];
1163 union mlx5_ifc_hca_cap_union_bits capability;
1166 struct mlx5_ifc_query_hca_cap_in_bits {
1168 u8 reserved_at_10[0x10];
1169 u8 reserved_at_20[0x10];
1171 u8 reserved_at_40[0x40];
1174 struct mlx5_ifc_mac_address_layout_bits {
1175 u8 reserved_at_0[0x10];
1176 u8 mac_addr_47_32[0x10];
1177 u8 mac_addr_31_0[0x20];
1180 struct mlx5_ifc_nic_vport_context_bits {
1181 u8 reserved_at_0[0x5];
1182 u8 min_wqe_inline_mode[0x3];
1183 u8 reserved_at_8[0x15];
1184 u8 disable_mc_local_lb[0x1];
1185 u8 disable_uc_local_lb[0x1];
1187 u8 arm_change_event[0x1];
1188 u8 reserved_at_21[0x1a];
1189 u8 event_on_mtu[0x1];
1190 u8 event_on_promisc_change[0x1];
1191 u8 event_on_vlan_change[0x1];
1192 u8 event_on_mc_address_change[0x1];
1193 u8 event_on_uc_address_change[0x1];
1194 u8 reserved_at_40[0xc];
1195 u8 affiliation_criteria[0x4];
1196 u8 affiliated_vhca_id[0x10];
1197 u8 reserved_at_60[0xd0];
1199 u8 system_image_guid[0x40];
1202 u8 reserved_at_200[0x140];
1203 u8 qkey_violation_counter[0x10];
1204 u8 reserved_at_350[0x430];
1207 u8 promisc_all[0x1];
1208 u8 reserved_at_783[0x2];
1209 u8 allowed_list_type[0x3];
1210 u8 reserved_at_788[0xc];
1211 u8 allowed_list_size[0xc];
1212 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1213 u8 reserved_at_7e0[0x20];
1216 struct mlx5_ifc_query_nic_vport_context_out_bits {
1218 u8 reserved_at_8[0x18];
1220 u8 reserved_at_40[0x40];
1221 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1224 struct mlx5_ifc_query_nic_vport_context_in_bits {
1226 u8 reserved_at_10[0x10];
1227 u8 reserved_at_20[0x10];
1229 u8 other_vport[0x1];
1230 u8 reserved_at_41[0xf];
1231 u8 vport_number[0x10];
1232 u8 reserved_at_60[0x5];
1233 u8 allowed_list_type[0x3];
1234 u8 reserved_at_68[0x18];
1237 /* CQE format mask. */
1238 #define MLX5E_CQE_FORMAT_MASK 0xc
1241 #define MLX5_OPC_MOD_MPW 0x01
1243 /* Compressed Rx CQE structure. */
1244 struct mlx5_mini_cqe8 {
1246 uint32_t rx_hash_result;
1249 uint16_t stride_idx;
1252 uint16_t wqe_counter;
1253 uint8_t s_wqe_opcode;
1261 * Convert a user mark to flow mark.
1264 * Mark value to convert.
1267 * Converted mark value.
1269 static inline uint32_t
1270 mlx5_flow_mark_set(uint32_t val)
1275 * Add one to the user value to differentiate un-marked flows from
1276 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
1277 * remains untouched.
1279 if (val != MLX5_FLOW_MARK_DEFAULT)
1281 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1283 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
1284 * word, byte-swapped by the kernel on little-endian systems. In this
1285 * case, left-shifting the resulting big-endian value ensures the
1286 * least significant 24 bits are retained when converting it back.
1288 ret = rte_cpu_to_be_32(val) >> 8;
1296 * Convert a mark to user mark.
1299 * Mark value to convert.
1302 * Converted mark value.
1304 static inline uint32_t
1305 mlx5_flow_mark_get(uint32_t val)
1308 * Subtract one from the retrieved value. It was added by
1309 * mlx5_flow_mark_set() to distinguish unmarked flows.
1311 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1312 return (val >> 8) - 1;
1318 #endif /* RTE_PMD_MLX5_PRM_H_ */