1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2021 6WIND S.A.
3 * Copyright 2021 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RX_H_
7 #define RTE_PMD_MLX5_RX_H_
10 #include <sys/queue.h>
13 #include <rte_mempool.h>
14 #include <rte_common.h>
15 #include <rte_spinlock.h>
17 #include <mlx5_common_mr.h>
20 #include "mlx5_autoconf.h"
23 /* Support tunnel matching. */
24 #define MLX5_FLOW_TUNNEL 10
26 struct mlx5_rxq_stats {
27 #ifdef MLX5_PMD_SOFT_COUNTERS
28 uint64_t ipackets; /**< Total of successfully received packets. */
29 uint64_t ibytes; /**< Total of successfully received bytes. */
31 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
32 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
35 /* Compressed CQE context. */
37 uint16_t ai; /* Array index. */
38 uint16_t ca; /* Current array index. */
39 uint16_t na; /* Next array index. */
40 uint16_t cq_ci; /* The next CQE. */
41 uint32_t cqe_cnt; /* Number of CQEs. */
44 /* Multi-Packet RQ buffer header. */
45 struct mlx5_mprq_buf {
46 struct rte_mempool *mp;
47 uint16_t refcnt; /* Atomically accessed refcnt. */
48 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
49 struct rte_mbuf_ext_shared_info shinfos[];
51 * Shared information per stride.
52 * More memory will be allocated for the first stride head-room and for
55 } __rte_cache_aligned;
57 /* Get pointer to the first stride. */
58 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
59 sizeof(struct mlx5_mprq_buf) + \
61 sizeof(struct rte_mbuf_ext_shared_info) + \
62 RTE_PKTMBUF_HEADROOM))
64 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
65 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
67 enum mlx5_rxq_err_state {
68 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
69 MLX5_RXQ_ERR_STATE_NEED_RESET,
70 MLX5_RXQ_ERR_STATE_NEED_READY,
74 MLX5_RXQ_CODE_EXIT = 0,
76 MLX5_RXQ_CODE_DROPPED,
79 struct mlx5_eth_rxseg {
80 struct rte_mempool *mp; /**< Memory pool to allocate segment from. */
81 uint16_t length; /**< Segment data length, configures split point. */
82 uint16_t offset; /**< Data offset from beginning of mbuf data buffer. */
83 uint32_t reserved; /**< Reserved field. */
86 /* RX queue descriptor. */
87 struct mlx5_rxq_data {
88 unsigned int csum:1; /* Enable checksum offloading. */
89 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
90 unsigned int rt_timestamp:1; /* Realtime timestamp format. */
91 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
92 unsigned int crc_present:1; /* CRC must be subtracted. */
93 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
94 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
95 unsigned int elts_n:4; /* Log 2 of Mbufs. */
96 unsigned int rss_hash:1; /* RSS hash result is enabled. */
97 unsigned int mark:1; /* Marked flow available on the queue. */
98 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
99 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
100 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
101 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
102 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
103 unsigned int lro:1; /* Enable LRO. */
104 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
105 unsigned int mcqe_format:3; /* CQE compression format. */
106 volatile uint32_t *rq_db;
107 volatile uint32_t *cq_db;
111 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
114 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
117 struct rxq_zip zip; /* Compressed context. */
118 uint16_t decompressed;
119 /* Number of ready mbufs decompressed from the CQ. */
121 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
122 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
124 volatile struct mlx5_cqe(*cqes)[];
125 struct rte_mbuf *(*elts)[];
126 struct mlx5_mprq_buf *(*mprq_bufs)[];
127 struct rte_mempool *mp;
128 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
129 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
130 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
131 uint16_t idx; /* Queue index. */
132 struct mlx5_rxq_stats stats;
133 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
134 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
135 void *cq_uar; /* Verbs CQ user access region. */
136 uint32_t cqn; /* CQ number. */
137 uint8_t cq_arm_sn; /* CQ arm seq number. */
139 rte_spinlock_t *uar_lock_cq;
140 /* CQ (UAR) access lock required for 32bit implementations */
142 uint32_t tunnel; /* Tunnel information. */
143 int timestamp_offset; /* Dynamic mbuf field for timestamp. */
144 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */
145 uint64_t flow_meta_mask;
146 int32_t flow_meta_offset;
147 uint32_t flow_meta_port_mask;
148 uint32_t rxseg_n; /* Number of split segment descriptions. */
149 struct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG];
150 /* Buffer split segment descriptions - sizes, offsets, pools. */
151 } __rte_cache_aligned;
154 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
155 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
156 MLX5_RXQ_TYPE_UNDEFINED,
159 /* RX queue control descriptor. */
160 struct mlx5_rxq_ctrl {
161 struct mlx5_rxq_data rxq; /* Data path structure. */
162 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
163 uint32_t refcnt; /* Reference counter. */
164 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
165 struct mlx5_priv *priv; /* Back pointer to private data. */
166 enum mlx5_rxq_type type; /* Rxq type. */
167 unsigned int socket; /* CPU socket ID for allocations. */
168 unsigned int irq:1; /* Whether IRQ is enabled. */
169 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
170 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
171 uint32_t wqn; /* WQ number. */
172 uint16_t dump_file_n; /* Number of dump files. */
173 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
174 uint32_t hairpin_status; /* Hairpin binding status. */
179 extern uint8_t rss_hash_default_key[];
181 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data);
182 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
183 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
184 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
185 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
186 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
187 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
188 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
189 unsigned int socket, const struct rte_eth_rxconf *conf,
190 struct rte_mempool *mp);
191 int mlx5_rx_hairpin_queue_setup
192 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
193 const struct rte_eth_hairpin_conf *hairpin_conf);
194 void mlx5_rx_queue_release(void *dpdk_rxq);
195 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
196 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
197 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
198 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
199 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
200 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
201 uint16_t desc, unsigned int socket,
202 const struct rte_eth_rxconf *conf,
203 const struct rte_eth_rxseg_split *rx_seg,
205 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
206 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
207 const struct rte_eth_hairpin_conf *hairpin_conf);
208 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
209 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
210 int mlx5_rxq_verify(struct rte_eth_dev *dev);
211 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
212 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
213 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev,
214 const uint16_t *queues,
216 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
217 struct mlx5_ind_table_obj *ind_tbl,
219 int mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,
220 struct mlx5_ind_table_obj *ind_tbl);
221 int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,
222 struct mlx5_ind_table_obj *ind_tbl,
223 uint16_t *queues, const uint32_t queues_n,
225 struct mlx5_cache_entry *mlx5_hrxq_create_cb(struct mlx5_cache_list *list,
226 struct mlx5_cache_entry *entry __rte_unused, void *cb_ctx);
227 int mlx5_hrxq_match_cb(struct mlx5_cache_list *list,
228 struct mlx5_cache_entry *entry,
230 void mlx5_hrxq_remove_cb(struct mlx5_cache_list *list,
231 struct mlx5_cache_entry *entry);
232 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
233 struct mlx5_flow_rss_desc *rss_desc);
234 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
235 uint32_t mlx5_hrxq_verify(struct rte_eth_dev *dev);
236 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
237 const struct rte_eth_hairpin_conf *mlx5_rxq_get_hairpin_conf
238 (struct rte_eth_dev *dev, uint16_t idx);
239 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev);
240 void mlx5_drop_action_destroy(struct rte_eth_dev *dev);
241 uint64_t mlx5_get_rx_port_offloads(void);
242 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
243 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
244 int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx,
245 const uint8_t *rss_key, uint32_t rss_key_len,
246 uint64_t hash_fields,
247 const uint16_t *queues, uint32_t queues_n);
251 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
252 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
253 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
254 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
255 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
256 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
258 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
260 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
261 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
262 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
263 struct rte_eth_rxq_info *qinfo);
264 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
265 struct rte_eth_burst_mode *mode);
266 int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
268 /* Vectorized version of mlx5_rx.c */
269 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
270 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
271 uint16_t mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts,
273 uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts,
278 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
281 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
282 * as mempool is pre-configured and static.
285 * Pointer to Rx queue structure.
290 * Searched LKey on success, UINT32_MAX on no match.
292 static __rte_always_inline uint32_t
293 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
295 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
298 /* Linear search on MR cache array. */
299 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
300 MLX5_MR_CACHE_N, addr);
301 if (likely(lkey != UINT32_MAX))
303 /* Take slower bottom-half (Binary Search) on miss. */
304 return mlx5_rx_addr2mr_bh(rxq, addr);
307 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
310 * Convert timestamp from HW format to linear counter
311 * from Packet Pacing Clock Queue CQE timestamp format.
314 * Pointer to the device shared context. Might be needed
315 * to convert according current device configuration.
317 * Timestamp from CQE to convert.
321 static __rte_always_inline uint64_t
322 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)
325 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;
329 * Set timestamp in mbuf dynamic field.
332 * Structure to write into.
334 * Dynamic field offset in mbuf structure.
338 static __rte_always_inline void
339 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset,
340 rte_mbuf_timestamp_t timestamp)
342 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp;
346 * Replace MPRQ buffer.
349 * Pointer to Rx queue structure.
351 * RQ index to replace.
353 static __rte_always_inline void
354 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
356 const uint32_t strd_n = 1 << rxq->strd_num_n;
357 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
358 volatile struct mlx5_wqe_data_seg *wqe =
359 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
360 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx];
363 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) {
364 MLX5_ASSERT(rep != NULL);
365 /* Replace MPRQ buf. */
366 (*rxq->mprq_bufs)[rq_idx] = rep;
368 addr = mlx5_mprq_buf_addr(rep, strd_n);
369 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
370 /* If there's only one MR, no need to replace LKey in WQE. */
371 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
372 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
373 /* Stash a mbuf for next replacement. */
374 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
375 rxq->mprq_repl = rep;
377 rxq->mprq_repl = NULL;
378 /* Release the old buffer. */
379 mlx5_mprq_buf_free(buf);
380 } else if (unlikely(rxq->mprq_repl == NULL)) {
381 struct mlx5_mprq_buf *rep;
384 * Currently, the MPRQ mempool is out of buffer
385 * and doing memcpy regardless of the size of Rx
386 * packet. Retry allocation to get back to
389 if (!rte_mempool_get(rxq->mprq_mp, (void **)&rep))
390 rxq->mprq_repl = rep;
395 * Attach or copy MPRQ buffer content to a packet.
398 * Pointer to Rx queue structure.
400 * Pointer to a packet to fill.
404 * Pointer to a MPRQ buffer to take the data from.
406 * Stride index to start from.
408 * Number of strides to consume.
410 static __rte_always_inline enum mlx5_rqx_code
411 mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len,
412 struct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt)
414 const uint32_t strd_n = 1 << rxq->strd_num_n;
415 const uint16_t strd_sz = 1 << rxq->strd_sz_n;
416 const uint16_t strd_shift =
417 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
418 const int32_t hdrm_overlap =
419 len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz;
420 const uint32_t offset = strd_idx * strd_sz + strd_shift;
421 void *addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
424 * Memcpy packets to the target mbuf if:
425 * - The size of packet is smaller than mprq_max_memcpy_len.
426 * - Out of buffer in the Mempool for Multi-Packet RQ.
427 * - The packet's stride overlaps a headroom and scatter is off.
429 if (len <= rxq->mprq_max_memcpy_len ||
430 rxq->mprq_repl == NULL ||
431 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) {
433 (uint32_t)(pkt->buf_len - RTE_PKTMBUF_HEADROOM))) {
434 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
437 } else if (rxq->strd_scatter_en) {
438 struct rte_mbuf *prev = pkt;
439 uint32_t seg_len = RTE_MIN(len, (uint32_t)
440 (pkt->buf_len - RTE_PKTMBUF_HEADROOM));
441 uint32_t rem_len = len - seg_len;
443 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
445 DATA_LEN(pkt) = seg_len;
447 struct rte_mbuf *next =
448 rte_pktmbuf_alloc(rxq->mp);
450 if (unlikely(next == NULL))
451 return MLX5_RXQ_CODE_NOMBUF;
453 SET_DATA_OFF(next, 0);
454 addr = RTE_PTR_ADD(addr, seg_len);
455 seg_len = RTE_MIN(rem_len, (uint32_t)
456 (next->buf_len - RTE_PKTMBUF_HEADROOM));
458 (rte_pktmbuf_mtod(next, void *),
460 DATA_LEN(next) = seg_len;
466 return MLX5_RXQ_CODE_DROPPED;
470 struct rte_mbuf_ext_shared_info *shinfo;
471 uint16_t buf_len = strd_cnt * strd_sz;
474 /* Increment the refcnt of the whole chunk. */
475 __atomic_add_fetch(&buf->refcnt, 1, __ATOMIC_RELAXED);
476 MLX5_ASSERT(__atomic_load_n(&buf->refcnt,
477 __ATOMIC_RELAXED) <= strd_n + 1);
478 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
480 * MLX5 device doesn't use iova but it is necessary in a
481 * case where the Rx packet is transmitted via a
484 buf_iova = rte_mempool_virt2iova(buf) +
485 RTE_PTR_DIFF(buf_addr, buf);
486 shinfo = &buf->shinfos[strd_idx];
487 rte_mbuf_ext_refcnt_set(shinfo, 1);
489 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
490 * attaching the stride to mbuf and more offload flags
491 * will be added below by calling rxq_cq_to_mbuf().
492 * Other fields will be overwritten.
494 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
496 /* Set mbuf head-room. */
497 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM);
498 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);
499 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >=
500 len - (hdrm_overlap > 0 ? hdrm_overlap : 0));
503 * Copy the last fragment of a packet (up to headroom
504 * size bytes) in case there is a stride overlap with
505 * a next packet's headroom. Allocate a separate mbuf
506 * to store this fragment and link it. Scatter is on.
508 if (hdrm_overlap > 0) {
509 MLX5_ASSERT(rxq->strd_scatter_en);
510 struct rte_mbuf *seg =
511 rte_pktmbuf_alloc(rxq->mp);
513 if (unlikely(seg == NULL))
514 return MLX5_RXQ_CODE_NOMBUF;
515 SET_DATA_OFF(seg, 0);
516 rte_memcpy(rte_pktmbuf_mtod(seg, void *),
517 RTE_PTR_ADD(addr, len - hdrm_overlap),
519 DATA_LEN(seg) = hdrm_overlap;
520 DATA_LEN(pkt) = len - hdrm_overlap;
525 return MLX5_RXQ_CODE_EXIT;
529 * Check whether Multi-Packet RQ can be enabled for the device.
532 * Pointer to Ethernet device.
535 * 1 if supported, negative errno value if not.
537 static __rte_always_inline int
538 mlx5_check_mprq_support(struct rte_eth_dev *dev)
540 struct mlx5_priv *priv = dev->data->dev_private;
542 if (priv->config.mprq.enabled &&
543 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
549 * Check whether Multi-Packet RQ is enabled for the Rx queue.
552 * Pointer to receive queue structure.
555 * 0 if disabled, otherwise enabled.
557 static __rte_always_inline int
558 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
560 return rxq->strd_num_n > 0;
564 * Check whether Multi-Packet RQ is enabled for the device.
567 * Pointer to Ethernet device.
570 * 0 if disabled, otherwise enabled.
572 static __rte_always_inline int
573 mlx5_mprq_enabled(struct rte_eth_dev *dev)
575 struct mlx5_priv *priv = dev->data->dev_private;
580 if (mlx5_check_mprq_support(dev) < 0)
582 /* All the configured queues should be enabled. */
583 for (i = 0; i < priv->rxqs_n; ++i) {
584 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
585 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
586 (rxq, struct mlx5_rxq_ctrl, rxq);
588 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
591 if (mlx5_rxq_mprq_enabled(rxq))
594 /* Multi-Packet RQ can't be partially configured. */
595 MLX5_ASSERT(n == 0 || n == n_ibv);
599 #endif /* RTE_PMD_MLX5_RX_H_ */