1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 #include <sys/queue.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
29 #include <rte_interrupts.h>
30 #include <rte_debug.h>
34 #include "mlx5_rxtx.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
38 #include "mlx5_glue.h"
40 /* Default RSS hash key also used for ConnectX-3. */
41 uint8_t rss_hash_default_key[] = {
42 0x2c, 0xc6, 0x81, 0xd1,
43 0x5b, 0xdb, 0xf4, 0xf7,
44 0xfc, 0xa2, 0x83, 0x19,
45 0xdb, 0x1a, 0x3e, 0x94,
46 0x6b, 0x9e, 0x38, 0xd9,
47 0x2c, 0x9c, 0x03, 0xd1,
48 0xad, 0x99, 0x44, 0xa7,
49 0xd9, 0x56, 0x3d, 0x59,
50 0x06, 0x3c, 0x25, 0xf3,
51 0xfc, 0x1f, 0xdc, 0x2a,
54 /* Length of the default RSS hash key. */
55 const size_t rss_hash_default_key_len = sizeof(rss_hash_default_key);
58 * Check whether Multi-Packet RQ can be enabled for the device.
61 * Pointer to Ethernet device.
64 * 1 if supported, negative errno value if not.
67 mlx5_check_mprq_support(struct rte_eth_dev *dev)
69 struct priv *priv = dev->data->dev_private;
71 if (priv->config.mprq.enabled &&
72 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
78 * Check whether Multi-Packet RQ is enabled for the Rx queue.
81 * Pointer to receive queue structure.
84 * 0 if disabled, otherwise enabled.
87 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
89 return rxq->strd_num_n > 0;
93 * Check whether Multi-Packet RQ is enabled for the device.
96 * Pointer to Ethernet device.
99 * 0 if disabled, otherwise enabled.
102 mlx5_mprq_enabled(struct rte_eth_dev *dev)
104 struct priv *priv = dev->data->dev_private;
108 if (mlx5_check_mprq_support(dev) < 0)
110 /* All the configured queues should be enabled. */
111 for (i = 0; i < priv->rxqs_n; ++i) {
112 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
116 if (mlx5_rxq_mprq_enabled(rxq))
119 /* Multi-Packet RQ can't be partially configured. */
120 assert(n == 0 || n == priv->rxqs_n);
121 return n == priv->rxqs_n;
125 * Allocate RX queue elements for Multi-Packet RQ.
128 * Pointer to RX queue structure.
131 * 0 on success, a negative errno value otherwise and rte_errno is set.
134 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
136 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
137 unsigned int wqe_n = 1 << rxq->elts_n;
141 /* Iterate on segments. */
142 for (i = 0; i <= wqe_n; ++i) {
143 struct mlx5_mprq_buf *buf;
145 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
146 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
151 (*rxq->mprq_bufs)[i] = buf;
153 rxq->mprq_repl = buf;
156 "port %u Rx queue %u allocated and configured %u segments",
157 rxq->port_id, rxq_ctrl->idx, wqe_n);
160 err = rte_errno; /* Save rte_errno before cleanup. */
162 for (i = 0; (i != wqe_n); ++i) {
163 if ((*rxq->mprq_bufs)[i] != NULL)
164 rte_mempool_put(rxq->mprq_mp,
165 (*rxq->mprq_bufs)[i]);
166 (*rxq->mprq_bufs)[i] = NULL;
168 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
169 rxq->port_id, rxq_ctrl->idx);
170 rte_errno = err; /* Restore rte_errno. */
175 * Allocate RX queue elements for Single-Packet RQ.
178 * Pointer to RX queue structure.
181 * 0 on success, errno value on failure.
184 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
186 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
187 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
191 /* Iterate on segments. */
192 for (i = 0; (i != elts_n); ++i) {
193 struct rte_mbuf *buf;
195 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
197 DRV_LOG(ERR, "port %u empty mbuf pool",
198 PORT_ID(rxq_ctrl->priv));
202 /* Headroom is reserved by rte_pktmbuf_alloc(). */
203 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
204 /* Buffer is supposed to be empty. */
205 assert(rte_pktmbuf_data_len(buf) == 0);
206 assert(rte_pktmbuf_pkt_len(buf) == 0);
208 /* Only the first segment keeps headroom. */
210 SET_DATA_OFF(buf, 0);
211 PORT(buf) = rxq_ctrl->rxq.port_id;
212 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
213 PKT_LEN(buf) = DATA_LEN(buf);
215 (*rxq_ctrl->rxq.elts)[i] = buf;
217 /* If Rx vector is activated. */
218 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
219 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
220 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
223 /* Initialize default rearm_data for vPMD. */
224 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
225 rte_mbuf_refcnt_set(mbuf_init, 1);
226 mbuf_init->nb_segs = 1;
227 mbuf_init->port = rxq->port_id;
229 * prevent compiler reordering:
230 * rearm_data covers previous fields.
232 rte_compiler_barrier();
233 rxq->mbuf_initializer =
234 *(uint64_t *)&mbuf_init->rearm_data;
235 /* Padding with a fake mbuf for vectorized Rx. */
236 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
237 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
240 "port %u Rx queue %u allocated and configured %u segments"
242 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx, elts_n,
243 elts_n / (1 << rxq_ctrl->rxq.sges_n));
246 err = rte_errno; /* Save rte_errno before cleanup. */
248 for (i = 0; (i != elts_n); ++i) {
249 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
250 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
251 (*rxq_ctrl->rxq.elts)[i] = NULL;
253 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
254 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
255 rte_errno = err; /* Restore rte_errno. */
260 * Allocate RX queue elements.
263 * Pointer to RX queue structure.
266 * 0 on success, errno value on failure.
269 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
271 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
272 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
276 * Free RX queue elements for Multi-Packet RQ.
279 * Pointer to RX queue structure.
282 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
284 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
287 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
288 rxq->port_id, rxq_ctrl->idx);
289 if (rxq->mprq_bufs == NULL)
291 assert(mlx5_rxq_check_vec_support(rxq) < 0);
292 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
293 if ((*rxq->mprq_bufs)[i] != NULL)
294 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
295 (*rxq->mprq_bufs)[i] = NULL;
297 if (rxq->mprq_repl != NULL) {
298 mlx5_mprq_buf_free(rxq->mprq_repl);
299 rxq->mprq_repl = NULL;
304 * Free RX queue elements for Single-Packet RQ.
307 * Pointer to RX queue structure.
310 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
312 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
313 const uint16_t q_n = (1 << rxq->elts_n);
314 const uint16_t q_mask = q_n - 1;
315 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
318 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
319 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
320 if (rxq->elts == NULL)
323 * Some mbuf in the Ring belongs to the application. They cannot be
326 if (mlx5_rxq_check_vec_support(rxq) > 0) {
327 for (i = 0; i < used; ++i)
328 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
329 rxq->rq_pi = rxq->rq_ci;
331 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
332 if ((*rxq->elts)[i] != NULL)
333 rte_pktmbuf_free_seg((*rxq->elts)[i]);
334 (*rxq->elts)[i] = NULL;
339 * Free RX queue elements.
342 * Pointer to RX queue structure.
345 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
347 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
348 rxq_free_elts_mprq(rxq_ctrl);
350 rxq_free_elts_sprq(rxq_ctrl);
354 * Clean up a RX queue.
356 * Destroy objects, free allocated memory and reset the structure for reuse.
359 * Pointer to RX queue structure.
362 mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl)
364 DRV_LOG(DEBUG, "port %u cleaning up Rx queue %u",
365 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
367 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
368 memset(rxq_ctrl, 0, sizeof(*rxq_ctrl));
372 * Returns the per-queue supported offloads.
375 * Pointer to Ethernet device.
378 * Supported Rx offloads.
381 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
383 struct priv *priv = dev->data->dev_private;
384 struct mlx5_dev_config *config = &priv->config;
385 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
386 DEV_RX_OFFLOAD_TIMESTAMP |
387 DEV_RX_OFFLOAD_JUMBO_FRAME);
389 if (config->hw_fcs_strip)
390 offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
392 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
393 DEV_RX_OFFLOAD_UDP_CKSUM |
394 DEV_RX_OFFLOAD_TCP_CKSUM);
395 if (config->hw_vlan_strip)
396 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
402 * Returns the per-port supported offloads.
405 * Supported Rx offloads.
408 mlx5_get_rx_port_offloads(void)
410 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
418 * Pointer to Ethernet device structure.
422 * Number of descriptors to configure in queue.
424 * NUMA socket on which memory must be allocated.
426 * Thresholds parameters.
428 * Memory pool for buffer allocations.
431 * 0 on success, a negative errno value otherwise and rte_errno is set.
434 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
435 unsigned int socket, const struct rte_eth_rxconf *conf,
436 struct rte_mempool *mp)
438 struct priv *priv = dev->data->dev_private;
439 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
440 struct mlx5_rxq_ctrl *rxq_ctrl =
441 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
443 if (!rte_is_power_of_2(desc)) {
444 desc = 1 << log2above(desc);
446 "port %u increased number of descriptors in Rx queue %u"
447 " to the next power of two (%d)",
448 dev->data->port_id, idx, desc);
450 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
451 dev->data->port_id, idx, desc);
452 if (idx >= priv->rxqs_n) {
453 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
454 dev->data->port_id, idx, priv->rxqs_n);
455 rte_errno = EOVERFLOW;
458 if (!mlx5_rxq_releasable(dev, idx)) {
459 DRV_LOG(ERR, "port %u unable to release queue index %u",
460 dev->data->port_id, idx);
464 mlx5_rxq_release(dev, idx);
465 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
467 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
468 dev->data->port_id, idx);
472 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
473 dev->data->port_id, idx);
474 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
479 * DPDK callback to release a RX queue.
482 * Generic RX queue pointer.
485 mlx5_rx_queue_release(void *dpdk_rxq)
487 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
488 struct mlx5_rxq_ctrl *rxq_ctrl;
493 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
494 priv = rxq_ctrl->priv;
495 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.stats.idx))
496 rte_panic("port %u Rx queue %u is still used by a flow and"
497 " cannot be removed\n",
498 PORT_ID(priv), rxq_ctrl->idx);
499 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.stats.idx);
503 * Allocate queue vector and fill epoll fd list for Rx interrupts.
506 * Pointer to Ethernet device.
509 * 0 on success, a negative errno value otherwise and rte_errno is set.
512 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
514 struct priv *priv = dev->data->dev_private;
516 unsigned int rxqs_n = priv->rxqs_n;
517 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
518 unsigned int count = 0;
519 struct rte_intr_handle *intr_handle = dev->intr_handle;
521 if (!dev->data->dev_conf.intr_conf.rxq)
523 mlx5_rx_intr_vec_disable(dev);
524 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
525 if (intr_handle->intr_vec == NULL) {
527 "port %u failed to allocate memory for interrupt"
528 " vector, Rx interrupts will not be supported",
533 intr_handle->type = RTE_INTR_HANDLE_EXT;
534 for (i = 0; i != n; ++i) {
535 /* This rxq ibv must not be released in this function. */
536 struct mlx5_rxq_ibv *rxq_ibv = mlx5_rxq_ibv_get(dev, i);
541 /* Skip queues that cannot request interrupts. */
542 if (!rxq_ibv || !rxq_ibv->channel) {
543 /* Use invalid intr_vec[] index to disable entry. */
544 intr_handle->intr_vec[i] =
545 RTE_INTR_VEC_RXTX_OFFSET +
546 RTE_MAX_RXTX_INTR_VEC_ID;
549 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
551 "port %u too many Rx queues for interrupt"
552 " vector size (%d), Rx interrupts cannot be"
554 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
555 mlx5_rx_intr_vec_disable(dev);
559 fd = rxq_ibv->channel->fd;
560 flags = fcntl(fd, F_GETFL);
561 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
565 "port %u failed to make Rx interrupt file"
566 " descriptor %d non-blocking for queue index"
568 dev->data->port_id, fd, i);
569 mlx5_rx_intr_vec_disable(dev);
572 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
573 intr_handle->efds[count] = fd;
577 mlx5_rx_intr_vec_disable(dev);
579 intr_handle->nb_efd = count;
584 * Clean up Rx interrupts handler.
587 * Pointer to Ethernet device.
590 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
592 struct priv *priv = dev->data->dev_private;
593 struct rte_intr_handle *intr_handle = dev->intr_handle;
595 unsigned int rxqs_n = priv->rxqs_n;
596 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
598 if (!dev->data->dev_conf.intr_conf.rxq)
600 if (!intr_handle->intr_vec)
602 for (i = 0; i != n; ++i) {
603 struct mlx5_rxq_ctrl *rxq_ctrl;
604 struct mlx5_rxq_data *rxq_data;
606 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
607 RTE_MAX_RXTX_INTR_VEC_ID)
610 * Need to access directly the queue to release the reference
611 * kept in priv_rx_intr_vec_enable().
613 rxq_data = (*priv->rxqs)[i];
614 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
615 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
618 rte_intr_free_epoll_fd(intr_handle);
619 if (intr_handle->intr_vec)
620 free(intr_handle->intr_vec);
621 intr_handle->nb_efd = 0;
622 intr_handle->intr_vec = NULL;
626 * MLX5 CQ notification .
629 * Pointer to receive queue structure.
631 * Sequence number per receive queue .
634 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
637 uint32_t doorbell_hi;
639 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
641 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
642 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
643 doorbell = (uint64_t)doorbell_hi << 32;
644 doorbell |= rxq->cqn;
645 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
646 rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);
650 * DPDK callback for Rx queue interrupt enable.
653 * Pointer to Ethernet device structure.
658 * 0 on success, a negative errno value otherwise and rte_errno is set.
661 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
663 struct priv *priv = dev->data->dev_private;
664 struct mlx5_rxq_data *rxq_data;
665 struct mlx5_rxq_ctrl *rxq_ctrl;
667 rxq_data = (*priv->rxqs)[rx_queue_id];
672 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
674 struct mlx5_rxq_ibv *rxq_ibv;
676 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
681 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
682 mlx5_rxq_ibv_release(rxq_ibv);
688 * DPDK callback for Rx queue interrupt disable.
691 * Pointer to Ethernet device structure.
696 * 0 on success, a negative errno value otherwise and rte_errno is set.
699 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
701 struct priv *priv = dev->data->dev_private;
702 struct mlx5_rxq_data *rxq_data;
703 struct mlx5_rxq_ctrl *rxq_ctrl;
704 struct mlx5_rxq_ibv *rxq_ibv = NULL;
705 struct ibv_cq *ev_cq;
709 rxq_data = (*priv->rxqs)[rx_queue_id];
714 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
717 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
722 ret = mlx5_glue->get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
723 if (ret || ev_cq != rxq_ibv->cq) {
727 rxq_data->cq_arm_sn++;
728 mlx5_glue->ack_cq_events(rxq_ibv->cq, 1);
731 ret = rte_errno; /* Save rte_errno before cleanup. */
733 mlx5_rxq_ibv_release(rxq_ibv);
734 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
735 dev->data->port_id, rx_queue_id);
736 rte_errno = ret; /* Restore rte_errno. */
741 * Create the Rx queue Verbs object.
744 * Pointer to Ethernet device.
746 * Queue index in DPDK Rx queue array
749 * The Verbs object initialised, NULL otherwise and rte_errno is set.
751 struct mlx5_rxq_ibv *
752 mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
754 struct priv *priv = dev->data->dev_private;
755 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
756 struct mlx5_rxq_ctrl *rxq_ctrl =
757 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
758 struct ibv_wq_attr mod;
761 struct ibv_cq_init_attr_ex ibv;
762 struct mlx5dv_cq_init_attr mlx5;
765 struct ibv_wq_init_attr ibv;
766 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
767 struct mlx5dv_wq_init_attr mlx5;
770 struct ibv_cq_ex cq_attr;
773 unsigned int wqe_n = 1 << rxq_data->elts_n;
774 struct mlx5_rxq_ibv *tmpl;
775 struct mlx5dv_cq cq_info;
776 struct mlx5dv_rwq rwq;
779 struct mlx5dv_obj obj;
780 struct mlx5_dev_config *config = &priv->config;
781 const int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);
784 assert(!rxq_ctrl->ibv);
785 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
786 priv->verbs_alloc_ctx.obj = rxq_ctrl;
787 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
791 "port %u Rx queue %u cannot allocate verbs resources",
792 dev->data->port_id, rxq_ctrl->idx);
796 tmpl->rxq_ctrl = rxq_ctrl;
798 tmpl->channel = mlx5_glue->create_comp_channel(priv->ctx);
799 if (!tmpl->channel) {
800 DRV_LOG(ERR, "port %u: comp channel creation failure",
807 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
810 attr.cq.ibv = (struct ibv_cq_init_attr_ex){
812 .channel = tmpl->channel,
815 attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
818 if (config->cqe_comp && !rxq_data->hw_timestamp) {
819 attr.cq.mlx5.comp_mask |=
820 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
821 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
823 * For vectorized Rx, it must not be doubled in order to
824 * make cq_ci and rq_ci aligned.
826 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
827 attr.cq.ibv.cqe *= 2;
828 } else if (config->cqe_comp && rxq_data->hw_timestamp) {
830 "port %u Rx CQE compression is disabled for HW"
834 tmpl->cq = mlx5_glue->cq_ex_to_cq
835 (mlx5_glue->dv_create_cq(priv->ctx, &attr.cq.ibv,
837 if (tmpl->cq == NULL) {
838 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
839 dev->data->port_id, idx);
843 DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d",
844 dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr);
845 DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d",
846 dev->data->port_id, priv->device_attr.orig_attr.max_sge);
847 attr.wq.ibv = (struct ibv_wq_init_attr){
848 .wq_context = NULL, /* Could be useful in the future. */
849 .wq_type = IBV_WQT_RQ,
850 /* Max number of outstanding WRs. */
851 .max_wr = wqe_n >> rxq_data->sges_n,
852 /* Max number of scatter/gather elements in a WR. */
853 .max_sge = 1 << rxq_data->sges_n,
857 IBV_WQ_FLAGS_CVLAN_STRIPPING |
859 .create_flags = (rxq_data->vlan_strip ?
860 IBV_WQ_FLAGS_CVLAN_STRIPPING :
863 /* By default, FCS (CRC) is stripped by hardware. */
864 if (rxq_data->crc_present) {
865 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
866 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
868 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
869 if (config->hw_padding) {
870 attr.wq.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
871 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
874 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
875 attr.wq.mlx5 = (struct mlx5dv_wq_init_attr){
879 struct mlx5dv_striding_rq_init_attr *mprq_attr =
880 &attr.wq.mlx5.striding_rq_attrs;
882 attr.wq.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
883 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
884 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
885 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
886 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
889 tmpl->wq = mlx5_glue->dv_create_wq(priv->ctx, &attr.wq.ibv,
892 tmpl->wq = mlx5_glue->create_wq(priv->ctx, &attr.wq.ibv);
894 if (tmpl->wq == NULL) {
895 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
896 dev->data->port_id, idx);
901 * Make sure number of WRs*SGEs match expectations since a queue
902 * cannot allocate more than "desc" buffers.
904 if (attr.wq.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
905 attr.wq.ibv.max_sge != (1u << rxq_data->sges_n)) {
907 "port %u Rx queue %u requested %u*%u but got %u*%u"
909 dev->data->port_id, idx,
910 wqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),
911 attr.wq.ibv.max_wr, attr.wq.ibv.max_sge);
915 /* Change queue state to ready. */
916 mod = (struct ibv_wq_attr){
917 .attr_mask = IBV_WQ_ATTR_STATE,
918 .wq_state = IBV_WQS_RDY,
920 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
923 "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
924 dev->data->port_id, idx);
928 obj.cq.in = tmpl->cq;
929 obj.cq.out = &cq_info;
930 obj.rwq.in = tmpl->wq;
932 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
937 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
939 "port %u wrong MLX5_CQE_SIZE environment variable"
940 " value: it should be set to %u",
941 dev->data->port_id, RTE_CACHE_LINE_SIZE);
945 /* Fill the rings. */
946 rxq_data->wqes = rwq.buf;
947 for (i = 0; (i != wqe_n); ++i) {
948 volatile struct mlx5_wqe_data_seg *scat;
953 struct mlx5_mprq_buf *buf = (*rxq_data->mprq_bufs)[i];
955 scat = &((volatile struct mlx5_wqe_mprq *)
956 rxq_data->wqes)[i].dseg;
957 addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
958 byte_count = (1 << rxq_data->strd_sz_n) *
959 (1 << rxq_data->strd_num_n);
961 struct rte_mbuf *buf = (*rxq_data->elts)[i];
963 scat = &((volatile struct mlx5_wqe_data_seg *)
965 addr = rte_pktmbuf_mtod(buf, uintptr_t);
966 byte_count = DATA_LEN(buf);
968 /* scat->addr must be able to store a pointer. */
969 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
970 *scat = (struct mlx5_wqe_data_seg){
971 .addr = rte_cpu_to_be_64(addr),
972 .byte_count = rte_cpu_to_be_32(byte_count),
973 .lkey = mlx5_rx_addr2mr(rxq_data, addr),
976 rxq_data->rq_db = rwq.dbrec;
977 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
979 rxq_data->strd_ci = 0;
981 rxq_data->zip = (struct rxq_zip){
984 rxq_data->cq_db = cq_info.dbrec;
985 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
986 rxq_data->cq_uar = cq_info.cq_uar;
987 rxq_data->cqn = cq_info.cqn;
988 rxq_data->cq_arm_sn = 0;
989 /* Update doorbell counter. */
990 rxq_data->rq_ci = wqe_n >> rxq_data->sges_n;
992 *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
993 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
995 rte_atomic32_inc(&tmpl->refcnt);
996 LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
997 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1000 ret = rte_errno; /* Save rte_errno before cleanup. */
1002 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1004 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1006 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->channel));
1007 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1008 rte_errno = ret; /* Restore rte_errno. */
1013 * Get an Rx queue Verbs object.
1016 * Pointer to Ethernet device.
1018 * Queue index in DPDK Rx queue array
1021 * The Verbs object if it exists.
1023 struct mlx5_rxq_ibv *
1024 mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
1026 struct priv *priv = dev->data->dev_private;
1027 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1028 struct mlx5_rxq_ctrl *rxq_ctrl;
1030 if (idx >= priv->rxqs_n)
1034 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1035 if (rxq_ctrl->ibv) {
1036 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
1038 return rxq_ctrl->ibv;
1042 * Release an Rx verbs queue object.
1045 * Verbs Rx queue object.
1048 * 1 while a reference on it exists, 0 when freed.
1051 mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv)
1054 assert(rxq_ibv->wq);
1055 assert(rxq_ibv->cq);
1056 if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
1057 rxq_free_elts(rxq_ibv->rxq_ctrl);
1058 claim_zero(mlx5_glue->destroy_wq(rxq_ibv->wq));
1059 claim_zero(mlx5_glue->destroy_cq(rxq_ibv->cq));
1060 if (rxq_ibv->channel)
1061 claim_zero(mlx5_glue->destroy_comp_channel
1062 (rxq_ibv->channel));
1063 LIST_REMOVE(rxq_ibv, next);
1071 * Verify the Verbs Rx queue list is empty
1074 * Pointer to Ethernet device.
1077 * The number of object not released.
1080 mlx5_rxq_ibv_verify(struct rte_eth_dev *dev)
1082 struct priv *priv = dev->data->dev_private;
1084 struct mlx5_rxq_ibv *rxq_ibv;
1086 LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
1087 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u still referenced",
1088 dev->data->port_id, rxq_ibv->rxq_ctrl->idx);
1095 * Return true if a single reference exists on the object.
1098 * Verbs Rx queue object.
1101 mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv)
1104 return (rte_atomic32_read(&rxq_ibv->refcnt) == 1);
1108 * Callback function to initialize mbufs for Multi-Packet RQ.
1111 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1112 void *_m, unsigned int i __rte_unused)
1114 struct mlx5_mprq_buf *buf = _m;
1116 memset(_m, 0, sizeof(*buf));
1118 rte_atomic16_set(&buf->refcnt, 1);
1122 * Free mempool of Multi-Packet RQ.
1125 * Pointer to Ethernet device.
1128 * 0 on success, negative errno value on failure.
1131 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1133 struct priv *priv = dev->data->dev_private;
1134 struct rte_mempool *mp = priv->mprq_mp;
1139 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1140 dev->data->port_id, mp->name);
1142 * If a buffer in the pool has been externally attached to a mbuf and it
1143 * is still in use by application, destroying the Rx qeueue can spoil
1144 * the packet. It is unlikely to happen but if application dynamically
1145 * creates and destroys with holding Rx packets, this can happen.
1147 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1148 * RQ isn't provided by application but managed by PMD.
1150 if (!rte_mempool_full(mp)) {
1152 "port %u mempool for Multi-Packet RQ is still in use",
1153 dev->data->port_id);
1157 rte_mempool_free(mp);
1158 /* Unset mempool for each Rx queue. */
1159 for (i = 0; i != priv->rxqs_n; ++i) {
1160 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1164 rxq->mprq_mp = NULL;
1170 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1171 * mempool. If already allocated, reuse it if there're enough elements.
1172 * Otherwise, resize it.
1175 * Pointer to Ethernet device.
1178 * 0 on success, negative errno value on failure.
1181 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1183 struct priv *priv = dev->data->dev_private;
1184 struct rte_mempool *mp = priv->mprq_mp;
1185 char name[RTE_MEMPOOL_NAMESIZE];
1186 unsigned int desc = 0;
1187 unsigned int buf_len;
1188 unsigned int obj_num;
1189 unsigned int obj_size;
1190 unsigned int strd_num_n = 0;
1191 unsigned int strd_sz_n = 0;
1194 if (!mlx5_mprq_enabled(dev))
1196 /* Count the total number of descriptors configured. */
1197 for (i = 0; i != priv->rxqs_n; ++i) {
1198 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1202 desc += 1 << rxq->elts_n;
1203 /* Get the max number of strides. */
1204 if (strd_num_n < rxq->strd_num_n)
1205 strd_num_n = rxq->strd_num_n;
1206 /* Get the max size of a stride. */
1207 if (strd_sz_n < rxq->strd_sz_n)
1208 strd_sz_n = rxq->strd_sz_n;
1210 assert(strd_num_n && strd_sz_n);
1211 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1212 obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1214 * Received packets can be either memcpy'd or externally referenced. In
1215 * case that the packet is attached to an mbuf as an external buffer, as
1216 * it isn't possible to predict how the buffers will be queued by
1217 * application, there's no option to exactly pre-allocate needed buffers
1218 * in advance but to speculatively prepares enough buffers.
1220 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1221 * received packets to buffers provided by application (rxq->mp) until
1222 * this Mempool gets available again.
1225 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1226 /* Check a mempool is already allocated and if it can be resued. */
1227 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1228 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1229 dev->data->port_id, mp->name);
1232 } else if (mp != NULL) {
1233 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1234 dev->data->port_id, mp->name);
1236 * If failed to free, which means it may be still in use, no way
1237 * but to keep using the existing one. On buffer underrun,
1238 * packets will be memcpy'd instead of external buffer
1241 if (mlx5_mprq_free_mp(dev)) {
1242 if (mp->elt_size >= obj_size)
1248 snprintf(name, sizeof(name), "%s-mprq", dev->device->name);
1249 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1250 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1251 dev->device->numa_node, 0);
1254 "port %u failed to allocate a mempool for"
1255 " Multi-Packet RQ, count=%u, size=%u",
1256 dev->data->port_id, obj_num, obj_size);
1262 /* Set mempool for each Rx queue. */
1263 for (i = 0; i != priv->rxqs_n; ++i) {
1264 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1270 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1271 dev->data->port_id);
1276 * Create a DPDK Rx queue.
1279 * Pointer to Ethernet device.
1283 * Number of descriptors to configure in queue.
1285 * NUMA socket on which memory must be allocated.
1288 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1290 struct mlx5_rxq_ctrl *
1291 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1292 unsigned int socket, const struct rte_eth_rxconf *conf,
1293 struct rte_mempool *mp)
1295 struct priv *priv = dev->data->dev_private;
1296 struct mlx5_rxq_ctrl *tmpl;
1297 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1298 unsigned int mprq_stride_size;
1299 struct mlx5_dev_config *config = &priv->config;
1301 * Always allocate extra slots, even if eventually
1302 * the vector Rx will not be used.
1305 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1306 uint64_t offloads = conf->offloads |
1307 dev->data->dev_conf.rxmode.offloads;
1308 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1310 tmpl = rte_calloc_socket("RXQ", 1,
1312 desc_n * sizeof(struct rte_mbuf *),
1318 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1319 MLX5_MR_BTREE_CACHE_N, socket)) {
1320 /* rte_errno is already set. */
1323 tmpl->socket = socket;
1324 if (dev->data->dev_conf.intr_conf.rxq)
1327 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1328 * following conditions are met:
1329 * - MPRQ is enabled.
1330 * - The number of descs is more than the number of strides.
1331 * - max_rx_pkt_len plus overhead is less than the max size of a
1333 * Otherwise, enable Rx scatter if necessary.
1335 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1337 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1338 sizeof(struct rte_mbuf_ext_shared_info) +
1339 RTE_PKTMBUF_HEADROOM;
1341 desc >= (1U << config->mprq.stride_num_n) &&
1342 mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1343 /* TODO: Rx scatter isn't supported yet. */
1344 tmpl->rxq.sges_n = 0;
1345 /* Trim the number of descs needed. */
1346 desc >>= config->mprq.stride_num_n;
1347 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1348 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1349 config->mprq.min_stride_size_n);
1350 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1351 tmpl->rxq.mprq_max_memcpy_len =
1352 RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1353 config->mprq.max_memcpy_len);
1355 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1356 " strd_num_n = %u, strd_sz_n = %u",
1357 dev->data->port_id, idx,
1358 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1359 } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1360 (mb_len - RTE_PKTMBUF_HEADROOM)) {
1361 tmpl->rxq.sges_n = 0;
1362 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1364 RTE_PKTMBUF_HEADROOM +
1365 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1366 unsigned int sges_n;
1369 * Determine the number of SGEs needed for a full packet
1370 * and round it to the next power of two.
1372 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1373 tmpl->rxq.sges_n = sges_n;
1374 /* Make sure rxq.sges_n did not overflow. */
1375 size = mb_len * (1 << tmpl->rxq.sges_n);
1376 size -= RTE_PKTMBUF_HEADROOM;
1377 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1379 "port %u too many SGEs (%u) needed to handle"
1380 " requested maximum packet size %u",
1383 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1384 rte_errno = EOVERFLOW;
1389 "port %u the requested maximum Rx packet size (%u) is"
1390 " larger than a single mbuf (%u) and scattered mode has"
1391 " not been requested",
1393 dev->data->dev_conf.rxmode.max_rx_pkt_len,
1394 mb_len - RTE_PKTMBUF_HEADROOM);
1396 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1397 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1398 if (desc % (1 << tmpl->rxq.sges_n)) {
1400 "port %u number of Rx queue descriptors (%u) is not a"
1401 " multiple of SGEs per packet (%u)",
1404 1 << tmpl->rxq.sges_n);
1408 /* Toggle RX checksum offload if hardware supports it. */
1409 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1410 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1411 /* Configure VLAN stripping. */
1412 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1413 /* By default, FCS (CRC) is stripped by hardware. */
1414 if (offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
1415 tmpl->rxq.crc_present = 0;
1416 } else if (config->hw_fcs_strip) {
1417 tmpl->rxq.crc_present = 1;
1420 "port %u CRC stripping has been disabled but will"
1421 " still be performed by hardware, make sure MLNX_OFED"
1422 " and firmware are up to date",
1423 dev->data->port_id);
1424 tmpl->rxq.crc_present = 0;
1427 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1428 " incoming frames to hide it",
1430 tmpl->rxq.crc_present ? "disabled" : "enabled",
1431 tmpl->rxq.crc_present << 2);
1433 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1434 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1435 tmpl->rxq.port_id = dev->data->port_id;
1438 tmpl->rxq.stats.idx = idx;
1439 tmpl->rxq.elts_n = log2above(desc);
1441 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1443 rte_atomic32_inc(&tmpl->refcnt);
1444 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1455 * Pointer to Ethernet device.
1460 * A pointer to the queue if it exists, NULL otherwise.
1462 struct mlx5_rxq_ctrl *
1463 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1465 struct priv *priv = dev->data->dev_private;
1466 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1468 if ((*priv->rxqs)[idx]) {
1469 rxq_ctrl = container_of((*priv->rxqs)[idx],
1470 struct mlx5_rxq_ctrl,
1472 mlx5_rxq_ibv_get(dev, idx);
1473 rte_atomic32_inc(&rxq_ctrl->refcnt);
1479 * Release a Rx queue.
1482 * Pointer to Ethernet device.
1487 * 1 while a reference on it exists, 0 when freed.
1490 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1492 struct priv *priv = dev->data->dev_private;
1493 struct mlx5_rxq_ctrl *rxq_ctrl;
1495 if (!(*priv->rxqs)[idx])
1497 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1498 assert(rxq_ctrl->priv);
1499 if (rxq_ctrl->ibv && !mlx5_rxq_ibv_release(rxq_ctrl->ibv))
1500 rxq_ctrl->ibv = NULL;
1501 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1502 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1503 LIST_REMOVE(rxq_ctrl, next);
1505 (*priv->rxqs)[idx] = NULL;
1512 * Verify if the queue can be released.
1515 * Pointer to Ethernet device.
1520 * 1 if the queue can be released, negative errno otherwise and rte_errno is
1524 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1526 struct priv *priv = dev->data->dev_private;
1527 struct mlx5_rxq_ctrl *rxq_ctrl;
1529 if (!(*priv->rxqs)[idx]) {
1533 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1534 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1538 * Verify the Rx Queue list is empty
1541 * Pointer to Ethernet device.
1544 * The number of object not released.
1547 mlx5_rxq_verify(struct rte_eth_dev *dev)
1549 struct priv *priv = dev->data->dev_private;
1550 struct mlx5_rxq_ctrl *rxq_ctrl;
1553 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1554 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1555 dev->data->port_id, rxq_ctrl->idx);
1562 * Create an indirection table.
1565 * Pointer to Ethernet device.
1567 * Queues entering in the indirection table.
1569 * Number of queues in the array.
1572 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1574 struct mlx5_ind_table_ibv *
1575 mlx5_ind_table_ibv_new(struct rte_eth_dev *dev, const uint16_t *queues,
1578 struct priv *priv = dev->data->dev_private;
1579 struct mlx5_ind_table_ibv *ind_tbl;
1580 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1581 log2above(queues_n) :
1582 log2above(priv->config.ind_table_max_size);
1583 struct ibv_wq *wq[1 << wq_n];
1587 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1588 queues_n * sizeof(uint16_t), 0);
1593 for (i = 0; i != queues_n; ++i) {
1594 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1598 wq[i] = rxq->ibv->wq;
1599 ind_tbl->queues[i] = queues[i];
1601 ind_tbl->queues_n = queues_n;
1602 /* Finalise indirection table. */
1603 for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1605 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1607 &(struct ibv_rwq_ind_table_init_attr){
1608 .log_ind_tbl_size = wq_n,
1612 if (!ind_tbl->ind_table) {
1616 rte_atomic32_inc(&ind_tbl->refcnt);
1617 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1621 DEBUG("port %u cannot create indirection table", dev->data->port_id);
1626 * Get an indirection table.
1629 * Pointer to Ethernet device.
1631 * Queues entering in the indirection table.
1633 * Number of queues in the array.
1636 * An indirection table if found.
1638 struct mlx5_ind_table_ibv *
1639 mlx5_ind_table_ibv_get(struct rte_eth_dev *dev, const uint16_t *queues,
1642 struct priv *priv = dev->data->dev_private;
1643 struct mlx5_ind_table_ibv *ind_tbl;
1645 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1646 if ((ind_tbl->queues_n == queues_n) &&
1647 (memcmp(ind_tbl->queues, queues,
1648 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1655 rte_atomic32_inc(&ind_tbl->refcnt);
1656 for (i = 0; i != ind_tbl->queues_n; ++i)
1657 mlx5_rxq_get(dev, ind_tbl->queues[i]);
1663 * Release an indirection table.
1666 * Pointer to Ethernet device.
1668 * Indirection table to release.
1671 * 1 while a reference on it exists, 0 when freed.
1674 mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
1675 struct mlx5_ind_table_ibv *ind_tbl)
1679 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1680 claim_zero(mlx5_glue->destroy_rwq_ind_table
1681 (ind_tbl->ind_table));
1682 for (i = 0; i != ind_tbl->queues_n; ++i)
1683 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1684 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1685 LIST_REMOVE(ind_tbl, next);
1693 * Verify the Rx Queue list is empty
1696 * Pointer to Ethernet device.
1699 * The number of object not released.
1702 mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev)
1704 struct priv *priv = dev->data->dev_private;
1705 struct mlx5_ind_table_ibv *ind_tbl;
1708 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1710 "port %u Verbs indirection table %p still referenced",
1711 dev->data->port_id, (void *)ind_tbl);
1718 * Create an Rx Hash queue.
1721 * Pointer to Ethernet device.
1723 * RSS key for the Rx hash queue.
1724 * @param rss_key_len
1726 * @param hash_fields
1727 * Verbs protocol hash field to make the RSS on.
1729 * Queues entering in hash queue. In case of empty hash_fields only the
1730 * first queue index will be taken for the indirection table.
1734 * Tunnel type, implies tunnel offloading like inner checksum if available.
1736 * RSS hash on tunnel level.
1739 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1742 mlx5_hrxq_new(struct rte_eth_dev *dev,
1743 const uint8_t *rss_key, uint32_t rss_key_len,
1744 uint64_t hash_fields,
1745 const uint16_t *queues, uint32_t queues_n,
1746 uint32_t tunnel, uint32_t rss_level)
1748 struct priv *priv = dev->data->dev_private;
1749 struct mlx5_hrxq *hrxq;
1750 struct mlx5_ind_table_ibv *ind_tbl;
1753 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1754 struct mlx5dv_qp_init_attr qp_init_attr = {0};
1757 queues_n = hash_fields ? queues_n : 1;
1758 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1760 ind_tbl = mlx5_ind_table_ibv_new(dev, queues, queues_n);
1766 rss_key_len = rss_hash_default_key_len;
1767 rss_key = rss_hash_default_key;
1769 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1771 qp_init_attr.comp_mask =
1772 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1773 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1775 qp = mlx5_glue->dv_create_qp
1777 &(struct ibv_qp_init_attr_ex){
1778 .qp_type = IBV_QPT_RAW_PACKET,
1780 IBV_QP_INIT_ATTR_PD |
1781 IBV_QP_INIT_ATTR_IND_TABLE |
1782 IBV_QP_INIT_ATTR_RX_HASH,
1783 .rx_hash_conf = (struct ibv_rx_hash_conf){
1784 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1785 .rx_hash_key_len = rss_key_len ? rss_key_len :
1786 rss_hash_default_key_len,
1787 .rx_hash_key = rss_key ?
1788 (void *)(uintptr_t)rss_key :
1789 rss_hash_default_key,
1790 .rx_hash_fields_mask = hash_fields |
1791 (tunnel && rss_level > 1 ?
1792 (uint32_t)IBV_RX_HASH_INNER : 0),
1794 .rwq_ind_tbl = ind_tbl->ind_table,
1799 qp = mlx5_glue->create_qp_ex
1801 &(struct ibv_qp_init_attr_ex){
1802 .qp_type = IBV_QPT_RAW_PACKET,
1804 IBV_QP_INIT_ATTR_PD |
1805 IBV_QP_INIT_ATTR_IND_TABLE |
1806 IBV_QP_INIT_ATTR_RX_HASH,
1807 .rx_hash_conf = (struct ibv_rx_hash_conf){
1808 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1809 .rx_hash_key_len = rss_key_len ? rss_key_len :
1810 rss_hash_default_key_len,
1811 .rx_hash_key = rss_key ?
1812 (void *)(uintptr_t)rss_key :
1813 rss_hash_default_key,
1814 .rx_hash_fields_mask = hash_fields,
1816 .rwq_ind_tbl = ind_tbl->ind_table,
1824 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1827 hrxq->ind_table = ind_tbl;
1829 hrxq->rss_key_len = rss_key_len;
1830 hrxq->hash_fields = hash_fields;
1831 hrxq->tunnel = tunnel;
1832 hrxq->rss_level = rss_level;
1833 memcpy(hrxq->rss_key, rss_key, rss_key_len);
1834 rte_atomic32_inc(&hrxq->refcnt);
1835 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1838 err = rte_errno; /* Save rte_errno before cleanup. */
1839 mlx5_ind_table_ibv_release(dev, ind_tbl);
1841 claim_zero(mlx5_glue->destroy_qp(qp));
1842 rte_errno = err; /* Restore rte_errno. */
1847 * Get an Rx Hash queue.
1850 * Pointer to Ethernet device.
1852 * RSS configuration for the Rx hash queue.
1854 * Queues entering in hash queue. In case of empty hash_fields only the
1855 * first queue index will be taken for the indirection table.
1859 * Tunnel type, implies tunnel offloading like inner checksum if available.
1861 * RSS hash on tunnel level
1864 * An hash Rx queue on success.
1867 mlx5_hrxq_get(struct rte_eth_dev *dev,
1868 const uint8_t *rss_key, uint32_t rss_key_len,
1869 uint64_t hash_fields,
1870 const uint16_t *queues, uint32_t queues_n,
1871 uint32_t tunnel, uint32_t rss_level)
1873 struct priv *priv = dev->data->dev_private;
1874 struct mlx5_hrxq *hrxq;
1876 queues_n = hash_fields ? queues_n : 1;
1877 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1878 struct mlx5_ind_table_ibv *ind_tbl;
1880 if (hrxq->rss_key_len != rss_key_len)
1882 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1884 if (hrxq->hash_fields != hash_fields)
1886 if (hrxq->tunnel != tunnel)
1888 if (hrxq->rss_level != rss_level)
1890 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1893 if (ind_tbl != hrxq->ind_table) {
1894 mlx5_ind_table_ibv_release(dev, ind_tbl);
1897 rte_atomic32_inc(&hrxq->refcnt);
1904 * Release the hash Rx queue.
1907 * Pointer to Ethernet device.
1909 * Pointer to Hash Rx queue to release.
1912 * 1 while a reference on it exists, 0 when freed.
1915 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1917 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1918 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
1919 mlx5_ind_table_ibv_release(dev, hrxq->ind_table);
1920 LIST_REMOVE(hrxq, next);
1924 claim_nonzero(mlx5_ind_table_ibv_release(dev, hrxq->ind_table));
1929 * Verify the Rx Queue list is empty
1932 * Pointer to Ethernet device.
1935 * The number of object not released.
1938 mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev)
1940 struct priv *priv = dev->data->dev_private;
1941 struct mlx5_hrxq *hrxq;
1944 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1946 "port %u Verbs hash Rx queue %p still referenced",
1947 dev->data->port_id, (void *)hrxq);