1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 #include <sys/queue.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
29 #include <rte_interrupts.h>
30 #include <rte_debug.h>
34 #include "mlx5_rxtx.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
38 #include "mlx5_glue.h"
40 /* Default RSS hash key also used for ConnectX-3. */
41 uint8_t rss_hash_default_key[] = {
42 0x2c, 0xc6, 0x81, 0xd1,
43 0x5b, 0xdb, 0xf4, 0xf7,
44 0xfc, 0xa2, 0x83, 0x19,
45 0xdb, 0x1a, 0x3e, 0x94,
46 0x6b, 0x9e, 0x38, 0xd9,
47 0x2c, 0x9c, 0x03, 0xd1,
48 0xad, 0x99, 0x44, 0xa7,
49 0xd9, 0x56, 0x3d, 0x59,
50 0x06, 0x3c, 0x25, 0xf3,
51 0xfc, 0x1f, 0xdc, 0x2a,
54 /* Length of the default RSS hash key. */
55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
56 (unsigned int)sizeof(rss_hash_default_key),
57 "wrong RSS default key size.");
60 * Check whether Multi-Packet RQ can be enabled for the device.
63 * Pointer to Ethernet device.
66 * 1 if supported, negative errno value if not.
69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
71 struct mlx5_priv *priv = dev->data->dev_private;
73 if (priv->config.mprq.enabled &&
74 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
80 * Check whether Multi-Packet RQ is enabled for the Rx queue.
83 * Pointer to receive queue structure.
86 * 0 if disabled, otherwise enabled.
89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
91 return rxq->strd_num_n > 0;
95 * Check whether Multi-Packet RQ is enabled for the device.
98 * Pointer to Ethernet device.
101 * 0 if disabled, otherwise enabled.
104 mlx5_mprq_enabled(struct rte_eth_dev *dev)
106 struct mlx5_priv *priv = dev->data->dev_private;
111 if (mlx5_check_mprq_support(dev) < 0)
113 /* All the configured queues should be enabled. */
114 for (i = 0; i < priv->rxqs_n; ++i) {
115 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
116 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
117 (rxq, struct mlx5_rxq_ctrl, rxq);
119 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
122 if (mlx5_rxq_mprq_enabled(rxq))
125 /* Multi-Packet RQ can't be partially configured. */
126 assert(n == 0 || n == n_ibv);
131 * Allocate RX queue elements for Multi-Packet RQ.
134 * Pointer to RX queue structure.
137 * 0 on success, a negative errno value otherwise and rte_errno is set.
140 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
142 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
143 unsigned int wqe_n = 1 << rxq->elts_n;
147 /* Iterate on segments. */
148 for (i = 0; i <= wqe_n; ++i) {
149 struct mlx5_mprq_buf *buf;
151 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
152 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
157 (*rxq->mprq_bufs)[i] = buf;
159 rxq->mprq_repl = buf;
162 "port %u Rx queue %u allocated and configured %u segments",
163 rxq->port_id, rxq->idx, wqe_n);
166 err = rte_errno; /* Save rte_errno before cleanup. */
168 for (i = 0; (i != wqe_n); ++i) {
169 if ((*rxq->mprq_bufs)[i] != NULL)
170 rte_mempool_put(rxq->mprq_mp,
171 (*rxq->mprq_bufs)[i]);
172 (*rxq->mprq_bufs)[i] = NULL;
174 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
175 rxq->port_id, rxq->idx);
176 rte_errno = err; /* Restore rte_errno. */
181 * Allocate RX queue elements for Single-Packet RQ.
184 * Pointer to RX queue structure.
187 * 0 on success, errno value on failure.
190 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
192 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
193 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
197 /* Iterate on segments. */
198 for (i = 0; (i != elts_n); ++i) {
199 struct rte_mbuf *buf;
201 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
203 DRV_LOG(ERR, "port %u empty mbuf pool",
204 PORT_ID(rxq_ctrl->priv));
208 /* Headroom is reserved by rte_pktmbuf_alloc(). */
209 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
210 /* Buffer is supposed to be empty. */
211 assert(rte_pktmbuf_data_len(buf) == 0);
212 assert(rte_pktmbuf_pkt_len(buf) == 0);
214 /* Only the first segment keeps headroom. */
216 SET_DATA_OFF(buf, 0);
217 PORT(buf) = rxq_ctrl->rxq.port_id;
218 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
219 PKT_LEN(buf) = DATA_LEN(buf);
221 (*rxq_ctrl->rxq.elts)[i] = buf;
223 /* If Rx vector is activated. */
224 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
225 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
226 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
229 /* Initialize default rearm_data for vPMD. */
230 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
231 rte_mbuf_refcnt_set(mbuf_init, 1);
232 mbuf_init->nb_segs = 1;
233 mbuf_init->port = rxq->port_id;
235 * prevent compiler reordering:
236 * rearm_data covers previous fields.
238 rte_compiler_barrier();
239 rxq->mbuf_initializer =
240 *(uint64_t *)&mbuf_init->rearm_data;
241 /* Padding with a fake mbuf for vectorized Rx. */
242 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
243 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
246 "port %u Rx queue %u allocated and configured %u segments"
248 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
249 elts_n / (1 << rxq_ctrl->rxq.sges_n));
252 err = rte_errno; /* Save rte_errno before cleanup. */
254 for (i = 0; (i != elts_n); ++i) {
255 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
256 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
257 (*rxq_ctrl->rxq.elts)[i] = NULL;
259 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
260 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
261 rte_errno = err; /* Restore rte_errno. */
266 * Allocate RX queue elements.
269 * Pointer to RX queue structure.
272 * 0 on success, errno value on failure.
275 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
277 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
278 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
282 * Free RX queue elements for Multi-Packet RQ.
285 * Pointer to RX queue structure.
288 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
290 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
293 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
294 rxq->port_id, rxq->idx);
295 if (rxq->mprq_bufs == NULL)
297 assert(mlx5_rxq_check_vec_support(rxq) < 0);
298 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
299 if ((*rxq->mprq_bufs)[i] != NULL)
300 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
301 (*rxq->mprq_bufs)[i] = NULL;
303 if (rxq->mprq_repl != NULL) {
304 mlx5_mprq_buf_free(rxq->mprq_repl);
305 rxq->mprq_repl = NULL;
310 * Free RX queue elements for Single-Packet RQ.
313 * Pointer to RX queue structure.
316 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
318 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
319 const uint16_t q_n = (1 << rxq->elts_n);
320 const uint16_t q_mask = q_n - 1;
321 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
324 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
325 PORT_ID(rxq_ctrl->priv), rxq->idx);
326 if (rxq->elts == NULL)
329 * Some mbuf in the Ring belongs to the application. They cannot be
332 if (mlx5_rxq_check_vec_support(rxq) > 0) {
333 for (i = 0; i < used; ++i)
334 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
335 rxq->rq_pi = rxq->rq_ci;
337 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
338 if ((*rxq->elts)[i] != NULL)
339 rte_pktmbuf_free_seg((*rxq->elts)[i]);
340 (*rxq->elts)[i] = NULL;
345 * Free RX queue elements.
348 * Pointer to RX queue structure.
351 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
353 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
354 rxq_free_elts_mprq(rxq_ctrl);
356 rxq_free_elts_sprq(rxq_ctrl);
360 * Returns the per-queue supported offloads.
363 * Pointer to Ethernet device.
366 * Supported Rx offloads.
369 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
371 struct mlx5_priv *priv = dev->data->dev_private;
372 struct mlx5_dev_config *config = &priv->config;
373 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
374 DEV_RX_OFFLOAD_TIMESTAMP |
375 DEV_RX_OFFLOAD_JUMBO_FRAME |
376 DEV_RX_OFFLOAD_RSS_HASH);
378 if (config->hw_fcs_strip)
379 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
382 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
383 DEV_RX_OFFLOAD_UDP_CKSUM |
384 DEV_RX_OFFLOAD_TCP_CKSUM);
385 if (config->hw_vlan_strip)
386 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
387 if (MLX5_LRO_SUPPORTED(dev))
388 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
394 * Returns the per-port supported offloads.
397 * Supported Rx offloads.
400 mlx5_get_rx_port_offloads(void)
402 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
408 * Verify if the queue can be released.
411 * Pointer to Ethernet device.
416 * 1 if the queue can be released
417 * 0 if the queue can not be released, there are references to it.
418 * Negative errno and rte_errno is set if queue doesn't exist.
421 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
423 struct mlx5_priv *priv = dev->data->dev_private;
424 struct mlx5_rxq_ctrl *rxq_ctrl;
426 if (!(*priv->rxqs)[idx]) {
430 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
431 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
435 * Rx queue presetup checks.
438 * Pointer to Ethernet device structure.
442 * Number of descriptors to configure in queue.
445 * 0 on success, a negative errno value otherwise and rte_errno is set.
448 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
450 struct mlx5_priv *priv = dev->data->dev_private;
452 if (!rte_is_power_of_2(desc)) {
453 desc = 1 << log2above(desc);
455 "port %u increased number of descriptors in Rx queue %u"
456 " to the next power of two (%d)",
457 dev->data->port_id, idx, desc);
459 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
460 dev->data->port_id, idx, desc);
461 if (idx >= priv->rxqs_n) {
462 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
463 dev->data->port_id, idx, priv->rxqs_n);
464 rte_errno = EOVERFLOW;
467 if (!mlx5_rxq_releasable(dev, idx)) {
468 DRV_LOG(ERR, "port %u unable to release queue index %u",
469 dev->data->port_id, idx);
473 mlx5_rxq_release(dev, idx);
480 * Pointer to Ethernet device structure.
484 * Number of descriptors to configure in queue.
486 * NUMA socket on which memory must be allocated.
488 * Thresholds parameters.
490 * Memory pool for buffer allocations.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
497 unsigned int socket, const struct rte_eth_rxconf *conf,
498 struct rte_mempool *mp)
500 struct mlx5_priv *priv = dev->data->dev_private;
501 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
502 struct mlx5_rxq_ctrl *rxq_ctrl =
503 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
506 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
509 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
511 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
512 dev->data->port_id, idx);
516 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
517 dev->data->port_id, idx);
518 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
525 * Pointer to Ethernet device structure.
529 * Number of descriptors to configure in queue.
530 * @param hairpin_conf
531 * Hairpin configuration parameters.
534 * 0 on success, a negative errno value otherwise and rte_errno is set.
537 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
539 const struct rte_eth_hairpin_conf *hairpin_conf)
541 struct mlx5_priv *priv = dev->data->dev_private;
542 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
543 struct mlx5_rxq_ctrl *rxq_ctrl =
544 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
547 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
550 if (hairpin_conf->peer_count != 1 ||
551 hairpin_conf->peers[0].port != dev->data->port_id ||
552 hairpin_conf->peers[0].queue >= priv->txqs_n) {
553 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
554 " invalid hairpind configuration", dev->data->port_id,
559 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
561 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
562 dev->data->port_id, idx);
566 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
567 dev->data->port_id, idx);
568 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
573 * DPDK callback to release a RX queue.
576 * Generic RX queue pointer.
579 mlx5_rx_queue_release(void *dpdk_rxq)
581 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
582 struct mlx5_rxq_ctrl *rxq_ctrl;
583 struct mlx5_priv *priv;
587 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
588 priv = rxq_ctrl->priv;
589 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
590 rte_panic("port %u Rx queue %u is still used by a flow and"
591 " cannot be removed\n",
592 PORT_ID(priv), rxq->idx);
593 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
597 * Get an Rx queue Verbs/DevX object.
600 * Pointer to Ethernet device.
602 * Queue index in DPDK Rx queue array
605 * The Verbs/DevX object if it exists.
607 static struct mlx5_rxq_obj *
608 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
610 struct mlx5_priv *priv = dev->data->dev_private;
611 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
612 struct mlx5_rxq_ctrl *rxq_ctrl;
614 if (idx >= priv->rxqs_n)
618 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
620 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
621 return rxq_ctrl->obj;
625 * Release the resources allocated for an RQ DevX object.
628 * DevX Rx queue object.
631 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
633 if (rxq_ctrl->rxq.wqes) {
634 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
635 rxq_ctrl->rxq.wqes = NULL;
637 if (rxq_ctrl->wq_umem) {
638 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
639 rxq_ctrl->wq_umem = NULL;
644 * Release an Rx hairpin related resources.
647 * Hairpin Rx queue object.
650 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
652 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
655 rq_attr.state = MLX5_RQC_STATE_RST;
656 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
657 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
658 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
662 * Release an Rx verbs/DevX queue object.
665 * Verbs/DevX Rx queue object.
668 * 1 while a reference on it exists, 0 when freed.
671 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
674 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV)
677 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
678 switch (rxq_obj->type) {
679 case MLX5_RXQ_OBJ_TYPE_IBV:
680 rxq_free_elts(rxq_obj->rxq_ctrl);
681 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
682 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
684 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
685 rxq_free_elts(rxq_obj->rxq_ctrl);
686 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
687 rxq_release_rq_resources(rxq_obj->rxq_ctrl);
688 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
690 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
691 rxq_obj_hairpin_release(rxq_obj);
694 if (rxq_obj->channel)
695 claim_zero(mlx5_glue->destroy_comp_channel
697 LIST_REMOVE(rxq_obj, next);
705 * Allocate queue vector and fill epoll fd list for Rx interrupts.
708 * Pointer to Ethernet device.
711 * 0 on success, a negative errno value otherwise and rte_errno is set.
714 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
716 struct mlx5_priv *priv = dev->data->dev_private;
718 unsigned int rxqs_n = priv->rxqs_n;
719 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
720 unsigned int count = 0;
721 struct rte_intr_handle *intr_handle = dev->intr_handle;
723 if (!dev->data->dev_conf.intr_conf.rxq)
725 mlx5_rx_intr_vec_disable(dev);
726 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
727 if (intr_handle->intr_vec == NULL) {
729 "port %u failed to allocate memory for interrupt"
730 " vector, Rx interrupts will not be supported",
735 intr_handle->type = RTE_INTR_HANDLE_EXT;
736 for (i = 0; i != n; ++i) {
737 /* This rxq obj must not be released in this function. */
738 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
743 /* Skip queues that cannot request interrupts. */
744 if (!rxq_obj || !rxq_obj->channel) {
745 /* Use invalid intr_vec[] index to disable entry. */
746 intr_handle->intr_vec[i] =
747 RTE_INTR_VEC_RXTX_OFFSET +
748 RTE_MAX_RXTX_INTR_VEC_ID;
751 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
753 "port %u too many Rx queues for interrupt"
754 " vector size (%d), Rx interrupts cannot be"
756 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
757 mlx5_rx_intr_vec_disable(dev);
761 fd = rxq_obj->channel->fd;
762 flags = fcntl(fd, F_GETFL);
763 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
767 "port %u failed to make Rx interrupt file"
768 " descriptor %d non-blocking for queue index"
770 dev->data->port_id, fd, i);
771 mlx5_rx_intr_vec_disable(dev);
774 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
775 intr_handle->efds[count] = fd;
779 mlx5_rx_intr_vec_disable(dev);
781 intr_handle->nb_efd = count;
786 * Clean up Rx interrupts handler.
789 * Pointer to Ethernet device.
792 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
794 struct mlx5_priv *priv = dev->data->dev_private;
795 struct rte_intr_handle *intr_handle = dev->intr_handle;
797 unsigned int rxqs_n = priv->rxqs_n;
798 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
800 if (!dev->data->dev_conf.intr_conf.rxq)
802 if (!intr_handle->intr_vec)
804 for (i = 0; i != n; ++i) {
805 struct mlx5_rxq_ctrl *rxq_ctrl;
806 struct mlx5_rxq_data *rxq_data;
808 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
809 RTE_MAX_RXTX_INTR_VEC_ID)
812 * Need to access directly the queue to release the reference
813 * kept in mlx5_rx_intr_vec_enable().
815 rxq_data = (*priv->rxqs)[i];
816 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
818 mlx5_rxq_obj_release(rxq_ctrl->obj);
821 rte_intr_free_epoll_fd(intr_handle);
822 if (intr_handle->intr_vec)
823 free(intr_handle->intr_vec);
824 intr_handle->nb_efd = 0;
825 intr_handle->intr_vec = NULL;
829 * MLX5 CQ notification .
832 * Pointer to receive queue structure.
834 * Sequence number per receive queue .
837 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
840 uint32_t doorbell_hi;
842 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
844 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
845 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
846 doorbell = (uint64_t)doorbell_hi << 32;
847 doorbell |= rxq->cqn;
848 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
849 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
850 cq_db_reg, rxq->uar_lock_cq);
854 * DPDK callback for Rx queue interrupt enable.
857 * Pointer to Ethernet device structure.
862 * 0 on success, a negative errno value otherwise and rte_errno is set.
865 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
867 struct mlx5_priv *priv = dev->data->dev_private;
868 struct mlx5_rxq_data *rxq_data;
869 struct mlx5_rxq_ctrl *rxq_ctrl;
871 rxq_data = (*priv->rxqs)[rx_queue_id];
876 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
878 struct mlx5_rxq_obj *rxq_obj;
880 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
885 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
886 mlx5_rxq_obj_release(rxq_obj);
892 * DPDK callback for Rx queue interrupt disable.
895 * Pointer to Ethernet device structure.
900 * 0 on success, a negative errno value otherwise and rte_errno is set.
903 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
905 struct mlx5_priv *priv = dev->data->dev_private;
906 struct mlx5_rxq_data *rxq_data;
907 struct mlx5_rxq_ctrl *rxq_ctrl;
908 struct mlx5_rxq_obj *rxq_obj = NULL;
909 struct ibv_cq *ev_cq;
913 rxq_data = (*priv->rxqs)[rx_queue_id];
918 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
921 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
926 ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
927 if (ret || ev_cq != rxq_obj->cq) {
931 rxq_data->cq_arm_sn++;
932 mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
933 mlx5_rxq_obj_release(rxq_obj);
936 ret = rte_errno; /* Save rte_errno before cleanup. */
938 mlx5_rxq_obj_release(rxq_obj);
939 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
940 dev->data->port_id, rx_queue_id);
941 rte_errno = ret; /* Restore rte_errno. */
946 * Create a CQ Verbs object.
949 * Pointer to Ethernet device.
951 * Pointer to device private data.
953 * Pointer to Rx queue data.
955 * Number of CQEs in CQ.
957 * Pointer to Rx queue object data.
960 * The Verbs object initialised, NULL otherwise and rte_errno is set.
962 static struct ibv_cq *
963 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
964 struct mlx5_rxq_data *rxq_data,
965 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
968 struct ibv_cq_init_attr_ex ibv;
969 struct mlx5dv_cq_init_attr mlx5;
972 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
974 .channel = rxq_obj->channel,
977 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
980 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
982 cq_attr.mlx5.comp_mask |=
983 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
984 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
985 cq_attr.mlx5.cqe_comp_res_format =
986 mlx5_rxq_mprq_enabled(rxq_data) ?
987 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
988 MLX5DV_CQE_RES_FORMAT_HASH;
990 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
993 * For vectorized Rx, it must not be doubled in order to
994 * make cq_ci and rq_ci aligned.
996 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
997 cq_attr.ibv.cqe *= 2;
998 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1000 "port %u Rx CQE compression is disabled for HW"
1002 dev->data->port_id);
1003 } else if (priv->config.cqe_comp && rxq_data->lro) {
1005 "port %u Rx CQE compression is disabled for LRO",
1006 dev->data->port_id);
1008 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1009 if (priv->config.cqe_pad) {
1010 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1011 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1014 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1020 * Create a WQ Verbs object.
1023 * Pointer to Ethernet device.
1025 * Pointer to device private data.
1027 * Pointer to Rx queue data.
1029 * Queue index in DPDK Rx queue array
1031 * Number of WQEs in WQ.
1033 * Pointer to Rx queue object data.
1036 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1038 static struct ibv_wq *
1039 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1040 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1041 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1044 struct ibv_wq_init_attr ibv;
1045 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1046 struct mlx5dv_wq_init_attr mlx5;
1050 wq_attr.ibv = (struct ibv_wq_init_attr){
1051 .wq_context = NULL, /* Could be useful in the future. */
1052 .wq_type = IBV_WQT_RQ,
1053 /* Max number of outstanding WRs. */
1054 .max_wr = wqe_n >> rxq_data->sges_n,
1055 /* Max number of scatter/gather elements in a WR. */
1056 .max_sge = 1 << rxq_data->sges_n,
1059 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1060 .create_flags = (rxq_data->vlan_strip ?
1061 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1063 /* By default, FCS (CRC) is stripped by hardware. */
1064 if (rxq_data->crc_present) {
1065 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1066 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1068 if (priv->config.hw_padding) {
1069 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1070 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1071 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1072 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1073 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1074 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1077 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1078 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1081 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1082 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1083 &wq_attr.mlx5.striding_rq_attrs;
1085 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1086 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1087 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1088 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1089 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1092 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1095 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1099 * Make sure number of WRs*SGEs match expectations since a queue
1100 * cannot allocate more than "desc" buffers.
1102 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1103 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1105 "port %u Rx queue %u requested %u*%u but got"
1107 dev->data->port_id, idx,
1108 wqe_n >> rxq_data->sges_n,
1109 (1 << rxq_data->sges_n),
1110 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1111 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1120 * Fill common fields of create RQ attributes structure.
1123 * Pointer to Rx queue data.
1125 * CQ number to use with this RQ.
1127 * RQ attributes structure to fill..
1130 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1131 struct mlx5_devx_create_rq_attr *rq_attr)
1133 rq_attr->state = MLX5_RQC_STATE_RST;
1134 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1136 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1140 * Fill common fields of DevX WQ attributes structure.
1143 * Pointer to device private data.
1145 * Pointer to Rx queue control structure.
1147 * WQ attributes structure to fill..
1150 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1151 struct mlx5_devx_wq_attr *wq_attr)
1153 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1154 MLX5_WQ_END_PAD_MODE_ALIGN :
1155 MLX5_WQ_END_PAD_MODE_NONE;
1156 wq_attr->pd = priv->sh->pdn;
1157 wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1158 wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1159 wq_attr->dbr_umem_valid = 1;
1160 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1161 wq_attr->wq_umem_valid = 1;
1165 * Create a RQ object using DevX.
1168 * Pointer to Ethernet device.
1170 * Queue index in DPDK Rx queue array
1172 * CQ number to use with this RQ.
1175 * The DevX object initialised, NULL otherwise and rte_errno is set.
1177 static struct mlx5_devx_obj *
1178 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1180 struct mlx5_priv *priv = dev->data->dev_private;
1181 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1182 struct mlx5_rxq_ctrl *rxq_ctrl =
1183 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1184 struct mlx5_devx_create_rq_attr rq_attr;
1185 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1186 uint32_t wq_size = 0;
1187 uint32_t wqe_size = 0;
1188 uint32_t log_wqe_size = 0;
1190 struct mlx5_devx_obj *rq;
1192 memset(&rq_attr, 0, sizeof(rq_attr));
1193 /* Fill RQ attributes. */
1194 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1195 rq_attr.flush_in_error_en = 1;
1196 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1197 /* Fill WQ attributes for this RQ. */
1198 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1199 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1201 * Number of strides in each WQE:
1202 * 512*2^single_wqe_log_num_of_strides.
1204 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1205 rxq_data->strd_num_n -
1206 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1207 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1208 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1209 rxq_data->strd_sz_n -
1210 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1211 wqe_size = sizeof(struct mlx5_wqe_mprq);
1213 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1214 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1216 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1217 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1218 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1219 /* Calculate and allocate WQ memory space. */
1220 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1221 wq_size = wqe_n * wqe_size;
1222 buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1226 rxq_data->wqes = buf;
1227 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1229 if (!rxq_ctrl->wq_umem) {
1233 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1234 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1236 rxq_release_rq_resources(rxq_ctrl);
1241 * Create the Rx hairpin queue object.
1244 * Pointer to Ethernet device.
1246 * Queue index in DPDK Rx queue array
1249 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1251 static struct mlx5_rxq_obj *
1252 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1254 struct mlx5_priv *priv = dev->data->dev_private;
1255 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1256 struct mlx5_rxq_ctrl *rxq_ctrl =
1257 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1258 struct mlx5_devx_create_rq_attr attr = { 0 };
1259 struct mlx5_rxq_obj *tmpl = NULL;
1263 assert(!rxq_ctrl->obj);
1264 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1268 "port %u Rx queue %u cannot allocate verbs resources",
1269 dev->data->port_id, rxq_data->idx);
1273 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1274 tmpl->rxq_ctrl = rxq_ctrl;
1276 /* Workaround for hairpin startup */
1277 attr.wq_attr.log_hairpin_num_packets = log2above(32);
1278 /* Workaround for packets larger than 1KB */
1279 attr.wq_attr.log_hairpin_data_sz =
1280 priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1281 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1285 "port %u Rx hairpin queue %u can't create rq object",
1286 dev->data->port_id, idx);
1290 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1291 idx, (void *)&tmpl);
1292 rte_atomic32_inc(&tmpl->refcnt);
1293 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1294 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1297 ret = rte_errno; /* Save rte_errno before cleanup. */
1299 mlx5_devx_cmd_destroy(tmpl->rq);
1300 rte_errno = ret; /* Restore rte_errno. */
1305 * Create the Rx queue Verbs/DevX object.
1308 * Pointer to Ethernet device.
1310 * Queue index in DPDK Rx queue array
1312 * Type of Rx queue object to create.
1315 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1317 struct mlx5_rxq_obj *
1318 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1319 enum mlx5_rxq_obj_type type)
1321 struct mlx5_priv *priv = dev->data->dev_private;
1322 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1323 struct mlx5_rxq_ctrl *rxq_ctrl =
1324 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1325 struct ibv_wq_attr mod;
1327 unsigned int wqe_n = 1 << rxq_data->elts_n;
1328 struct mlx5_rxq_obj *tmpl = NULL;
1329 struct mlx5dv_cq cq_info;
1330 struct mlx5dv_rwq rwq;
1332 struct mlx5dv_obj obj;
1335 assert(!rxq_ctrl->obj);
1336 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1337 return mlx5_rxq_obj_hairpin_new(dev, idx);
1338 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1339 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1340 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1344 "port %u Rx queue %u cannot allocate verbs resources",
1345 dev->data->port_id, rxq_data->idx);
1350 tmpl->rxq_ctrl = rxq_ctrl;
1351 if (rxq_ctrl->irq) {
1352 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1353 if (!tmpl->channel) {
1354 DRV_LOG(ERR, "port %u: comp channel creation failure",
1355 dev->data->port_id);
1360 if (mlx5_rxq_mprq_enabled(rxq_data))
1361 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1364 tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1366 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1367 dev->data->port_id, idx);
1371 obj.cq.in = tmpl->cq;
1372 obj.cq.out = &cq_info;
1373 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1378 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1380 "port %u wrong MLX5_CQE_SIZE environment variable"
1381 " value: it should be set to %u",
1382 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1386 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1387 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1388 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1389 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1390 /* Allocate door-bell for types created with DevX. */
1391 if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1392 struct mlx5_devx_dbr_page *dbr_page;
1395 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1398 rxq_ctrl->dbr_offset = dbr_offset;
1399 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1400 rxq_ctrl->dbr_umem_id_valid = 1;
1401 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1402 (uintptr_t)rxq_ctrl->dbr_offset);
1404 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1405 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1408 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1409 dev->data->port_id, idx);
1413 /* Change queue state to ready. */
1414 mod = (struct ibv_wq_attr){
1415 .attr_mask = IBV_WQ_ATTR_STATE,
1416 .wq_state = IBV_WQS_RDY,
1418 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1421 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1422 " failed", dev->data->port_id, idx);
1426 obj.rwq.in = tmpl->wq;
1428 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1433 rxq_data->wqes = rwq.buf;
1434 rxq_data->rq_db = rwq.dbrec;
1435 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1436 struct mlx5_devx_modify_rq_attr rq_attr;
1438 memset(&rq_attr, 0, sizeof(rq_attr));
1439 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1441 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1442 dev->data->port_id, idx);
1446 /* Change queue state to ready. */
1447 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1448 rq_attr.state = MLX5_RQC_STATE_RDY;
1449 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1453 /* Fill the rings. */
1454 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1455 rxq_data->cq_db = cq_info.dbrec;
1456 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1457 rxq_data->cq_uar = cq_info.cq_uar;
1458 rxq_data->cqn = cq_info.cqn;
1459 rxq_data->cq_arm_sn = 0;
1460 mlx5_rxq_initialize(rxq_data);
1461 rxq_data->cq_ci = 0;
1462 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1463 idx, (void *)&tmpl);
1464 rte_atomic32_inc(&tmpl->refcnt);
1465 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1466 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1470 ret = rte_errno; /* Save rte_errno before cleanup. */
1471 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1472 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1473 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1474 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1476 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1478 claim_zero(mlx5_glue->destroy_comp_channel
1481 rte_errno = ret; /* Restore rte_errno. */
1483 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1484 rxq_release_rq_resources(rxq_ctrl);
1485 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1490 * Verify the Rx queue objects list is empty
1493 * Pointer to Ethernet device.
1496 * The number of objects not released.
1499 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1501 struct mlx5_priv *priv = dev->data->dev_private;
1503 struct mlx5_rxq_obj *rxq_obj;
1505 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1506 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1507 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1514 * Callback function to initialize mbufs for Multi-Packet RQ.
1517 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1518 void *_m, unsigned int i __rte_unused)
1520 struct mlx5_mprq_buf *buf = _m;
1521 struct rte_mbuf_ext_shared_info *shinfo;
1522 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1525 memset(_m, 0, sizeof(*buf));
1527 rte_atomic16_set(&buf->refcnt, 1);
1528 for (j = 0; j != strd_n; ++j) {
1529 shinfo = &buf->shinfos[j];
1530 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1531 shinfo->fcb_opaque = buf;
1536 * Free mempool of Multi-Packet RQ.
1539 * Pointer to Ethernet device.
1542 * 0 on success, negative errno value on failure.
1545 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1547 struct mlx5_priv *priv = dev->data->dev_private;
1548 struct rte_mempool *mp = priv->mprq_mp;
1553 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1554 dev->data->port_id, mp->name);
1556 * If a buffer in the pool has been externally attached to a mbuf and it
1557 * is still in use by application, destroying the Rx queue can spoil
1558 * the packet. It is unlikely to happen but if application dynamically
1559 * creates and destroys with holding Rx packets, this can happen.
1561 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1562 * RQ isn't provided by application but managed by PMD.
1564 if (!rte_mempool_full(mp)) {
1566 "port %u mempool for Multi-Packet RQ is still in use",
1567 dev->data->port_id);
1571 rte_mempool_free(mp);
1572 /* Unset mempool for each Rx queue. */
1573 for (i = 0; i != priv->rxqs_n; ++i) {
1574 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1578 rxq->mprq_mp = NULL;
1580 priv->mprq_mp = NULL;
1585 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1586 * mempool. If already allocated, reuse it if there're enough elements.
1587 * Otherwise, resize it.
1590 * Pointer to Ethernet device.
1593 * 0 on success, negative errno value on failure.
1596 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1598 struct mlx5_priv *priv = dev->data->dev_private;
1599 struct rte_mempool *mp = priv->mprq_mp;
1600 char name[RTE_MEMPOOL_NAMESIZE];
1601 unsigned int desc = 0;
1602 unsigned int buf_len;
1603 unsigned int obj_num;
1604 unsigned int obj_size;
1605 unsigned int strd_num_n = 0;
1606 unsigned int strd_sz_n = 0;
1608 unsigned int n_ibv = 0;
1610 if (!mlx5_mprq_enabled(dev))
1612 /* Count the total number of descriptors configured. */
1613 for (i = 0; i != priv->rxqs_n; ++i) {
1614 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1615 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1616 (rxq, struct mlx5_rxq_ctrl, rxq);
1618 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1621 desc += 1 << rxq->elts_n;
1622 /* Get the max number of strides. */
1623 if (strd_num_n < rxq->strd_num_n)
1624 strd_num_n = rxq->strd_num_n;
1625 /* Get the max size of a stride. */
1626 if (strd_sz_n < rxq->strd_sz_n)
1627 strd_sz_n = rxq->strd_sz_n;
1629 assert(strd_num_n && strd_sz_n);
1630 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1631 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1632 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1634 * Received packets can be either memcpy'd or externally referenced. In
1635 * case that the packet is attached to an mbuf as an external buffer, as
1636 * it isn't possible to predict how the buffers will be queued by
1637 * application, there's no option to exactly pre-allocate needed buffers
1638 * in advance but to speculatively prepares enough buffers.
1640 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1641 * received packets to buffers provided by application (rxq->mp) until
1642 * this Mempool gets available again.
1645 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1647 * rte_mempool_create_empty() has sanity check to refuse large cache
1648 * size compared to the number of elements.
1649 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1650 * constant number 2 instead.
1652 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1653 /* Check a mempool is already allocated and if it can be resued. */
1654 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1655 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1656 dev->data->port_id, mp->name);
1659 } else if (mp != NULL) {
1660 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1661 dev->data->port_id, mp->name);
1663 * If failed to free, which means it may be still in use, no way
1664 * but to keep using the existing one. On buffer underrun,
1665 * packets will be memcpy'd instead of external buffer
1668 if (mlx5_mprq_free_mp(dev)) {
1669 if (mp->elt_size >= obj_size)
1675 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1676 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1677 0, NULL, NULL, mlx5_mprq_buf_init,
1678 (void *)(uintptr_t)(1 << strd_num_n),
1679 dev->device->numa_node, 0);
1682 "port %u failed to allocate a mempool for"
1683 " Multi-Packet RQ, count=%u, size=%u",
1684 dev->data->port_id, obj_num, obj_size);
1690 /* Set mempool for each Rx queue. */
1691 for (i = 0; i != priv->rxqs_n; ++i) {
1692 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1693 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1694 (rxq, struct mlx5_rxq_ctrl, rxq);
1696 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1700 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1701 dev->data->port_id);
1705 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1706 sizeof(struct rte_vlan_hdr) * 2 + \
1707 sizeof(struct rte_ipv6_hdr)))
1708 #define MAX_TCP_OPTION_SIZE 40u
1709 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1710 sizeof(struct rte_tcp_hdr) + \
1711 MAX_TCP_OPTION_SIZE))
1714 * Adjust the maximum LRO massage size.
1717 * Pointer to Ethernet device.
1718 * @param max_lro_size
1719 * The maximum size for LRO packet.
1722 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint32_t max_lro_size)
1724 struct mlx5_priv *priv = dev->data->dev_private;
1726 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1727 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1728 MLX5_MAX_TCP_HDR_OFFSET)
1729 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1730 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1731 assert(max_lro_size >= 256u);
1732 max_lro_size /= 256u;
1733 if (priv->max_lro_msg_size)
1734 priv->max_lro_msg_size =
1735 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1737 priv->max_lro_msg_size = max_lro_size;
1741 * Create a DPDK Rx queue.
1744 * Pointer to Ethernet device.
1748 * Number of descriptors to configure in queue.
1750 * NUMA socket on which memory must be allocated.
1753 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1755 struct mlx5_rxq_ctrl *
1756 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1757 unsigned int socket, const struct rte_eth_rxconf *conf,
1758 struct rte_mempool *mp)
1760 struct mlx5_priv *priv = dev->data->dev_private;
1761 struct mlx5_rxq_ctrl *tmpl;
1762 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1763 unsigned int mprq_stride_size;
1764 struct mlx5_dev_config *config = &priv->config;
1765 unsigned int strd_headroom_en;
1767 * Always allocate extra slots, even if eventually
1768 * the vector Rx will not be used.
1771 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1772 uint64_t offloads = conf->offloads |
1773 dev->data->dev_conf.rxmode.offloads;
1774 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1775 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1776 unsigned int max_rx_pkt_len = lro_on_queue ?
1777 dev->data->dev_conf.rxmode.max_lro_pkt_size :
1778 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1779 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1780 RTE_PKTMBUF_HEADROOM;
1781 unsigned int max_lro_size = 0;
1782 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1784 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1785 DEV_RX_OFFLOAD_SCATTER)) {
1786 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1787 " configured and no enough mbuf space(%u) to contain "
1788 "the maximum RX packet length(%u) with head-room(%u)",
1789 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1790 RTE_PKTMBUF_HEADROOM);
1794 tmpl = rte_calloc_socket("RXQ", 1,
1796 desc_n * sizeof(struct rte_mbuf *),
1802 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1803 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1804 MLX5_MR_BTREE_CACHE_N, socket)) {
1805 /* rte_errno is already set. */
1808 tmpl->socket = socket;
1809 if (dev->data->dev_conf.intr_conf.rxq)
1812 * LRO packet may consume all the stride memory, hence we cannot
1813 * guaranty head-room near the packet memory in the stride.
1814 * In this case scatter is, for sure, enabled and an empty mbuf may be
1815 * added in the start for the head-room.
1817 if (lro_on_queue && RTE_PKTMBUF_HEADROOM > 0 &&
1818 non_scatter_min_mbuf_size > mb_len) {
1819 strd_headroom_en = 0;
1820 mprq_stride_size = RTE_MIN(max_rx_pkt_len,
1821 1u << config->mprq.max_stride_size_n);
1823 strd_headroom_en = 1;
1824 mprq_stride_size = non_scatter_min_mbuf_size;
1827 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1828 * following conditions are met:
1829 * - MPRQ is enabled.
1830 * - The number of descs is more than the number of strides.
1831 * - max_rx_pkt_len plus overhead is less than the max size of a
1833 * Otherwise, enable Rx scatter if necessary.
1836 desc > (1U << config->mprq.stride_num_n) &&
1837 mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1838 /* TODO: Rx scatter isn't supported yet. */
1839 tmpl->rxq.sges_n = 0;
1840 /* Trim the number of descs needed. */
1841 desc >>= config->mprq.stride_num_n;
1842 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1843 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1844 config->mprq.min_stride_size_n);
1845 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1846 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1847 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1848 config->mprq.max_memcpy_len);
1849 max_lro_size = RTE_MIN(max_rx_pkt_len,
1850 (1u << tmpl->rxq.strd_num_n) *
1851 (1u << tmpl->rxq.strd_sz_n));
1853 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1854 " strd_num_n = %u, strd_sz_n = %u",
1855 dev->data->port_id, idx,
1856 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1857 } else if (max_rx_pkt_len <= first_mb_free_size) {
1858 tmpl->rxq.sges_n = 0;
1859 max_lro_size = max_rx_pkt_len;
1860 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1861 unsigned int size = non_scatter_min_mbuf_size;
1862 unsigned int sges_n;
1864 if (lro_on_queue && first_mb_free_size <
1865 MLX5_MAX_LRO_HEADER_FIX) {
1866 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1867 " to include the max header size(%u) for LRO",
1868 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1869 rte_errno = ENOTSUP;
1873 * Determine the number of SGEs needed for a full packet
1874 * and round it to the next power of two.
1876 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1877 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1879 "port %u too many SGEs (%u) needed to handle"
1880 " requested maximum packet size %u, the maximum"
1881 " supported are %u", dev->data->port_id,
1882 1 << sges_n, max_rx_pkt_len,
1883 1u << MLX5_MAX_LOG_RQ_SEGS);
1884 rte_errno = ENOTSUP;
1887 tmpl->rxq.sges_n = sges_n;
1888 max_lro_size = max_rx_pkt_len;
1890 if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1892 "port %u MPRQ is requested but cannot be enabled"
1893 " (requested: desc = %u, stride_sz = %u,"
1894 " supported: min_stride_num = %u, max_stride_sz = %u).",
1895 dev->data->port_id, desc, mprq_stride_size,
1896 (1 << config->mprq.stride_num_n),
1897 (1 << config->mprq.max_stride_size_n));
1898 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1899 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1900 if (desc % (1 << tmpl->rxq.sges_n)) {
1902 "port %u number of Rx queue descriptors (%u) is not a"
1903 " multiple of SGEs per packet (%u)",
1906 1 << tmpl->rxq.sges_n);
1910 mlx5_max_lro_msg_size_adjust(dev, max_lro_size);
1911 /* Toggle RX checksum offload if hardware supports it. */
1912 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1913 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1914 /* Configure VLAN stripping. */
1915 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1916 /* By default, FCS (CRC) is stripped by hardware. */
1917 tmpl->rxq.crc_present = 0;
1918 tmpl->rxq.lro = lro_on_queue;
1919 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1920 if (config->hw_fcs_strip) {
1922 * RQs used for LRO-enabled TIRs should not be
1923 * configured to scatter the FCS.
1927 "port %u CRC stripping has been "
1928 "disabled but will still be performed "
1929 "by hardware, because LRO is enabled",
1930 dev->data->port_id);
1932 tmpl->rxq.crc_present = 1;
1935 "port %u CRC stripping has been disabled but will"
1936 " still be performed by hardware, make sure MLNX_OFED"
1937 " and firmware are up to date",
1938 dev->data->port_id);
1942 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1943 " incoming frames to hide it",
1945 tmpl->rxq.crc_present ? "disabled" : "enabled",
1946 tmpl->rxq.crc_present << 2);
1948 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1949 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1950 tmpl->rxq.port_id = dev->data->port_id;
1953 tmpl->rxq.elts_n = log2above(desc);
1954 tmpl->rxq.rq_repl_thresh =
1955 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1957 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1959 tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1961 tmpl->rxq.idx = idx;
1962 rte_atomic32_inc(&tmpl->refcnt);
1963 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1971 * Create a DPDK Rx hairpin queue.
1974 * Pointer to Ethernet device.
1978 * Number of descriptors to configure in queue.
1979 * @param hairpin_conf
1980 * The hairpin binding configuration.
1983 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1985 struct mlx5_rxq_ctrl *
1986 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1987 const struct rte_eth_hairpin_conf *hairpin_conf)
1989 struct mlx5_priv *priv = dev->data->dev_private;
1990 struct mlx5_rxq_ctrl *tmpl;
1992 tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
1997 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
1998 tmpl->socket = SOCKET_ID_ANY;
1999 tmpl->rxq.rss_hash = 0;
2000 tmpl->rxq.port_id = dev->data->port_id;
2002 tmpl->rxq.mp = NULL;
2003 tmpl->rxq.elts_n = log2above(desc);
2004 tmpl->rxq.elts = NULL;
2005 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2006 tmpl->hairpin_conf = *hairpin_conf;
2007 tmpl->rxq.idx = idx;
2008 rte_atomic32_inc(&tmpl->refcnt);
2009 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2017 * Pointer to Ethernet device.
2022 * A pointer to the queue if it exists, NULL otherwise.
2024 struct mlx5_rxq_ctrl *
2025 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2027 struct mlx5_priv *priv = dev->data->dev_private;
2028 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2030 if ((*priv->rxqs)[idx]) {
2031 rxq_ctrl = container_of((*priv->rxqs)[idx],
2032 struct mlx5_rxq_ctrl,
2034 mlx5_rxq_obj_get(dev, idx);
2035 rte_atomic32_inc(&rxq_ctrl->refcnt);
2041 * Release a Rx queue.
2044 * Pointer to Ethernet device.
2049 * 1 while a reference on it exists, 0 when freed.
2052 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2054 struct mlx5_priv *priv = dev->data->dev_private;
2055 struct mlx5_rxq_ctrl *rxq_ctrl;
2057 if (!(*priv->rxqs)[idx])
2059 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2060 assert(rxq_ctrl->priv);
2061 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2062 rxq_ctrl->obj = NULL;
2063 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2064 if (rxq_ctrl->dbr_umem_id_valid)
2065 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
2066 rxq_ctrl->dbr_offset));
2067 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2068 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2069 LIST_REMOVE(rxq_ctrl, next);
2071 (*priv->rxqs)[idx] = NULL;
2078 * Verify the Rx Queue list is empty
2081 * Pointer to Ethernet device.
2084 * The number of object not released.
2087 mlx5_rxq_verify(struct rte_eth_dev *dev)
2089 struct mlx5_priv *priv = dev->data->dev_private;
2090 struct mlx5_rxq_ctrl *rxq_ctrl;
2093 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2094 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2095 dev->data->port_id, rxq_ctrl->rxq.idx);
2102 * Get a Rx queue type.
2105 * Pointer to Ethernet device.
2110 * The Rx queue type.
2113 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2115 struct mlx5_priv *priv = dev->data->dev_private;
2116 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2118 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2119 rxq_ctrl = container_of((*priv->rxqs)[idx],
2120 struct mlx5_rxq_ctrl,
2122 return rxq_ctrl->type;
2124 return MLX5_RXQ_TYPE_UNDEFINED;
2128 * Create an indirection table.
2131 * Pointer to Ethernet device.
2133 * Queues entering in the indirection table.
2135 * Number of queues in the array.
2138 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2140 static struct mlx5_ind_table_obj *
2141 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2142 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2144 struct mlx5_priv *priv = dev->data->dev_private;
2145 struct mlx5_ind_table_obj *ind_tbl;
2146 unsigned int i = 0, j = 0, k = 0;
2148 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2149 queues_n * sizeof(uint16_t), 0);
2154 ind_tbl->type = type;
2155 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2156 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2157 log2above(queues_n) :
2158 log2above(priv->config.ind_table_max_size);
2159 struct ibv_wq *wq[1 << wq_n];
2161 for (i = 0; i != queues_n; ++i) {
2162 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2166 wq[i] = rxq->obj->wq;
2167 ind_tbl->queues[i] = queues[i];
2169 ind_tbl->queues_n = queues_n;
2170 /* Finalise indirection table. */
2171 k = i; /* Retain value of i for use in error case. */
2172 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2174 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2176 &(struct ibv_rwq_ind_table_init_attr){
2177 .log_ind_tbl_size = wq_n,
2181 if (!ind_tbl->ind_table) {
2185 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2186 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2187 const unsigned int rqt_n =
2188 1 << (rte_is_power_of_2(queues_n) ?
2189 log2above(queues_n) :
2190 log2above(priv->config.ind_table_max_size));
2192 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2193 rqt_n * sizeof(uint32_t), 0);
2195 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2196 dev->data->port_id);
2200 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2201 rqt_attr->rqt_actual_size = rqt_n;
2202 for (i = 0; i != queues_n; ++i) {
2203 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2207 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2208 ind_tbl->queues[i] = queues[i];
2210 k = i; /* Retain value of i for use in error case. */
2211 for (j = 0; k != rqt_n; ++k, ++j)
2212 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2213 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2216 if (!ind_tbl->rqt) {
2217 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2218 dev->data->port_id);
2222 ind_tbl->queues_n = queues_n;
2224 rte_atomic32_inc(&ind_tbl->refcnt);
2225 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2228 for (j = 0; j < i; j++)
2229 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2231 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2236 * Get an indirection table.
2239 * Pointer to Ethernet device.
2241 * Queues entering in the indirection table.
2243 * Number of queues in the array.
2246 * An indirection table if found.
2248 static struct mlx5_ind_table_obj *
2249 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2252 struct mlx5_priv *priv = dev->data->dev_private;
2253 struct mlx5_ind_table_obj *ind_tbl;
2255 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2256 if ((ind_tbl->queues_n == queues_n) &&
2257 (memcmp(ind_tbl->queues, queues,
2258 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2265 rte_atomic32_inc(&ind_tbl->refcnt);
2266 for (i = 0; i != ind_tbl->queues_n; ++i)
2267 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2273 * Release an indirection table.
2276 * Pointer to Ethernet device.
2278 * Indirection table to release.
2281 * 1 while a reference on it exists, 0 when freed.
2284 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2285 struct mlx5_ind_table_obj *ind_tbl)
2289 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2290 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2291 claim_zero(mlx5_glue->destroy_rwq_ind_table
2292 (ind_tbl->ind_table));
2293 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2294 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2296 for (i = 0; i != ind_tbl->queues_n; ++i)
2297 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2298 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2299 LIST_REMOVE(ind_tbl, next);
2307 * Verify the Rx Queue list is empty
2310 * Pointer to Ethernet device.
2313 * The number of object not released.
2316 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2318 struct mlx5_priv *priv = dev->data->dev_private;
2319 struct mlx5_ind_table_obj *ind_tbl;
2322 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2324 "port %u indirection table obj %p still referenced",
2325 dev->data->port_id, (void *)ind_tbl);
2332 * Create an Rx Hash queue.
2335 * Pointer to Ethernet device.
2337 * RSS key for the Rx hash queue.
2338 * @param rss_key_len
2340 * @param hash_fields
2341 * Verbs protocol hash field to make the RSS on.
2343 * Queues entering in hash queue. In case of empty hash_fields only the
2344 * first queue index will be taken for the indirection table.
2351 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2354 mlx5_hrxq_new(struct rte_eth_dev *dev,
2355 const uint8_t *rss_key, uint32_t rss_key_len,
2356 uint64_t hash_fields,
2357 const uint16_t *queues, uint32_t queues_n,
2358 int tunnel __rte_unused)
2360 struct mlx5_priv *priv = dev->data->dev_private;
2361 struct mlx5_hrxq *hrxq;
2362 struct ibv_qp *qp = NULL;
2363 struct mlx5_ind_table_obj *ind_tbl;
2365 struct mlx5_devx_obj *tir = NULL;
2366 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2367 struct mlx5_rxq_ctrl *rxq_ctrl =
2368 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2370 queues_n = hash_fields ? queues_n : 1;
2371 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2373 enum mlx5_ind_tbl_type type;
2375 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2376 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2377 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2383 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2384 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2385 struct mlx5dv_qp_init_attr qp_init_attr;
2387 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2389 qp_init_attr.comp_mask =
2390 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2391 qp_init_attr.create_flags =
2392 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2394 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2395 if (dev->data->dev_conf.lpbk_mode) {
2397 * Allow packet sent from NIC loop back
2398 * w/o source MAC check.
2400 qp_init_attr.comp_mask |=
2401 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2402 qp_init_attr.create_flags |=
2403 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2406 qp = mlx5_glue->dv_create_qp
2408 &(struct ibv_qp_init_attr_ex){
2409 .qp_type = IBV_QPT_RAW_PACKET,
2411 IBV_QP_INIT_ATTR_PD |
2412 IBV_QP_INIT_ATTR_IND_TABLE |
2413 IBV_QP_INIT_ATTR_RX_HASH,
2414 .rx_hash_conf = (struct ibv_rx_hash_conf){
2416 IBV_RX_HASH_FUNC_TOEPLITZ,
2417 .rx_hash_key_len = rss_key_len,
2419 (void *)(uintptr_t)rss_key,
2420 .rx_hash_fields_mask = hash_fields,
2422 .rwq_ind_tbl = ind_tbl->ind_table,
2427 qp = mlx5_glue->create_qp_ex
2429 &(struct ibv_qp_init_attr_ex){
2430 .qp_type = IBV_QPT_RAW_PACKET,
2432 IBV_QP_INIT_ATTR_PD |
2433 IBV_QP_INIT_ATTR_IND_TABLE |
2434 IBV_QP_INIT_ATTR_RX_HASH,
2435 .rx_hash_conf = (struct ibv_rx_hash_conf){
2437 IBV_RX_HASH_FUNC_TOEPLITZ,
2438 .rx_hash_key_len = rss_key_len,
2440 (void *)(uintptr_t)rss_key,
2441 .rx_hash_fields_mask = hash_fields,
2443 .rwq_ind_tbl = ind_tbl->ind_table,
2451 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2452 struct mlx5_devx_tir_attr tir_attr;
2456 /* Enable TIR LRO only if all the queues were configured for. */
2457 for (i = 0; i < queues_n; ++i) {
2458 if (!(*priv->rxqs)[queues[i]]->lro) {
2463 memset(&tir_attr, 0, sizeof(tir_attr));
2464 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2465 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2466 memcpy(&tir_attr.rx_hash_field_selector_outer, &hash_fields,
2468 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2469 tir_attr.transport_domain = priv->sh->td->id;
2471 tir_attr.transport_domain = priv->sh->tdn;
2472 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2473 tir_attr.indirect_table = ind_tbl->rqt->id;
2474 if (dev->data->dev_conf.lpbk_mode)
2475 tir_attr.self_lb_block =
2476 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2478 tir_attr.lro_timeout_period_usecs =
2479 priv->config.lro.timeout;
2480 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2481 tir_attr.lro_enable_mask =
2482 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2483 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2485 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2487 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2488 dev->data->port_id);
2493 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2496 hrxq->ind_table = ind_tbl;
2497 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2499 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2501 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2502 if (!hrxq->action) {
2507 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2509 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2510 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2512 if (!hrxq->action) {
2518 hrxq->rss_key_len = rss_key_len;
2519 hrxq->hash_fields = hash_fields;
2520 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2521 rte_atomic32_inc(&hrxq->refcnt);
2522 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2525 err = rte_errno; /* Save rte_errno before cleanup. */
2526 mlx5_ind_table_obj_release(dev, ind_tbl);
2528 claim_zero(mlx5_glue->destroy_qp(qp));
2530 claim_zero(mlx5_devx_cmd_destroy(tir));
2531 rte_errno = err; /* Restore rte_errno. */
2536 * Get an Rx Hash queue.
2539 * Pointer to Ethernet device.
2541 * RSS configuration for the Rx hash queue.
2543 * Queues entering in hash queue. In case of empty hash_fields only the
2544 * first queue index will be taken for the indirection table.
2549 * An hash Rx queue on success.
2552 mlx5_hrxq_get(struct rte_eth_dev *dev,
2553 const uint8_t *rss_key, uint32_t rss_key_len,
2554 uint64_t hash_fields,
2555 const uint16_t *queues, uint32_t queues_n)
2557 struct mlx5_priv *priv = dev->data->dev_private;
2558 struct mlx5_hrxq *hrxq;
2560 queues_n = hash_fields ? queues_n : 1;
2561 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2562 struct mlx5_ind_table_obj *ind_tbl;
2564 if (hrxq->rss_key_len != rss_key_len)
2566 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2568 if (hrxq->hash_fields != hash_fields)
2570 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2573 if (ind_tbl != hrxq->ind_table) {
2574 mlx5_ind_table_obj_release(dev, ind_tbl);
2577 rte_atomic32_inc(&hrxq->refcnt);
2584 * Release the hash Rx queue.
2587 * Pointer to Ethernet device.
2589 * Pointer to Hash Rx queue to release.
2592 * 1 while a reference on it exists, 0 when freed.
2595 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2597 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2598 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2599 mlx5_glue->destroy_flow_action(hrxq->action);
2601 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2602 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2603 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2604 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2605 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2606 LIST_REMOVE(hrxq, next);
2610 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2615 * Verify the Rx Queue list is empty
2618 * Pointer to Ethernet device.
2621 * The number of object not released.
2624 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2626 struct mlx5_priv *priv = dev->data->dev_private;
2627 struct mlx5_hrxq *hrxq;
2630 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2632 "port %u hash Rx queue %p still referenced",
2633 dev->data->port_id, (void *)hrxq);
2640 * Create a drop Rx queue Verbs/DevX object.
2643 * Pointer to Ethernet device.
2646 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2648 static struct mlx5_rxq_obj *
2649 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2651 struct mlx5_priv *priv = dev->data->dev_private;
2652 struct ibv_context *ctx = priv->sh->ctx;
2654 struct ibv_wq *wq = NULL;
2655 struct mlx5_rxq_obj *rxq;
2657 if (priv->drop_queue.rxq)
2658 return priv->drop_queue.rxq;
2659 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2661 DEBUG("port %u cannot allocate CQ for drop queue",
2662 dev->data->port_id);
2666 wq = mlx5_glue->create_wq(ctx,
2667 &(struct ibv_wq_init_attr){
2668 .wq_type = IBV_WQT_RQ,
2675 DEBUG("port %u cannot allocate WQ for drop queue",
2676 dev->data->port_id);
2680 rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2682 DEBUG("port %u cannot allocate drop Rx queue memory",
2683 dev->data->port_id);
2689 priv->drop_queue.rxq = rxq;
2693 claim_zero(mlx5_glue->destroy_wq(wq));
2695 claim_zero(mlx5_glue->destroy_cq(cq));
2700 * Release a drop Rx queue Verbs/DevX object.
2703 * Pointer to Ethernet device.
2706 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2709 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2711 struct mlx5_priv *priv = dev->data->dev_private;
2712 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2715 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2717 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2719 priv->drop_queue.rxq = NULL;
2723 * Create a drop indirection table.
2726 * Pointer to Ethernet device.
2729 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2731 static struct mlx5_ind_table_obj *
2732 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2734 struct mlx5_priv *priv = dev->data->dev_private;
2735 struct mlx5_ind_table_obj *ind_tbl;
2736 struct mlx5_rxq_obj *rxq;
2737 struct mlx5_ind_table_obj tmpl;
2739 rxq = mlx5_rxq_obj_drop_new(dev);
2742 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2744 &(struct ibv_rwq_ind_table_init_attr){
2745 .log_ind_tbl_size = 0,
2746 .ind_tbl = &rxq->wq,
2749 if (!tmpl.ind_table) {
2750 DEBUG("port %u cannot allocate indirection table for drop"
2752 dev->data->port_id);
2756 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2761 ind_tbl->ind_table = tmpl.ind_table;
2764 mlx5_rxq_obj_drop_release(dev);
2769 * Release a drop indirection table.
2772 * Pointer to Ethernet device.
2775 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2777 struct mlx5_priv *priv = dev->data->dev_private;
2778 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2780 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2781 mlx5_rxq_obj_drop_release(dev);
2783 priv->drop_queue.hrxq->ind_table = NULL;
2787 * Create a drop Rx Hash queue.
2790 * Pointer to Ethernet device.
2793 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2796 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2798 struct mlx5_priv *priv = dev->data->dev_private;
2799 struct mlx5_ind_table_obj *ind_tbl = NULL;
2800 struct ibv_qp *qp = NULL;
2801 struct mlx5_hrxq *hrxq = NULL;
2803 if (priv->drop_queue.hrxq) {
2804 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2805 return priv->drop_queue.hrxq;
2807 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2810 "port %u cannot allocate memory for drop queue",
2811 dev->data->port_id);
2815 priv->drop_queue.hrxq = hrxq;
2816 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2819 hrxq->ind_table = ind_tbl;
2820 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2821 &(struct ibv_qp_init_attr_ex){
2822 .qp_type = IBV_QPT_RAW_PACKET,
2824 IBV_QP_INIT_ATTR_PD |
2825 IBV_QP_INIT_ATTR_IND_TABLE |
2826 IBV_QP_INIT_ATTR_RX_HASH,
2827 .rx_hash_conf = (struct ibv_rx_hash_conf){
2829 IBV_RX_HASH_FUNC_TOEPLITZ,
2830 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2831 .rx_hash_key = rss_hash_default_key,
2832 .rx_hash_fields_mask = 0,
2834 .rwq_ind_tbl = ind_tbl->ind_table,
2838 DEBUG("port %u cannot allocate QP for drop queue",
2839 dev->data->port_id);
2844 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2845 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2846 if (!hrxq->action) {
2851 rte_atomic32_set(&hrxq->refcnt, 1);
2854 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2855 if (hrxq && hrxq->action)
2856 mlx5_glue->destroy_flow_action(hrxq->action);
2859 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2861 mlx5_ind_table_obj_drop_release(dev);
2863 priv->drop_queue.hrxq = NULL;
2870 * Release a drop hash Rx queue.
2873 * Pointer to Ethernet device.
2876 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2878 struct mlx5_priv *priv = dev->data->dev_private;
2879 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2881 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2882 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2883 mlx5_glue->destroy_flow_action(hrxq->action);
2885 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2886 mlx5_ind_table_obj_drop_release(dev);
2888 priv->drop_queue.hrxq = NULL;