1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 #include <sys/queue.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
29 #include <rte_interrupts.h>
30 #include <rte_debug.h>
34 #include "mlx5_rxtx.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
38 #include "mlx5_glue.h"
39 #include "mlx5_flow.h"
41 /* Default RSS hash key also used for ConnectX-3. */
42 uint8_t rss_hash_default_key[] = {
43 0x2c, 0xc6, 0x81, 0xd1,
44 0x5b, 0xdb, 0xf4, 0xf7,
45 0xfc, 0xa2, 0x83, 0x19,
46 0xdb, 0x1a, 0x3e, 0x94,
47 0x6b, 0x9e, 0x38, 0xd9,
48 0x2c, 0x9c, 0x03, 0xd1,
49 0xad, 0x99, 0x44, 0xa7,
50 0xd9, 0x56, 0x3d, 0x59,
51 0x06, 0x3c, 0x25, 0xf3,
52 0xfc, 0x1f, 0xdc, 0x2a,
55 /* Length of the default RSS hash key. */
56 static_assert(MLX5_RSS_HASH_KEY_LEN ==
57 (unsigned int)sizeof(rss_hash_default_key),
58 "wrong RSS default key size.");
61 * Check whether Multi-Packet RQ can be enabled for the device.
64 * Pointer to Ethernet device.
67 * 1 if supported, negative errno value if not.
70 mlx5_check_mprq_support(struct rte_eth_dev *dev)
72 struct mlx5_priv *priv = dev->data->dev_private;
74 if (priv->config.mprq.enabled &&
75 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
81 * Check whether Multi-Packet RQ is enabled for the Rx queue.
84 * Pointer to receive queue structure.
87 * 0 if disabled, otherwise enabled.
90 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
92 return rxq->strd_num_n > 0;
96 * Check whether Multi-Packet RQ is enabled for the device.
99 * Pointer to Ethernet device.
102 * 0 if disabled, otherwise enabled.
105 mlx5_mprq_enabled(struct rte_eth_dev *dev)
107 struct mlx5_priv *priv = dev->data->dev_private;
112 if (mlx5_check_mprq_support(dev) < 0)
114 /* All the configured queues should be enabled. */
115 for (i = 0; i < priv->rxqs_n; ++i) {
116 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
117 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
118 (rxq, struct mlx5_rxq_ctrl, rxq);
120 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
123 if (mlx5_rxq_mprq_enabled(rxq))
126 /* Multi-Packet RQ can't be partially configured. */
127 assert(n == 0 || n == n_ibv);
132 * Allocate RX queue elements for Multi-Packet RQ.
135 * Pointer to RX queue structure.
138 * 0 on success, a negative errno value otherwise and rte_errno is set.
141 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
143 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
144 unsigned int wqe_n = 1 << rxq->elts_n;
148 /* Iterate on segments. */
149 for (i = 0; i <= wqe_n; ++i) {
150 struct mlx5_mprq_buf *buf;
152 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
153 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
158 (*rxq->mprq_bufs)[i] = buf;
160 rxq->mprq_repl = buf;
163 "port %u Rx queue %u allocated and configured %u segments",
164 rxq->port_id, rxq->idx, wqe_n);
167 err = rte_errno; /* Save rte_errno before cleanup. */
169 for (i = 0; (i != wqe_n); ++i) {
170 if ((*rxq->mprq_bufs)[i] != NULL)
171 rte_mempool_put(rxq->mprq_mp,
172 (*rxq->mprq_bufs)[i]);
173 (*rxq->mprq_bufs)[i] = NULL;
175 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
176 rxq->port_id, rxq->idx);
177 rte_errno = err; /* Restore rte_errno. */
182 * Allocate RX queue elements for Single-Packet RQ.
185 * Pointer to RX queue structure.
188 * 0 on success, errno value on failure.
191 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
193 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
194 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
198 /* Iterate on segments. */
199 for (i = 0; (i != elts_n); ++i) {
200 struct rte_mbuf *buf;
202 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
204 DRV_LOG(ERR, "port %u empty mbuf pool",
205 PORT_ID(rxq_ctrl->priv));
209 /* Headroom is reserved by rte_pktmbuf_alloc(). */
210 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
211 /* Buffer is supposed to be empty. */
212 assert(rte_pktmbuf_data_len(buf) == 0);
213 assert(rte_pktmbuf_pkt_len(buf) == 0);
215 /* Only the first segment keeps headroom. */
217 SET_DATA_OFF(buf, 0);
218 PORT(buf) = rxq_ctrl->rxq.port_id;
219 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
220 PKT_LEN(buf) = DATA_LEN(buf);
222 (*rxq_ctrl->rxq.elts)[i] = buf;
224 /* If Rx vector is activated. */
225 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
226 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
227 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
228 struct rte_pktmbuf_pool_private *priv =
229 (struct rte_pktmbuf_pool_private *)
230 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
233 /* Initialize default rearm_data for vPMD. */
234 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
235 rte_mbuf_refcnt_set(mbuf_init, 1);
236 mbuf_init->nb_segs = 1;
237 mbuf_init->port = rxq->port_id;
238 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
239 mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
241 * prevent compiler reordering:
242 * rearm_data covers previous fields.
244 rte_compiler_barrier();
245 rxq->mbuf_initializer =
246 *(rte_xmm_t *)&mbuf_init->rearm_data;
247 /* Padding with a fake mbuf for vectorized Rx. */
248 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
249 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
252 "port %u Rx queue %u allocated and configured %u segments"
254 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
255 elts_n / (1 << rxq_ctrl->rxq.sges_n));
258 err = rte_errno; /* Save rte_errno before cleanup. */
260 for (i = 0; (i != elts_n); ++i) {
261 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
262 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
263 (*rxq_ctrl->rxq.elts)[i] = NULL;
265 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
266 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
267 rte_errno = err; /* Restore rte_errno. */
272 * Allocate RX queue elements.
275 * Pointer to RX queue structure.
278 * 0 on success, errno value on failure.
281 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
283 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
284 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
288 * Free RX queue elements for Multi-Packet RQ.
291 * Pointer to RX queue structure.
294 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
296 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
299 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
300 rxq->port_id, rxq->idx);
301 if (rxq->mprq_bufs == NULL)
303 assert(mlx5_rxq_check_vec_support(rxq) < 0);
304 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
305 if ((*rxq->mprq_bufs)[i] != NULL)
306 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
307 (*rxq->mprq_bufs)[i] = NULL;
309 if (rxq->mprq_repl != NULL) {
310 mlx5_mprq_buf_free(rxq->mprq_repl);
311 rxq->mprq_repl = NULL;
316 * Free RX queue elements for Single-Packet RQ.
319 * Pointer to RX queue structure.
322 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
324 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
325 const uint16_t q_n = (1 << rxq->elts_n);
326 const uint16_t q_mask = q_n - 1;
327 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
330 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
331 PORT_ID(rxq_ctrl->priv), rxq->idx);
332 if (rxq->elts == NULL)
335 * Some mbuf in the Ring belongs to the application. They cannot be
338 if (mlx5_rxq_check_vec_support(rxq) > 0) {
339 for (i = 0; i < used; ++i)
340 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
341 rxq->rq_pi = rxq->rq_ci;
343 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
344 if ((*rxq->elts)[i] != NULL)
345 rte_pktmbuf_free_seg((*rxq->elts)[i]);
346 (*rxq->elts)[i] = NULL;
351 * Free RX queue elements.
354 * Pointer to RX queue structure.
357 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
359 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
360 rxq_free_elts_mprq(rxq_ctrl);
362 rxq_free_elts_sprq(rxq_ctrl);
366 * Returns the per-queue supported offloads.
369 * Pointer to Ethernet device.
372 * Supported Rx offloads.
375 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
377 struct mlx5_priv *priv = dev->data->dev_private;
378 struct mlx5_dev_config *config = &priv->config;
379 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
380 DEV_RX_OFFLOAD_TIMESTAMP |
381 DEV_RX_OFFLOAD_JUMBO_FRAME |
382 DEV_RX_OFFLOAD_RSS_HASH);
384 if (config->hw_fcs_strip)
385 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
388 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
389 DEV_RX_OFFLOAD_UDP_CKSUM |
390 DEV_RX_OFFLOAD_TCP_CKSUM);
391 if (config->hw_vlan_strip)
392 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
393 if (MLX5_LRO_SUPPORTED(dev))
394 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
400 * Returns the per-port supported offloads.
403 * Supported Rx offloads.
406 mlx5_get_rx_port_offloads(void)
408 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
414 * Verify if the queue can be released.
417 * Pointer to Ethernet device.
422 * 1 if the queue can be released
423 * 0 if the queue can not be released, there are references to it.
424 * Negative errno and rte_errno is set if queue doesn't exist.
427 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
429 struct mlx5_priv *priv = dev->data->dev_private;
430 struct mlx5_rxq_ctrl *rxq_ctrl;
432 if (!(*priv->rxqs)[idx]) {
436 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
437 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
441 * Rx queue presetup checks.
444 * Pointer to Ethernet device structure.
448 * Number of descriptors to configure in queue.
451 * 0 on success, a negative errno value otherwise and rte_errno is set.
454 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
456 struct mlx5_priv *priv = dev->data->dev_private;
458 if (!rte_is_power_of_2(desc)) {
459 desc = 1 << log2above(desc);
461 "port %u increased number of descriptors in Rx queue %u"
462 " to the next power of two (%d)",
463 dev->data->port_id, idx, desc);
465 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
466 dev->data->port_id, idx, desc);
467 if (idx >= priv->rxqs_n) {
468 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
469 dev->data->port_id, idx, priv->rxqs_n);
470 rte_errno = EOVERFLOW;
473 if (!mlx5_rxq_releasable(dev, idx)) {
474 DRV_LOG(ERR, "port %u unable to release queue index %u",
475 dev->data->port_id, idx);
479 mlx5_rxq_release(dev, idx);
486 * Pointer to Ethernet device structure.
490 * Number of descriptors to configure in queue.
492 * NUMA socket on which memory must be allocated.
494 * Thresholds parameters.
496 * Memory pool for buffer allocations.
499 * 0 on success, a negative errno value otherwise and rte_errno is set.
502 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
503 unsigned int socket, const struct rte_eth_rxconf *conf,
504 struct rte_mempool *mp)
506 struct mlx5_priv *priv = dev->data->dev_private;
507 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
508 struct mlx5_rxq_ctrl *rxq_ctrl =
509 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
512 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
515 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
517 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
518 dev->data->port_id, idx);
522 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
523 dev->data->port_id, idx);
524 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
531 * Pointer to Ethernet device structure.
535 * Number of descriptors to configure in queue.
536 * @param hairpin_conf
537 * Hairpin configuration parameters.
540 * 0 on success, a negative errno value otherwise and rte_errno is set.
543 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
545 const struct rte_eth_hairpin_conf *hairpin_conf)
547 struct mlx5_priv *priv = dev->data->dev_private;
548 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
549 struct mlx5_rxq_ctrl *rxq_ctrl =
550 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
553 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
556 if (hairpin_conf->peer_count != 1 ||
557 hairpin_conf->peers[0].port != dev->data->port_id ||
558 hairpin_conf->peers[0].queue >= priv->txqs_n) {
559 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
560 " invalid hairpind configuration", dev->data->port_id,
565 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
567 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
568 dev->data->port_id, idx);
572 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
573 dev->data->port_id, idx);
574 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
579 * DPDK callback to release a RX queue.
582 * Generic RX queue pointer.
585 mlx5_rx_queue_release(void *dpdk_rxq)
587 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
588 struct mlx5_rxq_ctrl *rxq_ctrl;
589 struct mlx5_priv *priv;
593 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
594 priv = rxq_ctrl->priv;
595 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
596 rte_panic("port %u Rx queue %u is still used by a flow and"
597 " cannot be removed\n",
598 PORT_ID(priv), rxq->idx);
599 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
603 * Get an Rx queue Verbs/DevX object.
606 * Pointer to Ethernet device.
608 * Queue index in DPDK Rx queue array
611 * The Verbs/DevX object if it exists.
613 static struct mlx5_rxq_obj *
614 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
616 struct mlx5_priv *priv = dev->data->dev_private;
617 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
618 struct mlx5_rxq_ctrl *rxq_ctrl;
620 if (idx >= priv->rxqs_n)
624 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
626 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
627 return rxq_ctrl->obj;
631 * Release the resources allocated for an RQ DevX object.
634 * DevX Rx queue object.
637 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
639 if (rxq_ctrl->rxq.wqes) {
640 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
641 rxq_ctrl->rxq.wqes = NULL;
643 if (rxq_ctrl->wq_umem) {
644 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
645 rxq_ctrl->wq_umem = NULL;
650 * Release an Rx hairpin related resources.
653 * Hairpin Rx queue object.
656 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
658 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
661 rq_attr.state = MLX5_RQC_STATE_RST;
662 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
663 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
664 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
668 * Release an Rx verbs/DevX queue object.
671 * Verbs/DevX Rx queue object.
674 * 1 while a reference on it exists, 0 when freed.
677 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
680 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
681 switch (rxq_obj->type) {
682 case MLX5_RXQ_OBJ_TYPE_IBV:
685 rxq_free_elts(rxq_obj->rxq_ctrl);
686 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
687 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
689 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
692 rxq_free_elts(rxq_obj->rxq_ctrl);
693 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
694 rxq_release_rq_resources(rxq_obj->rxq_ctrl);
695 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
697 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
699 rxq_obj_hairpin_release(rxq_obj);
702 if (rxq_obj->channel)
703 claim_zero(mlx5_glue->destroy_comp_channel
705 LIST_REMOVE(rxq_obj, next);
713 * Allocate queue vector and fill epoll fd list for Rx interrupts.
716 * Pointer to Ethernet device.
719 * 0 on success, a negative errno value otherwise and rte_errno is set.
722 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
724 struct mlx5_priv *priv = dev->data->dev_private;
726 unsigned int rxqs_n = priv->rxqs_n;
727 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
728 unsigned int count = 0;
729 struct rte_intr_handle *intr_handle = dev->intr_handle;
731 if (!dev->data->dev_conf.intr_conf.rxq)
733 mlx5_rx_intr_vec_disable(dev);
734 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
735 if (intr_handle->intr_vec == NULL) {
737 "port %u failed to allocate memory for interrupt"
738 " vector, Rx interrupts will not be supported",
743 intr_handle->type = RTE_INTR_HANDLE_EXT;
744 for (i = 0; i != n; ++i) {
745 /* This rxq obj must not be released in this function. */
746 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
751 /* Skip queues that cannot request interrupts. */
752 if (!rxq_obj || !rxq_obj->channel) {
753 /* Use invalid intr_vec[] index to disable entry. */
754 intr_handle->intr_vec[i] =
755 RTE_INTR_VEC_RXTX_OFFSET +
756 RTE_MAX_RXTX_INTR_VEC_ID;
759 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
761 "port %u too many Rx queues for interrupt"
762 " vector size (%d), Rx interrupts cannot be"
764 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
765 mlx5_rx_intr_vec_disable(dev);
769 fd = rxq_obj->channel->fd;
770 flags = fcntl(fd, F_GETFL);
771 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
775 "port %u failed to make Rx interrupt file"
776 " descriptor %d non-blocking for queue index"
778 dev->data->port_id, fd, i);
779 mlx5_rx_intr_vec_disable(dev);
782 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
783 intr_handle->efds[count] = fd;
787 mlx5_rx_intr_vec_disable(dev);
789 intr_handle->nb_efd = count;
794 * Clean up Rx interrupts handler.
797 * Pointer to Ethernet device.
800 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
802 struct mlx5_priv *priv = dev->data->dev_private;
803 struct rte_intr_handle *intr_handle = dev->intr_handle;
805 unsigned int rxqs_n = priv->rxqs_n;
806 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
808 if (!dev->data->dev_conf.intr_conf.rxq)
810 if (!intr_handle->intr_vec)
812 for (i = 0; i != n; ++i) {
813 struct mlx5_rxq_ctrl *rxq_ctrl;
814 struct mlx5_rxq_data *rxq_data;
816 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
817 RTE_MAX_RXTX_INTR_VEC_ID)
820 * Need to access directly the queue to release the reference
821 * kept in mlx5_rx_intr_vec_enable().
823 rxq_data = (*priv->rxqs)[i];
824 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
826 mlx5_rxq_obj_release(rxq_ctrl->obj);
829 rte_intr_free_epoll_fd(intr_handle);
830 if (intr_handle->intr_vec)
831 free(intr_handle->intr_vec);
832 intr_handle->nb_efd = 0;
833 intr_handle->intr_vec = NULL;
837 * MLX5 CQ notification .
840 * Pointer to receive queue structure.
842 * Sequence number per receive queue .
845 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
848 uint32_t doorbell_hi;
850 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
852 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
853 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
854 doorbell = (uint64_t)doorbell_hi << 32;
855 doorbell |= rxq->cqn;
856 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
857 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
858 cq_db_reg, rxq->uar_lock_cq);
862 * DPDK callback for Rx queue interrupt enable.
865 * Pointer to Ethernet device structure.
870 * 0 on success, a negative errno value otherwise and rte_errno is set.
873 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
875 struct mlx5_priv *priv = dev->data->dev_private;
876 struct mlx5_rxq_data *rxq_data;
877 struct mlx5_rxq_ctrl *rxq_ctrl;
879 rxq_data = (*priv->rxqs)[rx_queue_id];
884 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
886 struct mlx5_rxq_obj *rxq_obj;
888 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
893 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
894 mlx5_rxq_obj_release(rxq_obj);
900 * DPDK callback for Rx queue interrupt disable.
903 * Pointer to Ethernet device structure.
908 * 0 on success, a negative errno value otherwise and rte_errno is set.
911 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
913 struct mlx5_priv *priv = dev->data->dev_private;
914 struct mlx5_rxq_data *rxq_data;
915 struct mlx5_rxq_ctrl *rxq_ctrl;
916 struct mlx5_rxq_obj *rxq_obj = NULL;
917 struct ibv_cq *ev_cq;
921 rxq_data = (*priv->rxqs)[rx_queue_id];
926 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
929 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
934 ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
935 if (ret || ev_cq != rxq_obj->cq) {
939 rxq_data->cq_arm_sn++;
940 mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
941 mlx5_rxq_obj_release(rxq_obj);
944 ret = rte_errno; /* Save rte_errno before cleanup. */
946 mlx5_rxq_obj_release(rxq_obj);
947 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
948 dev->data->port_id, rx_queue_id);
949 rte_errno = ret; /* Restore rte_errno. */
954 * Create a CQ Verbs object.
957 * Pointer to Ethernet device.
959 * Pointer to device private data.
961 * Pointer to Rx queue data.
963 * Number of CQEs in CQ.
965 * Pointer to Rx queue object data.
968 * The Verbs object initialised, NULL otherwise and rte_errno is set.
970 static struct ibv_cq *
971 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
972 struct mlx5_rxq_data *rxq_data,
973 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
976 struct ibv_cq_init_attr_ex ibv;
977 struct mlx5dv_cq_init_attr mlx5;
980 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
982 .channel = rxq_obj->channel,
985 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
988 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
990 cq_attr.mlx5.comp_mask |=
991 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
992 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
993 cq_attr.mlx5.cqe_comp_res_format =
994 mlx5_rxq_mprq_enabled(rxq_data) ?
995 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
996 MLX5DV_CQE_RES_FORMAT_HASH;
998 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1001 * For vectorized Rx, it must not be doubled in order to
1002 * make cq_ci and rq_ci aligned.
1004 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1005 cq_attr.ibv.cqe *= 2;
1006 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1008 "port %u Rx CQE compression is disabled for HW"
1010 dev->data->port_id);
1011 } else if (priv->config.cqe_comp && rxq_data->lro) {
1013 "port %u Rx CQE compression is disabled for LRO",
1014 dev->data->port_id);
1016 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1017 if (priv->config.cqe_pad) {
1018 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1019 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1022 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1028 * Create a WQ Verbs object.
1031 * Pointer to Ethernet device.
1033 * Pointer to device private data.
1035 * Pointer to Rx queue data.
1037 * Queue index in DPDK Rx queue array
1039 * Number of WQEs in WQ.
1041 * Pointer to Rx queue object data.
1044 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1046 static struct ibv_wq *
1047 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1048 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1049 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1052 struct ibv_wq_init_attr ibv;
1053 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1054 struct mlx5dv_wq_init_attr mlx5;
1058 wq_attr.ibv = (struct ibv_wq_init_attr){
1059 .wq_context = NULL, /* Could be useful in the future. */
1060 .wq_type = IBV_WQT_RQ,
1061 /* Max number of outstanding WRs. */
1062 .max_wr = wqe_n >> rxq_data->sges_n,
1063 /* Max number of scatter/gather elements in a WR. */
1064 .max_sge = 1 << rxq_data->sges_n,
1067 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1068 .create_flags = (rxq_data->vlan_strip ?
1069 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1071 /* By default, FCS (CRC) is stripped by hardware. */
1072 if (rxq_data->crc_present) {
1073 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1074 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1076 if (priv->config.hw_padding) {
1077 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1078 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1079 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1080 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1081 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1082 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1085 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1086 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1089 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1090 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1091 &wq_attr.mlx5.striding_rq_attrs;
1093 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1094 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1095 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1096 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1097 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1100 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1103 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1107 * Make sure number of WRs*SGEs match expectations since a queue
1108 * cannot allocate more than "desc" buffers.
1110 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1111 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1113 "port %u Rx queue %u requested %u*%u but got"
1115 dev->data->port_id, idx,
1116 wqe_n >> rxq_data->sges_n,
1117 (1 << rxq_data->sges_n),
1118 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1119 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1128 * Fill common fields of create RQ attributes structure.
1131 * Pointer to Rx queue data.
1133 * CQ number to use with this RQ.
1135 * RQ attributes structure to fill..
1138 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1139 struct mlx5_devx_create_rq_attr *rq_attr)
1141 rq_attr->state = MLX5_RQC_STATE_RST;
1142 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1144 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1148 * Fill common fields of DevX WQ attributes structure.
1151 * Pointer to device private data.
1153 * Pointer to Rx queue control structure.
1155 * WQ attributes structure to fill..
1158 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1159 struct mlx5_devx_wq_attr *wq_attr)
1161 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1162 MLX5_WQ_END_PAD_MODE_ALIGN :
1163 MLX5_WQ_END_PAD_MODE_NONE;
1164 wq_attr->pd = priv->sh->pdn;
1165 wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1166 wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1167 wq_attr->dbr_umem_valid = 1;
1168 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1169 wq_attr->wq_umem_valid = 1;
1173 * Create a RQ object using DevX.
1176 * Pointer to Ethernet device.
1178 * Queue index in DPDK Rx queue array
1180 * CQ number to use with this RQ.
1183 * The DevX object initialised, NULL otherwise and rte_errno is set.
1185 static struct mlx5_devx_obj *
1186 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1190 struct mlx5_rxq_ctrl *rxq_ctrl =
1191 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1192 struct mlx5_devx_create_rq_attr rq_attr;
1193 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1194 uint32_t wq_size = 0;
1195 uint32_t wqe_size = 0;
1196 uint32_t log_wqe_size = 0;
1198 struct mlx5_devx_obj *rq;
1200 memset(&rq_attr, 0, sizeof(rq_attr));
1201 /* Fill RQ attributes. */
1202 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1203 rq_attr.flush_in_error_en = 1;
1204 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1205 /* Fill WQ attributes for this RQ. */
1206 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1207 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1209 * Number of strides in each WQE:
1210 * 512*2^single_wqe_log_num_of_strides.
1212 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1213 rxq_data->strd_num_n -
1214 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1215 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1216 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1217 rxq_data->strd_sz_n -
1218 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1219 wqe_size = sizeof(struct mlx5_wqe_mprq);
1221 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1222 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1224 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1225 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1226 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1227 /* Calculate and allocate WQ memory space. */
1228 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1229 wq_size = wqe_n * wqe_size;
1230 buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1234 rxq_data->wqes = buf;
1235 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1237 if (!rxq_ctrl->wq_umem) {
1241 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1242 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1244 rxq_release_rq_resources(rxq_ctrl);
1249 * Create the Rx hairpin queue object.
1252 * Pointer to Ethernet device.
1254 * Queue index in DPDK Rx queue array
1257 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1259 static struct mlx5_rxq_obj *
1260 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1262 struct mlx5_priv *priv = dev->data->dev_private;
1263 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1264 struct mlx5_rxq_ctrl *rxq_ctrl =
1265 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1266 struct mlx5_devx_create_rq_attr attr = { 0 };
1267 struct mlx5_rxq_obj *tmpl = NULL;
1271 assert(!rxq_ctrl->obj);
1272 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1276 "port %u Rx queue %u cannot allocate verbs resources",
1277 dev->data->port_id, rxq_data->idx);
1281 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1282 tmpl->rxq_ctrl = rxq_ctrl;
1284 /* Workaround for hairpin startup */
1285 attr.wq_attr.log_hairpin_num_packets = log2above(32);
1286 /* Workaround for packets larger than 1KB */
1287 attr.wq_attr.log_hairpin_data_sz =
1288 priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1289 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1293 "port %u Rx hairpin queue %u can't create rq object",
1294 dev->data->port_id, idx);
1298 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1299 idx, (void *)&tmpl);
1300 rte_atomic32_inc(&tmpl->refcnt);
1301 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1302 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1305 ret = rte_errno; /* Save rte_errno before cleanup. */
1307 mlx5_devx_cmd_destroy(tmpl->rq);
1308 rte_errno = ret; /* Restore rte_errno. */
1313 * Create the Rx queue Verbs/DevX object.
1316 * Pointer to Ethernet device.
1318 * Queue index in DPDK Rx queue array
1320 * Type of Rx queue object to create.
1323 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1325 struct mlx5_rxq_obj *
1326 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1327 enum mlx5_rxq_obj_type type)
1329 struct mlx5_priv *priv = dev->data->dev_private;
1330 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1331 struct mlx5_rxq_ctrl *rxq_ctrl =
1332 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1333 struct ibv_wq_attr mod;
1335 unsigned int wqe_n = 1 << rxq_data->elts_n;
1336 struct mlx5_rxq_obj *tmpl = NULL;
1337 struct mlx5dv_cq cq_info;
1338 struct mlx5dv_rwq rwq;
1340 struct mlx5dv_obj obj;
1343 assert(!rxq_ctrl->obj);
1344 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1345 return mlx5_rxq_obj_hairpin_new(dev, idx);
1346 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1347 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1348 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1352 "port %u Rx queue %u cannot allocate verbs resources",
1353 dev->data->port_id, rxq_data->idx);
1358 tmpl->rxq_ctrl = rxq_ctrl;
1359 if (rxq_ctrl->irq) {
1360 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1361 if (!tmpl->channel) {
1362 DRV_LOG(ERR, "port %u: comp channel creation failure",
1363 dev->data->port_id);
1368 if (mlx5_rxq_mprq_enabled(rxq_data))
1369 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1372 tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1374 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1375 dev->data->port_id, idx);
1379 obj.cq.in = tmpl->cq;
1380 obj.cq.out = &cq_info;
1381 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1386 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1388 "port %u wrong MLX5_CQE_SIZE environment variable"
1389 " value: it should be set to %u",
1390 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1394 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1395 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1396 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1397 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1398 /* Allocate door-bell for types created with DevX. */
1399 if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1400 struct mlx5_devx_dbr_page *dbr_page;
1403 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1406 rxq_ctrl->dbr_offset = dbr_offset;
1407 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1408 rxq_ctrl->dbr_umem_id_valid = 1;
1409 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1410 (uintptr_t)rxq_ctrl->dbr_offset);
1412 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1413 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1416 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1417 dev->data->port_id, idx);
1421 /* Change queue state to ready. */
1422 mod = (struct ibv_wq_attr){
1423 .attr_mask = IBV_WQ_ATTR_STATE,
1424 .wq_state = IBV_WQS_RDY,
1426 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1429 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1430 " failed", dev->data->port_id, idx);
1434 obj.rwq.in = tmpl->wq;
1436 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1441 rxq_data->wqes = rwq.buf;
1442 rxq_data->rq_db = rwq.dbrec;
1443 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1444 struct mlx5_devx_modify_rq_attr rq_attr;
1446 memset(&rq_attr, 0, sizeof(rq_attr));
1447 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1449 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1450 dev->data->port_id, idx);
1454 /* Change queue state to ready. */
1455 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1456 rq_attr.state = MLX5_RQC_STATE_RDY;
1457 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1461 /* Fill the rings. */
1462 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1463 rxq_data->cq_db = cq_info.dbrec;
1464 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1465 rxq_data->cq_uar = cq_info.cq_uar;
1466 rxq_data->cqn = cq_info.cqn;
1467 rxq_data->cq_arm_sn = 0;
1468 mlx5_rxq_initialize(rxq_data);
1469 rxq_data->cq_ci = 0;
1470 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1471 idx, (void *)&tmpl);
1472 rte_atomic32_inc(&tmpl->refcnt);
1473 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1474 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1478 ret = rte_errno; /* Save rte_errno before cleanup. */
1479 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1480 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1481 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1482 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1484 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1486 claim_zero(mlx5_glue->destroy_comp_channel
1489 rte_errno = ret; /* Restore rte_errno. */
1491 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1492 rxq_release_rq_resources(rxq_ctrl);
1493 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1498 * Verify the Rx queue objects list is empty
1501 * Pointer to Ethernet device.
1504 * The number of objects not released.
1507 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1509 struct mlx5_priv *priv = dev->data->dev_private;
1511 struct mlx5_rxq_obj *rxq_obj;
1513 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1514 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1515 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1522 * Callback function to initialize mbufs for Multi-Packet RQ.
1525 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1526 void *_m, unsigned int i __rte_unused)
1528 struct mlx5_mprq_buf *buf = _m;
1529 struct rte_mbuf_ext_shared_info *shinfo;
1530 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1533 memset(_m, 0, sizeof(*buf));
1535 rte_atomic16_set(&buf->refcnt, 1);
1536 for (j = 0; j != strd_n; ++j) {
1537 shinfo = &buf->shinfos[j];
1538 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1539 shinfo->fcb_opaque = buf;
1544 * Free mempool of Multi-Packet RQ.
1547 * Pointer to Ethernet device.
1550 * 0 on success, negative errno value on failure.
1553 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1555 struct mlx5_priv *priv = dev->data->dev_private;
1556 struct rte_mempool *mp = priv->mprq_mp;
1561 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1562 dev->data->port_id, mp->name);
1564 * If a buffer in the pool has been externally attached to a mbuf and it
1565 * is still in use by application, destroying the Rx queue can spoil
1566 * the packet. It is unlikely to happen but if application dynamically
1567 * creates and destroys with holding Rx packets, this can happen.
1569 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1570 * RQ isn't provided by application but managed by PMD.
1572 if (!rte_mempool_full(mp)) {
1574 "port %u mempool for Multi-Packet RQ is still in use",
1575 dev->data->port_id);
1579 rte_mempool_free(mp);
1580 /* Unset mempool for each Rx queue. */
1581 for (i = 0; i != priv->rxqs_n; ++i) {
1582 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1586 rxq->mprq_mp = NULL;
1588 priv->mprq_mp = NULL;
1593 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1594 * mempool. If already allocated, reuse it if there're enough elements.
1595 * Otherwise, resize it.
1598 * Pointer to Ethernet device.
1601 * 0 on success, negative errno value on failure.
1604 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1606 struct mlx5_priv *priv = dev->data->dev_private;
1607 struct rte_mempool *mp = priv->mprq_mp;
1608 char name[RTE_MEMPOOL_NAMESIZE];
1609 unsigned int desc = 0;
1610 unsigned int buf_len;
1611 unsigned int obj_num;
1612 unsigned int obj_size;
1613 unsigned int strd_num_n = 0;
1614 unsigned int strd_sz_n = 0;
1616 unsigned int n_ibv = 0;
1618 if (!mlx5_mprq_enabled(dev))
1620 /* Count the total number of descriptors configured. */
1621 for (i = 0; i != priv->rxqs_n; ++i) {
1622 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1623 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1624 (rxq, struct mlx5_rxq_ctrl, rxq);
1626 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1629 desc += 1 << rxq->elts_n;
1630 /* Get the max number of strides. */
1631 if (strd_num_n < rxq->strd_num_n)
1632 strd_num_n = rxq->strd_num_n;
1633 /* Get the max size of a stride. */
1634 if (strd_sz_n < rxq->strd_sz_n)
1635 strd_sz_n = rxq->strd_sz_n;
1637 assert(strd_num_n && strd_sz_n);
1638 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1639 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1640 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1642 * Received packets can be either memcpy'd or externally referenced. In
1643 * case that the packet is attached to an mbuf as an external buffer, as
1644 * it isn't possible to predict how the buffers will be queued by
1645 * application, there's no option to exactly pre-allocate needed buffers
1646 * in advance but to speculatively prepares enough buffers.
1648 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1649 * received packets to buffers provided by application (rxq->mp) until
1650 * this Mempool gets available again.
1653 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1655 * rte_mempool_create_empty() has sanity check to refuse large cache
1656 * size compared to the number of elements.
1657 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1658 * constant number 2 instead.
1660 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1661 /* Check a mempool is already allocated and if it can be resued. */
1662 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1663 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1664 dev->data->port_id, mp->name);
1667 } else if (mp != NULL) {
1668 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1669 dev->data->port_id, mp->name);
1671 * If failed to free, which means it may be still in use, no way
1672 * but to keep using the existing one. On buffer underrun,
1673 * packets will be memcpy'd instead of external buffer
1676 if (mlx5_mprq_free_mp(dev)) {
1677 if (mp->elt_size >= obj_size)
1683 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1684 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1685 0, NULL, NULL, mlx5_mprq_buf_init,
1686 (void *)(uintptr_t)(1 << strd_num_n),
1687 dev->device->numa_node, 0);
1690 "port %u failed to allocate a mempool for"
1691 " Multi-Packet RQ, count=%u, size=%u",
1692 dev->data->port_id, obj_num, obj_size);
1698 /* Set mempool for each Rx queue. */
1699 for (i = 0; i != priv->rxqs_n; ++i) {
1700 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1701 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1702 (rxq, struct mlx5_rxq_ctrl, rxq);
1704 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1708 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1709 dev->data->port_id);
1713 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1714 sizeof(struct rte_vlan_hdr) * 2 + \
1715 sizeof(struct rte_ipv6_hdr)))
1716 #define MAX_TCP_OPTION_SIZE 40u
1717 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1718 sizeof(struct rte_tcp_hdr) + \
1719 MAX_TCP_OPTION_SIZE))
1722 * Adjust the maximum LRO massage size.
1725 * Pointer to Ethernet device.
1728 * @param max_lro_size
1729 * The maximum size for LRO packet.
1732 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1733 uint32_t max_lro_size)
1735 struct mlx5_priv *priv = dev->data->dev_private;
1737 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1738 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1739 MLX5_MAX_TCP_HDR_OFFSET)
1740 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1741 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1742 assert(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1743 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1744 if (priv->max_lro_msg_size)
1745 priv->max_lro_msg_size =
1746 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1748 priv->max_lro_msg_size = max_lro_size;
1750 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1751 dev->data->port_id, idx,
1752 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1756 * Create a DPDK Rx queue.
1759 * Pointer to Ethernet device.
1763 * Number of descriptors to configure in queue.
1765 * NUMA socket on which memory must be allocated.
1768 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1770 struct mlx5_rxq_ctrl *
1771 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1772 unsigned int socket, const struct rte_eth_rxconf *conf,
1773 struct rte_mempool *mp)
1775 struct mlx5_priv *priv = dev->data->dev_private;
1776 struct mlx5_rxq_ctrl *tmpl;
1777 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1778 unsigned int mprq_stride_size;
1779 struct mlx5_dev_config *config = &priv->config;
1780 unsigned int strd_headroom_en;
1782 * Always allocate extra slots, even if eventually
1783 * the vector Rx will not be used.
1786 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1787 uint64_t offloads = conf->offloads |
1788 dev->data->dev_conf.rxmode.offloads;
1789 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1790 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1791 unsigned int max_rx_pkt_len = lro_on_queue ?
1792 dev->data->dev_conf.rxmode.max_lro_pkt_size :
1793 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1794 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1795 RTE_PKTMBUF_HEADROOM;
1796 unsigned int max_lro_size = 0;
1797 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1799 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1800 DEV_RX_OFFLOAD_SCATTER)) {
1801 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1802 " configured and no enough mbuf space(%u) to contain "
1803 "the maximum RX packet length(%u) with head-room(%u)",
1804 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1805 RTE_PKTMBUF_HEADROOM);
1809 tmpl = rte_calloc_socket("RXQ", 1,
1811 desc_n * sizeof(struct rte_mbuf *),
1817 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1818 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1819 MLX5_MR_BTREE_CACHE_N, socket)) {
1820 /* rte_errno is already set. */
1823 tmpl->socket = socket;
1824 if (dev->data->dev_conf.intr_conf.rxq)
1827 * LRO packet may consume all the stride memory, hence we cannot
1828 * guaranty head-room near the packet memory in the stride.
1829 * In this case scatter is, for sure, enabled and an empty mbuf may be
1830 * added in the start for the head-room.
1832 if (lro_on_queue && RTE_PKTMBUF_HEADROOM > 0 &&
1833 non_scatter_min_mbuf_size > mb_len) {
1834 strd_headroom_en = 0;
1835 mprq_stride_size = RTE_MIN(max_rx_pkt_len,
1836 1u << config->mprq.max_stride_size_n);
1838 strd_headroom_en = 1;
1839 mprq_stride_size = non_scatter_min_mbuf_size;
1842 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1843 * following conditions are met:
1844 * - MPRQ is enabled.
1845 * - The number of descs is more than the number of strides.
1846 * - max_rx_pkt_len plus overhead is less than the max size of a
1848 * Otherwise, enable Rx scatter if necessary.
1851 desc > (1U << config->mprq.stride_num_n) &&
1852 mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1853 /* TODO: Rx scatter isn't supported yet. */
1854 tmpl->rxq.sges_n = 0;
1855 /* Trim the number of descs needed. */
1856 desc >>= config->mprq.stride_num_n;
1857 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1858 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1859 config->mprq.min_stride_size_n);
1860 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1861 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1862 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1863 config->mprq.max_memcpy_len);
1864 max_lro_size = RTE_MIN(max_rx_pkt_len,
1865 (1u << tmpl->rxq.strd_num_n) *
1866 (1u << tmpl->rxq.strd_sz_n));
1868 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1869 " strd_num_n = %u, strd_sz_n = %u",
1870 dev->data->port_id, idx,
1871 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1872 } else if (max_rx_pkt_len <= first_mb_free_size) {
1873 tmpl->rxq.sges_n = 0;
1874 max_lro_size = max_rx_pkt_len;
1875 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1876 unsigned int size = non_scatter_min_mbuf_size;
1877 unsigned int sges_n;
1879 if (lro_on_queue && first_mb_free_size <
1880 MLX5_MAX_LRO_HEADER_FIX) {
1881 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1882 " to include the max header size(%u) for LRO",
1883 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1884 rte_errno = ENOTSUP;
1888 * Determine the number of SGEs needed for a full packet
1889 * and round it to the next power of two.
1891 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1892 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1894 "port %u too many SGEs (%u) needed to handle"
1895 " requested maximum packet size %u, the maximum"
1896 " supported are %u", dev->data->port_id,
1897 1 << sges_n, max_rx_pkt_len,
1898 1u << MLX5_MAX_LOG_RQ_SEGS);
1899 rte_errno = ENOTSUP;
1902 tmpl->rxq.sges_n = sges_n;
1903 max_lro_size = max_rx_pkt_len;
1905 if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1907 "port %u MPRQ is requested but cannot be enabled"
1908 " (requested: desc = %u, stride_sz = %u,"
1909 " supported: min_stride_num = %u, max_stride_sz = %u).",
1910 dev->data->port_id, desc, mprq_stride_size,
1911 (1 << config->mprq.stride_num_n),
1912 (1 << config->mprq.max_stride_size_n));
1913 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1914 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1915 if (desc % (1 << tmpl->rxq.sges_n)) {
1917 "port %u number of Rx queue descriptors (%u) is not a"
1918 " multiple of SGEs per packet (%u)",
1921 1 << tmpl->rxq.sges_n);
1925 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1926 /* Toggle RX checksum offload if hardware supports it. */
1927 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1928 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1929 /* Configure VLAN stripping. */
1930 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1931 /* By default, FCS (CRC) is stripped by hardware. */
1932 tmpl->rxq.crc_present = 0;
1933 tmpl->rxq.lro = lro_on_queue;
1934 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1935 if (config->hw_fcs_strip) {
1937 * RQs used for LRO-enabled TIRs should not be
1938 * configured to scatter the FCS.
1942 "port %u CRC stripping has been "
1943 "disabled but will still be performed "
1944 "by hardware, because LRO is enabled",
1945 dev->data->port_id);
1947 tmpl->rxq.crc_present = 1;
1950 "port %u CRC stripping has been disabled but will"
1951 " still be performed by hardware, make sure MLNX_OFED"
1952 " and firmware are up to date",
1953 dev->data->port_id);
1957 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1958 " incoming frames to hide it",
1960 tmpl->rxq.crc_present ? "disabled" : "enabled",
1961 tmpl->rxq.crc_present << 2);
1963 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1964 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1965 tmpl->rxq.port_id = dev->data->port_id;
1968 tmpl->rxq.elts_n = log2above(desc);
1969 tmpl->rxq.rq_repl_thresh =
1970 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1972 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1974 tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1976 tmpl->rxq.idx = idx;
1977 rte_atomic32_inc(&tmpl->refcnt);
1978 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1986 * Create a DPDK Rx hairpin queue.
1989 * Pointer to Ethernet device.
1993 * Number of descriptors to configure in queue.
1994 * @param hairpin_conf
1995 * The hairpin binding configuration.
1998 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2000 struct mlx5_rxq_ctrl *
2001 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2002 const struct rte_eth_hairpin_conf *hairpin_conf)
2004 struct mlx5_priv *priv = dev->data->dev_private;
2005 struct mlx5_rxq_ctrl *tmpl;
2007 tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
2012 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2013 tmpl->socket = SOCKET_ID_ANY;
2014 tmpl->rxq.rss_hash = 0;
2015 tmpl->rxq.port_id = dev->data->port_id;
2017 tmpl->rxq.mp = NULL;
2018 tmpl->rxq.elts_n = log2above(desc);
2019 tmpl->rxq.elts = NULL;
2020 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2021 tmpl->hairpin_conf = *hairpin_conf;
2022 tmpl->rxq.idx = idx;
2023 rte_atomic32_inc(&tmpl->refcnt);
2024 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2032 * Pointer to Ethernet device.
2037 * A pointer to the queue if it exists, NULL otherwise.
2039 struct mlx5_rxq_ctrl *
2040 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2042 struct mlx5_priv *priv = dev->data->dev_private;
2043 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2045 if ((*priv->rxqs)[idx]) {
2046 rxq_ctrl = container_of((*priv->rxqs)[idx],
2047 struct mlx5_rxq_ctrl,
2049 mlx5_rxq_obj_get(dev, idx);
2050 rte_atomic32_inc(&rxq_ctrl->refcnt);
2056 * Release a Rx queue.
2059 * Pointer to Ethernet device.
2064 * 1 while a reference on it exists, 0 when freed.
2067 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2069 struct mlx5_priv *priv = dev->data->dev_private;
2070 struct mlx5_rxq_ctrl *rxq_ctrl;
2072 if (!(*priv->rxqs)[idx])
2074 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2075 assert(rxq_ctrl->priv);
2076 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2077 rxq_ctrl->obj = NULL;
2078 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2079 if (rxq_ctrl->dbr_umem_id_valid)
2080 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
2081 rxq_ctrl->dbr_offset));
2082 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2083 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2084 LIST_REMOVE(rxq_ctrl, next);
2086 (*priv->rxqs)[idx] = NULL;
2093 * Verify the Rx Queue list is empty
2096 * Pointer to Ethernet device.
2099 * The number of object not released.
2102 mlx5_rxq_verify(struct rte_eth_dev *dev)
2104 struct mlx5_priv *priv = dev->data->dev_private;
2105 struct mlx5_rxq_ctrl *rxq_ctrl;
2108 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2109 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2110 dev->data->port_id, rxq_ctrl->rxq.idx);
2117 * Get a Rx queue type.
2120 * Pointer to Ethernet device.
2125 * The Rx queue type.
2128 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2130 struct mlx5_priv *priv = dev->data->dev_private;
2131 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2133 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2134 rxq_ctrl = container_of((*priv->rxqs)[idx],
2135 struct mlx5_rxq_ctrl,
2137 return rxq_ctrl->type;
2139 return MLX5_RXQ_TYPE_UNDEFINED;
2143 * Create an indirection table.
2146 * Pointer to Ethernet device.
2148 * Queues entering in the indirection table.
2150 * Number of queues in the array.
2153 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2155 static struct mlx5_ind_table_obj *
2156 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2157 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2159 struct mlx5_priv *priv = dev->data->dev_private;
2160 struct mlx5_ind_table_obj *ind_tbl;
2161 unsigned int i = 0, j = 0, k = 0;
2163 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2164 queues_n * sizeof(uint16_t), 0);
2169 ind_tbl->type = type;
2170 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2171 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2172 log2above(queues_n) :
2173 log2above(priv->config.ind_table_max_size);
2174 struct ibv_wq *wq[1 << wq_n];
2176 for (i = 0; i != queues_n; ++i) {
2177 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2181 wq[i] = rxq->obj->wq;
2182 ind_tbl->queues[i] = queues[i];
2184 ind_tbl->queues_n = queues_n;
2185 /* Finalise indirection table. */
2186 k = i; /* Retain value of i for use in error case. */
2187 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2189 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2191 &(struct ibv_rwq_ind_table_init_attr){
2192 .log_ind_tbl_size = wq_n,
2196 if (!ind_tbl->ind_table) {
2200 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2201 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2202 const unsigned int rqt_n =
2203 1 << (rte_is_power_of_2(queues_n) ?
2204 log2above(queues_n) :
2205 log2above(priv->config.ind_table_max_size));
2207 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2208 rqt_n * sizeof(uint32_t), 0);
2210 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2211 dev->data->port_id);
2215 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2216 rqt_attr->rqt_actual_size = rqt_n;
2217 for (i = 0; i != queues_n; ++i) {
2218 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2222 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2223 ind_tbl->queues[i] = queues[i];
2225 k = i; /* Retain value of i for use in error case. */
2226 for (j = 0; k != rqt_n; ++k, ++j)
2227 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2228 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2231 if (!ind_tbl->rqt) {
2232 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2233 dev->data->port_id);
2237 ind_tbl->queues_n = queues_n;
2239 rte_atomic32_inc(&ind_tbl->refcnt);
2240 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2243 for (j = 0; j < i; j++)
2244 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2246 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2251 * Get an indirection table.
2254 * Pointer to Ethernet device.
2256 * Queues entering in the indirection table.
2258 * Number of queues in the array.
2261 * An indirection table if found.
2263 static struct mlx5_ind_table_obj *
2264 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2267 struct mlx5_priv *priv = dev->data->dev_private;
2268 struct mlx5_ind_table_obj *ind_tbl;
2270 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2271 if ((ind_tbl->queues_n == queues_n) &&
2272 (memcmp(ind_tbl->queues, queues,
2273 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2280 rte_atomic32_inc(&ind_tbl->refcnt);
2281 for (i = 0; i != ind_tbl->queues_n; ++i)
2282 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2288 * Release an indirection table.
2291 * Pointer to Ethernet device.
2293 * Indirection table to release.
2296 * 1 while a reference on it exists, 0 when freed.
2299 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2300 struct mlx5_ind_table_obj *ind_tbl)
2304 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2305 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2306 claim_zero(mlx5_glue->destroy_rwq_ind_table
2307 (ind_tbl->ind_table));
2308 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2309 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2311 for (i = 0; i != ind_tbl->queues_n; ++i)
2312 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2313 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2314 LIST_REMOVE(ind_tbl, next);
2322 * Verify the Rx Queue list is empty
2325 * Pointer to Ethernet device.
2328 * The number of object not released.
2331 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2333 struct mlx5_priv *priv = dev->data->dev_private;
2334 struct mlx5_ind_table_obj *ind_tbl;
2337 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2339 "port %u indirection table obj %p still referenced",
2340 dev->data->port_id, (void *)ind_tbl);
2347 * Create an Rx Hash queue.
2350 * Pointer to Ethernet device.
2352 * RSS key for the Rx hash queue.
2353 * @param rss_key_len
2355 * @param hash_fields
2356 * Verbs protocol hash field to make the RSS on.
2358 * Queues entering in hash queue. In case of empty hash_fields only the
2359 * first queue index will be taken for the indirection table.
2366 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2369 mlx5_hrxq_new(struct rte_eth_dev *dev,
2370 const uint8_t *rss_key, uint32_t rss_key_len,
2371 uint64_t hash_fields,
2372 const uint16_t *queues, uint32_t queues_n,
2373 int tunnel __rte_unused)
2375 struct mlx5_priv *priv = dev->data->dev_private;
2376 struct mlx5_hrxq *hrxq;
2377 struct ibv_qp *qp = NULL;
2378 struct mlx5_ind_table_obj *ind_tbl;
2380 struct mlx5_devx_obj *tir = NULL;
2381 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2382 struct mlx5_rxq_ctrl *rxq_ctrl =
2383 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2385 queues_n = hash_fields ? queues_n : 1;
2386 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2388 enum mlx5_ind_tbl_type type;
2390 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2391 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2392 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2398 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2399 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2400 struct mlx5dv_qp_init_attr qp_init_attr;
2402 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2404 qp_init_attr.comp_mask =
2405 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2406 qp_init_attr.create_flags =
2407 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2409 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2410 if (dev->data->dev_conf.lpbk_mode) {
2412 * Allow packet sent from NIC loop back
2413 * w/o source MAC check.
2415 qp_init_attr.comp_mask |=
2416 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2417 qp_init_attr.create_flags |=
2418 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2421 qp = mlx5_glue->dv_create_qp
2423 &(struct ibv_qp_init_attr_ex){
2424 .qp_type = IBV_QPT_RAW_PACKET,
2426 IBV_QP_INIT_ATTR_PD |
2427 IBV_QP_INIT_ATTR_IND_TABLE |
2428 IBV_QP_INIT_ATTR_RX_HASH,
2429 .rx_hash_conf = (struct ibv_rx_hash_conf){
2431 IBV_RX_HASH_FUNC_TOEPLITZ,
2432 .rx_hash_key_len = rss_key_len,
2434 (void *)(uintptr_t)rss_key,
2435 .rx_hash_fields_mask = hash_fields,
2437 .rwq_ind_tbl = ind_tbl->ind_table,
2442 qp = mlx5_glue->create_qp_ex
2444 &(struct ibv_qp_init_attr_ex){
2445 .qp_type = IBV_QPT_RAW_PACKET,
2447 IBV_QP_INIT_ATTR_PD |
2448 IBV_QP_INIT_ATTR_IND_TABLE |
2449 IBV_QP_INIT_ATTR_RX_HASH,
2450 .rx_hash_conf = (struct ibv_rx_hash_conf){
2452 IBV_RX_HASH_FUNC_TOEPLITZ,
2453 .rx_hash_key_len = rss_key_len,
2455 (void *)(uintptr_t)rss_key,
2456 .rx_hash_fields_mask = hash_fields,
2458 .rwq_ind_tbl = ind_tbl->ind_table,
2466 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2467 struct mlx5_devx_tir_attr tir_attr;
2471 /* Enable TIR LRO only if all the queues were configured for. */
2472 for (i = 0; i < queues_n; ++i) {
2473 if (!(*priv->rxqs)[queues[i]]->lro) {
2478 memset(&tir_attr, 0, sizeof(tir_attr));
2479 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2480 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2481 tir_attr.tunneled_offload_en = !!tunnel;
2482 /* If needed, translate hash_fields bitmap to PRM format. */
2484 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2485 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2486 hash_fields & IBV_RX_HASH_INNER ?
2487 &tir_attr.rx_hash_field_selector_inner :
2488 &tir_attr.rx_hash_field_selector_outer;
2490 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2491 &tir_attr.rx_hash_field_selector_outer;
2494 /* 1 bit: 0: IPv4, 1: IPv6. */
2495 rx_hash_field_select->l3_prot_type =
2496 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2497 /* 1 bit: 0: TCP, 1: UDP. */
2498 rx_hash_field_select->l4_prot_type =
2499 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2500 /* Bitmask which sets which fields to use in RX Hash. */
2501 rx_hash_field_select->selected_fields =
2502 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2503 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2504 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2505 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2506 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2507 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2508 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2509 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2511 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2512 tir_attr.transport_domain = priv->sh->td->id;
2514 tir_attr.transport_domain = priv->sh->tdn;
2515 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2516 tir_attr.indirect_table = ind_tbl->rqt->id;
2517 if (dev->data->dev_conf.lpbk_mode)
2518 tir_attr.self_lb_block =
2519 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2521 tir_attr.lro_timeout_period_usecs =
2522 priv->config.lro.timeout;
2523 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2524 tir_attr.lro_enable_mask =
2525 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2526 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2528 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2530 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2531 dev->data->port_id);
2536 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2539 hrxq->ind_table = ind_tbl;
2540 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2542 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2544 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2545 if (!hrxq->action) {
2550 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2552 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2553 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2555 if (!hrxq->action) {
2561 hrxq->rss_key_len = rss_key_len;
2562 hrxq->hash_fields = hash_fields;
2563 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2564 rte_atomic32_inc(&hrxq->refcnt);
2565 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2568 err = rte_errno; /* Save rte_errno before cleanup. */
2569 mlx5_ind_table_obj_release(dev, ind_tbl);
2571 claim_zero(mlx5_glue->destroy_qp(qp));
2573 claim_zero(mlx5_devx_cmd_destroy(tir));
2574 rte_errno = err; /* Restore rte_errno. */
2579 * Get an Rx Hash queue.
2582 * Pointer to Ethernet device.
2584 * RSS configuration for the Rx hash queue.
2586 * Queues entering in hash queue. In case of empty hash_fields only the
2587 * first queue index will be taken for the indirection table.
2592 * An hash Rx queue on success.
2595 mlx5_hrxq_get(struct rte_eth_dev *dev,
2596 const uint8_t *rss_key, uint32_t rss_key_len,
2597 uint64_t hash_fields,
2598 const uint16_t *queues, uint32_t queues_n)
2600 struct mlx5_priv *priv = dev->data->dev_private;
2601 struct mlx5_hrxq *hrxq;
2603 queues_n = hash_fields ? queues_n : 1;
2604 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2605 struct mlx5_ind_table_obj *ind_tbl;
2607 if (hrxq->rss_key_len != rss_key_len)
2609 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2611 if (hrxq->hash_fields != hash_fields)
2613 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2616 if (ind_tbl != hrxq->ind_table) {
2617 mlx5_ind_table_obj_release(dev, ind_tbl);
2620 rte_atomic32_inc(&hrxq->refcnt);
2627 * Release the hash Rx queue.
2630 * Pointer to Ethernet device.
2632 * Pointer to Hash Rx queue to release.
2635 * 1 while a reference on it exists, 0 when freed.
2638 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2640 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2641 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2642 mlx5_glue->destroy_flow_action(hrxq->action);
2644 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2645 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2646 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2647 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2648 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2649 LIST_REMOVE(hrxq, next);
2653 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2658 * Verify the Rx Queue list is empty
2661 * Pointer to Ethernet device.
2664 * The number of object not released.
2667 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2669 struct mlx5_priv *priv = dev->data->dev_private;
2670 struct mlx5_hrxq *hrxq;
2673 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2675 "port %u hash Rx queue %p still referenced",
2676 dev->data->port_id, (void *)hrxq);
2683 * Create a drop Rx queue Verbs/DevX object.
2686 * Pointer to Ethernet device.
2689 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2691 static struct mlx5_rxq_obj *
2692 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2694 struct mlx5_priv *priv = dev->data->dev_private;
2695 struct ibv_context *ctx = priv->sh->ctx;
2697 struct ibv_wq *wq = NULL;
2698 struct mlx5_rxq_obj *rxq;
2700 if (priv->drop_queue.rxq)
2701 return priv->drop_queue.rxq;
2702 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2704 DEBUG("port %u cannot allocate CQ for drop queue",
2705 dev->data->port_id);
2709 wq = mlx5_glue->create_wq(ctx,
2710 &(struct ibv_wq_init_attr){
2711 .wq_type = IBV_WQT_RQ,
2718 DEBUG("port %u cannot allocate WQ for drop queue",
2719 dev->data->port_id);
2723 rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2725 DEBUG("port %u cannot allocate drop Rx queue memory",
2726 dev->data->port_id);
2732 priv->drop_queue.rxq = rxq;
2736 claim_zero(mlx5_glue->destroy_wq(wq));
2738 claim_zero(mlx5_glue->destroy_cq(cq));
2743 * Release a drop Rx queue Verbs/DevX object.
2746 * Pointer to Ethernet device.
2749 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2752 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2754 struct mlx5_priv *priv = dev->data->dev_private;
2755 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2758 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2760 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2762 priv->drop_queue.rxq = NULL;
2766 * Create a drop indirection table.
2769 * Pointer to Ethernet device.
2772 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2774 static struct mlx5_ind_table_obj *
2775 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2777 struct mlx5_priv *priv = dev->data->dev_private;
2778 struct mlx5_ind_table_obj *ind_tbl;
2779 struct mlx5_rxq_obj *rxq;
2780 struct mlx5_ind_table_obj tmpl;
2782 rxq = mlx5_rxq_obj_drop_new(dev);
2785 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2787 &(struct ibv_rwq_ind_table_init_attr){
2788 .log_ind_tbl_size = 0,
2789 .ind_tbl = &rxq->wq,
2792 if (!tmpl.ind_table) {
2793 DEBUG("port %u cannot allocate indirection table for drop"
2795 dev->data->port_id);
2799 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2804 ind_tbl->ind_table = tmpl.ind_table;
2807 mlx5_rxq_obj_drop_release(dev);
2812 * Release a drop indirection table.
2815 * Pointer to Ethernet device.
2818 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2820 struct mlx5_priv *priv = dev->data->dev_private;
2821 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2823 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2824 mlx5_rxq_obj_drop_release(dev);
2826 priv->drop_queue.hrxq->ind_table = NULL;
2830 * Create a drop Rx Hash queue.
2833 * Pointer to Ethernet device.
2836 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2839 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2841 struct mlx5_priv *priv = dev->data->dev_private;
2842 struct mlx5_ind_table_obj *ind_tbl = NULL;
2843 struct ibv_qp *qp = NULL;
2844 struct mlx5_hrxq *hrxq = NULL;
2846 if (priv->drop_queue.hrxq) {
2847 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2848 return priv->drop_queue.hrxq;
2850 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2853 "port %u cannot allocate memory for drop queue",
2854 dev->data->port_id);
2858 priv->drop_queue.hrxq = hrxq;
2859 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2862 hrxq->ind_table = ind_tbl;
2863 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2864 &(struct ibv_qp_init_attr_ex){
2865 .qp_type = IBV_QPT_RAW_PACKET,
2867 IBV_QP_INIT_ATTR_PD |
2868 IBV_QP_INIT_ATTR_IND_TABLE |
2869 IBV_QP_INIT_ATTR_RX_HASH,
2870 .rx_hash_conf = (struct ibv_rx_hash_conf){
2872 IBV_RX_HASH_FUNC_TOEPLITZ,
2873 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2874 .rx_hash_key = rss_hash_default_key,
2875 .rx_hash_fields_mask = 0,
2877 .rwq_ind_tbl = ind_tbl->ind_table,
2881 DEBUG("port %u cannot allocate QP for drop queue",
2882 dev->data->port_id);
2887 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2888 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2889 if (!hrxq->action) {
2894 rte_atomic32_set(&hrxq->refcnt, 1);
2897 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2898 if (hrxq && hrxq->action)
2899 mlx5_glue->destroy_flow_action(hrxq->action);
2902 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2904 mlx5_ind_table_obj_drop_release(dev);
2906 priv->drop_queue.hrxq = NULL;
2913 * Release a drop hash Rx queue.
2916 * Pointer to Ethernet device.
2919 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2921 struct mlx5_priv *priv = dev->data->dev_private;
2922 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2924 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2925 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2926 mlx5_glue->destroy_flow_action(hrxq->action);
2928 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2929 mlx5_ind_table_obj_drop_release(dev);
2931 priv->drop_queue.hrxq = NULL;