1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
14 #include <rte_malloc.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_common.h>
17 #include <rte_interrupts.h>
18 #include <rte_debug.h>
20 #include <rte_eal_paging.h>
22 #include <mlx5_glue.h>
23 #include <mlx5_devx_cmds.h>
24 #include <mlx5_malloc.h>
26 #include "mlx5_defs.h"
28 #include "mlx5_common_os.h"
29 #include "mlx5_rxtx.h"
30 #include "mlx5_utils.h"
31 #include "mlx5_autoconf.h"
32 #include "mlx5_flow.h"
35 /* Default RSS hash key also used for ConnectX-3. */
36 uint8_t rss_hash_default_key[] = {
37 0x2c, 0xc6, 0x81, 0xd1,
38 0x5b, 0xdb, 0xf4, 0xf7,
39 0xfc, 0xa2, 0x83, 0x19,
40 0xdb, 0x1a, 0x3e, 0x94,
41 0x6b, 0x9e, 0x38, 0xd9,
42 0x2c, 0x9c, 0x03, 0xd1,
43 0xad, 0x99, 0x44, 0xa7,
44 0xd9, 0x56, 0x3d, 0x59,
45 0x06, 0x3c, 0x25, 0xf3,
46 0xfc, 0x1f, 0xdc, 0x2a,
49 /* Length of the default RSS hash key. */
50 static_assert(MLX5_RSS_HASH_KEY_LEN ==
51 (unsigned int)sizeof(rss_hash_default_key),
52 "wrong RSS default key size.");
55 * Check whether Multi-Packet RQ can be enabled for the device.
58 * Pointer to Ethernet device.
61 * 1 if supported, negative errno value if not.
64 mlx5_check_mprq_support(struct rte_eth_dev *dev)
66 struct mlx5_priv *priv = dev->data->dev_private;
68 if (priv->config.mprq.enabled &&
69 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
75 * Check whether Multi-Packet RQ is enabled for the Rx queue.
78 * Pointer to receive queue structure.
81 * 0 if disabled, otherwise enabled.
84 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
86 return rxq->strd_num_n > 0;
90 * Check whether Multi-Packet RQ is enabled for the device.
93 * Pointer to Ethernet device.
96 * 0 if disabled, otherwise enabled.
99 mlx5_mprq_enabled(struct rte_eth_dev *dev)
101 struct mlx5_priv *priv = dev->data->dev_private;
106 if (mlx5_check_mprq_support(dev) < 0)
108 /* All the configured queues should be enabled. */
109 for (i = 0; i < priv->rxqs_n; ++i) {
110 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
111 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
112 (rxq, struct mlx5_rxq_ctrl, rxq);
114 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
117 if (mlx5_rxq_mprq_enabled(rxq))
120 /* Multi-Packet RQ can't be partially configured. */
121 MLX5_ASSERT(n == 0 || n == n_ibv);
126 * Allocate RX queue elements for Multi-Packet RQ.
129 * Pointer to RX queue structure.
132 * 0 on success, a negative errno value otherwise and rte_errno is set.
135 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
137 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
138 unsigned int wqe_n = 1 << rxq->elts_n;
142 /* Iterate on segments. */
143 for (i = 0; i <= wqe_n; ++i) {
144 struct mlx5_mprq_buf *buf;
146 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
147 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
152 (*rxq->mprq_bufs)[i] = buf;
154 rxq->mprq_repl = buf;
157 "port %u Rx queue %u allocated and configured %u segments",
158 rxq->port_id, rxq->idx, wqe_n);
161 err = rte_errno; /* Save rte_errno before cleanup. */
163 for (i = 0; (i != wqe_n); ++i) {
164 if ((*rxq->mprq_bufs)[i] != NULL)
165 rte_mempool_put(rxq->mprq_mp,
166 (*rxq->mprq_bufs)[i]);
167 (*rxq->mprq_bufs)[i] = NULL;
169 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
170 rxq->port_id, rxq->idx);
171 rte_errno = err; /* Restore rte_errno. */
176 * Allocate RX queue elements for Single-Packet RQ.
179 * Pointer to RX queue structure.
182 * 0 on success, errno value on failure.
185 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
187 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
188 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
192 /* Iterate on segments. */
193 for (i = 0; (i != elts_n); ++i) {
194 struct rte_mbuf *buf;
196 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
198 DRV_LOG(ERR, "port %u empty mbuf pool",
199 PORT_ID(rxq_ctrl->priv));
203 /* Headroom is reserved by rte_pktmbuf_alloc(). */
204 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
205 /* Buffer is supposed to be empty. */
206 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
207 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
208 MLX5_ASSERT(!buf->next);
209 /* Only the first segment keeps headroom. */
211 SET_DATA_OFF(buf, 0);
212 PORT(buf) = rxq_ctrl->rxq.port_id;
213 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
214 PKT_LEN(buf) = DATA_LEN(buf);
216 (*rxq_ctrl->rxq.elts)[i] = buf;
218 /* If Rx vector is activated. */
219 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
220 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
221 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
222 struct rte_pktmbuf_pool_private *priv =
223 (struct rte_pktmbuf_pool_private *)
224 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
227 /* Initialize default rearm_data for vPMD. */
228 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
229 rte_mbuf_refcnt_set(mbuf_init, 1);
230 mbuf_init->nb_segs = 1;
231 mbuf_init->port = rxq->port_id;
232 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
233 mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
235 * prevent compiler reordering:
236 * rearm_data covers previous fields.
238 rte_compiler_barrier();
239 rxq->mbuf_initializer =
240 *(rte_xmm_t *)&mbuf_init->rearm_data;
241 /* Padding with a fake mbuf for vectorized Rx. */
242 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
243 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
246 "port %u Rx queue %u allocated and configured %u segments"
248 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
249 elts_n / (1 << rxq_ctrl->rxq.sges_n));
252 err = rte_errno; /* Save rte_errno before cleanup. */
254 for (i = 0; (i != elts_n); ++i) {
255 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
256 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
257 (*rxq_ctrl->rxq.elts)[i] = NULL;
259 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
260 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
261 rte_errno = err; /* Restore rte_errno. */
266 * Allocate RX queue elements.
269 * Pointer to RX queue structure.
272 * 0 on success, errno value on failure.
275 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
277 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
278 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
282 * Free RX queue elements for Multi-Packet RQ.
285 * Pointer to RX queue structure.
288 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
290 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
293 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
294 rxq->port_id, rxq->idx);
295 if (rxq->mprq_bufs == NULL)
297 MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
298 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
299 if ((*rxq->mprq_bufs)[i] != NULL)
300 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
301 (*rxq->mprq_bufs)[i] = NULL;
303 if (rxq->mprq_repl != NULL) {
304 mlx5_mprq_buf_free(rxq->mprq_repl);
305 rxq->mprq_repl = NULL;
310 * Free RX queue elements for Single-Packet RQ.
313 * Pointer to RX queue structure.
316 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
318 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
319 const uint16_t q_n = (1 << rxq->elts_n);
320 const uint16_t q_mask = q_n - 1;
321 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
324 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
325 PORT_ID(rxq_ctrl->priv), rxq->idx);
326 if (rxq->elts == NULL)
329 * Some mbuf in the Ring belongs to the application. They cannot be
332 if (mlx5_rxq_check_vec_support(rxq) > 0) {
333 for (i = 0; i < used; ++i)
334 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
335 rxq->rq_pi = rxq->rq_ci;
337 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
338 if ((*rxq->elts)[i] != NULL)
339 rte_pktmbuf_free_seg((*rxq->elts)[i]);
340 (*rxq->elts)[i] = NULL;
345 * Free RX queue elements.
348 * Pointer to RX queue structure.
351 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
353 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
354 rxq_free_elts_mprq(rxq_ctrl);
356 rxq_free_elts_sprq(rxq_ctrl);
360 * Returns the per-queue supported offloads.
363 * Pointer to Ethernet device.
366 * Supported Rx offloads.
369 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
371 struct mlx5_priv *priv = dev->data->dev_private;
372 struct mlx5_dev_config *config = &priv->config;
373 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
374 DEV_RX_OFFLOAD_TIMESTAMP |
375 DEV_RX_OFFLOAD_JUMBO_FRAME |
376 DEV_RX_OFFLOAD_RSS_HASH);
378 if (config->hw_fcs_strip)
379 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
382 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
383 DEV_RX_OFFLOAD_UDP_CKSUM |
384 DEV_RX_OFFLOAD_TCP_CKSUM);
385 if (config->hw_vlan_strip)
386 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
387 if (MLX5_LRO_SUPPORTED(dev))
388 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
394 * Returns the per-port supported offloads.
397 * Supported Rx offloads.
400 mlx5_get_rx_port_offloads(void)
402 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
408 * Verify if the queue can be released.
411 * Pointer to Ethernet device.
416 * 1 if the queue can be released
417 * 0 if the queue can not be released, there are references to it.
418 * Negative errno and rte_errno is set if queue doesn't exist.
421 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
423 struct mlx5_priv *priv = dev->data->dev_private;
424 struct mlx5_rxq_ctrl *rxq_ctrl;
426 if (!(*priv->rxqs)[idx]) {
430 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
431 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
434 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
436 rxq_sync_cq(struct mlx5_rxq_data *rxq)
438 const uint16_t cqe_n = 1 << rxq->cqe_n;
439 const uint16_t cqe_mask = cqe_n - 1;
440 volatile struct mlx5_cqe *cqe;
445 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
446 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
447 if (ret == MLX5_CQE_STATUS_HW_OWN)
449 if (ret == MLX5_CQE_STATUS_ERR) {
453 MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
454 if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
458 /* Compute the next non compressed CQE. */
459 rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);
462 /* Move all CQEs to HW ownership, including possible MiniCQEs. */
463 for (i = 0; i < cqe_n; i++) {
464 cqe = &(*rxq->cqes)[i];
465 cqe->op_own = MLX5_CQE_INVALIDATE;
467 /* Resync CQE and WQE (WQ in RESET state). */
469 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
471 *rxq->rq_db = rte_cpu_to_be_32(0);
476 * Rx queue stop. Device queue goes to the RESET state,
477 * all involved mbufs are freed from WQ.
480 * Pointer to Ethernet device structure.
485 * 0 on success, a negative errno value otherwise and rte_errno is set.
488 mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
490 struct mlx5_priv *priv = dev->data->dev_private;
491 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
492 struct mlx5_rxq_ctrl *rxq_ctrl =
493 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
496 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
497 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
498 struct ibv_wq_attr mod = {
499 .attr_mask = IBV_WQ_ATTR_STATE,
500 .wq_state = IBV_WQS_RESET,
503 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
504 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
505 struct mlx5_devx_modify_rq_attr rq_attr;
507 memset(&rq_attr, 0, sizeof(rq_attr));
508 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
509 rq_attr.state = MLX5_RQC_STATE_RST;
510 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
513 DRV_LOG(ERR, "Cannot change Rx WQ state to RESET: %s",
518 /* Remove all processes CQEs. */
520 /* Free all involved mbufs. */
521 rxq_free_elts(rxq_ctrl);
522 /* Set the actual queue state. */
523 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
528 * Rx queue stop. Device queue goes to the RESET state,
529 * all involved mbufs are freed from WQ.
532 * Pointer to Ethernet device structure.
537 * 0 on success, a negative errno value otherwise and rte_errno is set.
540 mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
542 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
545 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
546 DRV_LOG(ERR, "Hairpin queue can't be stopped");
550 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
553 * Vectorized Rx burst requires the CQ and RQ indices
554 * synchronized, that might be broken on RQ restart
555 * and cause Rx malfunction, so queue stopping is
556 * not supported if vectorized Rx burst is engaged.
557 * The routine pointer depends on the process
558 * type, should perform check there.
560 if (pkt_burst == mlx5_rx_burst) {
561 DRV_LOG(ERR, "Rx queue stop is not supported "
562 "for vectorized Rx");
566 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
567 ret = mlx5_mp_os_req_queue_control(dev, idx,
568 MLX5_MP_REQ_QUEUE_RX_STOP);
570 ret = mlx5_rx_queue_stop_primary(dev, idx);
576 * Rx queue start. Device queue goes to the ready state,
577 * all required mbufs are allocated and WQ is replenished.
580 * Pointer to Ethernet device structure.
585 * 0 on success, a negative errno value otherwise and rte_errno is set.
588 mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
590 struct mlx5_priv *priv = dev->data->dev_private;
591 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
592 struct mlx5_rxq_ctrl *rxq_ctrl =
593 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
596 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
597 /* Allocate needed buffers. */
598 ret = rxq_alloc_elts(rxq_ctrl);
600 DRV_LOG(ERR, "Cannot reallocate buffers for Rx WQ");
605 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
607 /* Reset RQ consumer before moving queue to READY state. */
608 *rxq->rq_db = rte_cpu_to_be_32(0);
610 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
611 struct ibv_wq_attr mod = {
612 .attr_mask = IBV_WQ_ATTR_STATE,
613 .wq_state = IBV_WQS_RDY,
616 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
617 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
618 struct mlx5_devx_modify_rq_attr rq_attr;
620 memset(&rq_attr, 0, sizeof(rq_attr));
621 rq_attr.rq_state = MLX5_RQC_STATE_RST;
622 rq_attr.state = MLX5_RQC_STATE_RDY;
623 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
626 DRV_LOG(ERR, "Cannot change Rx WQ state to READY: %s",
631 /* Reinitialize RQ - set WQEs. */
632 mlx5_rxq_initialize(rxq);
633 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
634 /* Set actual queue state. */
635 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
640 * Rx queue start. Device queue goes to the ready state,
641 * all required mbufs are allocated and WQ is replenished.
644 * Pointer to Ethernet device structure.
649 * 0 on success, a negative errno value otherwise and rte_errno is set.
652 mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
656 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
657 DRV_LOG(ERR, "Hairpin queue can't be started");
661 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
663 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
664 ret = mlx5_mp_os_req_queue_control(dev, idx,
665 MLX5_MP_REQ_QUEUE_RX_START);
667 ret = mlx5_rx_queue_start_primary(dev, idx);
673 * Rx queue presetup checks.
676 * Pointer to Ethernet device structure.
680 * Number of descriptors to configure in queue.
683 * 0 on success, a negative errno value otherwise and rte_errno is set.
686 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
688 struct mlx5_priv *priv = dev->data->dev_private;
690 if (!rte_is_power_of_2(*desc)) {
691 *desc = 1 << log2above(*desc);
693 "port %u increased number of descriptors in Rx queue %u"
694 " to the next power of two (%d)",
695 dev->data->port_id, idx, *desc);
697 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
698 dev->data->port_id, idx, *desc);
699 if (idx >= priv->rxqs_n) {
700 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
701 dev->data->port_id, idx, priv->rxqs_n);
702 rte_errno = EOVERFLOW;
705 if (!mlx5_rxq_releasable(dev, idx)) {
706 DRV_LOG(ERR, "port %u unable to release queue index %u",
707 dev->data->port_id, idx);
711 mlx5_rxq_release(dev, idx);
718 * Pointer to Ethernet device structure.
722 * Number of descriptors to configure in queue.
724 * NUMA socket on which memory must be allocated.
726 * Thresholds parameters.
728 * Memory pool for buffer allocations.
731 * 0 on success, a negative errno value otherwise and rte_errno is set.
734 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
735 unsigned int socket, const struct rte_eth_rxconf *conf,
736 struct rte_mempool *mp)
738 struct mlx5_priv *priv = dev->data->dev_private;
739 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
740 struct mlx5_rxq_ctrl *rxq_ctrl =
741 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
744 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
747 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
749 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
750 dev->data->port_id, idx);
754 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
755 dev->data->port_id, idx);
756 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
763 * Pointer to Ethernet device structure.
767 * Number of descriptors to configure in queue.
768 * @param hairpin_conf
769 * Hairpin configuration parameters.
772 * 0 on success, a negative errno value otherwise and rte_errno is set.
775 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
777 const struct rte_eth_hairpin_conf *hairpin_conf)
779 struct mlx5_priv *priv = dev->data->dev_private;
780 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
781 struct mlx5_rxq_ctrl *rxq_ctrl =
782 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
785 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
788 if (hairpin_conf->peer_count != 1 ||
789 hairpin_conf->peers[0].port != dev->data->port_id ||
790 hairpin_conf->peers[0].queue >= priv->txqs_n) {
791 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
792 " invalid hairpind configuration", dev->data->port_id,
797 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
799 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
800 dev->data->port_id, idx);
804 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
805 dev->data->port_id, idx);
806 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
811 * DPDK callback to release a RX queue.
814 * Generic RX queue pointer.
817 mlx5_rx_queue_release(void *dpdk_rxq)
819 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
820 struct mlx5_rxq_ctrl *rxq_ctrl;
821 struct mlx5_priv *priv;
825 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
826 priv = rxq_ctrl->priv;
827 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
828 rte_panic("port %u Rx queue %u is still used by a flow and"
829 " cannot be removed\n",
830 PORT_ID(priv), rxq->idx);
831 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
835 * Release the resources allocated for an RQ DevX object.
838 * DevX Rx queue object.
841 rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
843 if (rxq_ctrl->rxq.wqes) {
844 mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
845 rxq_ctrl->rxq.wqes = NULL;
847 if (rxq_ctrl->wq_umem) {
848 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
849 rxq_ctrl->wq_umem = NULL;
854 * Release the resources allocated for the Rx CQ DevX object.
857 * DevX Rx queue object.
860 rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
862 if (rxq_ctrl->rxq.cqes) {
863 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);
864 rxq_ctrl->rxq.cqes = NULL;
866 if (rxq_ctrl->cq_umem) {
867 mlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);
868 rxq_ctrl->cq_umem = NULL;
873 * Release an Rx hairpin related resources.
876 * Hairpin Rx queue object.
879 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
881 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
883 MLX5_ASSERT(rxq_obj);
884 rq_attr.state = MLX5_RQC_STATE_RST;
885 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
886 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
887 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
891 * Release an Rx verbs/DevX queue object.
894 * Verbs/DevX Rx queue object.
897 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
899 struct mlx5_priv *priv = rxq_obj->rxq_ctrl->priv;
900 struct mlx5_rxq_ctrl *rxq_ctrl = rxq_obj->rxq_ctrl;
902 MLX5_ASSERT(rxq_obj);
903 switch (rxq_obj->type) {
904 case MLX5_RXQ_OBJ_TYPE_IBV:
905 MLX5_ASSERT(rxq_obj->wq);
906 MLX5_ASSERT(rxq_obj->ibv_cq);
907 rxq_free_elts(rxq_ctrl);
908 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
909 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
910 if (rxq_obj->ibv_channel)
911 claim_zero(mlx5_glue->destroy_comp_channel
912 (rxq_obj->ibv_channel));
914 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
915 MLX5_ASSERT(rxq_obj->rq);
916 MLX5_ASSERT(rxq_obj->devx_cq);
917 rxq_free_elts(rxq_ctrl);
918 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
919 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));
920 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
921 rxq_ctrl->rq_dbr_umem_id,
922 rxq_ctrl->rq_dbr_offset));
923 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
924 rxq_ctrl->cq_dbr_umem_id,
925 rxq_ctrl->cq_dbr_offset));
926 if (rxq_obj->devx_channel)
927 mlx5_glue->devx_destroy_event_channel
928 (rxq_obj->devx_channel);
929 rxq_release_devx_rq_resources(rxq_ctrl);
930 rxq_release_devx_cq_resources(rxq_ctrl);
932 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
933 MLX5_ASSERT(rxq_obj->rq);
934 rxq_obj_hairpin_release(rxq_obj);
937 LIST_REMOVE(rxq_obj, next);
942 * Allocate queue vector and fill epoll fd list for Rx interrupts.
945 * Pointer to Ethernet device.
948 * 0 on success, a negative errno value otherwise and rte_errno is set.
951 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
953 struct mlx5_priv *priv = dev->data->dev_private;
955 unsigned int rxqs_n = priv->rxqs_n;
956 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
957 unsigned int count = 0;
958 struct rte_intr_handle *intr_handle = dev->intr_handle;
960 if (!dev->data->dev_conf.intr_conf.rxq)
962 mlx5_rx_intr_vec_disable(dev);
963 intr_handle->intr_vec = mlx5_malloc(0,
964 n * sizeof(intr_handle->intr_vec[0]),
966 if (intr_handle->intr_vec == NULL) {
968 "port %u failed to allocate memory for interrupt"
969 " vector, Rx interrupts will not be supported",
974 intr_handle->type = RTE_INTR_HANDLE_EXT;
975 for (i = 0; i != n; ++i) {
976 /* This rxq obj must not be released in this function. */
977 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);
978 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl ? rxq_ctrl->obj : NULL;
981 /* Skip queues that cannot request interrupts. */
982 if (!rxq_obj || (!rxq_obj->ibv_channel &&
983 !rxq_obj->devx_channel)) {
984 /* Use invalid intr_vec[] index to disable entry. */
985 intr_handle->intr_vec[i] =
986 RTE_INTR_VEC_RXTX_OFFSET +
987 RTE_MAX_RXTX_INTR_VEC_ID;
988 /* Decrease the rxq_ctrl's refcnt */
990 mlx5_rxq_release(dev, i);
993 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
995 "port %u too many Rx queues for interrupt"
996 " vector size (%d), Rx interrupts cannot be"
998 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
999 mlx5_rx_intr_vec_disable(dev);
1003 rc = mlx5_os_set_nonblock_channel_fd(rxq_obj->fd);
1007 "port %u failed to make Rx interrupt file"
1008 " descriptor %d non-blocking for queue index"
1010 dev->data->port_id, rxq_obj->fd, i);
1011 mlx5_rx_intr_vec_disable(dev);
1014 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
1015 intr_handle->efds[count] = rxq_obj->fd;
1019 mlx5_rx_intr_vec_disable(dev);
1021 intr_handle->nb_efd = count;
1026 * Clean up Rx interrupts handler.
1029 * Pointer to Ethernet device.
1032 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
1034 struct mlx5_priv *priv = dev->data->dev_private;
1035 struct rte_intr_handle *intr_handle = dev->intr_handle;
1037 unsigned int rxqs_n = priv->rxqs_n;
1038 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
1040 if (!dev->data->dev_conf.intr_conf.rxq)
1042 if (!intr_handle->intr_vec)
1044 for (i = 0; i != n; ++i) {
1045 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
1046 RTE_MAX_RXTX_INTR_VEC_ID)
1049 * Need to access directly the queue to release the reference
1050 * kept in mlx5_rx_intr_vec_enable().
1052 mlx5_rxq_release(dev, i);
1055 rte_intr_free_epoll_fd(intr_handle);
1056 if (intr_handle->intr_vec)
1057 mlx5_free(intr_handle->intr_vec);
1058 intr_handle->nb_efd = 0;
1059 intr_handle->intr_vec = NULL;
1063 * MLX5 CQ notification .
1066 * Pointer to receive queue structure.
1068 * Sequence number per receive queue .
1071 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
1074 uint32_t doorbell_hi;
1076 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
1078 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
1079 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
1080 doorbell = (uint64_t)doorbell_hi << 32;
1081 doorbell |= rxq->cqn;
1082 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
1083 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
1084 cq_db_reg, rxq->uar_lock_cq);
1088 * DPDK callback for Rx queue interrupt enable.
1091 * Pointer to Ethernet device structure.
1092 * @param rx_queue_id
1096 * 0 on success, a negative errno value otherwise and rte_errno is set.
1099 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1101 struct mlx5_rxq_ctrl *rxq_ctrl;
1103 rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
1106 if (rxq_ctrl->irq) {
1107 if (!rxq_ctrl->obj) {
1108 mlx5_rxq_release(dev, rx_queue_id);
1111 mlx5_arm_cq(&rxq_ctrl->rxq, rxq_ctrl->rxq.cq_arm_sn);
1113 mlx5_rxq_release(dev, rx_queue_id);
1121 * DPDK callback for Rx queue interrupt disable.
1124 * Pointer to Ethernet device structure.
1125 * @param rx_queue_id
1129 * 0 on success, a negative errno value otherwise and rte_errno is set.
1132 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1134 struct mlx5_rxq_ctrl *rxq_ctrl;
1135 struct mlx5_rxq_obj *rxq_obj = NULL;
1136 struct ibv_cq *ev_cq;
1140 rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
1145 if (!rxq_ctrl->irq) {
1146 mlx5_rxq_release(dev, rx_queue_id);
1149 rxq_obj = rxq_ctrl->obj;
1152 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1153 ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel, &ev_cq,
1155 if (ret < 0 || ev_cq != rxq_obj->ibv_cq)
1157 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);
1158 } else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1159 #ifdef HAVE_IBV_DEVX_EVENT
1161 struct mlx5dv_devx_async_event_hdr event_resp;
1162 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
1166 ret = mlx5_glue->devx_get_event
1167 (rxq_obj->devx_channel, &out.event_resp,
1169 if (ret < 0 || out.event_resp.cookie !=
1170 (uint64_t)(uintptr_t)rxq_obj->devx_cq)
1172 #endif /* HAVE_IBV_DEVX_EVENT */
1174 rxq_ctrl->rxq.cq_arm_sn++;
1175 mlx5_rxq_release(dev, rx_queue_id);
1179 * For ret < 0 save the errno (may be EAGAIN which means the get_event
1180 * function was called before receiving one).
1186 ret = rte_errno; /* Save rte_errno before cleanup. */
1187 mlx5_rxq_release(dev, rx_queue_id);
1189 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
1190 dev->data->port_id, rx_queue_id);
1191 rte_errno = ret; /* Restore rte_errno. */
1196 * Create a CQ Verbs object.
1199 * Pointer to Ethernet device.
1201 * Pointer to device private data.
1203 * Pointer to Rx queue data.
1205 * Number of CQEs in CQ.
1207 * Pointer to Rx queue object data.
1210 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1212 static struct ibv_cq *
1213 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1214 struct mlx5_rxq_data *rxq_data,
1215 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
1218 struct ibv_cq_init_attr_ex ibv;
1219 struct mlx5dv_cq_init_attr mlx5;
1222 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
1224 .channel = rxq_obj->ibv_channel,
1227 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
1230 if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
1231 cq_attr.mlx5.comp_mask |=
1232 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
1233 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1234 cq_attr.mlx5.cqe_comp_res_format =
1235 mlx5_rxq_mprq_enabled(rxq_data) ?
1236 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
1237 MLX5DV_CQE_RES_FORMAT_HASH;
1239 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1242 * For vectorized Rx, it must not be doubled in order to
1243 * make cq_ci and rq_ci aligned.
1245 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1246 cq_attr.ibv.cqe *= 2;
1247 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1249 "port %u Rx CQE compression is disabled for HW"
1251 dev->data->port_id);
1253 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1254 if (priv->config.cqe_pad) {
1255 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1256 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1259 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1265 * Create a WQ Verbs object.
1268 * Pointer to Ethernet device.
1270 * Pointer to device private data.
1272 * Pointer to Rx queue data.
1274 * Queue index in DPDK Rx queue array
1276 * Number of WQEs in WQ.
1278 * Pointer to Rx queue object data.
1281 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1283 static struct ibv_wq *
1284 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1285 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1286 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1289 struct ibv_wq_init_attr ibv;
1290 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1291 struct mlx5dv_wq_init_attr mlx5;
1295 wq_attr.ibv = (struct ibv_wq_init_attr){
1296 .wq_context = NULL, /* Could be useful in the future. */
1297 .wq_type = IBV_WQT_RQ,
1298 /* Max number of outstanding WRs. */
1299 .max_wr = wqe_n >> rxq_data->sges_n,
1300 /* Max number of scatter/gather elements in a WR. */
1301 .max_sge = 1 << rxq_data->sges_n,
1303 .cq = rxq_obj->ibv_cq,
1304 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1305 .create_flags = (rxq_data->vlan_strip ?
1306 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1308 /* By default, FCS (CRC) is stripped by hardware. */
1309 if (rxq_data->crc_present) {
1310 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1311 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1313 if (priv->config.hw_padding) {
1314 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1315 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1316 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1317 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1318 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1319 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1322 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1323 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1326 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1327 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1328 &wq_attr.mlx5.striding_rq_attrs;
1330 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1331 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1332 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1333 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1334 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1337 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1340 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1344 * Make sure number of WRs*SGEs match expectations since a queue
1345 * cannot allocate more than "desc" buffers.
1347 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1348 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1350 "port %u Rx queue %u requested %u*%u but got"
1352 dev->data->port_id, idx,
1353 wqe_n >> rxq_data->sges_n,
1354 (1 << rxq_data->sges_n),
1355 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1356 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1365 * Fill common fields of create RQ attributes structure.
1368 * Pointer to Rx queue data.
1370 * CQ number to use with this RQ.
1372 * RQ attributes structure to fill..
1375 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1376 struct mlx5_devx_create_rq_attr *rq_attr)
1378 rq_attr->state = MLX5_RQC_STATE_RST;
1379 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1381 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1385 * Fill common fields of DevX WQ attributes structure.
1388 * Pointer to device private data.
1390 * Pointer to Rx queue control structure.
1392 * WQ attributes structure to fill..
1395 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1396 struct mlx5_devx_wq_attr *wq_attr)
1398 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1399 MLX5_WQ_END_PAD_MODE_ALIGN :
1400 MLX5_WQ_END_PAD_MODE_NONE;
1401 wq_attr->pd = priv->sh->pdn;
1402 wq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;
1403 wq_attr->dbr_umem_id = rxq_ctrl->rq_dbr_umem_id;
1404 wq_attr->dbr_umem_valid = 1;
1405 wq_attr->wq_umem_id = mlx5_os_get_umem_id(rxq_ctrl->wq_umem);
1406 wq_attr->wq_umem_valid = 1;
1410 * Create a RQ object using DevX.
1413 * Pointer to Ethernet device.
1415 * Queue index in DPDK Rx queue array
1417 * CQ number to use with this RQ.
1420 * The DevX object initialised, NULL otherwise and rte_errno is set.
1422 static struct mlx5_devx_obj *
1423 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1425 struct mlx5_priv *priv = dev->data->dev_private;
1426 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1427 struct mlx5_rxq_ctrl *rxq_ctrl =
1428 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1429 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
1430 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1431 uint32_t wq_size = 0;
1432 uint32_t wqe_size = 0;
1433 uint32_t log_wqe_size = 0;
1435 struct mlx5_devx_obj *rq;
1437 /* Fill RQ attributes. */
1438 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1439 rq_attr.flush_in_error_en = 1;
1440 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1441 /* Fill WQ attributes for this RQ. */
1442 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1443 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1445 * Number of strides in each WQE:
1446 * 512*2^single_wqe_log_num_of_strides.
1448 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1449 rxq_data->strd_num_n -
1450 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1451 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1452 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1453 rxq_data->strd_sz_n -
1454 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1455 wqe_size = sizeof(struct mlx5_wqe_mprq);
1457 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1458 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1460 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1461 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1462 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1463 /* Calculate and allocate WQ memory space. */
1464 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1465 wq_size = wqe_n * wqe_size;
1466 size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
1467 if (alignment == (size_t)-1) {
1468 DRV_LOG(ERR, "Failed to get mem page size");
1472 buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
1473 alignment, rxq_ctrl->socket);
1476 rxq_data->wqes = buf;
1477 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1479 if (!rxq_ctrl->wq_umem) {
1483 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1484 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1486 rxq_release_devx_rq_resources(rxq_ctrl);
1491 * Create a DevX CQ object for an Rx queue.
1494 * Pointer to Ethernet device.
1496 * Number of CQEs in CQ.
1498 * Queue index in DPDK Rx queue array
1500 * Pointer to Rx queue object data.
1503 * The DevX object initialised, NULL otherwise and rte_errno is set.
1505 static struct mlx5_devx_obj *
1506 mlx5_devx_cq_new(struct rte_eth_dev *dev, unsigned int cqe_n, uint16_t idx,
1507 struct mlx5_rxq_obj *rxq_obj)
1509 struct mlx5_devx_obj *cq_obj = 0;
1510 struct mlx5_devx_cq_attr cq_attr = { 0 };
1511 struct mlx5_priv *priv = dev->data->dev_private;
1512 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1513 struct mlx5_rxq_ctrl *rxq_ctrl =
1514 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1515 size_t page_size = rte_mem_page_size();
1516 uint32_t lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
1519 uint16_t event_nums[1] = {0};
1524 if (page_size == (size_t)-1) {
1525 DRV_LOG(ERR, "Failed to get page_size.");
1528 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
1530 cq_attr.cqe_comp_en = MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
1531 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1532 cq_attr.mini_cqe_res_format =
1533 mlx5_rxq_mprq_enabled(rxq_data) ?
1534 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
1535 MLX5DV_CQE_RES_FORMAT_HASH;
1537 cq_attr.mini_cqe_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1540 * For vectorized Rx, it must not be doubled in order to
1541 * make cq_ci and rq_ci aligned.
1543 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1545 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1547 "port %u Rx CQE compression is disabled for HW"
1549 dev->data->port_id);
1550 } else if (priv->config.cqe_comp && rxq_data->lro) {
1552 "port %u Rx CQE compression is disabled for LRO",
1553 dev->data->port_id);
1555 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1556 if (priv->config.cqe_pad)
1557 cq_attr.cqe_size = MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1559 log_cqe_n = log2above(cqe_n);
1560 cq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);
1561 /* Query the EQN for this core. */
1562 if (mlx5_glue->devx_query_eqn(priv->sh->ctx, lcore, &eqn)) {
1563 DRV_LOG(ERR, "Failed to query EQN for CQ.");
1567 buf = rte_calloc_socket(__func__, 1, cq_size, page_size,
1570 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
1573 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)buf;
1574 rxq_ctrl->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, buf,
1576 IBV_ACCESS_LOCAL_WRITE);
1577 if (!rxq_ctrl->cq_umem) {
1578 DRV_LOG(ERR, "Failed to register umem for CQ.");
1581 cq_attr.uar_page_id =
1582 mlx5_os_get_devx_uar_page_id(priv->sh->devx_rx_uar);
1583 cq_attr.q_umem_id = mlx5_os_get_umem_id(rxq_ctrl->cq_umem);
1584 cq_attr.q_umem_valid = 1;
1585 cq_attr.log_cq_size = log_cqe_n;
1586 cq_attr.log_page_size = rte_log2_u32(page_size);
1587 cq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;
1588 cq_attr.db_umem_id = rxq_ctrl->cq_dbr_umem_id;
1589 cq_attr.db_umem_valid = 1;
1590 cq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);
1593 rxq_data->cqe_n = log_cqe_n;
1594 rxq_data->cqn = cq_obj->id;
1595 if (rxq_obj->devx_channel) {
1596 ret = mlx5_glue->devx_subscribe_devx_event
1597 (rxq_obj->devx_channel,
1601 (uint64_t)(uintptr_t)cq_obj);
1603 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
1608 /* Initialise CQ to 1's to mark HW ownership for all CQEs. */
1609 memset((void *)(uintptr_t)rxq_data->cqes, 0xFF, cq_size);
1613 mlx5_devx_cmd_destroy(cq_obj);
1614 rxq_release_devx_cq_resources(rxq_ctrl);
1619 * Create the Rx hairpin queue object.
1622 * Pointer to Ethernet device.
1624 * Queue index in DPDK Rx queue array
1627 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1629 static struct mlx5_rxq_obj *
1630 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1632 struct mlx5_priv *priv = dev->data->dev_private;
1633 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1634 struct mlx5_rxq_ctrl *rxq_ctrl =
1635 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1636 struct mlx5_devx_create_rq_attr attr = { 0 };
1637 struct mlx5_rxq_obj *tmpl = NULL;
1638 uint32_t max_wq_data;
1640 MLX5_ASSERT(rxq_data);
1641 MLX5_ASSERT(!rxq_ctrl->obj);
1642 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1645 DRV_LOG(ERR, "port %u Rx queue %u cannot allocate resources",
1646 dev->data->port_id, rxq_data->idx);
1650 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1651 tmpl->rxq_ctrl = rxq_ctrl;
1653 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1654 /* Jumbo frames > 9KB should be supported, and more packets. */
1655 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1656 if (priv->config.log_hp_size > max_wq_data) {
1657 DRV_LOG(ERR, "total data size %u power of 2 is "
1658 "too large for hairpin",
1659 priv->config.log_hp_size);
1664 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1666 attr.wq_attr.log_hairpin_data_sz =
1667 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1668 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1670 /* Set the packets number to the maximum value for performance. */
1671 attr.wq_attr.log_hairpin_num_packets =
1672 attr.wq_attr.log_hairpin_data_sz -
1673 MLX5_HAIRPIN_QUEUE_STRIDE;
1674 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1678 "port %u Rx hairpin queue %u can't create rq object",
1679 dev->data->port_id, idx);
1684 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1685 idx, (void *)&tmpl);
1686 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1687 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
1692 * Create the Rx queue Verbs/DevX object.
1695 * Pointer to Ethernet device.
1697 * Queue index in DPDK Rx queue array
1699 * Type of Rx queue object to create.
1702 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1704 struct mlx5_rxq_obj *
1705 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1706 enum mlx5_rxq_obj_type type)
1708 struct mlx5_priv *priv = dev->data->dev_private;
1709 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1710 struct mlx5_rxq_ctrl *rxq_ctrl =
1711 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1712 struct ibv_wq_attr mod;
1714 unsigned int wqe_n = 1 << rxq_data->elts_n;
1715 struct mlx5_rxq_obj *tmpl = NULL;
1716 struct mlx5_devx_dbr_page *cq_dbr_page = NULL;
1717 struct mlx5_devx_dbr_page *rq_dbr_page = NULL;
1718 struct mlx5dv_cq cq_info;
1719 struct mlx5dv_rwq rwq;
1721 struct mlx5dv_obj obj;
1723 MLX5_ASSERT(rxq_data);
1724 MLX5_ASSERT(!rxq_ctrl->obj);
1725 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1726 return mlx5_rxq_obj_hairpin_new(dev, idx);
1727 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1730 DRV_LOG(ERR, "port %u Rx queue %u cannot allocate resources",
1731 dev->data->port_id, rxq_data->idx);
1736 tmpl->rxq_ctrl = rxq_ctrl;
1737 if (rxq_ctrl->irq) {
1738 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1740 mlx5_glue->create_comp_channel(priv->sh->ctx);
1741 if (!tmpl->ibv_channel) {
1742 DRV_LOG(ERR, "port %u: comp channel creation "
1743 "failure", dev->data->port_id);
1747 tmpl->fd = ((struct ibv_comp_channel *)
1748 (tmpl->ibv_channel))->fd;
1749 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1751 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
1753 tmpl->devx_channel =
1754 mlx5_glue->devx_create_event_channel
1757 if (!tmpl->devx_channel) {
1760 "Failed to create event channel %d.",
1765 mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
1768 if (mlx5_rxq_mprq_enabled(rxq_data))
1769 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1772 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1773 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
1774 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1775 dev->data->port_id, priv->sh->device_attr.max_sge);
1776 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1777 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1778 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1779 /* Create CQ using Verbs API. */
1780 tmpl->ibv_cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n,
1782 if (!tmpl->ibv_cq) {
1783 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1784 dev->data->port_id, idx);
1788 obj.cq.in = tmpl->ibv_cq;
1789 obj.cq.out = &cq_info;
1790 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1795 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1797 "port %u wrong MLX5_CQE_SIZE environment "
1798 "variable value: it should be set to %u",
1799 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1803 /* Fill the rings. */
1804 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1805 rxq_data->cq_db = cq_info.dbrec;
1807 (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1808 rxq_data->cq_uar = cq_info.cq_uar;
1809 rxq_data->cqn = cq_info.cqn;
1810 /* Create WQ (RQ) using Verbs API. */
1811 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1814 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1815 dev->data->port_id, idx);
1819 /* Change queue state to ready. */
1820 mod = (struct ibv_wq_attr){
1821 .attr_mask = IBV_WQ_ATTR_STATE,
1822 .wq_state = IBV_WQS_RDY,
1824 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1827 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1828 " failed", dev->data->port_id, idx);
1832 obj.rwq.in = tmpl->wq;
1834 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1839 rxq_data->wqes = rwq.buf;
1840 rxq_data->rq_db = rwq.dbrec;
1841 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1842 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1843 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
1846 /* Allocate CQ door-bell. */
1847 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1849 if (dbr_offset < 0) {
1850 DRV_LOG(ERR, "Failed to allocate CQ door-bell.");
1853 rxq_ctrl->cq_dbr_offset = dbr_offset;
1854 rxq_ctrl->cq_dbr_umem_id =
1855 mlx5_os_get_umem_id(cq_dbr_page->umem);
1857 (uint32_t *)((uintptr_t)cq_dbr_page->dbrs +
1858 (uintptr_t)rxq_ctrl->cq_dbr_offset);
1860 mlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);
1861 /* Create CQ using DevX API. */
1862 tmpl->devx_cq = mlx5_devx_cq_new(dev, cqe_n, idx, tmpl);
1863 if (!tmpl->devx_cq) {
1864 DRV_LOG(ERR, "Failed to create CQ.");
1867 /* Allocate RQ door-bell. */
1868 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1870 if (dbr_offset < 0) {
1871 DRV_LOG(ERR, "Failed to allocate RQ door-bell.");
1874 rxq_ctrl->rq_dbr_offset = dbr_offset;
1875 rxq_ctrl->rq_dbr_umem_id =
1876 mlx5_os_get_umem_id(rq_dbr_page->umem);
1878 (uint32_t *)((uintptr_t)rq_dbr_page->dbrs +
1879 (uintptr_t)rxq_ctrl->rq_dbr_offset);
1880 /* Create RQ using DevX API. */
1881 tmpl->rq = mlx5_devx_rq_new(dev, idx, tmpl->devx_cq->id);
1883 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1884 dev->data->port_id, idx);
1888 /* Change queue state to ready. */
1889 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1890 rq_attr.state = MLX5_RQC_STATE_RDY;
1891 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1895 rxq_data->cq_arm_sn = 0;
1896 mlx5_rxq_initialize(rxq_data);
1897 rxq_data->cq_ci = 0;
1898 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1899 idx, (void *)&tmpl);
1900 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1901 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1905 ret = rte_errno; /* Save rte_errno before cleanup. */
1906 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1908 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1910 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));
1911 if (tmpl->ibv_channel)
1912 claim_zero(mlx5_glue->destroy_comp_channel
1913 (tmpl->ibv_channel));
1914 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1915 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1917 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1919 claim_zero(mlx5_devx_cmd_destroy
1921 if (tmpl->devx_channel)
1922 mlx5_glue->devx_destroy_event_channel
1923 (tmpl->devx_channel);
1925 claim_zero(mlx5_release_dbr
1927 rxq_ctrl->rq_dbr_umem_id,
1928 rxq_ctrl->rq_dbr_offset));
1930 claim_zero(mlx5_release_dbr
1932 rxq_ctrl->cq_dbr_umem_id,
1933 rxq_ctrl->cq_dbr_offset));
1936 rte_errno = ret; /* Restore rte_errno. */
1938 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1939 rxq_release_devx_rq_resources(rxq_ctrl);
1940 rxq_release_devx_cq_resources(rxq_ctrl);
1946 * Verify the Rx queue objects list is empty
1949 * Pointer to Ethernet device.
1952 * The number of objects not released.
1955 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1957 struct mlx5_priv *priv = dev->data->dev_private;
1959 struct mlx5_rxq_obj *rxq_obj;
1961 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1962 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1963 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1970 * Callback function to initialize mbufs for Multi-Packet RQ.
1973 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1974 void *_m, unsigned int i __rte_unused)
1976 struct mlx5_mprq_buf *buf = _m;
1977 struct rte_mbuf_ext_shared_info *shinfo;
1978 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1981 memset(_m, 0, sizeof(*buf));
1983 rte_atomic16_set(&buf->refcnt, 1);
1984 for (j = 0; j != strd_n; ++j) {
1985 shinfo = &buf->shinfos[j];
1986 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1987 shinfo->fcb_opaque = buf;
1992 * Free mempool of Multi-Packet RQ.
1995 * Pointer to Ethernet device.
1998 * 0 on success, negative errno value on failure.
2001 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
2003 struct mlx5_priv *priv = dev->data->dev_private;
2004 struct rte_mempool *mp = priv->mprq_mp;
2009 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
2010 dev->data->port_id, mp->name);
2012 * If a buffer in the pool has been externally attached to a mbuf and it
2013 * is still in use by application, destroying the Rx queue can spoil
2014 * the packet. It is unlikely to happen but if application dynamically
2015 * creates and destroys with holding Rx packets, this can happen.
2017 * TODO: It is unavoidable for now because the mempool for Multi-Packet
2018 * RQ isn't provided by application but managed by PMD.
2020 if (!rte_mempool_full(mp)) {
2022 "port %u mempool for Multi-Packet RQ is still in use",
2023 dev->data->port_id);
2027 rte_mempool_free(mp);
2028 /* Unset mempool for each Rx queue. */
2029 for (i = 0; i != priv->rxqs_n; ++i) {
2030 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
2034 rxq->mprq_mp = NULL;
2036 priv->mprq_mp = NULL;
2041 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
2042 * mempool. If already allocated, reuse it if there're enough elements.
2043 * Otherwise, resize it.
2046 * Pointer to Ethernet device.
2049 * 0 on success, negative errno value on failure.
2052 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
2054 struct mlx5_priv *priv = dev->data->dev_private;
2055 struct rte_mempool *mp = priv->mprq_mp;
2056 char name[RTE_MEMPOOL_NAMESIZE];
2057 unsigned int desc = 0;
2058 unsigned int buf_len;
2059 unsigned int obj_num;
2060 unsigned int obj_size;
2061 unsigned int strd_num_n = 0;
2062 unsigned int strd_sz_n = 0;
2064 unsigned int n_ibv = 0;
2066 if (!mlx5_mprq_enabled(dev))
2068 /* Count the total number of descriptors configured. */
2069 for (i = 0; i != priv->rxqs_n; ++i) {
2070 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
2071 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
2072 (rxq, struct mlx5_rxq_ctrl, rxq);
2074 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
2077 desc += 1 << rxq->elts_n;
2078 /* Get the max number of strides. */
2079 if (strd_num_n < rxq->strd_num_n)
2080 strd_num_n = rxq->strd_num_n;
2081 /* Get the max size of a stride. */
2082 if (strd_sz_n < rxq->strd_sz_n)
2083 strd_sz_n = rxq->strd_sz_n;
2085 MLX5_ASSERT(strd_num_n && strd_sz_n);
2086 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
2087 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
2088 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
2090 * Received packets can be either memcpy'd or externally referenced. In
2091 * case that the packet is attached to an mbuf as an external buffer, as
2092 * it isn't possible to predict how the buffers will be queued by
2093 * application, there's no option to exactly pre-allocate needed buffers
2094 * in advance but to speculatively prepares enough buffers.
2096 * In the data path, if this Mempool is depleted, PMD will try to memcpy
2097 * received packets to buffers provided by application (rxq->mp) until
2098 * this Mempool gets available again.
2101 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
2103 * rte_mempool_create_empty() has sanity check to refuse large cache
2104 * size compared to the number of elements.
2105 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
2106 * constant number 2 instead.
2108 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
2109 /* Check a mempool is already allocated and if it can be resued. */
2110 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
2111 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
2112 dev->data->port_id, mp->name);
2115 } else if (mp != NULL) {
2116 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
2117 dev->data->port_id, mp->name);
2119 * If failed to free, which means it may be still in use, no way
2120 * but to keep using the existing one. On buffer underrun,
2121 * packets will be memcpy'd instead of external buffer
2124 if (mlx5_mprq_free_mp(dev)) {
2125 if (mp->elt_size >= obj_size)
2131 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
2132 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
2133 0, NULL, NULL, mlx5_mprq_buf_init,
2134 (void *)(uintptr_t)(1 << strd_num_n),
2135 dev->device->numa_node, 0);
2138 "port %u failed to allocate a mempool for"
2139 " Multi-Packet RQ, count=%u, size=%u",
2140 dev->data->port_id, obj_num, obj_size);
2146 /* Set mempool for each Rx queue. */
2147 for (i = 0; i != priv->rxqs_n; ++i) {
2148 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
2149 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
2150 (rxq, struct mlx5_rxq_ctrl, rxq);
2152 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
2156 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
2157 dev->data->port_id);
2161 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
2162 sizeof(struct rte_vlan_hdr) * 2 + \
2163 sizeof(struct rte_ipv6_hdr)))
2164 #define MAX_TCP_OPTION_SIZE 40u
2165 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
2166 sizeof(struct rte_tcp_hdr) + \
2167 MAX_TCP_OPTION_SIZE))
2170 * Adjust the maximum LRO massage size.
2173 * Pointer to Ethernet device.
2176 * @param max_lro_size
2177 * The maximum size for LRO packet.
2180 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
2181 uint32_t max_lro_size)
2183 struct mlx5_priv *priv = dev->data->dev_private;
2185 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
2186 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
2187 MLX5_MAX_TCP_HDR_OFFSET)
2188 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
2189 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
2190 MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
2191 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
2192 if (priv->max_lro_msg_size)
2193 priv->max_lro_msg_size =
2194 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
2196 priv->max_lro_msg_size = max_lro_size;
2198 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
2199 dev->data->port_id, idx,
2200 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
2204 * Create a DPDK Rx queue.
2207 * Pointer to Ethernet device.
2211 * Number of descriptors to configure in queue.
2213 * NUMA socket on which memory must be allocated.
2216 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2218 struct mlx5_rxq_ctrl *
2219 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2220 unsigned int socket, const struct rte_eth_rxconf *conf,
2221 struct rte_mempool *mp)
2223 struct mlx5_priv *priv = dev->data->dev_private;
2224 struct mlx5_rxq_ctrl *tmpl;
2225 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
2226 unsigned int mprq_stride_nums;
2227 unsigned int mprq_stride_size;
2228 unsigned int mprq_stride_cap;
2229 struct mlx5_dev_config *config = &priv->config;
2231 * Always allocate extra slots, even if eventually
2232 * the vector Rx will not be used.
2235 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
2236 uint64_t offloads = conf->offloads |
2237 dev->data->dev_conf.rxmode.offloads;
2238 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
2239 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
2240 unsigned int max_rx_pkt_len = lro_on_queue ?
2241 dev->data->dev_conf.rxmode.max_lro_pkt_size :
2242 dev->data->dev_conf.rxmode.max_rx_pkt_len;
2243 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
2244 RTE_PKTMBUF_HEADROOM;
2245 unsigned int max_lro_size = 0;
2246 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
2248 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
2249 DEV_RX_OFFLOAD_SCATTER)) {
2250 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
2251 " configured and no enough mbuf space(%u) to contain "
2252 "the maximum RX packet length(%u) with head-room(%u)",
2253 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
2254 RTE_PKTMBUF_HEADROOM);
2258 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
2259 desc_n * sizeof(struct rte_mbuf *), 0, socket);
2264 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
2265 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
2266 MLX5_MR_BTREE_CACHE_N, socket)) {
2267 /* rte_errno is already set. */
2270 tmpl->socket = socket;
2271 if (dev->data->dev_conf.intr_conf.rxq)
2273 mprq_stride_nums = config->mprq.stride_num_n ?
2274 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
2275 mprq_stride_size = non_scatter_min_mbuf_size <=
2276 (1U << config->mprq.max_stride_size_n) ?
2277 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
2278 mprq_stride_cap = (config->mprq.stride_num_n ?
2279 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
2280 (config->mprq.stride_size_n ?
2281 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
2283 * This Rx queue can be configured as a Multi-Packet RQ if all of the
2284 * following conditions are met:
2285 * - MPRQ is enabled.
2286 * - The number of descs is more than the number of strides.
2287 * - max_rx_pkt_len plus overhead is less than the max size
2288 * of a stride or mprq_stride_size is specified by a user.
2289 * Need to nake sure that there are enough stides to encap
2290 * the maximum packet size in case mprq_stride_size is set.
2291 * Otherwise, enable Rx scatter if necessary.
2293 if (mprq_en && desc > (1U << mprq_stride_nums) &&
2294 (non_scatter_min_mbuf_size <=
2295 (1U << config->mprq.max_stride_size_n) ||
2296 (config->mprq.stride_size_n &&
2297 non_scatter_min_mbuf_size <= mprq_stride_cap))) {
2298 /* TODO: Rx scatter isn't supported yet. */
2299 tmpl->rxq.sges_n = 0;
2300 /* Trim the number of descs needed. */
2301 desc >>= mprq_stride_nums;
2302 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
2303 config->mprq.stride_num_n : mprq_stride_nums;
2304 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
2305 config->mprq.stride_size_n : mprq_stride_size;
2306 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
2307 tmpl->rxq.strd_scatter_en =
2308 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
2309 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
2310 config->mprq.max_memcpy_len);
2311 max_lro_size = RTE_MIN(max_rx_pkt_len,
2312 (1u << tmpl->rxq.strd_num_n) *
2313 (1u << tmpl->rxq.strd_sz_n));
2315 "port %u Rx queue %u: Multi-Packet RQ is enabled"
2316 " strd_num_n = %u, strd_sz_n = %u",
2317 dev->data->port_id, idx,
2318 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
2319 } else if (max_rx_pkt_len <= first_mb_free_size) {
2320 tmpl->rxq.sges_n = 0;
2321 max_lro_size = max_rx_pkt_len;
2322 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
2323 unsigned int size = non_scatter_min_mbuf_size;
2324 unsigned int sges_n;
2326 if (lro_on_queue && first_mb_free_size <
2327 MLX5_MAX_LRO_HEADER_FIX) {
2328 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
2329 " to include the max header size(%u) for LRO",
2330 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
2331 rte_errno = ENOTSUP;
2335 * Determine the number of SGEs needed for a full packet
2336 * and round it to the next power of two.
2338 sges_n = log2above((size / mb_len) + !!(size % mb_len));
2339 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
2341 "port %u too many SGEs (%u) needed to handle"
2342 " requested maximum packet size %u, the maximum"
2343 " supported are %u", dev->data->port_id,
2344 1 << sges_n, max_rx_pkt_len,
2345 1u << MLX5_MAX_LOG_RQ_SEGS);
2346 rte_errno = ENOTSUP;
2349 tmpl->rxq.sges_n = sges_n;
2350 max_lro_size = max_rx_pkt_len;
2352 if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
2354 "port %u MPRQ is requested but cannot be enabled\n"
2355 " (requested: pkt_sz = %u, desc_num = %u,"
2356 " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
2357 " supported: min_rxqs_num = %u,"
2358 " min_stride_sz = %u, max_stride_sz = %u).",
2359 dev->data->port_id, non_scatter_min_mbuf_size,
2361 config->mprq.stride_size_n ?
2362 (1U << config->mprq.stride_size_n) :
2363 (1U << mprq_stride_size),
2364 config->mprq.stride_num_n ?
2365 (1U << config->mprq.stride_num_n) :
2366 (1U << mprq_stride_nums),
2367 config->mprq.min_rxqs_num,
2368 (1U << config->mprq.min_stride_size_n),
2369 (1U << config->mprq.max_stride_size_n));
2370 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
2371 dev->data->port_id, 1 << tmpl->rxq.sges_n);
2372 if (desc % (1 << tmpl->rxq.sges_n)) {
2374 "port %u number of Rx queue descriptors (%u) is not a"
2375 " multiple of SGEs per packet (%u)",
2378 1 << tmpl->rxq.sges_n);
2382 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
2383 /* Toggle RX checksum offload if hardware supports it. */
2384 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
2385 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
2386 /* Configure VLAN stripping. */
2387 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
2388 /* By default, FCS (CRC) is stripped by hardware. */
2389 tmpl->rxq.crc_present = 0;
2390 tmpl->rxq.lro = lro_on_queue;
2391 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
2392 if (config->hw_fcs_strip) {
2394 * RQs used for LRO-enabled TIRs should not be
2395 * configured to scatter the FCS.
2399 "port %u CRC stripping has been "
2400 "disabled but will still be performed "
2401 "by hardware, because LRO is enabled",
2402 dev->data->port_id);
2404 tmpl->rxq.crc_present = 1;
2407 "port %u CRC stripping has been disabled but will"
2408 " still be performed by hardware, make sure MLNX_OFED"
2409 " and firmware are up to date",
2410 dev->data->port_id);
2414 "port %u CRC stripping is %s, %u bytes will be subtracted from"
2415 " incoming frames to hide it",
2417 tmpl->rxq.crc_present ? "disabled" : "enabled",
2418 tmpl->rxq.crc_present << 2);
2420 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
2421 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
2422 tmpl->rxq.port_id = dev->data->port_id;
2425 tmpl->rxq.elts_n = log2above(desc);
2426 tmpl->rxq.rq_repl_thresh =
2427 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
2429 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
2431 tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
2433 tmpl->rxq.idx = idx;
2434 rte_atomic32_inc(&tmpl->refcnt);
2435 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2443 * Create a DPDK Rx hairpin queue.
2446 * Pointer to Ethernet device.
2450 * Number of descriptors to configure in queue.
2451 * @param hairpin_conf
2452 * The hairpin binding configuration.
2455 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2457 struct mlx5_rxq_ctrl *
2458 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2459 const struct rte_eth_hairpin_conf *hairpin_conf)
2461 struct mlx5_priv *priv = dev->data->dev_private;
2462 struct mlx5_rxq_ctrl *tmpl;
2464 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
2470 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2471 tmpl->socket = SOCKET_ID_ANY;
2472 tmpl->rxq.rss_hash = 0;
2473 tmpl->rxq.port_id = dev->data->port_id;
2475 tmpl->rxq.mp = NULL;
2476 tmpl->rxq.elts_n = log2above(desc);
2477 tmpl->rxq.elts = NULL;
2478 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2479 tmpl->hairpin_conf = *hairpin_conf;
2480 tmpl->rxq.idx = idx;
2481 rte_atomic32_inc(&tmpl->refcnt);
2482 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2490 * Pointer to Ethernet device.
2495 * A pointer to the queue if it exists, NULL otherwise.
2497 struct mlx5_rxq_ctrl *
2498 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2500 struct mlx5_priv *priv = dev->data->dev_private;
2501 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
2502 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2505 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2506 rte_atomic32_inc(&rxq_ctrl->refcnt);
2512 * Release a Rx queue.
2515 * Pointer to Ethernet device.
2520 * 1 while a reference on it exists, 0 when freed.
2523 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2525 struct mlx5_priv *priv = dev->data->dev_private;
2526 struct mlx5_rxq_ctrl *rxq_ctrl;
2528 if (!(*priv->rxqs)[idx])
2530 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2531 if (!rte_atomic32_dec_and_test(&rxq_ctrl->refcnt))
2533 if (rxq_ctrl->obj) {
2534 mlx5_rxq_obj_release(rxq_ctrl->obj);
2535 rxq_ctrl->obj = NULL;
2537 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2538 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2539 LIST_REMOVE(rxq_ctrl, next);
2540 mlx5_free(rxq_ctrl);
2541 (*priv->rxqs)[idx] = NULL;
2546 * Verify the Rx Queue list is empty
2549 * Pointer to Ethernet device.
2552 * The number of object not released.
2555 mlx5_rxq_verify(struct rte_eth_dev *dev)
2557 struct mlx5_priv *priv = dev->data->dev_private;
2558 struct mlx5_rxq_ctrl *rxq_ctrl;
2561 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2562 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2563 dev->data->port_id, rxq_ctrl->rxq.idx);
2570 * Get a Rx queue type.
2573 * Pointer to Ethernet device.
2578 * The Rx queue type.
2581 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2583 struct mlx5_priv *priv = dev->data->dev_private;
2584 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2586 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2587 rxq_ctrl = container_of((*priv->rxqs)[idx],
2588 struct mlx5_rxq_ctrl,
2590 return rxq_ctrl->type;
2592 return MLX5_RXQ_TYPE_UNDEFINED;
2596 * Create an indirection table.
2599 * Pointer to Ethernet device.
2601 * Queues entering in the indirection table.
2603 * Number of queues in the array.
2606 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2608 static struct mlx5_ind_table_obj *
2609 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2610 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2612 struct mlx5_priv *priv = dev->data->dev_private;
2613 struct mlx5_ind_table_obj *ind_tbl;
2614 unsigned int i = 0, j = 0, k = 0;
2616 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) +
2617 queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY);
2622 ind_tbl->type = type;
2623 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2624 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2625 log2above(queues_n) :
2626 log2above(priv->config.ind_table_max_size);
2627 struct ibv_wq *wq[1 << wq_n];
2629 for (i = 0; i != queues_n; ++i) {
2630 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2634 wq[i] = rxq->obj->wq;
2635 ind_tbl->queues[i] = queues[i];
2637 ind_tbl->queues_n = queues_n;
2638 /* Finalise indirection table. */
2639 k = i; /* Retain value of i for use in error case. */
2640 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2642 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2644 &(struct ibv_rwq_ind_table_init_attr){
2645 .log_ind_tbl_size = wq_n,
2649 if (!ind_tbl->ind_table) {
2653 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2654 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2655 const unsigned int rqt_n =
2656 1 << (rte_is_power_of_2(queues_n) ?
2657 log2above(queues_n) :
2658 log2above(priv->config.ind_table_max_size));
2660 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
2661 rqt_n * sizeof(uint32_t), 0,
2664 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2665 dev->data->port_id);
2669 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2670 rqt_attr->rqt_actual_size = rqt_n;
2671 for (i = 0; i != queues_n; ++i) {
2672 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2676 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2677 ind_tbl->queues[i] = queues[i];
2679 k = i; /* Retain value of i for use in error case. */
2680 for (j = 0; k != rqt_n; ++k, ++j)
2681 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2682 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2684 mlx5_free(rqt_attr);
2685 if (!ind_tbl->rqt) {
2686 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2687 dev->data->port_id);
2691 ind_tbl->queues_n = queues_n;
2693 rte_atomic32_inc(&ind_tbl->refcnt);
2694 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2697 for (j = 0; j < i; j++)
2698 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2700 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2705 * Get an indirection table.
2708 * Pointer to Ethernet device.
2710 * Queues entering in the indirection table.
2712 * Number of queues in the array.
2715 * An indirection table if found.
2717 static struct mlx5_ind_table_obj *
2718 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2721 struct mlx5_priv *priv = dev->data->dev_private;
2722 struct mlx5_ind_table_obj *ind_tbl;
2724 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2725 if ((ind_tbl->queues_n == queues_n) &&
2726 (memcmp(ind_tbl->queues, queues,
2727 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2734 rte_atomic32_inc(&ind_tbl->refcnt);
2735 for (i = 0; i != ind_tbl->queues_n; ++i)
2736 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2742 * Release an indirection table.
2745 * Pointer to Ethernet device.
2747 * Indirection table to release.
2750 * 1 while a reference on it exists, 0 when freed.
2753 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2754 struct mlx5_ind_table_obj *ind_tbl)
2758 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2759 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2760 claim_zero(mlx5_glue->destroy_rwq_ind_table
2761 (ind_tbl->ind_table));
2762 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2763 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2765 for (i = 0; i != ind_tbl->queues_n; ++i)
2766 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2767 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2768 LIST_REMOVE(ind_tbl, next);
2776 * Verify the Rx Queue list is empty
2779 * Pointer to Ethernet device.
2782 * The number of object not released.
2785 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2787 struct mlx5_priv *priv = dev->data->dev_private;
2788 struct mlx5_ind_table_obj *ind_tbl;
2791 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2793 "port %u indirection table obj %p still referenced",
2794 dev->data->port_id, (void *)ind_tbl);
2801 * Create an Rx Hash queue.
2804 * Pointer to Ethernet device.
2806 * RSS key for the Rx hash queue.
2807 * @param rss_key_len
2809 * @param hash_fields
2810 * Verbs protocol hash field to make the RSS on.
2812 * Queues entering in hash queue. In case of empty hash_fields only the
2813 * first queue index will be taken for the indirection table.
2820 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
2823 mlx5_hrxq_new(struct rte_eth_dev *dev,
2824 const uint8_t *rss_key, uint32_t rss_key_len,
2825 uint64_t hash_fields,
2826 const uint16_t *queues, uint32_t queues_n,
2827 int tunnel __rte_unused)
2829 struct mlx5_priv *priv = dev->data->dev_private;
2830 struct mlx5_hrxq *hrxq = NULL;
2831 uint32_t hrxq_idx = 0;
2832 struct ibv_qp *qp = NULL;
2833 struct mlx5_ind_table_obj *ind_tbl;
2835 struct mlx5_devx_obj *tir = NULL;
2836 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2837 struct mlx5_rxq_ctrl *rxq_ctrl =
2838 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2840 queues_n = hash_fields ? queues_n : 1;
2841 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2843 enum mlx5_ind_tbl_type type;
2845 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2846 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2847 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2853 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2854 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2855 struct mlx5dv_qp_init_attr qp_init_attr;
2857 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2859 qp_init_attr.comp_mask =
2860 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2861 qp_init_attr.create_flags =
2862 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2864 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2865 if (dev->data->dev_conf.lpbk_mode) {
2867 * Allow packet sent from NIC loop back
2868 * w/o source MAC check.
2870 qp_init_attr.comp_mask |=
2871 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2872 qp_init_attr.create_flags |=
2873 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2876 qp = mlx5_glue->dv_create_qp
2878 &(struct ibv_qp_init_attr_ex){
2879 .qp_type = IBV_QPT_RAW_PACKET,
2881 IBV_QP_INIT_ATTR_PD |
2882 IBV_QP_INIT_ATTR_IND_TABLE |
2883 IBV_QP_INIT_ATTR_RX_HASH,
2884 .rx_hash_conf = (struct ibv_rx_hash_conf){
2886 IBV_RX_HASH_FUNC_TOEPLITZ,
2887 .rx_hash_key_len = rss_key_len,
2889 (void *)(uintptr_t)rss_key,
2890 .rx_hash_fields_mask = hash_fields,
2892 .rwq_ind_tbl = ind_tbl->ind_table,
2897 qp = mlx5_glue->create_qp_ex
2899 &(struct ibv_qp_init_attr_ex){
2900 .qp_type = IBV_QPT_RAW_PACKET,
2902 IBV_QP_INIT_ATTR_PD |
2903 IBV_QP_INIT_ATTR_IND_TABLE |
2904 IBV_QP_INIT_ATTR_RX_HASH,
2905 .rx_hash_conf = (struct ibv_rx_hash_conf){
2907 IBV_RX_HASH_FUNC_TOEPLITZ,
2908 .rx_hash_key_len = rss_key_len,
2910 (void *)(uintptr_t)rss_key,
2911 .rx_hash_fields_mask = hash_fields,
2913 .rwq_ind_tbl = ind_tbl->ind_table,
2921 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2922 struct mlx5_devx_tir_attr tir_attr;
2926 /* Enable TIR LRO only if all the queues were configured for. */
2927 for (i = 0; i < queues_n; ++i) {
2928 if (!(*priv->rxqs)[queues[i]]->lro) {
2933 memset(&tir_attr, 0, sizeof(tir_attr));
2934 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2935 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2936 tir_attr.tunneled_offload_en = !!tunnel;
2937 /* If needed, translate hash_fields bitmap to PRM format. */
2939 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2940 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2941 hash_fields & IBV_RX_HASH_INNER ?
2942 &tir_attr.rx_hash_field_selector_inner :
2943 &tir_attr.rx_hash_field_selector_outer;
2945 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2946 &tir_attr.rx_hash_field_selector_outer;
2949 /* 1 bit: 0: IPv4, 1: IPv6. */
2950 rx_hash_field_select->l3_prot_type =
2951 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2952 /* 1 bit: 0: TCP, 1: UDP. */
2953 rx_hash_field_select->l4_prot_type =
2954 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2955 /* Bitmask which sets which fields to use in RX Hash. */
2956 rx_hash_field_select->selected_fields =
2957 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2958 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2959 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2960 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2961 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2962 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2963 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2964 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2966 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2967 tir_attr.transport_domain = priv->sh->td->id;
2969 tir_attr.transport_domain = priv->sh->tdn;
2970 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2971 MLX5_RSS_HASH_KEY_LEN);
2972 tir_attr.indirect_table = ind_tbl->rqt->id;
2973 if (dev->data->dev_conf.lpbk_mode)
2974 tir_attr.self_lb_block =
2975 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2977 tir_attr.lro_timeout_period_usecs =
2978 priv->config.lro.timeout;
2979 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2980 tir_attr.lro_enable_mask =
2981 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2982 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2984 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2986 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2987 dev->data->port_id);
2992 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2995 hrxq->ind_table = ind_tbl;
2996 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2998 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3000 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
3001 if (!hrxq->action) {
3006 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
3008 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3009 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
3011 if (!hrxq->action) {
3017 hrxq->rss_key_len = rss_key_len;
3018 hrxq->hash_fields = hash_fields;
3019 memcpy(hrxq->rss_key, rss_key, rss_key_len);
3020 rte_atomic32_inc(&hrxq->refcnt);
3021 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
3025 err = rte_errno; /* Save rte_errno before cleanup. */
3026 mlx5_ind_table_obj_release(dev, ind_tbl);
3028 claim_zero(mlx5_glue->destroy_qp(qp));
3030 claim_zero(mlx5_devx_cmd_destroy(tir));
3032 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
3033 rte_errno = err; /* Restore rte_errno. */
3038 * Get an Rx Hash queue.
3041 * Pointer to Ethernet device.
3043 * RSS configuration for the Rx hash queue.
3045 * Queues entering in hash queue. In case of empty hash_fields only the
3046 * first queue index will be taken for the indirection table.
3051 * An hash Rx queue index on success.
3054 mlx5_hrxq_get(struct rte_eth_dev *dev,
3055 const uint8_t *rss_key, uint32_t rss_key_len,
3056 uint64_t hash_fields,
3057 const uint16_t *queues, uint32_t queues_n)
3059 struct mlx5_priv *priv = dev->data->dev_private;
3060 struct mlx5_hrxq *hrxq;
3063 queues_n = hash_fields ? queues_n : 1;
3064 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
3066 struct mlx5_ind_table_obj *ind_tbl;
3068 if (hrxq->rss_key_len != rss_key_len)
3070 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
3072 if (hrxq->hash_fields != hash_fields)
3074 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
3077 if (ind_tbl != hrxq->ind_table) {
3078 mlx5_ind_table_obj_release(dev, ind_tbl);
3081 rte_atomic32_inc(&hrxq->refcnt);
3088 * Release the hash Rx queue.
3091 * Pointer to Ethernet device.
3093 * Index to Hash Rx queue to release.
3096 * 1 while a reference on it exists, 0 when freed.
3099 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
3101 struct mlx5_priv *priv = dev->data->dev_private;
3102 struct mlx5_hrxq *hrxq;
3104 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
3107 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
3108 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3109 mlx5_glue->destroy_flow_action(hrxq->action);
3111 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
3112 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3113 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
3114 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
3115 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
3116 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
3117 hrxq_idx, hrxq, next);
3118 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
3121 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
3126 * Verify the Rx Queue list is empty
3129 * Pointer to Ethernet device.
3132 * The number of object not released.
3135 mlx5_hrxq_verify(struct rte_eth_dev *dev)
3137 struct mlx5_priv *priv = dev->data->dev_private;
3138 struct mlx5_hrxq *hrxq;
3142 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
3145 "port %u hash Rx queue %p still referenced",
3146 dev->data->port_id, (void *)hrxq);
3153 * Create a drop Rx queue Verbs/DevX object.
3156 * Pointer to Ethernet device.
3159 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3161 static struct mlx5_rxq_obj *
3162 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
3164 struct mlx5_priv *priv = dev->data->dev_private;
3165 struct ibv_context *ctx = priv->sh->ctx;
3167 struct ibv_wq *wq = NULL;
3168 struct mlx5_rxq_obj *rxq;
3170 if (priv->drop_queue.rxq)
3171 return priv->drop_queue.rxq;
3172 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
3174 DEBUG("port %u cannot allocate CQ for drop queue",
3175 dev->data->port_id);
3179 wq = mlx5_glue->create_wq(ctx,
3180 &(struct ibv_wq_init_attr){
3181 .wq_type = IBV_WQT_RQ,
3188 DEBUG("port %u cannot allocate WQ for drop queue",
3189 dev->data->port_id);
3193 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
3195 DEBUG("port %u cannot allocate drop Rx queue memory",
3196 dev->data->port_id);
3202 priv->drop_queue.rxq = rxq;
3206 claim_zero(mlx5_glue->destroy_wq(wq));
3208 claim_zero(mlx5_glue->destroy_cq(cq));
3213 * Release a drop Rx queue Verbs/DevX object.
3216 * Pointer to Ethernet device.
3219 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3222 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
3224 struct mlx5_priv *priv = dev->data->dev_private;
3225 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
3228 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
3230 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
3232 priv->drop_queue.rxq = NULL;
3236 * Create a drop indirection table.
3239 * Pointer to Ethernet device.
3242 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3244 static struct mlx5_ind_table_obj *
3245 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
3247 struct mlx5_priv *priv = dev->data->dev_private;
3248 struct mlx5_ind_table_obj *ind_tbl;
3249 struct mlx5_rxq_obj *rxq;
3250 struct mlx5_ind_table_obj tmpl;
3252 rxq = mlx5_rxq_obj_drop_new(dev);
3255 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
3257 &(struct ibv_rwq_ind_table_init_attr){
3258 .log_ind_tbl_size = 0,
3259 .ind_tbl = (struct ibv_wq **)&rxq->wq,
3262 if (!tmpl.ind_table) {
3263 DEBUG("port %u cannot allocate indirection table for drop"
3265 dev->data->port_id);
3269 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl), 0,
3275 ind_tbl->ind_table = tmpl.ind_table;
3278 mlx5_rxq_obj_drop_release(dev);
3283 * Release a drop indirection table.
3286 * Pointer to Ethernet device.
3289 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
3291 struct mlx5_priv *priv = dev->data->dev_private;
3292 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
3294 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
3295 mlx5_rxq_obj_drop_release(dev);
3297 priv->drop_queue.hrxq->ind_table = NULL;
3301 * Create a drop Rx Hash queue.
3304 * Pointer to Ethernet device.
3307 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3310 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
3312 struct mlx5_priv *priv = dev->data->dev_private;
3313 struct mlx5_ind_table_obj *ind_tbl = NULL;
3314 struct ibv_qp *qp = NULL;
3315 struct mlx5_hrxq *hrxq = NULL;
3317 if (priv->drop_queue.hrxq) {
3318 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
3319 return priv->drop_queue.hrxq;
3321 hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);
3324 "port %u cannot allocate memory for drop queue",
3325 dev->data->port_id);
3329 priv->drop_queue.hrxq = hrxq;
3330 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
3333 hrxq->ind_table = ind_tbl;
3334 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
3335 &(struct ibv_qp_init_attr_ex){
3336 .qp_type = IBV_QPT_RAW_PACKET,
3338 IBV_QP_INIT_ATTR_PD |
3339 IBV_QP_INIT_ATTR_IND_TABLE |
3340 IBV_QP_INIT_ATTR_RX_HASH,
3341 .rx_hash_conf = (struct ibv_rx_hash_conf){
3343 IBV_RX_HASH_FUNC_TOEPLITZ,
3344 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
3345 .rx_hash_key = rss_hash_default_key,
3346 .rx_hash_fields_mask = 0,
3348 .rwq_ind_tbl = ind_tbl->ind_table,
3352 DEBUG("port %u cannot allocate QP for drop queue",
3353 dev->data->port_id);
3358 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3359 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
3360 if (!hrxq->action) {
3365 rte_atomic32_set(&hrxq->refcnt, 1);
3368 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3369 if (hrxq && hrxq->action)
3370 mlx5_glue->destroy_flow_action(hrxq->action);
3373 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3375 mlx5_ind_table_obj_drop_release(dev);
3377 priv->drop_queue.hrxq = NULL;
3384 * Release a drop hash Rx queue.
3387 * Pointer to Ethernet device.
3390 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
3392 struct mlx5_priv *priv = dev->data->dev_private;
3393 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
3395 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
3396 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3397 mlx5_glue->destroy_flow_action(hrxq->action);
3399 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3400 mlx5_ind_table_obj_drop_release(dev);
3402 priv->drop_queue.hrxq = NULL;
3408 * Set the Rx queue timestamp conversion parameters
3411 * Pointer to the Ethernet device structure.
3414 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
3416 struct mlx5_priv *priv = dev->data->dev_private;
3417 struct mlx5_dev_ctx_shared *sh = priv->sh;
3418 struct mlx5_rxq_data *data;
3421 for (i = 0; i != priv->rxqs_n; ++i) {
3422 if (!(*priv->rxqs)[i])
3424 data = (*priv->rxqs)[i];
3426 data->rt_timestamp = priv->config.rt_timestamp;