drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 const size_t rss_hash_default_key_len = sizeof(rss_hash_default_key);
  56
  57 /**
  58  * Check whether Multi-Packet RQ can be enabled for the device.
  59  *
  60  * @param dev
  61  *   Pointer to Ethernet device.
  62  *
  63  * @return
  64  *   1 if supported, negative errno value if not.
  65  */
  66 inline int
  67 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  68 {
  69         struct priv *priv = dev->data->dev_private;
  70
  71         if (priv->config.mprq.enabled &&
  72             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  73                 return 1;
  74         return -ENOTSUP;
  75 }
  76
  77 /**
  78  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  79  *
  80  *  @param rxq
  81  *     Pointer to receive queue structure.
  82  *
  83  * @return
  84  *   0 if disabled, otherwise enabled.
  85  */
  86 inline int
  87 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  88 {
  89         return rxq->strd_num_n > 0;
  90 }
  91
  92 /**
  93  * Check whether Multi-Packet RQ is enabled for the device.
  94  *
  95  * @param dev
  96  *   Pointer to Ethernet device.
  97  *
  98  * @return
  99  *   0 if disabled, otherwise enabled.
 100  */
 101 inline int
 102 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 103 {
 104         struct priv *priv = dev->data->dev_private;
 105         uint16_t i;
 106         uint16_t n = 0;
 107
 108         if (mlx5_check_mprq_support(dev) < 0)
 109                 return 0;
 110         /* All the configured queues should be enabled. */
 111         for (i = 0; i < priv->rxqs_n; ++i) {
 112                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 113
 114                 if (!rxq)
 115                         continue;
 116                 if (mlx5_rxq_mprq_enabled(rxq))
 117                         ++n;
 118         }
 119         /* Multi-Packet RQ can't be partially configured. */
 120         assert(n == 0 || n == priv->rxqs_n);
 121         return n == priv->rxqs_n;
 122 }
 123
 124 /**
 125  * Allocate RX queue elements for Multi-Packet RQ.
 126  *
 127  * @param rxq_ctrl
 128  *   Pointer to RX queue structure.
 129  *
 130  * @return
 131  *   0 on success, a negative errno value otherwise and rte_errno is set.
 132  */
 133 static int
 134 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 135 {
 136         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 137         unsigned int wqe_n = 1 << rxq->elts_n;
 138         unsigned int i;
 139         int err;
 140
 141         /* Iterate on segments. */
 142         for (i = 0; i <= wqe_n; ++i) {
 143                 struct mlx5_mprq_buf *buf;
 144
 145                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 146                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 147                         rte_errno = ENOMEM;
 148                         goto error;
 149                 }
 150                 if (i < wqe_n)
 151                         (*rxq->mprq_bufs)[i] = buf;
 152                 else
 153                         rxq->mprq_repl = buf;
 154         }
 155         DRV_LOG(DEBUG,
 156                 "port %u Rx queue %u allocated and configured %u segments",
 157                 rxq->port_id, rxq_ctrl->idx, wqe_n);
 158         return 0;
 159 error:
 160         err = rte_errno; /* Save rte_errno before cleanup. */
 161         wqe_n = i;
 162         for (i = 0; (i != wqe_n); ++i) {
 163                 if ((*rxq->elts)[i] != NULL)
 164                         rte_mempool_put(rxq->mprq_mp,
 165                                         (*rxq->mprq_bufs)[i]);
 166                 (*rxq->mprq_bufs)[i] = NULL;
 167         }
 168         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 169                 rxq->port_id, rxq_ctrl->idx);
 170         rte_errno = err; /* Restore rte_errno. */
 171         return -rte_errno;
 172 }
 173
 174 /**
 175  * Allocate RX queue elements for Single-Packet RQ.
 176  *
 177  * @param rxq_ctrl
 178  *   Pointer to RX queue structure.
 179  *
 180  * @return
 181  *   0 on success, errno value on failure.
 182  */
 183 static int
 184 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 185 {
 186         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 187         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 188         unsigned int i;
 189         int err;
 190
 191         /* Iterate on segments. */
 192         for (i = 0; (i != elts_n); ++i) {
 193                 struct rte_mbuf *buf;
 194
 195                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 196                 if (buf == NULL) {
 197                         DRV_LOG(ERR, "port %u empty mbuf pool",
 198                                 PORT_ID(rxq_ctrl->priv));
 199                         rte_errno = ENOMEM;
 200                         goto error;
 201                 }
 202                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 203                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 204                 /* Buffer is supposed to be empty. */
 205                 assert(rte_pktmbuf_data_len(buf) == 0);
 206                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 207                 assert(!buf->next);
 208                 /* Only the first segment keeps headroom. */
 209                 if (i % sges_n)
 210                         SET_DATA_OFF(buf, 0);
 211                 PORT(buf) = rxq_ctrl->rxq.port_id;
 212                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 213                 PKT_LEN(buf) = DATA_LEN(buf);
 214                 NB_SEGS(buf) = 1;
 215                 (*rxq_ctrl->rxq.elts)[i] = buf;
 216         }
 217         /* If Rx vector is activated. */
 218         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 219                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 220                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 221                 int j;
 222
 223                 /* Initialize default rearm_data for vPMD. */
 224                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 225                 rte_mbuf_refcnt_set(mbuf_init, 1);
 226                 mbuf_init->nb_segs = 1;
 227                 mbuf_init->port = rxq->port_id;
 228                 /*
 229                  * prevent compiler reordering:
 230                  * rearm_data covers previous fields.
 231                  */
 232                 rte_compiler_barrier();
 233                 rxq->mbuf_initializer =
 234                         *(uint64_t *)&mbuf_init->rearm_data;
 235                 /* Padding with a fake mbuf for vectorized Rx. */
 236                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 237                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 238         }
 239         DRV_LOG(DEBUG,
 240                 "port %u Rx queue %u allocated and configured %u segments"
 241                 " (max %u packets)",
 242                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx, elts_n,
 243                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 244         return 0;
 245 error:
 246         err = rte_errno; /* Save rte_errno before cleanup. */
 247         elts_n = i;
 248         for (i = 0; (i != elts_n); ++i) {
 249                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 250                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 251                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 252         }
 253         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 254                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
 255         rte_errno = err; /* Restore rte_errno. */
 256         return -rte_errno;
 257 }
 258
 259 /**
 260  * Allocate RX queue elements.
 261  *
 262  * @param rxq_ctrl
 263  *   Pointer to RX queue structure.
 264  *
 265  * @return
 266  *   0 on success, errno value on failure.
 267  */
 268 int
 269 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 270 {
 271         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 272                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 273 }
 274
 275 /**
 276  * Free RX queue elements for Multi-Packet RQ.
 277  *
 278  * @param rxq_ctrl
 279  *   Pointer to RX queue structure.
 280  */
 281 static void
 282 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 283 {
 284         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 285         uint16_t i;
 286
 287         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 288                 rxq->port_id, rxq_ctrl->idx);
 289         if (rxq->mprq_bufs == NULL)
 290                 return;
 291         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 292         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 293                 if ((*rxq->mprq_bufs)[i] != NULL)
 294                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 295                 (*rxq->mprq_bufs)[i] = NULL;
 296         }
 297         if (rxq->mprq_repl != NULL) {
 298                 mlx5_mprq_buf_free(rxq->mprq_repl);
 299                 rxq->mprq_repl = NULL;
 300         }
 301 }
 302
 303 /**
 304  * Free RX queue elements for Single-Packet RQ.
 305  *
 306  * @param rxq_ctrl
 307  *   Pointer to RX queue structure.
 308  */
 309 static void
 310 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 311 {
 312         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 313         const uint16_t q_n = (1 << rxq->elts_n);
 314         const uint16_t q_mask = q_n - 1;
 315         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 316         uint16_t i;
 317
 318         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 319                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
 320         if (rxq->elts == NULL)
 321                 return;
 322         /**
 323          * Some mbuf in the Ring belongs to the application.  They cannot be
 324          * freed.
 325          */
 326         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 327                 for (i = 0; i < used; ++i)
 328                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 329                 rxq->rq_pi = rxq->rq_ci;
 330         }
 331         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 332                 if ((*rxq->elts)[i] != NULL)
 333                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 334                 (*rxq->elts)[i] = NULL;
 335         }
 336 }
 337
 338 /**
 339  * Free RX queue elements.
 340  *
 341  * @param rxq_ctrl
 342  *   Pointer to RX queue structure.
 343  */
 344 static void
 345 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 346 {
 347         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 348                 rxq_free_elts_mprq(rxq_ctrl);
 349         else
 350                 rxq_free_elts_sprq(rxq_ctrl);
 351 }
 352
 353 /**
 354  * Clean up a RX queue.
 355  *
 356  * Destroy objects, free allocated memory and reset the structure for reuse.
 357  *
 358  * @param rxq_ctrl
 359  *   Pointer to RX queue structure.
 360  */
 361 void
 362 mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl)
 363 {
 364         DRV_LOG(DEBUG, "port %u cleaning up Rx queue %u",
 365                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
 366         if (rxq_ctrl->ibv)
 367                 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
 368         memset(rxq_ctrl, 0, sizeof(*rxq_ctrl));
 369 }
 370
 371 /**
 372  * Returns the per-queue supported offloads.
 373  *
 374  * @param dev
 375  *   Pointer to Ethernet device.
 376  *
 377  * @return
 378  *   Supported Rx offloads.
 379  */
 380 uint64_t
 381 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 382 {
 383         struct priv *priv = dev->data->dev_private;
 384         struct mlx5_dev_config *config = &priv->config;
 385         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 386                              DEV_RX_OFFLOAD_TIMESTAMP |
 387                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 388
 389         if (config->hw_fcs_strip)
 390                 offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
 391         if (config->hw_csum)
 392                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 393                              DEV_RX_OFFLOAD_UDP_CKSUM |
 394                              DEV_RX_OFFLOAD_TCP_CKSUM);
 395         if (config->hw_vlan_strip)
 396                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 397         return offloads;
 398 }
 399
 400
 401 /**
 402  * Returns the per-port supported offloads.
 403  *
 404  * @return
 405  *   Supported Rx offloads.
 406  */
 407 uint64_t
 408 mlx5_get_rx_port_offloads(void)
 409 {
 410         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 411
 412         return offloads;
 413 }
 414
 415 /**
 416  *
 417  * @param dev
 418  *   Pointer to Ethernet device structure.
 419  * @param idx
 420  *   RX queue index.
 421  * @param desc
 422  *   Number of descriptors to configure in queue.
 423  * @param socket
 424  *   NUMA socket on which memory must be allocated.
 425  * @param[in] conf
 426  *   Thresholds parameters.
 427  * @param mp
 428  *   Memory pool for buffer allocations.
 429  *
 430  * @return
 431  *   0 on success, a negative errno value otherwise and rte_errno is set.
 432  */
 433 int
 434 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 435                     unsigned int socket, const struct rte_eth_rxconf *conf,
 436                     struct rte_mempool *mp)
 437 {
 438         struct priv *priv = dev->data->dev_private;
 439         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 440         struct mlx5_rxq_ctrl *rxq_ctrl =
 441                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 442
 443         if (!rte_is_power_of_2(desc)) {
 444                 desc = 1 << log2above(desc);
 445                 DRV_LOG(WARNING,
 446                         "port %u increased number of descriptors in Rx queue %u"
 447                         " to the next power of two (%d)",
 448                         dev->data->port_id, idx, desc);
 449         }
 450         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 451                 dev->data->port_id, idx, desc);
 452         if (idx >= priv->rxqs_n) {
 453                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 454                         dev->data->port_id, idx, priv->rxqs_n);
 455                 rte_errno = EOVERFLOW;
 456                 return -rte_errno;
 457         }
 458         if (!mlx5_rxq_releasable(dev, idx)) {
 459                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 460                         dev->data->port_id, idx);
 461                 rte_errno = EBUSY;
 462                 return -rte_errno;
 463         }
 464         mlx5_rxq_release(dev, idx);
 465         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 466         if (!rxq_ctrl) {
 467                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 468                         dev->data->port_id, idx);
 469                 rte_errno = ENOMEM;
 470                 return -rte_errno;
 471         }
 472         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 473                 dev->data->port_id, idx);
 474         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 475         return 0;
 476 }
 477
 478 /**
 479  * DPDK callback to release a RX queue.
 480  *
 481  * @param dpdk_rxq
 482  *   Generic RX queue pointer.
 483  */
 484 void
 485 mlx5_rx_queue_release(void *dpdk_rxq)
 486 {
 487         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 488         struct mlx5_rxq_ctrl *rxq_ctrl;
 489         struct priv *priv;
 490
 491         if (rxq == NULL)
 492                 return;
 493         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 494         priv = rxq_ctrl->priv;
 495         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.stats.idx))
 496                 rte_panic("port %u Rx queue %u is still used by a flow and"
 497                           " cannot be removed\n",
 498                           PORT_ID(priv), rxq_ctrl->idx);
 499         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.stats.idx);
 500 }
 501
 502 /**
 503  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 504  *
 505  * @param dev
 506  *   Pointer to Ethernet device.
 507  *
 508  * @return
 509  *   0 on success, a negative errno value otherwise and rte_errno is set.
 510  */
 511 int
 512 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 513 {
 514         struct priv *priv = dev->data->dev_private;
 515         unsigned int i;
 516         unsigned int rxqs_n = priv->rxqs_n;
 517         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 518         unsigned int count = 0;
 519         struct rte_intr_handle *intr_handle = dev->intr_handle;
 520
 521         if (!dev->data->dev_conf.intr_conf.rxq)
 522                 return 0;
 523         mlx5_rx_intr_vec_disable(dev);
 524         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 525         if (intr_handle->intr_vec == NULL) {
 526                 DRV_LOG(ERR,
 527                         "port %u failed to allocate memory for interrupt"
 528                         " vector, Rx interrupts will not be supported",
 529                         dev->data->port_id);
 530                 rte_errno = ENOMEM;
 531                 return -rte_errno;
 532         }
 533         intr_handle->type = RTE_INTR_HANDLE_EXT;
 534         for (i = 0; i != n; ++i) {
 535                 /* This rxq ibv must not be released in this function. */
 536                 struct mlx5_rxq_ibv *rxq_ibv = mlx5_rxq_ibv_get(dev, i);
 537                 int fd;
 538                 int flags;
 539                 int rc;
 540
 541                 /* Skip queues that cannot request interrupts. */
 542                 if (!rxq_ibv || !rxq_ibv->channel) {
 543                         /* Use invalid intr_vec[] index to disable entry. */
 544                         intr_handle->intr_vec[i] =
 545                                 RTE_INTR_VEC_RXTX_OFFSET +
 546                                 RTE_MAX_RXTX_INTR_VEC_ID;
 547                         continue;
 548                 }
 549                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 550                         DRV_LOG(ERR,
 551                                 "port %u too many Rx queues for interrupt"
 552                                 " vector size (%d), Rx interrupts cannot be"
 553                                 " enabled",
 554                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 555                         mlx5_rx_intr_vec_disable(dev);
 556                         rte_errno = ENOMEM;
 557                         return -rte_errno;
 558                 }
 559                 fd = rxq_ibv->channel->fd;
 560                 flags = fcntl(fd, F_GETFL);
 561                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 562                 if (rc < 0) {
 563                         rte_errno = errno;
 564                         DRV_LOG(ERR,
 565                                 "port %u failed to make Rx interrupt file"
 566                                 " descriptor %d non-blocking for queue index"
 567                                 " %d",
 568                                 dev->data->port_id, fd, i);
 569                         mlx5_rx_intr_vec_disable(dev);
 570                         return -rte_errno;
 571                 }
 572                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 573                 intr_handle->efds[count] = fd;
 574                 count++;
 575         }
 576         if (!count)
 577                 mlx5_rx_intr_vec_disable(dev);
 578         else
 579                 intr_handle->nb_efd = count;
 580         return 0;
 581 }
 582
 583 /**
 584  * Clean up Rx interrupts handler.
 585  *
 586  * @param dev
 587  *   Pointer to Ethernet device.
 588  */
 589 void
 590 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 591 {
 592         struct priv *priv = dev->data->dev_private;
 593         struct rte_intr_handle *intr_handle = dev->intr_handle;
 594         unsigned int i;
 595         unsigned int rxqs_n = priv->rxqs_n;
 596         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 597
 598         if (!dev->data->dev_conf.intr_conf.rxq)
 599                 return;
 600         if (!intr_handle->intr_vec)
 601                 goto free;
 602         for (i = 0; i != n; ++i) {
 603                 struct mlx5_rxq_ctrl *rxq_ctrl;
 604                 struct mlx5_rxq_data *rxq_data;
 605
 606                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 607                     RTE_MAX_RXTX_INTR_VEC_ID)
 608                         continue;
 609                 /**
 610                  * Need to access directly the queue to release the reference
 611                  * kept in priv_rx_intr_vec_enable().
 612                  */
 613                 rxq_data = (*priv->rxqs)[i];
 614                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 615                 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
 616         }
 617 free:
 618         rte_intr_free_epoll_fd(intr_handle);
 619         if (intr_handle->intr_vec)
 620                 free(intr_handle->intr_vec);
 621         intr_handle->nb_efd = 0;
 622         intr_handle->intr_vec = NULL;
 623 }
 624
 625 /**
 626  *  MLX5 CQ notification .
 627  *
 628  *  @param rxq
 629  *     Pointer to receive queue structure.
 630  *  @param sq_n_rxq
 631  *     Sequence number per receive queue .
 632  */
 633 static inline void
 634 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 635 {
 636         int sq_n = 0;
 637         uint32_t doorbell_hi;
 638         uint64_t doorbell;
 639         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 640
 641         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 642         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 643         doorbell = (uint64_t)doorbell_hi << 32;
 644         doorbell |=  rxq->cqn;
 645         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 646         rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);
 647 }
 648
 649 /**
 650  * DPDK callback for Rx queue interrupt enable.
 651  *
 652  * @param dev
 653  *   Pointer to Ethernet device structure.
 654  * @param rx_queue_id
 655  *   Rx queue number.
 656  *
 657  * @return
 658  *   0 on success, a negative errno value otherwise and rte_errno is set.
 659  */
 660 int
 661 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 662 {
 663         struct priv *priv = dev->data->dev_private;
 664         struct mlx5_rxq_data *rxq_data;
 665         struct mlx5_rxq_ctrl *rxq_ctrl;
 666
 667         rxq_data = (*priv->rxqs)[rx_queue_id];
 668         if (!rxq_data) {
 669                 rte_errno = EINVAL;
 670                 return -rte_errno;
 671         }
 672         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 673         if (rxq_ctrl->irq) {
 674                 struct mlx5_rxq_ibv *rxq_ibv;
 675
 676                 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 677                 if (!rxq_ibv) {
 678                         rte_errno = EINVAL;
 679                         return -rte_errno;
 680                 }
 681                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 682                 mlx5_rxq_ibv_release(rxq_ibv);
 683         }
 684         return 0;
 685 }
 686
 687 /**
 688  * DPDK callback for Rx queue interrupt disable.
 689  *
 690  * @param dev
 691  *   Pointer to Ethernet device structure.
 692  * @param rx_queue_id
 693  *   Rx queue number.
 694  *
 695  * @return
 696  *   0 on success, a negative errno value otherwise and rte_errno is set.
 697  */
 698 int
 699 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 700 {
 701         struct priv *priv = dev->data->dev_private;
 702         struct mlx5_rxq_data *rxq_data;
 703         struct mlx5_rxq_ctrl *rxq_ctrl;
 704         struct mlx5_rxq_ibv *rxq_ibv = NULL;
 705         struct ibv_cq *ev_cq;
 706         void *ev_ctx;
 707         int ret;
 708
 709         rxq_data = (*priv->rxqs)[rx_queue_id];
 710         if (!rxq_data) {
 711                 rte_errno = EINVAL;
 712                 return -rte_errno;
 713         }
 714         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 715         if (!rxq_ctrl->irq)
 716                 return 0;
 717         rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 718         if (!rxq_ibv) {
 719                 rte_errno = EINVAL;
 720                 return -rte_errno;
 721         }
 722         ret = mlx5_glue->get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
 723         if (ret || ev_cq != rxq_ibv->cq) {
 724                 rte_errno = EINVAL;
 725                 goto exit;
 726         }
 727         rxq_data->cq_arm_sn++;
 728         mlx5_glue->ack_cq_events(rxq_ibv->cq, 1);
 729         return 0;
 730 exit:
 731         ret = rte_errno; /* Save rte_errno before cleanup. */
 732         if (rxq_ibv)
 733                 mlx5_rxq_ibv_release(rxq_ibv);
 734         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 735                 dev->data->port_id, rx_queue_id);
 736         rte_errno = ret; /* Restore rte_errno. */
 737         return -rte_errno;
 738 }
 739
 740 /**
 741  * Create the Rx queue Verbs object.
 742  *
 743  * @param dev
 744  *   Pointer to Ethernet device.
 745  * @param idx
 746  *   Queue index in DPDK Rx queue array
 747  *
 748  * @return
 749  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 750  */
 751 struct mlx5_rxq_ibv *
 752 mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
 753 {
 754         struct priv *priv = dev->data->dev_private;
 755         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 756         struct mlx5_rxq_ctrl *rxq_ctrl =
 757                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 758         struct ibv_wq_attr mod;
 759         union {
 760                 struct {
 761                         struct ibv_cq_init_attr_ex ibv;
 762                         struct mlx5dv_cq_init_attr mlx5;
 763                 } cq;
 764                 struct {
 765                         struct ibv_wq_init_attr ibv;
 766 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 767                         struct mlx5dv_wq_init_attr mlx5;
 768 #endif
 769                 } wq;
 770                 struct ibv_cq_ex cq_attr;
 771         } attr;
 772         unsigned int cqe_n;
 773         unsigned int wqe_n = 1 << rxq_data->elts_n;
 774         struct mlx5_rxq_ibv *tmpl;
 775         struct mlx5dv_cq cq_info;
 776         struct mlx5dv_rwq rwq;
 777         unsigned int i;
 778         int ret = 0;
 779         struct mlx5dv_obj obj;
 780         struct mlx5_dev_config *config = &priv->config;
 781         const int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);
 782
 783         assert(rxq_data);
 784         assert(!rxq_ctrl->ibv);
 785         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
 786         priv->verbs_alloc_ctx.obj = rxq_ctrl;
 787         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
 788                                  rxq_ctrl->socket);
 789         if (!tmpl) {
 790                 DRV_LOG(ERR,
 791                         "port %u Rx queue %u cannot allocate verbs resources",
 792                         dev->data->port_id, rxq_ctrl->idx);
 793                 rte_errno = ENOMEM;
 794                 goto error;
 795         }
 796         tmpl->rxq_ctrl = rxq_ctrl;
 797         if (rxq_ctrl->irq) {
 798                 tmpl->channel = mlx5_glue->create_comp_channel(priv->ctx);
 799                 if (!tmpl->channel) {
 800                         DRV_LOG(ERR, "port %u: comp channel creation failure",
 801                                 dev->data->port_id);
 802                         rte_errno = ENOMEM;
 803                         goto error;
 804                 }
 805         }
 806         if (mprq_en)
 807                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
 808         else
 809                 cqe_n = wqe_n  - 1;
 810         attr.cq.ibv = (struct ibv_cq_init_attr_ex){
 811                 .cqe = cqe_n,
 812                 .channel = tmpl->channel,
 813                 .comp_mask = 0,
 814         };
 815         attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
 816                 .comp_mask = 0,
 817         };
 818         if (config->cqe_comp && !rxq_data->hw_timestamp) {
 819                 attr.cq.mlx5.comp_mask |=
 820                         MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 821                 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 822                 /*
 823                  * For vectorized Rx, it must not be doubled in order to
 824                  * make cq_ci and rq_ci aligned.
 825                  */
 826                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 827                         attr.cq.ibv.cqe *= 2;
 828         } else if (config->cqe_comp && rxq_data->hw_timestamp) {
 829                 DRV_LOG(DEBUG,
 830                         "port %u Rx CQE compression is disabled for HW"
 831                         " timestamp",
 832                         dev->data->port_id);
 833         }
 834         tmpl->cq = mlx5_glue->cq_ex_to_cq
 835                 (mlx5_glue->dv_create_cq(priv->ctx, &attr.cq.ibv,
 836                                          &attr.cq.mlx5));
 837         if (tmpl->cq == NULL) {
 838                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
 839                         dev->data->port_id, idx);
 840                 rte_errno = ENOMEM;
 841                 goto error;
 842         }
 843         DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d",
 844                 dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr);
 845         DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d",
 846                 dev->data->port_id, priv->device_attr.orig_attr.max_sge);
 847         attr.wq.ibv = (struct ibv_wq_init_attr){
 848                 .wq_context = NULL, /* Could be useful in the future. */
 849                 .wq_type = IBV_WQT_RQ,
 850                 /* Max number of outstanding WRs. */
 851                 .max_wr = wqe_n >> rxq_data->sges_n,
 852                 /* Max number of scatter/gather elements in a WR. */
 853                 .max_sge = 1 << rxq_data->sges_n,
 854                 .pd = priv->pd,
 855                 .cq = tmpl->cq,
 856                 .comp_mask =
 857                         IBV_WQ_FLAGS_CVLAN_STRIPPING |
 858                         0,
 859                 .create_flags = (rxq_data->vlan_strip ?
 860                                  IBV_WQ_FLAGS_CVLAN_STRIPPING :
 861                                  0),
 862         };
 863         /* By default, FCS (CRC) is stripped by hardware. */
 864         if (rxq_data->crc_present) {
 865                 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 866                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 867         }
 868 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 869         if (config->hw_padding) {
 870                 attr.wq.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 871                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 872         }
 873 #endif
 874 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 875         attr.wq.mlx5 = (struct mlx5dv_wq_init_attr){
 876                 .comp_mask = 0,
 877         };
 878         if (mprq_en) {
 879                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
 880                         &attr.wq.mlx5.striding_rq_attrs;
 881
 882                 attr.wq.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
 883                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
 884                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
 885                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
 886                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
 887                 };
 888         }
 889         tmpl->wq = mlx5_glue->dv_create_wq(priv->ctx, &attr.wq.ibv,
 890                                            &attr.wq.mlx5);
 891 #else
 892         tmpl->wq = mlx5_glue->create_wq(priv->ctx, &attr.wq.ibv);
 893 #endif
 894         if (tmpl->wq == NULL) {
 895                 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
 896                         dev->data->port_id, idx);
 897                 rte_errno = ENOMEM;
 898                 goto error;
 899         }
 900         /*
 901          * Make sure number of WRs*SGEs match expectations since a queue
 902          * cannot allocate more than "desc" buffers.
 903          */
 904         if (attr.wq.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
 905             attr.wq.ibv.max_sge != (1u << rxq_data->sges_n)) {
 906                 DRV_LOG(ERR,
 907                         "port %u Rx queue %u requested %u*%u but got %u*%u"
 908                         " WRs*SGEs",
 909                         dev->data->port_id, idx,
 910                         wqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),
 911                         attr.wq.ibv.max_wr, attr.wq.ibv.max_sge);
 912                 rte_errno = EINVAL;
 913                 goto error;
 914         }
 915         /* Change queue state to ready. */
 916         mod = (struct ibv_wq_attr){
 917                 .attr_mask = IBV_WQ_ATTR_STATE,
 918                 .wq_state = IBV_WQS_RDY,
 919         };
 920         ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
 921         if (ret) {
 922                 DRV_LOG(ERR,
 923                         "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
 924                         dev->data->port_id, idx);
 925                 rte_errno = ret;
 926                 goto error;
 927         }
 928         obj.cq.in = tmpl->cq;
 929         obj.cq.out = &cq_info;
 930         obj.rwq.in = tmpl->wq;
 931         obj.rwq.out = &rwq;
 932         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
 933         if (ret) {
 934                 rte_errno = ret;
 935                 goto error;
 936         }
 937         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
 938                 DRV_LOG(ERR,
 939                         "port %u wrong MLX5_CQE_SIZE environment variable"
 940                         " value: it should be set to %u",
 941                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
 942                 rte_errno = EINVAL;
 943                 goto error;
 944         }
 945         /* Fill the rings. */
 946         rxq_data->wqes = rwq.buf;
 947         for (i = 0; (i != wqe_n); ++i) {
 948                 volatile struct mlx5_wqe_data_seg *scat;
 949                 uintptr_t addr;
 950                 uint32_t byte_count;
 951
 952                 if (mprq_en) {
 953                         struct mlx5_mprq_buf *buf = (*rxq_data->mprq_bufs)[i];
 954
 955                         scat = &((volatile struct mlx5_wqe_mprq *)
 956                                  rxq_data->wqes)[i].dseg;
 957                         addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
 958                         byte_count = (1 << rxq_data->strd_sz_n) *
 959                                      (1 << rxq_data->strd_num_n);
 960                 } else {
 961                         struct rte_mbuf *buf = (*rxq_data->elts)[i];
 962
 963                         scat = &((volatile struct mlx5_wqe_data_seg *)
 964                                  rxq_data->wqes)[i];
 965                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 966                         byte_count = DATA_LEN(buf);
 967                 }
 968                 /* scat->addr must be able to store a pointer. */
 969                 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
 970                 *scat = (struct mlx5_wqe_data_seg){
 971                         .addr = rte_cpu_to_be_64(addr),
 972                         .byte_count = rte_cpu_to_be_32(byte_count),
 973                         .lkey = mlx5_rx_addr2mr(rxq_data, addr),
 974                 };
 975         }
 976         rxq_data->rq_db = rwq.dbrec;
 977         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
 978         rxq_data->cq_ci = 0;
 979         rxq_data->strd_ci = 0;
 980         rxq_data->rq_pi = 0;
 981         rxq_data->zip = (struct rxq_zip){
 982                 .ai = 0,
 983         };
 984         rxq_data->cq_db = cq_info.dbrec;
 985         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
 986         rxq_data->cq_uar = cq_info.cq_uar;
 987         rxq_data->cqn = cq_info.cqn;
 988         rxq_data->cq_arm_sn = 0;
 989         /* Update doorbell counter. */
 990         rxq_data->rq_ci = wqe_n >> rxq_data->sges_n;
 991         rte_wmb();
 992         *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
 993         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
 994                 idx, (void *)&tmpl);
 995         rte_atomic32_inc(&tmpl->refcnt);
 996         DRV_LOG(DEBUG, "port %u Verbs Rx queue %u: refcnt %d",
 997                 dev->data->port_id, idx, rte_atomic32_read(&tmpl->refcnt));
 998         LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
 999         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1000         return tmpl;
1001 error:
1002         ret = rte_errno; /* Save rte_errno before cleanup. */
1003         if (tmpl->wq)
1004                 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1005         if (tmpl->cq)
1006                 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1007         if (tmpl->channel)
1008                 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->channel));
1009         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1010         rte_errno = ret; /* Restore rte_errno. */
1011         return NULL;
1012 }
1013
1014 /**
1015  * Get an Rx queue Verbs object.
1016  *
1017  * @param dev
1018  *   Pointer to Ethernet device.
1019  * @param idx
1020  *   Queue index in DPDK Rx queue array
1021  *
1022  * @return
1023  *   The Verbs object if it exists.
1024  */
1025 struct mlx5_rxq_ibv *
1026 mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
1027 {
1028         struct priv *priv = dev->data->dev_private;
1029         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1030         struct mlx5_rxq_ctrl *rxq_ctrl;
1031
1032         if (idx >= priv->rxqs_n)
1033                 return NULL;
1034         if (!rxq_data)
1035                 return NULL;
1036         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1037         if (rxq_ctrl->ibv) {
1038                 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
1039                 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u: refcnt %d",
1040                         dev->data->port_id, rxq_ctrl->idx,
1041                         rte_atomic32_read(&rxq_ctrl->ibv->refcnt));
1042         }
1043         return rxq_ctrl->ibv;
1044 }
1045
1046 /**
1047  * Release an Rx verbs queue object.
1048  *
1049  * @param rxq_ibv
1050  *   Verbs Rx queue object.
1051  *
1052  * @return
1053  *   1 while a reference on it exists, 0 when freed.
1054  */
1055 int
1056 mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv)
1057 {
1058         assert(rxq_ibv);
1059         assert(rxq_ibv->wq);
1060         assert(rxq_ibv->cq);
1061         DRV_LOG(DEBUG, "port %u Verbs Rx queue %u: refcnt %d",
1062                 PORT_ID(rxq_ibv->rxq_ctrl->priv),
1063                 rxq_ibv->rxq_ctrl->idx, rte_atomic32_read(&rxq_ibv->refcnt));
1064         if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
1065                 rxq_free_elts(rxq_ibv->rxq_ctrl);
1066                 claim_zero(mlx5_glue->destroy_wq(rxq_ibv->wq));
1067                 claim_zero(mlx5_glue->destroy_cq(rxq_ibv->cq));
1068                 if (rxq_ibv->channel)
1069                         claim_zero(mlx5_glue->destroy_comp_channel
1070                                    (rxq_ibv->channel));
1071                 LIST_REMOVE(rxq_ibv, next);
1072                 rte_free(rxq_ibv);
1073                 return 0;
1074         }
1075         return 1;
1076 }
1077
1078 /**
1079  * Verify the Verbs Rx queue list is empty
1080  *
1081  * @param dev
1082  *   Pointer to Ethernet device.
1083  *
1084  * @return
1085  *   The number of object not released.
1086  */
1087 int
1088 mlx5_rxq_ibv_verify(struct rte_eth_dev *dev)
1089 {
1090         struct priv *priv = dev->data->dev_private;
1091         int ret = 0;
1092         struct mlx5_rxq_ibv *rxq_ibv;
1093
1094         LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
1095                 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u still referenced",
1096                         dev->data->port_id, rxq_ibv->rxq_ctrl->idx);
1097                 ++ret;
1098         }
1099         return ret;
1100 }
1101
1102 /**
1103  * Return true if a single reference exists on the object.
1104  *
1105  * @param rxq_ibv
1106  *   Verbs Rx queue object.
1107  */
1108 int
1109 mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv)
1110 {
1111         assert(rxq_ibv);
1112         return (rte_atomic32_read(&rxq_ibv->refcnt) == 1);
1113 }
1114
1115 /**
1116  * Callback function to initialize mbufs for Multi-Packet RQ.
1117  */
1118 static inline void
1119 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1120                     void *_m, unsigned int i __rte_unused)
1121 {
1122         struct mlx5_mprq_buf *buf = _m;
1123
1124         memset(_m, 0, sizeof(*buf));
1125         buf->mp = mp;
1126         rte_atomic16_set(&buf->refcnt, 1);
1127 }
1128
1129 /**
1130  * Free mempool of Multi-Packet RQ.
1131  *
1132  * @param dev
1133  *   Pointer to Ethernet device.
1134  *
1135  * @return
1136  *   0 on success, negative errno value on failure.
1137  */
1138 int
1139 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1140 {
1141         struct priv *priv = dev->data->dev_private;
1142         struct rte_mempool *mp = priv->mprq_mp;
1143         unsigned int i;
1144
1145         if (mp == NULL)
1146                 return 0;
1147         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1148                 dev->data->port_id, mp->name);
1149         /*
1150          * If a buffer in the pool has been externally attached to a mbuf and it
1151          * is still in use by application, destroying the Rx qeueue can spoil
1152          * the packet. It is unlikely to happen but if application dynamically
1153          * creates and destroys with holding Rx packets, this can happen.
1154          *
1155          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1156          * RQ isn't provided by application but managed by PMD.
1157          */
1158         if (!rte_mempool_full(mp)) {
1159                 DRV_LOG(ERR,
1160                         "port %u mempool for Multi-Packet RQ is still in use",
1161                         dev->data->port_id);
1162                 rte_errno = EBUSY;
1163                 return -rte_errno;
1164         }
1165         rte_mempool_free(mp);
1166         /* Unset mempool for each Rx queue. */
1167         for (i = 0; i != priv->rxqs_n; ++i) {
1168                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1169
1170                 if (rxq == NULL)
1171                         continue;
1172                 rxq->mprq_mp = NULL;
1173         }
1174         return 0;
1175 }
1176
1177 /**
1178  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1179  * mempool. If already allocated, reuse it if there're enough elements.
1180  * Otherwise, resize it.
1181  *
1182  * @param dev
1183  *   Pointer to Ethernet device.
1184  *
1185  * @return
1186  *   0 on success, negative errno value on failure.
1187  */
1188 int
1189 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1190 {
1191         struct priv *priv = dev->data->dev_private;
1192         struct rte_mempool *mp = priv->mprq_mp;
1193         char name[RTE_MEMPOOL_NAMESIZE];
1194         unsigned int desc = 0;
1195         unsigned int buf_len;
1196         unsigned int obj_num;
1197         unsigned int obj_size;
1198         unsigned int strd_num_n = 0;
1199         unsigned int strd_sz_n = 0;
1200         unsigned int i;
1201
1202         if (!mlx5_mprq_enabled(dev))
1203                 return 0;
1204         /* Count the total number of descriptors configured. */
1205         for (i = 0; i != priv->rxqs_n; ++i) {
1206                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1207
1208                 if (rxq == NULL)
1209                         continue;
1210                 desc += 1 << rxq->elts_n;
1211                 /* Get the max number of strides. */
1212                 if (strd_num_n < rxq->strd_num_n)
1213                         strd_num_n = rxq->strd_num_n;
1214                 /* Get the max size of a stride. */
1215                 if (strd_sz_n < rxq->strd_sz_n)
1216                         strd_sz_n = rxq->strd_sz_n;
1217         }
1218         assert(strd_num_n && strd_sz_n);
1219         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1220         obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1221         /*
1222          * Received packets can be either memcpy'd or externally referenced. In
1223          * case that the packet is attached to an mbuf as an external buffer, as
1224          * it isn't possible to predict how the buffers will be queued by
1225          * application, there's no option to exactly pre-allocate needed buffers
1226          * in advance but to speculatively prepares enough buffers.
1227          *
1228          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1229          * received packets to buffers provided by application (rxq->mp) until
1230          * this Mempool gets available again.
1231          */
1232         desc *= 4;
1233         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1234         /* Check a mempool is already allocated and if it can be resued. */
1235         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1236                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1237                         dev->data->port_id, mp->name);
1238                 /* Reuse. */
1239                 goto exit;
1240         } else if (mp != NULL) {
1241                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1242                         dev->data->port_id, mp->name);
1243                 /*
1244                  * If failed to free, which means it may be still in use, no way
1245                  * but to keep using the existing one. On buffer underrun,
1246                  * packets will be memcpy'd instead of external buffer
1247                  * attachment.
1248                  */
1249                 if (mlx5_mprq_free_mp(dev)) {
1250                         if (mp->elt_size >= obj_size)
1251                                 goto exit;
1252                         else
1253                                 return -rte_errno;
1254                 }
1255         }
1256         snprintf(name, sizeof(name), "%s-mprq", dev->device->name);
1257         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1258                                 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1259                                 dev->device->numa_node, 0);
1260         if (mp == NULL) {
1261                 DRV_LOG(ERR,
1262                         "port %u failed to allocate a mempool for"
1263                         " Multi-Packet RQ, count=%u, size=%u",
1264                         dev->data->port_id, obj_num, obj_size);
1265                 rte_errno = ENOMEM;
1266                 return -rte_errno;
1267         }
1268         priv->mprq_mp = mp;
1269 exit:
1270         /* Set mempool for each Rx queue. */
1271         for (i = 0; i != priv->rxqs_n; ++i) {
1272                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1273
1274                 if (rxq == NULL)
1275                         continue;
1276                 rxq->mprq_mp = mp;
1277         }
1278         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1279                 dev->data->port_id);
1280         return 0;
1281 }
1282
1283 /**
1284  * Create a DPDK Rx queue.
1285  *
1286  * @param dev
1287  *   Pointer to Ethernet device.
1288  * @param idx
1289  *   RX queue index.
1290  * @param desc
1291  *   Number of descriptors to configure in queue.
1292  * @param socket
1293  *   NUMA socket on which memory must be allocated.
1294  *
1295  * @return
1296  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1297  */
1298 struct mlx5_rxq_ctrl *
1299 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1300              unsigned int socket, const struct rte_eth_rxconf *conf,
1301              struct rte_mempool *mp)
1302 {
1303         struct priv *priv = dev->data->dev_private;
1304         struct mlx5_rxq_ctrl *tmpl;
1305         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1306         unsigned int mprq_stride_size;
1307         struct mlx5_dev_config *config = &priv->config;
1308         /*
1309          * Always allocate extra slots, even if eventually
1310          * the vector Rx will not be used.
1311          */
1312         uint16_t desc_n =
1313                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1314         uint64_t offloads = conf->offloads |
1315                            dev->data->dev_conf.rxmode.offloads;
1316         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1317
1318         tmpl = rte_calloc_socket("RXQ", 1,
1319                                  sizeof(*tmpl) +
1320                                  desc_n * sizeof(struct rte_mbuf *),
1321                                  0, socket);
1322         if (!tmpl) {
1323                 rte_errno = ENOMEM;
1324                 return NULL;
1325         }
1326         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1327                                MLX5_MR_BTREE_CACHE_N, socket)) {
1328                 /* rte_errno is already set. */
1329                 goto error;
1330         }
1331         tmpl->socket = socket;
1332         if (dev->data->dev_conf.intr_conf.rxq)
1333                 tmpl->irq = 1;
1334         /*
1335          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1336          * following conditions are met:
1337          *  - MPRQ is enabled.
1338          *  - The number of descs is more than the number of strides.
1339          *  - max_rx_pkt_len plus overhead is less than the max size of a
1340          *    stride.
1341          *  Otherwise, enable Rx scatter if necessary.
1342          */
1343         assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1344         mprq_stride_size =
1345                 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1346                 sizeof(struct rte_mbuf_ext_shared_info) +
1347                 RTE_PKTMBUF_HEADROOM;
1348         if (mprq_en &&
1349             desc >= (1U << config->mprq.stride_num_n) &&
1350             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1351                 /* TODO: Rx scatter isn't supported yet. */
1352                 tmpl->rxq.sges_n = 0;
1353                 /* Trim the number of descs needed. */
1354                 desc >>= config->mprq.stride_num_n;
1355                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1356                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1357                                               config->mprq.min_stride_size_n);
1358                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1359                 tmpl->rxq.mprq_max_memcpy_len =
1360                         RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1361                                 config->mprq.max_memcpy_len);
1362                 DRV_LOG(DEBUG,
1363                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1364                         " strd_num_n = %u, strd_sz_n = %u",
1365                         dev->data->port_id, idx,
1366                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1367         } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1368                    (mb_len - RTE_PKTMBUF_HEADROOM)) {
1369                 tmpl->rxq.sges_n = 0;
1370         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1371                 unsigned int size =
1372                         RTE_PKTMBUF_HEADROOM +
1373                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1374                 unsigned int sges_n;
1375
1376                 /*
1377                  * Determine the number of SGEs needed for a full packet
1378                  * and round it to the next power of two.
1379                  */
1380                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1381                 tmpl->rxq.sges_n = sges_n;
1382                 /* Make sure rxq.sges_n did not overflow. */
1383                 size = mb_len * (1 << tmpl->rxq.sges_n);
1384                 size -= RTE_PKTMBUF_HEADROOM;
1385                 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1386                         DRV_LOG(ERR,
1387                                 "port %u too many SGEs (%u) needed to handle"
1388                                 " requested maximum packet size %u",
1389                                 dev->data->port_id,
1390                                 1 << sges_n,
1391                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1392                         rte_errno = EOVERFLOW;
1393                         goto error;
1394                 }
1395         } else {
1396                 DRV_LOG(WARNING,
1397                         "port %u the requested maximum Rx packet size (%u) is"
1398                         " larger than a single mbuf (%u) and scattered mode has"
1399                         " not been requested",
1400                         dev->data->port_id,
1401                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
1402                         mb_len - RTE_PKTMBUF_HEADROOM);
1403         }
1404         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1405                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1406         if (desc % (1 << tmpl->rxq.sges_n)) {
1407                 DRV_LOG(ERR,
1408                         "port %u number of Rx queue descriptors (%u) is not a"
1409                         " multiple of SGEs per packet (%u)",
1410                         dev->data->port_id,
1411                         desc,
1412                         1 << tmpl->rxq.sges_n);
1413                 rte_errno = EINVAL;
1414                 goto error;
1415         }
1416         /* Toggle RX checksum offload if hardware supports it. */
1417         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1418         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1419         /* Configure VLAN stripping. */
1420         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1421         /* By default, FCS (CRC) is stripped by hardware. */
1422         if (offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
1423                 tmpl->rxq.crc_present = 0;
1424         } else if (config->hw_fcs_strip) {
1425                 tmpl->rxq.crc_present = 1;
1426         } else {
1427                 DRV_LOG(WARNING,
1428                         "port %u CRC stripping has been disabled but will"
1429                         " still be performed by hardware, make sure MLNX_OFED"
1430                         " and firmware are up to date",
1431                         dev->data->port_id);
1432                 tmpl->rxq.crc_present = 0;
1433         }
1434         DRV_LOG(DEBUG,
1435                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1436                 " incoming frames to hide it",
1437                 dev->data->port_id,
1438                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1439                 tmpl->rxq.crc_present << 2);
1440         /* Save port ID. */
1441         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1442                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1443         tmpl->rxq.port_id = dev->data->port_id;
1444         tmpl->priv = priv;
1445         tmpl->rxq.mp = mp;
1446         tmpl->rxq.stats.idx = idx;
1447         tmpl->rxq.elts_n = log2above(desc);
1448         tmpl->rxq.elts =
1449                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1450         tmpl->idx = idx;
1451         rte_atomic32_inc(&tmpl->refcnt);
1452         DRV_LOG(DEBUG, "port %u Rx queue %u: refcnt %d", dev->data->port_id,
1453                 idx, rte_atomic32_read(&tmpl->refcnt));
1454         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1455         return tmpl;
1456 error:
1457         rte_free(tmpl);
1458         return NULL;
1459 }
1460
1461 /**
1462  * Get a Rx queue.
1463  *
1464  * @param dev
1465  *   Pointer to Ethernet device.
1466  * @param idx
1467  *   TX queue index.
1468  *
1469  * @return
1470  *   A pointer to the queue if it exists, NULL otherwise.
1471  */
1472 struct mlx5_rxq_ctrl *
1473 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1474 {
1475         struct priv *priv = dev->data->dev_private;
1476         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1477
1478         if ((*priv->rxqs)[idx]) {
1479                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1480                                         struct mlx5_rxq_ctrl,
1481                                         rxq);
1482                 mlx5_rxq_ibv_get(dev, idx);
1483                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1484                 DRV_LOG(DEBUG, "port %u Rx queue %u: refcnt %d",
1485                         dev->data->port_id, rxq_ctrl->idx,
1486                         rte_atomic32_read(&rxq_ctrl->refcnt));
1487         }
1488         return rxq_ctrl;
1489 }
1490
1491 /**
1492  * Release a Rx queue.
1493  *
1494  * @param dev
1495  *   Pointer to Ethernet device.
1496  * @param idx
1497  *   TX queue index.
1498  *
1499  * @return
1500  *   1 while a reference on it exists, 0 when freed.
1501  */
1502 int
1503 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1504 {
1505         struct priv *priv = dev->data->dev_private;
1506         struct mlx5_rxq_ctrl *rxq_ctrl;
1507
1508         if (!(*priv->rxqs)[idx])
1509                 return 0;
1510         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1511         assert(rxq_ctrl->priv);
1512         if (rxq_ctrl->ibv && !mlx5_rxq_ibv_release(rxq_ctrl->ibv))
1513                 rxq_ctrl->ibv = NULL;
1514         DRV_LOG(DEBUG, "port %u Rx queue %u: refcnt %d", dev->data->port_id,
1515                 rxq_ctrl->idx, rte_atomic32_read(&rxq_ctrl->refcnt));
1516         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1517                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1518                 LIST_REMOVE(rxq_ctrl, next);
1519                 rte_free(rxq_ctrl);
1520                 (*priv->rxqs)[idx] = NULL;
1521                 return 0;
1522         }
1523         return 1;
1524 }
1525
1526 /**
1527  * Verify if the queue can be released.
1528  *
1529  * @param dev
1530  *   Pointer to Ethernet device.
1531  * @param idx
1532  *   TX queue index.
1533  *
1534  * @return
1535  *   1 if the queue can be released, negative errno otherwise and rte_errno is
1536  *   set.
1537  */
1538 int
1539 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1540 {
1541         struct priv *priv = dev->data->dev_private;
1542         struct mlx5_rxq_ctrl *rxq_ctrl;
1543
1544         if (!(*priv->rxqs)[idx]) {
1545                 rte_errno = EINVAL;
1546                 return -rte_errno;
1547         }
1548         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1549         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1550 }
1551
1552 /**
1553  * Verify the Rx Queue list is empty
1554  *
1555  * @param dev
1556  *   Pointer to Ethernet device.
1557  *
1558  * @return
1559  *   The number of object not released.
1560  */
1561 int
1562 mlx5_rxq_verify(struct rte_eth_dev *dev)
1563 {
1564         struct priv *priv = dev->data->dev_private;
1565         struct mlx5_rxq_ctrl *rxq_ctrl;
1566         int ret = 0;
1567
1568         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1569                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1570                         dev->data->port_id, rxq_ctrl->idx);
1571                 ++ret;
1572         }
1573         return ret;
1574 }
1575
1576 /**
1577  * Create an indirection table.
1578  *
1579  * @param dev
1580  *   Pointer to Ethernet device.
1581  * @param queues
1582  *   Queues entering in the indirection table.
1583  * @param queues_n
1584  *   Number of queues in the array.
1585  *
1586  * @return
1587  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1588  */
1589 struct mlx5_ind_table_ibv *
1590 mlx5_ind_table_ibv_new(struct rte_eth_dev *dev, const uint16_t *queues,
1591                        uint32_t queues_n)
1592 {
1593         struct priv *priv = dev->data->dev_private;
1594         struct mlx5_ind_table_ibv *ind_tbl;
1595         const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1596                 log2above(queues_n) :
1597                 log2above(priv->config.ind_table_max_size);
1598         struct ibv_wq *wq[1 << wq_n];
1599         unsigned int i;
1600         unsigned int j;
1601
1602         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1603                              queues_n * sizeof(uint16_t), 0);
1604         if (!ind_tbl) {
1605                 rte_errno = ENOMEM;
1606                 return NULL;
1607         }
1608         for (i = 0; i != queues_n; ++i) {
1609                 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1610
1611                 if (!rxq)
1612                         goto error;
1613                 wq[i] = rxq->ibv->wq;
1614                 ind_tbl->queues[i] = queues[i];
1615         }
1616         ind_tbl->queues_n = queues_n;
1617         /* Finalise indirection table. */
1618         for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1619                 wq[i] = wq[j];
1620         ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1621                 (priv->ctx,
1622                  &(struct ibv_rwq_ind_table_init_attr){
1623                         .log_ind_tbl_size = wq_n,
1624                         .ind_tbl = wq,
1625                         .comp_mask = 0,
1626                  });
1627         if (!ind_tbl->ind_table) {
1628                 rte_errno = errno;
1629                 goto error;
1630         }
1631         rte_atomic32_inc(&ind_tbl->refcnt);
1632         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1633         DEBUG("port %u new indirection table %p: queues:%u refcnt:%d",
1634               dev->data->port_id, (void *)ind_tbl, 1 << wq_n,
1635               rte_atomic32_read(&ind_tbl->refcnt));
1636         return ind_tbl;
1637 error:
1638         rte_free(ind_tbl);
1639         DRV_LOG(DEBUG, "port %u cannot create indirection table",
1640                 dev->data->port_id);
1641         return NULL;
1642 }
1643
1644 /**
1645  * Get an indirection table.
1646  *
1647  * @param dev
1648  *   Pointer to Ethernet device.
1649  * @param queues
1650  *   Queues entering in the indirection table.
1651  * @param queues_n
1652  *   Number of queues in the array.
1653  *
1654  * @return
1655  *   An indirection table if found.
1656  */
1657 struct mlx5_ind_table_ibv *
1658 mlx5_ind_table_ibv_get(struct rte_eth_dev *dev, const uint16_t *queues,
1659                        uint32_t queues_n)
1660 {
1661         struct priv *priv = dev->data->dev_private;
1662         struct mlx5_ind_table_ibv *ind_tbl;
1663
1664         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1665                 if ((ind_tbl->queues_n == queues_n) &&
1666                     (memcmp(ind_tbl->queues, queues,
1667                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1668                      == 0))
1669                         break;
1670         }
1671         if (ind_tbl) {
1672                 unsigned int i;
1673
1674                 rte_atomic32_inc(&ind_tbl->refcnt);
1675                 DRV_LOG(DEBUG, "port %u indirection table %p: refcnt %d",
1676                         dev->data->port_id, (void *)ind_tbl,
1677                         rte_atomic32_read(&ind_tbl->refcnt));
1678                 for (i = 0; i != ind_tbl->queues_n; ++i)
1679                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1680         }
1681         return ind_tbl;
1682 }
1683
1684 /**
1685  * Release an indirection table.
1686  *
1687  * @param dev
1688  *   Pointer to Ethernet device.
1689  * @param ind_table
1690  *   Indirection table to release.
1691  *
1692  * @return
1693  *   1 while a reference on it exists, 0 when freed.
1694  */
1695 int
1696 mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
1697                            struct mlx5_ind_table_ibv *ind_tbl)
1698 {
1699         unsigned int i;
1700
1701         DRV_LOG(DEBUG, "port %u indirection table %p: refcnt %d",
1702                 dev->data->port_id, (void *)ind_tbl,
1703                 rte_atomic32_read(&ind_tbl->refcnt));
1704         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
1705                 claim_zero(mlx5_glue->destroy_rwq_ind_table
1706                            (ind_tbl->ind_table));
1707                 DEBUG("port %u delete indirection table %p: queues: %u",
1708                       dev->data->port_id, (void *)ind_tbl, ind_tbl->queues_n);
1709         }
1710         for (i = 0; i != ind_tbl->queues_n; ++i)
1711                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1712         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1713                 LIST_REMOVE(ind_tbl, next);
1714                 rte_free(ind_tbl);
1715                 return 0;
1716         }
1717         return 1;
1718 }
1719
1720 /**
1721  * Verify the Rx Queue list is empty
1722  *
1723  * @param dev
1724  *   Pointer to Ethernet device.
1725  *
1726  * @return
1727  *   The number of object not released.
1728  */
1729 int
1730 mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev)
1731 {
1732         struct priv *priv = dev->data->dev_private;
1733         struct mlx5_ind_table_ibv *ind_tbl;
1734         int ret = 0;
1735
1736         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1737                 DRV_LOG(DEBUG,
1738                         "port %u Verbs indirection table %p still referenced",
1739                         dev->data->port_id, (void *)ind_tbl);
1740                 ++ret;
1741         }
1742         return ret;
1743 }
1744
1745 /**
1746  * Create an Rx Hash queue.
1747  *
1748  * @param dev
1749  *   Pointer to Ethernet device.
1750  * @param rss_key
1751  *   RSS key for the Rx hash queue.
1752  * @param rss_key_len
1753  *   RSS key length.
1754  * @param hash_fields
1755  *   Verbs protocol hash field to make the RSS on.
1756  * @param queues
1757  *   Queues entering in hash queue. In case of empty hash_fields only the
1758  *   first queue index will be taken for the indirection table.
1759  * @param queues_n
1760  *   Number of queues.
1761  * @param tunnel
1762  *   Tunnel type, implies tunnel offloading like inner checksum if available.
1763  * @param rss_level
1764  *   RSS hash on tunnel level.
1765  *
1766  * @return
1767  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1768  */
1769 struct mlx5_hrxq *
1770 mlx5_hrxq_new(struct rte_eth_dev *dev,
1771               const uint8_t *rss_key, uint32_t rss_key_len,
1772               uint64_t hash_fields,
1773               const uint16_t *queues, uint32_t queues_n,
1774               uint32_t tunnel, uint32_t rss_level)
1775 {
1776         struct priv *priv = dev->data->dev_private;
1777         struct mlx5_hrxq *hrxq;
1778         struct mlx5_ind_table_ibv *ind_tbl;
1779         struct ibv_qp *qp;
1780         int err;
1781 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1782         struct mlx5dv_qp_init_attr qp_init_attr = {0};
1783 #endif
1784
1785         queues_n = hash_fields ? queues_n : 1;
1786         ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1787         if (!ind_tbl)
1788                 ind_tbl = mlx5_ind_table_ibv_new(dev, queues, queues_n);
1789         if (!ind_tbl) {
1790                 rte_errno = ENOMEM;
1791                 return NULL;
1792         }
1793         if (!rss_key_len) {
1794                 rss_key_len = rss_hash_default_key_len;
1795                 rss_key = rss_hash_default_key;
1796         }
1797 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1798         if (tunnel) {
1799                 qp_init_attr.comp_mask =
1800                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1801                 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1802         }
1803         qp = mlx5_glue->dv_create_qp
1804                 (priv->ctx,
1805                  &(struct ibv_qp_init_attr_ex){
1806                         .qp_type = IBV_QPT_RAW_PACKET,
1807                         .comp_mask =
1808                                 IBV_QP_INIT_ATTR_PD |
1809                                 IBV_QP_INIT_ATTR_IND_TABLE |
1810                                 IBV_QP_INIT_ATTR_RX_HASH,
1811                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1812                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1813                                 .rx_hash_key_len = rss_key_len ? rss_key_len :
1814                                                    rss_hash_default_key_len,
1815                                 .rx_hash_key = rss_key ?
1816                                                (void *)(uintptr_t)rss_key :
1817                                                rss_hash_default_key,
1818                                 .rx_hash_fields_mask = hash_fields |
1819                                         (tunnel && rss_level > 1 ?
1820                                         (uint32_t)IBV_RX_HASH_INNER : 0),
1821                         },
1822                         .rwq_ind_tbl = ind_tbl->ind_table,
1823                         .pd = priv->pd,
1824                  },
1825                  &qp_init_attr);
1826         DEBUG("port %u new QP:%p ind_tbl:%p hash_fields:0x%" PRIx64
1827               " tunnel:0x%x level:%u dv_attr:comp_mask:0x%" PRIx64
1828               " create_flags:0x%x",
1829               dev->data->port_id, (void *)qp, (void *)ind_tbl,
1830               (tunnel && rss_level == 2 ? (uint32_t)IBV_RX_HASH_INNER : 0) |
1831               hash_fields, tunnel, rss_level,
1832               qp_init_attr.comp_mask, qp_init_attr.create_flags);
1833 #else
1834         qp = mlx5_glue->create_qp_ex
1835                 (priv->ctx,
1836                  &(struct ibv_qp_init_attr_ex){
1837                         .qp_type = IBV_QPT_RAW_PACKET,
1838                         .comp_mask =
1839                                 IBV_QP_INIT_ATTR_PD |
1840                                 IBV_QP_INIT_ATTR_IND_TABLE |
1841                                 IBV_QP_INIT_ATTR_RX_HASH,
1842                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1843                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1844                                 .rx_hash_key_len = rss_key_len ? rss_key_len :
1845                                                    rss_hash_default_key_len,
1846                                 .rx_hash_key = rss_key ?
1847                                                (void *)(uintptr_t)rss_key :
1848                                                rss_hash_default_key,
1849                                 .rx_hash_fields_mask = hash_fields,
1850                         },
1851                         .rwq_ind_tbl = ind_tbl->ind_table,
1852                         .pd = priv->pd,
1853                  });
1854         DEBUG("port %u new QP:%p ind_tbl:%p hash_fields:0x%" PRIx64
1855               " tunnel:0x%x level:%hhu",
1856               dev->data->port_id, (void *)qp, (void *)ind_tbl,
1857               hash_fields, tunnel, rss_level);
1858 #endif
1859         if (!qp) {
1860                 rte_errno = errno;
1861                 goto error;
1862         }
1863         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1864         if (!hrxq)
1865                 goto error;
1866         hrxq->ind_table = ind_tbl;
1867         hrxq->qp = qp;
1868         hrxq->rss_key_len = rss_key_len;
1869         hrxq->hash_fields = hash_fields;
1870         hrxq->tunnel = tunnel;
1871         hrxq->rss_level = rss_level;
1872         memcpy(hrxq->rss_key, rss_key, rss_key_len);
1873         rte_atomic32_inc(&hrxq->refcnt);
1874         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1875         DRV_LOG(DEBUG, "port %u hash Rx queue %p: refcnt %d",
1876                 dev->data->port_id, (void *)hrxq,
1877                 rte_atomic32_read(&hrxq->refcnt));
1878         return hrxq;
1879 error:
1880         err = rte_errno; /* Save rte_errno before cleanup. */
1881         mlx5_ind_table_ibv_release(dev, ind_tbl);
1882         if (qp)
1883                 claim_zero(mlx5_glue->destroy_qp(qp));
1884         rte_errno = err; /* Restore rte_errno. */
1885         return NULL;
1886 }
1887
1888 /**
1889  * Get an Rx Hash queue.
1890  *
1891  * @param dev
1892  *   Pointer to Ethernet device.
1893  * @param rss_conf
1894  *   RSS configuration for the Rx hash queue.
1895  * @param queues
1896  *   Queues entering in hash queue. In case of empty hash_fields only the
1897  *   first queue index will be taken for the indirection table.
1898  * @param queues_n
1899  *   Number of queues.
1900  * @param tunnel
1901  *   Tunnel type, implies tunnel offloading like inner checksum if available.
1902  * @param rss_level
1903  *   RSS hash on tunnel level
1904  *
1905  * @return
1906  *   An hash Rx queue on success.
1907  */
1908 struct mlx5_hrxq *
1909 mlx5_hrxq_get(struct rte_eth_dev *dev,
1910               const uint8_t *rss_key, uint32_t rss_key_len,
1911               uint64_t hash_fields,
1912               const uint16_t *queues, uint32_t queues_n,
1913               uint32_t tunnel, uint32_t rss_level)
1914 {
1915         struct priv *priv = dev->data->dev_private;
1916         struct mlx5_hrxq *hrxq;
1917
1918         queues_n = hash_fields ? queues_n : 1;
1919         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1920                 struct mlx5_ind_table_ibv *ind_tbl;
1921
1922                 if (hrxq->rss_key_len != rss_key_len)
1923                         continue;
1924                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1925                         continue;
1926                 if (hrxq->hash_fields != hash_fields)
1927                         continue;
1928                 if (hrxq->tunnel != tunnel)
1929                         continue;
1930                 if (hrxq->rss_level != rss_level)
1931                         continue;
1932                 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1933                 if (!ind_tbl)
1934                         continue;
1935                 if (ind_tbl != hrxq->ind_table) {
1936                         mlx5_ind_table_ibv_release(dev, ind_tbl);
1937                         continue;
1938                 }
1939                 rte_atomic32_inc(&hrxq->refcnt);
1940                 DRV_LOG(DEBUG, "port %u hash Rx queue %p: refcnt %d",
1941                         dev->data->port_id, (void *)hrxq,
1942                         rte_atomic32_read(&hrxq->refcnt));
1943                 return hrxq;
1944         }
1945         return NULL;
1946 }
1947
1948 /**
1949  * Release the hash Rx queue.
1950  *
1951  * @param dev
1952  *   Pointer to Ethernet device.
1953  * @param hrxq
1954  *   Pointer to Hash Rx queue to release.
1955  *
1956  * @return
1957  *   1 while a reference on it exists, 0 when freed.
1958  */
1959 int
1960 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1961 {
1962         DRV_LOG(DEBUG, "port %u hash Rx queue %p: refcnt %d",
1963                 dev->data->port_id, (void *)hrxq,
1964                 rte_atomic32_read(&hrxq->refcnt));
1965         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1966                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
1967                 DEBUG("port %u delete QP %p: hash: 0x%" PRIx64 ", tunnel:"
1968                       " 0x%x, level: %u",
1969                       dev->data->port_id, (void *)hrxq, hrxq->hash_fields,
1970                       hrxq->tunnel, hrxq->rss_level);
1971                 mlx5_ind_table_ibv_release(dev, hrxq->ind_table);
1972                 LIST_REMOVE(hrxq, next);
1973                 rte_free(hrxq);
1974                 return 0;
1975         }
1976         claim_nonzero(mlx5_ind_table_ibv_release(dev, hrxq->ind_table));
1977         return 1;
1978 }
1979
1980 /**
1981  * Verify the Rx Queue list is empty
1982  *
1983  * @param dev
1984  *   Pointer to Ethernet device.
1985  *
1986  * @return
1987  *   The number of object not released.
1988  */
1989 int
1990 mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev)
1991 {
1992         struct priv *priv = dev->data->dev_private;
1993         struct mlx5_hrxq *hrxq;
1994         int ret = 0;
1995
1996         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1997                 DRV_LOG(DEBUG,
1998                         "port %u Verbs hash Rx queue %p still referenced",
1999                         dev->data->port_id, (void *)hrxq);
2000                 ++ret;
2001         }
2002         return ret;
2003 }