4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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40 #include <sys/queue.h>
43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
48 #include <infiniband/mlx5dv.h>
50 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_malloc.h>
55 #include <rte_ethdev.h>
56 #include <rte_common.h>
57 #include <rte_interrupts.h>
58 #include <rte_debug.h>
62 #include "mlx5_rxtx.h"
63 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Default RSS hash key also used for ConnectX-3. */
68 uint8_t rss_hash_default_key[] = {
69 0x2c, 0xc6, 0x81, 0xd1,
70 0x5b, 0xdb, 0xf4, 0xf7,
71 0xfc, 0xa2, 0x83, 0x19,
72 0xdb, 0x1a, 0x3e, 0x94,
73 0x6b, 0x9e, 0x38, 0xd9,
74 0x2c, 0x9c, 0x03, 0xd1,
75 0xad, 0x99, 0x44, 0xa7,
76 0xd9, 0x56, 0x3d, 0x59,
77 0x06, 0x3c, 0x25, 0xf3,
78 0xfc, 0x1f, 0xdc, 0x2a,
81 /* Length of the default RSS hash key. */
82 const size_t rss_hash_default_key_len = sizeof(rss_hash_default_key);
85 * Allocate RX queue elements.
88 * Pointer to RX queue structure.
91 * 0 on success, errno value on failure.
94 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
96 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
97 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
101 /* Iterate on segments. */
102 for (i = 0; (i != elts_n); ++i) {
103 struct rte_mbuf *buf;
105 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
107 ERROR("%p: empty mbuf pool", (void *)rxq_ctrl);
111 /* Headroom is reserved by rte_pktmbuf_alloc(). */
112 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
113 /* Buffer is supposed to be empty. */
114 assert(rte_pktmbuf_data_len(buf) == 0);
115 assert(rte_pktmbuf_pkt_len(buf) == 0);
117 /* Only the first segment keeps headroom. */
119 SET_DATA_OFF(buf, 0);
120 PORT(buf) = rxq_ctrl->rxq.port_id;
121 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
122 PKT_LEN(buf) = DATA_LEN(buf);
124 (*rxq_ctrl->rxq.elts)[i] = buf;
126 /* If Rx vector is activated. */
127 if (rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
128 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
129 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
132 /* Initialize default rearm_data for vPMD. */
133 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
134 rte_mbuf_refcnt_set(mbuf_init, 1);
135 mbuf_init->nb_segs = 1;
136 mbuf_init->port = rxq->port_id;
138 * prevent compiler reordering:
139 * rearm_data covers previous fields.
141 rte_compiler_barrier();
142 rxq->mbuf_initializer =
143 *(uint64_t *)&mbuf_init->rearm_data;
144 /* Padding with a fake mbuf for vectorized Rx. */
145 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
146 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
148 DEBUG("%p: allocated and configured %u segments (max %u packets)",
149 (void *)rxq_ctrl, elts_n, elts_n / (1 << rxq_ctrl->rxq.sges_n));
154 for (i = 0; (i != elts_n); ++i) {
155 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
156 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
157 (*rxq_ctrl->rxq.elts)[i] = NULL;
159 DEBUG("%p: failed, freed everything", (void *)rxq_ctrl);
165 * Free RX queue elements.
168 * Pointer to RX queue structure.
171 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
173 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
174 const uint16_t q_n = (1 << rxq->elts_n);
175 const uint16_t q_mask = q_n - 1;
176 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
179 DEBUG("%p: freeing WRs", (void *)rxq_ctrl);
180 if (rxq->elts == NULL)
183 * Some mbuf in the Ring belongs to the application. They cannot be
186 if (rxq_check_vec_support(rxq) > 0) {
187 for (i = 0; i < used; ++i)
188 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
189 rxq->rq_pi = rxq->rq_ci;
191 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
192 if ((*rxq->elts)[i] != NULL)
193 rte_pktmbuf_free_seg((*rxq->elts)[i]);
194 (*rxq->elts)[i] = NULL;
199 * Clean up a RX queue.
201 * Destroy objects, free allocated memory and reset the structure for reuse.
204 * Pointer to RX queue structure.
207 mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl)
209 DEBUG("cleaning up %p", (void *)rxq_ctrl);
211 mlx5_priv_rxq_ibv_release(rxq_ctrl->priv, rxq_ctrl->ibv);
212 memset(rxq_ctrl, 0, sizeof(*rxq_ctrl));
218 * Pointer to Ethernet device structure.
222 * Number of descriptors to configure in queue.
224 * NUMA socket on which memory must be allocated.
226 * Thresholds parameters.
228 * Memory pool for buffer allocations.
231 * 0 on success, negative errno value on failure.
234 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
235 unsigned int socket, const struct rte_eth_rxconf *conf,
236 struct rte_mempool *mp)
238 struct priv *priv = dev->data->dev_private;
239 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
240 struct mlx5_rxq_ctrl *rxq_ctrl =
241 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
245 if (mlx5_is_secondary())
246 return -E_RTE_SECONDARY;
248 if (!rte_is_power_of_2(desc)) {
249 desc = 1 << log2above(desc);
250 WARN("%p: increased number of descriptors in RX queue %u"
251 " to the next power of two (%d)",
252 (void *)dev, idx, desc);
254 DEBUG("%p: configuring queue %u for %u descriptors",
255 (void *)dev, idx, desc);
256 if (idx >= priv->rxqs_n) {
257 ERROR("%p: queue index out of range (%u >= %u)",
258 (void *)dev, idx, priv->rxqs_n);
262 if (!mlx5_priv_rxq_releasable(priv, idx)) {
264 ERROR("%p: unable to release queue index %u",
268 mlx5_priv_rxq_release(priv, idx);
269 rxq_ctrl = mlx5_priv_rxq_new(priv, idx, desc, socket, mp);
271 ERROR("%p: unable to allocate queue index %u",
276 DEBUG("%p: adding RX queue %p to list",
277 (void *)dev, (void *)rxq_ctrl);
278 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
285 * DPDK callback to release a RX queue.
288 * Generic RX queue pointer.
291 mlx5_rx_queue_release(void *dpdk_rxq)
293 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
294 struct mlx5_rxq_ctrl *rxq_ctrl;
297 if (mlx5_is_secondary())
302 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
303 priv = rxq_ctrl->priv;
305 if (!mlx5_priv_rxq_releasable(priv, rxq_ctrl->rxq.stats.idx))
306 rte_panic("Rx queue %p is still used by a flow and cannot be"
307 " removed\n", (void *)rxq_ctrl);
308 mlx5_priv_rxq_release(priv, rxq_ctrl->rxq.stats.idx);
313 * Allocate queue vector and fill epoll fd list for Rx interrupts.
316 * Pointer to private structure.
319 * 0 on success, negative on failure.
322 priv_rx_intr_vec_enable(struct priv *priv)
325 unsigned int rxqs_n = priv->rxqs_n;
326 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
327 unsigned int count = 0;
328 struct rte_intr_handle *intr_handle = priv->dev->intr_handle;
330 assert(!mlx5_is_secondary());
331 if (!priv->dev->data->dev_conf.intr_conf.rxq)
333 priv_rx_intr_vec_disable(priv);
334 intr_handle->intr_vec = malloc(sizeof(intr_handle->intr_vec[rxqs_n]));
335 if (intr_handle->intr_vec == NULL) {
336 ERROR("failed to allocate memory for interrupt vector,"
337 " Rx interrupts will not be supported");
340 intr_handle->type = RTE_INTR_HANDLE_EXT;
341 for (i = 0; i != n; ++i) {
342 /* This rxq ibv must not be released in this function. */
343 struct mlx5_rxq_ibv *rxq_ibv = mlx5_priv_rxq_ibv_get(priv, i);
348 /* Skip queues that cannot request interrupts. */
349 if (!rxq_ibv || !rxq_ibv->channel) {
350 /* Use invalid intr_vec[] index to disable entry. */
351 intr_handle->intr_vec[i] =
352 RTE_INTR_VEC_RXTX_OFFSET +
353 RTE_MAX_RXTX_INTR_VEC_ID;
356 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
357 ERROR("too many Rx queues for interrupt vector size"
358 " (%d), Rx interrupts cannot be enabled",
359 RTE_MAX_RXTX_INTR_VEC_ID);
360 priv_rx_intr_vec_disable(priv);
363 fd = rxq_ibv->channel->fd;
364 flags = fcntl(fd, F_GETFL);
365 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
367 ERROR("failed to make Rx interrupt file descriptor"
368 " %d non-blocking for queue index %d", fd, i);
369 priv_rx_intr_vec_disable(priv);
372 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
373 intr_handle->efds[count] = fd;
377 priv_rx_intr_vec_disable(priv);
379 intr_handle->nb_efd = count;
384 * Clean up Rx interrupts handler.
387 * Pointer to private structure.
390 priv_rx_intr_vec_disable(struct priv *priv)
392 struct rte_intr_handle *intr_handle = priv->dev->intr_handle;
394 unsigned int rxqs_n = priv->rxqs_n;
395 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
397 if (!priv->dev->data->dev_conf.intr_conf.rxq)
399 if (!intr_handle->intr_vec)
401 for (i = 0; i != n; ++i) {
402 struct mlx5_rxq_ctrl *rxq_ctrl;
403 struct mlx5_rxq_data *rxq_data;
405 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
406 RTE_MAX_RXTX_INTR_VEC_ID)
409 * Need to access directly the queue to release the reference
410 * kept in priv_rx_intr_vec_enable().
412 rxq_data = (*priv->rxqs)[i];
413 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
414 mlx5_priv_rxq_ibv_release(priv, rxq_ctrl->ibv);
417 rte_intr_free_epoll_fd(intr_handle);
418 if (intr_handle->intr_vec)
419 free(intr_handle->intr_vec);
420 intr_handle->nb_efd = 0;
421 intr_handle->intr_vec = NULL;
425 * MLX5 CQ notification .
428 * Pointer to receive queue structure.
430 * Sequence number per receive queue .
433 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
436 uint32_t doorbell_hi;
438 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
440 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
441 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
442 doorbell = (uint64_t)doorbell_hi << 32;
443 doorbell |= rxq->cqn;
444 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
446 rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);
450 * DPDK callback for Rx queue interrupt enable.
453 * Pointer to Ethernet device structure.
458 * 0 on success, negative on failure.
461 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
463 struct priv *priv = mlx5_get_priv(dev);
464 struct mlx5_rxq_data *rxq_data;
465 struct mlx5_rxq_ctrl *rxq_ctrl;
469 rxq_data = (*priv->rxqs)[rx_queue_id];
474 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
476 struct mlx5_rxq_ibv *rxq_ibv;
478 rxq_ibv = mlx5_priv_rxq_ibv_get(priv, rx_queue_id);
483 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
484 mlx5_priv_rxq_ibv_release(priv, rxq_ibv);
489 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
494 * DPDK callback for Rx queue interrupt disable.
497 * Pointer to Ethernet device structure.
502 * 0 on success, negative on failure.
505 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
507 struct priv *priv = mlx5_get_priv(dev);
508 struct mlx5_rxq_data *rxq_data;
509 struct mlx5_rxq_ctrl *rxq_ctrl;
510 struct mlx5_rxq_ibv *rxq_ibv = NULL;
511 struct ibv_cq *ev_cq;
516 rxq_data = (*priv->rxqs)[rx_queue_id];
521 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
524 rxq_ibv = mlx5_priv_rxq_ibv_get(priv, rx_queue_id);
529 ret = ibv_get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
530 if (ret || ev_cq != rxq_ibv->cq) {
534 rxq_data->cq_arm_sn++;
535 ibv_ack_cq_events(rxq_ibv->cq, 1);
538 mlx5_priv_rxq_ibv_release(priv, rxq_ibv);
541 WARN("unable to disable interrupt on rx queue %d",
547 * Create the Rx queue Verbs object.
550 * Pointer to private structure.
552 * Queue index in DPDK Rx queue array
555 * The Verbs object initialised if it can be created.
558 mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
560 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
561 struct mlx5_rxq_ctrl *rxq_ctrl =
562 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
563 struct ibv_wq_attr mod;
566 struct ibv_cq_init_attr_ex ibv;
567 struct mlx5dv_cq_init_attr mlx5;
569 struct ibv_wq_init_attr wq;
570 struct ibv_cq_ex cq_attr;
572 unsigned int cqe_n = (1 << rxq_data->elts_n) - 1;
573 struct mlx5_rxq_ibv *tmpl;
574 struct mlx5dv_cq cq_info;
575 struct mlx5dv_rwq rwq;
578 struct mlx5dv_obj obj;
581 assert(!rxq_ctrl->ibv);
582 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
585 ERROR("%p: cannot allocate verbs resources",
589 tmpl->rxq_ctrl = rxq_ctrl;
590 /* Use the entire RX mempool as the memory region. */
591 tmpl->mr = priv_mr_get(priv, rxq_data->mp);
593 tmpl->mr = priv_mr_new(priv, rxq_data->mp);
595 ERROR("%p: MR creation failure", (void *)rxq_ctrl);
600 tmpl->channel = ibv_create_comp_channel(priv->ctx);
601 if (!tmpl->channel) {
602 ERROR("%p: Comp Channel creation failure",
607 attr.cq.ibv = (struct ibv_cq_init_attr_ex){
609 .channel = tmpl->channel,
612 attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
615 if (priv->cqe_comp && !rxq_data->hw_timestamp) {
616 attr.cq.mlx5.comp_mask |=
617 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
618 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
620 * For vectorized Rx, it must not be doubled in order to
621 * make cq_ci and rq_ci aligned.
623 if (rxq_check_vec_support(rxq_data) < 0)
624 attr.cq.ibv.cqe *= 2;
625 } else if (priv->cqe_comp && rxq_data->hw_timestamp) {
626 DEBUG("Rx CQE compression is disabled for HW timestamp");
628 tmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,
630 if (tmpl->cq == NULL) {
631 ERROR("%p: CQ creation failure", (void *)rxq_ctrl);
634 DEBUG("priv->device_attr.max_qp_wr is %d",
635 priv->device_attr.orig_attr.max_qp_wr);
636 DEBUG("priv->device_attr.max_sge is %d",
637 priv->device_attr.orig_attr.max_sge);
638 attr.wq = (struct ibv_wq_init_attr){
639 .wq_context = NULL, /* Could be useful in the future. */
640 .wq_type = IBV_WQT_RQ,
641 /* Max number of outstanding WRs. */
642 .max_wr = (1 << rxq_data->elts_n) >> rxq_data->sges_n,
643 /* Max number of scatter/gather elements in a WR. */
644 .max_sge = 1 << rxq_data->sges_n,
648 IBV_WQ_FLAGS_CVLAN_STRIPPING |
650 .create_flags = (rxq_data->vlan_strip ?
651 IBV_WQ_FLAGS_CVLAN_STRIPPING :
654 /* By default, FCS (CRC) is stripped by hardware. */
655 if (rxq_data->crc_present) {
656 attr.wq.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
657 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
659 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
660 if (priv->hw_padding) {
661 attr.wq.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
662 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
665 tmpl->wq = ibv_create_wq(priv->ctx, &attr.wq);
666 if (tmpl->wq == NULL) {
667 ERROR("%p: WQ creation failure", (void *)rxq_ctrl);
671 * Make sure number of WRs*SGEs match expectations since a queue
672 * cannot allocate more than "desc" buffers.
674 if (((int)attr.wq.max_wr !=
675 ((1 << rxq_data->elts_n) >> rxq_data->sges_n)) ||
676 ((int)attr.wq.max_sge != (1 << rxq_data->sges_n))) {
677 ERROR("%p: requested %u*%u but got %u*%u WRs*SGEs",
679 ((1 << rxq_data->elts_n) >> rxq_data->sges_n),
680 (1 << rxq_data->sges_n),
681 attr.wq.max_wr, attr.wq.max_sge);
684 /* Change queue state to ready. */
685 mod = (struct ibv_wq_attr){
686 .attr_mask = IBV_WQ_ATTR_STATE,
687 .wq_state = IBV_WQS_RDY,
689 ret = ibv_modify_wq(tmpl->wq, &mod);
691 ERROR("%p: WQ state to IBV_WQS_RDY failed",
695 obj.cq.in = tmpl->cq;
696 obj.cq.out = &cq_info;
697 obj.rwq.in = tmpl->wq;
699 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
702 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
703 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
704 "it should be set to %u", RTE_CACHE_LINE_SIZE);
707 /* Fill the rings. */
708 rxq_data->wqes = (volatile struct mlx5_wqe_data_seg (*)[])
710 for (i = 0; (i != (unsigned int)(1 << rxq_data->elts_n)); ++i) {
711 struct rte_mbuf *buf = (*rxq_data->elts)[i];
712 volatile struct mlx5_wqe_data_seg *scat = &(*rxq_data->wqes)[i];
714 /* scat->addr must be able to store a pointer. */
715 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
716 *scat = (struct mlx5_wqe_data_seg){
717 .addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
719 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
720 .lkey = tmpl->mr->lkey,
723 rxq_data->rq_db = rwq.dbrec;
724 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
728 rxq_data->zip = (struct rxq_zip){
731 rxq_data->cq_db = cq_info.dbrec;
732 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
733 rxq_data->cq_uar = cq_info.cq_uar;
734 rxq_data->cqn = cq_info.cqn;
735 rxq_data->cq_arm_sn = 0;
736 /* Update doorbell counter. */
737 rxq_data->rq_ci = (1 << rxq_data->elts_n) >> rxq_data->sges_n;
739 *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
740 DEBUG("%p: rxq updated with %p", (void *)rxq_ctrl, (void *)&tmpl);
741 rte_atomic32_inc(&tmpl->refcnt);
742 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
743 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
744 LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
748 claim_zero(ibv_destroy_wq(tmpl->wq));
750 claim_zero(ibv_destroy_cq(tmpl->cq));
752 claim_zero(ibv_destroy_comp_channel(tmpl->channel));
754 priv_mr_release(priv, tmpl->mr);
759 * Get an Rx queue Verbs object.
762 * Pointer to private structure.
764 * Queue index in DPDK Rx queue array
767 * The Verbs object if it exists.
770 mlx5_priv_rxq_ibv_get(struct priv *priv, uint16_t idx)
772 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
773 struct mlx5_rxq_ctrl *rxq_ctrl;
775 if (idx >= priv->rxqs_n)
779 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
781 priv_mr_get(priv, rxq_data->mp);
782 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
783 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
784 (void *)rxq_ctrl->ibv,
785 rte_atomic32_read(&rxq_ctrl->ibv->refcnt));
787 return rxq_ctrl->ibv;
791 * Release an Rx verbs queue object.
794 * Pointer to private structure.
796 * Verbs Rx queue object.
799 * 0 on success, errno value on failure.
802 mlx5_priv_rxq_ibv_release(struct priv *priv, struct mlx5_rxq_ibv *rxq_ibv)
810 ret = priv_mr_release(priv, rxq_ibv->mr);
813 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
814 (void *)rxq_ibv, rte_atomic32_read(&rxq_ibv->refcnt));
815 if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
816 rxq_free_elts(rxq_ibv->rxq_ctrl);
817 claim_zero(ibv_destroy_wq(rxq_ibv->wq));
818 claim_zero(ibv_destroy_cq(rxq_ibv->cq));
819 if (rxq_ibv->channel)
820 claim_zero(ibv_destroy_comp_channel(rxq_ibv->channel));
821 LIST_REMOVE(rxq_ibv, next);
829 * Verify the Verbs Rx queue list is empty
832 * Pointer to private structure.
834 * @return the number of object not released.
837 mlx5_priv_rxq_ibv_verify(struct priv *priv)
840 struct mlx5_rxq_ibv *rxq_ibv;
842 LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
843 DEBUG("%p: Verbs Rx queue %p still referenced", (void *)priv,
851 * Return true if a single reference exists on the object.
854 * Pointer to private structure.
856 * Verbs Rx queue object.
859 mlx5_priv_rxq_ibv_releasable(struct priv *priv, struct mlx5_rxq_ibv *rxq_ibv)
863 return (rte_atomic32_read(&rxq_ibv->refcnt) == 1);
867 * Create a DPDK Rx queue.
870 * Pointer to private structure.
874 * Number of descriptors to configure in queue.
876 * NUMA socket on which memory must be allocated.
879 * A DPDK queue object on success.
881 struct mlx5_rxq_ctrl*
882 mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc,
883 unsigned int socket, struct rte_mempool *mp)
885 struct rte_eth_dev *dev = priv->dev;
886 struct mlx5_rxq_ctrl *tmpl;
887 const uint16_t desc_n =
888 desc + priv->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
889 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
891 tmpl = rte_calloc_socket("RXQ", 1,
893 desc_n * sizeof(struct rte_mbuf *),
897 tmpl->socket = socket;
898 if (priv->dev->data->dev_conf.intr_conf.rxq)
900 /* Enable scattered packets support for this queue if necessary. */
901 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
902 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
903 (mb_len - RTE_PKTMBUF_HEADROOM)) {
904 tmpl->rxq.sges_n = 0;
905 } else if (dev->data->dev_conf.rxmode.enable_scatter) {
907 RTE_PKTMBUF_HEADROOM +
908 dev->data->dev_conf.rxmode.max_rx_pkt_len;
912 * Determine the number of SGEs needed for a full packet
913 * and round it to the next power of two.
915 sges_n = log2above((size / mb_len) + !!(size % mb_len));
916 tmpl->rxq.sges_n = sges_n;
917 /* Make sure rxq.sges_n did not overflow. */
918 size = mb_len * (1 << tmpl->rxq.sges_n);
919 size -= RTE_PKTMBUF_HEADROOM;
920 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
921 ERROR("%p: too many SGEs (%u) needed to handle"
922 " requested maximum packet size %u",
925 dev->data->dev_conf.rxmode.max_rx_pkt_len);
929 WARN("%p: the requested maximum Rx packet size (%u) is"
930 " larger than a single mbuf (%u) and scattered"
931 " mode has not been requested",
933 dev->data->dev_conf.rxmode.max_rx_pkt_len,
934 mb_len - RTE_PKTMBUF_HEADROOM);
936 DEBUG("%p: maximum number of segments per packet: %u",
937 (void *)dev, 1 << tmpl->rxq.sges_n);
938 if (desc % (1 << tmpl->rxq.sges_n)) {
939 ERROR("%p: number of RX queue descriptors (%u) is not a"
940 " multiple of SGEs per packet (%u)",
943 1 << tmpl->rxq.sges_n);
946 /* Toggle RX checksum offload if hardware supports it. */
948 tmpl->rxq.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
949 if (priv->hw_csum_l2tun)
950 tmpl->rxq.csum_l2tun =
951 !!dev->data->dev_conf.rxmode.hw_ip_checksum;
952 tmpl->rxq.hw_timestamp =
953 !!dev->data->dev_conf.rxmode.hw_timestamp;
954 /* Configure VLAN stripping. */
955 tmpl->rxq.vlan_strip = (priv->hw_vlan_strip &&
956 !!dev->data->dev_conf.rxmode.hw_vlan_strip);
957 /* By default, FCS (CRC) is stripped by hardware. */
958 if (dev->data->dev_conf.rxmode.hw_strip_crc) {
959 tmpl->rxq.crc_present = 0;
960 } else if (priv->hw_fcs_strip) {
961 tmpl->rxq.crc_present = 1;
963 WARN("%p: CRC stripping has been disabled but will still"
964 " be performed by hardware, make sure MLNX_OFED and"
965 " firmware are up to date",
967 tmpl->rxq.crc_present = 0;
969 DEBUG("%p: CRC stripping is %s, %u bytes will be subtracted from"
970 " incoming frames to hide it",
972 tmpl->rxq.crc_present ? "disabled" : "enabled",
973 tmpl->rxq.crc_present << 2);
975 tmpl->rxq.rss_hash = priv->rxqs_n > 1;
976 tmpl->rxq.port_id = dev->data->port_id;
979 tmpl->rxq.stats.idx = idx;
980 tmpl->rxq.elts_n = log2above(desc);
982 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
983 rte_atomic32_inc(&tmpl->refcnt);
984 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
985 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
986 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
997 * Pointer to private structure.
1002 * A pointer to the queue if it exists.
1004 struct mlx5_rxq_ctrl*
1005 mlx5_priv_rxq_get(struct priv *priv, uint16_t idx)
1007 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1009 if ((*priv->rxqs)[idx]) {
1010 rxq_ctrl = container_of((*priv->rxqs)[idx],
1011 struct mlx5_rxq_ctrl,
1014 mlx5_priv_rxq_ibv_get(priv, idx);
1015 rte_atomic32_inc(&rxq_ctrl->refcnt);
1016 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
1017 (void *)rxq_ctrl, rte_atomic32_read(&rxq_ctrl->refcnt));
1023 * Release a Rx queue.
1026 * Pointer to private structure.
1031 * 0 on success, errno value on failure.
1034 mlx5_priv_rxq_release(struct priv *priv, uint16_t idx)
1036 struct mlx5_rxq_ctrl *rxq_ctrl;
1038 if (!(*priv->rxqs)[idx])
1040 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1041 assert(rxq_ctrl->priv);
1042 if (rxq_ctrl->ibv) {
1045 ret = mlx5_priv_rxq_ibv_release(rxq_ctrl->priv, rxq_ctrl->ibv);
1047 rxq_ctrl->ibv = NULL;
1049 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
1050 (void *)rxq_ctrl, rte_atomic32_read(&rxq_ctrl->refcnt));
1051 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1052 LIST_REMOVE(rxq_ctrl, next);
1054 (*priv->rxqs)[idx] = NULL;
1061 * Verify if the queue can be released.
1064 * Pointer to private structure.
1069 * 1 if the queue can be released.
1072 mlx5_priv_rxq_releasable(struct priv *priv, uint16_t idx)
1074 struct mlx5_rxq_ctrl *rxq_ctrl;
1076 if (!(*priv->rxqs)[idx])
1078 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1079 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1083 * Verify the Rx Queue list is empty
1086 * Pointer to private structure.
1088 * @return the number of object not released.
1091 mlx5_priv_rxq_verify(struct priv *priv)
1093 struct mlx5_rxq_ctrl *rxq_ctrl;
1096 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1097 DEBUG("%p: Rx Queue %p still referenced", (void *)priv,
1105 * Create an indirection table.
1108 * Pointer to private structure.
1110 * Queues entering in the indirection table.
1112 * Number of queues in the array.
1115 * A new indirection table.
1117 struct mlx5_ind_table_ibv*
1118 mlx5_priv_ind_table_ibv_new(struct priv *priv, uint16_t queues[],
1121 struct mlx5_ind_table_ibv *ind_tbl;
1122 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1123 log2above(queues_n) :
1124 log2above(priv->ind_table_max_size);
1125 struct ibv_wq *wq[1 << wq_n];
1129 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1130 queues_n * sizeof(uint16_t), 0);
1133 for (i = 0; i != queues_n; ++i) {
1134 struct mlx5_rxq_ctrl *rxq =
1135 mlx5_priv_rxq_get(priv, queues[i]);
1139 wq[i] = rxq->ibv->wq;
1140 ind_tbl->queues[i] = queues[i];
1142 ind_tbl->queues_n = queues_n;
1143 /* Finalise indirection table. */
1144 for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1146 ind_tbl->ind_table = ibv_create_rwq_ind_table(
1148 &(struct ibv_rwq_ind_table_init_attr){
1149 .log_ind_tbl_size = wq_n,
1153 if (!ind_tbl->ind_table)
1155 rte_atomic32_inc(&ind_tbl->refcnt);
1156 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1157 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1158 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1162 DEBUG("%p cannot create indirection table", (void *)priv);
1167 * Get an indirection table.
1170 * Pointer to private structure.
1172 * Queues entering in the indirection table.
1174 * Number of queues in the array.
1177 * An indirection table if found.
1179 struct mlx5_ind_table_ibv*
1180 mlx5_priv_ind_table_ibv_get(struct priv *priv, uint16_t queues[],
1183 struct mlx5_ind_table_ibv *ind_tbl;
1185 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1186 if ((ind_tbl->queues_n == queues_n) &&
1187 (memcmp(ind_tbl->queues, queues,
1188 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1195 rte_atomic32_inc(&ind_tbl->refcnt);
1196 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1197 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1198 for (i = 0; i != ind_tbl->queues_n; ++i)
1199 mlx5_priv_rxq_get(priv, ind_tbl->queues[i]);
1205 * Release an indirection table.
1208 * Pointer to private structure.
1210 * Indirection table to release.
1213 * 0 on success, errno value on failure.
1216 mlx5_priv_ind_table_ibv_release(struct priv *priv,
1217 struct mlx5_ind_table_ibv *ind_tbl)
1221 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1222 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1223 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1224 claim_zero(ibv_destroy_rwq_ind_table(ind_tbl->ind_table));
1225 for (i = 0; i != ind_tbl->queues_n; ++i)
1226 claim_nonzero(mlx5_priv_rxq_release(priv, ind_tbl->queues[i]));
1227 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1228 LIST_REMOVE(ind_tbl, next);
1236 * Verify the Rx Queue list is empty
1239 * Pointer to private structure.
1241 * @return the number of object not released.
1244 mlx5_priv_ind_table_ibv_verify(struct priv *priv)
1246 struct mlx5_ind_table_ibv *ind_tbl;
1249 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1250 DEBUG("%p: Verbs indirection table %p still referenced",
1251 (void *)priv, (void *)ind_tbl);
1258 * Create an Rx Hash queue.
1261 * Pointer to private structure.
1263 * RSS key for the Rx hash queue.
1264 * @param rss_key_len
1266 * @param hash_fields
1267 * Verbs protocol hash field to make the RSS on.
1269 * Queues entering in hash queue. In case of empty hash_fields only the
1270 * first queue index will be taken for the indirection table.
1275 * An hash Rx queue on success.
1278 mlx5_priv_hrxq_new(struct priv *priv, uint8_t *rss_key, uint8_t rss_key_len,
1279 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1281 struct mlx5_hrxq *hrxq;
1282 struct mlx5_ind_table_ibv *ind_tbl;
1285 queues_n = hash_fields ? queues_n : 1;
1286 ind_tbl = mlx5_priv_ind_table_ibv_get(priv, queues, queues_n);
1288 ind_tbl = mlx5_priv_ind_table_ibv_new(priv, queues, queues_n);
1291 qp = ibv_create_qp_ex(
1293 &(struct ibv_qp_init_attr_ex){
1294 .qp_type = IBV_QPT_RAW_PACKET,
1296 IBV_QP_INIT_ATTR_PD |
1297 IBV_QP_INIT_ATTR_IND_TABLE |
1298 IBV_QP_INIT_ATTR_RX_HASH,
1299 .rx_hash_conf = (struct ibv_rx_hash_conf){
1300 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1301 .rx_hash_key_len = rss_key_len,
1302 .rx_hash_key = rss_key,
1303 .rx_hash_fields_mask = hash_fields,
1305 .rwq_ind_tbl = ind_tbl->ind_table,
1310 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1313 hrxq->ind_table = ind_tbl;
1315 hrxq->rss_key_len = rss_key_len;
1316 hrxq->hash_fields = hash_fields;
1317 memcpy(hrxq->rss_key, rss_key, rss_key_len);
1318 rte_atomic32_inc(&hrxq->refcnt);
1319 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1320 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1321 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1324 mlx5_priv_ind_table_ibv_release(priv, ind_tbl);
1326 claim_zero(ibv_destroy_qp(qp));
1331 * Get an Rx Hash queue.
1334 * Pointer to private structure.
1336 * RSS configuration for the Rx hash queue.
1338 * Queues entering in hash queue. In case of empty hash_fields only the
1339 * first queue index will be taken for the indirection table.
1344 * An hash Rx queue on success.
1347 mlx5_priv_hrxq_get(struct priv *priv, uint8_t *rss_key, uint8_t rss_key_len,
1348 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1350 struct mlx5_hrxq *hrxq;
1352 queues_n = hash_fields ? queues_n : 1;
1353 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1354 struct mlx5_ind_table_ibv *ind_tbl;
1356 if (hrxq->rss_key_len != rss_key_len)
1358 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1360 if (hrxq->hash_fields != hash_fields)
1362 ind_tbl = mlx5_priv_ind_table_ibv_get(priv, queues, queues_n);
1365 if (ind_tbl != hrxq->ind_table) {
1366 mlx5_priv_ind_table_ibv_release(priv, ind_tbl);
1369 rte_atomic32_inc(&hrxq->refcnt);
1370 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1371 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1378 * Release the hash Rx queue.
1381 * Pointer to private structure.
1383 * Pointer to Hash Rx queue to release.
1386 * 0 on success, errno value on failure.
1389 mlx5_priv_hrxq_release(struct priv *priv, struct mlx5_hrxq *hrxq)
1391 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1392 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1393 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1394 claim_zero(ibv_destroy_qp(hrxq->qp));
1395 mlx5_priv_ind_table_ibv_release(priv, hrxq->ind_table);
1396 LIST_REMOVE(hrxq, next);
1400 claim_nonzero(mlx5_priv_ind_table_ibv_release(priv, hrxq->ind_table));
1405 * Verify the Rx Queue list is empty
1408 * Pointer to private structure.
1410 * @return the number of object not released.
1413 mlx5_priv_hrxq_ibv_verify(struct priv *priv)
1415 struct mlx5_hrxq *hrxq;
1418 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1419 DEBUG("%p: Verbs Hash Rx queue %p still referenced",
1420 (void *)priv, (void *)hrxq);