4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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40 #include <sys/queue.h>
43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
48 #include <infiniband/mlx5dv.h>
50 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_malloc.h>
55 #include <rte_ethdev_driver.h>
56 #include <rte_common.h>
57 #include <rte_interrupts.h>
58 #include <rte_debug.h>
62 #include "mlx5_rxtx.h"
63 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Default RSS hash key also used for ConnectX-3. */
68 uint8_t rss_hash_default_key[] = {
69 0x2c, 0xc6, 0x81, 0xd1,
70 0x5b, 0xdb, 0xf4, 0xf7,
71 0xfc, 0xa2, 0x83, 0x19,
72 0xdb, 0x1a, 0x3e, 0x94,
73 0x6b, 0x9e, 0x38, 0xd9,
74 0x2c, 0x9c, 0x03, 0xd1,
75 0xad, 0x99, 0x44, 0xa7,
76 0xd9, 0x56, 0x3d, 0x59,
77 0x06, 0x3c, 0x25, 0xf3,
78 0xfc, 0x1f, 0xdc, 0x2a,
81 /* Length of the default RSS hash key. */
82 const size_t rss_hash_default_key_len = sizeof(rss_hash_default_key);
85 * Allocate RX queue elements.
88 * Pointer to RX queue structure.
91 * 0 on success, errno value on failure.
94 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
96 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
97 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
101 /* Iterate on segments. */
102 for (i = 0; (i != elts_n); ++i) {
103 struct rte_mbuf *buf;
105 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
107 ERROR("%p: empty mbuf pool", (void *)rxq_ctrl);
111 /* Headroom is reserved by rte_pktmbuf_alloc(). */
112 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
113 /* Buffer is supposed to be empty. */
114 assert(rte_pktmbuf_data_len(buf) == 0);
115 assert(rte_pktmbuf_pkt_len(buf) == 0);
117 /* Only the first segment keeps headroom. */
119 SET_DATA_OFF(buf, 0);
120 PORT(buf) = rxq_ctrl->rxq.port_id;
121 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
122 PKT_LEN(buf) = DATA_LEN(buf);
124 (*rxq_ctrl->rxq.elts)[i] = buf;
126 /* If Rx vector is activated. */
127 if (rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
128 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
129 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
132 /* Initialize default rearm_data for vPMD. */
133 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
134 rte_mbuf_refcnt_set(mbuf_init, 1);
135 mbuf_init->nb_segs = 1;
136 mbuf_init->port = rxq->port_id;
138 * prevent compiler reordering:
139 * rearm_data covers previous fields.
141 rte_compiler_barrier();
142 rxq->mbuf_initializer =
143 *(uint64_t *)&mbuf_init->rearm_data;
144 /* Padding with a fake mbuf for vectorized Rx. */
145 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
146 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
148 DEBUG("%p: allocated and configured %u segments (max %u packets)",
149 (void *)rxq_ctrl, elts_n, elts_n / (1 << rxq_ctrl->rxq.sges_n));
154 for (i = 0; (i != elts_n); ++i) {
155 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
156 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
157 (*rxq_ctrl->rxq.elts)[i] = NULL;
159 DEBUG("%p: failed, freed everything", (void *)rxq_ctrl);
165 * Free RX queue elements.
168 * Pointer to RX queue structure.
171 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
173 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
174 const uint16_t q_n = (1 << rxq->elts_n);
175 const uint16_t q_mask = q_n - 1;
176 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
179 DEBUG("%p: freeing WRs", (void *)rxq_ctrl);
180 if (rxq->elts == NULL)
183 * Some mbuf in the Ring belongs to the application. They cannot be
186 if (rxq_check_vec_support(rxq) > 0) {
187 for (i = 0; i < used; ++i)
188 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
189 rxq->rq_pi = rxq->rq_ci;
191 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
192 if ((*rxq->elts)[i] != NULL)
193 rte_pktmbuf_free_seg((*rxq->elts)[i]);
194 (*rxq->elts)[i] = NULL;
199 * Clean up a RX queue.
201 * Destroy objects, free allocated memory and reset the structure for reuse.
204 * Pointer to RX queue structure.
207 mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl)
209 DEBUG("cleaning up %p", (void *)rxq_ctrl);
211 mlx5_priv_rxq_ibv_release(rxq_ctrl->priv, rxq_ctrl->ibv);
212 memset(rxq_ctrl, 0, sizeof(*rxq_ctrl));
216 * Returns the per-queue supported offloads.
219 * Pointer to private structure.
222 * Supported Rx offloads.
225 mlx5_priv_get_rx_queue_offloads(struct priv *priv)
227 struct mlx5_dev_config *config = &priv->config;
228 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
229 DEV_RX_OFFLOAD_TIMESTAMP |
230 DEV_RX_OFFLOAD_JUMBO_FRAME);
232 if (config->hw_fcs_strip)
233 offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
235 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
236 DEV_RX_OFFLOAD_UDP_CKSUM |
237 DEV_RX_OFFLOAD_TCP_CKSUM);
238 if (config->hw_vlan_strip)
239 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
245 * Returns the per-port supported offloads.
248 * Pointer to private structure.
250 * Supported Rx offloads.
253 mlx5_priv_get_rx_port_offloads(struct priv *priv __rte_unused)
255 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
261 * Checks if the per-queue offload configuration is valid.
264 * Pointer to private structure.
266 * Per-queue offloads configuration.
269 * 1 if the configuration is valid, 0 otherwise.
272 priv_is_rx_queue_offloads_allowed(struct priv *priv, uint64_t offloads)
274 uint64_t port_offloads = priv->dev->data->dev_conf.rxmode.offloads;
275 uint64_t queue_supp_offloads =
276 mlx5_priv_get_rx_queue_offloads(priv);
277 uint64_t port_supp_offloads = mlx5_priv_get_rx_port_offloads(priv);
279 if ((offloads & (queue_supp_offloads | port_supp_offloads)) !=
282 if (((port_offloads ^ offloads) & port_supp_offloads))
290 * Pointer to Ethernet device structure.
294 * Number of descriptors to configure in queue.
296 * NUMA socket on which memory must be allocated.
298 * Thresholds parameters.
300 * Memory pool for buffer allocations.
303 * 0 on success, negative errno value on failure.
306 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
307 unsigned int socket, const struct rte_eth_rxconf *conf,
308 struct rte_mempool *mp)
310 struct priv *priv = dev->data->dev_private;
311 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
312 struct mlx5_rxq_ctrl *rxq_ctrl =
313 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
317 if (!rte_is_power_of_2(desc)) {
318 desc = 1 << log2above(desc);
319 WARN("%p: increased number of descriptors in RX queue %u"
320 " to the next power of two (%d)",
321 (void *)dev, idx, desc);
323 DEBUG("%p: configuring queue %u for %u descriptors",
324 (void *)dev, idx, desc);
325 if (idx >= priv->rxqs_n) {
326 ERROR("%p: queue index out of range (%u >= %u)",
327 (void *)dev, idx, priv->rxqs_n);
331 if (!priv_is_rx_queue_offloads_allowed(priv, conf->offloads)) {
333 ERROR("%p: Rx queue offloads 0x%" PRIx64 " don't match port "
334 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
335 (void *)dev, conf->offloads,
336 dev->data->dev_conf.rxmode.offloads,
337 (mlx5_priv_get_rx_port_offloads(priv) |
338 mlx5_priv_get_rx_queue_offloads(priv)));
341 if (!mlx5_priv_rxq_releasable(priv, idx)) {
343 ERROR("%p: unable to release queue index %u",
347 mlx5_priv_rxq_release(priv, idx);
348 rxq_ctrl = mlx5_priv_rxq_new(priv, idx, desc, socket, conf, mp);
350 ERROR("%p: unable to allocate queue index %u",
355 DEBUG("%p: adding RX queue %p to list",
356 (void *)dev, (void *)rxq_ctrl);
357 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
364 * DPDK callback to release a RX queue.
367 * Generic RX queue pointer.
370 mlx5_rx_queue_release(void *dpdk_rxq)
372 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
373 struct mlx5_rxq_ctrl *rxq_ctrl;
378 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
379 priv = rxq_ctrl->priv;
381 if (!mlx5_priv_rxq_releasable(priv, rxq_ctrl->rxq.stats.idx))
382 rte_panic("Rx queue %p is still used by a flow and cannot be"
383 " removed\n", (void *)rxq_ctrl);
384 mlx5_priv_rxq_release(priv, rxq_ctrl->rxq.stats.idx);
389 * Allocate queue vector and fill epoll fd list for Rx interrupts.
392 * Pointer to private structure.
395 * 0 on success, negative on failure.
398 priv_rx_intr_vec_enable(struct priv *priv)
401 unsigned int rxqs_n = priv->rxqs_n;
402 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
403 unsigned int count = 0;
404 struct rte_intr_handle *intr_handle = priv->dev->intr_handle;
406 if (!priv->dev->data->dev_conf.intr_conf.rxq)
408 priv_rx_intr_vec_disable(priv);
409 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
410 if (intr_handle->intr_vec == NULL) {
411 ERROR("failed to allocate memory for interrupt vector,"
412 " Rx interrupts will not be supported");
415 intr_handle->type = RTE_INTR_HANDLE_EXT;
416 for (i = 0; i != n; ++i) {
417 /* This rxq ibv must not be released in this function. */
418 struct mlx5_rxq_ibv *rxq_ibv = mlx5_priv_rxq_ibv_get(priv, i);
423 /* Skip queues that cannot request interrupts. */
424 if (!rxq_ibv || !rxq_ibv->channel) {
425 /* Use invalid intr_vec[] index to disable entry. */
426 intr_handle->intr_vec[i] =
427 RTE_INTR_VEC_RXTX_OFFSET +
428 RTE_MAX_RXTX_INTR_VEC_ID;
431 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
432 ERROR("too many Rx queues for interrupt vector size"
433 " (%d), Rx interrupts cannot be enabled",
434 RTE_MAX_RXTX_INTR_VEC_ID);
435 priv_rx_intr_vec_disable(priv);
438 fd = rxq_ibv->channel->fd;
439 flags = fcntl(fd, F_GETFL);
440 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
442 ERROR("failed to make Rx interrupt file descriptor"
443 " %d non-blocking for queue index %d", fd, i);
444 priv_rx_intr_vec_disable(priv);
447 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
448 intr_handle->efds[count] = fd;
452 priv_rx_intr_vec_disable(priv);
454 intr_handle->nb_efd = count;
459 * Clean up Rx interrupts handler.
462 * Pointer to private structure.
465 priv_rx_intr_vec_disable(struct priv *priv)
467 struct rte_intr_handle *intr_handle = priv->dev->intr_handle;
469 unsigned int rxqs_n = priv->rxqs_n;
470 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
472 if (!priv->dev->data->dev_conf.intr_conf.rxq)
474 if (!intr_handle->intr_vec)
476 for (i = 0; i != n; ++i) {
477 struct mlx5_rxq_ctrl *rxq_ctrl;
478 struct mlx5_rxq_data *rxq_data;
480 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
481 RTE_MAX_RXTX_INTR_VEC_ID)
484 * Need to access directly the queue to release the reference
485 * kept in priv_rx_intr_vec_enable().
487 rxq_data = (*priv->rxqs)[i];
488 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
489 mlx5_priv_rxq_ibv_release(priv, rxq_ctrl->ibv);
492 rte_intr_free_epoll_fd(intr_handle);
493 if (intr_handle->intr_vec)
494 free(intr_handle->intr_vec);
495 intr_handle->nb_efd = 0;
496 intr_handle->intr_vec = NULL;
500 * MLX5 CQ notification .
503 * Pointer to receive queue structure.
505 * Sequence number per receive queue .
508 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
511 uint32_t doorbell_hi;
513 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
515 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
516 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
517 doorbell = (uint64_t)doorbell_hi << 32;
518 doorbell |= rxq->cqn;
519 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
520 rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);
524 * DPDK callback for Rx queue interrupt enable.
527 * Pointer to Ethernet device structure.
532 * 0 on success, negative on failure.
535 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
537 struct priv *priv = dev->data->dev_private;
538 struct mlx5_rxq_data *rxq_data;
539 struct mlx5_rxq_ctrl *rxq_ctrl;
543 rxq_data = (*priv->rxqs)[rx_queue_id];
548 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
550 struct mlx5_rxq_ibv *rxq_ibv;
552 rxq_ibv = mlx5_priv_rxq_ibv_get(priv, rx_queue_id);
557 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
558 mlx5_priv_rxq_ibv_release(priv, rxq_ibv);
563 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
568 * DPDK callback for Rx queue interrupt disable.
571 * Pointer to Ethernet device structure.
576 * 0 on success, negative on failure.
579 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
581 struct priv *priv = dev->data->dev_private;
582 struct mlx5_rxq_data *rxq_data;
583 struct mlx5_rxq_ctrl *rxq_ctrl;
584 struct mlx5_rxq_ibv *rxq_ibv = NULL;
585 struct ibv_cq *ev_cq;
590 rxq_data = (*priv->rxqs)[rx_queue_id];
595 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
598 rxq_ibv = mlx5_priv_rxq_ibv_get(priv, rx_queue_id);
603 ret = ibv_get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
604 if (ret || ev_cq != rxq_ibv->cq) {
608 rxq_data->cq_arm_sn++;
609 ibv_ack_cq_events(rxq_ibv->cq, 1);
612 mlx5_priv_rxq_ibv_release(priv, rxq_ibv);
615 WARN("unable to disable interrupt on rx queue %d",
621 * Create the Rx queue Verbs object.
624 * Pointer to private structure.
626 * Queue index in DPDK Rx queue array
629 * The Verbs object initialised if it can be created.
632 mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
634 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
635 struct mlx5_rxq_ctrl *rxq_ctrl =
636 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
637 struct ibv_wq_attr mod;
640 struct ibv_cq_init_attr_ex ibv;
641 struct mlx5dv_cq_init_attr mlx5;
643 struct ibv_wq_init_attr wq;
644 struct ibv_cq_ex cq_attr;
646 unsigned int cqe_n = (1 << rxq_data->elts_n) - 1;
647 struct mlx5_rxq_ibv *tmpl;
648 struct mlx5dv_cq cq_info;
649 struct mlx5dv_rwq rwq;
652 struct mlx5dv_obj obj;
653 struct mlx5_dev_config *config = &priv->config;
656 assert(!rxq_ctrl->ibv);
657 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
660 ERROR("%p: cannot allocate verbs resources",
664 tmpl->rxq_ctrl = rxq_ctrl;
665 /* Use the entire RX mempool as the memory region. */
666 tmpl->mr = priv_mr_get(priv, rxq_data->mp);
668 tmpl->mr = priv_mr_new(priv, rxq_data->mp);
670 ERROR("%p: MR creation failure", (void *)rxq_ctrl);
675 tmpl->channel = ibv_create_comp_channel(priv->ctx);
676 if (!tmpl->channel) {
677 ERROR("%p: Comp Channel creation failure",
682 attr.cq.ibv = (struct ibv_cq_init_attr_ex){
684 .channel = tmpl->channel,
687 attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
690 if (config->cqe_comp && !rxq_data->hw_timestamp) {
691 attr.cq.mlx5.comp_mask |=
692 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
693 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
695 * For vectorized Rx, it must not be doubled in order to
696 * make cq_ci and rq_ci aligned.
698 if (rxq_check_vec_support(rxq_data) < 0)
699 attr.cq.ibv.cqe *= 2;
700 } else if (config->cqe_comp && rxq_data->hw_timestamp) {
701 DEBUG("Rx CQE compression is disabled for HW timestamp");
703 tmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,
705 if (tmpl->cq == NULL) {
706 ERROR("%p: CQ creation failure", (void *)rxq_ctrl);
709 DEBUG("priv->device_attr.max_qp_wr is %d",
710 priv->device_attr.orig_attr.max_qp_wr);
711 DEBUG("priv->device_attr.max_sge is %d",
712 priv->device_attr.orig_attr.max_sge);
713 attr.wq = (struct ibv_wq_init_attr){
714 .wq_context = NULL, /* Could be useful in the future. */
715 .wq_type = IBV_WQT_RQ,
716 /* Max number of outstanding WRs. */
717 .max_wr = (1 << rxq_data->elts_n) >> rxq_data->sges_n,
718 /* Max number of scatter/gather elements in a WR. */
719 .max_sge = 1 << rxq_data->sges_n,
723 IBV_WQ_FLAGS_CVLAN_STRIPPING |
725 .create_flags = (rxq_data->vlan_strip ?
726 IBV_WQ_FLAGS_CVLAN_STRIPPING :
729 /* By default, FCS (CRC) is stripped by hardware. */
730 if (rxq_data->crc_present) {
731 attr.wq.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
732 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
734 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
735 if (config->hw_padding) {
736 attr.wq.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
737 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
740 tmpl->wq = ibv_create_wq(priv->ctx, &attr.wq);
741 if (tmpl->wq == NULL) {
742 ERROR("%p: WQ creation failure", (void *)rxq_ctrl);
746 * Make sure number of WRs*SGEs match expectations since a queue
747 * cannot allocate more than "desc" buffers.
749 if (((int)attr.wq.max_wr !=
750 ((1 << rxq_data->elts_n) >> rxq_data->sges_n)) ||
751 ((int)attr.wq.max_sge != (1 << rxq_data->sges_n))) {
752 ERROR("%p: requested %u*%u but got %u*%u WRs*SGEs",
754 ((1 << rxq_data->elts_n) >> rxq_data->sges_n),
755 (1 << rxq_data->sges_n),
756 attr.wq.max_wr, attr.wq.max_sge);
759 /* Change queue state to ready. */
760 mod = (struct ibv_wq_attr){
761 .attr_mask = IBV_WQ_ATTR_STATE,
762 .wq_state = IBV_WQS_RDY,
764 ret = ibv_modify_wq(tmpl->wq, &mod);
766 ERROR("%p: WQ state to IBV_WQS_RDY failed",
770 obj.cq.in = tmpl->cq;
771 obj.cq.out = &cq_info;
772 obj.rwq.in = tmpl->wq;
774 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
777 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
778 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
779 "it should be set to %u", RTE_CACHE_LINE_SIZE);
782 /* Fill the rings. */
783 rxq_data->wqes = (volatile struct mlx5_wqe_data_seg (*)[])
785 for (i = 0; (i != (unsigned int)(1 << rxq_data->elts_n)); ++i) {
786 struct rte_mbuf *buf = (*rxq_data->elts)[i];
787 volatile struct mlx5_wqe_data_seg *scat = &(*rxq_data->wqes)[i];
789 /* scat->addr must be able to store a pointer. */
790 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
791 *scat = (struct mlx5_wqe_data_seg){
792 .addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
794 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
795 .lkey = tmpl->mr->lkey,
798 rxq_data->rq_db = rwq.dbrec;
799 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
803 rxq_data->zip = (struct rxq_zip){
806 rxq_data->cq_db = cq_info.dbrec;
807 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
808 rxq_data->cq_uar = cq_info.cq_uar;
809 rxq_data->cqn = cq_info.cqn;
810 rxq_data->cq_arm_sn = 0;
811 /* Update doorbell counter. */
812 rxq_data->rq_ci = (1 << rxq_data->elts_n) >> rxq_data->sges_n;
814 *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
815 DEBUG("%p: rxq updated with %p", (void *)rxq_ctrl, (void *)&tmpl);
816 rte_atomic32_inc(&tmpl->refcnt);
817 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
818 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
819 LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
823 claim_zero(ibv_destroy_wq(tmpl->wq));
825 claim_zero(ibv_destroy_cq(tmpl->cq));
827 claim_zero(ibv_destroy_comp_channel(tmpl->channel));
829 priv_mr_release(priv, tmpl->mr);
834 * Get an Rx queue Verbs object.
837 * Pointer to private structure.
839 * Queue index in DPDK Rx queue array
842 * The Verbs object if it exists.
845 mlx5_priv_rxq_ibv_get(struct priv *priv, uint16_t idx)
847 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
848 struct mlx5_rxq_ctrl *rxq_ctrl;
850 if (idx >= priv->rxqs_n)
854 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
856 priv_mr_get(priv, rxq_data->mp);
857 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
858 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
859 (void *)rxq_ctrl->ibv,
860 rte_atomic32_read(&rxq_ctrl->ibv->refcnt));
862 return rxq_ctrl->ibv;
866 * Release an Rx verbs queue object.
869 * Pointer to private structure.
871 * Verbs Rx queue object.
874 * 0 on success, errno value on failure.
877 mlx5_priv_rxq_ibv_release(struct priv *priv, struct mlx5_rxq_ibv *rxq_ibv)
885 ret = priv_mr_release(priv, rxq_ibv->mr);
888 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
889 (void *)rxq_ibv, rte_atomic32_read(&rxq_ibv->refcnt));
890 if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
891 rxq_free_elts(rxq_ibv->rxq_ctrl);
892 claim_zero(ibv_destroy_wq(rxq_ibv->wq));
893 claim_zero(ibv_destroy_cq(rxq_ibv->cq));
894 if (rxq_ibv->channel)
895 claim_zero(ibv_destroy_comp_channel(rxq_ibv->channel));
896 LIST_REMOVE(rxq_ibv, next);
904 * Verify the Verbs Rx queue list is empty
907 * Pointer to private structure.
909 * @return the number of object not released.
912 mlx5_priv_rxq_ibv_verify(struct priv *priv)
915 struct mlx5_rxq_ibv *rxq_ibv;
917 LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
918 DEBUG("%p: Verbs Rx queue %p still referenced", (void *)priv,
926 * Return true if a single reference exists on the object.
929 * Pointer to private structure.
931 * Verbs Rx queue object.
934 mlx5_priv_rxq_ibv_releasable(struct priv *priv, struct mlx5_rxq_ibv *rxq_ibv)
938 return (rte_atomic32_read(&rxq_ibv->refcnt) == 1);
942 * Create a DPDK Rx queue.
945 * Pointer to private structure.
949 * Number of descriptors to configure in queue.
951 * NUMA socket on which memory must be allocated.
954 * A DPDK queue object on success.
956 struct mlx5_rxq_ctrl*
957 mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc,
958 unsigned int socket, const struct rte_eth_rxconf *conf,
959 struct rte_mempool *mp)
961 struct rte_eth_dev *dev = priv->dev;
962 struct mlx5_rxq_ctrl *tmpl;
963 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
964 struct mlx5_dev_config *config = &priv->config;
966 * Always allocate extra slots, even if eventually
967 * the vector Rx will not be used.
969 const uint16_t desc_n =
970 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
972 tmpl = rte_calloc_socket("RXQ", 1,
974 desc_n * sizeof(struct rte_mbuf *),
978 tmpl->socket = socket;
979 if (priv->dev->data->dev_conf.intr_conf.rxq)
981 /* Enable scattered packets support for this queue if necessary. */
982 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
983 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
984 (mb_len - RTE_PKTMBUF_HEADROOM)) {
985 tmpl->rxq.sges_n = 0;
986 } else if (conf->offloads & DEV_RX_OFFLOAD_SCATTER) {
988 RTE_PKTMBUF_HEADROOM +
989 dev->data->dev_conf.rxmode.max_rx_pkt_len;
993 * Determine the number of SGEs needed for a full packet
994 * and round it to the next power of two.
996 sges_n = log2above((size / mb_len) + !!(size % mb_len));
997 tmpl->rxq.sges_n = sges_n;
998 /* Make sure rxq.sges_n did not overflow. */
999 size = mb_len * (1 << tmpl->rxq.sges_n);
1000 size -= RTE_PKTMBUF_HEADROOM;
1001 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1002 ERROR("%p: too many SGEs (%u) needed to handle"
1003 " requested maximum packet size %u",
1006 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1010 WARN("%p: the requested maximum Rx packet size (%u) is"
1011 " larger than a single mbuf (%u) and scattered"
1012 " mode has not been requested",
1014 dev->data->dev_conf.rxmode.max_rx_pkt_len,
1015 mb_len - RTE_PKTMBUF_HEADROOM);
1017 DEBUG("%p: maximum number of segments per packet: %u",
1018 (void *)dev, 1 << tmpl->rxq.sges_n);
1019 if (desc % (1 << tmpl->rxq.sges_n)) {
1020 ERROR("%p: number of RX queue descriptors (%u) is not a"
1021 " multiple of SGEs per packet (%u)",
1024 1 << tmpl->rxq.sges_n);
1027 /* Toggle RX checksum offload if hardware supports it. */
1028 tmpl->rxq.csum = !!(conf->offloads & DEV_RX_OFFLOAD_CHECKSUM);
1029 tmpl->rxq.csum_l2tun = (!!(conf->offloads & DEV_RX_OFFLOAD_CHECKSUM) &&
1030 priv->config.hw_csum_l2tun);
1031 tmpl->rxq.hw_timestamp = !!(conf->offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1032 /* Configure VLAN stripping. */
1033 tmpl->rxq.vlan_strip = !!(conf->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1034 /* By default, FCS (CRC) is stripped by hardware. */
1035 if (conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
1036 tmpl->rxq.crc_present = 0;
1037 } else if (config->hw_fcs_strip) {
1038 tmpl->rxq.crc_present = 1;
1040 WARN("%p: CRC stripping has been disabled but will still"
1041 " be performed by hardware, make sure MLNX_OFED and"
1042 " firmware are up to date",
1044 tmpl->rxq.crc_present = 0;
1046 DEBUG("%p: CRC stripping is %s, %u bytes will be subtracted from"
1047 " incoming frames to hide it",
1049 tmpl->rxq.crc_present ? "disabled" : "enabled",
1050 tmpl->rxq.crc_present << 2);
1052 tmpl->rxq.rss_hash = priv->rxqs_n > 1;
1053 tmpl->rxq.port_id = dev->data->port_id;
1056 tmpl->rxq.stats.idx = idx;
1057 tmpl->rxq.elts_n = log2above(desc);
1059 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1060 rte_atomic32_inc(&tmpl->refcnt);
1061 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
1062 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
1063 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1074 * Pointer to private structure.
1079 * A pointer to the queue if it exists.
1081 struct mlx5_rxq_ctrl*
1082 mlx5_priv_rxq_get(struct priv *priv, uint16_t idx)
1084 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1086 if ((*priv->rxqs)[idx]) {
1087 rxq_ctrl = container_of((*priv->rxqs)[idx],
1088 struct mlx5_rxq_ctrl,
1091 mlx5_priv_rxq_ibv_get(priv, idx);
1092 rte_atomic32_inc(&rxq_ctrl->refcnt);
1093 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
1094 (void *)rxq_ctrl, rte_atomic32_read(&rxq_ctrl->refcnt));
1100 * Release a Rx queue.
1103 * Pointer to private structure.
1108 * 0 on success, errno value on failure.
1111 mlx5_priv_rxq_release(struct priv *priv, uint16_t idx)
1113 struct mlx5_rxq_ctrl *rxq_ctrl;
1115 if (!(*priv->rxqs)[idx])
1117 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1118 assert(rxq_ctrl->priv);
1119 if (rxq_ctrl->ibv) {
1122 ret = mlx5_priv_rxq_ibv_release(rxq_ctrl->priv, rxq_ctrl->ibv);
1124 rxq_ctrl->ibv = NULL;
1126 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
1127 (void *)rxq_ctrl, rte_atomic32_read(&rxq_ctrl->refcnt));
1128 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1129 LIST_REMOVE(rxq_ctrl, next);
1131 (*priv->rxqs)[idx] = NULL;
1138 * Verify if the queue can be released.
1141 * Pointer to private structure.
1146 * 1 if the queue can be released.
1149 mlx5_priv_rxq_releasable(struct priv *priv, uint16_t idx)
1151 struct mlx5_rxq_ctrl *rxq_ctrl;
1153 if (!(*priv->rxqs)[idx])
1155 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1156 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1160 * Verify the Rx Queue list is empty
1163 * Pointer to private structure.
1165 * @return the number of object not released.
1168 mlx5_priv_rxq_verify(struct priv *priv)
1170 struct mlx5_rxq_ctrl *rxq_ctrl;
1173 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1174 DEBUG("%p: Rx Queue %p still referenced", (void *)priv,
1182 * Create an indirection table.
1185 * Pointer to private structure.
1187 * Queues entering in the indirection table.
1189 * Number of queues in the array.
1192 * A new indirection table.
1194 struct mlx5_ind_table_ibv*
1195 mlx5_priv_ind_table_ibv_new(struct priv *priv, uint16_t queues[],
1198 struct mlx5_ind_table_ibv *ind_tbl;
1199 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1200 log2above(queues_n) :
1201 log2above(priv->ind_table_max_size);
1202 struct ibv_wq *wq[1 << wq_n];
1206 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1207 queues_n * sizeof(uint16_t), 0);
1210 for (i = 0; i != queues_n; ++i) {
1211 struct mlx5_rxq_ctrl *rxq =
1212 mlx5_priv_rxq_get(priv, queues[i]);
1216 wq[i] = rxq->ibv->wq;
1217 ind_tbl->queues[i] = queues[i];
1219 ind_tbl->queues_n = queues_n;
1220 /* Finalise indirection table. */
1221 for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1223 ind_tbl->ind_table = ibv_create_rwq_ind_table(
1225 &(struct ibv_rwq_ind_table_init_attr){
1226 .log_ind_tbl_size = wq_n,
1230 if (!ind_tbl->ind_table)
1232 rte_atomic32_inc(&ind_tbl->refcnt);
1233 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1234 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1235 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1239 DEBUG("%p cannot create indirection table", (void *)priv);
1244 * Get an indirection table.
1247 * Pointer to private structure.
1249 * Queues entering in the indirection table.
1251 * Number of queues in the array.
1254 * An indirection table if found.
1256 struct mlx5_ind_table_ibv*
1257 mlx5_priv_ind_table_ibv_get(struct priv *priv, uint16_t queues[],
1260 struct mlx5_ind_table_ibv *ind_tbl;
1262 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1263 if ((ind_tbl->queues_n == queues_n) &&
1264 (memcmp(ind_tbl->queues, queues,
1265 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1272 rte_atomic32_inc(&ind_tbl->refcnt);
1273 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1274 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1275 for (i = 0; i != ind_tbl->queues_n; ++i)
1276 mlx5_priv_rxq_get(priv, ind_tbl->queues[i]);
1282 * Release an indirection table.
1285 * Pointer to private structure.
1287 * Indirection table to release.
1290 * 0 on success, errno value on failure.
1293 mlx5_priv_ind_table_ibv_release(struct priv *priv,
1294 struct mlx5_ind_table_ibv *ind_tbl)
1298 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1299 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1300 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1301 claim_zero(ibv_destroy_rwq_ind_table(ind_tbl->ind_table));
1302 for (i = 0; i != ind_tbl->queues_n; ++i)
1303 claim_nonzero(mlx5_priv_rxq_release(priv, ind_tbl->queues[i]));
1304 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1305 LIST_REMOVE(ind_tbl, next);
1313 * Verify the Rx Queue list is empty
1316 * Pointer to private structure.
1318 * @return the number of object not released.
1321 mlx5_priv_ind_table_ibv_verify(struct priv *priv)
1323 struct mlx5_ind_table_ibv *ind_tbl;
1326 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1327 DEBUG("%p: Verbs indirection table %p still referenced",
1328 (void *)priv, (void *)ind_tbl);
1335 * Create an Rx Hash queue.
1338 * Pointer to private structure.
1340 * RSS key for the Rx hash queue.
1341 * @param rss_key_len
1343 * @param hash_fields
1344 * Verbs protocol hash field to make the RSS on.
1346 * Queues entering in hash queue. In case of empty hash_fields only the
1347 * first queue index will be taken for the indirection table.
1352 * An hash Rx queue on success.
1355 mlx5_priv_hrxq_new(struct priv *priv, uint8_t *rss_key, uint8_t rss_key_len,
1356 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1358 struct mlx5_hrxq *hrxq;
1359 struct mlx5_ind_table_ibv *ind_tbl;
1362 queues_n = hash_fields ? queues_n : 1;
1363 ind_tbl = mlx5_priv_ind_table_ibv_get(priv, queues, queues_n);
1365 ind_tbl = mlx5_priv_ind_table_ibv_new(priv, queues, queues_n);
1368 qp = ibv_create_qp_ex(
1370 &(struct ibv_qp_init_attr_ex){
1371 .qp_type = IBV_QPT_RAW_PACKET,
1373 IBV_QP_INIT_ATTR_PD |
1374 IBV_QP_INIT_ATTR_IND_TABLE |
1375 IBV_QP_INIT_ATTR_RX_HASH,
1376 .rx_hash_conf = (struct ibv_rx_hash_conf){
1377 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1378 .rx_hash_key_len = rss_key_len,
1379 .rx_hash_key = rss_key,
1380 .rx_hash_fields_mask = hash_fields,
1382 .rwq_ind_tbl = ind_tbl->ind_table,
1387 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1390 hrxq->ind_table = ind_tbl;
1392 hrxq->rss_key_len = rss_key_len;
1393 hrxq->hash_fields = hash_fields;
1394 memcpy(hrxq->rss_key, rss_key, rss_key_len);
1395 rte_atomic32_inc(&hrxq->refcnt);
1396 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1397 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1398 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1401 mlx5_priv_ind_table_ibv_release(priv, ind_tbl);
1403 claim_zero(ibv_destroy_qp(qp));
1408 * Get an Rx Hash queue.
1411 * Pointer to private structure.
1413 * RSS configuration for the Rx hash queue.
1415 * Queues entering in hash queue. In case of empty hash_fields only the
1416 * first queue index will be taken for the indirection table.
1421 * An hash Rx queue on success.
1424 mlx5_priv_hrxq_get(struct priv *priv, uint8_t *rss_key, uint8_t rss_key_len,
1425 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1427 struct mlx5_hrxq *hrxq;
1429 queues_n = hash_fields ? queues_n : 1;
1430 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1431 struct mlx5_ind_table_ibv *ind_tbl;
1433 if (hrxq->rss_key_len != rss_key_len)
1435 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1437 if (hrxq->hash_fields != hash_fields)
1439 ind_tbl = mlx5_priv_ind_table_ibv_get(priv, queues, queues_n);
1442 if (ind_tbl != hrxq->ind_table) {
1443 mlx5_priv_ind_table_ibv_release(priv, ind_tbl);
1446 rte_atomic32_inc(&hrxq->refcnt);
1447 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1448 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1455 * Release the hash Rx queue.
1458 * Pointer to private structure.
1460 * Pointer to Hash Rx queue to release.
1463 * 0 on success, errno value on failure.
1466 mlx5_priv_hrxq_release(struct priv *priv, struct mlx5_hrxq *hrxq)
1468 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1469 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1470 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1471 claim_zero(ibv_destroy_qp(hrxq->qp));
1472 mlx5_priv_ind_table_ibv_release(priv, hrxq->ind_table);
1473 LIST_REMOVE(hrxq, next);
1477 claim_nonzero(mlx5_priv_ind_table_ibv_release(priv, hrxq->ind_table));
1482 * Verify the Rx Queue list is empty
1485 * Pointer to private structure.
1487 * @return the number of object not released.
1490 mlx5_priv_hrxq_ibv_verify(struct priv *priv)
1492 struct mlx5_hrxq *hrxq;
1495 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1496 DEBUG("%p: Verbs Hash Rx queue %p still referenced",
1497 (void *)priv, (void *)hrxq);