1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 #include <sys/queue.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
29 #include <rte_interrupts.h>
30 #include <rte_debug.h>
34 #include "mlx5_rxtx.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
38 #include "mlx5_glue.h"
40 /* Default RSS hash key also used for ConnectX-3. */
41 uint8_t rss_hash_default_key[] = {
42 0x2c, 0xc6, 0x81, 0xd1,
43 0x5b, 0xdb, 0xf4, 0xf7,
44 0xfc, 0xa2, 0x83, 0x19,
45 0xdb, 0x1a, 0x3e, 0x94,
46 0x6b, 0x9e, 0x38, 0xd9,
47 0x2c, 0x9c, 0x03, 0xd1,
48 0xad, 0x99, 0x44, 0xa7,
49 0xd9, 0x56, 0x3d, 0x59,
50 0x06, 0x3c, 0x25, 0xf3,
51 0xfc, 0x1f, 0xdc, 0x2a,
54 /* Length of the default RSS hash key. */
55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
56 (unsigned int)sizeof(rss_hash_default_key),
57 "wrong RSS default key size.");
60 * Check whether Multi-Packet RQ can be enabled for the device.
63 * Pointer to Ethernet device.
66 * 1 if supported, negative errno value if not.
69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
71 struct mlx5_priv *priv = dev->data->dev_private;
73 if (priv->config.mprq.enabled &&
74 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
80 * Check whether Multi-Packet RQ is enabled for the Rx queue.
83 * Pointer to receive queue structure.
86 * 0 if disabled, otherwise enabled.
89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
91 return rxq->strd_num_n > 0;
95 * Check whether Multi-Packet RQ is enabled for the device.
98 * Pointer to Ethernet device.
101 * 0 if disabled, otherwise enabled.
104 mlx5_mprq_enabled(struct rte_eth_dev *dev)
106 struct mlx5_priv *priv = dev->data->dev_private;
111 if (mlx5_check_mprq_support(dev) < 0)
113 /* All the configured queues should be enabled. */
114 for (i = 0; i < priv->rxqs_n; ++i) {
115 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
116 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
117 (rxq, struct mlx5_rxq_ctrl, rxq);
119 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
122 if (mlx5_rxq_mprq_enabled(rxq))
125 /* Multi-Packet RQ can't be partially configured. */
126 assert(n == 0 || n == n_ibv);
131 * Allocate RX queue elements for Multi-Packet RQ.
134 * Pointer to RX queue structure.
137 * 0 on success, a negative errno value otherwise and rte_errno is set.
140 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
142 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
143 unsigned int wqe_n = 1 << rxq->elts_n;
147 /* Iterate on segments. */
148 for (i = 0; i <= wqe_n; ++i) {
149 struct mlx5_mprq_buf *buf;
151 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
152 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
157 (*rxq->mprq_bufs)[i] = buf;
159 rxq->mprq_repl = buf;
162 "port %u Rx queue %u allocated and configured %u segments",
163 rxq->port_id, rxq->idx, wqe_n);
166 err = rte_errno; /* Save rte_errno before cleanup. */
168 for (i = 0; (i != wqe_n); ++i) {
169 if ((*rxq->mprq_bufs)[i] != NULL)
170 rte_mempool_put(rxq->mprq_mp,
171 (*rxq->mprq_bufs)[i]);
172 (*rxq->mprq_bufs)[i] = NULL;
174 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
175 rxq->port_id, rxq->idx);
176 rte_errno = err; /* Restore rte_errno. */
181 * Allocate RX queue elements for Single-Packet RQ.
184 * Pointer to RX queue structure.
187 * 0 on success, errno value on failure.
190 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
192 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
193 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
197 /* Iterate on segments. */
198 for (i = 0; (i != elts_n); ++i) {
199 struct rte_mbuf *buf;
201 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
203 DRV_LOG(ERR, "port %u empty mbuf pool",
204 PORT_ID(rxq_ctrl->priv));
208 /* Headroom is reserved by rte_pktmbuf_alloc(). */
209 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
210 /* Buffer is supposed to be empty. */
211 assert(rte_pktmbuf_data_len(buf) == 0);
212 assert(rte_pktmbuf_pkt_len(buf) == 0);
214 /* Only the first segment keeps headroom. */
216 SET_DATA_OFF(buf, 0);
217 PORT(buf) = rxq_ctrl->rxq.port_id;
218 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
219 PKT_LEN(buf) = DATA_LEN(buf);
221 (*rxq_ctrl->rxq.elts)[i] = buf;
223 /* If Rx vector is activated. */
224 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
225 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
226 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
229 /* Initialize default rearm_data for vPMD. */
230 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
231 rte_mbuf_refcnt_set(mbuf_init, 1);
232 mbuf_init->nb_segs = 1;
233 mbuf_init->port = rxq->port_id;
235 * prevent compiler reordering:
236 * rearm_data covers previous fields.
238 rte_compiler_barrier();
239 rxq->mbuf_initializer =
240 *(uint64_t *)&mbuf_init->rearm_data;
241 /* Padding with a fake mbuf for vectorized Rx. */
242 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
243 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
246 "port %u Rx queue %u allocated and configured %u segments"
248 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
249 elts_n / (1 << rxq_ctrl->rxq.sges_n));
252 err = rte_errno; /* Save rte_errno before cleanup. */
254 for (i = 0; (i != elts_n); ++i) {
255 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
256 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
257 (*rxq_ctrl->rxq.elts)[i] = NULL;
259 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
260 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
261 rte_errno = err; /* Restore rte_errno. */
266 * Allocate RX queue elements.
269 * Pointer to RX queue structure.
272 * 0 on success, errno value on failure.
275 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
277 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
278 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
282 * Free RX queue elements for Multi-Packet RQ.
285 * Pointer to RX queue structure.
288 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
290 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
293 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
294 rxq->port_id, rxq->idx);
295 if (rxq->mprq_bufs == NULL)
297 assert(mlx5_rxq_check_vec_support(rxq) < 0);
298 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
299 if ((*rxq->mprq_bufs)[i] != NULL)
300 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
301 (*rxq->mprq_bufs)[i] = NULL;
303 if (rxq->mprq_repl != NULL) {
304 mlx5_mprq_buf_free(rxq->mprq_repl);
305 rxq->mprq_repl = NULL;
310 * Free RX queue elements for Single-Packet RQ.
313 * Pointer to RX queue structure.
316 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
318 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
319 const uint16_t q_n = (1 << rxq->elts_n);
320 const uint16_t q_mask = q_n - 1;
321 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
324 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
325 PORT_ID(rxq_ctrl->priv), rxq->idx);
326 if (rxq->elts == NULL)
329 * Some mbuf in the Ring belongs to the application. They cannot be
332 if (mlx5_rxq_check_vec_support(rxq) > 0) {
333 for (i = 0; i < used; ++i)
334 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
335 rxq->rq_pi = rxq->rq_ci;
337 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
338 if ((*rxq->elts)[i] != NULL)
339 rte_pktmbuf_free_seg((*rxq->elts)[i]);
340 (*rxq->elts)[i] = NULL;
345 * Free RX queue elements.
348 * Pointer to RX queue structure.
351 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
353 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
354 rxq_free_elts_mprq(rxq_ctrl);
356 rxq_free_elts_sprq(rxq_ctrl);
360 * Returns the per-queue supported offloads.
363 * Pointer to Ethernet device.
366 * Supported Rx offloads.
369 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
371 struct mlx5_priv *priv = dev->data->dev_private;
372 struct mlx5_dev_config *config = &priv->config;
373 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
374 DEV_RX_OFFLOAD_TIMESTAMP |
375 DEV_RX_OFFLOAD_JUMBO_FRAME |
376 DEV_RX_OFFLOAD_RSS_HASH);
378 if (config->hw_fcs_strip)
379 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
382 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
383 DEV_RX_OFFLOAD_UDP_CKSUM |
384 DEV_RX_OFFLOAD_TCP_CKSUM);
385 if (config->hw_vlan_strip)
386 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
387 if (MLX5_LRO_SUPPORTED(dev))
388 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
394 * Returns the per-port supported offloads.
397 * Supported Rx offloads.
400 mlx5_get_rx_port_offloads(void)
402 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
408 * Verify if the queue can be released.
411 * Pointer to Ethernet device.
416 * 1 if the queue can be released
417 * 0 if the queue can not be released, there are references to it.
418 * Negative errno and rte_errno is set if queue doesn't exist.
421 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
423 struct mlx5_priv *priv = dev->data->dev_private;
424 struct mlx5_rxq_ctrl *rxq_ctrl;
426 if (!(*priv->rxqs)[idx]) {
430 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
431 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
435 * Rx queue presetup checks.
438 * Pointer to Ethernet device structure.
442 * Number of descriptors to configure in queue.
445 * 0 on success, a negative errno value otherwise and rte_errno is set.
448 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
450 struct mlx5_priv *priv = dev->data->dev_private;
452 if (!rte_is_power_of_2(desc)) {
453 desc = 1 << log2above(desc);
455 "port %u increased number of descriptors in Rx queue %u"
456 " to the next power of two (%d)",
457 dev->data->port_id, idx, desc);
459 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
460 dev->data->port_id, idx, desc);
461 if (idx >= priv->rxqs_n) {
462 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
463 dev->data->port_id, idx, priv->rxqs_n);
464 rte_errno = EOVERFLOW;
467 if (!mlx5_rxq_releasable(dev, idx)) {
468 DRV_LOG(ERR, "port %u unable to release queue index %u",
469 dev->data->port_id, idx);
473 mlx5_rxq_release(dev, idx);
480 * Pointer to Ethernet device structure.
484 * Number of descriptors to configure in queue.
486 * NUMA socket on which memory must be allocated.
488 * Thresholds parameters.
490 * Memory pool for buffer allocations.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
497 unsigned int socket, const struct rte_eth_rxconf *conf,
498 struct rte_mempool *mp)
500 struct mlx5_priv *priv = dev->data->dev_private;
501 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
502 struct mlx5_rxq_ctrl *rxq_ctrl =
503 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
506 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
509 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
511 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
512 dev->data->port_id, idx);
516 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
517 dev->data->port_id, idx);
518 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
525 * Pointer to Ethernet device structure.
529 * Number of descriptors to configure in queue.
530 * @param hairpin_conf
531 * Hairpin configuration parameters.
534 * 0 on success, a negative errno value otherwise and rte_errno is set.
537 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
539 const struct rte_eth_hairpin_conf *hairpin_conf)
541 struct mlx5_priv *priv = dev->data->dev_private;
542 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
543 struct mlx5_rxq_ctrl *rxq_ctrl =
544 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
547 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
550 if (hairpin_conf->peer_count != 1 ||
551 hairpin_conf->peers[0].port != dev->data->port_id ||
552 hairpin_conf->peers[0].queue >= priv->txqs_n) {
553 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
554 " invalid hairpind configuration", dev->data->port_id,
559 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
561 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
562 dev->data->port_id, idx);
566 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
567 dev->data->port_id, idx);
568 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
573 * DPDK callback to release a RX queue.
576 * Generic RX queue pointer.
579 mlx5_rx_queue_release(void *dpdk_rxq)
581 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
582 struct mlx5_rxq_ctrl *rxq_ctrl;
583 struct mlx5_priv *priv;
587 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
588 priv = rxq_ctrl->priv;
589 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
590 rte_panic("port %u Rx queue %u is still used by a flow and"
591 " cannot be removed\n",
592 PORT_ID(priv), rxq->idx);
593 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
597 * Get an Rx queue Verbs/DevX object.
600 * Pointer to Ethernet device.
602 * Queue index in DPDK Rx queue array
605 * The Verbs/DevX object if it exists.
607 static struct mlx5_rxq_obj *
608 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
610 struct mlx5_priv *priv = dev->data->dev_private;
611 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
612 struct mlx5_rxq_ctrl *rxq_ctrl;
614 if (idx >= priv->rxqs_n)
618 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
620 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
621 return rxq_ctrl->obj;
625 * Release the resources allocated for an RQ DevX object.
628 * DevX Rx queue object.
631 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
633 if (rxq_ctrl->rxq.wqes) {
634 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
635 rxq_ctrl->rxq.wqes = NULL;
637 if (rxq_ctrl->wq_umem) {
638 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
639 rxq_ctrl->wq_umem = NULL;
644 * Release an Rx hairpin related resources.
647 * Hairpin Rx queue object.
650 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
652 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
655 rq_attr.state = MLX5_RQC_STATE_RST;
656 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
657 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
658 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
662 * Release an Rx verbs/DevX queue object.
665 * Verbs/DevX Rx queue object.
668 * 1 while a reference on it exists, 0 when freed.
671 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
674 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
675 switch (rxq_obj->type) {
676 case MLX5_RXQ_OBJ_TYPE_IBV:
679 rxq_free_elts(rxq_obj->rxq_ctrl);
680 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
681 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
683 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
686 rxq_free_elts(rxq_obj->rxq_ctrl);
687 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
688 rxq_release_rq_resources(rxq_obj->rxq_ctrl);
689 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
691 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
693 rxq_obj_hairpin_release(rxq_obj);
696 if (rxq_obj->channel)
697 claim_zero(mlx5_glue->destroy_comp_channel
699 LIST_REMOVE(rxq_obj, next);
707 * Allocate queue vector and fill epoll fd list for Rx interrupts.
710 * Pointer to Ethernet device.
713 * 0 on success, a negative errno value otherwise and rte_errno is set.
716 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
718 struct mlx5_priv *priv = dev->data->dev_private;
720 unsigned int rxqs_n = priv->rxqs_n;
721 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
722 unsigned int count = 0;
723 struct rte_intr_handle *intr_handle = dev->intr_handle;
725 if (!dev->data->dev_conf.intr_conf.rxq)
727 mlx5_rx_intr_vec_disable(dev);
728 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
729 if (intr_handle->intr_vec == NULL) {
731 "port %u failed to allocate memory for interrupt"
732 " vector, Rx interrupts will not be supported",
737 intr_handle->type = RTE_INTR_HANDLE_EXT;
738 for (i = 0; i != n; ++i) {
739 /* This rxq obj must not be released in this function. */
740 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
745 /* Skip queues that cannot request interrupts. */
746 if (!rxq_obj || !rxq_obj->channel) {
747 /* Use invalid intr_vec[] index to disable entry. */
748 intr_handle->intr_vec[i] =
749 RTE_INTR_VEC_RXTX_OFFSET +
750 RTE_MAX_RXTX_INTR_VEC_ID;
753 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
755 "port %u too many Rx queues for interrupt"
756 " vector size (%d), Rx interrupts cannot be"
758 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
759 mlx5_rx_intr_vec_disable(dev);
763 fd = rxq_obj->channel->fd;
764 flags = fcntl(fd, F_GETFL);
765 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
769 "port %u failed to make Rx interrupt file"
770 " descriptor %d non-blocking for queue index"
772 dev->data->port_id, fd, i);
773 mlx5_rx_intr_vec_disable(dev);
776 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
777 intr_handle->efds[count] = fd;
781 mlx5_rx_intr_vec_disable(dev);
783 intr_handle->nb_efd = count;
788 * Clean up Rx interrupts handler.
791 * Pointer to Ethernet device.
794 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
796 struct mlx5_priv *priv = dev->data->dev_private;
797 struct rte_intr_handle *intr_handle = dev->intr_handle;
799 unsigned int rxqs_n = priv->rxqs_n;
800 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
802 if (!dev->data->dev_conf.intr_conf.rxq)
804 if (!intr_handle->intr_vec)
806 for (i = 0; i != n; ++i) {
807 struct mlx5_rxq_ctrl *rxq_ctrl;
808 struct mlx5_rxq_data *rxq_data;
810 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
811 RTE_MAX_RXTX_INTR_VEC_ID)
814 * Need to access directly the queue to release the reference
815 * kept in mlx5_rx_intr_vec_enable().
817 rxq_data = (*priv->rxqs)[i];
818 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
820 mlx5_rxq_obj_release(rxq_ctrl->obj);
823 rte_intr_free_epoll_fd(intr_handle);
824 if (intr_handle->intr_vec)
825 free(intr_handle->intr_vec);
826 intr_handle->nb_efd = 0;
827 intr_handle->intr_vec = NULL;
831 * MLX5 CQ notification .
834 * Pointer to receive queue structure.
836 * Sequence number per receive queue .
839 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
842 uint32_t doorbell_hi;
844 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
846 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
847 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
848 doorbell = (uint64_t)doorbell_hi << 32;
849 doorbell |= rxq->cqn;
850 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
851 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
852 cq_db_reg, rxq->uar_lock_cq);
856 * DPDK callback for Rx queue interrupt enable.
859 * Pointer to Ethernet device structure.
864 * 0 on success, a negative errno value otherwise and rte_errno is set.
867 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
869 struct mlx5_priv *priv = dev->data->dev_private;
870 struct mlx5_rxq_data *rxq_data;
871 struct mlx5_rxq_ctrl *rxq_ctrl;
873 rxq_data = (*priv->rxqs)[rx_queue_id];
878 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
880 struct mlx5_rxq_obj *rxq_obj;
882 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
887 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
888 mlx5_rxq_obj_release(rxq_obj);
894 * DPDK callback for Rx queue interrupt disable.
897 * Pointer to Ethernet device structure.
902 * 0 on success, a negative errno value otherwise and rte_errno is set.
905 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
907 struct mlx5_priv *priv = dev->data->dev_private;
908 struct mlx5_rxq_data *rxq_data;
909 struct mlx5_rxq_ctrl *rxq_ctrl;
910 struct mlx5_rxq_obj *rxq_obj = NULL;
911 struct ibv_cq *ev_cq;
915 rxq_data = (*priv->rxqs)[rx_queue_id];
920 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
923 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
928 ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
929 if (ret || ev_cq != rxq_obj->cq) {
933 rxq_data->cq_arm_sn++;
934 mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
935 mlx5_rxq_obj_release(rxq_obj);
938 ret = rte_errno; /* Save rte_errno before cleanup. */
940 mlx5_rxq_obj_release(rxq_obj);
941 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
942 dev->data->port_id, rx_queue_id);
943 rte_errno = ret; /* Restore rte_errno. */
948 * Create a CQ Verbs object.
951 * Pointer to Ethernet device.
953 * Pointer to device private data.
955 * Pointer to Rx queue data.
957 * Number of CQEs in CQ.
959 * Pointer to Rx queue object data.
962 * The Verbs object initialised, NULL otherwise and rte_errno is set.
964 static struct ibv_cq *
965 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
966 struct mlx5_rxq_data *rxq_data,
967 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
970 struct ibv_cq_init_attr_ex ibv;
971 struct mlx5dv_cq_init_attr mlx5;
974 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
976 .channel = rxq_obj->channel,
979 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
982 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
984 cq_attr.mlx5.comp_mask |=
985 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
986 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
987 cq_attr.mlx5.cqe_comp_res_format =
988 mlx5_rxq_mprq_enabled(rxq_data) ?
989 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
990 MLX5DV_CQE_RES_FORMAT_HASH;
992 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
995 * For vectorized Rx, it must not be doubled in order to
996 * make cq_ci and rq_ci aligned.
998 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
999 cq_attr.ibv.cqe *= 2;
1000 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1002 "port %u Rx CQE compression is disabled for HW"
1004 dev->data->port_id);
1005 } else if (priv->config.cqe_comp && rxq_data->lro) {
1007 "port %u Rx CQE compression is disabled for LRO",
1008 dev->data->port_id);
1010 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1011 if (priv->config.cqe_pad) {
1012 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1013 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1016 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1022 * Create a WQ Verbs object.
1025 * Pointer to Ethernet device.
1027 * Pointer to device private data.
1029 * Pointer to Rx queue data.
1031 * Queue index in DPDK Rx queue array
1033 * Number of WQEs in WQ.
1035 * Pointer to Rx queue object data.
1038 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1040 static struct ibv_wq *
1041 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1042 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1043 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1046 struct ibv_wq_init_attr ibv;
1047 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1048 struct mlx5dv_wq_init_attr mlx5;
1052 wq_attr.ibv = (struct ibv_wq_init_attr){
1053 .wq_context = NULL, /* Could be useful in the future. */
1054 .wq_type = IBV_WQT_RQ,
1055 /* Max number of outstanding WRs. */
1056 .max_wr = wqe_n >> rxq_data->sges_n,
1057 /* Max number of scatter/gather elements in a WR. */
1058 .max_sge = 1 << rxq_data->sges_n,
1061 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1062 .create_flags = (rxq_data->vlan_strip ?
1063 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1065 /* By default, FCS (CRC) is stripped by hardware. */
1066 if (rxq_data->crc_present) {
1067 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1068 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1070 if (priv->config.hw_padding) {
1071 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1072 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1073 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1074 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1075 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1076 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1079 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1080 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1083 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1084 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1085 &wq_attr.mlx5.striding_rq_attrs;
1087 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1088 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1089 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1090 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1091 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1094 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1097 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1101 * Make sure number of WRs*SGEs match expectations since a queue
1102 * cannot allocate more than "desc" buffers.
1104 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1105 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1107 "port %u Rx queue %u requested %u*%u but got"
1109 dev->data->port_id, idx,
1110 wqe_n >> rxq_data->sges_n,
1111 (1 << rxq_data->sges_n),
1112 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1113 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1122 * Fill common fields of create RQ attributes structure.
1125 * Pointer to Rx queue data.
1127 * CQ number to use with this RQ.
1129 * RQ attributes structure to fill..
1132 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1133 struct mlx5_devx_create_rq_attr *rq_attr)
1135 rq_attr->state = MLX5_RQC_STATE_RST;
1136 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1138 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1142 * Fill common fields of DevX WQ attributes structure.
1145 * Pointer to device private data.
1147 * Pointer to Rx queue control structure.
1149 * WQ attributes structure to fill..
1152 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1153 struct mlx5_devx_wq_attr *wq_attr)
1155 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1156 MLX5_WQ_END_PAD_MODE_ALIGN :
1157 MLX5_WQ_END_PAD_MODE_NONE;
1158 wq_attr->pd = priv->sh->pdn;
1159 wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1160 wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1161 wq_attr->dbr_umem_valid = 1;
1162 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1163 wq_attr->wq_umem_valid = 1;
1167 * Create a RQ object using DevX.
1170 * Pointer to Ethernet device.
1172 * Queue index in DPDK Rx queue array
1174 * CQ number to use with this RQ.
1177 * The DevX object initialised, NULL otherwise and rte_errno is set.
1179 static struct mlx5_devx_obj *
1180 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1182 struct mlx5_priv *priv = dev->data->dev_private;
1183 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1184 struct mlx5_rxq_ctrl *rxq_ctrl =
1185 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1186 struct mlx5_devx_create_rq_attr rq_attr;
1187 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1188 uint32_t wq_size = 0;
1189 uint32_t wqe_size = 0;
1190 uint32_t log_wqe_size = 0;
1192 struct mlx5_devx_obj *rq;
1194 memset(&rq_attr, 0, sizeof(rq_attr));
1195 /* Fill RQ attributes. */
1196 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1197 rq_attr.flush_in_error_en = 1;
1198 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1199 /* Fill WQ attributes for this RQ. */
1200 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1201 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1203 * Number of strides in each WQE:
1204 * 512*2^single_wqe_log_num_of_strides.
1206 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1207 rxq_data->strd_num_n -
1208 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1209 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1210 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1211 rxq_data->strd_sz_n -
1212 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1213 wqe_size = sizeof(struct mlx5_wqe_mprq);
1215 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1216 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1218 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1219 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1220 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1221 /* Calculate and allocate WQ memory space. */
1222 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1223 wq_size = wqe_n * wqe_size;
1224 buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1228 rxq_data->wqes = buf;
1229 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1231 if (!rxq_ctrl->wq_umem) {
1235 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1236 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1238 rxq_release_rq_resources(rxq_ctrl);
1243 * Create the Rx hairpin queue object.
1246 * Pointer to Ethernet device.
1248 * Queue index in DPDK Rx queue array
1251 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1253 static struct mlx5_rxq_obj *
1254 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1256 struct mlx5_priv *priv = dev->data->dev_private;
1257 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1258 struct mlx5_rxq_ctrl *rxq_ctrl =
1259 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1260 struct mlx5_devx_create_rq_attr attr = { 0 };
1261 struct mlx5_rxq_obj *tmpl = NULL;
1265 assert(!rxq_ctrl->obj);
1266 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1270 "port %u Rx queue %u cannot allocate verbs resources",
1271 dev->data->port_id, rxq_data->idx);
1275 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1276 tmpl->rxq_ctrl = rxq_ctrl;
1278 /* Workaround for hairpin startup */
1279 attr.wq_attr.log_hairpin_num_packets = log2above(32);
1280 /* Workaround for packets larger than 1KB */
1281 attr.wq_attr.log_hairpin_data_sz =
1282 priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1283 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1287 "port %u Rx hairpin queue %u can't create rq object",
1288 dev->data->port_id, idx);
1292 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1293 idx, (void *)&tmpl);
1294 rte_atomic32_inc(&tmpl->refcnt);
1295 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1296 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1299 ret = rte_errno; /* Save rte_errno before cleanup. */
1301 mlx5_devx_cmd_destroy(tmpl->rq);
1302 rte_errno = ret; /* Restore rte_errno. */
1307 * Create the Rx queue Verbs/DevX object.
1310 * Pointer to Ethernet device.
1312 * Queue index in DPDK Rx queue array
1314 * Type of Rx queue object to create.
1317 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1319 struct mlx5_rxq_obj *
1320 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1321 enum mlx5_rxq_obj_type type)
1323 struct mlx5_priv *priv = dev->data->dev_private;
1324 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1325 struct mlx5_rxq_ctrl *rxq_ctrl =
1326 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1327 struct ibv_wq_attr mod;
1329 unsigned int wqe_n = 1 << rxq_data->elts_n;
1330 struct mlx5_rxq_obj *tmpl = NULL;
1331 struct mlx5dv_cq cq_info;
1332 struct mlx5dv_rwq rwq;
1334 struct mlx5dv_obj obj;
1337 assert(!rxq_ctrl->obj);
1338 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1339 return mlx5_rxq_obj_hairpin_new(dev, idx);
1340 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1341 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1342 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1346 "port %u Rx queue %u cannot allocate verbs resources",
1347 dev->data->port_id, rxq_data->idx);
1352 tmpl->rxq_ctrl = rxq_ctrl;
1353 if (rxq_ctrl->irq) {
1354 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1355 if (!tmpl->channel) {
1356 DRV_LOG(ERR, "port %u: comp channel creation failure",
1357 dev->data->port_id);
1362 if (mlx5_rxq_mprq_enabled(rxq_data))
1363 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1366 tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1368 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1369 dev->data->port_id, idx);
1373 obj.cq.in = tmpl->cq;
1374 obj.cq.out = &cq_info;
1375 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1380 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1382 "port %u wrong MLX5_CQE_SIZE environment variable"
1383 " value: it should be set to %u",
1384 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1388 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1389 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1390 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1391 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1392 /* Allocate door-bell for types created with DevX. */
1393 if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1394 struct mlx5_devx_dbr_page *dbr_page;
1397 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1400 rxq_ctrl->dbr_offset = dbr_offset;
1401 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1402 rxq_ctrl->dbr_umem_id_valid = 1;
1403 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1404 (uintptr_t)rxq_ctrl->dbr_offset);
1406 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1407 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1410 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1411 dev->data->port_id, idx);
1415 /* Change queue state to ready. */
1416 mod = (struct ibv_wq_attr){
1417 .attr_mask = IBV_WQ_ATTR_STATE,
1418 .wq_state = IBV_WQS_RDY,
1420 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1423 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1424 " failed", dev->data->port_id, idx);
1428 obj.rwq.in = tmpl->wq;
1430 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1435 rxq_data->wqes = rwq.buf;
1436 rxq_data->rq_db = rwq.dbrec;
1437 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1438 struct mlx5_devx_modify_rq_attr rq_attr;
1440 memset(&rq_attr, 0, sizeof(rq_attr));
1441 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1443 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1444 dev->data->port_id, idx);
1448 /* Change queue state to ready. */
1449 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1450 rq_attr.state = MLX5_RQC_STATE_RDY;
1451 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1455 /* Fill the rings. */
1456 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1457 rxq_data->cq_db = cq_info.dbrec;
1458 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1459 rxq_data->cq_uar = cq_info.cq_uar;
1460 rxq_data->cqn = cq_info.cqn;
1461 rxq_data->cq_arm_sn = 0;
1462 mlx5_rxq_initialize(rxq_data);
1463 rxq_data->cq_ci = 0;
1464 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1465 idx, (void *)&tmpl);
1466 rte_atomic32_inc(&tmpl->refcnt);
1467 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1468 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1472 ret = rte_errno; /* Save rte_errno before cleanup. */
1473 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1474 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1475 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1476 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1478 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1480 claim_zero(mlx5_glue->destroy_comp_channel
1483 rte_errno = ret; /* Restore rte_errno. */
1485 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1486 rxq_release_rq_resources(rxq_ctrl);
1487 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1492 * Verify the Rx queue objects list is empty
1495 * Pointer to Ethernet device.
1498 * The number of objects not released.
1501 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1503 struct mlx5_priv *priv = dev->data->dev_private;
1505 struct mlx5_rxq_obj *rxq_obj;
1507 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1508 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1509 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1516 * Callback function to initialize mbufs for Multi-Packet RQ.
1519 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1520 void *_m, unsigned int i __rte_unused)
1522 struct mlx5_mprq_buf *buf = _m;
1523 struct rte_mbuf_ext_shared_info *shinfo;
1524 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1527 memset(_m, 0, sizeof(*buf));
1529 rte_atomic16_set(&buf->refcnt, 1);
1530 for (j = 0; j != strd_n; ++j) {
1531 shinfo = &buf->shinfos[j];
1532 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1533 shinfo->fcb_opaque = buf;
1538 * Free mempool of Multi-Packet RQ.
1541 * Pointer to Ethernet device.
1544 * 0 on success, negative errno value on failure.
1547 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1549 struct mlx5_priv *priv = dev->data->dev_private;
1550 struct rte_mempool *mp = priv->mprq_mp;
1555 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1556 dev->data->port_id, mp->name);
1558 * If a buffer in the pool has been externally attached to a mbuf and it
1559 * is still in use by application, destroying the Rx queue can spoil
1560 * the packet. It is unlikely to happen but if application dynamically
1561 * creates and destroys with holding Rx packets, this can happen.
1563 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1564 * RQ isn't provided by application but managed by PMD.
1566 if (!rte_mempool_full(mp)) {
1568 "port %u mempool for Multi-Packet RQ is still in use",
1569 dev->data->port_id);
1573 rte_mempool_free(mp);
1574 /* Unset mempool for each Rx queue. */
1575 for (i = 0; i != priv->rxqs_n; ++i) {
1576 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1580 rxq->mprq_mp = NULL;
1582 priv->mprq_mp = NULL;
1587 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1588 * mempool. If already allocated, reuse it if there're enough elements.
1589 * Otherwise, resize it.
1592 * Pointer to Ethernet device.
1595 * 0 on success, negative errno value on failure.
1598 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1600 struct mlx5_priv *priv = dev->data->dev_private;
1601 struct rte_mempool *mp = priv->mprq_mp;
1602 char name[RTE_MEMPOOL_NAMESIZE];
1603 unsigned int desc = 0;
1604 unsigned int buf_len;
1605 unsigned int obj_num;
1606 unsigned int obj_size;
1607 unsigned int strd_num_n = 0;
1608 unsigned int strd_sz_n = 0;
1610 unsigned int n_ibv = 0;
1612 if (!mlx5_mprq_enabled(dev))
1614 /* Count the total number of descriptors configured. */
1615 for (i = 0; i != priv->rxqs_n; ++i) {
1616 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1617 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1618 (rxq, struct mlx5_rxq_ctrl, rxq);
1620 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1623 desc += 1 << rxq->elts_n;
1624 /* Get the max number of strides. */
1625 if (strd_num_n < rxq->strd_num_n)
1626 strd_num_n = rxq->strd_num_n;
1627 /* Get the max size of a stride. */
1628 if (strd_sz_n < rxq->strd_sz_n)
1629 strd_sz_n = rxq->strd_sz_n;
1631 assert(strd_num_n && strd_sz_n);
1632 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1633 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1634 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1636 * Received packets can be either memcpy'd or externally referenced. In
1637 * case that the packet is attached to an mbuf as an external buffer, as
1638 * it isn't possible to predict how the buffers will be queued by
1639 * application, there's no option to exactly pre-allocate needed buffers
1640 * in advance but to speculatively prepares enough buffers.
1642 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1643 * received packets to buffers provided by application (rxq->mp) until
1644 * this Mempool gets available again.
1647 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1649 * rte_mempool_create_empty() has sanity check to refuse large cache
1650 * size compared to the number of elements.
1651 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1652 * constant number 2 instead.
1654 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1655 /* Check a mempool is already allocated and if it can be resued. */
1656 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1657 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1658 dev->data->port_id, mp->name);
1661 } else if (mp != NULL) {
1662 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1663 dev->data->port_id, mp->name);
1665 * If failed to free, which means it may be still in use, no way
1666 * but to keep using the existing one. On buffer underrun,
1667 * packets will be memcpy'd instead of external buffer
1670 if (mlx5_mprq_free_mp(dev)) {
1671 if (mp->elt_size >= obj_size)
1677 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1678 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1679 0, NULL, NULL, mlx5_mprq_buf_init,
1680 (void *)(uintptr_t)(1 << strd_num_n),
1681 dev->device->numa_node, 0);
1684 "port %u failed to allocate a mempool for"
1685 " Multi-Packet RQ, count=%u, size=%u",
1686 dev->data->port_id, obj_num, obj_size);
1692 /* Set mempool for each Rx queue. */
1693 for (i = 0; i != priv->rxqs_n; ++i) {
1694 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1695 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1696 (rxq, struct mlx5_rxq_ctrl, rxq);
1698 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1702 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1703 dev->data->port_id);
1707 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1708 sizeof(struct rte_vlan_hdr) * 2 + \
1709 sizeof(struct rte_ipv6_hdr)))
1710 #define MAX_TCP_OPTION_SIZE 40u
1711 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1712 sizeof(struct rte_tcp_hdr) + \
1713 MAX_TCP_OPTION_SIZE))
1716 * Adjust the maximum LRO massage size.
1719 * Pointer to Ethernet device.
1722 * @param max_lro_size
1723 * The maximum size for LRO packet.
1726 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1727 uint32_t max_lro_size)
1729 struct mlx5_priv *priv = dev->data->dev_private;
1731 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1732 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1733 MLX5_MAX_TCP_HDR_OFFSET)
1734 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1735 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1736 assert(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1737 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1738 if (priv->max_lro_msg_size)
1739 priv->max_lro_msg_size =
1740 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1742 priv->max_lro_msg_size = max_lro_size;
1744 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1745 dev->data->port_id, idx,
1746 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1750 * Create a DPDK Rx queue.
1753 * Pointer to Ethernet device.
1757 * Number of descriptors to configure in queue.
1759 * NUMA socket on which memory must be allocated.
1762 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1764 struct mlx5_rxq_ctrl *
1765 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1766 unsigned int socket, const struct rte_eth_rxconf *conf,
1767 struct rte_mempool *mp)
1769 struct mlx5_priv *priv = dev->data->dev_private;
1770 struct mlx5_rxq_ctrl *tmpl;
1771 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1772 unsigned int mprq_stride_size;
1773 struct mlx5_dev_config *config = &priv->config;
1774 unsigned int strd_headroom_en;
1776 * Always allocate extra slots, even if eventually
1777 * the vector Rx will not be used.
1780 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1781 uint64_t offloads = conf->offloads |
1782 dev->data->dev_conf.rxmode.offloads;
1783 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1784 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1785 unsigned int max_rx_pkt_len = lro_on_queue ?
1786 dev->data->dev_conf.rxmode.max_lro_pkt_size :
1787 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1788 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1789 RTE_PKTMBUF_HEADROOM;
1790 unsigned int max_lro_size = 0;
1791 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1793 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1794 DEV_RX_OFFLOAD_SCATTER)) {
1795 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1796 " configured and no enough mbuf space(%u) to contain "
1797 "the maximum RX packet length(%u) with head-room(%u)",
1798 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1799 RTE_PKTMBUF_HEADROOM);
1803 tmpl = rte_calloc_socket("RXQ", 1,
1805 desc_n * sizeof(struct rte_mbuf *),
1811 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1812 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1813 MLX5_MR_BTREE_CACHE_N, socket)) {
1814 /* rte_errno is already set. */
1817 tmpl->socket = socket;
1818 if (dev->data->dev_conf.intr_conf.rxq)
1821 * LRO packet may consume all the stride memory, hence we cannot
1822 * guaranty head-room near the packet memory in the stride.
1823 * In this case scatter is, for sure, enabled and an empty mbuf may be
1824 * added in the start for the head-room.
1826 if (lro_on_queue && RTE_PKTMBUF_HEADROOM > 0 &&
1827 non_scatter_min_mbuf_size > mb_len) {
1828 strd_headroom_en = 0;
1829 mprq_stride_size = RTE_MIN(max_rx_pkt_len,
1830 1u << config->mprq.max_stride_size_n);
1832 strd_headroom_en = 1;
1833 mprq_stride_size = non_scatter_min_mbuf_size;
1836 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1837 * following conditions are met:
1838 * - MPRQ is enabled.
1839 * - The number of descs is more than the number of strides.
1840 * - max_rx_pkt_len plus overhead is less than the max size of a
1842 * Otherwise, enable Rx scatter if necessary.
1845 desc > (1U << config->mprq.stride_num_n) &&
1846 mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1847 /* TODO: Rx scatter isn't supported yet. */
1848 tmpl->rxq.sges_n = 0;
1849 /* Trim the number of descs needed. */
1850 desc >>= config->mprq.stride_num_n;
1851 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1852 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1853 config->mprq.min_stride_size_n);
1854 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1855 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1856 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1857 config->mprq.max_memcpy_len);
1858 max_lro_size = RTE_MIN(max_rx_pkt_len,
1859 (1u << tmpl->rxq.strd_num_n) *
1860 (1u << tmpl->rxq.strd_sz_n));
1862 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1863 " strd_num_n = %u, strd_sz_n = %u",
1864 dev->data->port_id, idx,
1865 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1866 } else if (max_rx_pkt_len <= first_mb_free_size) {
1867 tmpl->rxq.sges_n = 0;
1868 max_lro_size = max_rx_pkt_len;
1869 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1870 unsigned int size = non_scatter_min_mbuf_size;
1871 unsigned int sges_n;
1873 if (lro_on_queue && first_mb_free_size <
1874 MLX5_MAX_LRO_HEADER_FIX) {
1875 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1876 " to include the max header size(%u) for LRO",
1877 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1878 rte_errno = ENOTSUP;
1882 * Determine the number of SGEs needed for a full packet
1883 * and round it to the next power of two.
1885 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1886 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1888 "port %u too many SGEs (%u) needed to handle"
1889 " requested maximum packet size %u, the maximum"
1890 " supported are %u", dev->data->port_id,
1891 1 << sges_n, max_rx_pkt_len,
1892 1u << MLX5_MAX_LOG_RQ_SEGS);
1893 rte_errno = ENOTSUP;
1896 tmpl->rxq.sges_n = sges_n;
1897 max_lro_size = max_rx_pkt_len;
1899 if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1901 "port %u MPRQ is requested but cannot be enabled"
1902 " (requested: desc = %u, stride_sz = %u,"
1903 " supported: min_stride_num = %u, max_stride_sz = %u).",
1904 dev->data->port_id, desc, mprq_stride_size,
1905 (1 << config->mprq.stride_num_n),
1906 (1 << config->mprq.max_stride_size_n));
1907 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1908 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1909 if (desc % (1 << tmpl->rxq.sges_n)) {
1911 "port %u number of Rx queue descriptors (%u) is not a"
1912 " multiple of SGEs per packet (%u)",
1915 1 << tmpl->rxq.sges_n);
1919 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1920 /* Toggle RX checksum offload if hardware supports it. */
1921 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1922 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1923 /* Configure VLAN stripping. */
1924 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1925 /* By default, FCS (CRC) is stripped by hardware. */
1926 tmpl->rxq.crc_present = 0;
1927 tmpl->rxq.lro = lro_on_queue;
1928 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1929 if (config->hw_fcs_strip) {
1931 * RQs used for LRO-enabled TIRs should not be
1932 * configured to scatter the FCS.
1936 "port %u CRC stripping has been "
1937 "disabled but will still be performed "
1938 "by hardware, because LRO is enabled",
1939 dev->data->port_id);
1941 tmpl->rxq.crc_present = 1;
1944 "port %u CRC stripping has been disabled but will"
1945 " still be performed by hardware, make sure MLNX_OFED"
1946 " and firmware are up to date",
1947 dev->data->port_id);
1951 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1952 " incoming frames to hide it",
1954 tmpl->rxq.crc_present ? "disabled" : "enabled",
1955 tmpl->rxq.crc_present << 2);
1957 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1958 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1959 tmpl->rxq.port_id = dev->data->port_id;
1962 tmpl->rxq.elts_n = log2above(desc);
1963 tmpl->rxq.rq_repl_thresh =
1964 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1966 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1968 tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1970 tmpl->rxq.idx = idx;
1971 rte_atomic32_inc(&tmpl->refcnt);
1972 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1980 * Create a DPDK Rx hairpin queue.
1983 * Pointer to Ethernet device.
1987 * Number of descriptors to configure in queue.
1988 * @param hairpin_conf
1989 * The hairpin binding configuration.
1992 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1994 struct mlx5_rxq_ctrl *
1995 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1996 const struct rte_eth_hairpin_conf *hairpin_conf)
1998 struct mlx5_priv *priv = dev->data->dev_private;
1999 struct mlx5_rxq_ctrl *tmpl;
2001 tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
2006 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2007 tmpl->socket = SOCKET_ID_ANY;
2008 tmpl->rxq.rss_hash = 0;
2009 tmpl->rxq.port_id = dev->data->port_id;
2011 tmpl->rxq.mp = NULL;
2012 tmpl->rxq.elts_n = log2above(desc);
2013 tmpl->rxq.elts = NULL;
2014 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2015 tmpl->hairpin_conf = *hairpin_conf;
2016 tmpl->rxq.idx = idx;
2017 rte_atomic32_inc(&tmpl->refcnt);
2018 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2026 * Pointer to Ethernet device.
2031 * A pointer to the queue if it exists, NULL otherwise.
2033 struct mlx5_rxq_ctrl *
2034 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2036 struct mlx5_priv *priv = dev->data->dev_private;
2037 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2039 if ((*priv->rxqs)[idx]) {
2040 rxq_ctrl = container_of((*priv->rxqs)[idx],
2041 struct mlx5_rxq_ctrl,
2043 mlx5_rxq_obj_get(dev, idx);
2044 rte_atomic32_inc(&rxq_ctrl->refcnt);
2050 * Release a Rx queue.
2053 * Pointer to Ethernet device.
2058 * 1 while a reference on it exists, 0 when freed.
2061 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2063 struct mlx5_priv *priv = dev->data->dev_private;
2064 struct mlx5_rxq_ctrl *rxq_ctrl;
2066 if (!(*priv->rxqs)[idx])
2068 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2069 assert(rxq_ctrl->priv);
2070 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2071 rxq_ctrl->obj = NULL;
2072 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2073 if (rxq_ctrl->dbr_umem_id_valid)
2074 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
2075 rxq_ctrl->dbr_offset));
2076 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2077 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2078 LIST_REMOVE(rxq_ctrl, next);
2080 (*priv->rxqs)[idx] = NULL;
2087 * Verify the Rx Queue list is empty
2090 * Pointer to Ethernet device.
2093 * The number of object not released.
2096 mlx5_rxq_verify(struct rte_eth_dev *dev)
2098 struct mlx5_priv *priv = dev->data->dev_private;
2099 struct mlx5_rxq_ctrl *rxq_ctrl;
2102 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2103 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2104 dev->data->port_id, rxq_ctrl->rxq.idx);
2111 * Get a Rx queue type.
2114 * Pointer to Ethernet device.
2119 * The Rx queue type.
2122 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2124 struct mlx5_priv *priv = dev->data->dev_private;
2125 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2127 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2128 rxq_ctrl = container_of((*priv->rxqs)[idx],
2129 struct mlx5_rxq_ctrl,
2131 return rxq_ctrl->type;
2133 return MLX5_RXQ_TYPE_UNDEFINED;
2137 * Create an indirection table.
2140 * Pointer to Ethernet device.
2142 * Queues entering in the indirection table.
2144 * Number of queues in the array.
2147 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2149 static struct mlx5_ind_table_obj *
2150 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2151 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2153 struct mlx5_priv *priv = dev->data->dev_private;
2154 struct mlx5_ind_table_obj *ind_tbl;
2155 unsigned int i = 0, j = 0, k = 0;
2157 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2158 queues_n * sizeof(uint16_t), 0);
2163 ind_tbl->type = type;
2164 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2165 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2166 log2above(queues_n) :
2167 log2above(priv->config.ind_table_max_size);
2168 struct ibv_wq *wq[1 << wq_n];
2170 for (i = 0; i != queues_n; ++i) {
2171 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2175 wq[i] = rxq->obj->wq;
2176 ind_tbl->queues[i] = queues[i];
2178 ind_tbl->queues_n = queues_n;
2179 /* Finalise indirection table. */
2180 k = i; /* Retain value of i for use in error case. */
2181 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2183 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2185 &(struct ibv_rwq_ind_table_init_attr){
2186 .log_ind_tbl_size = wq_n,
2190 if (!ind_tbl->ind_table) {
2194 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2195 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2196 const unsigned int rqt_n =
2197 1 << (rte_is_power_of_2(queues_n) ?
2198 log2above(queues_n) :
2199 log2above(priv->config.ind_table_max_size));
2201 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2202 rqt_n * sizeof(uint32_t), 0);
2204 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2205 dev->data->port_id);
2209 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2210 rqt_attr->rqt_actual_size = rqt_n;
2211 for (i = 0; i != queues_n; ++i) {
2212 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2216 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2217 ind_tbl->queues[i] = queues[i];
2219 k = i; /* Retain value of i for use in error case. */
2220 for (j = 0; k != rqt_n; ++k, ++j)
2221 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2222 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2225 if (!ind_tbl->rqt) {
2226 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2227 dev->data->port_id);
2231 ind_tbl->queues_n = queues_n;
2233 rte_atomic32_inc(&ind_tbl->refcnt);
2234 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2237 for (j = 0; j < i; j++)
2238 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2240 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2245 * Get an indirection table.
2248 * Pointer to Ethernet device.
2250 * Queues entering in the indirection table.
2252 * Number of queues in the array.
2255 * An indirection table if found.
2257 static struct mlx5_ind_table_obj *
2258 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2261 struct mlx5_priv *priv = dev->data->dev_private;
2262 struct mlx5_ind_table_obj *ind_tbl;
2264 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2265 if ((ind_tbl->queues_n == queues_n) &&
2266 (memcmp(ind_tbl->queues, queues,
2267 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2274 rte_atomic32_inc(&ind_tbl->refcnt);
2275 for (i = 0; i != ind_tbl->queues_n; ++i)
2276 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2282 * Release an indirection table.
2285 * Pointer to Ethernet device.
2287 * Indirection table to release.
2290 * 1 while a reference on it exists, 0 when freed.
2293 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2294 struct mlx5_ind_table_obj *ind_tbl)
2298 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2299 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2300 claim_zero(mlx5_glue->destroy_rwq_ind_table
2301 (ind_tbl->ind_table));
2302 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2303 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2305 for (i = 0; i != ind_tbl->queues_n; ++i)
2306 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2307 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2308 LIST_REMOVE(ind_tbl, next);
2316 * Verify the Rx Queue list is empty
2319 * Pointer to Ethernet device.
2322 * The number of object not released.
2325 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2327 struct mlx5_priv *priv = dev->data->dev_private;
2328 struct mlx5_ind_table_obj *ind_tbl;
2331 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2333 "port %u indirection table obj %p still referenced",
2334 dev->data->port_id, (void *)ind_tbl);
2341 * Create an Rx Hash queue.
2344 * Pointer to Ethernet device.
2346 * RSS key for the Rx hash queue.
2347 * @param rss_key_len
2349 * @param hash_fields
2350 * Verbs protocol hash field to make the RSS on.
2352 * Queues entering in hash queue. In case of empty hash_fields only the
2353 * first queue index will be taken for the indirection table.
2360 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2363 mlx5_hrxq_new(struct rte_eth_dev *dev,
2364 const uint8_t *rss_key, uint32_t rss_key_len,
2365 uint64_t hash_fields,
2366 const uint16_t *queues, uint32_t queues_n,
2367 int tunnel __rte_unused)
2369 struct mlx5_priv *priv = dev->data->dev_private;
2370 struct mlx5_hrxq *hrxq;
2371 struct ibv_qp *qp = NULL;
2372 struct mlx5_ind_table_obj *ind_tbl;
2374 struct mlx5_devx_obj *tir = NULL;
2375 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2376 struct mlx5_rxq_ctrl *rxq_ctrl =
2377 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2379 queues_n = hash_fields ? queues_n : 1;
2380 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2382 enum mlx5_ind_tbl_type type;
2384 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2385 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2386 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2392 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2393 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2394 struct mlx5dv_qp_init_attr qp_init_attr;
2396 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2398 qp_init_attr.comp_mask =
2399 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2400 qp_init_attr.create_flags =
2401 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2403 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2404 if (dev->data->dev_conf.lpbk_mode) {
2406 * Allow packet sent from NIC loop back
2407 * w/o source MAC check.
2409 qp_init_attr.comp_mask |=
2410 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2411 qp_init_attr.create_flags |=
2412 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2415 qp = mlx5_glue->dv_create_qp
2417 &(struct ibv_qp_init_attr_ex){
2418 .qp_type = IBV_QPT_RAW_PACKET,
2420 IBV_QP_INIT_ATTR_PD |
2421 IBV_QP_INIT_ATTR_IND_TABLE |
2422 IBV_QP_INIT_ATTR_RX_HASH,
2423 .rx_hash_conf = (struct ibv_rx_hash_conf){
2425 IBV_RX_HASH_FUNC_TOEPLITZ,
2426 .rx_hash_key_len = rss_key_len,
2428 (void *)(uintptr_t)rss_key,
2429 .rx_hash_fields_mask = hash_fields,
2431 .rwq_ind_tbl = ind_tbl->ind_table,
2436 qp = mlx5_glue->create_qp_ex
2438 &(struct ibv_qp_init_attr_ex){
2439 .qp_type = IBV_QPT_RAW_PACKET,
2441 IBV_QP_INIT_ATTR_PD |
2442 IBV_QP_INIT_ATTR_IND_TABLE |
2443 IBV_QP_INIT_ATTR_RX_HASH,
2444 .rx_hash_conf = (struct ibv_rx_hash_conf){
2446 IBV_RX_HASH_FUNC_TOEPLITZ,
2447 .rx_hash_key_len = rss_key_len,
2449 (void *)(uintptr_t)rss_key,
2450 .rx_hash_fields_mask = hash_fields,
2452 .rwq_ind_tbl = ind_tbl->ind_table,
2460 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2461 struct mlx5_devx_tir_attr tir_attr;
2465 /* Enable TIR LRO only if all the queues were configured for. */
2466 for (i = 0; i < queues_n; ++i) {
2467 if (!(*priv->rxqs)[queues[i]]->lro) {
2472 memset(&tir_attr, 0, sizeof(tir_attr));
2473 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2474 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2475 memcpy(&tir_attr.rx_hash_field_selector_outer, &hash_fields,
2477 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2478 tir_attr.transport_domain = priv->sh->td->id;
2480 tir_attr.transport_domain = priv->sh->tdn;
2481 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2482 tir_attr.indirect_table = ind_tbl->rqt->id;
2483 if (dev->data->dev_conf.lpbk_mode)
2484 tir_attr.self_lb_block =
2485 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2487 tir_attr.lro_timeout_period_usecs =
2488 priv->config.lro.timeout;
2489 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2490 tir_attr.lro_enable_mask =
2491 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2492 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2494 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2496 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2497 dev->data->port_id);
2502 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2505 hrxq->ind_table = ind_tbl;
2506 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2508 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2510 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2511 if (!hrxq->action) {
2516 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2518 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2519 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2521 if (!hrxq->action) {
2527 hrxq->rss_key_len = rss_key_len;
2528 hrxq->hash_fields = hash_fields;
2529 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2530 rte_atomic32_inc(&hrxq->refcnt);
2531 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2534 err = rte_errno; /* Save rte_errno before cleanup. */
2535 mlx5_ind_table_obj_release(dev, ind_tbl);
2537 claim_zero(mlx5_glue->destroy_qp(qp));
2539 claim_zero(mlx5_devx_cmd_destroy(tir));
2540 rte_errno = err; /* Restore rte_errno. */
2545 * Get an Rx Hash queue.
2548 * Pointer to Ethernet device.
2550 * RSS configuration for the Rx hash queue.
2552 * Queues entering in hash queue. In case of empty hash_fields only the
2553 * first queue index will be taken for the indirection table.
2558 * An hash Rx queue on success.
2561 mlx5_hrxq_get(struct rte_eth_dev *dev,
2562 const uint8_t *rss_key, uint32_t rss_key_len,
2563 uint64_t hash_fields,
2564 const uint16_t *queues, uint32_t queues_n)
2566 struct mlx5_priv *priv = dev->data->dev_private;
2567 struct mlx5_hrxq *hrxq;
2569 queues_n = hash_fields ? queues_n : 1;
2570 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2571 struct mlx5_ind_table_obj *ind_tbl;
2573 if (hrxq->rss_key_len != rss_key_len)
2575 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2577 if (hrxq->hash_fields != hash_fields)
2579 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2582 if (ind_tbl != hrxq->ind_table) {
2583 mlx5_ind_table_obj_release(dev, ind_tbl);
2586 rte_atomic32_inc(&hrxq->refcnt);
2593 * Release the hash Rx queue.
2596 * Pointer to Ethernet device.
2598 * Pointer to Hash Rx queue to release.
2601 * 1 while a reference on it exists, 0 when freed.
2604 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2606 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2607 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2608 mlx5_glue->destroy_flow_action(hrxq->action);
2610 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2611 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2612 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2613 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2614 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2615 LIST_REMOVE(hrxq, next);
2619 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2624 * Verify the Rx Queue list is empty
2627 * Pointer to Ethernet device.
2630 * The number of object not released.
2633 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2635 struct mlx5_priv *priv = dev->data->dev_private;
2636 struct mlx5_hrxq *hrxq;
2639 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2641 "port %u hash Rx queue %p still referenced",
2642 dev->data->port_id, (void *)hrxq);
2649 * Create a drop Rx queue Verbs/DevX object.
2652 * Pointer to Ethernet device.
2655 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2657 static struct mlx5_rxq_obj *
2658 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2660 struct mlx5_priv *priv = dev->data->dev_private;
2661 struct ibv_context *ctx = priv->sh->ctx;
2663 struct ibv_wq *wq = NULL;
2664 struct mlx5_rxq_obj *rxq;
2666 if (priv->drop_queue.rxq)
2667 return priv->drop_queue.rxq;
2668 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2670 DEBUG("port %u cannot allocate CQ for drop queue",
2671 dev->data->port_id);
2675 wq = mlx5_glue->create_wq(ctx,
2676 &(struct ibv_wq_init_attr){
2677 .wq_type = IBV_WQT_RQ,
2684 DEBUG("port %u cannot allocate WQ for drop queue",
2685 dev->data->port_id);
2689 rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2691 DEBUG("port %u cannot allocate drop Rx queue memory",
2692 dev->data->port_id);
2698 priv->drop_queue.rxq = rxq;
2702 claim_zero(mlx5_glue->destroy_wq(wq));
2704 claim_zero(mlx5_glue->destroy_cq(cq));
2709 * Release a drop Rx queue Verbs/DevX object.
2712 * Pointer to Ethernet device.
2715 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2718 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2720 struct mlx5_priv *priv = dev->data->dev_private;
2721 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2724 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2726 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2728 priv->drop_queue.rxq = NULL;
2732 * Create a drop indirection table.
2735 * Pointer to Ethernet device.
2738 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2740 static struct mlx5_ind_table_obj *
2741 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2743 struct mlx5_priv *priv = dev->data->dev_private;
2744 struct mlx5_ind_table_obj *ind_tbl;
2745 struct mlx5_rxq_obj *rxq;
2746 struct mlx5_ind_table_obj tmpl;
2748 rxq = mlx5_rxq_obj_drop_new(dev);
2751 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2753 &(struct ibv_rwq_ind_table_init_attr){
2754 .log_ind_tbl_size = 0,
2755 .ind_tbl = &rxq->wq,
2758 if (!tmpl.ind_table) {
2759 DEBUG("port %u cannot allocate indirection table for drop"
2761 dev->data->port_id);
2765 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2770 ind_tbl->ind_table = tmpl.ind_table;
2773 mlx5_rxq_obj_drop_release(dev);
2778 * Release a drop indirection table.
2781 * Pointer to Ethernet device.
2784 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2786 struct mlx5_priv *priv = dev->data->dev_private;
2787 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2789 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2790 mlx5_rxq_obj_drop_release(dev);
2792 priv->drop_queue.hrxq->ind_table = NULL;
2796 * Create a drop Rx Hash queue.
2799 * Pointer to Ethernet device.
2802 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2805 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2807 struct mlx5_priv *priv = dev->data->dev_private;
2808 struct mlx5_ind_table_obj *ind_tbl = NULL;
2809 struct ibv_qp *qp = NULL;
2810 struct mlx5_hrxq *hrxq = NULL;
2812 if (priv->drop_queue.hrxq) {
2813 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2814 return priv->drop_queue.hrxq;
2816 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2819 "port %u cannot allocate memory for drop queue",
2820 dev->data->port_id);
2824 priv->drop_queue.hrxq = hrxq;
2825 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2828 hrxq->ind_table = ind_tbl;
2829 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2830 &(struct ibv_qp_init_attr_ex){
2831 .qp_type = IBV_QPT_RAW_PACKET,
2833 IBV_QP_INIT_ATTR_PD |
2834 IBV_QP_INIT_ATTR_IND_TABLE |
2835 IBV_QP_INIT_ATTR_RX_HASH,
2836 .rx_hash_conf = (struct ibv_rx_hash_conf){
2838 IBV_RX_HASH_FUNC_TOEPLITZ,
2839 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2840 .rx_hash_key = rss_hash_default_key,
2841 .rx_hash_fields_mask = 0,
2843 .rwq_ind_tbl = ind_tbl->ind_table,
2847 DEBUG("port %u cannot allocate QP for drop queue",
2848 dev->data->port_id);
2853 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2854 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2855 if (!hrxq->action) {
2860 rte_atomic32_set(&hrxq->refcnt, 1);
2863 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2864 if (hrxq && hrxq->action)
2865 mlx5_glue->destroy_flow_action(hrxq->action);
2868 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2870 mlx5_ind_table_obj_drop_release(dev);
2872 priv->drop_queue.hrxq = NULL;
2879 * Release a drop hash Rx queue.
2882 * Pointer to Ethernet device.
2885 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2887 struct mlx5_priv *priv = dev->data->dev_private;
2888 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2890 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2891 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2892 mlx5_glue->destroy_flow_action(hrxq->action);
2894 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2895 mlx5_ind_table_obj_drop_release(dev);
2897 priv->drop_queue.hrxq = NULL;