1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
14 #include <rte_malloc.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_common.h>
17 #include <rte_interrupts.h>
18 #include <rte_debug.h>
20 #include <rte_eal_paging.h>
22 #include <mlx5_glue.h>
23 #include <mlx5_devx_cmds.h>
24 #include <mlx5_malloc.h>
26 #include "mlx5_defs.h"
28 #include "mlx5_common_os.h"
29 #include "mlx5_rxtx.h"
30 #include "mlx5_utils.h"
31 #include "mlx5_autoconf.h"
32 #include "mlx5_flow.h"
35 /* Default RSS hash key also used for ConnectX-3. */
36 uint8_t rss_hash_default_key[] = {
37 0x2c, 0xc6, 0x81, 0xd1,
38 0x5b, 0xdb, 0xf4, 0xf7,
39 0xfc, 0xa2, 0x83, 0x19,
40 0xdb, 0x1a, 0x3e, 0x94,
41 0x6b, 0x9e, 0x38, 0xd9,
42 0x2c, 0x9c, 0x03, 0xd1,
43 0xad, 0x99, 0x44, 0xa7,
44 0xd9, 0x56, 0x3d, 0x59,
45 0x06, 0x3c, 0x25, 0xf3,
46 0xfc, 0x1f, 0xdc, 0x2a,
49 /* Length of the default RSS hash key. */
50 static_assert(MLX5_RSS_HASH_KEY_LEN ==
51 (unsigned int)sizeof(rss_hash_default_key),
52 "wrong RSS default key size.");
55 * Check whether Multi-Packet RQ can be enabled for the device.
58 * Pointer to Ethernet device.
61 * 1 if supported, negative errno value if not.
64 mlx5_check_mprq_support(struct rte_eth_dev *dev)
66 struct mlx5_priv *priv = dev->data->dev_private;
68 if (priv->config.mprq.enabled &&
69 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
75 * Check whether Multi-Packet RQ is enabled for the Rx queue.
78 * Pointer to receive queue structure.
81 * 0 if disabled, otherwise enabled.
84 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
86 return rxq->strd_num_n > 0;
90 * Check whether Multi-Packet RQ is enabled for the device.
93 * Pointer to Ethernet device.
96 * 0 if disabled, otherwise enabled.
99 mlx5_mprq_enabled(struct rte_eth_dev *dev)
101 struct mlx5_priv *priv = dev->data->dev_private;
106 if (mlx5_check_mprq_support(dev) < 0)
108 /* All the configured queues should be enabled. */
109 for (i = 0; i < priv->rxqs_n; ++i) {
110 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
111 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
112 (rxq, struct mlx5_rxq_ctrl, rxq);
114 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
117 if (mlx5_rxq_mprq_enabled(rxq))
120 /* Multi-Packet RQ can't be partially configured. */
121 MLX5_ASSERT(n == 0 || n == n_ibv);
126 * Allocate RX queue elements for Multi-Packet RQ.
129 * Pointer to RX queue structure.
132 * 0 on success, a negative errno value otherwise and rte_errno is set.
135 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
137 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
138 unsigned int wqe_n = 1 << rxq->elts_n;
142 /* Iterate on segments. */
143 for (i = 0; i <= wqe_n; ++i) {
144 struct mlx5_mprq_buf *buf;
146 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
147 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
152 (*rxq->mprq_bufs)[i] = buf;
154 rxq->mprq_repl = buf;
157 "port %u Rx queue %u allocated and configured %u segments",
158 rxq->port_id, rxq->idx, wqe_n);
161 err = rte_errno; /* Save rte_errno before cleanup. */
163 for (i = 0; (i != wqe_n); ++i) {
164 if ((*rxq->mprq_bufs)[i] != NULL)
165 rte_mempool_put(rxq->mprq_mp,
166 (*rxq->mprq_bufs)[i]);
167 (*rxq->mprq_bufs)[i] = NULL;
169 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
170 rxq->port_id, rxq->idx);
171 rte_errno = err; /* Restore rte_errno. */
176 * Allocate RX queue elements for Single-Packet RQ.
179 * Pointer to RX queue structure.
182 * 0 on success, errno value on failure.
185 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
187 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
188 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
192 /* Iterate on segments. */
193 for (i = 0; (i != elts_n); ++i) {
194 struct rte_mbuf *buf;
196 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
198 DRV_LOG(ERR, "port %u empty mbuf pool",
199 PORT_ID(rxq_ctrl->priv));
203 /* Headroom is reserved by rte_pktmbuf_alloc(). */
204 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
205 /* Buffer is supposed to be empty. */
206 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
207 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
208 MLX5_ASSERT(!buf->next);
209 /* Only the first segment keeps headroom. */
211 SET_DATA_OFF(buf, 0);
212 PORT(buf) = rxq_ctrl->rxq.port_id;
213 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
214 PKT_LEN(buf) = DATA_LEN(buf);
216 (*rxq_ctrl->rxq.elts)[i] = buf;
218 /* If Rx vector is activated. */
219 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
220 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
221 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
222 struct rte_pktmbuf_pool_private *priv =
223 (struct rte_pktmbuf_pool_private *)
224 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
227 /* Initialize default rearm_data for vPMD. */
228 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
229 rte_mbuf_refcnt_set(mbuf_init, 1);
230 mbuf_init->nb_segs = 1;
231 mbuf_init->port = rxq->port_id;
232 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
233 mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
235 * prevent compiler reordering:
236 * rearm_data covers previous fields.
238 rte_compiler_barrier();
239 rxq->mbuf_initializer =
240 *(rte_xmm_t *)&mbuf_init->rearm_data;
241 /* Padding with a fake mbuf for vectorized Rx. */
242 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
243 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
246 "port %u Rx queue %u allocated and configured %u segments"
248 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
249 elts_n / (1 << rxq_ctrl->rxq.sges_n));
252 err = rte_errno; /* Save rte_errno before cleanup. */
254 for (i = 0; (i != elts_n); ++i) {
255 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
256 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
257 (*rxq_ctrl->rxq.elts)[i] = NULL;
259 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
260 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
261 rte_errno = err; /* Restore rte_errno. */
266 * Allocate RX queue elements.
269 * Pointer to RX queue structure.
272 * 0 on success, errno value on failure.
275 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
277 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
278 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
282 * Free RX queue elements for Multi-Packet RQ.
285 * Pointer to RX queue structure.
288 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
290 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
293 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
294 rxq->port_id, rxq->idx);
295 if (rxq->mprq_bufs == NULL)
297 MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
298 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
299 if ((*rxq->mprq_bufs)[i] != NULL)
300 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
301 (*rxq->mprq_bufs)[i] = NULL;
303 if (rxq->mprq_repl != NULL) {
304 mlx5_mprq_buf_free(rxq->mprq_repl);
305 rxq->mprq_repl = NULL;
310 * Free RX queue elements for Single-Packet RQ.
313 * Pointer to RX queue structure.
316 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
318 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
319 const uint16_t q_n = (1 << rxq->elts_n);
320 const uint16_t q_mask = q_n - 1;
321 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
324 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
325 PORT_ID(rxq_ctrl->priv), rxq->idx);
326 if (rxq->elts == NULL)
329 * Some mbuf in the Ring belongs to the application. They cannot be
332 if (mlx5_rxq_check_vec_support(rxq) > 0) {
333 for (i = 0; i < used; ++i)
334 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
335 rxq->rq_pi = rxq->rq_ci;
337 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
338 if ((*rxq->elts)[i] != NULL)
339 rte_pktmbuf_free_seg((*rxq->elts)[i]);
340 (*rxq->elts)[i] = NULL;
345 * Free RX queue elements.
348 * Pointer to RX queue structure.
351 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
353 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
354 rxq_free_elts_mprq(rxq_ctrl);
356 rxq_free_elts_sprq(rxq_ctrl);
360 * Returns the per-queue supported offloads.
363 * Pointer to Ethernet device.
366 * Supported Rx offloads.
369 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
371 struct mlx5_priv *priv = dev->data->dev_private;
372 struct mlx5_dev_config *config = &priv->config;
373 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
374 DEV_RX_OFFLOAD_TIMESTAMP |
375 DEV_RX_OFFLOAD_JUMBO_FRAME |
376 DEV_RX_OFFLOAD_RSS_HASH);
378 if (config->hw_fcs_strip)
379 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
382 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
383 DEV_RX_OFFLOAD_UDP_CKSUM |
384 DEV_RX_OFFLOAD_TCP_CKSUM);
385 if (config->hw_vlan_strip)
386 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
387 if (MLX5_LRO_SUPPORTED(dev))
388 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
394 * Returns the per-port supported offloads.
397 * Supported Rx offloads.
400 mlx5_get_rx_port_offloads(void)
402 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
408 * Verify if the queue can be released.
411 * Pointer to Ethernet device.
416 * 1 if the queue can be released
417 * 0 if the queue can not be released, there are references to it.
418 * Negative errno and rte_errno is set if queue doesn't exist.
421 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
423 struct mlx5_priv *priv = dev->data->dev_private;
424 struct mlx5_rxq_ctrl *rxq_ctrl;
426 if (!(*priv->rxqs)[idx]) {
430 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
431 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
435 * Rx queue presetup checks.
438 * Pointer to Ethernet device structure.
442 * Number of descriptors to configure in queue.
445 * 0 on success, a negative errno value otherwise and rte_errno is set.
448 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
450 struct mlx5_priv *priv = dev->data->dev_private;
452 if (!rte_is_power_of_2(*desc)) {
453 *desc = 1 << log2above(*desc);
455 "port %u increased number of descriptors in Rx queue %u"
456 " to the next power of two (%d)",
457 dev->data->port_id, idx, *desc);
459 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
460 dev->data->port_id, idx, *desc);
461 if (idx >= priv->rxqs_n) {
462 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
463 dev->data->port_id, idx, priv->rxqs_n);
464 rte_errno = EOVERFLOW;
467 if (!mlx5_rxq_releasable(dev, idx)) {
468 DRV_LOG(ERR, "port %u unable to release queue index %u",
469 dev->data->port_id, idx);
473 mlx5_rxq_release(dev, idx);
480 * Pointer to Ethernet device structure.
484 * Number of descriptors to configure in queue.
486 * NUMA socket on which memory must be allocated.
488 * Thresholds parameters.
490 * Memory pool for buffer allocations.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
497 unsigned int socket, const struct rte_eth_rxconf *conf,
498 struct rte_mempool *mp)
500 struct mlx5_priv *priv = dev->data->dev_private;
501 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
502 struct mlx5_rxq_ctrl *rxq_ctrl =
503 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
506 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
509 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
511 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
512 dev->data->port_id, idx);
516 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
517 dev->data->port_id, idx);
518 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
525 * Pointer to Ethernet device structure.
529 * Number of descriptors to configure in queue.
530 * @param hairpin_conf
531 * Hairpin configuration parameters.
534 * 0 on success, a negative errno value otherwise and rte_errno is set.
537 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
539 const struct rte_eth_hairpin_conf *hairpin_conf)
541 struct mlx5_priv *priv = dev->data->dev_private;
542 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
543 struct mlx5_rxq_ctrl *rxq_ctrl =
544 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
547 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
550 if (hairpin_conf->peer_count != 1 ||
551 hairpin_conf->peers[0].port != dev->data->port_id ||
552 hairpin_conf->peers[0].queue >= priv->txqs_n) {
553 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
554 " invalid hairpind configuration", dev->data->port_id,
559 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
561 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
562 dev->data->port_id, idx);
566 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
567 dev->data->port_id, idx);
568 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
573 * DPDK callback to release a RX queue.
576 * Generic RX queue pointer.
579 mlx5_rx_queue_release(void *dpdk_rxq)
581 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
582 struct mlx5_rxq_ctrl *rxq_ctrl;
583 struct mlx5_priv *priv;
587 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
588 priv = rxq_ctrl->priv;
589 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
590 rte_panic("port %u Rx queue %u is still used by a flow and"
591 " cannot be removed\n",
592 PORT_ID(priv), rxq->idx);
593 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
597 * Get an Rx queue Verbs/DevX object.
600 * Pointer to Ethernet device.
602 * Queue index in DPDK Rx queue array
605 * The Verbs/DevX object if it exists.
607 static struct mlx5_rxq_obj *
608 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
610 struct mlx5_priv *priv = dev->data->dev_private;
611 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
612 struct mlx5_rxq_ctrl *rxq_ctrl;
614 if (idx >= priv->rxqs_n)
618 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
620 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
621 return rxq_ctrl->obj;
625 * Release the resources allocated for an RQ DevX object.
628 * DevX Rx queue object.
631 rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
633 if (rxq_ctrl->rxq.wqes) {
634 mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
635 rxq_ctrl->rxq.wqes = NULL;
637 if (rxq_ctrl->wq_umem) {
638 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
639 rxq_ctrl->wq_umem = NULL;
644 * Release the resources allocated for the Rx CQ DevX object.
647 * DevX Rx queue object.
650 rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
652 if (rxq_ctrl->rxq.cqes) {
653 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);
654 rxq_ctrl->rxq.cqes = NULL;
656 if (rxq_ctrl->cq_umem) {
657 mlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);
658 rxq_ctrl->cq_umem = NULL;
663 * Release an Rx hairpin related resources.
666 * Hairpin Rx queue object.
669 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
671 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
673 MLX5_ASSERT(rxq_obj);
674 rq_attr.state = MLX5_RQC_STATE_RST;
675 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
676 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
677 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
681 * Release an Rx verbs/DevX queue object.
684 * Verbs/DevX Rx queue object.
687 * 1 while a reference on it exists, 0 when freed.
690 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
692 MLX5_ASSERT(rxq_obj);
693 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
694 switch (rxq_obj->type) {
695 case MLX5_RXQ_OBJ_TYPE_IBV:
696 MLX5_ASSERT(rxq_obj->wq);
697 MLX5_ASSERT(rxq_obj->ibv_cq);
698 rxq_free_elts(rxq_obj->rxq_ctrl);
699 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
700 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
701 if (rxq_obj->ibv_channel)
702 claim_zero(mlx5_glue->destroy_comp_channel
703 (rxq_obj->ibv_channel));
705 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
706 MLX5_ASSERT(rxq_obj->rq);
707 MLX5_ASSERT(rxq_obj->devx_cq);
708 rxq_free_elts(rxq_obj->rxq_ctrl);
709 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
710 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));
711 if (rxq_obj->devx_channel)
712 mlx5_glue->devx_destroy_event_channel
713 (rxq_obj->devx_channel);
714 rxq_release_devx_rq_resources(rxq_obj->rxq_ctrl);
715 rxq_release_devx_cq_resources(rxq_obj->rxq_ctrl);
717 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
718 MLX5_ASSERT(rxq_obj->rq);
719 rxq_obj_hairpin_release(rxq_obj);
722 LIST_REMOVE(rxq_obj, next);
730 * Allocate queue vector and fill epoll fd list for Rx interrupts.
733 * Pointer to Ethernet device.
736 * 0 on success, a negative errno value otherwise and rte_errno is set.
739 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
741 struct mlx5_priv *priv = dev->data->dev_private;
743 unsigned int rxqs_n = priv->rxqs_n;
744 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
745 unsigned int count = 0;
746 struct rte_intr_handle *intr_handle = dev->intr_handle;
748 if (!dev->data->dev_conf.intr_conf.rxq)
750 mlx5_rx_intr_vec_disable(dev);
751 intr_handle->intr_vec = mlx5_malloc(0,
752 n * sizeof(intr_handle->intr_vec[0]),
754 if (intr_handle->intr_vec == NULL) {
756 "port %u failed to allocate memory for interrupt"
757 " vector, Rx interrupts will not be supported",
762 intr_handle->type = RTE_INTR_HANDLE_EXT;
763 for (i = 0; i != n; ++i) {
764 /* This rxq obj must not be released in this function. */
765 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
768 /* Skip queues that cannot request interrupts. */
769 if (!rxq_obj || (!rxq_obj->ibv_channel &&
770 !rxq_obj->devx_channel)) {
771 /* Use invalid intr_vec[] index to disable entry. */
772 intr_handle->intr_vec[i] =
773 RTE_INTR_VEC_RXTX_OFFSET +
774 RTE_MAX_RXTX_INTR_VEC_ID;
777 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
779 "port %u too many Rx queues for interrupt"
780 " vector size (%d), Rx interrupts cannot be"
782 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
783 mlx5_rx_intr_vec_disable(dev);
787 rc = mlx5_os_set_nonblock_channel_fd(rxq_obj->fd);
791 "port %u failed to make Rx interrupt file"
792 " descriptor %d non-blocking for queue index"
794 dev->data->port_id, rxq_obj->fd, i);
795 mlx5_rx_intr_vec_disable(dev);
798 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
799 intr_handle->efds[count] = rxq_obj->fd;
803 mlx5_rx_intr_vec_disable(dev);
805 intr_handle->nb_efd = count;
810 * Clean up Rx interrupts handler.
813 * Pointer to Ethernet device.
816 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
818 struct mlx5_priv *priv = dev->data->dev_private;
819 struct rte_intr_handle *intr_handle = dev->intr_handle;
821 unsigned int rxqs_n = priv->rxqs_n;
822 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
824 if (!dev->data->dev_conf.intr_conf.rxq)
826 if (!intr_handle->intr_vec)
828 for (i = 0; i != n; ++i) {
829 struct mlx5_rxq_ctrl *rxq_ctrl;
830 struct mlx5_rxq_data *rxq_data;
832 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
833 RTE_MAX_RXTX_INTR_VEC_ID)
836 * Need to access directly the queue to release the reference
837 * kept in mlx5_rx_intr_vec_enable().
839 rxq_data = (*priv->rxqs)[i];
840 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
842 mlx5_rxq_obj_release(rxq_ctrl->obj);
845 rte_intr_free_epoll_fd(intr_handle);
846 if (intr_handle->intr_vec)
847 mlx5_free(intr_handle->intr_vec);
848 intr_handle->nb_efd = 0;
849 intr_handle->intr_vec = NULL;
853 * MLX5 CQ notification .
856 * Pointer to receive queue structure.
858 * Sequence number per receive queue .
861 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
864 uint32_t doorbell_hi;
866 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
868 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
869 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
870 doorbell = (uint64_t)doorbell_hi << 32;
871 doorbell |= rxq->cqn;
872 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
873 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
874 cq_db_reg, rxq->uar_lock_cq);
878 * DPDK callback for Rx queue interrupt enable.
881 * Pointer to Ethernet device structure.
886 * 0 on success, a negative errno value otherwise and rte_errno is set.
889 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
891 struct mlx5_priv *priv = dev->data->dev_private;
892 struct mlx5_rxq_data *rxq_data;
893 struct mlx5_rxq_ctrl *rxq_ctrl;
895 rxq_data = (*priv->rxqs)[rx_queue_id];
900 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
902 struct mlx5_rxq_obj *rxq_obj;
904 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
909 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
910 mlx5_rxq_obj_release(rxq_obj);
916 * DPDK callback for Rx queue interrupt disable.
919 * Pointer to Ethernet device structure.
924 * 0 on success, a negative errno value otherwise and rte_errno is set.
927 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
929 struct mlx5_priv *priv = dev->data->dev_private;
930 struct mlx5_rxq_data *rxq_data;
931 struct mlx5_rxq_ctrl *rxq_ctrl;
932 struct mlx5_rxq_obj *rxq_obj = NULL;
933 struct ibv_cq *ev_cq;
937 rxq_data = (*priv->rxqs)[rx_queue_id];
942 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
945 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
950 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
951 ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel, &ev_cq,
953 if (ret || ev_cq != rxq_obj->ibv_cq) {
957 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);
958 } else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
959 #ifdef HAVE_IBV_DEVX_EVENT
960 struct mlx5dv_devx_async_event_hdr *event_data = NULL;
962 ret = mlx5_glue->devx_get_event
963 (rxq_obj->devx_channel, event_data,
964 sizeof(struct mlx5dv_devx_async_event_hdr));
965 if (ret <= 0 || event_data->cookie !=
966 (uint64_t)(uintptr_t)rxq_obj->devx_cq) {
970 #endif /* HAVE_IBV_DEVX_EVENT */
972 rxq_data->cq_arm_sn++;
973 mlx5_rxq_obj_release(rxq_obj);
976 ret = rte_errno; /* Save rte_errno before cleanup. */
978 mlx5_rxq_obj_release(rxq_obj);
979 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
980 dev->data->port_id, rx_queue_id);
981 rte_errno = ret; /* Restore rte_errno. */
986 * Create a CQ Verbs object.
989 * Pointer to Ethernet device.
991 * Pointer to device private data.
993 * Pointer to Rx queue data.
995 * Number of CQEs in CQ.
997 * Pointer to Rx queue object data.
1000 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1002 static struct ibv_cq *
1003 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1004 struct mlx5_rxq_data *rxq_data,
1005 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
1008 struct ibv_cq_init_attr_ex ibv;
1009 struct mlx5dv_cq_init_attr mlx5;
1012 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
1014 .channel = rxq_obj->ibv_channel,
1017 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
1020 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
1022 cq_attr.mlx5.comp_mask |=
1023 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
1024 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1025 cq_attr.mlx5.cqe_comp_res_format =
1026 mlx5_rxq_mprq_enabled(rxq_data) ?
1027 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
1028 MLX5DV_CQE_RES_FORMAT_HASH;
1030 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1033 * For vectorized Rx, it must not be doubled in order to
1034 * make cq_ci and rq_ci aligned.
1036 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1037 cq_attr.ibv.cqe *= 2;
1038 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1040 "port %u Rx CQE compression is disabled for HW"
1042 dev->data->port_id);
1043 } else if (priv->config.cqe_comp && rxq_data->lro) {
1045 "port %u Rx CQE compression is disabled for LRO",
1046 dev->data->port_id);
1048 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1049 if (priv->config.cqe_pad) {
1050 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1051 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1054 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1060 * Create a WQ Verbs object.
1063 * Pointer to Ethernet device.
1065 * Pointer to device private data.
1067 * Pointer to Rx queue data.
1069 * Queue index in DPDK Rx queue array
1071 * Number of WQEs in WQ.
1073 * Pointer to Rx queue object data.
1076 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1078 static struct ibv_wq *
1079 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1080 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1081 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1084 struct ibv_wq_init_attr ibv;
1085 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1086 struct mlx5dv_wq_init_attr mlx5;
1090 wq_attr.ibv = (struct ibv_wq_init_attr){
1091 .wq_context = NULL, /* Could be useful in the future. */
1092 .wq_type = IBV_WQT_RQ,
1093 /* Max number of outstanding WRs. */
1094 .max_wr = wqe_n >> rxq_data->sges_n,
1095 /* Max number of scatter/gather elements in a WR. */
1096 .max_sge = 1 << rxq_data->sges_n,
1098 .cq = rxq_obj->ibv_cq,
1099 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1100 .create_flags = (rxq_data->vlan_strip ?
1101 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1103 /* By default, FCS (CRC) is stripped by hardware. */
1104 if (rxq_data->crc_present) {
1105 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1106 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1108 if (priv->config.hw_padding) {
1109 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1110 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1111 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1112 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1113 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1114 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1117 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1118 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1121 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1122 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1123 &wq_attr.mlx5.striding_rq_attrs;
1125 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1126 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1127 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1128 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1129 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1132 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1135 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1139 * Make sure number of WRs*SGEs match expectations since a queue
1140 * cannot allocate more than "desc" buffers.
1142 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1143 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1145 "port %u Rx queue %u requested %u*%u but got"
1147 dev->data->port_id, idx,
1148 wqe_n >> rxq_data->sges_n,
1149 (1 << rxq_data->sges_n),
1150 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1151 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1160 * Fill common fields of create RQ attributes structure.
1163 * Pointer to Rx queue data.
1165 * CQ number to use with this RQ.
1167 * RQ attributes structure to fill..
1170 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1171 struct mlx5_devx_create_rq_attr *rq_attr)
1173 rq_attr->state = MLX5_RQC_STATE_RST;
1174 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1176 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1180 * Fill common fields of DevX WQ attributes structure.
1183 * Pointer to device private data.
1185 * Pointer to Rx queue control structure.
1187 * WQ attributes structure to fill..
1190 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1191 struct mlx5_devx_wq_attr *wq_attr)
1193 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1194 MLX5_WQ_END_PAD_MODE_ALIGN :
1195 MLX5_WQ_END_PAD_MODE_NONE;
1196 wq_attr->pd = priv->sh->pdn;
1197 wq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;
1198 wq_attr->dbr_umem_id = rxq_ctrl->rq_dbr_umem_id;
1199 wq_attr->dbr_umem_valid = 1;
1200 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1201 wq_attr->wq_umem_valid = 1;
1205 * Create a RQ object using DevX.
1208 * Pointer to Ethernet device.
1210 * Queue index in DPDK Rx queue array
1212 * CQ number to use with this RQ.
1215 * The DevX object initialised, NULL otherwise and rte_errno is set.
1217 static struct mlx5_devx_obj *
1218 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1220 struct mlx5_priv *priv = dev->data->dev_private;
1221 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1222 struct mlx5_rxq_ctrl *rxq_ctrl =
1223 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1224 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
1225 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1226 uint32_t wq_size = 0;
1227 uint32_t wqe_size = 0;
1228 uint32_t log_wqe_size = 0;
1230 struct mlx5_devx_obj *rq;
1232 /* Fill RQ attributes. */
1233 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1234 rq_attr.flush_in_error_en = 1;
1235 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1236 /* Fill WQ attributes for this RQ. */
1237 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1238 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1240 * Number of strides in each WQE:
1241 * 512*2^single_wqe_log_num_of_strides.
1243 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1244 rxq_data->strd_num_n -
1245 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1246 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1247 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1248 rxq_data->strd_sz_n -
1249 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1250 wqe_size = sizeof(struct mlx5_wqe_mprq);
1252 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1253 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1255 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1256 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1257 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1258 /* Calculate and allocate WQ memory space. */
1259 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1260 wq_size = wqe_n * wqe_size;
1261 size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
1262 if (alignment == (size_t)-1) {
1263 DRV_LOG(ERR, "Failed to get mem page size");
1267 buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
1268 alignment, rxq_ctrl->socket);
1271 rxq_data->wqes = buf;
1272 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1274 if (!rxq_ctrl->wq_umem) {
1278 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1279 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1281 rxq_release_devx_rq_resources(rxq_ctrl);
1286 * Create a DevX CQ object for an Rx queue.
1289 * Pointer to Ethernet device.
1291 * Number of CQEs in CQ.
1293 * Queue index in DPDK Rx queue array
1295 * Pointer to Rx queue object data.
1298 * The DevX object initialised, NULL otherwise and rte_errno is set.
1300 static struct mlx5_devx_obj *
1301 mlx5_devx_cq_new(struct rte_eth_dev *dev, unsigned int cqe_n, uint16_t idx,
1302 struct mlx5_rxq_obj *rxq_obj)
1304 struct mlx5_devx_obj *cq_obj = 0;
1305 struct mlx5_devx_cq_attr cq_attr = { 0 };
1306 struct mlx5_priv *priv = dev->data->dev_private;
1307 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1308 struct mlx5_rxq_ctrl *rxq_ctrl =
1309 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1310 size_t page_size = rte_mem_page_size();
1311 uint32_t lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
1314 uint16_t event_nums[1] = {0};
1319 if (page_size == (size_t)-1) {
1320 DRV_LOG(ERR, "Failed to get page_size.");
1323 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
1325 cq_attr.cqe_comp_en = MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
1326 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1327 cq_attr.mini_cqe_res_format =
1328 mlx5_rxq_mprq_enabled(rxq_data) ?
1329 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
1330 MLX5DV_CQE_RES_FORMAT_HASH;
1332 cq_attr.mini_cqe_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1335 * For vectorized Rx, it must not be doubled in order to
1336 * make cq_ci and rq_ci aligned.
1338 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1340 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1342 "port %u Rx CQE compression is disabled for HW"
1344 dev->data->port_id);
1345 } else if (priv->config.cqe_comp && rxq_data->lro) {
1347 "port %u Rx CQE compression is disabled for LRO",
1348 dev->data->port_id);
1350 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1351 if (priv->config.cqe_pad)
1352 cq_attr.cqe_size = MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1354 log_cqe_n = log2above(cqe_n);
1355 cq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);
1356 /* Query the EQN for this core. */
1357 if (mlx5_glue->devx_query_eqn(priv->sh->ctx, lcore, &eqn)) {
1358 DRV_LOG(ERR, "Failed to query EQN for CQ.");
1362 buf = rte_calloc_socket(__func__, 1, cq_size, page_size,
1365 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
1368 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)buf;
1369 rxq_ctrl->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, buf,
1371 IBV_ACCESS_LOCAL_WRITE);
1372 if (!rxq_ctrl->cq_umem) {
1373 DRV_LOG(ERR, "Failed to register umem for CQ.");
1376 cq_attr.uar_page_id = priv->sh->devx_rx_uar->page_id;
1377 cq_attr.q_umem_id = rxq_ctrl->cq_umem->umem_id;
1378 cq_attr.q_umem_valid = 1;
1379 cq_attr.log_cq_size = log_cqe_n;
1380 cq_attr.log_page_size = rte_log2_u32(page_size);
1381 cq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;
1382 cq_attr.db_umem_id = rxq_ctrl->cq_dbr_umem_id;
1383 cq_attr.db_umem_valid = rxq_ctrl->cq_dbr_umem_id_valid;
1384 cq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);
1387 rxq_data->cqe_n = log_cqe_n;
1388 rxq_data->cqn = cq_obj->id;
1389 if (rxq_obj->devx_channel) {
1390 ret = mlx5_glue->devx_subscribe_devx_event
1391 (rxq_obj->devx_channel,
1395 (uint64_t)(uintptr_t)cq_obj);
1397 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
1402 /* Initialise CQ to 1's to mark HW ownership for all CQEs. */
1403 memset((void *)(uintptr_t)rxq_data->cqes, 0xFF, cq_size);
1406 rxq_release_devx_cq_resources(rxq_ctrl);
1411 * Create the Rx hairpin queue object.
1414 * Pointer to Ethernet device.
1416 * Queue index in DPDK Rx queue array
1419 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1421 static struct mlx5_rxq_obj *
1422 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1424 struct mlx5_priv *priv = dev->data->dev_private;
1425 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1426 struct mlx5_rxq_ctrl *rxq_ctrl =
1427 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1428 struct mlx5_devx_create_rq_attr attr = { 0 };
1429 struct mlx5_rxq_obj *tmpl = NULL;
1430 uint32_t max_wq_data;
1432 MLX5_ASSERT(rxq_data);
1433 MLX5_ASSERT(!rxq_ctrl->obj);
1434 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1438 "port %u Rx queue %u cannot allocate verbs resources",
1439 dev->data->port_id, rxq_data->idx);
1443 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1444 tmpl->rxq_ctrl = rxq_ctrl;
1446 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1447 /* Jumbo frames > 9KB should be supported, and more packets. */
1448 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1449 if (priv->config.log_hp_size > max_wq_data) {
1450 DRV_LOG(ERR, "total data size %u power of 2 is "
1451 "too large for hairpin",
1452 priv->config.log_hp_size);
1457 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1459 attr.wq_attr.log_hairpin_data_sz =
1460 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1461 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1463 /* Set the packets number to the maximum value for performance. */
1464 attr.wq_attr.log_hairpin_num_packets =
1465 attr.wq_attr.log_hairpin_data_sz -
1466 MLX5_HAIRPIN_QUEUE_STRIDE;
1467 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1471 "port %u Rx hairpin queue %u can't create rq object",
1472 dev->data->port_id, idx);
1477 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1478 idx, (void *)&tmpl);
1479 rte_atomic32_inc(&tmpl->refcnt);
1480 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1481 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1486 * Create the Rx queue Verbs/DevX object.
1489 * Pointer to Ethernet device.
1491 * Queue index in DPDK Rx queue array
1493 * Type of Rx queue object to create.
1496 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1498 struct mlx5_rxq_obj *
1499 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1500 enum mlx5_rxq_obj_type type)
1502 struct mlx5_priv *priv = dev->data->dev_private;
1503 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1504 struct mlx5_rxq_ctrl *rxq_ctrl =
1505 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1506 struct ibv_wq_attr mod;
1508 unsigned int wqe_n = 1 << rxq_data->elts_n;
1509 struct mlx5_rxq_obj *tmpl = NULL;
1510 struct mlx5dv_cq cq_info;
1511 struct mlx5dv_rwq rwq;
1513 struct mlx5dv_obj obj;
1515 MLX5_ASSERT(rxq_data);
1516 MLX5_ASSERT(!rxq_ctrl->obj);
1517 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1518 return mlx5_rxq_obj_hairpin_new(dev, idx);
1519 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1520 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1521 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1525 "port %u Rx queue %u cannot allocate resources",
1526 dev->data->port_id, rxq_data->idx);
1531 tmpl->rxq_ctrl = rxq_ctrl;
1532 if (rxq_ctrl->irq) {
1533 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1535 mlx5_glue->create_comp_channel(priv->sh->ctx);
1536 if (!tmpl->ibv_channel) {
1537 DRV_LOG(ERR, "port %u: comp channel creation "
1538 "failure", dev->data->port_id);
1542 tmpl->fd = tmpl->ibv_channel->fd;
1543 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1545 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
1547 tmpl->devx_channel =
1548 mlx5_glue->devx_create_event_channel
1551 if (!tmpl->devx_channel) {
1554 "Failed to create event channel %d.",
1558 tmpl->fd = tmpl->devx_channel->fd;
1561 if (mlx5_rxq_mprq_enabled(rxq_data))
1562 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1565 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1566 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
1567 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1568 dev->data->port_id, priv->sh->device_attr.max_sge);
1569 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1570 /* Create CQ using Verbs API. */
1571 tmpl->ibv_cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n,
1573 if (!tmpl->ibv_cq) {
1574 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1575 dev->data->port_id, idx);
1579 obj.cq.in = tmpl->ibv_cq;
1580 obj.cq.out = &cq_info;
1581 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1586 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1588 "port %u wrong MLX5_CQE_SIZE environment "
1589 "variable value: it should be set to %u",
1590 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1594 /* Fill the rings. */
1595 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1596 rxq_data->cq_db = cq_info.dbrec;
1598 (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1599 rxq_data->cq_uar = cq_info.cq_uar;
1600 rxq_data->cqn = cq_info.cqn;
1601 /* Create WQ (RQ) using Verbs API. */
1602 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1605 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1606 dev->data->port_id, idx);
1610 /* Change queue state to ready. */
1611 mod = (struct ibv_wq_attr){
1612 .attr_mask = IBV_WQ_ATTR_STATE,
1613 .wq_state = IBV_WQS_RDY,
1615 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1618 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1619 " failed", dev->data->port_id, idx);
1623 obj.rwq.in = tmpl->wq;
1625 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1630 rxq_data->wqes = rwq.buf;
1631 rxq_data->rq_db = rwq.dbrec;
1632 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1633 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
1634 struct mlx5_devx_dbr_page *dbr_page;
1637 /* Allocate CQ door-bell. */
1638 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1640 if (dbr_offset < 0) {
1641 DRV_LOG(ERR, "Failed to allocate CQ door-bell.");
1644 rxq_ctrl->cq_dbr_offset = dbr_offset;
1645 rxq_ctrl->cq_dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
1646 rxq_ctrl->cq_dbr_umem_id_valid = 1;
1648 (uint32_t *)((uintptr_t)dbr_page->dbrs +
1649 (uintptr_t)rxq_ctrl->cq_dbr_offset);
1650 rxq_data->cq_uar = priv->sh->devx_rx_uar->base_addr;
1651 /* Create CQ using DevX API. */
1652 tmpl->devx_cq = mlx5_devx_cq_new(dev, cqe_n, idx, tmpl);
1653 if (!tmpl->devx_cq) {
1654 DRV_LOG(ERR, "Failed to create CQ.");
1657 /* Allocate RQ door-bell. */
1658 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1660 if (dbr_offset < 0) {
1661 DRV_LOG(ERR, "Failed to allocate RQ door-bell.");
1664 rxq_ctrl->rq_dbr_offset = dbr_offset;
1665 rxq_ctrl->rq_dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
1666 rxq_ctrl->rq_dbr_umem_id_valid = 1;
1668 (uint32_t *)((uintptr_t)dbr_page->dbrs +
1669 (uintptr_t)rxq_ctrl->rq_dbr_offset);
1670 /* Create RQ using DevX API. */
1671 tmpl->rq = mlx5_devx_rq_new(dev, idx, tmpl->devx_cq->id);
1673 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1674 dev->data->port_id, idx);
1678 /* Change queue state to ready. */
1679 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1680 rq_attr.state = MLX5_RQC_STATE_RDY;
1681 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1685 rxq_data->cq_arm_sn = 0;
1686 mlx5_rxq_initialize(rxq_data);
1687 rxq_data->cq_ci = 0;
1688 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1689 idx, (void *)&tmpl);
1690 rte_atomic32_inc(&tmpl->refcnt);
1691 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1692 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1696 ret = rte_errno; /* Save rte_errno before cleanup. */
1697 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1699 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1701 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));
1702 if (tmpl->ibv_channel)
1703 claim_zero(mlx5_glue->destroy_comp_channel
1704 (tmpl->ibv_channel));
1705 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1707 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1709 claim_zero(mlx5_devx_cmd_destroy
1711 if (tmpl->devx_channel)
1712 mlx5_glue->devx_destroy_event_channel
1713 (tmpl->devx_channel);
1716 rte_errno = ret; /* Restore rte_errno. */
1718 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1719 rxq_release_devx_rq_resources(rxq_ctrl);
1720 rxq_release_devx_cq_resources(rxq_ctrl);
1722 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1727 * Verify the Rx queue objects list is empty
1730 * Pointer to Ethernet device.
1733 * The number of objects not released.
1736 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1738 struct mlx5_priv *priv = dev->data->dev_private;
1740 struct mlx5_rxq_obj *rxq_obj;
1742 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1743 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1744 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1751 * Callback function to initialize mbufs for Multi-Packet RQ.
1754 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1755 void *_m, unsigned int i __rte_unused)
1757 struct mlx5_mprq_buf *buf = _m;
1758 struct rte_mbuf_ext_shared_info *shinfo;
1759 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1762 memset(_m, 0, sizeof(*buf));
1764 rte_atomic16_set(&buf->refcnt, 1);
1765 for (j = 0; j != strd_n; ++j) {
1766 shinfo = &buf->shinfos[j];
1767 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1768 shinfo->fcb_opaque = buf;
1773 * Free mempool of Multi-Packet RQ.
1776 * Pointer to Ethernet device.
1779 * 0 on success, negative errno value on failure.
1782 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1784 struct mlx5_priv *priv = dev->data->dev_private;
1785 struct rte_mempool *mp = priv->mprq_mp;
1790 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1791 dev->data->port_id, mp->name);
1793 * If a buffer in the pool has been externally attached to a mbuf and it
1794 * is still in use by application, destroying the Rx queue can spoil
1795 * the packet. It is unlikely to happen but if application dynamically
1796 * creates and destroys with holding Rx packets, this can happen.
1798 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1799 * RQ isn't provided by application but managed by PMD.
1801 if (!rte_mempool_full(mp)) {
1803 "port %u mempool for Multi-Packet RQ is still in use",
1804 dev->data->port_id);
1808 rte_mempool_free(mp);
1809 /* Unset mempool for each Rx queue. */
1810 for (i = 0; i != priv->rxqs_n; ++i) {
1811 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1815 rxq->mprq_mp = NULL;
1817 priv->mprq_mp = NULL;
1822 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1823 * mempool. If already allocated, reuse it if there're enough elements.
1824 * Otherwise, resize it.
1827 * Pointer to Ethernet device.
1830 * 0 on success, negative errno value on failure.
1833 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1835 struct mlx5_priv *priv = dev->data->dev_private;
1836 struct rte_mempool *mp = priv->mprq_mp;
1837 char name[RTE_MEMPOOL_NAMESIZE];
1838 unsigned int desc = 0;
1839 unsigned int buf_len;
1840 unsigned int obj_num;
1841 unsigned int obj_size;
1842 unsigned int strd_num_n = 0;
1843 unsigned int strd_sz_n = 0;
1845 unsigned int n_ibv = 0;
1847 if (!mlx5_mprq_enabled(dev))
1849 /* Count the total number of descriptors configured. */
1850 for (i = 0; i != priv->rxqs_n; ++i) {
1851 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1852 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1853 (rxq, struct mlx5_rxq_ctrl, rxq);
1855 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1858 desc += 1 << rxq->elts_n;
1859 /* Get the max number of strides. */
1860 if (strd_num_n < rxq->strd_num_n)
1861 strd_num_n = rxq->strd_num_n;
1862 /* Get the max size of a stride. */
1863 if (strd_sz_n < rxq->strd_sz_n)
1864 strd_sz_n = rxq->strd_sz_n;
1866 MLX5_ASSERT(strd_num_n && strd_sz_n);
1867 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1868 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1869 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1871 * Received packets can be either memcpy'd or externally referenced. In
1872 * case that the packet is attached to an mbuf as an external buffer, as
1873 * it isn't possible to predict how the buffers will be queued by
1874 * application, there's no option to exactly pre-allocate needed buffers
1875 * in advance but to speculatively prepares enough buffers.
1877 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1878 * received packets to buffers provided by application (rxq->mp) until
1879 * this Mempool gets available again.
1882 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1884 * rte_mempool_create_empty() has sanity check to refuse large cache
1885 * size compared to the number of elements.
1886 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1887 * constant number 2 instead.
1889 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1890 /* Check a mempool is already allocated and if it can be resued. */
1891 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1892 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1893 dev->data->port_id, mp->name);
1896 } else if (mp != NULL) {
1897 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1898 dev->data->port_id, mp->name);
1900 * If failed to free, which means it may be still in use, no way
1901 * but to keep using the existing one. On buffer underrun,
1902 * packets will be memcpy'd instead of external buffer
1905 if (mlx5_mprq_free_mp(dev)) {
1906 if (mp->elt_size >= obj_size)
1912 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1913 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1914 0, NULL, NULL, mlx5_mprq_buf_init,
1915 (void *)(uintptr_t)(1 << strd_num_n),
1916 dev->device->numa_node, 0);
1919 "port %u failed to allocate a mempool for"
1920 " Multi-Packet RQ, count=%u, size=%u",
1921 dev->data->port_id, obj_num, obj_size);
1927 /* Set mempool for each Rx queue. */
1928 for (i = 0; i != priv->rxqs_n; ++i) {
1929 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1930 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1931 (rxq, struct mlx5_rxq_ctrl, rxq);
1933 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1937 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1938 dev->data->port_id);
1942 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1943 sizeof(struct rte_vlan_hdr) * 2 + \
1944 sizeof(struct rte_ipv6_hdr)))
1945 #define MAX_TCP_OPTION_SIZE 40u
1946 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1947 sizeof(struct rte_tcp_hdr) + \
1948 MAX_TCP_OPTION_SIZE))
1951 * Adjust the maximum LRO massage size.
1954 * Pointer to Ethernet device.
1957 * @param max_lro_size
1958 * The maximum size for LRO packet.
1961 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1962 uint32_t max_lro_size)
1964 struct mlx5_priv *priv = dev->data->dev_private;
1966 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1967 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1968 MLX5_MAX_TCP_HDR_OFFSET)
1969 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1970 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1971 MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1972 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1973 if (priv->max_lro_msg_size)
1974 priv->max_lro_msg_size =
1975 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1977 priv->max_lro_msg_size = max_lro_size;
1979 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1980 dev->data->port_id, idx,
1981 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1985 * Create a DPDK Rx queue.
1988 * Pointer to Ethernet device.
1992 * Number of descriptors to configure in queue.
1994 * NUMA socket on which memory must be allocated.
1997 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1999 struct mlx5_rxq_ctrl *
2000 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2001 unsigned int socket, const struct rte_eth_rxconf *conf,
2002 struct rte_mempool *mp)
2004 struct mlx5_priv *priv = dev->data->dev_private;
2005 struct mlx5_rxq_ctrl *tmpl;
2006 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
2007 unsigned int mprq_stride_nums;
2008 unsigned int mprq_stride_size;
2009 unsigned int mprq_stride_cap;
2010 struct mlx5_dev_config *config = &priv->config;
2012 * Always allocate extra slots, even if eventually
2013 * the vector Rx will not be used.
2016 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
2017 uint64_t offloads = conf->offloads |
2018 dev->data->dev_conf.rxmode.offloads;
2019 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
2020 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
2021 unsigned int max_rx_pkt_len = lro_on_queue ?
2022 dev->data->dev_conf.rxmode.max_lro_pkt_size :
2023 dev->data->dev_conf.rxmode.max_rx_pkt_len;
2024 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
2025 RTE_PKTMBUF_HEADROOM;
2026 unsigned int max_lro_size = 0;
2027 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
2029 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
2030 DEV_RX_OFFLOAD_SCATTER)) {
2031 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
2032 " configured and no enough mbuf space(%u) to contain "
2033 "the maximum RX packet length(%u) with head-room(%u)",
2034 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
2035 RTE_PKTMBUF_HEADROOM);
2039 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
2040 desc_n * sizeof(struct rte_mbuf *), 0, socket);
2045 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
2046 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
2047 MLX5_MR_BTREE_CACHE_N, socket)) {
2048 /* rte_errno is already set. */
2051 tmpl->socket = socket;
2052 if (dev->data->dev_conf.intr_conf.rxq)
2054 mprq_stride_nums = config->mprq.stride_num_n ?
2055 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
2056 mprq_stride_size = non_scatter_min_mbuf_size <=
2057 (1U << config->mprq.max_stride_size_n) ?
2058 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
2059 mprq_stride_cap = (config->mprq.stride_num_n ?
2060 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
2061 (config->mprq.stride_size_n ?
2062 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
2064 * This Rx queue can be configured as a Multi-Packet RQ if all of the
2065 * following conditions are met:
2066 * - MPRQ is enabled.
2067 * - The number of descs is more than the number of strides.
2068 * - max_rx_pkt_len plus overhead is less than the max size
2069 * of a stride or mprq_stride_size is specified by a user.
2070 * Need to nake sure that there are enough stides to encap
2071 * the maximum packet size in case mprq_stride_size is set.
2072 * Otherwise, enable Rx scatter if necessary.
2074 if (mprq_en && desc > (1U << mprq_stride_nums) &&
2075 (non_scatter_min_mbuf_size <=
2076 (1U << config->mprq.max_stride_size_n) ||
2077 (config->mprq.stride_size_n &&
2078 non_scatter_min_mbuf_size <= mprq_stride_cap))) {
2079 /* TODO: Rx scatter isn't supported yet. */
2080 tmpl->rxq.sges_n = 0;
2081 /* Trim the number of descs needed. */
2082 desc >>= mprq_stride_nums;
2083 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
2084 config->mprq.stride_num_n : mprq_stride_nums;
2085 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
2086 config->mprq.stride_size_n : mprq_stride_size;
2087 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
2088 tmpl->rxq.strd_scatter_en =
2089 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
2090 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
2091 config->mprq.max_memcpy_len);
2092 max_lro_size = RTE_MIN(max_rx_pkt_len,
2093 (1u << tmpl->rxq.strd_num_n) *
2094 (1u << tmpl->rxq.strd_sz_n));
2096 "port %u Rx queue %u: Multi-Packet RQ is enabled"
2097 " strd_num_n = %u, strd_sz_n = %u",
2098 dev->data->port_id, idx,
2099 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
2100 } else if (max_rx_pkt_len <= first_mb_free_size) {
2101 tmpl->rxq.sges_n = 0;
2102 max_lro_size = max_rx_pkt_len;
2103 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
2104 unsigned int size = non_scatter_min_mbuf_size;
2105 unsigned int sges_n;
2107 if (lro_on_queue && first_mb_free_size <
2108 MLX5_MAX_LRO_HEADER_FIX) {
2109 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
2110 " to include the max header size(%u) for LRO",
2111 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
2112 rte_errno = ENOTSUP;
2116 * Determine the number of SGEs needed for a full packet
2117 * and round it to the next power of two.
2119 sges_n = log2above((size / mb_len) + !!(size % mb_len));
2120 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
2122 "port %u too many SGEs (%u) needed to handle"
2123 " requested maximum packet size %u, the maximum"
2124 " supported are %u", dev->data->port_id,
2125 1 << sges_n, max_rx_pkt_len,
2126 1u << MLX5_MAX_LOG_RQ_SEGS);
2127 rte_errno = ENOTSUP;
2130 tmpl->rxq.sges_n = sges_n;
2131 max_lro_size = max_rx_pkt_len;
2133 if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
2135 "port %u MPRQ is requested but cannot be enabled\n"
2136 " (requested: pkt_sz = %u, desc_num = %u,"
2137 " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
2138 " supported: min_rxqs_num = %u,"
2139 " min_stride_sz = %u, max_stride_sz = %u).",
2140 dev->data->port_id, non_scatter_min_mbuf_size,
2142 config->mprq.stride_size_n ?
2143 (1U << config->mprq.stride_size_n) :
2144 (1U << mprq_stride_size),
2145 config->mprq.stride_num_n ?
2146 (1U << config->mprq.stride_num_n) :
2147 (1U << mprq_stride_nums),
2148 config->mprq.min_rxqs_num,
2149 (1U << config->mprq.min_stride_size_n),
2150 (1U << config->mprq.max_stride_size_n));
2151 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
2152 dev->data->port_id, 1 << tmpl->rxq.sges_n);
2153 if (desc % (1 << tmpl->rxq.sges_n)) {
2155 "port %u number of Rx queue descriptors (%u) is not a"
2156 " multiple of SGEs per packet (%u)",
2159 1 << tmpl->rxq.sges_n);
2163 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
2164 /* Toggle RX checksum offload if hardware supports it. */
2165 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
2166 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
2167 /* Configure VLAN stripping. */
2168 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
2169 /* By default, FCS (CRC) is stripped by hardware. */
2170 tmpl->rxq.crc_present = 0;
2171 tmpl->rxq.lro = lro_on_queue;
2172 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
2173 if (config->hw_fcs_strip) {
2175 * RQs used for LRO-enabled TIRs should not be
2176 * configured to scatter the FCS.
2180 "port %u CRC stripping has been "
2181 "disabled but will still be performed "
2182 "by hardware, because LRO is enabled",
2183 dev->data->port_id);
2185 tmpl->rxq.crc_present = 1;
2188 "port %u CRC stripping has been disabled but will"
2189 " still be performed by hardware, make sure MLNX_OFED"
2190 " and firmware are up to date",
2191 dev->data->port_id);
2195 "port %u CRC stripping is %s, %u bytes will be subtracted from"
2196 " incoming frames to hide it",
2198 tmpl->rxq.crc_present ? "disabled" : "enabled",
2199 tmpl->rxq.crc_present << 2);
2201 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
2202 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
2203 tmpl->rxq.port_id = dev->data->port_id;
2206 tmpl->rxq.elts_n = log2above(desc);
2207 tmpl->rxq.rq_repl_thresh =
2208 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
2210 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
2212 tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
2214 tmpl->rxq.idx = idx;
2215 rte_atomic32_inc(&tmpl->refcnt);
2216 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2224 * Create a DPDK Rx hairpin queue.
2227 * Pointer to Ethernet device.
2231 * Number of descriptors to configure in queue.
2232 * @param hairpin_conf
2233 * The hairpin binding configuration.
2236 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2238 struct mlx5_rxq_ctrl *
2239 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2240 const struct rte_eth_hairpin_conf *hairpin_conf)
2242 struct mlx5_priv *priv = dev->data->dev_private;
2243 struct mlx5_rxq_ctrl *tmpl;
2245 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
2251 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2252 tmpl->socket = SOCKET_ID_ANY;
2253 tmpl->rxq.rss_hash = 0;
2254 tmpl->rxq.port_id = dev->data->port_id;
2256 tmpl->rxq.mp = NULL;
2257 tmpl->rxq.elts_n = log2above(desc);
2258 tmpl->rxq.elts = NULL;
2259 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2260 tmpl->hairpin_conf = *hairpin_conf;
2261 tmpl->rxq.idx = idx;
2262 rte_atomic32_inc(&tmpl->refcnt);
2263 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2271 * Pointer to Ethernet device.
2276 * A pointer to the queue if it exists, NULL otherwise.
2278 struct mlx5_rxq_ctrl *
2279 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2281 struct mlx5_priv *priv = dev->data->dev_private;
2282 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2284 if ((*priv->rxqs)[idx]) {
2285 rxq_ctrl = container_of((*priv->rxqs)[idx],
2286 struct mlx5_rxq_ctrl,
2288 mlx5_rxq_obj_get(dev, idx);
2289 rte_atomic32_inc(&rxq_ctrl->refcnt);
2295 * Release a Rx queue.
2298 * Pointer to Ethernet device.
2303 * 1 while a reference on it exists, 0 when freed.
2306 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2308 struct mlx5_priv *priv = dev->data->dev_private;
2309 struct mlx5_rxq_ctrl *rxq_ctrl;
2311 if (!(*priv->rxqs)[idx])
2313 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2314 MLX5_ASSERT(rxq_ctrl->priv);
2315 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2316 rxq_ctrl->obj = NULL;
2317 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2318 if (rxq_ctrl->rq_dbr_umem_id_valid)
2319 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
2320 rxq_ctrl->rq_dbr_umem_id,
2321 rxq_ctrl->rq_dbr_offset));
2322 if (rxq_ctrl->cq_dbr_umem_id_valid)
2323 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
2324 rxq_ctrl->cq_dbr_umem_id,
2325 rxq_ctrl->cq_dbr_offset));
2326 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2327 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2328 LIST_REMOVE(rxq_ctrl, next);
2329 mlx5_free(rxq_ctrl);
2330 (*priv->rxqs)[idx] = NULL;
2337 * Verify the Rx Queue list is empty
2340 * Pointer to Ethernet device.
2343 * The number of object not released.
2346 mlx5_rxq_verify(struct rte_eth_dev *dev)
2348 struct mlx5_priv *priv = dev->data->dev_private;
2349 struct mlx5_rxq_ctrl *rxq_ctrl;
2352 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2353 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2354 dev->data->port_id, rxq_ctrl->rxq.idx);
2361 * Get a Rx queue type.
2364 * Pointer to Ethernet device.
2369 * The Rx queue type.
2372 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2374 struct mlx5_priv *priv = dev->data->dev_private;
2375 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2377 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2378 rxq_ctrl = container_of((*priv->rxqs)[idx],
2379 struct mlx5_rxq_ctrl,
2381 return rxq_ctrl->type;
2383 return MLX5_RXQ_TYPE_UNDEFINED;
2387 * Create an indirection table.
2390 * Pointer to Ethernet device.
2392 * Queues entering in the indirection table.
2394 * Number of queues in the array.
2397 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2399 static struct mlx5_ind_table_obj *
2400 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2401 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2403 struct mlx5_priv *priv = dev->data->dev_private;
2404 struct mlx5_ind_table_obj *ind_tbl;
2405 unsigned int i = 0, j = 0, k = 0;
2407 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) +
2408 queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY);
2413 ind_tbl->type = type;
2414 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2415 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2416 log2above(queues_n) :
2417 log2above(priv->config.ind_table_max_size);
2418 struct ibv_wq *wq[1 << wq_n];
2420 for (i = 0; i != queues_n; ++i) {
2421 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2425 wq[i] = rxq->obj->wq;
2426 ind_tbl->queues[i] = queues[i];
2428 ind_tbl->queues_n = queues_n;
2429 /* Finalise indirection table. */
2430 k = i; /* Retain value of i for use in error case. */
2431 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2433 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2435 &(struct ibv_rwq_ind_table_init_attr){
2436 .log_ind_tbl_size = wq_n,
2440 if (!ind_tbl->ind_table) {
2444 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2445 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2446 const unsigned int rqt_n =
2447 1 << (rte_is_power_of_2(queues_n) ?
2448 log2above(queues_n) :
2449 log2above(priv->config.ind_table_max_size));
2451 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
2452 rqt_n * sizeof(uint32_t), 0,
2455 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2456 dev->data->port_id);
2460 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2461 rqt_attr->rqt_actual_size = rqt_n;
2462 for (i = 0; i != queues_n; ++i) {
2463 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2467 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2468 ind_tbl->queues[i] = queues[i];
2470 k = i; /* Retain value of i for use in error case. */
2471 for (j = 0; k != rqt_n; ++k, ++j)
2472 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2473 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2475 mlx5_free(rqt_attr);
2476 if (!ind_tbl->rqt) {
2477 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2478 dev->data->port_id);
2482 ind_tbl->queues_n = queues_n;
2484 rte_atomic32_inc(&ind_tbl->refcnt);
2485 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2488 for (j = 0; j < i; j++)
2489 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2491 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2496 * Get an indirection table.
2499 * Pointer to Ethernet device.
2501 * Queues entering in the indirection table.
2503 * Number of queues in the array.
2506 * An indirection table if found.
2508 static struct mlx5_ind_table_obj *
2509 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2512 struct mlx5_priv *priv = dev->data->dev_private;
2513 struct mlx5_ind_table_obj *ind_tbl;
2515 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2516 if ((ind_tbl->queues_n == queues_n) &&
2517 (memcmp(ind_tbl->queues, queues,
2518 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2525 rte_atomic32_inc(&ind_tbl->refcnt);
2526 for (i = 0; i != ind_tbl->queues_n; ++i)
2527 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2533 * Release an indirection table.
2536 * Pointer to Ethernet device.
2538 * Indirection table to release.
2541 * 1 while a reference on it exists, 0 when freed.
2544 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2545 struct mlx5_ind_table_obj *ind_tbl)
2549 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2550 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2551 claim_zero(mlx5_glue->destroy_rwq_ind_table
2552 (ind_tbl->ind_table));
2553 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2554 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2556 for (i = 0; i != ind_tbl->queues_n; ++i)
2557 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2558 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2559 LIST_REMOVE(ind_tbl, next);
2567 * Verify the Rx Queue list is empty
2570 * Pointer to Ethernet device.
2573 * The number of object not released.
2576 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2578 struct mlx5_priv *priv = dev->data->dev_private;
2579 struct mlx5_ind_table_obj *ind_tbl;
2582 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2584 "port %u indirection table obj %p still referenced",
2585 dev->data->port_id, (void *)ind_tbl);
2592 * Create an Rx Hash queue.
2595 * Pointer to Ethernet device.
2597 * RSS key for the Rx hash queue.
2598 * @param rss_key_len
2600 * @param hash_fields
2601 * Verbs protocol hash field to make the RSS on.
2603 * Queues entering in hash queue. In case of empty hash_fields only the
2604 * first queue index will be taken for the indirection table.
2611 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
2614 mlx5_hrxq_new(struct rte_eth_dev *dev,
2615 const uint8_t *rss_key, uint32_t rss_key_len,
2616 uint64_t hash_fields,
2617 const uint16_t *queues, uint32_t queues_n,
2618 int tunnel __rte_unused)
2620 struct mlx5_priv *priv = dev->data->dev_private;
2621 struct mlx5_hrxq *hrxq;
2622 uint32_t hrxq_idx = 0;
2623 struct ibv_qp *qp = NULL;
2624 struct mlx5_ind_table_obj *ind_tbl;
2626 struct mlx5_devx_obj *tir = NULL;
2627 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2628 struct mlx5_rxq_ctrl *rxq_ctrl =
2629 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2631 queues_n = hash_fields ? queues_n : 1;
2632 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2634 enum mlx5_ind_tbl_type type;
2636 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2637 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2638 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2644 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2645 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2646 struct mlx5dv_qp_init_attr qp_init_attr;
2648 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2650 qp_init_attr.comp_mask =
2651 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2652 qp_init_attr.create_flags =
2653 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2655 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2656 if (dev->data->dev_conf.lpbk_mode) {
2658 * Allow packet sent from NIC loop back
2659 * w/o source MAC check.
2661 qp_init_attr.comp_mask |=
2662 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2663 qp_init_attr.create_flags |=
2664 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2667 qp = mlx5_glue->dv_create_qp
2669 &(struct ibv_qp_init_attr_ex){
2670 .qp_type = IBV_QPT_RAW_PACKET,
2672 IBV_QP_INIT_ATTR_PD |
2673 IBV_QP_INIT_ATTR_IND_TABLE |
2674 IBV_QP_INIT_ATTR_RX_HASH,
2675 .rx_hash_conf = (struct ibv_rx_hash_conf){
2677 IBV_RX_HASH_FUNC_TOEPLITZ,
2678 .rx_hash_key_len = rss_key_len,
2680 (void *)(uintptr_t)rss_key,
2681 .rx_hash_fields_mask = hash_fields,
2683 .rwq_ind_tbl = ind_tbl->ind_table,
2688 qp = mlx5_glue->create_qp_ex
2690 &(struct ibv_qp_init_attr_ex){
2691 .qp_type = IBV_QPT_RAW_PACKET,
2693 IBV_QP_INIT_ATTR_PD |
2694 IBV_QP_INIT_ATTR_IND_TABLE |
2695 IBV_QP_INIT_ATTR_RX_HASH,
2696 .rx_hash_conf = (struct ibv_rx_hash_conf){
2698 IBV_RX_HASH_FUNC_TOEPLITZ,
2699 .rx_hash_key_len = rss_key_len,
2701 (void *)(uintptr_t)rss_key,
2702 .rx_hash_fields_mask = hash_fields,
2704 .rwq_ind_tbl = ind_tbl->ind_table,
2712 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2713 struct mlx5_devx_tir_attr tir_attr;
2717 /* Enable TIR LRO only if all the queues were configured for. */
2718 for (i = 0; i < queues_n; ++i) {
2719 if (!(*priv->rxqs)[queues[i]]->lro) {
2724 memset(&tir_attr, 0, sizeof(tir_attr));
2725 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2726 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2727 tir_attr.tunneled_offload_en = !!tunnel;
2728 /* If needed, translate hash_fields bitmap to PRM format. */
2730 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2731 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2732 hash_fields & IBV_RX_HASH_INNER ?
2733 &tir_attr.rx_hash_field_selector_inner :
2734 &tir_attr.rx_hash_field_selector_outer;
2736 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2737 &tir_attr.rx_hash_field_selector_outer;
2740 /* 1 bit: 0: IPv4, 1: IPv6. */
2741 rx_hash_field_select->l3_prot_type =
2742 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2743 /* 1 bit: 0: TCP, 1: UDP. */
2744 rx_hash_field_select->l4_prot_type =
2745 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2746 /* Bitmask which sets which fields to use in RX Hash. */
2747 rx_hash_field_select->selected_fields =
2748 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2749 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2750 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2751 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2752 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2753 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2754 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2755 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2757 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2758 tir_attr.transport_domain = priv->sh->td->id;
2760 tir_attr.transport_domain = priv->sh->tdn;
2761 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2762 MLX5_RSS_HASH_KEY_LEN);
2763 tir_attr.indirect_table = ind_tbl->rqt->id;
2764 if (dev->data->dev_conf.lpbk_mode)
2765 tir_attr.self_lb_block =
2766 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2768 tir_attr.lro_timeout_period_usecs =
2769 priv->config.lro.timeout;
2770 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2771 tir_attr.lro_enable_mask =
2772 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2773 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2775 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2777 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2778 dev->data->port_id);
2783 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2786 hrxq->ind_table = ind_tbl;
2787 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2789 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2791 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2792 if (!hrxq->action) {
2797 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2799 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2800 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2802 if (!hrxq->action) {
2808 hrxq->rss_key_len = rss_key_len;
2809 hrxq->hash_fields = hash_fields;
2810 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2811 rte_atomic32_inc(&hrxq->refcnt);
2812 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
2816 err = rte_errno; /* Save rte_errno before cleanup. */
2817 mlx5_ind_table_obj_release(dev, ind_tbl);
2819 claim_zero(mlx5_glue->destroy_qp(qp));
2821 claim_zero(mlx5_devx_cmd_destroy(tir));
2822 rte_errno = err; /* Restore rte_errno. */
2827 * Get an Rx Hash queue.
2830 * Pointer to Ethernet device.
2832 * RSS configuration for the Rx hash queue.
2834 * Queues entering in hash queue. In case of empty hash_fields only the
2835 * first queue index will be taken for the indirection table.
2840 * An hash Rx queue index on success.
2843 mlx5_hrxq_get(struct rte_eth_dev *dev,
2844 const uint8_t *rss_key, uint32_t rss_key_len,
2845 uint64_t hash_fields,
2846 const uint16_t *queues, uint32_t queues_n)
2848 struct mlx5_priv *priv = dev->data->dev_private;
2849 struct mlx5_hrxq *hrxq;
2852 queues_n = hash_fields ? queues_n : 1;
2853 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2855 struct mlx5_ind_table_obj *ind_tbl;
2857 if (hrxq->rss_key_len != rss_key_len)
2859 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2861 if (hrxq->hash_fields != hash_fields)
2863 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2866 if (ind_tbl != hrxq->ind_table) {
2867 mlx5_ind_table_obj_release(dev, ind_tbl);
2870 rte_atomic32_inc(&hrxq->refcnt);
2877 * Release the hash Rx queue.
2880 * Pointer to Ethernet device.
2882 * Index to Hash Rx queue to release.
2885 * 1 while a reference on it exists, 0 when freed.
2888 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2890 struct mlx5_priv *priv = dev->data->dev_private;
2891 struct mlx5_hrxq *hrxq;
2893 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2896 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2897 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2898 mlx5_glue->destroy_flow_action(hrxq->action);
2900 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2901 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2902 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2903 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2904 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2905 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
2906 hrxq_idx, hrxq, next);
2907 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2910 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2915 * Verify the Rx Queue list is empty
2918 * Pointer to Ethernet device.
2921 * The number of object not released.
2924 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2926 struct mlx5_priv *priv = dev->data->dev_private;
2927 struct mlx5_hrxq *hrxq;
2931 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2934 "port %u hash Rx queue %p still referenced",
2935 dev->data->port_id, (void *)hrxq);
2942 * Create a drop Rx queue Verbs/DevX object.
2945 * Pointer to Ethernet device.
2948 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2950 static struct mlx5_rxq_obj *
2951 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2953 struct mlx5_priv *priv = dev->data->dev_private;
2954 struct ibv_context *ctx = priv->sh->ctx;
2956 struct ibv_wq *wq = NULL;
2957 struct mlx5_rxq_obj *rxq;
2959 if (priv->drop_queue.rxq)
2960 return priv->drop_queue.rxq;
2961 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2963 DEBUG("port %u cannot allocate CQ for drop queue",
2964 dev->data->port_id);
2968 wq = mlx5_glue->create_wq(ctx,
2969 &(struct ibv_wq_init_attr){
2970 .wq_type = IBV_WQT_RQ,
2977 DEBUG("port %u cannot allocate WQ for drop queue",
2978 dev->data->port_id);
2982 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
2984 DEBUG("port %u cannot allocate drop Rx queue memory",
2985 dev->data->port_id);
2991 priv->drop_queue.rxq = rxq;
2995 claim_zero(mlx5_glue->destroy_wq(wq));
2997 claim_zero(mlx5_glue->destroy_cq(cq));
3002 * Release a drop Rx queue Verbs/DevX object.
3005 * Pointer to Ethernet device.
3008 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3011 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
3013 struct mlx5_priv *priv = dev->data->dev_private;
3014 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
3017 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
3019 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
3021 priv->drop_queue.rxq = NULL;
3025 * Create a drop indirection table.
3028 * Pointer to Ethernet device.
3031 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3033 static struct mlx5_ind_table_obj *
3034 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
3036 struct mlx5_priv *priv = dev->data->dev_private;
3037 struct mlx5_ind_table_obj *ind_tbl;
3038 struct mlx5_rxq_obj *rxq;
3039 struct mlx5_ind_table_obj tmpl;
3041 rxq = mlx5_rxq_obj_drop_new(dev);
3044 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
3046 &(struct ibv_rwq_ind_table_init_attr){
3047 .log_ind_tbl_size = 0,
3048 .ind_tbl = &rxq->wq,
3051 if (!tmpl.ind_table) {
3052 DEBUG("port %u cannot allocate indirection table for drop"
3054 dev->data->port_id);
3058 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl), 0,
3064 ind_tbl->ind_table = tmpl.ind_table;
3067 mlx5_rxq_obj_drop_release(dev);
3072 * Release a drop indirection table.
3075 * Pointer to Ethernet device.
3078 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
3080 struct mlx5_priv *priv = dev->data->dev_private;
3081 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
3083 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
3084 mlx5_rxq_obj_drop_release(dev);
3086 priv->drop_queue.hrxq->ind_table = NULL;
3090 * Create a drop Rx Hash queue.
3093 * Pointer to Ethernet device.
3096 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3099 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
3101 struct mlx5_priv *priv = dev->data->dev_private;
3102 struct mlx5_ind_table_obj *ind_tbl = NULL;
3103 struct ibv_qp *qp = NULL;
3104 struct mlx5_hrxq *hrxq = NULL;
3106 if (priv->drop_queue.hrxq) {
3107 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
3108 return priv->drop_queue.hrxq;
3110 hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);
3113 "port %u cannot allocate memory for drop queue",
3114 dev->data->port_id);
3118 priv->drop_queue.hrxq = hrxq;
3119 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
3122 hrxq->ind_table = ind_tbl;
3123 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
3124 &(struct ibv_qp_init_attr_ex){
3125 .qp_type = IBV_QPT_RAW_PACKET,
3127 IBV_QP_INIT_ATTR_PD |
3128 IBV_QP_INIT_ATTR_IND_TABLE |
3129 IBV_QP_INIT_ATTR_RX_HASH,
3130 .rx_hash_conf = (struct ibv_rx_hash_conf){
3132 IBV_RX_HASH_FUNC_TOEPLITZ,
3133 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
3134 .rx_hash_key = rss_hash_default_key,
3135 .rx_hash_fields_mask = 0,
3137 .rwq_ind_tbl = ind_tbl->ind_table,
3141 DEBUG("port %u cannot allocate QP for drop queue",
3142 dev->data->port_id);
3147 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3148 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
3149 if (!hrxq->action) {
3154 rte_atomic32_set(&hrxq->refcnt, 1);
3157 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3158 if (hrxq && hrxq->action)
3159 mlx5_glue->destroy_flow_action(hrxq->action);
3162 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3164 mlx5_ind_table_obj_drop_release(dev);
3166 priv->drop_queue.hrxq = NULL;
3173 * Release a drop hash Rx queue.
3176 * Pointer to Ethernet device.
3179 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
3181 struct mlx5_priv *priv = dev->data->dev_private;
3182 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
3184 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
3185 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3186 mlx5_glue->destroy_flow_action(hrxq->action);
3188 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3189 mlx5_ind_table_obj_drop_release(dev);
3191 priv->drop_queue.hrxq = NULL;
3197 * Set the Rx queue timestamp conversion parameters
3200 * Pointer to the Ethernet device structure.
3203 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
3205 struct mlx5_priv *priv = dev->data->dev_private;
3206 struct mlx5_dev_ctx_shared *sh = priv->sh;
3207 struct mlx5_rxq_data *data;
3210 for (i = 0; i != priv->rxqs_n; ++i) {
3211 if (!(*priv->rxqs)[i])
3213 data = (*priv->rxqs)[i];
3215 data->rt_timestamp = priv->config.rt_timestamp;