1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
28 #include <rte_interrupts.h>
29 #include <rte_debug.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
35 #include "mlx5_defs.h"
37 #include "mlx5_rxtx.h"
38 #include "mlx5_utils.h"
39 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
43 /* Default RSS hash key also used for ConnectX-3. */
44 uint8_t rss_hash_default_key[] = {
45 0x2c, 0xc6, 0x81, 0xd1,
46 0x5b, 0xdb, 0xf4, 0xf7,
47 0xfc, 0xa2, 0x83, 0x19,
48 0xdb, 0x1a, 0x3e, 0x94,
49 0x6b, 0x9e, 0x38, 0xd9,
50 0x2c, 0x9c, 0x03, 0xd1,
51 0xad, 0x99, 0x44, 0xa7,
52 0xd9, 0x56, 0x3d, 0x59,
53 0x06, 0x3c, 0x25, 0xf3,
54 0xfc, 0x1f, 0xdc, 0x2a,
57 /* Length of the default RSS hash key. */
58 static_assert(MLX5_RSS_HASH_KEY_LEN ==
59 (unsigned int)sizeof(rss_hash_default_key),
60 "wrong RSS default key size.");
63 * Check whether Multi-Packet RQ can be enabled for the device.
66 * Pointer to Ethernet device.
69 * 1 if supported, negative errno value if not.
72 mlx5_check_mprq_support(struct rte_eth_dev *dev)
74 struct mlx5_priv *priv = dev->data->dev_private;
76 if (priv->config.mprq.enabled &&
77 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
83 * Check whether Multi-Packet RQ is enabled for the Rx queue.
86 * Pointer to receive queue structure.
89 * 0 if disabled, otherwise enabled.
92 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
94 return rxq->strd_num_n > 0;
98 * Check whether Multi-Packet RQ is enabled for the device.
101 * Pointer to Ethernet device.
104 * 0 if disabled, otherwise enabled.
107 mlx5_mprq_enabled(struct rte_eth_dev *dev)
109 struct mlx5_priv *priv = dev->data->dev_private;
114 if (mlx5_check_mprq_support(dev) < 0)
116 /* All the configured queues should be enabled. */
117 for (i = 0; i < priv->rxqs_n; ++i) {
118 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
119 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
120 (rxq, struct mlx5_rxq_ctrl, rxq);
122 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
125 if (mlx5_rxq_mprq_enabled(rxq))
128 /* Multi-Packet RQ can't be partially configured. */
129 MLX5_ASSERT(n == 0 || n == n_ibv);
134 * Allocate RX queue elements for Multi-Packet RQ.
137 * Pointer to RX queue structure.
140 * 0 on success, a negative errno value otherwise and rte_errno is set.
143 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
145 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
146 unsigned int wqe_n = 1 << rxq->elts_n;
150 /* Iterate on segments. */
151 for (i = 0; i <= wqe_n; ++i) {
152 struct mlx5_mprq_buf *buf;
154 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
155 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
160 (*rxq->mprq_bufs)[i] = buf;
162 rxq->mprq_repl = buf;
165 "port %u Rx queue %u allocated and configured %u segments",
166 rxq->port_id, rxq->idx, wqe_n);
169 err = rte_errno; /* Save rte_errno before cleanup. */
171 for (i = 0; (i != wqe_n); ++i) {
172 if ((*rxq->mprq_bufs)[i] != NULL)
173 rte_mempool_put(rxq->mprq_mp,
174 (*rxq->mprq_bufs)[i]);
175 (*rxq->mprq_bufs)[i] = NULL;
177 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
178 rxq->port_id, rxq->idx);
179 rte_errno = err; /* Restore rte_errno. */
184 * Allocate RX queue elements for Single-Packet RQ.
187 * Pointer to RX queue structure.
190 * 0 on success, errno value on failure.
193 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
195 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
196 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
200 /* Iterate on segments. */
201 for (i = 0; (i != elts_n); ++i) {
202 struct rte_mbuf *buf;
204 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
206 DRV_LOG(ERR, "port %u empty mbuf pool",
207 PORT_ID(rxq_ctrl->priv));
211 /* Headroom is reserved by rte_pktmbuf_alloc(). */
212 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
213 /* Buffer is supposed to be empty. */
214 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
215 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
216 MLX5_ASSERT(!buf->next);
217 /* Only the first segment keeps headroom. */
219 SET_DATA_OFF(buf, 0);
220 PORT(buf) = rxq_ctrl->rxq.port_id;
221 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
222 PKT_LEN(buf) = DATA_LEN(buf);
224 (*rxq_ctrl->rxq.elts)[i] = buf;
226 /* If Rx vector is activated. */
227 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
228 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
229 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
230 struct rte_pktmbuf_pool_private *priv =
231 (struct rte_pktmbuf_pool_private *)
232 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
235 /* Initialize default rearm_data for vPMD. */
236 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
237 rte_mbuf_refcnt_set(mbuf_init, 1);
238 mbuf_init->nb_segs = 1;
239 mbuf_init->port = rxq->port_id;
240 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
241 mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
243 * prevent compiler reordering:
244 * rearm_data covers previous fields.
246 rte_compiler_barrier();
247 rxq->mbuf_initializer =
248 *(rte_xmm_t *)&mbuf_init->rearm_data;
249 /* Padding with a fake mbuf for vectorized Rx. */
250 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
251 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
254 "port %u Rx queue %u allocated and configured %u segments"
256 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
257 elts_n / (1 << rxq_ctrl->rxq.sges_n));
260 err = rte_errno; /* Save rte_errno before cleanup. */
262 for (i = 0; (i != elts_n); ++i) {
263 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
264 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
265 (*rxq_ctrl->rxq.elts)[i] = NULL;
267 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
268 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
269 rte_errno = err; /* Restore rte_errno. */
274 * Allocate RX queue elements.
277 * Pointer to RX queue structure.
280 * 0 on success, errno value on failure.
283 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
285 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
286 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
290 * Free RX queue elements for Multi-Packet RQ.
293 * Pointer to RX queue structure.
296 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
298 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
301 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
302 rxq->port_id, rxq->idx);
303 if (rxq->mprq_bufs == NULL)
305 MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
306 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
307 if ((*rxq->mprq_bufs)[i] != NULL)
308 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
309 (*rxq->mprq_bufs)[i] = NULL;
311 if (rxq->mprq_repl != NULL) {
312 mlx5_mprq_buf_free(rxq->mprq_repl);
313 rxq->mprq_repl = NULL;
318 * Free RX queue elements for Single-Packet RQ.
321 * Pointer to RX queue structure.
324 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
326 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
327 const uint16_t q_n = (1 << rxq->elts_n);
328 const uint16_t q_mask = q_n - 1;
329 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
332 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
333 PORT_ID(rxq_ctrl->priv), rxq->idx);
334 if (rxq->elts == NULL)
337 * Some mbuf in the Ring belongs to the application. They cannot be
340 if (mlx5_rxq_check_vec_support(rxq) > 0) {
341 for (i = 0; i < used; ++i)
342 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
343 rxq->rq_pi = rxq->rq_ci;
345 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
346 if ((*rxq->elts)[i] != NULL)
347 rte_pktmbuf_free_seg((*rxq->elts)[i]);
348 (*rxq->elts)[i] = NULL;
353 * Free RX queue elements.
356 * Pointer to RX queue structure.
359 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
361 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
362 rxq_free_elts_mprq(rxq_ctrl);
364 rxq_free_elts_sprq(rxq_ctrl);
368 * Returns the per-queue supported offloads.
371 * Pointer to Ethernet device.
374 * Supported Rx offloads.
377 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
379 struct mlx5_priv *priv = dev->data->dev_private;
380 struct mlx5_dev_config *config = &priv->config;
381 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
382 DEV_RX_OFFLOAD_TIMESTAMP |
383 DEV_RX_OFFLOAD_JUMBO_FRAME |
384 DEV_RX_OFFLOAD_RSS_HASH);
386 if (config->hw_fcs_strip)
387 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
390 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
391 DEV_RX_OFFLOAD_UDP_CKSUM |
392 DEV_RX_OFFLOAD_TCP_CKSUM);
393 if (config->hw_vlan_strip)
394 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
395 if (MLX5_LRO_SUPPORTED(dev))
396 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
402 * Returns the per-port supported offloads.
405 * Supported Rx offloads.
408 mlx5_get_rx_port_offloads(void)
410 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
416 * Verify if the queue can be released.
419 * Pointer to Ethernet device.
424 * 1 if the queue can be released
425 * 0 if the queue can not be released, there are references to it.
426 * Negative errno and rte_errno is set if queue doesn't exist.
429 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
431 struct mlx5_priv *priv = dev->data->dev_private;
432 struct mlx5_rxq_ctrl *rxq_ctrl;
434 if (!(*priv->rxqs)[idx]) {
438 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
439 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
443 * Rx queue presetup checks.
446 * Pointer to Ethernet device structure.
450 * Number of descriptors to configure in queue.
453 * 0 on success, a negative errno value otherwise and rte_errno is set.
456 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
458 struct mlx5_priv *priv = dev->data->dev_private;
460 if (!rte_is_power_of_2(desc)) {
461 desc = 1 << log2above(desc);
463 "port %u increased number of descriptors in Rx queue %u"
464 " to the next power of two (%d)",
465 dev->data->port_id, idx, desc);
467 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
468 dev->data->port_id, idx, desc);
469 if (idx >= priv->rxqs_n) {
470 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
471 dev->data->port_id, idx, priv->rxqs_n);
472 rte_errno = EOVERFLOW;
475 if (!mlx5_rxq_releasable(dev, idx)) {
476 DRV_LOG(ERR, "port %u unable to release queue index %u",
477 dev->data->port_id, idx);
481 mlx5_rxq_release(dev, idx);
488 * Pointer to Ethernet device structure.
492 * Number of descriptors to configure in queue.
494 * NUMA socket on which memory must be allocated.
496 * Thresholds parameters.
498 * Memory pool for buffer allocations.
501 * 0 on success, a negative errno value otherwise and rte_errno is set.
504 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
505 unsigned int socket, const struct rte_eth_rxconf *conf,
506 struct rte_mempool *mp)
508 struct mlx5_priv *priv = dev->data->dev_private;
509 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
510 struct mlx5_rxq_ctrl *rxq_ctrl =
511 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
514 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
517 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
519 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
520 dev->data->port_id, idx);
524 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
525 dev->data->port_id, idx);
526 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
533 * Pointer to Ethernet device structure.
537 * Number of descriptors to configure in queue.
538 * @param hairpin_conf
539 * Hairpin configuration parameters.
542 * 0 on success, a negative errno value otherwise and rte_errno is set.
545 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
547 const struct rte_eth_hairpin_conf *hairpin_conf)
549 struct mlx5_priv *priv = dev->data->dev_private;
550 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
551 struct mlx5_rxq_ctrl *rxq_ctrl =
552 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
555 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
558 if (hairpin_conf->peer_count != 1 ||
559 hairpin_conf->peers[0].port != dev->data->port_id ||
560 hairpin_conf->peers[0].queue >= priv->txqs_n) {
561 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
562 " invalid hairpind configuration", dev->data->port_id,
567 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
569 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
570 dev->data->port_id, idx);
574 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
575 dev->data->port_id, idx);
576 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
581 * DPDK callback to release a RX queue.
584 * Generic RX queue pointer.
587 mlx5_rx_queue_release(void *dpdk_rxq)
589 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
590 struct mlx5_rxq_ctrl *rxq_ctrl;
591 struct mlx5_priv *priv;
595 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
596 priv = rxq_ctrl->priv;
597 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
598 rte_panic("port %u Rx queue %u is still used by a flow and"
599 " cannot be removed\n",
600 PORT_ID(priv), rxq->idx);
601 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
605 * Get an Rx queue Verbs/DevX object.
608 * Pointer to Ethernet device.
610 * Queue index in DPDK Rx queue array
613 * The Verbs/DevX object if it exists.
615 static struct mlx5_rxq_obj *
616 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
618 struct mlx5_priv *priv = dev->data->dev_private;
619 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
620 struct mlx5_rxq_ctrl *rxq_ctrl;
622 if (idx >= priv->rxqs_n)
626 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
628 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
629 return rxq_ctrl->obj;
633 * Release the resources allocated for an RQ DevX object.
636 * DevX Rx queue object.
639 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
641 if (rxq_ctrl->rxq.wqes) {
642 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
643 rxq_ctrl->rxq.wqes = NULL;
645 if (rxq_ctrl->wq_umem) {
646 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
647 rxq_ctrl->wq_umem = NULL;
652 * Release an Rx hairpin related resources.
655 * Hairpin Rx queue object.
658 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
660 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
662 MLX5_ASSERT(rxq_obj);
663 rq_attr.state = MLX5_RQC_STATE_RST;
664 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
665 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
666 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
670 * Release an Rx verbs/DevX queue object.
673 * Verbs/DevX Rx queue object.
676 * 1 while a reference on it exists, 0 when freed.
679 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
681 MLX5_ASSERT(rxq_obj);
682 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
683 switch (rxq_obj->type) {
684 case MLX5_RXQ_OBJ_TYPE_IBV:
685 MLX5_ASSERT(rxq_obj->wq);
686 MLX5_ASSERT(rxq_obj->cq);
687 rxq_free_elts(rxq_obj->rxq_ctrl);
688 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
689 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
691 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
692 MLX5_ASSERT(rxq_obj->cq);
693 MLX5_ASSERT(rxq_obj->rq);
694 rxq_free_elts(rxq_obj->rxq_ctrl);
695 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
696 rxq_release_rq_resources(rxq_obj->rxq_ctrl);
697 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
699 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
700 MLX5_ASSERT(rxq_obj->rq);
701 rxq_obj_hairpin_release(rxq_obj);
704 if (rxq_obj->channel)
705 claim_zero(mlx5_glue->destroy_comp_channel
707 LIST_REMOVE(rxq_obj, next);
715 * Allocate queue vector and fill epoll fd list for Rx interrupts.
718 * Pointer to Ethernet device.
721 * 0 on success, a negative errno value otherwise and rte_errno is set.
724 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
726 struct mlx5_priv *priv = dev->data->dev_private;
728 unsigned int rxqs_n = priv->rxqs_n;
729 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
730 unsigned int count = 0;
731 struct rte_intr_handle *intr_handle = dev->intr_handle;
733 if (!dev->data->dev_conf.intr_conf.rxq)
735 mlx5_rx_intr_vec_disable(dev);
736 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
737 if (intr_handle->intr_vec == NULL) {
739 "port %u failed to allocate memory for interrupt"
740 " vector, Rx interrupts will not be supported",
745 intr_handle->type = RTE_INTR_HANDLE_EXT;
746 for (i = 0; i != n; ++i) {
747 /* This rxq obj must not be released in this function. */
748 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
753 /* Skip queues that cannot request interrupts. */
754 if (!rxq_obj || !rxq_obj->channel) {
755 /* Use invalid intr_vec[] index to disable entry. */
756 intr_handle->intr_vec[i] =
757 RTE_INTR_VEC_RXTX_OFFSET +
758 RTE_MAX_RXTX_INTR_VEC_ID;
761 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
763 "port %u too many Rx queues for interrupt"
764 " vector size (%d), Rx interrupts cannot be"
766 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
767 mlx5_rx_intr_vec_disable(dev);
771 fd = rxq_obj->channel->fd;
772 flags = fcntl(fd, F_GETFL);
773 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
777 "port %u failed to make Rx interrupt file"
778 " descriptor %d non-blocking for queue index"
780 dev->data->port_id, fd, i);
781 mlx5_rx_intr_vec_disable(dev);
784 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
785 intr_handle->efds[count] = fd;
789 mlx5_rx_intr_vec_disable(dev);
791 intr_handle->nb_efd = count;
796 * Clean up Rx interrupts handler.
799 * Pointer to Ethernet device.
802 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
804 struct mlx5_priv *priv = dev->data->dev_private;
805 struct rte_intr_handle *intr_handle = dev->intr_handle;
807 unsigned int rxqs_n = priv->rxqs_n;
808 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
810 if (!dev->data->dev_conf.intr_conf.rxq)
812 if (!intr_handle->intr_vec)
814 for (i = 0; i != n; ++i) {
815 struct mlx5_rxq_ctrl *rxq_ctrl;
816 struct mlx5_rxq_data *rxq_data;
818 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
819 RTE_MAX_RXTX_INTR_VEC_ID)
822 * Need to access directly the queue to release the reference
823 * kept in mlx5_rx_intr_vec_enable().
825 rxq_data = (*priv->rxqs)[i];
826 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
828 mlx5_rxq_obj_release(rxq_ctrl->obj);
831 rte_intr_free_epoll_fd(intr_handle);
832 if (intr_handle->intr_vec)
833 free(intr_handle->intr_vec);
834 intr_handle->nb_efd = 0;
835 intr_handle->intr_vec = NULL;
839 * MLX5 CQ notification .
842 * Pointer to receive queue structure.
844 * Sequence number per receive queue .
847 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
850 uint32_t doorbell_hi;
852 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
854 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
855 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
856 doorbell = (uint64_t)doorbell_hi << 32;
857 doorbell |= rxq->cqn;
858 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
859 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
860 cq_db_reg, rxq->uar_lock_cq);
864 * DPDK callback for Rx queue interrupt enable.
867 * Pointer to Ethernet device structure.
872 * 0 on success, a negative errno value otherwise and rte_errno is set.
875 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
877 struct mlx5_priv *priv = dev->data->dev_private;
878 struct mlx5_rxq_data *rxq_data;
879 struct mlx5_rxq_ctrl *rxq_ctrl;
881 rxq_data = (*priv->rxqs)[rx_queue_id];
886 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
888 struct mlx5_rxq_obj *rxq_obj;
890 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
895 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
896 mlx5_rxq_obj_release(rxq_obj);
902 * DPDK callback for Rx queue interrupt disable.
905 * Pointer to Ethernet device structure.
910 * 0 on success, a negative errno value otherwise and rte_errno is set.
913 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
915 struct mlx5_priv *priv = dev->data->dev_private;
916 struct mlx5_rxq_data *rxq_data;
917 struct mlx5_rxq_ctrl *rxq_ctrl;
918 struct mlx5_rxq_obj *rxq_obj = NULL;
919 struct ibv_cq *ev_cq;
923 rxq_data = (*priv->rxqs)[rx_queue_id];
928 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
931 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
936 ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
937 if (ret || ev_cq != rxq_obj->cq) {
941 rxq_data->cq_arm_sn++;
942 mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
943 mlx5_rxq_obj_release(rxq_obj);
946 ret = rte_errno; /* Save rte_errno before cleanup. */
948 mlx5_rxq_obj_release(rxq_obj);
949 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
950 dev->data->port_id, rx_queue_id);
951 rte_errno = ret; /* Restore rte_errno. */
956 * Create a CQ Verbs object.
959 * Pointer to Ethernet device.
961 * Pointer to device private data.
963 * Pointer to Rx queue data.
965 * Number of CQEs in CQ.
967 * Pointer to Rx queue object data.
970 * The Verbs object initialised, NULL otherwise and rte_errno is set.
972 static struct ibv_cq *
973 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
974 struct mlx5_rxq_data *rxq_data,
975 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
978 struct ibv_cq_init_attr_ex ibv;
979 struct mlx5dv_cq_init_attr mlx5;
982 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
984 .channel = rxq_obj->channel,
987 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
990 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
992 cq_attr.mlx5.comp_mask |=
993 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
994 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
995 cq_attr.mlx5.cqe_comp_res_format =
996 mlx5_rxq_mprq_enabled(rxq_data) ?
997 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
998 MLX5DV_CQE_RES_FORMAT_HASH;
1000 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1003 * For vectorized Rx, it must not be doubled in order to
1004 * make cq_ci and rq_ci aligned.
1006 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1007 cq_attr.ibv.cqe *= 2;
1008 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1010 "port %u Rx CQE compression is disabled for HW"
1012 dev->data->port_id);
1013 } else if (priv->config.cqe_comp && rxq_data->lro) {
1015 "port %u Rx CQE compression is disabled for LRO",
1016 dev->data->port_id);
1018 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1019 if (priv->config.cqe_pad) {
1020 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1021 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1024 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1030 * Create a WQ Verbs object.
1033 * Pointer to Ethernet device.
1035 * Pointer to device private data.
1037 * Pointer to Rx queue data.
1039 * Queue index in DPDK Rx queue array
1041 * Number of WQEs in WQ.
1043 * Pointer to Rx queue object data.
1046 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1048 static struct ibv_wq *
1049 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1050 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1051 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1054 struct ibv_wq_init_attr ibv;
1055 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1056 struct mlx5dv_wq_init_attr mlx5;
1060 wq_attr.ibv = (struct ibv_wq_init_attr){
1061 .wq_context = NULL, /* Could be useful in the future. */
1062 .wq_type = IBV_WQT_RQ,
1063 /* Max number of outstanding WRs. */
1064 .max_wr = wqe_n >> rxq_data->sges_n,
1065 /* Max number of scatter/gather elements in a WR. */
1066 .max_sge = 1 << rxq_data->sges_n,
1069 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1070 .create_flags = (rxq_data->vlan_strip ?
1071 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1073 /* By default, FCS (CRC) is stripped by hardware. */
1074 if (rxq_data->crc_present) {
1075 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1076 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1078 if (priv->config.hw_padding) {
1079 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1080 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1081 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1082 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1083 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1084 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1087 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1088 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1091 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1092 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1093 &wq_attr.mlx5.striding_rq_attrs;
1095 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1096 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1097 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1098 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1099 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1102 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1105 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1109 * Make sure number of WRs*SGEs match expectations since a queue
1110 * cannot allocate more than "desc" buffers.
1112 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1113 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1115 "port %u Rx queue %u requested %u*%u but got"
1117 dev->data->port_id, idx,
1118 wqe_n >> rxq_data->sges_n,
1119 (1 << rxq_data->sges_n),
1120 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1121 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1130 * Fill common fields of create RQ attributes structure.
1133 * Pointer to Rx queue data.
1135 * CQ number to use with this RQ.
1137 * RQ attributes structure to fill..
1140 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1141 struct mlx5_devx_create_rq_attr *rq_attr)
1143 rq_attr->state = MLX5_RQC_STATE_RST;
1144 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1146 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1150 * Fill common fields of DevX WQ attributes structure.
1153 * Pointer to device private data.
1155 * Pointer to Rx queue control structure.
1157 * WQ attributes structure to fill..
1160 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1161 struct mlx5_devx_wq_attr *wq_attr)
1163 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1164 MLX5_WQ_END_PAD_MODE_ALIGN :
1165 MLX5_WQ_END_PAD_MODE_NONE;
1166 wq_attr->pd = priv->sh->pdn;
1167 wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1168 wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1169 wq_attr->dbr_umem_valid = 1;
1170 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1171 wq_attr->wq_umem_valid = 1;
1175 * Create a RQ object using DevX.
1178 * Pointer to Ethernet device.
1180 * Queue index in DPDK Rx queue array
1182 * CQ number to use with this RQ.
1185 * The DevX object initialised, NULL otherwise and rte_errno is set.
1187 static struct mlx5_devx_obj *
1188 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1190 struct mlx5_priv *priv = dev->data->dev_private;
1191 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1192 struct mlx5_rxq_ctrl *rxq_ctrl =
1193 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1194 struct mlx5_devx_create_rq_attr rq_attr;
1195 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1196 uint32_t wq_size = 0;
1197 uint32_t wqe_size = 0;
1198 uint32_t log_wqe_size = 0;
1200 struct mlx5_devx_obj *rq;
1202 memset(&rq_attr, 0, sizeof(rq_attr));
1203 /* Fill RQ attributes. */
1204 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1205 rq_attr.flush_in_error_en = 1;
1206 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1207 /* Fill WQ attributes for this RQ. */
1208 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1209 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1211 * Number of strides in each WQE:
1212 * 512*2^single_wqe_log_num_of_strides.
1214 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1215 rxq_data->strd_num_n -
1216 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1217 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1218 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1219 rxq_data->strd_sz_n -
1220 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1221 wqe_size = sizeof(struct mlx5_wqe_mprq);
1223 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1224 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1226 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1227 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1228 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1229 /* Calculate and allocate WQ memory space. */
1230 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1231 wq_size = wqe_n * wqe_size;
1232 buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1236 rxq_data->wqes = buf;
1237 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1239 if (!rxq_ctrl->wq_umem) {
1243 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1244 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1246 rxq_release_rq_resources(rxq_ctrl);
1251 * Create the Rx hairpin queue object.
1254 * Pointer to Ethernet device.
1256 * Queue index in DPDK Rx queue array
1259 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1261 static struct mlx5_rxq_obj *
1262 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1264 struct mlx5_priv *priv = dev->data->dev_private;
1265 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1266 struct mlx5_rxq_ctrl *rxq_ctrl =
1267 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1268 struct mlx5_devx_create_rq_attr attr = { 0 };
1269 struct mlx5_rxq_obj *tmpl = NULL;
1270 uint32_t max_wq_data;
1272 MLX5_ASSERT(rxq_data);
1273 MLX5_ASSERT(!rxq_ctrl->obj);
1274 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1278 "port %u Rx queue %u cannot allocate verbs resources",
1279 dev->data->port_id, rxq_data->idx);
1283 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1284 tmpl->rxq_ctrl = rxq_ctrl;
1286 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1287 /* Jumbo frames > 9KB should be supported, and more packets. */
1288 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1289 if (priv->config.log_hp_size > max_wq_data) {
1290 DRV_LOG(ERR, "total data size %u power of 2 is "
1291 "too large for hairpin",
1292 priv->config.log_hp_size);
1297 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1299 attr.wq_attr.log_hairpin_data_sz =
1300 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1301 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1303 /* Set the packets number to the maximum value for performance. */
1304 attr.wq_attr.log_hairpin_num_packets =
1305 attr.wq_attr.log_hairpin_data_sz -
1306 MLX5_HAIRPIN_QUEUE_STRIDE;
1307 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1311 "port %u Rx hairpin queue %u can't create rq object",
1312 dev->data->port_id, idx);
1317 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1318 idx, (void *)&tmpl);
1319 rte_atomic32_inc(&tmpl->refcnt);
1320 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1321 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1326 * Create the Rx queue Verbs/DevX object.
1329 * Pointer to Ethernet device.
1331 * Queue index in DPDK Rx queue array
1333 * Type of Rx queue object to create.
1336 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1338 struct mlx5_rxq_obj *
1339 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1340 enum mlx5_rxq_obj_type type)
1342 struct mlx5_priv *priv = dev->data->dev_private;
1343 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1344 struct mlx5_rxq_ctrl *rxq_ctrl =
1345 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1346 struct ibv_wq_attr mod;
1348 unsigned int wqe_n = 1 << rxq_data->elts_n;
1349 struct mlx5_rxq_obj *tmpl = NULL;
1350 struct mlx5dv_cq cq_info;
1351 struct mlx5dv_rwq rwq;
1353 struct mlx5dv_obj obj;
1355 MLX5_ASSERT(rxq_data);
1356 MLX5_ASSERT(!rxq_ctrl->obj);
1357 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1358 return mlx5_rxq_obj_hairpin_new(dev, idx);
1359 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1360 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1361 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1365 "port %u Rx queue %u cannot allocate verbs resources",
1366 dev->data->port_id, rxq_data->idx);
1371 tmpl->rxq_ctrl = rxq_ctrl;
1372 if (rxq_ctrl->irq) {
1373 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1374 if (!tmpl->channel) {
1375 DRV_LOG(ERR, "port %u: comp channel creation failure",
1376 dev->data->port_id);
1381 if (mlx5_rxq_mprq_enabled(rxq_data))
1382 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1385 tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1387 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1388 dev->data->port_id, idx);
1392 obj.cq.in = tmpl->cq;
1393 obj.cq.out = &cq_info;
1394 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1399 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1401 "port %u wrong MLX5_CQE_SIZE environment variable"
1402 " value: it should be set to %u",
1403 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1407 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1408 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
1409 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1410 dev->data->port_id, priv->sh->device_attr.max_sge);
1411 /* Allocate door-bell for types created with DevX. */
1412 if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1413 struct mlx5_devx_dbr_page *dbr_page;
1416 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1419 rxq_ctrl->dbr_offset = dbr_offset;
1420 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1421 rxq_ctrl->dbr_umem_id_valid = 1;
1422 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1423 (uintptr_t)rxq_ctrl->dbr_offset);
1425 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1426 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1429 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1430 dev->data->port_id, idx);
1434 /* Change queue state to ready. */
1435 mod = (struct ibv_wq_attr){
1436 .attr_mask = IBV_WQ_ATTR_STATE,
1437 .wq_state = IBV_WQS_RDY,
1439 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1442 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1443 " failed", dev->data->port_id, idx);
1447 obj.rwq.in = tmpl->wq;
1449 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1454 rxq_data->wqes = rwq.buf;
1455 rxq_data->rq_db = rwq.dbrec;
1456 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1457 struct mlx5_devx_modify_rq_attr rq_attr;
1459 memset(&rq_attr, 0, sizeof(rq_attr));
1460 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1462 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1463 dev->data->port_id, idx);
1467 /* Change queue state to ready. */
1468 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1469 rq_attr.state = MLX5_RQC_STATE_RDY;
1470 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1474 /* Fill the rings. */
1475 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1476 rxq_data->cq_db = cq_info.dbrec;
1477 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1478 rxq_data->cq_uar = cq_info.cq_uar;
1479 rxq_data->cqn = cq_info.cqn;
1480 rxq_data->cq_arm_sn = 0;
1481 mlx5_rxq_initialize(rxq_data);
1482 rxq_data->cq_ci = 0;
1483 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1484 idx, (void *)&tmpl);
1485 rte_atomic32_inc(&tmpl->refcnt);
1486 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1487 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1491 ret = rte_errno; /* Save rte_errno before cleanup. */
1492 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1493 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1494 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1495 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1497 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1499 claim_zero(mlx5_glue->destroy_comp_channel
1502 rte_errno = ret; /* Restore rte_errno. */
1504 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1505 rxq_release_rq_resources(rxq_ctrl);
1506 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1511 * Verify the Rx queue objects list is empty
1514 * Pointer to Ethernet device.
1517 * The number of objects not released.
1520 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1522 struct mlx5_priv *priv = dev->data->dev_private;
1524 struct mlx5_rxq_obj *rxq_obj;
1526 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1527 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1528 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1535 * Callback function to initialize mbufs for Multi-Packet RQ.
1538 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1539 void *_m, unsigned int i __rte_unused)
1541 struct mlx5_mprq_buf *buf = _m;
1542 struct rte_mbuf_ext_shared_info *shinfo;
1543 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1546 memset(_m, 0, sizeof(*buf));
1548 rte_atomic16_set(&buf->refcnt, 1);
1549 for (j = 0; j != strd_n; ++j) {
1550 shinfo = &buf->shinfos[j];
1551 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1552 shinfo->fcb_opaque = buf;
1557 * Free mempool of Multi-Packet RQ.
1560 * Pointer to Ethernet device.
1563 * 0 on success, negative errno value on failure.
1566 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1568 struct mlx5_priv *priv = dev->data->dev_private;
1569 struct rte_mempool *mp = priv->mprq_mp;
1574 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1575 dev->data->port_id, mp->name);
1577 * If a buffer in the pool has been externally attached to a mbuf and it
1578 * is still in use by application, destroying the Rx queue can spoil
1579 * the packet. It is unlikely to happen but if application dynamically
1580 * creates and destroys with holding Rx packets, this can happen.
1582 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1583 * RQ isn't provided by application but managed by PMD.
1585 if (!rte_mempool_full(mp)) {
1587 "port %u mempool for Multi-Packet RQ is still in use",
1588 dev->data->port_id);
1592 rte_mempool_free(mp);
1593 /* Unset mempool for each Rx queue. */
1594 for (i = 0; i != priv->rxqs_n; ++i) {
1595 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1599 rxq->mprq_mp = NULL;
1601 priv->mprq_mp = NULL;
1606 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1607 * mempool. If already allocated, reuse it if there're enough elements.
1608 * Otherwise, resize it.
1611 * Pointer to Ethernet device.
1614 * 0 on success, negative errno value on failure.
1617 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1619 struct mlx5_priv *priv = dev->data->dev_private;
1620 struct rte_mempool *mp = priv->mprq_mp;
1621 char name[RTE_MEMPOOL_NAMESIZE];
1622 unsigned int desc = 0;
1623 unsigned int buf_len;
1624 unsigned int obj_num;
1625 unsigned int obj_size;
1626 unsigned int strd_num_n = 0;
1627 unsigned int strd_sz_n = 0;
1629 unsigned int n_ibv = 0;
1631 if (!mlx5_mprq_enabled(dev))
1633 /* Count the total number of descriptors configured. */
1634 for (i = 0; i != priv->rxqs_n; ++i) {
1635 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1636 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1637 (rxq, struct mlx5_rxq_ctrl, rxq);
1639 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1642 desc += 1 << rxq->elts_n;
1643 /* Get the max number of strides. */
1644 if (strd_num_n < rxq->strd_num_n)
1645 strd_num_n = rxq->strd_num_n;
1646 /* Get the max size of a stride. */
1647 if (strd_sz_n < rxq->strd_sz_n)
1648 strd_sz_n = rxq->strd_sz_n;
1650 MLX5_ASSERT(strd_num_n && strd_sz_n);
1651 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1652 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1653 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1655 * Received packets can be either memcpy'd or externally referenced. In
1656 * case that the packet is attached to an mbuf as an external buffer, as
1657 * it isn't possible to predict how the buffers will be queued by
1658 * application, there's no option to exactly pre-allocate needed buffers
1659 * in advance but to speculatively prepares enough buffers.
1661 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1662 * received packets to buffers provided by application (rxq->mp) until
1663 * this Mempool gets available again.
1666 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1668 * rte_mempool_create_empty() has sanity check to refuse large cache
1669 * size compared to the number of elements.
1670 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1671 * constant number 2 instead.
1673 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1674 /* Check a mempool is already allocated and if it can be resued. */
1675 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1676 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1677 dev->data->port_id, mp->name);
1680 } else if (mp != NULL) {
1681 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1682 dev->data->port_id, mp->name);
1684 * If failed to free, which means it may be still in use, no way
1685 * but to keep using the existing one. On buffer underrun,
1686 * packets will be memcpy'd instead of external buffer
1689 if (mlx5_mprq_free_mp(dev)) {
1690 if (mp->elt_size >= obj_size)
1696 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1697 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1698 0, NULL, NULL, mlx5_mprq_buf_init,
1699 (void *)(uintptr_t)(1 << strd_num_n),
1700 dev->device->numa_node, 0);
1703 "port %u failed to allocate a mempool for"
1704 " Multi-Packet RQ, count=%u, size=%u",
1705 dev->data->port_id, obj_num, obj_size);
1711 /* Set mempool for each Rx queue. */
1712 for (i = 0; i != priv->rxqs_n; ++i) {
1713 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1714 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1715 (rxq, struct mlx5_rxq_ctrl, rxq);
1717 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1721 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1722 dev->data->port_id);
1726 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1727 sizeof(struct rte_vlan_hdr) * 2 + \
1728 sizeof(struct rte_ipv6_hdr)))
1729 #define MAX_TCP_OPTION_SIZE 40u
1730 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1731 sizeof(struct rte_tcp_hdr) + \
1732 MAX_TCP_OPTION_SIZE))
1735 * Adjust the maximum LRO massage size.
1738 * Pointer to Ethernet device.
1741 * @param max_lro_size
1742 * The maximum size for LRO packet.
1745 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1746 uint32_t max_lro_size)
1748 struct mlx5_priv *priv = dev->data->dev_private;
1750 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1751 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1752 MLX5_MAX_TCP_HDR_OFFSET)
1753 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1754 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1755 MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1756 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1757 if (priv->max_lro_msg_size)
1758 priv->max_lro_msg_size =
1759 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1761 priv->max_lro_msg_size = max_lro_size;
1763 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1764 dev->data->port_id, idx,
1765 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1769 * Create a DPDK Rx queue.
1772 * Pointer to Ethernet device.
1776 * Number of descriptors to configure in queue.
1778 * NUMA socket on which memory must be allocated.
1781 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1783 struct mlx5_rxq_ctrl *
1784 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1785 unsigned int socket, const struct rte_eth_rxconf *conf,
1786 struct rte_mempool *mp)
1788 struct mlx5_priv *priv = dev->data->dev_private;
1789 struct mlx5_rxq_ctrl *tmpl;
1790 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1791 unsigned int mprq_stride_nums;
1792 unsigned int mprq_stride_size;
1793 unsigned int mprq_stride_cap;
1794 struct mlx5_dev_config *config = &priv->config;
1796 * Always allocate extra slots, even if eventually
1797 * the vector Rx will not be used.
1800 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1801 uint64_t offloads = conf->offloads |
1802 dev->data->dev_conf.rxmode.offloads;
1803 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1804 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1805 unsigned int max_rx_pkt_len = lro_on_queue ?
1806 dev->data->dev_conf.rxmode.max_lro_pkt_size :
1807 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1808 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1809 RTE_PKTMBUF_HEADROOM;
1810 unsigned int max_lro_size = 0;
1811 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1813 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1814 DEV_RX_OFFLOAD_SCATTER)) {
1815 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1816 " configured and no enough mbuf space(%u) to contain "
1817 "the maximum RX packet length(%u) with head-room(%u)",
1818 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1819 RTE_PKTMBUF_HEADROOM);
1823 tmpl = rte_calloc_socket("RXQ", 1,
1825 desc_n * sizeof(struct rte_mbuf *),
1831 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1832 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1833 MLX5_MR_BTREE_CACHE_N, socket)) {
1834 /* rte_errno is already set. */
1837 tmpl->socket = socket;
1838 if (dev->data->dev_conf.intr_conf.rxq)
1840 mprq_stride_nums = config->mprq.stride_num_n ?
1841 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
1842 mprq_stride_size = non_scatter_min_mbuf_size <=
1843 (1U << config->mprq.max_stride_size_n) ?
1844 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
1845 mprq_stride_cap = (config->mprq.stride_num_n ?
1846 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
1847 (config->mprq.stride_size_n ?
1848 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
1850 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1851 * following conditions are met:
1852 * - MPRQ is enabled.
1853 * - The number of descs is more than the number of strides.
1854 * - max_rx_pkt_len plus overhead is less than the max size
1855 * of a stride or mprq_stride_size is specified by a user.
1856 * Need to nake sure that there are enough stides to encap
1857 * the maximum packet size in case mprq_stride_size is set.
1858 * Otherwise, enable Rx scatter if necessary.
1860 if (mprq_en && desc > (1U << mprq_stride_nums) &&
1861 (non_scatter_min_mbuf_size <=
1862 (1U << config->mprq.max_stride_size_n) ||
1863 (config->mprq.stride_size_n &&
1864 non_scatter_min_mbuf_size <= mprq_stride_cap))) {
1865 /* TODO: Rx scatter isn't supported yet. */
1866 tmpl->rxq.sges_n = 0;
1867 /* Trim the number of descs needed. */
1868 desc >>= mprq_stride_nums;
1869 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
1870 config->mprq.stride_num_n : mprq_stride_nums;
1871 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
1872 config->mprq.stride_size_n : mprq_stride_size;
1873 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1874 tmpl->rxq.strd_scatter_en =
1875 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
1876 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1877 config->mprq.max_memcpy_len);
1878 max_lro_size = RTE_MIN(max_rx_pkt_len,
1879 (1u << tmpl->rxq.strd_num_n) *
1880 (1u << tmpl->rxq.strd_sz_n));
1882 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1883 " strd_num_n = %u, strd_sz_n = %u",
1884 dev->data->port_id, idx,
1885 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1886 } else if (max_rx_pkt_len <= first_mb_free_size) {
1887 tmpl->rxq.sges_n = 0;
1888 max_lro_size = max_rx_pkt_len;
1889 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1890 unsigned int size = non_scatter_min_mbuf_size;
1891 unsigned int sges_n;
1893 if (lro_on_queue && first_mb_free_size <
1894 MLX5_MAX_LRO_HEADER_FIX) {
1895 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1896 " to include the max header size(%u) for LRO",
1897 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1898 rte_errno = ENOTSUP;
1902 * Determine the number of SGEs needed for a full packet
1903 * and round it to the next power of two.
1905 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1906 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1908 "port %u too many SGEs (%u) needed to handle"
1909 " requested maximum packet size %u, the maximum"
1910 " supported are %u", dev->data->port_id,
1911 1 << sges_n, max_rx_pkt_len,
1912 1u << MLX5_MAX_LOG_RQ_SEGS);
1913 rte_errno = ENOTSUP;
1916 tmpl->rxq.sges_n = sges_n;
1917 max_lro_size = max_rx_pkt_len;
1919 if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1921 "port %u MPRQ is requested but cannot be enabled\n"
1922 " (requested: pkt_sz = %u, desc_num = %u,"
1923 " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
1924 " supported: min_rxqs_num = %u,"
1925 " min_stride_sz = %u, max_stride_sz = %u).",
1926 dev->data->port_id, non_scatter_min_mbuf_size,
1928 config->mprq.stride_size_n ?
1929 (1U << config->mprq.stride_size_n) :
1930 (1U << mprq_stride_size),
1931 config->mprq.stride_num_n ?
1932 (1U << config->mprq.stride_num_n) :
1933 (1U << mprq_stride_nums),
1934 config->mprq.min_rxqs_num,
1935 (1U << config->mprq.min_stride_size_n),
1936 (1U << config->mprq.max_stride_size_n));
1937 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1938 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1939 if (desc % (1 << tmpl->rxq.sges_n)) {
1941 "port %u number of Rx queue descriptors (%u) is not a"
1942 " multiple of SGEs per packet (%u)",
1945 1 << tmpl->rxq.sges_n);
1949 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1950 /* Toggle RX checksum offload if hardware supports it. */
1951 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1952 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1953 /* Configure VLAN stripping. */
1954 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1955 /* By default, FCS (CRC) is stripped by hardware. */
1956 tmpl->rxq.crc_present = 0;
1957 tmpl->rxq.lro = lro_on_queue;
1958 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1959 if (config->hw_fcs_strip) {
1961 * RQs used for LRO-enabled TIRs should not be
1962 * configured to scatter the FCS.
1966 "port %u CRC stripping has been "
1967 "disabled but will still be performed "
1968 "by hardware, because LRO is enabled",
1969 dev->data->port_id);
1971 tmpl->rxq.crc_present = 1;
1974 "port %u CRC stripping has been disabled but will"
1975 " still be performed by hardware, make sure MLNX_OFED"
1976 " and firmware are up to date",
1977 dev->data->port_id);
1981 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1982 " incoming frames to hide it",
1984 tmpl->rxq.crc_present ? "disabled" : "enabled",
1985 tmpl->rxq.crc_present << 2);
1987 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1988 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1989 tmpl->rxq.port_id = dev->data->port_id;
1992 tmpl->rxq.elts_n = log2above(desc);
1993 tmpl->rxq.rq_repl_thresh =
1994 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1996 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1998 tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
2000 tmpl->rxq.idx = idx;
2001 rte_atomic32_inc(&tmpl->refcnt);
2002 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2010 * Create a DPDK Rx hairpin queue.
2013 * Pointer to Ethernet device.
2017 * Number of descriptors to configure in queue.
2018 * @param hairpin_conf
2019 * The hairpin binding configuration.
2022 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2024 struct mlx5_rxq_ctrl *
2025 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2026 const struct rte_eth_hairpin_conf *hairpin_conf)
2028 struct mlx5_priv *priv = dev->data->dev_private;
2029 struct mlx5_rxq_ctrl *tmpl;
2031 tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
2036 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2037 tmpl->socket = SOCKET_ID_ANY;
2038 tmpl->rxq.rss_hash = 0;
2039 tmpl->rxq.port_id = dev->data->port_id;
2041 tmpl->rxq.mp = NULL;
2042 tmpl->rxq.elts_n = log2above(desc);
2043 tmpl->rxq.elts = NULL;
2044 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2045 tmpl->hairpin_conf = *hairpin_conf;
2046 tmpl->rxq.idx = idx;
2047 rte_atomic32_inc(&tmpl->refcnt);
2048 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2056 * Pointer to Ethernet device.
2061 * A pointer to the queue if it exists, NULL otherwise.
2063 struct mlx5_rxq_ctrl *
2064 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2066 struct mlx5_priv *priv = dev->data->dev_private;
2067 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2069 if ((*priv->rxqs)[idx]) {
2070 rxq_ctrl = container_of((*priv->rxqs)[idx],
2071 struct mlx5_rxq_ctrl,
2073 mlx5_rxq_obj_get(dev, idx);
2074 rte_atomic32_inc(&rxq_ctrl->refcnt);
2080 * Release a Rx queue.
2083 * Pointer to Ethernet device.
2088 * 1 while a reference on it exists, 0 when freed.
2091 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2093 struct mlx5_priv *priv = dev->data->dev_private;
2094 struct mlx5_rxq_ctrl *rxq_ctrl;
2096 if (!(*priv->rxqs)[idx])
2098 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2099 MLX5_ASSERT(rxq_ctrl->priv);
2100 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2101 rxq_ctrl->obj = NULL;
2102 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2103 if (rxq_ctrl->dbr_umem_id_valid)
2104 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
2105 rxq_ctrl->dbr_offset));
2106 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2107 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2108 LIST_REMOVE(rxq_ctrl, next);
2110 (*priv->rxqs)[idx] = NULL;
2117 * Verify the Rx Queue list is empty
2120 * Pointer to Ethernet device.
2123 * The number of object not released.
2126 mlx5_rxq_verify(struct rte_eth_dev *dev)
2128 struct mlx5_priv *priv = dev->data->dev_private;
2129 struct mlx5_rxq_ctrl *rxq_ctrl;
2132 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2133 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2134 dev->data->port_id, rxq_ctrl->rxq.idx);
2141 * Get a Rx queue type.
2144 * Pointer to Ethernet device.
2149 * The Rx queue type.
2152 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2154 struct mlx5_priv *priv = dev->data->dev_private;
2155 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2157 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2158 rxq_ctrl = container_of((*priv->rxqs)[idx],
2159 struct mlx5_rxq_ctrl,
2161 return rxq_ctrl->type;
2163 return MLX5_RXQ_TYPE_UNDEFINED;
2167 * Create an indirection table.
2170 * Pointer to Ethernet device.
2172 * Queues entering in the indirection table.
2174 * Number of queues in the array.
2177 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2179 static struct mlx5_ind_table_obj *
2180 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2181 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2183 struct mlx5_priv *priv = dev->data->dev_private;
2184 struct mlx5_ind_table_obj *ind_tbl;
2185 unsigned int i = 0, j = 0, k = 0;
2187 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2188 queues_n * sizeof(uint16_t), 0);
2193 ind_tbl->type = type;
2194 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2195 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2196 log2above(queues_n) :
2197 log2above(priv->config.ind_table_max_size);
2198 struct ibv_wq *wq[1 << wq_n];
2200 for (i = 0; i != queues_n; ++i) {
2201 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2205 wq[i] = rxq->obj->wq;
2206 ind_tbl->queues[i] = queues[i];
2208 ind_tbl->queues_n = queues_n;
2209 /* Finalise indirection table. */
2210 k = i; /* Retain value of i for use in error case. */
2211 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2213 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2215 &(struct ibv_rwq_ind_table_init_attr){
2216 .log_ind_tbl_size = wq_n,
2220 if (!ind_tbl->ind_table) {
2224 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2225 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2226 const unsigned int rqt_n =
2227 1 << (rte_is_power_of_2(queues_n) ?
2228 log2above(queues_n) :
2229 log2above(priv->config.ind_table_max_size));
2231 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2232 rqt_n * sizeof(uint32_t), 0);
2234 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2235 dev->data->port_id);
2239 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2240 rqt_attr->rqt_actual_size = rqt_n;
2241 for (i = 0; i != queues_n; ++i) {
2242 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2246 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2247 ind_tbl->queues[i] = queues[i];
2249 k = i; /* Retain value of i for use in error case. */
2250 for (j = 0; k != rqt_n; ++k, ++j)
2251 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2252 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2255 if (!ind_tbl->rqt) {
2256 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2257 dev->data->port_id);
2261 ind_tbl->queues_n = queues_n;
2263 rte_atomic32_inc(&ind_tbl->refcnt);
2264 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2267 for (j = 0; j < i; j++)
2268 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2270 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2275 * Get an indirection table.
2278 * Pointer to Ethernet device.
2280 * Queues entering in the indirection table.
2282 * Number of queues in the array.
2285 * An indirection table if found.
2287 static struct mlx5_ind_table_obj *
2288 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2291 struct mlx5_priv *priv = dev->data->dev_private;
2292 struct mlx5_ind_table_obj *ind_tbl;
2294 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2295 if ((ind_tbl->queues_n == queues_n) &&
2296 (memcmp(ind_tbl->queues, queues,
2297 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2304 rte_atomic32_inc(&ind_tbl->refcnt);
2305 for (i = 0; i != ind_tbl->queues_n; ++i)
2306 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2312 * Release an indirection table.
2315 * Pointer to Ethernet device.
2317 * Indirection table to release.
2320 * 1 while a reference on it exists, 0 when freed.
2323 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2324 struct mlx5_ind_table_obj *ind_tbl)
2328 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2329 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2330 claim_zero(mlx5_glue->destroy_rwq_ind_table
2331 (ind_tbl->ind_table));
2332 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2333 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2335 for (i = 0; i != ind_tbl->queues_n; ++i)
2336 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2337 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2338 LIST_REMOVE(ind_tbl, next);
2346 * Verify the Rx Queue list is empty
2349 * Pointer to Ethernet device.
2352 * The number of object not released.
2355 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2357 struct mlx5_priv *priv = dev->data->dev_private;
2358 struct mlx5_ind_table_obj *ind_tbl;
2361 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2363 "port %u indirection table obj %p still referenced",
2364 dev->data->port_id, (void *)ind_tbl);
2371 * Create an Rx Hash queue.
2374 * Pointer to Ethernet device.
2376 * RSS key for the Rx hash queue.
2377 * @param rss_key_len
2379 * @param hash_fields
2380 * Verbs protocol hash field to make the RSS on.
2382 * Queues entering in hash queue. In case of empty hash_fields only the
2383 * first queue index will be taken for the indirection table.
2390 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
2393 mlx5_hrxq_new(struct rte_eth_dev *dev,
2394 const uint8_t *rss_key, uint32_t rss_key_len,
2395 uint64_t hash_fields,
2396 const uint16_t *queues, uint32_t queues_n,
2397 int tunnel __rte_unused)
2399 struct mlx5_priv *priv = dev->data->dev_private;
2400 struct mlx5_hrxq *hrxq;
2401 uint32_t hrxq_idx = 0;
2402 struct ibv_qp *qp = NULL;
2403 struct mlx5_ind_table_obj *ind_tbl;
2405 struct mlx5_devx_obj *tir = NULL;
2406 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2407 struct mlx5_rxq_ctrl *rxq_ctrl =
2408 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2410 queues_n = hash_fields ? queues_n : 1;
2411 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2413 enum mlx5_ind_tbl_type type;
2415 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2416 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2417 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2423 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2424 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2425 struct mlx5dv_qp_init_attr qp_init_attr;
2427 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2429 qp_init_attr.comp_mask =
2430 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2431 qp_init_attr.create_flags =
2432 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2434 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2435 if (dev->data->dev_conf.lpbk_mode) {
2437 * Allow packet sent from NIC loop back
2438 * w/o source MAC check.
2440 qp_init_attr.comp_mask |=
2441 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2442 qp_init_attr.create_flags |=
2443 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2446 qp = mlx5_glue->dv_create_qp
2448 &(struct ibv_qp_init_attr_ex){
2449 .qp_type = IBV_QPT_RAW_PACKET,
2451 IBV_QP_INIT_ATTR_PD |
2452 IBV_QP_INIT_ATTR_IND_TABLE |
2453 IBV_QP_INIT_ATTR_RX_HASH,
2454 .rx_hash_conf = (struct ibv_rx_hash_conf){
2456 IBV_RX_HASH_FUNC_TOEPLITZ,
2457 .rx_hash_key_len = rss_key_len,
2459 (void *)(uintptr_t)rss_key,
2460 .rx_hash_fields_mask = hash_fields,
2462 .rwq_ind_tbl = ind_tbl->ind_table,
2467 qp = mlx5_glue->create_qp_ex
2469 &(struct ibv_qp_init_attr_ex){
2470 .qp_type = IBV_QPT_RAW_PACKET,
2472 IBV_QP_INIT_ATTR_PD |
2473 IBV_QP_INIT_ATTR_IND_TABLE |
2474 IBV_QP_INIT_ATTR_RX_HASH,
2475 .rx_hash_conf = (struct ibv_rx_hash_conf){
2477 IBV_RX_HASH_FUNC_TOEPLITZ,
2478 .rx_hash_key_len = rss_key_len,
2480 (void *)(uintptr_t)rss_key,
2481 .rx_hash_fields_mask = hash_fields,
2483 .rwq_ind_tbl = ind_tbl->ind_table,
2491 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2492 struct mlx5_devx_tir_attr tir_attr;
2496 /* Enable TIR LRO only if all the queues were configured for. */
2497 for (i = 0; i < queues_n; ++i) {
2498 if (!(*priv->rxqs)[queues[i]]->lro) {
2503 memset(&tir_attr, 0, sizeof(tir_attr));
2504 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2505 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2506 tir_attr.tunneled_offload_en = !!tunnel;
2507 /* If needed, translate hash_fields bitmap to PRM format. */
2509 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2510 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2511 hash_fields & IBV_RX_HASH_INNER ?
2512 &tir_attr.rx_hash_field_selector_inner :
2513 &tir_attr.rx_hash_field_selector_outer;
2515 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2516 &tir_attr.rx_hash_field_selector_outer;
2519 /* 1 bit: 0: IPv4, 1: IPv6. */
2520 rx_hash_field_select->l3_prot_type =
2521 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2522 /* 1 bit: 0: TCP, 1: UDP. */
2523 rx_hash_field_select->l4_prot_type =
2524 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2525 /* Bitmask which sets which fields to use in RX Hash. */
2526 rx_hash_field_select->selected_fields =
2527 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2528 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2529 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2530 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2531 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2532 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2533 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2534 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2536 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2537 tir_attr.transport_domain = priv->sh->td->id;
2539 tir_attr.transport_domain = priv->sh->tdn;
2540 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2541 MLX5_RSS_HASH_KEY_LEN);
2542 tir_attr.indirect_table = ind_tbl->rqt->id;
2543 if (dev->data->dev_conf.lpbk_mode)
2544 tir_attr.self_lb_block =
2545 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2547 tir_attr.lro_timeout_period_usecs =
2548 priv->config.lro.timeout;
2549 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2550 tir_attr.lro_enable_mask =
2551 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2552 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2554 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2556 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2557 dev->data->port_id);
2562 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2565 hrxq->ind_table = ind_tbl;
2566 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2568 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2570 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2571 if (!hrxq->action) {
2576 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2578 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2579 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2581 if (!hrxq->action) {
2587 hrxq->rss_key_len = rss_key_len;
2588 hrxq->hash_fields = hash_fields;
2589 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2590 rte_atomic32_inc(&hrxq->refcnt);
2591 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
2595 err = rte_errno; /* Save rte_errno before cleanup. */
2596 mlx5_ind_table_obj_release(dev, ind_tbl);
2598 claim_zero(mlx5_glue->destroy_qp(qp));
2600 claim_zero(mlx5_devx_cmd_destroy(tir));
2601 rte_errno = err; /* Restore rte_errno. */
2606 * Get an Rx Hash queue.
2609 * Pointer to Ethernet device.
2611 * RSS configuration for the Rx hash queue.
2613 * Queues entering in hash queue. In case of empty hash_fields only the
2614 * first queue index will be taken for the indirection table.
2619 * An hash Rx queue index on success.
2622 mlx5_hrxq_get(struct rte_eth_dev *dev,
2623 const uint8_t *rss_key, uint32_t rss_key_len,
2624 uint64_t hash_fields,
2625 const uint16_t *queues, uint32_t queues_n)
2627 struct mlx5_priv *priv = dev->data->dev_private;
2628 struct mlx5_hrxq *hrxq;
2631 queues_n = hash_fields ? queues_n : 1;
2632 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2634 struct mlx5_ind_table_obj *ind_tbl;
2636 if (hrxq->rss_key_len != rss_key_len)
2638 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2640 if (hrxq->hash_fields != hash_fields)
2642 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2645 if (ind_tbl != hrxq->ind_table) {
2646 mlx5_ind_table_obj_release(dev, ind_tbl);
2649 rte_atomic32_inc(&hrxq->refcnt);
2656 * Release the hash Rx queue.
2659 * Pointer to Ethernet device.
2661 * Index to Hash Rx queue to release.
2664 * 1 while a reference on it exists, 0 when freed.
2667 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2669 struct mlx5_priv *priv = dev->data->dev_private;
2670 struct mlx5_hrxq *hrxq;
2672 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2675 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2676 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2677 mlx5_glue->destroy_flow_action(hrxq->action);
2679 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2680 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2681 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2682 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2683 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2684 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
2685 hrxq_idx, hrxq, next);
2686 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2689 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2694 * Verify the Rx Queue list is empty
2697 * Pointer to Ethernet device.
2700 * The number of object not released.
2703 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2705 struct mlx5_priv *priv = dev->data->dev_private;
2706 struct mlx5_hrxq *hrxq;
2710 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2713 "port %u hash Rx queue %p still referenced",
2714 dev->data->port_id, (void *)hrxq);
2721 * Create a drop Rx queue Verbs/DevX object.
2724 * Pointer to Ethernet device.
2727 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2729 static struct mlx5_rxq_obj *
2730 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2732 struct mlx5_priv *priv = dev->data->dev_private;
2733 struct ibv_context *ctx = priv->sh->ctx;
2735 struct ibv_wq *wq = NULL;
2736 struct mlx5_rxq_obj *rxq;
2738 if (priv->drop_queue.rxq)
2739 return priv->drop_queue.rxq;
2740 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2742 DEBUG("port %u cannot allocate CQ for drop queue",
2743 dev->data->port_id);
2747 wq = mlx5_glue->create_wq(ctx,
2748 &(struct ibv_wq_init_attr){
2749 .wq_type = IBV_WQT_RQ,
2756 DEBUG("port %u cannot allocate WQ for drop queue",
2757 dev->data->port_id);
2761 rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2763 DEBUG("port %u cannot allocate drop Rx queue memory",
2764 dev->data->port_id);
2770 priv->drop_queue.rxq = rxq;
2774 claim_zero(mlx5_glue->destroy_wq(wq));
2776 claim_zero(mlx5_glue->destroy_cq(cq));
2781 * Release a drop Rx queue Verbs/DevX object.
2784 * Pointer to Ethernet device.
2787 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2790 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2792 struct mlx5_priv *priv = dev->data->dev_private;
2793 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2796 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2798 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2800 priv->drop_queue.rxq = NULL;
2804 * Create a drop indirection table.
2807 * Pointer to Ethernet device.
2810 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2812 static struct mlx5_ind_table_obj *
2813 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2815 struct mlx5_priv *priv = dev->data->dev_private;
2816 struct mlx5_ind_table_obj *ind_tbl;
2817 struct mlx5_rxq_obj *rxq;
2818 struct mlx5_ind_table_obj tmpl;
2820 rxq = mlx5_rxq_obj_drop_new(dev);
2823 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2825 &(struct ibv_rwq_ind_table_init_attr){
2826 .log_ind_tbl_size = 0,
2827 .ind_tbl = &rxq->wq,
2830 if (!tmpl.ind_table) {
2831 DEBUG("port %u cannot allocate indirection table for drop"
2833 dev->data->port_id);
2837 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2842 ind_tbl->ind_table = tmpl.ind_table;
2845 mlx5_rxq_obj_drop_release(dev);
2850 * Release a drop indirection table.
2853 * Pointer to Ethernet device.
2856 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2858 struct mlx5_priv *priv = dev->data->dev_private;
2859 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2861 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2862 mlx5_rxq_obj_drop_release(dev);
2864 priv->drop_queue.hrxq->ind_table = NULL;
2868 * Create a drop Rx Hash queue.
2871 * Pointer to Ethernet device.
2874 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2877 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2879 struct mlx5_priv *priv = dev->data->dev_private;
2880 struct mlx5_ind_table_obj *ind_tbl = NULL;
2881 struct ibv_qp *qp = NULL;
2882 struct mlx5_hrxq *hrxq = NULL;
2884 if (priv->drop_queue.hrxq) {
2885 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2886 return priv->drop_queue.hrxq;
2888 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2891 "port %u cannot allocate memory for drop queue",
2892 dev->data->port_id);
2896 priv->drop_queue.hrxq = hrxq;
2897 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2900 hrxq->ind_table = ind_tbl;
2901 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2902 &(struct ibv_qp_init_attr_ex){
2903 .qp_type = IBV_QPT_RAW_PACKET,
2905 IBV_QP_INIT_ATTR_PD |
2906 IBV_QP_INIT_ATTR_IND_TABLE |
2907 IBV_QP_INIT_ATTR_RX_HASH,
2908 .rx_hash_conf = (struct ibv_rx_hash_conf){
2910 IBV_RX_HASH_FUNC_TOEPLITZ,
2911 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2912 .rx_hash_key = rss_hash_default_key,
2913 .rx_hash_fields_mask = 0,
2915 .rwq_ind_tbl = ind_tbl->ind_table,
2919 DEBUG("port %u cannot allocate QP for drop queue",
2920 dev->data->port_id);
2925 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2926 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2927 if (!hrxq->action) {
2932 rte_atomic32_set(&hrxq->refcnt, 1);
2935 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2936 if (hrxq && hrxq->action)
2937 mlx5_glue->destroy_flow_action(hrxq->action);
2940 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2942 mlx5_ind_table_obj_drop_release(dev);
2944 priv->drop_queue.hrxq = NULL;
2951 * Release a drop hash Rx queue.
2954 * Pointer to Ethernet device.
2957 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2959 struct mlx5_priv *priv = dev->data->dev_private;
2960 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2962 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2963 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2964 mlx5_glue->destroy_flow_action(hrxq->action);
2966 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2967 mlx5_ind_table_obj_drop_release(dev);
2969 priv->drop_queue.hrxq = NULL;