1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 #include <sys/queue.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
29 #include <rte_interrupts.h>
30 #include <rte_debug.h>
34 #include "mlx5_rxtx.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
38 #include "mlx5_glue.h"
40 /* Default RSS hash key also used for ConnectX-3. */
41 uint8_t rss_hash_default_key[] = {
42 0x2c, 0xc6, 0x81, 0xd1,
43 0x5b, 0xdb, 0xf4, 0xf7,
44 0xfc, 0xa2, 0x83, 0x19,
45 0xdb, 0x1a, 0x3e, 0x94,
46 0x6b, 0x9e, 0x38, 0xd9,
47 0x2c, 0x9c, 0x03, 0xd1,
48 0xad, 0x99, 0x44, 0xa7,
49 0xd9, 0x56, 0x3d, 0x59,
50 0x06, 0x3c, 0x25, 0xf3,
51 0xfc, 0x1f, 0xdc, 0x2a,
54 /* Length of the default RSS hash key. */
55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
56 (unsigned int)sizeof(rss_hash_default_key),
57 "wrong RSS default key size.");
60 * Check whether Multi-Packet RQ can be enabled for the device.
63 * Pointer to Ethernet device.
66 * 1 if supported, negative errno value if not.
69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
71 struct mlx5_priv *priv = dev->data->dev_private;
73 if (priv->config.mprq.enabled &&
74 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
80 * Check whether Multi-Packet RQ is enabled for the Rx queue.
83 * Pointer to receive queue structure.
86 * 0 if disabled, otherwise enabled.
89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
91 return rxq->strd_num_n > 0;
95 * Check whether Multi-Packet RQ is enabled for the device.
98 * Pointer to Ethernet device.
101 * 0 if disabled, otherwise enabled.
104 mlx5_mprq_enabled(struct rte_eth_dev *dev)
106 struct mlx5_priv *priv = dev->data->dev_private;
110 if (mlx5_check_mprq_support(dev) < 0)
112 /* All the configured queues should be enabled. */
113 for (i = 0; i < priv->rxqs_n; ++i) {
114 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
118 if (mlx5_rxq_mprq_enabled(rxq))
121 /* Multi-Packet RQ can't be partially configured. */
122 assert(n == 0 || n == priv->rxqs_n);
123 return n == priv->rxqs_n;
127 * Allocate RX queue elements for Multi-Packet RQ.
130 * Pointer to RX queue structure.
133 * 0 on success, a negative errno value otherwise and rte_errno is set.
136 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
138 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
139 unsigned int wqe_n = 1 << rxq->elts_n;
143 /* Iterate on segments. */
144 for (i = 0; i <= wqe_n; ++i) {
145 struct mlx5_mprq_buf *buf;
147 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
148 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
153 (*rxq->mprq_bufs)[i] = buf;
155 rxq->mprq_repl = buf;
158 "port %u Rx queue %u allocated and configured %u segments",
159 rxq->port_id, rxq->idx, wqe_n);
162 err = rte_errno; /* Save rte_errno before cleanup. */
164 for (i = 0; (i != wqe_n); ++i) {
165 if ((*rxq->mprq_bufs)[i] != NULL)
166 rte_mempool_put(rxq->mprq_mp,
167 (*rxq->mprq_bufs)[i]);
168 (*rxq->mprq_bufs)[i] = NULL;
170 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
171 rxq->port_id, rxq->idx);
172 rte_errno = err; /* Restore rte_errno. */
177 * Allocate RX queue elements for Single-Packet RQ.
180 * Pointer to RX queue structure.
183 * 0 on success, errno value on failure.
186 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
188 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
189 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
193 /* Iterate on segments. */
194 for (i = 0; (i != elts_n); ++i) {
195 struct rte_mbuf *buf;
197 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
199 DRV_LOG(ERR, "port %u empty mbuf pool",
200 PORT_ID(rxq_ctrl->priv));
204 /* Headroom is reserved by rte_pktmbuf_alloc(). */
205 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
206 /* Buffer is supposed to be empty. */
207 assert(rte_pktmbuf_data_len(buf) == 0);
208 assert(rte_pktmbuf_pkt_len(buf) == 0);
210 /* Only the first segment keeps headroom. */
212 SET_DATA_OFF(buf, 0);
213 PORT(buf) = rxq_ctrl->rxq.port_id;
214 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
215 PKT_LEN(buf) = DATA_LEN(buf);
217 (*rxq_ctrl->rxq.elts)[i] = buf;
219 /* If Rx vector is activated. */
220 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
221 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
222 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
225 /* Initialize default rearm_data for vPMD. */
226 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
227 rte_mbuf_refcnt_set(mbuf_init, 1);
228 mbuf_init->nb_segs = 1;
229 mbuf_init->port = rxq->port_id;
231 * prevent compiler reordering:
232 * rearm_data covers previous fields.
234 rte_compiler_barrier();
235 rxq->mbuf_initializer =
236 *(uint64_t *)&mbuf_init->rearm_data;
237 /* Padding with a fake mbuf for vectorized Rx. */
238 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
239 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
242 "port %u Rx queue %u allocated and configured %u segments"
244 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
245 elts_n / (1 << rxq_ctrl->rxq.sges_n));
248 err = rte_errno; /* Save rte_errno before cleanup. */
250 for (i = 0; (i != elts_n); ++i) {
251 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
252 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
253 (*rxq_ctrl->rxq.elts)[i] = NULL;
255 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
256 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
257 rte_errno = err; /* Restore rte_errno. */
262 * Allocate RX queue elements.
265 * Pointer to RX queue structure.
268 * 0 on success, errno value on failure.
271 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
273 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
274 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
278 * Free RX queue elements for Multi-Packet RQ.
281 * Pointer to RX queue structure.
284 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
286 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
289 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
290 rxq->port_id, rxq->idx);
291 if (rxq->mprq_bufs == NULL)
293 assert(mlx5_rxq_check_vec_support(rxq) < 0);
294 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
295 if ((*rxq->mprq_bufs)[i] != NULL)
296 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
297 (*rxq->mprq_bufs)[i] = NULL;
299 if (rxq->mprq_repl != NULL) {
300 mlx5_mprq_buf_free(rxq->mprq_repl);
301 rxq->mprq_repl = NULL;
306 * Free RX queue elements for Single-Packet RQ.
309 * Pointer to RX queue structure.
312 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
314 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
315 const uint16_t q_n = (1 << rxq->elts_n);
316 const uint16_t q_mask = q_n - 1;
317 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
320 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
321 PORT_ID(rxq_ctrl->priv), rxq->idx);
322 if (rxq->elts == NULL)
325 * Some mbuf in the Ring belongs to the application. They cannot be
328 if (mlx5_rxq_check_vec_support(rxq) > 0) {
329 for (i = 0; i < used; ++i)
330 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
331 rxq->rq_pi = rxq->rq_ci;
333 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
334 if ((*rxq->elts)[i] != NULL)
335 rte_pktmbuf_free_seg((*rxq->elts)[i]);
336 (*rxq->elts)[i] = NULL;
341 * Free RX queue elements.
344 * Pointer to RX queue structure.
347 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
349 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
350 rxq_free_elts_mprq(rxq_ctrl);
352 rxq_free_elts_sprq(rxq_ctrl);
356 * Returns the per-queue supported offloads.
359 * Pointer to Ethernet device.
362 * Supported Rx offloads.
365 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
367 struct mlx5_priv *priv = dev->data->dev_private;
368 struct mlx5_dev_config *config = &priv->config;
369 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
370 DEV_RX_OFFLOAD_TIMESTAMP |
371 DEV_RX_OFFLOAD_JUMBO_FRAME);
373 if (config->hw_fcs_strip)
374 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
377 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
378 DEV_RX_OFFLOAD_UDP_CKSUM |
379 DEV_RX_OFFLOAD_TCP_CKSUM);
380 if (config->hw_vlan_strip)
381 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
387 * Returns the per-port supported offloads.
390 * Supported Rx offloads.
393 mlx5_get_rx_port_offloads(void)
395 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
403 * Pointer to Ethernet device structure.
407 * Number of descriptors to configure in queue.
409 * NUMA socket on which memory must be allocated.
411 * Thresholds parameters.
413 * Memory pool for buffer allocations.
416 * 0 on success, a negative errno value otherwise and rte_errno is set.
419 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
420 unsigned int socket, const struct rte_eth_rxconf *conf,
421 struct rte_mempool *mp)
423 struct mlx5_priv *priv = dev->data->dev_private;
424 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
425 struct mlx5_rxq_ctrl *rxq_ctrl =
426 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
428 if (!rte_is_power_of_2(desc)) {
429 desc = 1 << log2above(desc);
431 "port %u increased number of descriptors in Rx queue %u"
432 " to the next power of two (%d)",
433 dev->data->port_id, idx, desc);
435 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
436 dev->data->port_id, idx, desc);
437 if (idx >= priv->rxqs_n) {
438 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
439 dev->data->port_id, idx, priv->rxqs_n);
440 rte_errno = EOVERFLOW;
443 if (!mlx5_rxq_releasable(dev, idx)) {
444 DRV_LOG(ERR, "port %u unable to release queue index %u",
445 dev->data->port_id, idx);
449 mlx5_rxq_release(dev, idx);
450 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
452 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
453 dev->data->port_id, idx);
457 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
458 dev->data->port_id, idx);
459 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
464 * DPDK callback to release a RX queue.
467 * Generic RX queue pointer.
470 mlx5_rx_queue_release(void *dpdk_rxq)
472 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
473 struct mlx5_rxq_ctrl *rxq_ctrl;
474 struct mlx5_priv *priv;
478 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
479 priv = rxq_ctrl->priv;
480 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
481 rte_panic("port %u Rx queue %u is still used by a flow and"
482 " cannot be removed\n",
483 PORT_ID(priv), rxq->idx);
484 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
488 * Allocate queue vector and fill epoll fd list for Rx interrupts.
491 * Pointer to Ethernet device.
494 * 0 on success, a negative errno value otherwise and rte_errno is set.
497 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
499 struct mlx5_priv *priv = dev->data->dev_private;
501 unsigned int rxqs_n = priv->rxqs_n;
502 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
503 unsigned int count = 0;
504 struct rte_intr_handle *intr_handle = dev->intr_handle;
506 if (!dev->data->dev_conf.intr_conf.rxq)
508 mlx5_rx_intr_vec_disable(dev);
509 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
510 if (intr_handle->intr_vec == NULL) {
512 "port %u failed to allocate memory for interrupt"
513 " vector, Rx interrupts will not be supported",
518 intr_handle->type = RTE_INTR_HANDLE_EXT;
519 for (i = 0; i != n; ++i) {
520 /* This rxq ibv must not be released in this function. */
521 struct mlx5_rxq_ibv *rxq_ibv = mlx5_rxq_ibv_get(dev, i);
526 /* Skip queues that cannot request interrupts. */
527 if (!rxq_ibv || !rxq_ibv->channel) {
528 /* Use invalid intr_vec[] index to disable entry. */
529 intr_handle->intr_vec[i] =
530 RTE_INTR_VEC_RXTX_OFFSET +
531 RTE_MAX_RXTX_INTR_VEC_ID;
534 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
536 "port %u too many Rx queues for interrupt"
537 " vector size (%d), Rx interrupts cannot be"
539 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
540 mlx5_rx_intr_vec_disable(dev);
544 fd = rxq_ibv->channel->fd;
545 flags = fcntl(fd, F_GETFL);
546 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
550 "port %u failed to make Rx interrupt file"
551 " descriptor %d non-blocking for queue index"
553 dev->data->port_id, fd, i);
554 mlx5_rx_intr_vec_disable(dev);
557 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
558 intr_handle->efds[count] = fd;
562 mlx5_rx_intr_vec_disable(dev);
564 intr_handle->nb_efd = count;
569 * Clean up Rx interrupts handler.
572 * Pointer to Ethernet device.
575 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
577 struct mlx5_priv *priv = dev->data->dev_private;
578 struct rte_intr_handle *intr_handle = dev->intr_handle;
580 unsigned int rxqs_n = priv->rxqs_n;
581 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
583 if (!dev->data->dev_conf.intr_conf.rxq)
585 if (!intr_handle->intr_vec)
587 for (i = 0; i != n; ++i) {
588 struct mlx5_rxq_ctrl *rxq_ctrl;
589 struct mlx5_rxq_data *rxq_data;
591 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
592 RTE_MAX_RXTX_INTR_VEC_ID)
595 * Need to access directly the queue to release the reference
596 * kept in mlx5_rx_intr_vec_enable().
598 rxq_data = (*priv->rxqs)[i];
599 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
601 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
604 rte_intr_free_epoll_fd(intr_handle);
605 if (intr_handle->intr_vec)
606 free(intr_handle->intr_vec);
607 intr_handle->nb_efd = 0;
608 intr_handle->intr_vec = NULL;
612 * MLX5 CQ notification .
615 * Pointer to receive queue structure.
617 * Sequence number per receive queue .
620 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
623 uint32_t doorbell_hi;
625 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
627 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
628 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
629 doorbell = (uint64_t)doorbell_hi << 32;
630 doorbell |= rxq->cqn;
631 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
632 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
633 cq_db_reg, rxq->uar_lock_cq);
637 * DPDK callback for Rx queue interrupt enable.
640 * Pointer to Ethernet device structure.
645 * 0 on success, a negative errno value otherwise and rte_errno is set.
648 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
650 struct mlx5_priv *priv = dev->data->dev_private;
651 struct mlx5_rxq_data *rxq_data;
652 struct mlx5_rxq_ctrl *rxq_ctrl;
654 rxq_data = (*priv->rxqs)[rx_queue_id];
659 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
661 struct mlx5_rxq_ibv *rxq_ibv;
663 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
668 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
669 mlx5_rxq_ibv_release(rxq_ibv);
675 * DPDK callback for Rx queue interrupt disable.
678 * Pointer to Ethernet device structure.
683 * 0 on success, a negative errno value otherwise and rte_errno is set.
686 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
688 struct mlx5_priv *priv = dev->data->dev_private;
689 struct mlx5_rxq_data *rxq_data;
690 struct mlx5_rxq_ctrl *rxq_ctrl;
691 struct mlx5_rxq_ibv *rxq_ibv = NULL;
692 struct ibv_cq *ev_cq;
696 rxq_data = (*priv->rxqs)[rx_queue_id];
701 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
704 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
709 ret = mlx5_glue->get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
710 if (ret || ev_cq != rxq_ibv->cq) {
714 rxq_data->cq_arm_sn++;
715 mlx5_glue->ack_cq_events(rxq_ibv->cq, 1);
716 mlx5_rxq_ibv_release(rxq_ibv);
719 ret = rte_errno; /* Save rte_errno before cleanup. */
721 mlx5_rxq_ibv_release(rxq_ibv);
722 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
723 dev->data->port_id, rx_queue_id);
724 rte_errno = ret; /* Restore rte_errno. */
729 * Create the Rx queue Verbs object.
732 * Pointer to Ethernet device.
734 * Queue index in DPDK Rx queue array
737 * The Verbs object initialised, NULL otherwise and rte_errno is set.
739 struct mlx5_rxq_ibv *
740 mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
742 struct mlx5_priv *priv = dev->data->dev_private;
743 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
744 struct mlx5_rxq_ctrl *rxq_ctrl =
745 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
746 struct ibv_wq_attr mod;
749 struct ibv_cq_init_attr_ex ibv;
750 struct mlx5dv_cq_init_attr mlx5;
753 struct ibv_wq_init_attr ibv;
754 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
755 struct mlx5dv_wq_init_attr mlx5;
758 struct ibv_cq_ex cq_attr;
761 unsigned int wqe_n = 1 << rxq_data->elts_n;
762 struct mlx5_rxq_ibv *tmpl;
763 struct mlx5dv_cq cq_info;
764 struct mlx5dv_rwq rwq;
767 struct mlx5dv_obj obj;
768 struct mlx5_dev_config *config = &priv->config;
769 const int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);
772 assert(!rxq_ctrl->ibv);
773 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
774 priv->verbs_alloc_ctx.obj = rxq_ctrl;
775 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
779 "port %u Rx queue %u cannot allocate verbs resources",
780 dev->data->port_id, rxq_data->idx);
784 tmpl->rxq_ctrl = rxq_ctrl;
786 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
787 if (!tmpl->channel) {
788 DRV_LOG(ERR, "port %u: comp channel creation failure",
795 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
798 attr.cq.ibv = (struct ibv_cq_init_attr_ex){
800 .channel = tmpl->channel,
803 attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
806 if (config->cqe_comp && !rxq_data->hw_timestamp) {
807 attr.cq.mlx5.comp_mask |=
808 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
809 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
810 attr.cq.mlx5.cqe_comp_res_format =
811 mprq_en ? MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
812 MLX5DV_CQE_RES_FORMAT_HASH;
814 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
817 * For vectorized Rx, it must not be doubled in order to
818 * make cq_ci and rq_ci aligned.
820 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
821 attr.cq.ibv.cqe *= 2;
822 } else if (config->cqe_comp && rxq_data->hw_timestamp) {
824 "port %u Rx CQE compression is disabled for HW"
828 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
829 if (config->cqe_pad) {
830 attr.cq.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
831 attr.cq.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
834 tmpl->cq = mlx5_glue->cq_ex_to_cq
835 (mlx5_glue->dv_create_cq(priv->sh->ctx, &attr.cq.ibv,
837 if (tmpl->cq == NULL) {
838 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
839 dev->data->port_id, idx);
843 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
844 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
845 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
846 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
847 attr.wq.ibv = (struct ibv_wq_init_attr){
848 .wq_context = NULL, /* Could be useful in the future. */
849 .wq_type = IBV_WQT_RQ,
850 /* Max number of outstanding WRs. */
851 .max_wr = wqe_n >> rxq_data->sges_n,
852 /* Max number of scatter/gather elements in a WR. */
853 .max_sge = 1 << rxq_data->sges_n,
857 IBV_WQ_FLAGS_CVLAN_STRIPPING |
859 .create_flags = (rxq_data->vlan_strip ?
860 IBV_WQ_FLAGS_CVLAN_STRIPPING :
863 /* By default, FCS (CRC) is stripped by hardware. */
864 if (rxq_data->crc_present) {
865 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
866 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
868 if (config->hw_padding) {
869 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
870 attr.wq.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
871 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
872 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
873 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
874 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
877 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
878 attr.wq.mlx5 = (struct mlx5dv_wq_init_attr){
882 struct mlx5dv_striding_rq_init_attr *mprq_attr =
883 &attr.wq.mlx5.striding_rq_attrs;
885 attr.wq.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
886 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
887 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
888 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
889 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
892 tmpl->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &attr.wq.ibv,
895 tmpl->wq = mlx5_glue->create_wq(priv->sh->ctx, &attr.wq.ibv);
897 if (tmpl->wq == NULL) {
898 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
899 dev->data->port_id, idx);
904 * Make sure number of WRs*SGEs match expectations since a queue
905 * cannot allocate more than "desc" buffers.
907 if (attr.wq.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
908 attr.wq.ibv.max_sge != (1u << rxq_data->sges_n)) {
910 "port %u Rx queue %u requested %u*%u but got %u*%u"
912 dev->data->port_id, idx,
913 wqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),
914 attr.wq.ibv.max_wr, attr.wq.ibv.max_sge);
918 /* Change queue state to ready. */
919 mod = (struct ibv_wq_attr){
920 .attr_mask = IBV_WQ_ATTR_STATE,
921 .wq_state = IBV_WQS_RDY,
923 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
926 "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
927 dev->data->port_id, idx);
931 obj.cq.in = tmpl->cq;
932 obj.cq.out = &cq_info;
933 obj.rwq.in = tmpl->wq;
935 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
940 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
942 "port %u wrong MLX5_CQE_SIZE environment variable"
943 " value: it should be set to %u",
944 dev->data->port_id, RTE_CACHE_LINE_SIZE);
948 /* Fill the rings. */
949 rxq_data->wqes = rwq.buf;
950 for (i = 0; (i != wqe_n); ++i) {
951 volatile struct mlx5_wqe_data_seg *scat;
956 struct mlx5_mprq_buf *buf = (*rxq_data->mprq_bufs)[i];
958 scat = &((volatile struct mlx5_wqe_mprq *)
959 rxq_data->wqes)[i].dseg;
960 addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
961 byte_count = (1 << rxq_data->strd_sz_n) *
962 (1 << rxq_data->strd_num_n);
964 struct rte_mbuf *buf = (*rxq_data->elts)[i];
966 scat = &((volatile struct mlx5_wqe_data_seg *)
968 addr = rte_pktmbuf_mtod(buf, uintptr_t);
969 byte_count = DATA_LEN(buf);
971 /* scat->addr must be able to store a pointer. */
972 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
973 *scat = (struct mlx5_wqe_data_seg){
974 .addr = rte_cpu_to_be_64(addr),
975 .byte_count = rte_cpu_to_be_32(byte_count),
976 .lkey = mlx5_rx_addr2mr(rxq_data, addr),
979 rxq_data->rq_db = rwq.dbrec;
980 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
982 rxq_data->consumed_strd = 0;
984 rxq_data->zip = (struct rxq_zip){
987 rxq_data->cq_db = cq_info.dbrec;
988 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
989 rxq_data->cq_uar = cq_info.cq_uar;
990 rxq_data->cqn = cq_info.cqn;
991 rxq_data->cq_arm_sn = 0;
992 /* Update doorbell counter. */
993 rxq_data->rq_ci = wqe_n >> rxq_data->sges_n;
995 *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
996 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
998 rte_atomic32_inc(&tmpl->refcnt);
999 LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
1000 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1003 ret = rte_errno; /* Save rte_errno before cleanup. */
1005 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1007 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1009 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->channel));
1010 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1011 rte_errno = ret; /* Restore rte_errno. */
1016 * Get an Rx queue Verbs object.
1019 * Pointer to Ethernet device.
1021 * Queue index in DPDK Rx queue array
1024 * The Verbs object if it exists.
1026 struct mlx5_rxq_ibv *
1027 mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
1029 struct mlx5_priv *priv = dev->data->dev_private;
1030 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1031 struct mlx5_rxq_ctrl *rxq_ctrl;
1033 if (idx >= priv->rxqs_n)
1037 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1038 if (rxq_ctrl->ibv) {
1039 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
1041 return rxq_ctrl->ibv;
1045 * Release an Rx verbs queue object.
1048 * Verbs Rx queue object.
1051 * 1 while a reference on it exists, 0 when freed.
1054 mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv)
1057 assert(rxq_ibv->wq);
1058 assert(rxq_ibv->cq);
1059 if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
1060 rxq_free_elts(rxq_ibv->rxq_ctrl);
1061 claim_zero(mlx5_glue->destroy_wq(rxq_ibv->wq));
1062 claim_zero(mlx5_glue->destroy_cq(rxq_ibv->cq));
1063 if (rxq_ibv->channel)
1064 claim_zero(mlx5_glue->destroy_comp_channel
1065 (rxq_ibv->channel));
1066 LIST_REMOVE(rxq_ibv, next);
1074 * Verify the Verbs Rx queue list is empty
1077 * Pointer to Ethernet device.
1080 * The number of object not released.
1083 mlx5_rxq_ibv_verify(struct rte_eth_dev *dev)
1085 struct mlx5_priv *priv = dev->data->dev_private;
1087 struct mlx5_rxq_ibv *rxq_ibv;
1089 LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
1090 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u still referenced",
1091 dev->data->port_id, rxq_ibv->rxq_ctrl->rxq.idx);
1098 * Callback function to initialize mbufs for Multi-Packet RQ.
1101 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1102 void *_m, unsigned int i __rte_unused)
1104 struct mlx5_mprq_buf *buf = _m;
1106 memset(_m, 0, sizeof(*buf));
1108 rte_atomic16_set(&buf->refcnt, 1);
1112 * Free mempool of Multi-Packet RQ.
1115 * Pointer to Ethernet device.
1118 * 0 on success, negative errno value on failure.
1121 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1123 struct mlx5_priv *priv = dev->data->dev_private;
1124 struct rte_mempool *mp = priv->mprq_mp;
1129 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1130 dev->data->port_id, mp->name);
1132 * If a buffer in the pool has been externally attached to a mbuf and it
1133 * is still in use by application, destroying the Rx qeueue can spoil
1134 * the packet. It is unlikely to happen but if application dynamically
1135 * creates and destroys with holding Rx packets, this can happen.
1137 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1138 * RQ isn't provided by application but managed by PMD.
1140 if (!rte_mempool_full(mp)) {
1142 "port %u mempool for Multi-Packet RQ is still in use",
1143 dev->data->port_id);
1147 rte_mempool_free(mp);
1148 /* Unset mempool for each Rx queue. */
1149 for (i = 0; i != priv->rxqs_n; ++i) {
1150 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1154 rxq->mprq_mp = NULL;
1156 priv->mprq_mp = NULL;
1161 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1162 * mempool. If already allocated, reuse it if there're enough elements.
1163 * Otherwise, resize it.
1166 * Pointer to Ethernet device.
1169 * 0 on success, negative errno value on failure.
1172 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1174 struct mlx5_priv *priv = dev->data->dev_private;
1175 struct rte_mempool *mp = priv->mprq_mp;
1176 char name[RTE_MEMPOOL_NAMESIZE];
1177 unsigned int desc = 0;
1178 unsigned int buf_len;
1179 unsigned int obj_num;
1180 unsigned int obj_size;
1181 unsigned int strd_num_n = 0;
1182 unsigned int strd_sz_n = 0;
1185 if (!mlx5_mprq_enabled(dev))
1187 /* Count the total number of descriptors configured. */
1188 for (i = 0; i != priv->rxqs_n; ++i) {
1189 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1193 desc += 1 << rxq->elts_n;
1194 /* Get the max number of strides. */
1195 if (strd_num_n < rxq->strd_num_n)
1196 strd_num_n = rxq->strd_num_n;
1197 /* Get the max size of a stride. */
1198 if (strd_sz_n < rxq->strd_sz_n)
1199 strd_sz_n = rxq->strd_sz_n;
1201 assert(strd_num_n && strd_sz_n);
1202 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1203 obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1205 * Received packets can be either memcpy'd or externally referenced. In
1206 * case that the packet is attached to an mbuf as an external buffer, as
1207 * it isn't possible to predict how the buffers will be queued by
1208 * application, there's no option to exactly pre-allocate needed buffers
1209 * in advance but to speculatively prepares enough buffers.
1211 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1212 * received packets to buffers provided by application (rxq->mp) until
1213 * this Mempool gets available again.
1216 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1218 * rte_mempool_create_empty() has sanity check to refuse large cache
1219 * size compared to the number of elements.
1220 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1221 * constant number 2 instead.
1223 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1224 /* Check a mempool is already allocated and if it can be resued. */
1225 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1226 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1227 dev->data->port_id, mp->name);
1230 } else if (mp != NULL) {
1231 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1232 dev->data->port_id, mp->name);
1234 * If failed to free, which means it may be still in use, no way
1235 * but to keep using the existing one. On buffer underrun,
1236 * packets will be memcpy'd instead of external buffer
1239 if (mlx5_mprq_free_mp(dev)) {
1240 if (mp->elt_size >= obj_size)
1246 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1247 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1248 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1249 dev->device->numa_node, 0);
1252 "port %u failed to allocate a mempool for"
1253 " Multi-Packet RQ, count=%u, size=%u",
1254 dev->data->port_id, obj_num, obj_size);
1260 /* Set mempool for each Rx queue. */
1261 for (i = 0; i != priv->rxqs_n; ++i) {
1262 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1268 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1269 dev->data->port_id);
1274 * Create a DPDK Rx queue.
1277 * Pointer to Ethernet device.
1281 * Number of descriptors to configure in queue.
1283 * NUMA socket on which memory must be allocated.
1286 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1288 struct mlx5_rxq_ctrl *
1289 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1290 unsigned int socket, const struct rte_eth_rxconf *conf,
1291 struct rte_mempool *mp)
1293 struct mlx5_priv *priv = dev->data->dev_private;
1294 struct mlx5_rxq_ctrl *tmpl;
1295 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1296 unsigned int mprq_stride_size;
1297 struct mlx5_dev_config *config = &priv->config;
1299 * Always allocate extra slots, even if eventually
1300 * the vector Rx will not be used.
1303 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1304 uint64_t offloads = conf->offloads |
1305 dev->data->dev_conf.rxmode.offloads;
1306 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1308 tmpl = rte_calloc_socket("RXQ", 1,
1310 desc_n * sizeof(struct rte_mbuf *),
1316 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1317 MLX5_MR_BTREE_CACHE_N, socket)) {
1318 /* rte_errno is already set. */
1321 tmpl->socket = socket;
1322 if (dev->data->dev_conf.intr_conf.rxq)
1325 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1326 * following conditions are met:
1327 * - MPRQ is enabled.
1328 * - The number of descs is more than the number of strides.
1329 * - max_rx_pkt_len plus overhead is less than the max size of a
1331 * Otherwise, enable Rx scatter if necessary.
1333 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1335 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1336 sizeof(struct rte_mbuf_ext_shared_info) +
1337 RTE_PKTMBUF_HEADROOM;
1339 desc > (1U << config->mprq.stride_num_n) &&
1340 mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1341 /* TODO: Rx scatter isn't supported yet. */
1342 tmpl->rxq.sges_n = 0;
1343 /* Trim the number of descs needed. */
1344 desc >>= config->mprq.stride_num_n;
1345 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1346 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1347 config->mprq.min_stride_size_n);
1348 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1349 tmpl->rxq.mprq_max_memcpy_len =
1350 RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1351 config->mprq.max_memcpy_len);
1353 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1354 " strd_num_n = %u, strd_sz_n = %u",
1355 dev->data->port_id, idx,
1356 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1357 } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1358 (mb_len - RTE_PKTMBUF_HEADROOM)) {
1359 tmpl->rxq.sges_n = 0;
1360 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1362 RTE_PKTMBUF_HEADROOM +
1363 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1364 unsigned int sges_n;
1367 * Determine the number of SGEs needed for a full packet
1368 * and round it to the next power of two.
1370 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1371 tmpl->rxq.sges_n = sges_n;
1372 /* Make sure rxq.sges_n did not overflow. */
1373 size = mb_len * (1 << tmpl->rxq.sges_n);
1374 size -= RTE_PKTMBUF_HEADROOM;
1375 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1377 "port %u too many SGEs (%u) needed to handle"
1378 " requested maximum packet size %u",
1381 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1382 rte_errno = EOVERFLOW;
1387 "port %u the requested maximum Rx packet size (%u) is"
1388 " larger than a single mbuf (%u) and scattered mode has"
1389 " not been requested",
1391 dev->data->dev_conf.rxmode.max_rx_pkt_len,
1392 mb_len - RTE_PKTMBUF_HEADROOM);
1394 if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1396 "port %u MPRQ is requested but cannot be enabled"
1397 " (requested: desc = %u, stride_sz = %u,"
1398 " supported: min_stride_num = %u, max_stride_sz = %u).",
1399 dev->data->port_id, desc, mprq_stride_size,
1400 (1 << config->mprq.stride_num_n),
1401 (1 << config->mprq.max_stride_size_n));
1402 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1403 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1404 if (desc % (1 << tmpl->rxq.sges_n)) {
1406 "port %u number of Rx queue descriptors (%u) is not a"
1407 " multiple of SGEs per packet (%u)",
1410 1 << tmpl->rxq.sges_n);
1414 /* Toggle RX checksum offload if hardware supports it. */
1415 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1416 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1417 /* Configure VLAN stripping. */
1418 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1419 /* By default, FCS (CRC) is stripped by hardware. */
1420 tmpl->rxq.crc_present = 0;
1421 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1422 if (config->hw_fcs_strip) {
1423 tmpl->rxq.crc_present = 1;
1426 "port %u CRC stripping has been disabled but will"
1427 " still be performed by hardware, make sure MLNX_OFED"
1428 " and firmware are up to date",
1429 dev->data->port_id);
1433 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1434 " incoming frames to hide it",
1436 tmpl->rxq.crc_present ? "disabled" : "enabled",
1437 tmpl->rxq.crc_present << 2);
1439 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1440 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1441 tmpl->rxq.port_id = dev->data->port_id;
1444 tmpl->rxq.elts_n = log2above(desc);
1445 tmpl->rxq.rq_repl_thresh =
1446 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1448 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1450 tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1452 tmpl->rxq.idx = idx;
1453 rte_atomic32_inc(&tmpl->refcnt);
1454 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1465 * Pointer to Ethernet device.
1470 * A pointer to the queue if it exists, NULL otherwise.
1472 struct mlx5_rxq_ctrl *
1473 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1475 struct mlx5_priv *priv = dev->data->dev_private;
1476 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1478 if ((*priv->rxqs)[idx]) {
1479 rxq_ctrl = container_of((*priv->rxqs)[idx],
1480 struct mlx5_rxq_ctrl,
1482 mlx5_rxq_ibv_get(dev, idx);
1483 rte_atomic32_inc(&rxq_ctrl->refcnt);
1489 * Release a Rx queue.
1492 * Pointer to Ethernet device.
1497 * 1 while a reference on it exists, 0 when freed.
1500 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1502 struct mlx5_priv *priv = dev->data->dev_private;
1503 struct mlx5_rxq_ctrl *rxq_ctrl;
1505 if (!(*priv->rxqs)[idx])
1507 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1508 assert(rxq_ctrl->priv);
1509 if (rxq_ctrl->ibv && !mlx5_rxq_ibv_release(rxq_ctrl->ibv))
1510 rxq_ctrl->ibv = NULL;
1511 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1512 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1513 LIST_REMOVE(rxq_ctrl, next);
1515 (*priv->rxqs)[idx] = NULL;
1522 * Verify if the queue can be released.
1525 * Pointer to Ethernet device.
1530 * 1 if the queue can be released, negative errno otherwise and rte_errno is
1534 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1536 struct mlx5_priv *priv = dev->data->dev_private;
1537 struct mlx5_rxq_ctrl *rxq_ctrl;
1539 if (!(*priv->rxqs)[idx]) {
1543 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1544 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1548 * Verify the Rx Queue list is empty
1551 * Pointer to Ethernet device.
1554 * The number of object not released.
1557 mlx5_rxq_verify(struct rte_eth_dev *dev)
1559 struct mlx5_priv *priv = dev->data->dev_private;
1560 struct mlx5_rxq_ctrl *rxq_ctrl;
1563 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1564 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1565 dev->data->port_id, rxq_ctrl->rxq.idx);
1572 * Create an indirection table.
1575 * Pointer to Ethernet device.
1577 * Queues entering in the indirection table.
1579 * Number of queues in the array.
1582 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1584 struct mlx5_ind_table_ibv *
1585 mlx5_ind_table_ibv_new(struct rte_eth_dev *dev, const uint16_t *queues,
1588 struct mlx5_priv *priv = dev->data->dev_private;
1589 struct mlx5_ind_table_ibv *ind_tbl;
1590 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1591 log2above(queues_n) :
1592 log2above(priv->config.ind_table_max_size);
1593 struct ibv_wq *wq[1 << wq_n];
1597 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1598 queues_n * sizeof(uint16_t), 0);
1603 for (i = 0; i != queues_n; ++i) {
1604 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1608 wq[i] = rxq->ibv->wq;
1609 ind_tbl->queues[i] = queues[i];
1611 ind_tbl->queues_n = queues_n;
1612 /* Finalise indirection table. */
1613 for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1615 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1617 &(struct ibv_rwq_ind_table_init_attr){
1618 .log_ind_tbl_size = wq_n,
1622 if (!ind_tbl->ind_table) {
1626 rte_atomic32_inc(&ind_tbl->refcnt);
1627 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1631 DEBUG("port %u cannot create indirection table", dev->data->port_id);
1636 * Get an indirection table.
1639 * Pointer to Ethernet device.
1641 * Queues entering in the indirection table.
1643 * Number of queues in the array.
1646 * An indirection table if found.
1648 struct mlx5_ind_table_ibv *
1649 mlx5_ind_table_ibv_get(struct rte_eth_dev *dev, const uint16_t *queues,
1652 struct mlx5_priv *priv = dev->data->dev_private;
1653 struct mlx5_ind_table_ibv *ind_tbl;
1655 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1656 if ((ind_tbl->queues_n == queues_n) &&
1657 (memcmp(ind_tbl->queues, queues,
1658 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1665 rte_atomic32_inc(&ind_tbl->refcnt);
1666 for (i = 0; i != ind_tbl->queues_n; ++i)
1667 mlx5_rxq_get(dev, ind_tbl->queues[i]);
1673 * Release an indirection table.
1676 * Pointer to Ethernet device.
1678 * Indirection table to release.
1681 * 1 while a reference on it exists, 0 when freed.
1684 mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
1685 struct mlx5_ind_table_ibv *ind_tbl)
1689 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1690 claim_zero(mlx5_glue->destroy_rwq_ind_table
1691 (ind_tbl->ind_table));
1692 for (i = 0; i != ind_tbl->queues_n; ++i)
1693 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1694 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1695 LIST_REMOVE(ind_tbl, next);
1703 * Verify the Rx Queue list is empty
1706 * Pointer to Ethernet device.
1709 * The number of object not released.
1712 mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev)
1714 struct mlx5_priv *priv = dev->data->dev_private;
1715 struct mlx5_ind_table_ibv *ind_tbl;
1718 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1720 "port %u Verbs indirection table %p still referenced",
1721 dev->data->port_id, (void *)ind_tbl);
1728 * Create an Rx Hash queue.
1731 * Pointer to Ethernet device.
1733 * RSS key for the Rx hash queue.
1734 * @param rss_key_len
1736 * @param hash_fields
1737 * Verbs protocol hash field to make the RSS on.
1739 * Queues entering in hash queue. In case of empty hash_fields only the
1740 * first queue index will be taken for the indirection table.
1747 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1750 mlx5_hrxq_new(struct rte_eth_dev *dev,
1751 const uint8_t *rss_key, uint32_t rss_key_len,
1752 uint64_t hash_fields,
1753 const uint16_t *queues, uint32_t queues_n,
1754 int tunnel __rte_unused)
1756 struct mlx5_priv *priv = dev->data->dev_private;
1757 struct mlx5_hrxq *hrxq;
1758 struct mlx5_ind_table_ibv *ind_tbl;
1760 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1761 struct mlx5dv_qp_init_attr qp_init_attr;
1765 queues_n = hash_fields ? queues_n : 1;
1766 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1768 ind_tbl = mlx5_ind_table_ibv_new(dev, queues, queues_n);
1773 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1774 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
1776 qp_init_attr.comp_mask =
1777 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1778 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1780 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1781 if (dev->data->dev_conf.lpbk_mode) {
1782 /* Allow packet sent from NIC loop back w/o source MAC check. */
1783 qp_init_attr.comp_mask |=
1784 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1785 qp_init_attr.create_flags |=
1786 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1789 qp = mlx5_glue->dv_create_qp
1791 &(struct ibv_qp_init_attr_ex){
1792 .qp_type = IBV_QPT_RAW_PACKET,
1794 IBV_QP_INIT_ATTR_PD |
1795 IBV_QP_INIT_ATTR_IND_TABLE |
1796 IBV_QP_INIT_ATTR_RX_HASH,
1797 .rx_hash_conf = (struct ibv_rx_hash_conf){
1798 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1799 .rx_hash_key_len = rss_key_len,
1800 .rx_hash_key = (void *)(uintptr_t)rss_key,
1801 .rx_hash_fields_mask = hash_fields,
1803 .rwq_ind_tbl = ind_tbl->ind_table,
1808 qp = mlx5_glue->create_qp_ex
1810 &(struct ibv_qp_init_attr_ex){
1811 .qp_type = IBV_QPT_RAW_PACKET,
1813 IBV_QP_INIT_ATTR_PD |
1814 IBV_QP_INIT_ATTR_IND_TABLE |
1815 IBV_QP_INIT_ATTR_RX_HASH,
1816 .rx_hash_conf = (struct ibv_rx_hash_conf){
1817 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1818 .rx_hash_key_len = rss_key_len,
1819 .rx_hash_key = (void *)(uintptr_t)rss_key,
1820 .rx_hash_fields_mask = hash_fields,
1822 .rwq_ind_tbl = ind_tbl->ind_table,
1830 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1833 hrxq->ind_table = ind_tbl;
1835 hrxq->rss_key_len = rss_key_len;
1836 hrxq->hash_fields = hash_fields;
1837 memcpy(hrxq->rss_key, rss_key, rss_key_len);
1838 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1839 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
1840 if (!hrxq->action) {
1845 rte_atomic32_inc(&hrxq->refcnt);
1846 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1849 err = rte_errno; /* Save rte_errno before cleanup. */
1850 mlx5_ind_table_ibv_release(dev, ind_tbl);
1852 claim_zero(mlx5_glue->destroy_qp(qp));
1853 rte_errno = err; /* Restore rte_errno. */
1858 * Get an Rx Hash queue.
1861 * Pointer to Ethernet device.
1863 * RSS configuration for the Rx hash queue.
1865 * Queues entering in hash queue. In case of empty hash_fields only the
1866 * first queue index will be taken for the indirection table.
1871 * An hash Rx queue on success.
1874 mlx5_hrxq_get(struct rte_eth_dev *dev,
1875 const uint8_t *rss_key, uint32_t rss_key_len,
1876 uint64_t hash_fields,
1877 const uint16_t *queues, uint32_t queues_n)
1879 struct mlx5_priv *priv = dev->data->dev_private;
1880 struct mlx5_hrxq *hrxq;
1882 queues_n = hash_fields ? queues_n : 1;
1883 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1884 struct mlx5_ind_table_ibv *ind_tbl;
1886 if (hrxq->rss_key_len != rss_key_len)
1888 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1890 if (hrxq->hash_fields != hash_fields)
1892 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1895 if (ind_tbl != hrxq->ind_table) {
1896 mlx5_ind_table_ibv_release(dev, ind_tbl);
1899 rte_atomic32_inc(&hrxq->refcnt);
1906 * Release the hash Rx queue.
1909 * Pointer to Ethernet device.
1911 * Pointer to Hash Rx queue to release.
1914 * 1 while a reference on it exists, 0 when freed.
1917 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1919 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1920 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1921 mlx5_glue->destroy_flow_action(hrxq->action);
1923 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
1924 mlx5_ind_table_ibv_release(dev, hrxq->ind_table);
1925 LIST_REMOVE(hrxq, next);
1929 claim_nonzero(mlx5_ind_table_ibv_release(dev, hrxq->ind_table));
1934 * Verify the Rx Queue list is empty
1937 * Pointer to Ethernet device.
1940 * The number of object not released.
1943 mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev)
1945 struct mlx5_priv *priv = dev->data->dev_private;
1946 struct mlx5_hrxq *hrxq;
1949 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1951 "port %u Verbs hash Rx queue %p still referenced",
1952 dev->data->port_id, (void *)hrxq);
1959 * Create a drop Rx queue Verbs object.
1962 * Pointer to Ethernet device.
1965 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1967 struct mlx5_rxq_ibv *
1968 mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev)
1970 struct mlx5_priv *priv = dev->data->dev_private;
1971 struct ibv_context *ctx = priv->sh->ctx;
1973 struct ibv_wq *wq = NULL;
1974 struct mlx5_rxq_ibv *rxq;
1976 if (priv->drop_queue.rxq)
1977 return priv->drop_queue.rxq;
1978 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
1980 DEBUG("port %u cannot allocate CQ for drop queue",
1981 dev->data->port_id);
1985 wq = mlx5_glue->create_wq(ctx,
1986 &(struct ibv_wq_init_attr){
1987 .wq_type = IBV_WQT_RQ,
1994 DEBUG("port %u cannot allocate WQ for drop queue",
1995 dev->data->port_id);
1999 rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2001 DEBUG("port %u cannot allocate drop Rx queue memory",
2002 dev->data->port_id);
2008 priv->drop_queue.rxq = rxq;
2012 claim_zero(mlx5_glue->destroy_wq(wq));
2014 claim_zero(mlx5_glue->destroy_cq(cq));
2019 * Release a drop Rx queue Verbs object.
2022 * Pointer to Ethernet device.
2025 * The Verbs object initialised, NULL otherwise and rte_errno is set.
2028 mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev)
2030 struct mlx5_priv *priv = dev->data->dev_private;
2031 struct mlx5_rxq_ibv *rxq = priv->drop_queue.rxq;
2034 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2036 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2038 priv->drop_queue.rxq = NULL;
2042 * Create a drop indirection table.
2045 * Pointer to Ethernet device.
2048 * The Verbs object initialised, NULL otherwise and rte_errno is set.
2050 struct mlx5_ind_table_ibv *
2051 mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev)
2053 struct mlx5_priv *priv = dev->data->dev_private;
2054 struct mlx5_ind_table_ibv *ind_tbl;
2055 struct mlx5_rxq_ibv *rxq;
2056 struct mlx5_ind_table_ibv tmpl;
2058 rxq = mlx5_rxq_ibv_drop_new(dev);
2061 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2063 &(struct ibv_rwq_ind_table_init_attr){
2064 .log_ind_tbl_size = 0,
2065 .ind_tbl = &rxq->wq,
2068 if (!tmpl.ind_table) {
2069 DEBUG("port %u cannot allocate indirection table for drop"
2071 dev->data->port_id);
2075 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2080 ind_tbl->ind_table = tmpl.ind_table;
2083 mlx5_rxq_ibv_drop_release(dev);
2088 * Release a drop indirection table.
2091 * Pointer to Ethernet device.
2094 mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev)
2096 struct mlx5_priv *priv = dev->data->dev_private;
2097 struct mlx5_ind_table_ibv *ind_tbl = priv->drop_queue.hrxq->ind_table;
2099 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2100 mlx5_rxq_ibv_drop_release(dev);
2102 priv->drop_queue.hrxq->ind_table = NULL;
2106 * Create a drop Rx Hash queue.
2109 * Pointer to Ethernet device.
2112 * The Verbs object initialised, NULL otherwise and rte_errno is set.
2115 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2117 struct mlx5_priv *priv = dev->data->dev_private;
2118 struct mlx5_ind_table_ibv *ind_tbl;
2120 struct mlx5_hrxq *hrxq;
2122 if (priv->drop_queue.hrxq) {
2123 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2124 return priv->drop_queue.hrxq;
2126 ind_tbl = mlx5_ind_table_ibv_drop_new(dev);
2129 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2130 &(struct ibv_qp_init_attr_ex){
2131 .qp_type = IBV_QPT_RAW_PACKET,
2133 IBV_QP_INIT_ATTR_PD |
2134 IBV_QP_INIT_ATTR_IND_TABLE |
2135 IBV_QP_INIT_ATTR_RX_HASH,
2136 .rx_hash_conf = (struct ibv_rx_hash_conf){
2138 IBV_RX_HASH_FUNC_TOEPLITZ,
2139 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2140 .rx_hash_key = rss_hash_default_key,
2141 .rx_hash_fields_mask = 0,
2143 .rwq_ind_tbl = ind_tbl->ind_table,
2147 DEBUG("port %u cannot allocate QP for drop queue",
2148 dev->data->port_id);
2152 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2155 "port %u cannot allocate memory for drop queue",
2156 dev->data->port_id);
2160 hrxq->ind_table = ind_tbl;
2162 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2163 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2164 if (!hrxq->action) {
2169 priv->drop_queue.hrxq = hrxq;
2170 rte_atomic32_set(&hrxq->refcnt, 1);
2174 mlx5_ind_table_ibv_drop_release(dev);
2179 * Release a drop hash Rx queue.
2182 * Pointer to Ethernet device.
2185 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2187 struct mlx5_priv *priv = dev->data->dev_private;
2188 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2190 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2191 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2192 mlx5_glue->destroy_flow_action(hrxq->action);
2194 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2195 mlx5_ind_table_ibv_drop_release(dev);
2197 priv->drop_queue.hrxq = NULL;