drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  56               (unsigned int)sizeof(rss_hash_default_key),
  57               "wrong RSS default key size.");
  58
  59 /**
  60  * Check whether Multi-Packet RQ can be enabled for the device.
  61  *
  62  * @param dev
  63  *   Pointer to Ethernet device.
  64  *
  65  * @return
  66  *   1 if supported, negative errno value if not.
  67  */
  68 inline int
  69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  70 {
  71         struct mlx5_priv *priv = dev->data->dev_private;
  72
  73         if (priv->config.mprq.enabled &&
  74             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  75                 return 1;
  76         return -ENOTSUP;
  77 }
  78
  79 /**
  80  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  81  *
  82  *  @param rxq
  83  *     Pointer to receive queue structure.
  84  *
  85  * @return
  86  *   0 if disabled, otherwise enabled.
  87  */
  88 inline int
  89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  90 {
  91         return rxq->strd_num_n > 0;
  92 }
  93
  94 /**
  95  * Check whether Multi-Packet RQ is enabled for the device.
  96  *
  97  * @param dev
  98  *   Pointer to Ethernet device.
  99  *
 100  * @return
 101  *   0 if disabled, otherwise enabled.
 102  */
 103 inline int
 104 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 105 {
 106         struct mlx5_priv *priv = dev->data->dev_private;
 107         uint16_t i;
 108         uint16_t n = 0;
 109
 110         if (mlx5_check_mprq_support(dev) < 0)
 111                 return 0;
 112         /* All the configured queues should be enabled. */
 113         for (i = 0; i < priv->rxqs_n; ++i) {
 114                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 115
 116                 if (!rxq)
 117                         continue;
 118                 if (mlx5_rxq_mprq_enabled(rxq))
 119                         ++n;
 120         }
 121         /* Multi-Packet RQ can't be partially configured. */
 122         assert(n == 0 || n == priv->rxqs_n);
 123         return n == priv->rxqs_n;
 124 }
 125
 126 /**
 127  * Allocate RX queue elements for Multi-Packet RQ.
 128  *
 129  * @param rxq_ctrl
 130  *   Pointer to RX queue structure.
 131  *
 132  * @return
 133  *   0 on success, a negative errno value otherwise and rte_errno is set.
 134  */
 135 static int
 136 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 137 {
 138         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 139         unsigned int wqe_n = 1 << rxq->elts_n;
 140         unsigned int i;
 141         int err;
 142
 143         /* Iterate on segments. */
 144         for (i = 0; i <= wqe_n; ++i) {
 145                 struct mlx5_mprq_buf *buf;
 146
 147                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 148                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 149                         rte_errno = ENOMEM;
 150                         goto error;
 151                 }
 152                 if (i < wqe_n)
 153                         (*rxq->mprq_bufs)[i] = buf;
 154                 else
 155                         rxq->mprq_repl = buf;
 156         }
 157         DRV_LOG(DEBUG,
 158                 "port %u Rx queue %u allocated and configured %u segments",
 159                 rxq->port_id, rxq->idx, wqe_n);
 160         return 0;
 161 error:
 162         err = rte_errno; /* Save rte_errno before cleanup. */
 163         wqe_n = i;
 164         for (i = 0; (i != wqe_n); ++i) {
 165                 if ((*rxq->mprq_bufs)[i] != NULL)
 166                         rte_mempool_put(rxq->mprq_mp,
 167                                         (*rxq->mprq_bufs)[i]);
 168                 (*rxq->mprq_bufs)[i] = NULL;
 169         }
 170         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 171                 rxq->port_id, rxq->idx);
 172         rte_errno = err; /* Restore rte_errno. */
 173         return -rte_errno;
 174 }
 175
 176 /**
 177  * Allocate RX queue elements for Single-Packet RQ.
 178  *
 179  * @param rxq_ctrl
 180  *   Pointer to RX queue structure.
 181  *
 182  * @return
 183  *   0 on success, errno value on failure.
 184  */
 185 static int
 186 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 187 {
 188         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 189         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 190         unsigned int i;
 191         int err;
 192
 193         /* Iterate on segments. */
 194         for (i = 0; (i != elts_n); ++i) {
 195                 struct rte_mbuf *buf;
 196
 197                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 198                 if (buf == NULL) {
 199                         DRV_LOG(ERR, "port %u empty mbuf pool",
 200                                 PORT_ID(rxq_ctrl->priv));
 201                         rte_errno = ENOMEM;
 202                         goto error;
 203                 }
 204                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 205                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 206                 /* Buffer is supposed to be empty. */
 207                 assert(rte_pktmbuf_data_len(buf) == 0);
 208                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 209                 assert(!buf->next);
 210                 /* Only the first segment keeps headroom. */
 211                 if (i % sges_n)
 212                         SET_DATA_OFF(buf, 0);
 213                 PORT(buf) = rxq_ctrl->rxq.port_id;
 214                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 215                 PKT_LEN(buf) = DATA_LEN(buf);
 216                 NB_SEGS(buf) = 1;
 217                 (*rxq_ctrl->rxq.elts)[i] = buf;
 218         }
 219         /* If Rx vector is activated. */
 220         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 221                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 222                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 223                 int j;
 224
 225                 /* Initialize default rearm_data for vPMD. */
 226                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 227                 rte_mbuf_refcnt_set(mbuf_init, 1);
 228                 mbuf_init->nb_segs = 1;
 229                 mbuf_init->port = rxq->port_id;
 230                 /*
 231                  * prevent compiler reordering:
 232                  * rearm_data covers previous fields.
 233                  */
 234                 rte_compiler_barrier();
 235                 rxq->mbuf_initializer =
 236                         *(uint64_t *)&mbuf_init->rearm_data;
 237                 /* Padding with a fake mbuf for vectorized Rx. */
 238                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 239                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 240         }
 241         DRV_LOG(DEBUG,
 242                 "port %u Rx queue %u allocated and configured %u segments"
 243                 " (max %u packets)",
 244                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 245                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 246         return 0;
 247 error:
 248         err = rte_errno; /* Save rte_errno before cleanup. */
 249         elts_n = i;
 250         for (i = 0; (i != elts_n); ++i) {
 251                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 252                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 253                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 254         }
 255         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 256                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 257         rte_errno = err; /* Restore rte_errno. */
 258         return -rte_errno;
 259 }
 260
 261 /**
 262  * Allocate RX queue elements.
 263  *
 264  * @param rxq_ctrl
 265  *   Pointer to RX queue structure.
 266  *
 267  * @return
 268  *   0 on success, errno value on failure.
 269  */
 270 int
 271 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 272 {
 273         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 274                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 275 }
 276
 277 /**
 278  * Free RX queue elements for Multi-Packet RQ.
 279  *
 280  * @param rxq_ctrl
 281  *   Pointer to RX queue structure.
 282  */
 283 static void
 284 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 285 {
 286         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 287         uint16_t i;
 288
 289         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 290                 rxq->port_id, rxq->idx);
 291         if (rxq->mprq_bufs == NULL)
 292                 return;
 293         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 294         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 295                 if ((*rxq->mprq_bufs)[i] != NULL)
 296                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 297                 (*rxq->mprq_bufs)[i] = NULL;
 298         }
 299         if (rxq->mprq_repl != NULL) {
 300                 mlx5_mprq_buf_free(rxq->mprq_repl);
 301                 rxq->mprq_repl = NULL;
 302         }
 303 }
 304
 305 /**
 306  * Free RX queue elements for Single-Packet RQ.
 307  *
 308  * @param rxq_ctrl
 309  *   Pointer to RX queue structure.
 310  */
 311 static void
 312 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 313 {
 314         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 315         const uint16_t q_n = (1 << rxq->elts_n);
 316         const uint16_t q_mask = q_n - 1;
 317         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 318         uint16_t i;
 319
 320         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 321                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 322         if (rxq->elts == NULL)
 323                 return;
 324         /**
 325          * Some mbuf in the Ring belongs to the application.  They cannot be
 326          * freed.
 327          */
 328         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 329                 for (i = 0; i < used; ++i)
 330                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 331                 rxq->rq_pi = rxq->rq_ci;
 332         }
 333         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 334                 if ((*rxq->elts)[i] != NULL)
 335                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 336                 (*rxq->elts)[i] = NULL;
 337         }
 338 }
 339
 340 /**
 341  * Free RX queue elements.
 342  *
 343  * @param rxq_ctrl
 344  *   Pointer to RX queue structure.
 345  */
 346 static void
 347 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 348 {
 349         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 350                 rxq_free_elts_mprq(rxq_ctrl);
 351         else
 352                 rxq_free_elts_sprq(rxq_ctrl);
 353 }
 354
 355 /**
 356  * Returns the per-queue supported offloads.
 357  *
 358  * @param dev
 359  *   Pointer to Ethernet device.
 360  *
 361  * @return
 362  *   Supported Rx offloads.
 363  */
 364 uint64_t
 365 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 366 {
 367         struct mlx5_priv *priv = dev->data->dev_private;
 368         struct mlx5_dev_config *config = &priv->config;
 369         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 370                              DEV_RX_OFFLOAD_TIMESTAMP |
 371                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 372
 373         if (config->hw_fcs_strip)
 374                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 375
 376         if (config->hw_csum)
 377                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 378                              DEV_RX_OFFLOAD_UDP_CKSUM |
 379                              DEV_RX_OFFLOAD_TCP_CKSUM);
 380         if (config->hw_vlan_strip)
 381                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 382         return offloads;
 383 }
 384
 385
 386 /**
 387  * Returns the per-port supported offloads.
 388  *
 389  * @return
 390  *   Supported Rx offloads.
 391  */
 392 uint64_t
 393 mlx5_get_rx_port_offloads(void)
 394 {
 395         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 396
 397         return offloads;
 398 }
 399
 400 /**
 401  *
 402  * @param dev
 403  *   Pointer to Ethernet device structure.
 404  * @param idx
 405  *   RX queue index.
 406  * @param desc
 407  *   Number of descriptors to configure in queue.
 408  * @param socket
 409  *   NUMA socket on which memory must be allocated.
 410  * @param[in] conf
 411  *   Thresholds parameters.
 412  * @param mp
 413  *   Memory pool for buffer allocations.
 414  *
 415  * @return
 416  *   0 on success, a negative errno value otherwise and rte_errno is set.
 417  */
 418 int
 419 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 420                     unsigned int socket, const struct rte_eth_rxconf *conf,
 421                     struct rte_mempool *mp)
 422 {
 423         struct mlx5_priv *priv = dev->data->dev_private;
 424         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 425         struct mlx5_rxq_ctrl *rxq_ctrl =
 426                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 427
 428         if (!rte_is_power_of_2(desc)) {
 429                 desc = 1 << log2above(desc);
 430                 DRV_LOG(WARNING,
 431                         "port %u increased number of descriptors in Rx queue %u"
 432                         " to the next power of two (%d)",
 433                         dev->data->port_id, idx, desc);
 434         }
 435         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 436                 dev->data->port_id, idx, desc);
 437         if (idx >= priv->rxqs_n) {
 438                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 439                         dev->data->port_id, idx, priv->rxqs_n);
 440                 rte_errno = EOVERFLOW;
 441                 return -rte_errno;
 442         }
 443         if (!mlx5_rxq_releasable(dev, idx)) {
 444                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 445                         dev->data->port_id, idx);
 446                 rte_errno = EBUSY;
 447                 return -rte_errno;
 448         }
 449         mlx5_rxq_release(dev, idx);
 450         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 451         if (!rxq_ctrl) {
 452                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 453                         dev->data->port_id, idx);
 454                 rte_errno = ENOMEM;
 455                 return -rte_errno;
 456         }
 457         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 458                 dev->data->port_id, idx);
 459         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 460         return 0;
 461 }
 462
 463 /**
 464  * DPDK callback to release a RX queue.
 465  *
 466  * @param dpdk_rxq
 467  *   Generic RX queue pointer.
 468  */
 469 void
 470 mlx5_rx_queue_release(void *dpdk_rxq)
 471 {
 472         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 473         struct mlx5_rxq_ctrl *rxq_ctrl;
 474         struct mlx5_priv *priv;
 475
 476         if (rxq == NULL)
 477                 return;
 478         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 479         priv = rxq_ctrl->priv;
 480         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 481                 rte_panic("port %u Rx queue %u is still used by a flow and"
 482                           " cannot be removed\n",
 483                           PORT_ID(priv), rxq->idx);
 484         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 485 }
 486
 487 /**
 488  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 489  *
 490  * @param dev
 491  *   Pointer to Ethernet device.
 492  *
 493  * @return
 494  *   0 on success, a negative errno value otherwise and rte_errno is set.
 495  */
 496 int
 497 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 498 {
 499         struct mlx5_priv *priv = dev->data->dev_private;
 500         unsigned int i;
 501         unsigned int rxqs_n = priv->rxqs_n;
 502         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 503         unsigned int count = 0;
 504         struct rte_intr_handle *intr_handle = dev->intr_handle;
 505
 506         if (!dev->data->dev_conf.intr_conf.rxq)
 507                 return 0;
 508         mlx5_rx_intr_vec_disable(dev);
 509         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 510         if (intr_handle->intr_vec == NULL) {
 511                 DRV_LOG(ERR,
 512                         "port %u failed to allocate memory for interrupt"
 513                         " vector, Rx interrupts will not be supported",
 514                         dev->data->port_id);
 515                 rte_errno = ENOMEM;
 516                 return -rte_errno;
 517         }
 518         intr_handle->type = RTE_INTR_HANDLE_EXT;
 519         for (i = 0; i != n; ++i) {
 520                 /* This rxq ibv must not be released in this function. */
 521                 struct mlx5_rxq_ibv *rxq_ibv = mlx5_rxq_ibv_get(dev, i);
 522                 int fd;
 523                 int flags;
 524                 int rc;
 525
 526                 /* Skip queues that cannot request interrupts. */
 527                 if (!rxq_ibv || !rxq_ibv->channel) {
 528                         /* Use invalid intr_vec[] index to disable entry. */
 529                         intr_handle->intr_vec[i] =
 530                                 RTE_INTR_VEC_RXTX_OFFSET +
 531                                 RTE_MAX_RXTX_INTR_VEC_ID;
 532                         continue;
 533                 }
 534                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 535                         DRV_LOG(ERR,
 536                                 "port %u too many Rx queues for interrupt"
 537                                 " vector size (%d), Rx interrupts cannot be"
 538                                 " enabled",
 539                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 540                         mlx5_rx_intr_vec_disable(dev);
 541                         rte_errno = ENOMEM;
 542                         return -rte_errno;
 543                 }
 544                 fd = rxq_ibv->channel->fd;
 545                 flags = fcntl(fd, F_GETFL);
 546                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 547                 if (rc < 0) {
 548                         rte_errno = errno;
 549                         DRV_LOG(ERR,
 550                                 "port %u failed to make Rx interrupt file"
 551                                 " descriptor %d non-blocking for queue index"
 552                                 " %d",
 553                                 dev->data->port_id, fd, i);
 554                         mlx5_rx_intr_vec_disable(dev);
 555                         return -rte_errno;
 556                 }
 557                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 558                 intr_handle->efds[count] = fd;
 559                 count++;
 560         }
 561         if (!count)
 562                 mlx5_rx_intr_vec_disable(dev);
 563         else
 564                 intr_handle->nb_efd = count;
 565         return 0;
 566 }
 567
 568 /**
 569  * Clean up Rx interrupts handler.
 570  *
 571  * @param dev
 572  *   Pointer to Ethernet device.
 573  */
 574 void
 575 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 576 {
 577         struct mlx5_priv *priv = dev->data->dev_private;
 578         struct rte_intr_handle *intr_handle = dev->intr_handle;
 579         unsigned int i;
 580         unsigned int rxqs_n = priv->rxqs_n;
 581         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 582
 583         if (!dev->data->dev_conf.intr_conf.rxq)
 584                 return;
 585         if (!intr_handle->intr_vec)
 586                 goto free;
 587         for (i = 0; i != n; ++i) {
 588                 struct mlx5_rxq_ctrl *rxq_ctrl;
 589                 struct mlx5_rxq_data *rxq_data;
 590
 591                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 592                     RTE_MAX_RXTX_INTR_VEC_ID)
 593                         continue;
 594                 /**
 595                  * Need to access directly the queue to release the reference
 596                  * kept in priv_rx_intr_vec_enable().
 597                  */
 598                 rxq_data = (*priv->rxqs)[i];
 599                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 600                 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
 601         }
 602 free:
 603         rte_intr_free_epoll_fd(intr_handle);
 604         if (intr_handle->intr_vec)
 605                 free(intr_handle->intr_vec);
 606         intr_handle->nb_efd = 0;
 607         intr_handle->intr_vec = NULL;
 608 }
 609
 610 /**
 611  *  MLX5 CQ notification .
 612  *
 613  *  @param rxq
 614  *     Pointer to receive queue structure.
 615  *  @param sq_n_rxq
 616  *     Sequence number per receive queue .
 617  */
 618 static inline void
 619 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 620 {
 621         int sq_n = 0;
 622         uint32_t doorbell_hi;
 623         uint64_t doorbell;
 624         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 625
 626         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 627         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 628         doorbell = (uint64_t)doorbell_hi << 32;
 629         doorbell |=  rxq->cqn;
 630         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 631         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 632                          cq_db_reg, rxq->uar_lock_cq);
 633 }
 634
 635 /**
 636  * DPDK callback for Rx queue interrupt enable.
 637  *
 638  * @param dev
 639  *   Pointer to Ethernet device structure.
 640  * @param rx_queue_id
 641  *   Rx queue number.
 642  *
 643  * @return
 644  *   0 on success, a negative errno value otherwise and rte_errno is set.
 645  */
 646 int
 647 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 648 {
 649         struct mlx5_priv *priv = dev->data->dev_private;
 650         struct mlx5_rxq_data *rxq_data;
 651         struct mlx5_rxq_ctrl *rxq_ctrl;
 652
 653         rxq_data = (*priv->rxqs)[rx_queue_id];
 654         if (!rxq_data) {
 655                 rte_errno = EINVAL;
 656                 return -rte_errno;
 657         }
 658         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 659         if (rxq_ctrl->irq) {
 660                 struct mlx5_rxq_ibv *rxq_ibv;
 661
 662                 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 663                 if (!rxq_ibv) {
 664                         rte_errno = EINVAL;
 665                         return -rte_errno;
 666                 }
 667                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 668                 mlx5_rxq_ibv_release(rxq_ibv);
 669         }
 670         return 0;
 671 }
 672
 673 /**
 674  * DPDK callback for Rx queue interrupt disable.
 675  *
 676  * @param dev
 677  *   Pointer to Ethernet device structure.
 678  * @param rx_queue_id
 679  *   Rx queue number.
 680  *
 681  * @return
 682  *   0 on success, a negative errno value otherwise and rte_errno is set.
 683  */
 684 int
 685 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 686 {
 687         struct mlx5_priv *priv = dev->data->dev_private;
 688         struct mlx5_rxq_data *rxq_data;
 689         struct mlx5_rxq_ctrl *rxq_ctrl;
 690         struct mlx5_rxq_ibv *rxq_ibv = NULL;
 691         struct ibv_cq *ev_cq;
 692         void *ev_ctx;
 693         int ret;
 694
 695         rxq_data = (*priv->rxqs)[rx_queue_id];
 696         if (!rxq_data) {
 697                 rte_errno = EINVAL;
 698                 return -rte_errno;
 699         }
 700         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 701         if (!rxq_ctrl->irq)
 702                 return 0;
 703         rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 704         if (!rxq_ibv) {
 705                 rte_errno = EINVAL;
 706                 return -rte_errno;
 707         }
 708         ret = mlx5_glue->get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
 709         if (ret || ev_cq != rxq_ibv->cq) {
 710                 rte_errno = EINVAL;
 711                 goto exit;
 712         }
 713         rxq_data->cq_arm_sn++;
 714         mlx5_glue->ack_cq_events(rxq_ibv->cq, 1);
 715         mlx5_rxq_ibv_release(rxq_ibv);
 716         return 0;
 717 exit:
 718         ret = rte_errno; /* Save rte_errno before cleanup. */
 719         if (rxq_ibv)
 720                 mlx5_rxq_ibv_release(rxq_ibv);
 721         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 722                 dev->data->port_id, rx_queue_id);
 723         rte_errno = ret; /* Restore rte_errno. */
 724         return -rte_errno;
 725 }
 726
 727 /**
 728  * Create the Rx queue Verbs object.
 729  *
 730  * @param dev
 731  *   Pointer to Ethernet device.
 732  * @param idx
 733  *   Queue index in DPDK Rx queue array
 734  *
 735  * @return
 736  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 737  */
 738 struct mlx5_rxq_ibv *
 739 mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
 740 {
 741         struct mlx5_priv *priv = dev->data->dev_private;
 742         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 743         struct mlx5_rxq_ctrl *rxq_ctrl =
 744                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 745         struct ibv_wq_attr mod;
 746         union {
 747                 struct {
 748                         struct ibv_cq_init_attr_ex ibv;
 749                         struct mlx5dv_cq_init_attr mlx5;
 750                 } cq;
 751                 struct {
 752                         struct ibv_wq_init_attr ibv;
 753 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 754                         struct mlx5dv_wq_init_attr mlx5;
 755 #endif
 756                 } wq;
 757                 struct ibv_cq_ex cq_attr;
 758         } attr;
 759         unsigned int cqe_n;
 760         unsigned int wqe_n = 1 << rxq_data->elts_n;
 761         struct mlx5_rxq_ibv *tmpl;
 762         struct mlx5dv_cq cq_info;
 763         struct mlx5dv_rwq rwq;
 764         unsigned int i;
 765         int ret = 0;
 766         struct mlx5dv_obj obj;
 767         struct mlx5_dev_config *config = &priv->config;
 768         const int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);
 769
 770         assert(rxq_data);
 771         assert(!rxq_ctrl->ibv);
 772         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
 773         priv->verbs_alloc_ctx.obj = rxq_ctrl;
 774         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
 775                                  rxq_ctrl->socket);
 776         if (!tmpl) {
 777                 DRV_LOG(ERR,
 778                         "port %u Rx queue %u cannot allocate verbs resources",
 779                         dev->data->port_id, rxq_data->idx);
 780                 rte_errno = ENOMEM;
 781                 goto error;
 782         }
 783         tmpl->rxq_ctrl = rxq_ctrl;
 784         if (rxq_ctrl->irq) {
 785                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
 786                 if (!tmpl->channel) {
 787                         DRV_LOG(ERR, "port %u: comp channel creation failure",
 788                                 dev->data->port_id);
 789                         rte_errno = ENOMEM;
 790                         goto error;
 791                 }
 792         }
 793         if (mprq_en)
 794                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
 795         else
 796                 cqe_n = wqe_n  - 1;
 797         attr.cq.ibv = (struct ibv_cq_init_attr_ex){
 798                 .cqe = cqe_n,
 799                 .channel = tmpl->channel,
 800                 .comp_mask = 0,
 801         };
 802         attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
 803                 .comp_mask = 0,
 804         };
 805         if (config->cqe_comp && !rxq_data->hw_timestamp) {
 806                 attr.cq.mlx5.comp_mask |=
 807                         MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 808 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 809                 attr.cq.mlx5.cqe_comp_res_format =
 810                         mprq_en ? MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 811                                   MLX5DV_CQE_RES_FORMAT_HASH;
 812 #else
 813                 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 814 #endif
 815                 /*
 816                  * For vectorized Rx, it must not be doubled in order to
 817                  * make cq_ci and rq_ci aligned.
 818                  */
 819                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 820                         attr.cq.ibv.cqe *= 2;
 821         } else if (config->cqe_comp && rxq_data->hw_timestamp) {
 822                 DRV_LOG(DEBUG,
 823                         "port %u Rx CQE compression is disabled for HW"
 824                         " timestamp",
 825                         dev->data->port_id);
 826         }
 827 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
 828         if (config->cqe_pad) {
 829                 attr.cq.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
 830                 attr.cq.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
 831         }
 832 #endif
 833         tmpl->cq = mlx5_glue->cq_ex_to_cq
 834                 (mlx5_glue->dv_create_cq(priv->sh->ctx, &attr.cq.ibv,
 835                                          &attr.cq.mlx5));
 836         if (tmpl->cq == NULL) {
 837                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
 838                         dev->data->port_id, idx);
 839                 rte_errno = ENOMEM;
 840                 goto error;
 841         }
 842         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
 843                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
 844         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
 845                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
 846         attr.wq.ibv = (struct ibv_wq_init_attr){
 847                 .wq_context = NULL, /* Could be useful in the future. */
 848                 .wq_type = IBV_WQT_RQ,
 849                 /* Max number of outstanding WRs. */
 850                 .max_wr = wqe_n >> rxq_data->sges_n,
 851                 /* Max number of scatter/gather elements in a WR. */
 852                 .max_sge = 1 << rxq_data->sges_n,
 853                 .pd = priv->sh->pd,
 854                 .cq = tmpl->cq,
 855                 .comp_mask =
 856                         IBV_WQ_FLAGS_CVLAN_STRIPPING |
 857                         0,
 858                 .create_flags = (rxq_data->vlan_strip ?
 859                                  IBV_WQ_FLAGS_CVLAN_STRIPPING :
 860                                  0),
 861         };
 862         /* By default, FCS (CRC) is stripped by hardware. */
 863         if (rxq_data->crc_present) {
 864                 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 865                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 866         }
 867         if (config->hw_padding) {
 868 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
 869                 attr.wq.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 870                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 871 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
 872                 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
 873                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 874 #endif
 875         }
 876 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 877         attr.wq.mlx5 = (struct mlx5dv_wq_init_attr){
 878                 .comp_mask = 0,
 879         };
 880         if (mprq_en) {
 881                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
 882                         &attr.wq.mlx5.striding_rq_attrs;
 883
 884                 attr.wq.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
 885                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
 886                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
 887                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
 888                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
 889                 };
 890         }
 891         tmpl->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &attr.wq.ibv,
 892                                            &attr.wq.mlx5);
 893 #else
 894         tmpl->wq = mlx5_glue->create_wq(priv->sh->ctx, &attr.wq.ibv);
 895 #endif
 896         if (tmpl->wq == NULL) {
 897                 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
 898                         dev->data->port_id, idx);
 899                 rte_errno = ENOMEM;
 900                 goto error;
 901         }
 902         /*
 903          * Make sure number of WRs*SGEs match expectations since a queue
 904          * cannot allocate more than "desc" buffers.
 905          */
 906         if (attr.wq.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
 907             attr.wq.ibv.max_sge != (1u << rxq_data->sges_n)) {
 908                 DRV_LOG(ERR,
 909                         "port %u Rx queue %u requested %u*%u but got %u*%u"
 910                         " WRs*SGEs",
 911                         dev->data->port_id, idx,
 912                         wqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),
 913                         attr.wq.ibv.max_wr, attr.wq.ibv.max_sge);
 914                 rte_errno = EINVAL;
 915                 goto error;
 916         }
 917         /* Change queue state to ready. */
 918         mod = (struct ibv_wq_attr){
 919                 .attr_mask = IBV_WQ_ATTR_STATE,
 920                 .wq_state = IBV_WQS_RDY,
 921         };
 922         ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
 923         if (ret) {
 924                 DRV_LOG(ERR,
 925                         "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
 926                         dev->data->port_id, idx);
 927                 rte_errno = ret;
 928                 goto error;
 929         }
 930         obj.cq.in = tmpl->cq;
 931         obj.cq.out = &cq_info;
 932         obj.rwq.in = tmpl->wq;
 933         obj.rwq.out = &rwq;
 934         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
 935         if (ret) {
 936                 rte_errno = ret;
 937                 goto error;
 938         }
 939         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
 940                 DRV_LOG(ERR,
 941                         "port %u wrong MLX5_CQE_SIZE environment variable"
 942                         " value: it should be set to %u",
 943                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
 944                 rte_errno = EINVAL;
 945                 goto error;
 946         }
 947         /* Fill the rings. */
 948         rxq_data->wqes = rwq.buf;
 949         for (i = 0; (i != wqe_n); ++i) {
 950                 volatile struct mlx5_wqe_data_seg *scat;
 951                 uintptr_t addr;
 952                 uint32_t byte_count;
 953
 954                 if (mprq_en) {
 955                         struct mlx5_mprq_buf *buf = (*rxq_data->mprq_bufs)[i];
 956
 957                         scat = &((volatile struct mlx5_wqe_mprq *)
 958                                  rxq_data->wqes)[i].dseg;
 959                         addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
 960                         byte_count = (1 << rxq_data->strd_sz_n) *
 961                                      (1 << rxq_data->strd_num_n);
 962                 } else {
 963                         struct rte_mbuf *buf = (*rxq_data->elts)[i];
 964
 965                         scat = &((volatile struct mlx5_wqe_data_seg *)
 966                                  rxq_data->wqes)[i];
 967                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 968                         byte_count = DATA_LEN(buf);
 969                 }
 970                 /* scat->addr must be able to store a pointer. */
 971                 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
 972                 *scat = (struct mlx5_wqe_data_seg){
 973                         .addr = rte_cpu_to_be_64(addr),
 974                         .byte_count = rte_cpu_to_be_32(byte_count),
 975                         .lkey = mlx5_rx_addr2mr(rxq_data, addr),
 976                 };
 977         }
 978         rxq_data->rq_db = rwq.dbrec;
 979         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
 980         rxq_data->cq_ci = 0;
 981         rxq_data->consumed_strd = 0;
 982         rxq_data->rq_pi = 0;
 983         rxq_data->zip = (struct rxq_zip){
 984                 .ai = 0,
 985         };
 986         rxq_data->cq_db = cq_info.dbrec;
 987         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
 988         rxq_data->cq_uar = cq_info.cq_uar;
 989         rxq_data->cqn = cq_info.cqn;
 990         rxq_data->cq_arm_sn = 0;
 991         /* Update doorbell counter. */
 992         rxq_data->rq_ci = wqe_n >> rxq_data->sges_n;
 993         rte_wmb();
 994         *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
 995         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
 996                 idx, (void *)&tmpl);
 997         rte_atomic32_inc(&tmpl->refcnt);
 998         LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
 999         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1000         return tmpl;
1001 error:
1002         ret = rte_errno; /* Save rte_errno before cleanup. */
1003         if (tmpl->wq)
1004                 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1005         if (tmpl->cq)
1006                 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1007         if (tmpl->channel)
1008                 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->channel));
1009         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1010         rte_errno = ret; /* Restore rte_errno. */
1011         return NULL;
1012 }
1013
1014 /**
1015  * Get an Rx queue Verbs object.
1016  *
1017  * @param dev
1018  *   Pointer to Ethernet device.
1019  * @param idx
1020  *   Queue index in DPDK Rx queue array
1021  *
1022  * @return
1023  *   The Verbs object if it exists.
1024  */
1025 struct mlx5_rxq_ibv *
1026 mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
1027 {
1028         struct mlx5_priv *priv = dev->data->dev_private;
1029         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1030         struct mlx5_rxq_ctrl *rxq_ctrl;
1031
1032         if (idx >= priv->rxqs_n)
1033                 return NULL;
1034         if (!rxq_data)
1035                 return NULL;
1036         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1037         if (rxq_ctrl->ibv) {
1038                 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
1039         }
1040         return rxq_ctrl->ibv;
1041 }
1042
1043 /**
1044  * Release an Rx verbs queue object.
1045  *
1046  * @param rxq_ibv
1047  *   Verbs Rx queue object.
1048  *
1049  * @return
1050  *   1 while a reference on it exists, 0 when freed.
1051  */
1052 int
1053 mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv)
1054 {
1055         assert(rxq_ibv);
1056         assert(rxq_ibv->wq);
1057         assert(rxq_ibv->cq);
1058         if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
1059                 rxq_free_elts(rxq_ibv->rxq_ctrl);
1060                 claim_zero(mlx5_glue->destroy_wq(rxq_ibv->wq));
1061                 claim_zero(mlx5_glue->destroy_cq(rxq_ibv->cq));
1062                 if (rxq_ibv->channel)
1063                         claim_zero(mlx5_glue->destroy_comp_channel
1064                                    (rxq_ibv->channel));
1065                 LIST_REMOVE(rxq_ibv, next);
1066                 rte_free(rxq_ibv);
1067                 return 0;
1068         }
1069         return 1;
1070 }
1071
1072 /**
1073  * Verify the Verbs Rx queue list is empty
1074  *
1075  * @param dev
1076  *   Pointer to Ethernet device.
1077  *
1078  * @return
1079  *   The number of object not released.
1080  */
1081 int
1082 mlx5_rxq_ibv_verify(struct rte_eth_dev *dev)
1083 {
1084         struct mlx5_priv *priv = dev->data->dev_private;
1085         int ret = 0;
1086         struct mlx5_rxq_ibv *rxq_ibv;
1087
1088         LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
1089                 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u still referenced",
1090                         dev->data->port_id, rxq_ibv->rxq_ctrl->rxq.idx);
1091                 ++ret;
1092         }
1093         return ret;
1094 }
1095
1096 /**
1097  * Callback function to initialize mbufs for Multi-Packet RQ.
1098  */
1099 static inline void
1100 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1101                     void *_m, unsigned int i __rte_unused)
1102 {
1103         struct mlx5_mprq_buf *buf = _m;
1104
1105         memset(_m, 0, sizeof(*buf));
1106         buf->mp = mp;
1107         rte_atomic16_set(&buf->refcnt, 1);
1108 }
1109
1110 /**
1111  * Free mempool of Multi-Packet RQ.
1112  *
1113  * @param dev
1114  *   Pointer to Ethernet device.
1115  *
1116  * @return
1117  *   0 on success, negative errno value on failure.
1118  */
1119 int
1120 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1121 {
1122         struct mlx5_priv *priv = dev->data->dev_private;
1123         struct rte_mempool *mp = priv->mprq_mp;
1124         unsigned int i;
1125
1126         if (mp == NULL)
1127                 return 0;
1128         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1129                 dev->data->port_id, mp->name);
1130         /*
1131          * If a buffer in the pool has been externally attached to a mbuf and it
1132          * is still in use by application, destroying the Rx qeueue can spoil
1133          * the packet. It is unlikely to happen but if application dynamically
1134          * creates and destroys with holding Rx packets, this can happen.
1135          *
1136          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1137          * RQ isn't provided by application but managed by PMD.
1138          */
1139         if (!rte_mempool_full(mp)) {
1140                 DRV_LOG(ERR,
1141                         "port %u mempool for Multi-Packet RQ is still in use",
1142                         dev->data->port_id);
1143                 rte_errno = EBUSY;
1144                 return -rte_errno;
1145         }
1146         rte_mempool_free(mp);
1147         /* Unset mempool for each Rx queue. */
1148         for (i = 0; i != priv->rxqs_n; ++i) {
1149                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1150
1151                 if (rxq == NULL)
1152                         continue;
1153                 rxq->mprq_mp = NULL;
1154         }
1155         priv->mprq_mp = NULL;
1156         return 0;
1157 }
1158
1159 /**
1160  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1161  * mempool. If already allocated, reuse it if there're enough elements.
1162  * Otherwise, resize it.
1163  *
1164  * @param dev
1165  *   Pointer to Ethernet device.
1166  *
1167  * @return
1168  *   0 on success, negative errno value on failure.
1169  */
1170 int
1171 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1172 {
1173         struct mlx5_priv *priv = dev->data->dev_private;
1174         struct rte_mempool *mp = priv->mprq_mp;
1175         char name[RTE_MEMPOOL_NAMESIZE];
1176         unsigned int desc = 0;
1177         unsigned int buf_len;
1178         unsigned int obj_num;
1179         unsigned int obj_size;
1180         unsigned int strd_num_n = 0;
1181         unsigned int strd_sz_n = 0;
1182         unsigned int i;
1183
1184         if (!mlx5_mprq_enabled(dev))
1185                 return 0;
1186         /* Count the total number of descriptors configured. */
1187         for (i = 0; i != priv->rxqs_n; ++i) {
1188                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1189
1190                 if (rxq == NULL)
1191                         continue;
1192                 desc += 1 << rxq->elts_n;
1193                 /* Get the max number of strides. */
1194                 if (strd_num_n < rxq->strd_num_n)
1195                         strd_num_n = rxq->strd_num_n;
1196                 /* Get the max size of a stride. */
1197                 if (strd_sz_n < rxq->strd_sz_n)
1198                         strd_sz_n = rxq->strd_sz_n;
1199         }
1200         assert(strd_num_n && strd_sz_n);
1201         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1202         obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1203         /*
1204          * Received packets can be either memcpy'd or externally referenced. In
1205          * case that the packet is attached to an mbuf as an external buffer, as
1206          * it isn't possible to predict how the buffers will be queued by
1207          * application, there's no option to exactly pre-allocate needed buffers
1208          * in advance but to speculatively prepares enough buffers.
1209          *
1210          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1211          * received packets to buffers provided by application (rxq->mp) until
1212          * this Mempool gets available again.
1213          */
1214         desc *= 4;
1215         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1216         /*
1217          * rte_mempool_create_empty() has sanity check to refuse large cache
1218          * size compared to the number of elements.
1219          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1220          * constant number 2 instead.
1221          */
1222         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1223         /* Check a mempool is already allocated and if it can be resued. */
1224         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1225                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1226                         dev->data->port_id, mp->name);
1227                 /* Reuse. */
1228                 goto exit;
1229         } else if (mp != NULL) {
1230                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1231                         dev->data->port_id, mp->name);
1232                 /*
1233                  * If failed to free, which means it may be still in use, no way
1234                  * but to keep using the existing one. On buffer underrun,
1235                  * packets will be memcpy'd instead of external buffer
1236                  * attachment.
1237                  */
1238                 if (mlx5_mprq_free_mp(dev)) {
1239                         if (mp->elt_size >= obj_size)
1240                                 goto exit;
1241                         else
1242                                 return -rte_errno;
1243                 }
1244         }
1245         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1246         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1247                                 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1248                                 dev->device->numa_node, 0);
1249         if (mp == NULL) {
1250                 DRV_LOG(ERR,
1251                         "port %u failed to allocate a mempool for"
1252                         " Multi-Packet RQ, count=%u, size=%u",
1253                         dev->data->port_id, obj_num, obj_size);
1254                 rte_errno = ENOMEM;
1255                 return -rte_errno;
1256         }
1257         priv->mprq_mp = mp;
1258 exit:
1259         /* Set mempool for each Rx queue. */
1260         for (i = 0; i != priv->rxqs_n; ++i) {
1261                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1262
1263                 if (rxq == NULL)
1264                         continue;
1265                 rxq->mprq_mp = mp;
1266         }
1267         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1268                 dev->data->port_id);
1269         return 0;
1270 }
1271
1272 /**
1273  * Create a DPDK Rx queue.
1274  *
1275  * @param dev
1276  *   Pointer to Ethernet device.
1277  * @param idx
1278  *   RX queue index.
1279  * @param desc
1280  *   Number of descriptors to configure in queue.
1281  * @param socket
1282  *   NUMA socket on which memory must be allocated.
1283  *
1284  * @return
1285  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1286  */
1287 struct mlx5_rxq_ctrl *
1288 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1289              unsigned int socket, const struct rte_eth_rxconf *conf,
1290              struct rte_mempool *mp)
1291 {
1292         struct mlx5_priv *priv = dev->data->dev_private;
1293         struct mlx5_rxq_ctrl *tmpl;
1294         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1295         unsigned int mprq_stride_size;
1296         struct mlx5_dev_config *config = &priv->config;
1297         /*
1298          * Always allocate extra slots, even if eventually
1299          * the vector Rx will not be used.
1300          */
1301         uint16_t desc_n =
1302                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1303         uint64_t offloads = conf->offloads |
1304                            dev->data->dev_conf.rxmode.offloads;
1305         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1306
1307         tmpl = rte_calloc_socket("RXQ", 1,
1308                                  sizeof(*tmpl) +
1309                                  desc_n * sizeof(struct rte_mbuf *),
1310                                  0, socket);
1311         if (!tmpl) {
1312                 rte_errno = ENOMEM;
1313                 return NULL;
1314         }
1315         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1316                                MLX5_MR_BTREE_CACHE_N, socket)) {
1317                 /* rte_errno is already set. */
1318                 goto error;
1319         }
1320         tmpl->socket = socket;
1321         if (dev->data->dev_conf.intr_conf.rxq)
1322                 tmpl->irq = 1;
1323         /*
1324          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1325          * following conditions are met:
1326          *  - MPRQ is enabled.
1327          *  - The number of descs is more than the number of strides.
1328          *  - max_rx_pkt_len plus overhead is less than the max size of a
1329          *    stride.
1330          *  Otherwise, enable Rx scatter if necessary.
1331          */
1332         assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1333         mprq_stride_size =
1334                 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1335                 sizeof(struct rte_mbuf_ext_shared_info) +
1336                 RTE_PKTMBUF_HEADROOM;
1337         if (mprq_en &&
1338             desc > (1U << config->mprq.stride_num_n) &&
1339             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1340                 /* TODO: Rx scatter isn't supported yet. */
1341                 tmpl->rxq.sges_n = 0;
1342                 /* Trim the number of descs needed. */
1343                 desc >>= config->mprq.stride_num_n;
1344                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1345                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1346                                               config->mprq.min_stride_size_n);
1347                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1348                 tmpl->rxq.mprq_max_memcpy_len =
1349                         RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1350                                 config->mprq.max_memcpy_len);
1351                 DRV_LOG(DEBUG,
1352                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1353                         " strd_num_n = %u, strd_sz_n = %u",
1354                         dev->data->port_id, idx,
1355                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1356         } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1357                    (mb_len - RTE_PKTMBUF_HEADROOM)) {
1358                 tmpl->rxq.sges_n = 0;
1359         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1360                 unsigned int size =
1361                         RTE_PKTMBUF_HEADROOM +
1362                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1363                 unsigned int sges_n;
1364
1365                 /*
1366                  * Determine the number of SGEs needed for a full packet
1367                  * and round it to the next power of two.
1368                  */
1369                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1370                 tmpl->rxq.sges_n = sges_n;
1371                 /* Make sure rxq.sges_n did not overflow. */
1372                 size = mb_len * (1 << tmpl->rxq.sges_n);
1373                 size -= RTE_PKTMBUF_HEADROOM;
1374                 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1375                         DRV_LOG(ERR,
1376                                 "port %u too many SGEs (%u) needed to handle"
1377                                 " requested maximum packet size %u",
1378                                 dev->data->port_id,
1379                                 1 << sges_n,
1380                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1381                         rte_errno = EOVERFLOW;
1382                         goto error;
1383                 }
1384         } else {
1385                 DRV_LOG(WARNING,
1386                         "port %u the requested maximum Rx packet size (%u) is"
1387                         " larger than a single mbuf (%u) and scattered mode has"
1388                         " not been requested",
1389                         dev->data->port_id,
1390                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
1391                         mb_len - RTE_PKTMBUF_HEADROOM);
1392         }
1393         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1394                 DRV_LOG(WARNING,
1395                         "port %u MPRQ is requested but cannot be enabled"
1396                         " (requested: desc = %u, stride_sz = %u,"
1397                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1398                         dev->data->port_id, desc, mprq_stride_size,
1399                         (1 << config->mprq.stride_num_n),
1400                         (1 << config->mprq.max_stride_size_n));
1401         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1402                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1403         if (desc % (1 << tmpl->rxq.sges_n)) {
1404                 DRV_LOG(ERR,
1405                         "port %u number of Rx queue descriptors (%u) is not a"
1406                         " multiple of SGEs per packet (%u)",
1407                         dev->data->port_id,
1408                         desc,
1409                         1 << tmpl->rxq.sges_n);
1410                 rte_errno = EINVAL;
1411                 goto error;
1412         }
1413         /* Toggle RX checksum offload if hardware supports it. */
1414         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1415         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1416         /* Configure VLAN stripping. */
1417         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1418         /* By default, FCS (CRC) is stripped by hardware. */
1419         tmpl->rxq.crc_present = 0;
1420         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1421                 if (config->hw_fcs_strip) {
1422                         tmpl->rxq.crc_present = 1;
1423                 } else {
1424                         DRV_LOG(WARNING,
1425                                 "port %u CRC stripping has been disabled but will"
1426                                 " still be performed by hardware, make sure MLNX_OFED"
1427                                 " and firmware are up to date",
1428                                 dev->data->port_id);
1429                 }
1430         }
1431         DRV_LOG(DEBUG,
1432                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1433                 " incoming frames to hide it",
1434                 dev->data->port_id,
1435                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1436                 tmpl->rxq.crc_present << 2);
1437         /* Save port ID. */
1438         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1439                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1440         tmpl->rxq.port_id = dev->data->port_id;
1441         tmpl->priv = priv;
1442         tmpl->rxq.mp = mp;
1443         tmpl->rxq.elts_n = log2above(desc);
1444         tmpl->rxq.rq_repl_thresh =
1445                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1446         tmpl->rxq.elts =
1447                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1448 #ifndef RTE_ARCH_64
1449         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1450 #endif
1451         tmpl->rxq.idx = idx;
1452         rte_atomic32_inc(&tmpl->refcnt);
1453         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1454         return tmpl;
1455 error:
1456         rte_free(tmpl);
1457         return NULL;
1458 }
1459
1460 /**
1461  * Get a Rx queue.
1462  *
1463  * @param dev
1464  *   Pointer to Ethernet device.
1465  * @param idx
1466  *   RX queue index.
1467  *
1468  * @return
1469  *   A pointer to the queue if it exists, NULL otherwise.
1470  */
1471 struct mlx5_rxq_ctrl *
1472 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1473 {
1474         struct mlx5_priv *priv = dev->data->dev_private;
1475         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1476
1477         if ((*priv->rxqs)[idx]) {
1478                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1479                                         struct mlx5_rxq_ctrl,
1480                                         rxq);
1481                 mlx5_rxq_ibv_get(dev, idx);
1482                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1483         }
1484         return rxq_ctrl;
1485 }
1486
1487 /**
1488  * Release a Rx queue.
1489  *
1490  * @param dev
1491  *   Pointer to Ethernet device.
1492  * @param idx
1493  *   RX queue index.
1494  *
1495  * @return
1496  *   1 while a reference on it exists, 0 when freed.
1497  */
1498 int
1499 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1500 {
1501         struct mlx5_priv *priv = dev->data->dev_private;
1502         struct mlx5_rxq_ctrl *rxq_ctrl;
1503
1504         if (!(*priv->rxqs)[idx])
1505                 return 0;
1506         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1507         assert(rxq_ctrl->priv);
1508         if (rxq_ctrl->ibv && !mlx5_rxq_ibv_release(rxq_ctrl->ibv))
1509                 rxq_ctrl->ibv = NULL;
1510         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1511                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1512                 LIST_REMOVE(rxq_ctrl, next);
1513                 rte_free(rxq_ctrl);
1514                 (*priv->rxqs)[idx] = NULL;
1515                 return 0;
1516         }
1517         return 1;
1518 }
1519
1520 /**
1521  * Verify if the queue can be released.
1522  *
1523  * @param dev
1524  *   Pointer to Ethernet device.
1525  * @param idx
1526  *   RX queue index.
1527  *
1528  * @return
1529  *   1 if the queue can be released, negative errno otherwise and rte_errno is
1530  *   set.
1531  */
1532 int
1533 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1534 {
1535         struct mlx5_priv *priv = dev->data->dev_private;
1536         struct mlx5_rxq_ctrl *rxq_ctrl;
1537
1538         if (!(*priv->rxqs)[idx]) {
1539                 rte_errno = EINVAL;
1540                 return -rte_errno;
1541         }
1542         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1543         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1544 }
1545
1546 /**
1547  * Verify the Rx Queue list is empty
1548  *
1549  * @param dev
1550  *   Pointer to Ethernet device.
1551  *
1552  * @return
1553  *   The number of object not released.
1554  */
1555 int
1556 mlx5_rxq_verify(struct rte_eth_dev *dev)
1557 {
1558         struct mlx5_priv *priv = dev->data->dev_private;
1559         struct mlx5_rxq_ctrl *rxq_ctrl;
1560         int ret = 0;
1561
1562         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1563                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1564                         dev->data->port_id, rxq_ctrl->rxq.idx);
1565                 ++ret;
1566         }
1567         return ret;
1568 }
1569
1570 /**
1571  * Create an indirection table.
1572  *
1573  * @param dev
1574  *   Pointer to Ethernet device.
1575  * @param queues
1576  *   Queues entering in the indirection table.
1577  * @param queues_n
1578  *   Number of queues in the array.
1579  *
1580  * @return
1581  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1582  */
1583 struct mlx5_ind_table_ibv *
1584 mlx5_ind_table_ibv_new(struct rte_eth_dev *dev, const uint16_t *queues,
1585                        uint32_t queues_n)
1586 {
1587         struct mlx5_priv *priv = dev->data->dev_private;
1588         struct mlx5_ind_table_ibv *ind_tbl;
1589         const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1590                 log2above(queues_n) :
1591                 log2above(priv->config.ind_table_max_size);
1592         struct ibv_wq *wq[1 << wq_n];
1593         unsigned int i;
1594         unsigned int j;
1595
1596         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1597                              queues_n * sizeof(uint16_t), 0);
1598         if (!ind_tbl) {
1599                 rte_errno = ENOMEM;
1600                 return NULL;
1601         }
1602         for (i = 0; i != queues_n; ++i) {
1603                 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1604
1605                 if (!rxq)
1606                         goto error;
1607                 wq[i] = rxq->ibv->wq;
1608                 ind_tbl->queues[i] = queues[i];
1609         }
1610         ind_tbl->queues_n = queues_n;
1611         /* Finalise indirection table. */
1612         for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1613                 wq[i] = wq[j];
1614         ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1615                 (priv->sh->ctx,
1616                  &(struct ibv_rwq_ind_table_init_attr){
1617                         .log_ind_tbl_size = wq_n,
1618                         .ind_tbl = wq,
1619                         .comp_mask = 0,
1620                  });
1621         if (!ind_tbl->ind_table) {
1622                 rte_errno = errno;
1623                 goto error;
1624         }
1625         rte_atomic32_inc(&ind_tbl->refcnt);
1626         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1627         return ind_tbl;
1628 error:
1629         rte_free(ind_tbl);
1630         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1631         return NULL;
1632 }
1633
1634 /**
1635  * Get an indirection table.
1636  *
1637  * @param dev
1638  *   Pointer to Ethernet device.
1639  * @param queues
1640  *   Queues entering in the indirection table.
1641  * @param queues_n
1642  *   Number of queues in the array.
1643  *
1644  * @return
1645  *   An indirection table if found.
1646  */
1647 struct mlx5_ind_table_ibv *
1648 mlx5_ind_table_ibv_get(struct rte_eth_dev *dev, const uint16_t *queues,
1649                        uint32_t queues_n)
1650 {
1651         struct mlx5_priv *priv = dev->data->dev_private;
1652         struct mlx5_ind_table_ibv *ind_tbl;
1653
1654         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1655                 if ((ind_tbl->queues_n == queues_n) &&
1656                     (memcmp(ind_tbl->queues, queues,
1657                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1658                      == 0))
1659                         break;
1660         }
1661         if (ind_tbl) {
1662                 unsigned int i;
1663
1664                 rte_atomic32_inc(&ind_tbl->refcnt);
1665                 for (i = 0; i != ind_tbl->queues_n; ++i)
1666                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1667         }
1668         return ind_tbl;
1669 }
1670
1671 /**
1672  * Release an indirection table.
1673  *
1674  * @param dev
1675  *   Pointer to Ethernet device.
1676  * @param ind_table
1677  *   Indirection table to release.
1678  *
1679  * @return
1680  *   1 while a reference on it exists, 0 when freed.
1681  */
1682 int
1683 mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
1684                            struct mlx5_ind_table_ibv *ind_tbl)
1685 {
1686         unsigned int i;
1687
1688         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1689                 claim_zero(mlx5_glue->destroy_rwq_ind_table
1690                            (ind_tbl->ind_table));
1691         for (i = 0; i != ind_tbl->queues_n; ++i)
1692                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1693         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1694                 LIST_REMOVE(ind_tbl, next);
1695                 rte_free(ind_tbl);
1696                 return 0;
1697         }
1698         return 1;
1699 }
1700
1701 /**
1702  * Verify the Rx Queue list is empty
1703  *
1704  * @param dev
1705  *   Pointer to Ethernet device.
1706  *
1707  * @return
1708  *   The number of object not released.
1709  */
1710 int
1711 mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev)
1712 {
1713         struct mlx5_priv *priv = dev->data->dev_private;
1714         struct mlx5_ind_table_ibv *ind_tbl;
1715         int ret = 0;
1716
1717         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1718                 DRV_LOG(DEBUG,
1719                         "port %u Verbs indirection table %p still referenced",
1720                         dev->data->port_id, (void *)ind_tbl);
1721                 ++ret;
1722         }
1723         return ret;
1724 }
1725
1726 /**
1727  * Create an Rx Hash queue.
1728  *
1729  * @param dev
1730  *   Pointer to Ethernet device.
1731  * @param rss_key
1732  *   RSS key for the Rx hash queue.
1733  * @param rss_key_len
1734  *   RSS key length.
1735  * @param hash_fields
1736  *   Verbs protocol hash field to make the RSS on.
1737  * @param queues
1738  *   Queues entering in hash queue. In case of empty hash_fields only the
1739  *   first queue index will be taken for the indirection table.
1740  * @param queues_n
1741  *   Number of queues.
1742  * @param tunnel
1743  *   Tunnel type.
1744  *
1745  * @return
1746  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1747  */
1748 struct mlx5_hrxq *
1749 mlx5_hrxq_new(struct rte_eth_dev *dev,
1750               const uint8_t *rss_key, uint32_t rss_key_len,
1751               uint64_t hash_fields,
1752               const uint16_t *queues, uint32_t queues_n,
1753               int tunnel __rte_unused)
1754 {
1755         struct mlx5_priv *priv = dev->data->dev_private;
1756         struct mlx5_hrxq *hrxq;
1757         struct mlx5_ind_table_ibv *ind_tbl;
1758         struct ibv_qp *qp;
1759 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1760         struct mlx5dv_qp_init_attr qp_init_attr;
1761 #endif
1762         int err;
1763
1764         queues_n = hash_fields ? queues_n : 1;
1765         ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1766         if (!ind_tbl)
1767                 ind_tbl = mlx5_ind_table_ibv_new(dev, queues, queues_n);
1768         if (!ind_tbl) {
1769                 rte_errno = ENOMEM;
1770                 return NULL;
1771         }
1772 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1773         memset(&qp_init_attr, 0, sizeof(qp_init_attr));
1774         if (tunnel) {
1775                 qp_init_attr.comp_mask =
1776                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1777                 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1778         }
1779 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1780         if (dev->data->dev_conf.lpbk_mode) {
1781                 /* Allow packet sent from NIC loop back w/o source MAC check. */
1782                 qp_init_attr.comp_mask |=
1783                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1784                 qp_init_attr.create_flags |=
1785                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1786         }
1787 #endif
1788         qp = mlx5_glue->dv_create_qp
1789                 (priv->sh->ctx,
1790                  &(struct ibv_qp_init_attr_ex){
1791                         .qp_type = IBV_QPT_RAW_PACKET,
1792                         .comp_mask =
1793                                 IBV_QP_INIT_ATTR_PD |
1794                                 IBV_QP_INIT_ATTR_IND_TABLE |
1795                                 IBV_QP_INIT_ATTR_RX_HASH,
1796                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1797                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1798                                 .rx_hash_key_len = rss_key_len,
1799                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1800                                 .rx_hash_fields_mask = hash_fields,
1801                         },
1802                         .rwq_ind_tbl = ind_tbl->ind_table,
1803                         .pd = priv->sh->pd,
1804                  },
1805                  &qp_init_attr);
1806 #else
1807         qp = mlx5_glue->create_qp_ex
1808                 (priv->sh->ctx,
1809                  &(struct ibv_qp_init_attr_ex){
1810                         .qp_type = IBV_QPT_RAW_PACKET,
1811                         .comp_mask =
1812                                 IBV_QP_INIT_ATTR_PD |
1813                                 IBV_QP_INIT_ATTR_IND_TABLE |
1814                                 IBV_QP_INIT_ATTR_RX_HASH,
1815                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1816                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1817                                 .rx_hash_key_len = rss_key_len,
1818                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1819                                 .rx_hash_fields_mask = hash_fields,
1820                         },
1821                         .rwq_ind_tbl = ind_tbl->ind_table,
1822                         .pd = priv->sh->pd,
1823                  });
1824 #endif
1825         if (!qp) {
1826                 rte_errno = errno;
1827                 goto error;
1828         }
1829         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1830         if (!hrxq)
1831                 goto error;
1832         hrxq->ind_table = ind_tbl;
1833         hrxq->qp = qp;
1834         hrxq->rss_key_len = rss_key_len;
1835         hrxq->hash_fields = hash_fields;
1836         memcpy(hrxq->rss_key, rss_key, rss_key_len);
1837 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1838         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
1839         if (!hrxq->action) {
1840                 rte_errno = errno;
1841                 goto error;
1842         }
1843 #endif
1844         rte_atomic32_inc(&hrxq->refcnt);
1845         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1846         return hrxq;
1847 error:
1848         err = rte_errno; /* Save rte_errno before cleanup. */
1849         mlx5_ind_table_ibv_release(dev, ind_tbl);
1850         if (qp)
1851                 claim_zero(mlx5_glue->destroy_qp(qp));
1852         rte_errno = err; /* Restore rte_errno. */
1853         return NULL;
1854 }
1855
1856 /**
1857  * Get an Rx Hash queue.
1858  *
1859  * @param dev
1860  *   Pointer to Ethernet device.
1861  * @param rss_conf
1862  *   RSS configuration for the Rx hash queue.
1863  * @param queues
1864  *   Queues entering in hash queue. In case of empty hash_fields only the
1865  *   first queue index will be taken for the indirection table.
1866  * @param queues_n
1867  *   Number of queues.
1868  *
1869  * @return
1870  *   An hash Rx queue on success.
1871  */
1872 struct mlx5_hrxq *
1873 mlx5_hrxq_get(struct rte_eth_dev *dev,
1874               const uint8_t *rss_key, uint32_t rss_key_len,
1875               uint64_t hash_fields,
1876               const uint16_t *queues, uint32_t queues_n)
1877 {
1878         struct mlx5_priv *priv = dev->data->dev_private;
1879         struct mlx5_hrxq *hrxq;
1880
1881         queues_n = hash_fields ? queues_n : 1;
1882         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1883                 struct mlx5_ind_table_ibv *ind_tbl;
1884
1885                 if (hrxq->rss_key_len != rss_key_len)
1886                         continue;
1887                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1888                         continue;
1889                 if (hrxq->hash_fields != hash_fields)
1890                         continue;
1891                 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1892                 if (!ind_tbl)
1893                         continue;
1894                 if (ind_tbl != hrxq->ind_table) {
1895                         mlx5_ind_table_ibv_release(dev, ind_tbl);
1896                         continue;
1897                 }
1898                 rte_atomic32_inc(&hrxq->refcnt);
1899                 return hrxq;
1900         }
1901         return NULL;
1902 }
1903
1904 /**
1905  * Release the hash Rx queue.
1906  *
1907  * @param dev
1908  *   Pointer to Ethernet device.
1909  * @param hrxq
1910  *   Pointer to Hash Rx queue to release.
1911  *
1912  * @return
1913  *   1 while a reference on it exists, 0 when freed.
1914  */
1915 int
1916 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1917 {
1918         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1919 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1920                 mlx5_glue->destroy_flow_action(hrxq->action);
1921 #endif
1922                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
1923                 mlx5_ind_table_ibv_release(dev, hrxq->ind_table);
1924                 LIST_REMOVE(hrxq, next);
1925                 rte_free(hrxq);
1926                 return 0;
1927         }
1928         claim_nonzero(mlx5_ind_table_ibv_release(dev, hrxq->ind_table));
1929         return 1;
1930 }
1931
1932 /**
1933  * Verify the Rx Queue list is empty
1934  *
1935  * @param dev
1936  *   Pointer to Ethernet device.
1937  *
1938  * @return
1939  *   The number of object not released.
1940  */
1941 int
1942 mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev)
1943 {
1944         struct mlx5_priv *priv = dev->data->dev_private;
1945         struct mlx5_hrxq *hrxq;
1946         int ret = 0;
1947
1948         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1949                 DRV_LOG(DEBUG,
1950                         "port %u Verbs hash Rx queue %p still referenced",
1951                         dev->data->port_id, (void *)hrxq);
1952                 ++ret;
1953         }
1954         return ret;
1955 }
1956
1957 /**
1958  * Create a drop Rx queue Verbs object.
1959  *
1960  * @param dev
1961  *   Pointer to Ethernet device.
1962  *
1963  * @return
1964  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1965  */
1966 struct mlx5_rxq_ibv *
1967 mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev)
1968 {
1969         struct mlx5_priv *priv = dev->data->dev_private;
1970         struct ibv_context *ctx = priv->sh->ctx;
1971         struct ibv_cq *cq;
1972         struct ibv_wq *wq = NULL;
1973         struct mlx5_rxq_ibv *rxq;
1974
1975         if (priv->drop_queue.rxq)
1976                 return priv->drop_queue.rxq;
1977         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
1978         if (!cq) {
1979                 DEBUG("port %u cannot allocate CQ for drop queue",
1980                       dev->data->port_id);
1981                 rte_errno = errno;
1982                 goto error;
1983         }
1984         wq = mlx5_glue->create_wq(ctx,
1985                  &(struct ibv_wq_init_attr){
1986                         .wq_type = IBV_WQT_RQ,
1987                         .max_wr = 1,
1988                         .max_sge = 1,
1989                         .pd = priv->sh->pd,
1990                         .cq = cq,
1991                  });
1992         if (!wq) {
1993                 DEBUG("port %u cannot allocate WQ for drop queue",
1994                       dev->data->port_id);
1995                 rte_errno = errno;
1996                 goto error;
1997         }
1998         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
1999         if (!rxq) {
2000                 DEBUG("port %u cannot allocate drop Rx queue memory",
2001                       dev->data->port_id);
2002                 rte_errno = ENOMEM;
2003                 goto error;
2004         }
2005         rxq->cq = cq;
2006         rxq->wq = wq;
2007         priv->drop_queue.rxq = rxq;
2008         return rxq;
2009 error:
2010         if (wq)
2011                 claim_zero(mlx5_glue->destroy_wq(wq));
2012         if (cq)
2013                 claim_zero(mlx5_glue->destroy_cq(cq));
2014         return NULL;
2015 }
2016
2017 /**
2018  * Release a drop Rx queue Verbs object.
2019  *
2020  * @param dev
2021  *   Pointer to Ethernet device.
2022  *
2023  * @return
2024  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2025  */
2026 void
2027 mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev)
2028 {
2029         struct mlx5_priv *priv = dev->data->dev_private;
2030         struct mlx5_rxq_ibv *rxq = priv->drop_queue.rxq;
2031
2032         if (rxq->wq)
2033                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2034         if (rxq->cq)
2035                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2036         rte_free(rxq);
2037         priv->drop_queue.rxq = NULL;
2038 }
2039
2040 /**
2041  * Create a drop indirection table.
2042  *
2043  * @param dev
2044  *   Pointer to Ethernet device.
2045  *
2046  * @return
2047  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2048  */
2049 struct mlx5_ind_table_ibv *
2050 mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev)
2051 {
2052         struct mlx5_priv *priv = dev->data->dev_private;
2053         struct mlx5_ind_table_ibv *ind_tbl;
2054         struct mlx5_rxq_ibv *rxq;
2055         struct mlx5_ind_table_ibv tmpl;
2056
2057         rxq = mlx5_rxq_ibv_drop_new(dev);
2058         if (!rxq)
2059                 return NULL;
2060         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2061                 (priv->sh->ctx,
2062                  &(struct ibv_rwq_ind_table_init_attr){
2063                         .log_ind_tbl_size = 0,
2064                         .ind_tbl = &rxq->wq,
2065                         .comp_mask = 0,
2066                  });
2067         if (!tmpl.ind_table) {
2068                 DEBUG("port %u cannot allocate indirection table for drop"
2069                       " queue",
2070                       dev->data->port_id);
2071                 rte_errno = errno;
2072                 goto error;
2073         }
2074         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2075         if (!ind_tbl) {
2076                 rte_errno = ENOMEM;
2077                 goto error;
2078         }
2079         ind_tbl->ind_table = tmpl.ind_table;
2080         return ind_tbl;
2081 error:
2082         mlx5_rxq_ibv_drop_release(dev);
2083         return NULL;
2084 }
2085
2086 /**
2087  * Release a drop indirection table.
2088  *
2089  * @param dev
2090  *   Pointer to Ethernet device.
2091  */
2092 void
2093 mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev)
2094 {
2095         struct mlx5_priv *priv = dev->data->dev_private;
2096         struct mlx5_ind_table_ibv *ind_tbl = priv->drop_queue.hrxq->ind_table;
2097
2098         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2099         mlx5_rxq_ibv_drop_release(dev);
2100         rte_free(ind_tbl);
2101         priv->drop_queue.hrxq->ind_table = NULL;
2102 }
2103
2104 /**
2105  * Create a drop Rx Hash queue.
2106  *
2107  * @param dev
2108  *   Pointer to Ethernet device.
2109  *
2110  * @return
2111  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2112  */
2113 struct mlx5_hrxq *
2114 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2115 {
2116         struct mlx5_priv *priv = dev->data->dev_private;
2117         struct mlx5_ind_table_ibv *ind_tbl;
2118         struct ibv_qp *qp;
2119         struct mlx5_hrxq *hrxq;
2120
2121         if (priv->drop_queue.hrxq) {
2122                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2123                 return priv->drop_queue.hrxq;
2124         }
2125         ind_tbl = mlx5_ind_table_ibv_drop_new(dev);
2126         if (!ind_tbl)
2127                 return NULL;
2128         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2129                  &(struct ibv_qp_init_attr_ex){
2130                         .qp_type = IBV_QPT_RAW_PACKET,
2131                         .comp_mask =
2132                                 IBV_QP_INIT_ATTR_PD |
2133                                 IBV_QP_INIT_ATTR_IND_TABLE |
2134                                 IBV_QP_INIT_ATTR_RX_HASH,
2135                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2136                                 .rx_hash_function =
2137                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2138                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2139                                 .rx_hash_key = rss_hash_default_key,
2140                                 .rx_hash_fields_mask = 0,
2141                                 },
2142                         .rwq_ind_tbl = ind_tbl->ind_table,
2143                         .pd = priv->sh->pd
2144                  });
2145         if (!qp) {
2146                 DEBUG("port %u cannot allocate QP for drop queue",
2147                       dev->data->port_id);
2148                 rte_errno = errno;
2149                 goto error;
2150         }
2151         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2152         if (!hrxq) {
2153                 DRV_LOG(WARNING,
2154                         "port %u cannot allocate memory for drop queue",
2155                         dev->data->port_id);
2156                 rte_errno = ENOMEM;
2157                 goto error;
2158         }
2159         hrxq->ind_table = ind_tbl;
2160         hrxq->qp = qp;
2161 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2162         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2163         if (!hrxq->action) {
2164                 rte_errno = errno;
2165                 goto error;
2166         }
2167 #endif
2168         priv->drop_queue.hrxq = hrxq;
2169         rte_atomic32_set(&hrxq->refcnt, 1);
2170         return hrxq;
2171 error:
2172         if (ind_tbl)
2173                 mlx5_ind_table_ibv_drop_release(dev);
2174         return NULL;
2175 }
2176
2177 /**
2178  * Release a drop hash Rx queue.
2179  *
2180  * @param dev
2181  *   Pointer to Ethernet device.
2182  */
2183 void
2184 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2185 {
2186         struct mlx5_priv *priv = dev->data->dev_private;
2187         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2188
2189         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2190 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2191                 mlx5_glue->destroy_flow_action(hrxq->action);
2192 #endif
2193                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2194                 mlx5_ind_table_ibv_drop_release(dev);
2195                 rte_free(hrxq);
2196                 priv->drop_queue.hrxq = NULL;
2197         }
2198 }