1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 #include <sys/queue.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
29 #include <rte_interrupts.h>
30 #include <rte_debug.h>
34 #include "mlx5_rxtx.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
38 #include "mlx5_glue.h"
39 #include "mlx5_flow.h"
41 /* Default RSS hash key also used for ConnectX-3. */
42 uint8_t rss_hash_default_key[] = {
43 0x2c, 0xc6, 0x81, 0xd1,
44 0x5b, 0xdb, 0xf4, 0xf7,
45 0xfc, 0xa2, 0x83, 0x19,
46 0xdb, 0x1a, 0x3e, 0x94,
47 0x6b, 0x9e, 0x38, 0xd9,
48 0x2c, 0x9c, 0x03, 0xd1,
49 0xad, 0x99, 0x44, 0xa7,
50 0xd9, 0x56, 0x3d, 0x59,
51 0x06, 0x3c, 0x25, 0xf3,
52 0xfc, 0x1f, 0xdc, 0x2a,
55 /* Length of the default RSS hash key. */
56 static_assert(MLX5_RSS_HASH_KEY_LEN ==
57 (unsigned int)sizeof(rss_hash_default_key),
58 "wrong RSS default key size.");
61 * Check whether Multi-Packet RQ can be enabled for the device.
64 * Pointer to Ethernet device.
67 * 1 if supported, negative errno value if not.
70 mlx5_check_mprq_support(struct rte_eth_dev *dev)
72 struct mlx5_priv *priv = dev->data->dev_private;
74 if (priv->config.mprq.enabled &&
75 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
81 * Check whether Multi-Packet RQ is enabled for the Rx queue.
84 * Pointer to receive queue structure.
87 * 0 if disabled, otherwise enabled.
90 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
92 return rxq->strd_num_n > 0;
96 * Check whether Multi-Packet RQ is enabled for the device.
99 * Pointer to Ethernet device.
102 * 0 if disabled, otherwise enabled.
105 mlx5_mprq_enabled(struct rte_eth_dev *dev)
107 struct mlx5_priv *priv = dev->data->dev_private;
112 if (mlx5_check_mprq_support(dev) < 0)
114 /* All the configured queues should be enabled. */
115 for (i = 0; i < priv->rxqs_n; ++i) {
116 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
117 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
118 (rxq, struct mlx5_rxq_ctrl, rxq);
120 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
123 if (mlx5_rxq_mprq_enabled(rxq))
126 /* Multi-Packet RQ can't be partially configured. */
127 assert(n == 0 || n == n_ibv);
132 * Allocate RX queue elements for Multi-Packet RQ.
135 * Pointer to RX queue structure.
138 * 0 on success, a negative errno value otherwise and rte_errno is set.
141 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
143 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
144 unsigned int wqe_n = 1 << rxq->elts_n;
148 /* Iterate on segments. */
149 for (i = 0; i <= wqe_n; ++i) {
150 struct mlx5_mprq_buf *buf;
152 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
153 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
158 (*rxq->mprq_bufs)[i] = buf;
160 rxq->mprq_repl = buf;
163 "port %u Rx queue %u allocated and configured %u segments",
164 rxq->port_id, rxq->idx, wqe_n);
167 err = rte_errno; /* Save rte_errno before cleanup. */
169 for (i = 0; (i != wqe_n); ++i) {
170 if ((*rxq->mprq_bufs)[i] != NULL)
171 rte_mempool_put(rxq->mprq_mp,
172 (*rxq->mprq_bufs)[i]);
173 (*rxq->mprq_bufs)[i] = NULL;
175 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
176 rxq->port_id, rxq->idx);
177 rte_errno = err; /* Restore rte_errno. */
182 * Allocate RX queue elements for Single-Packet RQ.
185 * Pointer to RX queue structure.
188 * 0 on success, errno value on failure.
191 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
193 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
194 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
198 /* Iterate on segments. */
199 for (i = 0; (i != elts_n); ++i) {
200 struct rte_mbuf *buf;
202 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
204 DRV_LOG(ERR, "port %u empty mbuf pool",
205 PORT_ID(rxq_ctrl->priv));
209 /* Headroom is reserved by rte_pktmbuf_alloc(). */
210 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
211 /* Buffer is supposed to be empty. */
212 assert(rte_pktmbuf_data_len(buf) == 0);
213 assert(rte_pktmbuf_pkt_len(buf) == 0);
215 /* Only the first segment keeps headroom. */
217 SET_DATA_OFF(buf, 0);
218 PORT(buf) = rxq_ctrl->rxq.port_id;
219 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
220 PKT_LEN(buf) = DATA_LEN(buf);
222 (*rxq_ctrl->rxq.elts)[i] = buf;
224 /* If Rx vector is activated. */
225 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
226 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
227 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
230 /* Initialize default rearm_data for vPMD. */
231 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
232 rte_mbuf_refcnt_set(mbuf_init, 1);
233 mbuf_init->nb_segs = 1;
234 mbuf_init->port = rxq->port_id;
236 * prevent compiler reordering:
237 * rearm_data covers previous fields.
239 rte_compiler_barrier();
240 rxq->mbuf_initializer =
241 *(uint64_t *)&mbuf_init->rearm_data;
242 /* Padding with a fake mbuf for vectorized Rx. */
243 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
244 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
247 "port %u Rx queue %u allocated and configured %u segments"
249 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
250 elts_n / (1 << rxq_ctrl->rxq.sges_n));
253 err = rte_errno; /* Save rte_errno before cleanup. */
255 for (i = 0; (i != elts_n); ++i) {
256 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
257 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
258 (*rxq_ctrl->rxq.elts)[i] = NULL;
260 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
261 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
262 rte_errno = err; /* Restore rte_errno. */
267 * Allocate RX queue elements.
270 * Pointer to RX queue structure.
273 * 0 on success, errno value on failure.
276 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
278 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
279 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
283 * Free RX queue elements for Multi-Packet RQ.
286 * Pointer to RX queue structure.
289 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
291 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
294 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
295 rxq->port_id, rxq->idx);
296 if (rxq->mprq_bufs == NULL)
298 assert(mlx5_rxq_check_vec_support(rxq) < 0);
299 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
300 if ((*rxq->mprq_bufs)[i] != NULL)
301 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
302 (*rxq->mprq_bufs)[i] = NULL;
304 if (rxq->mprq_repl != NULL) {
305 mlx5_mprq_buf_free(rxq->mprq_repl);
306 rxq->mprq_repl = NULL;
311 * Free RX queue elements for Single-Packet RQ.
314 * Pointer to RX queue structure.
317 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
319 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
320 const uint16_t q_n = (1 << rxq->elts_n);
321 const uint16_t q_mask = q_n - 1;
322 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
325 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
326 PORT_ID(rxq_ctrl->priv), rxq->idx);
327 if (rxq->elts == NULL)
330 * Some mbuf in the Ring belongs to the application. They cannot be
333 if (mlx5_rxq_check_vec_support(rxq) > 0) {
334 for (i = 0; i < used; ++i)
335 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
336 rxq->rq_pi = rxq->rq_ci;
338 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
339 if ((*rxq->elts)[i] != NULL)
340 rte_pktmbuf_free_seg((*rxq->elts)[i]);
341 (*rxq->elts)[i] = NULL;
346 * Free RX queue elements.
349 * Pointer to RX queue structure.
352 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
354 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
355 rxq_free_elts_mprq(rxq_ctrl);
357 rxq_free_elts_sprq(rxq_ctrl);
361 * Returns the per-queue supported offloads.
364 * Pointer to Ethernet device.
367 * Supported Rx offloads.
370 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
372 struct mlx5_priv *priv = dev->data->dev_private;
373 struct mlx5_dev_config *config = &priv->config;
374 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
375 DEV_RX_OFFLOAD_TIMESTAMP |
376 DEV_RX_OFFLOAD_JUMBO_FRAME |
377 DEV_RX_OFFLOAD_RSS_HASH);
379 if (config->hw_fcs_strip)
380 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
383 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
384 DEV_RX_OFFLOAD_UDP_CKSUM |
385 DEV_RX_OFFLOAD_TCP_CKSUM);
386 if (config->hw_vlan_strip)
387 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
388 if (MLX5_LRO_SUPPORTED(dev))
389 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
395 * Returns the per-port supported offloads.
398 * Supported Rx offloads.
401 mlx5_get_rx_port_offloads(void)
403 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
409 * Verify if the queue can be released.
412 * Pointer to Ethernet device.
417 * 1 if the queue can be released
418 * 0 if the queue can not be released, there are references to it.
419 * Negative errno and rte_errno is set if queue doesn't exist.
422 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
424 struct mlx5_priv *priv = dev->data->dev_private;
425 struct mlx5_rxq_ctrl *rxq_ctrl;
427 if (!(*priv->rxqs)[idx]) {
431 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
432 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
436 * Rx queue presetup checks.
439 * Pointer to Ethernet device structure.
443 * Number of descriptors to configure in queue.
446 * 0 on success, a negative errno value otherwise and rte_errno is set.
449 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
451 struct mlx5_priv *priv = dev->data->dev_private;
453 if (!rte_is_power_of_2(desc)) {
454 desc = 1 << log2above(desc);
456 "port %u increased number of descriptors in Rx queue %u"
457 " to the next power of two (%d)",
458 dev->data->port_id, idx, desc);
460 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
461 dev->data->port_id, idx, desc);
462 if (idx >= priv->rxqs_n) {
463 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
464 dev->data->port_id, idx, priv->rxqs_n);
465 rte_errno = EOVERFLOW;
468 if (!mlx5_rxq_releasable(dev, idx)) {
469 DRV_LOG(ERR, "port %u unable to release queue index %u",
470 dev->data->port_id, idx);
474 mlx5_rxq_release(dev, idx);
481 * Pointer to Ethernet device structure.
485 * Number of descriptors to configure in queue.
487 * NUMA socket on which memory must be allocated.
489 * Thresholds parameters.
491 * Memory pool for buffer allocations.
494 * 0 on success, a negative errno value otherwise and rte_errno is set.
497 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
498 unsigned int socket, const struct rte_eth_rxconf *conf,
499 struct rte_mempool *mp)
501 struct mlx5_priv *priv = dev->data->dev_private;
502 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
503 struct mlx5_rxq_ctrl *rxq_ctrl =
504 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
507 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
510 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
512 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
513 dev->data->port_id, idx);
517 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
518 dev->data->port_id, idx);
519 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
526 * Pointer to Ethernet device structure.
530 * Number of descriptors to configure in queue.
531 * @param hairpin_conf
532 * Hairpin configuration parameters.
535 * 0 on success, a negative errno value otherwise and rte_errno is set.
538 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
540 const struct rte_eth_hairpin_conf *hairpin_conf)
542 struct mlx5_priv *priv = dev->data->dev_private;
543 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
544 struct mlx5_rxq_ctrl *rxq_ctrl =
545 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
548 res = mlx5_rx_queue_pre_setup(dev, idx, desc);
551 if (hairpin_conf->peer_count != 1 ||
552 hairpin_conf->peers[0].port != dev->data->port_id ||
553 hairpin_conf->peers[0].queue >= priv->txqs_n) {
554 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
555 " invalid hairpind configuration", dev->data->port_id,
560 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
562 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
563 dev->data->port_id, idx);
567 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
568 dev->data->port_id, idx);
569 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
574 * DPDK callback to release a RX queue.
577 * Generic RX queue pointer.
580 mlx5_rx_queue_release(void *dpdk_rxq)
582 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
583 struct mlx5_rxq_ctrl *rxq_ctrl;
584 struct mlx5_priv *priv;
588 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
589 priv = rxq_ctrl->priv;
590 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
591 rte_panic("port %u Rx queue %u is still used by a flow and"
592 " cannot be removed\n",
593 PORT_ID(priv), rxq->idx);
594 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
598 * Get an Rx queue Verbs/DevX object.
601 * Pointer to Ethernet device.
603 * Queue index in DPDK Rx queue array
606 * The Verbs/DevX object if it exists.
608 static struct mlx5_rxq_obj *
609 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
611 struct mlx5_priv *priv = dev->data->dev_private;
612 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
613 struct mlx5_rxq_ctrl *rxq_ctrl;
615 if (idx >= priv->rxqs_n)
619 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
621 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
622 return rxq_ctrl->obj;
626 * Release the resources allocated for an RQ DevX object.
629 * DevX Rx queue object.
632 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
634 if (rxq_ctrl->rxq.wqes) {
635 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
636 rxq_ctrl->rxq.wqes = NULL;
638 if (rxq_ctrl->wq_umem) {
639 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
640 rxq_ctrl->wq_umem = NULL;
645 * Release an Rx hairpin related resources.
648 * Hairpin Rx queue object.
651 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
653 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
656 rq_attr.state = MLX5_RQC_STATE_RST;
657 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
658 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
659 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
663 * Release an Rx verbs/DevX queue object.
666 * Verbs/DevX Rx queue object.
669 * 1 while a reference on it exists, 0 when freed.
672 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
675 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
676 switch (rxq_obj->type) {
677 case MLX5_RXQ_OBJ_TYPE_IBV:
680 rxq_free_elts(rxq_obj->rxq_ctrl);
681 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
682 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
684 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
687 rxq_free_elts(rxq_obj->rxq_ctrl);
688 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
689 rxq_release_rq_resources(rxq_obj->rxq_ctrl);
690 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
692 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
694 rxq_obj_hairpin_release(rxq_obj);
697 if (rxq_obj->channel)
698 claim_zero(mlx5_glue->destroy_comp_channel
700 LIST_REMOVE(rxq_obj, next);
708 * Allocate queue vector and fill epoll fd list for Rx interrupts.
711 * Pointer to Ethernet device.
714 * 0 on success, a negative errno value otherwise and rte_errno is set.
717 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
719 struct mlx5_priv *priv = dev->data->dev_private;
721 unsigned int rxqs_n = priv->rxqs_n;
722 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
723 unsigned int count = 0;
724 struct rte_intr_handle *intr_handle = dev->intr_handle;
726 if (!dev->data->dev_conf.intr_conf.rxq)
728 mlx5_rx_intr_vec_disable(dev);
729 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
730 if (intr_handle->intr_vec == NULL) {
732 "port %u failed to allocate memory for interrupt"
733 " vector, Rx interrupts will not be supported",
738 intr_handle->type = RTE_INTR_HANDLE_EXT;
739 for (i = 0; i != n; ++i) {
740 /* This rxq obj must not be released in this function. */
741 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
746 /* Skip queues that cannot request interrupts. */
747 if (!rxq_obj || !rxq_obj->channel) {
748 /* Use invalid intr_vec[] index to disable entry. */
749 intr_handle->intr_vec[i] =
750 RTE_INTR_VEC_RXTX_OFFSET +
751 RTE_MAX_RXTX_INTR_VEC_ID;
754 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
756 "port %u too many Rx queues for interrupt"
757 " vector size (%d), Rx interrupts cannot be"
759 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
760 mlx5_rx_intr_vec_disable(dev);
764 fd = rxq_obj->channel->fd;
765 flags = fcntl(fd, F_GETFL);
766 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
770 "port %u failed to make Rx interrupt file"
771 " descriptor %d non-blocking for queue index"
773 dev->data->port_id, fd, i);
774 mlx5_rx_intr_vec_disable(dev);
777 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
778 intr_handle->efds[count] = fd;
782 mlx5_rx_intr_vec_disable(dev);
784 intr_handle->nb_efd = count;
789 * Clean up Rx interrupts handler.
792 * Pointer to Ethernet device.
795 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
797 struct mlx5_priv *priv = dev->data->dev_private;
798 struct rte_intr_handle *intr_handle = dev->intr_handle;
800 unsigned int rxqs_n = priv->rxqs_n;
801 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
803 if (!dev->data->dev_conf.intr_conf.rxq)
805 if (!intr_handle->intr_vec)
807 for (i = 0; i != n; ++i) {
808 struct mlx5_rxq_ctrl *rxq_ctrl;
809 struct mlx5_rxq_data *rxq_data;
811 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
812 RTE_MAX_RXTX_INTR_VEC_ID)
815 * Need to access directly the queue to release the reference
816 * kept in mlx5_rx_intr_vec_enable().
818 rxq_data = (*priv->rxqs)[i];
819 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
821 mlx5_rxq_obj_release(rxq_ctrl->obj);
824 rte_intr_free_epoll_fd(intr_handle);
825 if (intr_handle->intr_vec)
826 free(intr_handle->intr_vec);
827 intr_handle->nb_efd = 0;
828 intr_handle->intr_vec = NULL;
832 * MLX5 CQ notification .
835 * Pointer to receive queue structure.
837 * Sequence number per receive queue .
840 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
843 uint32_t doorbell_hi;
845 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
847 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
848 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
849 doorbell = (uint64_t)doorbell_hi << 32;
850 doorbell |= rxq->cqn;
851 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
852 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
853 cq_db_reg, rxq->uar_lock_cq);
857 * DPDK callback for Rx queue interrupt enable.
860 * Pointer to Ethernet device structure.
865 * 0 on success, a negative errno value otherwise and rte_errno is set.
868 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
870 struct mlx5_priv *priv = dev->data->dev_private;
871 struct mlx5_rxq_data *rxq_data;
872 struct mlx5_rxq_ctrl *rxq_ctrl;
874 rxq_data = (*priv->rxqs)[rx_queue_id];
879 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
881 struct mlx5_rxq_obj *rxq_obj;
883 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
888 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
889 mlx5_rxq_obj_release(rxq_obj);
895 * DPDK callback for Rx queue interrupt disable.
898 * Pointer to Ethernet device structure.
903 * 0 on success, a negative errno value otherwise and rte_errno is set.
906 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
908 struct mlx5_priv *priv = dev->data->dev_private;
909 struct mlx5_rxq_data *rxq_data;
910 struct mlx5_rxq_ctrl *rxq_ctrl;
911 struct mlx5_rxq_obj *rxq_obj = NULL;
912 struct ibv_cq *ev_cq;
916 rxq_data = (*priv->rxqs)[rx_queue_id];
921 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
924 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
929 ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
930 if (ret || ev_cq != rxq_obj->cq) {
934 rxq_data->cq_arm_sn++;
935 mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
936 mlx5_rxq_obj_release(rxq_obj);
939 ret = rte_errno; /* Save rte_errno before cleanup. */
941 mlx5_rxq_obj_release(rxq_obj);
942 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
943 dev->data->port_id, rx_queue_id);
944 rte_errno = ret; /* Restore rte_errno. */
949 * Create a CQ Verbs object.
952 * Pointer to Ethernet device.
954 * Pointer to device private data.
956 * Pointer to Rx queue data.
958 * Number of CQEs in CQ.
960 * Pointer to Rx queue object data.
963 * The Verbs object initialised, NULL otherwise and rte_errno is set.
965 static struct ibv_cq *
966 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
967 struct mlx5_rxq_data *rxq_data,
968 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
971 struct ibv_cq_init_attr_ex ibv;
972 struct mlx5dv_cq_init_attr mlx5;
975 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
977 .channel = rxq_obj->channel,
980 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
983 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
985 cq_attr.mlx5.comp_mask |=
986 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
987 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
988 cq_attr.mlx5.cqe_comp_res_format =
989 mlx5_rxq_mprq_enabled(rxq_data) ?
990 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
991 MLX5DV_CQE_RES_FORMAT_HASH;
993 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
996 * For vectorized Rx, it must not be doubled in order to
997 * make cq_ci and rq_ci aligned.
999 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1000 cq_attr.ibv.cqe *= 2;
1001 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1003 "port %u Rx CQE compression is disabled for HW"
1005 dev->data->port_id);
1006 } else if (priv->config.cqe_comp && rxq_data->lro) {
1008 "port %u Rx CQE compression is disabled for LRO",
1009 dev->data->port_id);
1011 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1012 if (priv->config.cqe_pad) {
1013 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1014 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1017 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1023 * Create a WQ Verbs object.
1026 * Pointer to Ethernet device.
1028 * Pointer to device private data.
1030 * Pointer to Rx queue data.
1032 * Queue index in DPDK Rx queue array
1034 * Number of WQEs in WQ.
1036 * Pointer to Rx queue object data.
1039 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1041 static struct ibv_wq *
1042 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1043 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1044 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1047 struct ibv_wq_init_attr ibv;
1048 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1049 struct mlx5dv_wq_init_attr mlx5;
1053 wq_attr.ibv = (struct ibv_wq_init_attr){
1054 .wq_context = NULL, /* Could be useful in the future. */
1055 .wq_type = IBV_WQT_RQ,
1056 /* Max number of outstanding WRs. */
1057 .max_wr = wqe_n >> rxq_data->sges_n,
1058 /* Max number of scatter/gather elements in a WR. */
1059 .max_sge = 1 << rxq_data->sges_n,
1062 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1063 .create_flags = (rxq_data->vlan_strip ?
1064 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1066 /* By default, FCS (CRC) is stripped by hardware. */
1067 if (rxq_data->crc_present) {
1068 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1069 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1071 if (priv->config.hw_padding) {
1072 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1073 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1074 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1075 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1076 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1077 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1080 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1081 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1084 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1085 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1086 &wq_attr.mlx5.striding_rq_attrs;
1088 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1089 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1090 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1091 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1092 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1095 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1098 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1102 * Make sure number of WRs*SGEs match expectations since a queue
1103 * cannot allocate more than "desc" buffers.
1105 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1106 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1108 "port %u Rx queue %u requested %u*%u but got"
1110 dev->data->port_id, idx,
1111 wqe_n >> rxq_data->sges_n,
1112 (1 << rxq_data->sges_n),
1113 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1114 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1123 * Fill common fields of create RQ attributes structure.
1126 * Pointer to Rx queue data.
1128 * CQ number to use with this RQ.
1130 * RQ attributes structure to fill..
1133 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1134 struct mlx5_devx_create_rq_attr *rq_attr)
1136 rq_attr->state = MLX5_RQC_STATE_RST;
1137 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1139 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1143 * Fill common fields of DevX WQ attributes structure.
1146 * Pointer to device private data.
1148 * Pointer to Rx queue control structure.
1150 * WQ attributes structure to fill..
1153 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1154 struct mlx5_devx_wq_attr *wq_attr)
1156 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1157 MLX5_WQ_END_PAD_MODE_ALIGN :
1158 MLX5_WQ_END_PAD_MODE_NONE;
1159 wq_attr->pd = priv->sh->pdn;
1160 wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1161 wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1162 wq_attr->dbr_umem_valid = 1;
1163 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1164 wq_attr->wq_umem_valid = 1;
1168 * Create a RQ object using DevX.
1171 * Pointer to Ethernet device.
1173 * Queue index in DPDK Rx queue array
1175 * CQ number to use with this RQ.
1178 * The DevX object initialised, NULL otherwise and rte_errno is set.
1180 static struct mlx5_devx_obj *
1181 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1183 struct mlx5_priv *priv = dev->data->dev_private;
1184 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1185 struct mlx5_rxq_ctrl *rxq_ctrl =
1186 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1187 struct mlx5_devx_create_rq_attr rq_attr;
1188 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1189 uint32_t wq_size = 0;
1190 uint32_t wqe_size = 0;
1191 uint32_t log_wqe_size = 0;
1193 struct mlx5_devx_obj *rq;
1195 memset(&rq_attr, 0, sizeof(rq_attr));
1196 /* Fill RQ attributes. */
1197 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1198 rq_attr.flush_in_error_en = 1;
1199 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1200 /* Fill WQ attributes for this RQ. */
1201 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1202 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1204 * Number of strides in each WQE:
1205 * 512*2^single_wqe_log_num_of_strides.
1207 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1208 rxq_data->strd_num_n -
1209 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1210 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1211 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1212 rxq_data->strd_sz_n -
1213 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1214 wqe_size = sizeof(struct mlx5_wqe_mprq);
1216 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1217 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1219 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1220 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1221 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1222 /* Calculate and allocate WQ memory space. */
1223 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1224 wq_size = wqe_n * wqe_size;
1225 buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1229 rxq_data->wqes = buf;
1230 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1232 if (!rxq_ctrl->wq_umem) {
1236 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1237 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1239 rxq_release_rq_resources(rxq_ctrl);
1244 * Create the Rx hairpin queue object.
1247 * Pointer to Ethernet device.
1249 * Queue index in DPDK Rx queue array
1252 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1254 static struct mlx5_rxq_obj *
1255 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1257 struct mlx5_priv *priv = dev->data->dev_private;
1258 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1259 struct mlx5_rxq_ctrl *rxq_ctrl =
1260 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1261 struct mlx5_devx_create_rq_attr attr = { 0 };
1262 struct mlx5_rxq_obj *tmpl = NULL;
1266 assert(!rxq_ctrl->obj);
1267 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1271 "port %u Rx queue %u cannot allocate verbs resources",
1272 dev->data->port_id, rxq_data->idx);
1276 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1277 tmpl->rxq_ctrl = rxq_ctrl;
1279 /* Workaround for hairpin startup */
1280 attr.wq_attr.log_hairpin_num_packets = log2above(32);
1281 /* Workaround for packets larger than 1KB */
1282 attr.wq_attr.log_hairpin_data_sz =
1283 priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1284 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1288 "port %u Rx hairpin queue %u can't create rq object",
1289 dev->data->port_id, idx);
1293 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1294 idx, (void *)&tmpl);
1295 rte_atomic32_inc(&tmpl->refcnt);
1296 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1297 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1300 ret = rte_errno; /* Save rte_errno before cleanup. */
1302 mlx5_devx_cmd_destroy(tmpl->rq);
1303 rte_errno = ret; /* Restore rte_errno. */
1308 * Create the Rx queue Verbs/DevX object.
1311 * Pointer to Ethernet device.
1313 * Queue index in DPDK Rx queue array
1315 * Type of Rx queue object to create.
1318 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1320 struct mlx5_rxq_obj *
1321 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1322 enum mlx5_rxq_obj_type type)
1324 struct mlx5_priv *priv = dev->data->dev_private;
1325 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1326 struct mlx5_rxq_ctrl *rxq_ctrl =
1327 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1328 struct ibv_wq_attr mod;
1330 unsigned int wqe_n = 1 << rxq_data->elts_n;
1331 struct mlx5_rxq_obj *tmpl = NULL;
1332 struct mlx5dv_cq cq_info;
1333 struct mlx5dv_rwq rwq;
1335 struct mlx5dv_obj obj;
1338 assert(!rxq_ctrl->obj);
1339 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1340 return mlx5_rxq_obj_hairpin_new(dev, idx);
1341 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1342 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1343 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1347 "port %u Rx queue %u cannot allocate verbs resources",
1348 dev->data->port_id, rxq_data->idx);
1353 tmpl->rxq_ctrl = rxq_ctrl;
1354 if (rxq_ctrl->irq) {
1355 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1356 if (!tmpl->channel) {
1357 DRV_LOG(ERR, "port %u: comp channel creation failure",
1358 dev->data->port_id);
1363 if (mlx5_rxq_mprq_enabled(rxq_data))
1364 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1367 tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1369 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1370 dev->data->port_id, idx);
1374 obj.cq.in = tmpl->cq;
1375 obj.cq.out = &cq_info;
1376 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1381 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1383 "port %u wrong MLX5_CQE_SIZE environment variable"
1384 " value: it should be set to %u",
1385 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1389 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1390 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1391 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1392 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1393 /* Allocate door-bell for types created with DevX. */
1394 if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1395 struct mlx5_devx_dbr_page *dbr_page;
1398 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1401 rxq_ctrl->dbr_offset = dbr_offset;
1402 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1403 rxq_ctrl->dbr_umem_id_valid = 1;
1404 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1405 (uintptr_t)rxq_ctrl->dbr_offset);
1407 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1408 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1411 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1412 dev->data->port_id, idx);
1416 /* Change queue state to ready. */
1417 mod = (struct ibv_wq_attr){
1418 .attr_mask = IBV_WQ_ATTR_STATE,
1419 .wq_state = IBV_WQS_RDY,
1421 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1424 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1425 " failed", dev->data->port_id, idx);
1429 obj.rwq.in = tmpl->wq;
1431 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1436 rxq_data->wqes = rwq.buf;
1437 rxq_data->rq_db = rwq.dbrec;
1438 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1439 struct mlx5_devx_modify_rq_attr rq_attr;
1441 memset(&rq_attr, 0, sizeof(rq_attr));
1442 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1444 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1445 dev->data->port_id, idx);
1449 /* Change queue state to ready. */
1450 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1451 rq_attr.state = MLX5_RQC_STATE_RDY;
1452 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1456 /* Fill the rings. */
1457 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1458 rxq_data->cq_db = cq_info.dbrec;
1459 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1460 rxq_data->cq_uar = cq_info.cq_uar;
1461 rxq_data->cqn = cq_info.cqn;
1462 rxq_data->cq_arm_sn = 0;
1463 mlx5_rxq_initialize(rxq_data);
1464 rxq_data->cq_ci = 0;
1465 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1466 idx, (void *)&tmpl);
1467 rte_atomic32_inc(&tmpl->refcnt);
1468 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1469 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1473 ret = rte_errno; /* Save rte_errno before cleanup. */
1474 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1475 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1476 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1477 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1479 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1481 claim_zero(mlx5_glue->destroy_comp_channel
1484 rte_errno = ret; /* Restore rte_errno. */
1486 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1487 rxq_release_rq_resources(rxq_ctrl);
1488 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1493 * Verify the Rx queue objects list is empty
1496 * Pointer to Ethernet device.
1499 * The number of objects not released.
1502 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1504 struct mlx5_priv *priv = dev->data->dev_private;
1506 struct mlx5_rxq_obj *rxq_obj;
1508 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1509 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1510 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1517 * Callback function to initialize mbufs for Multi-Packet RQ.
1520 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1521 void *_m, unsigned int i __rte_unused)
1523 struct mlx5_mprq_buf *buf = _m;
1524 struct rte_mbuf_ext_shared_info *shinfo;
1525 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1528 memset(_m, 0, sizeof(*buf));
1530 rte_atomic16_set(&buf->refcnt, 1);
1531 for (j = 0; j != strd_n; ++j) {
1532 shinfo = &buf->shinfos[j];
1533 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1534 shinfo->fcb_opaque = buf;
1539 * Free mempool of Multi-Packet RQ.
1542 * Pointer to Ethernet device.
1545 * 0 on success, negative errno value on failure.
1548 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1550 struct mlx5_priv *priv = dev->data->dev_private;
1551 struct rte_mempool *mp = priv->mprq_mp;
1556 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1557 dev->data->port_id, mp->name);
1559 * If a buffer in the pool has been externally attached to a mbuf and it
1560 * is still in use by application, destroying the Rx queue can spoil
1561 * the packet. It is unlikely to happen but if application dynamically
1562 * creates and destroys with holding Rx packets, this can happen.
1564 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1565 * RQ isn't provided by application but managed by PMD.
1567 if (!rte_mempool_full(mp)) {
1569 "port %u mempool for Multi-Packet RQ is still in use",
1570 dev->data->port_id);
1574 rte_mempool_free(mp);
1575 /* Unset mempool for each Rx queue. */
1576 for (i = 0; i != priv->rxqs_n; ++i) {
1577 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1581 rxq->mprq_mp = NULL;
1583 priv->mprq_mp = NULL;
1588 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1589 * mempool. If already allocated, reuse it if there're enough elements.
1590 * Otherwise, resize it.
1593 * Pointer to Ethernet device.
1596 * 0 on success, negative errno value on failure.
1599 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1601 struct mlx5_priv *priv = dev->data->dev_private;
1602 struct rte_mempool *mp = priv->mprq_mp;
1603 char name[RTE_MEMPOOL_NAMESIZE];
1604 unsigned int desc = 0;
1605 unsigned int buf_len;
1606 unsigned int obj_num;
1607 unsigned int obj_size;
1608 unsigned int strd_num_n = 0;
1609 unsigned int strd_sz_n = 0;
1611 unsigned int n_ibv = 0;
1613 if (!mlx5_mprq_enabled(dev))
1615 /* Count the total number of descriptors configured. */
1616 for (i = 0; i != priv->rxqs_n; ++i) {
1617 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1618 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1619 (rxq, struct mlx5_rxq_ctrl, rxq);
1621 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1624 desc += 1 << rxq->elts_n;
1625 /* Get the max number of strides. */
1626 if (strd_num_n < rxq->strd_num_n)
1627 strd_num_n = rxq->strd_num_n;
1628 /* Get the max size of a stride. */
1629 if (strd_sz_n < rxq->strd_sz_n)
1630 strd_sz_n = rxq->strd_sz_n;
1632 assert(strd_num_n && strd_sz_n);
1633 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1634 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1635 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1637 * Received packets can be either memcpy'd or externally referenced. In
1638 * case that the packet is attached to an mbuf as an external buffer, as
1639 * it isn't possible to predict how the buffers will be queued by
1640 * application, there's no option to exactly pre-allocate needed buffers
1641 * in advance but to speculatively prepares enough buffers.
1643 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1644 * received packets to buffers provided by application (rxq->mp) until
1645 * this Mempool gets available again.
1648 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1650 * rte_mempool_create_empty() has sanity check to refuse large cache
1651 * size compared to the number of elements.
1652 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1653 * constant number 2 instead.
1655 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1656 /* Check a mempool is already allocated and if it can be resued. */
1657 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1658 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1659 dev->data->port_id, mp->name);
1662 } else if (mp != NULL) {
1663 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1664 dev->data->port_id, mp->name);
1666 * If failed to free, which means it may be still in use, no way
1667 * but to keep using the existing one. On buffer underrun,
1668 * packets will be memcpy'd instead of external buffer
1671 if (mlx5_mprq_free_mp(dev)) {
1672 if (mp->elt_size >= obj_size)
1678 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1679 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1680 0, NULL, NULL, mlx5_mprq_buf_init,
1681 (void *)(uintptr_t)(1 << strd_num_n),
1682 dev->device->numa_node, 0);
1685 "port %u failed to allocate a mempool for"
1686 " Multi-Packet RQ, count=%u, size=%u",
1687 dev->data->port_id, obj_num, obj_size);
1693 /* Set mempool for each Rx queue. */
1694 for (i = 0; i != priv->rxqs_n; ++i) {
1695 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1696 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1697 (rxq, struct mlx5_rxq_ctrl, rxq);
1699 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1703 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1704 dev->data->port_id);
1708 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1709 sizeof(struct rte_vlan_hdr) * 2 + \
1710 sizeof(struct rte_ipv6_hdr)))
1711 #define MAX_TCP_OPTION_SIZE 40u
1712 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1713 sizeof(struct rte_tcp_hdr) + \
1714 MAX_TCP_OPTION_SIZE))
1717 * Adjust the maximum LRO massage size.
1720 * Pointer to Ethernet device.
1723 * @param max_lro_size
1724 * The maximum size for LRO packet.
1727 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1728 uint32_t max_lro_size)
1730 struct mlx5_priv *priv = dev->data->dev_private;
1732 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1733 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1734 MLX5_MAX_TCP_HDR_OFFSET)
1735 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1736 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1737 assert(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1738 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1739 if (priv->max_lro_msg_size)
1740 priv->max_lro_msg_size =
1741 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1743 priv->max_lro_msg_size = max_lro_size;
1745 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1746 dev->data->port_id, idx,
1747 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1751 * Create a DPDK Rx queue.
1754 * Pointer to Ethernet device.
1758 * Number of descriptors to configure in queue.
1760 * NUMA socket on which memory must be allocated.
1763 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1765 struct mlx5_rxq_ctrl *
1766 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1767 unsigned int socket, const struct rte_eth_rxconf *conf,
1768 struct rte_mempool *mp)
1770 struct mlx5_priv *priv = dev->data->dev_private;
1771 struct mlx5_rxq_ctrl *tmpl;
1772 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1773 unsigned int mprq_stride_size;
1774 struct mlx5_dev_config *config = &priv->config;
1775 unsigned int strd_headroom_en;
1777 * Always allocate extra slots, even if eventually
1778 * the vector Rx will not be used.
1781 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1782 uint64_t offloads = conf->offloads |
1783 dev->data->dev_conf.rxmode.offloads;
1784 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1785 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1786 unsigned int max_rx_pkt_len = lro_on_queue ?
1787 dev->data->dev_conf.rxmode.max_lro_pkt_size :
1788 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1789 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1790 RTE_PKTMBUF_HEADROOM;
1791 unsigned int max_lro_size = 0;
1792 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1794 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1795 DEV_RX_OFFLOAD_SCATTER)) {
1796 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1797 " configured and no enough mbuf space(%u) to contain "
1798 "the maximum RX packet length(%u) with head-room(%u)",
1799 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1800 RTE_PKTMBUF_HEADROOM);
1804 tmpl = rte_calloc_socket("RXQ", 1,
1806 desc_n * sizeof(struct rte_mbuf *),
1812 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1813 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1814 MLX5_MR_BTREE_CACHE_N, socket)) {
1815 /* rte_errno is already set. */
1818 tmpl->socket = socket;
1819 if (dev->data->dev_conf.intr_conf.rxq)
1822 * LRO packet may consume all the stride memory, hence we cannot
1823 * guaranty head-room near the packet memory in the stride.
1824 * In this case scatter is, for sure, enabled and an empty mbuf may be
1825 * added in the start for the head-room.
1827 if (lro_on_queue && RTE_PKTMBUF_HEADROOM > 0 &&
1828 non_scatter_min_mbuf_size > mb_len) {
1829 strd_headroom_en = 0;
1830 mprq_stride_size = RTE_MIN(max_rx_pkt_len,
1831 1u << config->mprq.max_stride_size_n);
1833 strd_headroom_en = 1;
1834 mprq_stride_size = non_scatter_min_mbuf_size;
1837 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1838 * following conditions are met:
1839 * - MPRQ is enabled.
1840 * - The number of descs is more than the number of strides.
1841 * - max_rx_pkt_len plus overhead is less than the max size of a
1843 * Otherwise, enable Rx scatter if necessary.
1846 desc > (1U << config->mprq.stride_num_n) &&
1847 mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1848 /* TODO: Rx scatter isn't supported yet. */
1849 tmpl->rxq.sges_n = 0;
1850 /* Trim the number of descs needed. */
1851 desc >>= config->mprq.stride_num_n;
1852 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1853 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1854 config->mprq.min_stride_size_n);
1855 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1856 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1857 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1858 config->mprq.max_memcpy_len);
1859 max_lro_size = RTE_MIN(max_rx_pkt_len,
1860 (1u << tmpl->rxq.strd_num_n) *
1861 (1u << tmpl->rxq.strd_sz_n));
1863 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1864 " strd_num_n = %u, strd_sz_n = %u",
1865 dev->data->port_id, idx,
1866 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1867 } else if (max_rx_pkt_len <= first_mb_free_size) {
1868 tmpl->rxq.sges_n = 0;
1869 max_lro_size = max_rx_pkt_len;
1870 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1871 unsigned int size = non_scatter_min_mbuf_size;
1872 unsigned int sges_n;
1874 if (lro_on_queue && first_mb_free_size <
1875 MLX5_MAX_LRO_HEADER_FIX) {
1876 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1877 " to include the max header size(%u) for LRO",
1878 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1879 rte_errno = ENOTSUP;
1883 * Determine the number of SGEs needed for a full packet
1884 * and round it to the next power of two.
1886 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1887 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1889 "port %u too many SGEs (%u) needed to handle"
1890 " requested maximum packet size %u, the maximum"
1891 " supported are %u", dev->data->port_id,
1892 1 << sges_n, max_rx_pkt_len,
1893 1u << MLX5_MAX_LOG_RQ_SEGS);
1894 rte_errno = ENOTSUP;
1897 tmpl->rxq.sges_n = sges_n;
1898 max_lro_size = max_rx_pkt_len;
1900 if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1902 "port %u MPRQ is requested but cannot be enabled"
1903 " (requested: desc = %u, stride_sz = %u,"
1904 " supported: min_stride_num = %u, max_stride_sz = %u).",
1905 dev->data->port_id, desc, mprq_stride_size,
1906 (1 << config->mprq.stride_num_n),
1907 (1 << config->mprq.max_stride_size_n));
1908 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1909 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1910 if (desc % (1 << tmpl->rxq.sges_n)) {
1912 "port %u number of Rx queue descriptors (%u) is not a"
1913 " multiple of SGEs per packet (%u)",
1916 1 << tmpl->rxq.sges_n);
1920 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1921 /* Toggle RX checksum offload if hardware supports it. */
1922 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1923 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1924 /* Configure VLAN stripping. */
1925 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1926 /* By default, FCS (CRC) is stripped by hardware. */
1927 tmpl->rxq.crc_present = 0;
1928 tmpl->rxq.lro = lro_on_queue;
1929 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1930 if (config->hw_fcs_strip) {
1932 * RQs used for LRO-enabled TIRs should not be
1933 * configured to scatter the FCS.
1937 "port %u CRC stripping has been "
1938 "disabled but will still be performed "
1939 "by hardware, because LRO is enabled",
1940 dev->data->port_id);
1942 tmpl->rxq.crc_present = 1;
1945 "port %u CRC stripping has been disabled but will"
1946 " still be performed by hardware, make sure MLNX_OFED"
1947 " and firmware are up to date",
1948 dev->data->port_id);
1952 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1953 " incoming frames to hide it",
1955 tmpl->rxq.crc_present ? "disabled" : "enabled",
1956 tmpl->rxq.crc_present << 2);
1958 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1959 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1960 tmpl->rxq.port_id = dev->data->port_id;
1963 tmpl->rxq.elts_n = log2above(desc);
1964 tmpl->rxq.rq_repl_thresh =
1965 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1967 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1969 tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1971 tmpl->rxq.idx = idx;
1972 rte_atomic32_inc(&tmpl->refcnt);
1973 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1981 * Create a DPDK Rx hairpin queue.
1984 * Pointer to Ethernet device.
1988 * Number of descriptors to configure in queue.
1989 * @param hairpin_conf
1990 * The hairpin binding configuration.
1993 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1995 struct mlx5_rxq_ctrl *
1996 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1997 const struct rte_eth_hairpin_conf *hairpin_conf)
1999 struct mlx5_priv *priv = dev->data->dev_private;
2000 struct mlx5_rxq_ctrl *tmpl;
2002 tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
2007 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2008 tmpl->socket = SOCKET_ID_ANY;
2009 tmpl->rxq.rss_hash = 0;
2010 tmpl->rxq.port_id = dev->data->port_id;
2012 tmpl->rxq.mp = NULL;
2013 tmpl->rxq.elts_n = log2above(desc);
2014 tmpl->rxq.elts = NULL;
2015 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2016 tmpl->hairpin_conf = *hairpin_conf;
2017 tmpl->rxq.idx = idx;
2018 rte_atomic32_inc(&tmpl->refcnt);
2019 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2027 * Pointer to Ethernet device.
2032 * A pointer to the queue if it exists, NULL otherwise.
2034 struct mlx5_rxq_ctrl *
2035 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2037 struct mlx5_priv *priv = dev->data->dev_private;
2038 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2040 if ((*priv->rxqs)[idx]) {
2041 rxq_ctrl = container_of((*priv->rxqs)[idx],
2042 struct mlx5_rxq_ctrl,
2044 mlx5_rxq_obj_get(dev, idx);
2045 rte_atomic32_inc(&rxq_ctrl->refcnt);
2051 * Release a Rx queue.
2054 * Pointer to Ethernet device.
2059 * 1 while a reference on it exists, 0 when freed.
2062 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2064 struct mlx5_priv *priv = dev->data->dev_private;
2065 struct mlx5_rxq_ctrl *rxq_ctrl;
2067 if (!(*priv->rxqs)[idx])
2069 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2070 assert(rxq_ctrl->priv);
2071 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2072 rxq_ctrl->obj = NULL;
2073 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2074 if (rxq_ctrl->dbr_umem_id_valid)
2075 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
2076 rxq_ctrl->dbr_offset));
2077 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2078 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2079 LIST_REMOVE(rxq_ctrl, next);
2081 (*priv->rxqs)[idx] = NULL;
2088 * Verify the Rx Queue list is empty
2091 * Pointer to Ethernet device.
2094 * The number of object not released.
2097 mlx5_rxq_verify(struct rte_eth_dev *dev)
2099 struct mlx5_priv *priv = dev->data->dev_private;
2100 struct mlx5_rxq_ctrl *rxq_ctrl;
2103 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2104 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2105 dev->data->port_id, rxq_ctrl->rxq.idx);
2112 * Get a Rx queue type.
2115 * Pointer to Ethernet device.
2120 * The Rx queue type.
2123 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2125 struct mlx5_priv *priv = dev->data->dev_private;
2126 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2128 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2129 rxq_ctrl = container_of((*priv->rxqs)[idx],
2130 struct mlx5_rxq_ctrl,
2132 return rxq_ctrl->type;
2134 return MLX5_RXQ_TYPE_UNDEFINED;
2138 * Create an indirection table.
2141 * Pointer to Ethernet device.
2143 * Queues entering in the indirection table.
2145 * Number of queues in the array.
2148 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2150 static struct mlx5_ind_table_obj *
2151 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2152 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2154 struct mlx5_priv *priv = dev->data->dev_private;
2155 struct mlx5_ind_table_obj *ind_tbl;
2156 unsigned int i = 0, j = 0, k = 0;
2158 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2159 queues_n * sizeof(uint16_t), 0);
2164 ind_tbl->type = type;
2165 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2166 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2167 log2above(queues_n) :
2168 log2above(priv->config.ind_table_max_size);
2169 struct ibv_wq *wq[1 << wq_n];
2171 for (i = 0; i != queues_n; ++i) {
2172 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2176 wq[i] = rxq->obj->wq;
2177 ind_tbl->queues[i] = queues[i];
2179 ind_tbl->queues_n = queues_n;
2180 /* Finalise indirection table. */
2181 k = i; /* Retain value of i for use in error case. */
2182 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2184 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2186 &(struct ibv_rwq_ind_table_init_attr){
2187 .log_ind_tbl_size = wq_n,
2191 if (!ind_tbl->ind_table) {
2195 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2196 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2197 const unsigned int rqt_n =
2198 1 << (rte_is_power_of_2(queues_n) ?
2199 log2above(queues_n) :
2200 log2above(priv->config.ind_table_max_size));
2202 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2203 rqt_n * sizeof(uint32_t), 0);
2205 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2206 dev->data->port_id);
2210 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2211 rqt_attr->rqt_actual_size = rqt_n;
2212 for (i = 0; i != queues_n; ++i) {
2213 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2217 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2218 ind_tbl->queues[i] = queues[i];
2220 k = i; /* Retain value of i for use in error case. */
2221 for (j = 0; k != rqt_n; ++k, ++j)
2222 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2223 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2226 if (!ind_tbl->rqt) {
2227 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2228 dev->data->port_id);
2232 ind_tbl->queues_n = queues_n;
2234 rte_atomic32_inc(&ind_tbl->refcnt);
2235 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2238 for (j = 0; j < i; j++)
2239 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2241 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2246 * Get an indirection table.
2249 * Pointer to Ethernet device.
2251 * Queues entering in the indirection table.
2253 * Number of queues in the array.
2256 * An indirection table if found.
2258 static struct mlx5_ind_table_obj *
2259 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2262 struct mlx5_priv *priv = dev->data->dev_private;
2263 struct mlx5_ind_table_obj *ind_tbl;
2265 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2266 if ((ind_tbl->queues_n == queues_n) &&
2267 (memcmp(ind_tbl->queues, queues,
2268 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2275 rte_atomic32_inc(&ind_tbl->refcnt);
2276 for (i = 0; i != ind_tbl->queues_n; ++i)
2277 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2283 * Release an indirection table.
2286 * Pointer to Ethernet device.
2288 * Indirection table to release.
2291 * 1 while a reference on it exists, 0 when freed.
2294 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2295 struct mlx5_ind_table_obj *ind_tbl)
2299 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2300 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2301 claim_zero(mlx5_glue->destroy_rwq_ind_table
2302 (ind_tbl->ind_table));
2303 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2304 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2306 for (i = 0; i != ind_tbl->queues_n; ++i)
2307 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2308 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2309 LIST_REMOVE(ind_tbl, next);
2317 * Verify the Rx Queue list is empty
2320 * Pointer to Ethernet device.
2323 * The number of object not released.
2326 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2328 struct mlx5_priv *priv = dev->data->dev_private;
2329 struct mlx5_ind_table_obj *ind_tbl;
2332 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2334 "port %u indirection table obj %p still referenced",
2335 dev->data->port_id, (void *)ind_tbl);
2342 * Create an Rx Hash queue.
2345 * Pointer to Ethernet device.
2347 * RSS key for the Rx hash queue.
2348 * @param rss_key_len
2350 * @param hash_fields
2351 * Verbs protocol hash field to make the RSS on.
2353 * Queues entering in hash queue. In case of empty hash_fields only the
2354 * first queue index will be taken for the indirection table.
2361 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2364 mlx5_hrxq_new(struct rte_eth_dev *dev,
2365 const uint8_t *rss_key, uint32_t rss_key_len,
2366 uint64_t hash_fields,
2367 const uint16_t *queues, uint32_t queues_n,
2368 int tunnel __rte_unused)
2370 struct mlx5_priv *priv = dev->data->dev_private;
2371 struct mlx5_hrxq *hrxq;
2372 struct ibv_qp *qp = NULL;
2373 struct mlx5_ind_table_obj *ind_tbl;
2375 struct mlx5_devx_obj *tir = NULL;
2376 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2377 struct mlx5_rxq_ctrl *rxq_ctrl =
2378 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2380 queues_n = hash_fields ? queues_n : 1;
2381 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2383 enum mlx5_ind_tbl_type type;
2385 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2386 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2387 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2393 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2394 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2395 struct mlx5dv_qp_init_attr qp_init_attr;
2397 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2399 qp_init_attr.comp_mask =
2400 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2401 qp_init_attr.create_flags =
2402 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2404 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2405 if (dev->data->dev_conf.lpbk_mode) {
2407 * Allow packet sent from NIC loop back
2408 * w/o source MAC check.
2410 qp_init_attr.comp_mask |=
2411 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2412 qp_init_attr.create_flags |=
2413 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2416 qp = mlx5_glue->dv_create_qp
2418 &(struct ibv_qp_init_attr_ex){
2419 .qp_type = IBV_QPT_RAW_PACKET,
2421 IBV_QP_INIT_ATTR_PD |
2422 IBV_QP_INIT_ATTR_IND_TABLE |
2423 IBV_QP_INIT_ATTR_RX_HASH,
2424 .rx_hash_conf = (struct ibv_rx_hash_conf){
2426 IBV_RX_HASH_FUNC_TOEPLITZ,
2427 .rx_hash_key_len = rss_key_len,
2429 (void *)(uintptr_t)rss_key,
2430 .rx_hash_fields_mask = hash_fields,
2432 .rwq_ind_tbl = ind_tbl->ind_table,
2437 qp = mlx5_glue->create_qp_ex
2439 &(struct ibv_qp_init_attr_ex){
2440 .qp_type = IBV_QPT_RAW_PACKET,
2442 IBV_QP_INIT_ATTR_PD |
2443 IBV_QP_INIT_ATTR_IND_TABLE |
2444 IBV_QP_INIT_ATTR_RX_HASH,
2445 .rx_hash_conf = (struct ibv_rx_hash_conf){
2447 IBV_RX_HASH_FUNC_TOEPLITZ,
2448 .rx_hash_key_len = rss_key_len,
2450 (void *)(uintptr_t)rss_key,
2451 .rx_hash_fields_mask = hash_fields,
2453 .rwq_ind_tbl = ind_tbl->ind_table,
2461 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2462 struct mlx5_devx_tir_attr tir_attr;
2463 struct mlx5_rx_hash_field_select *rx_hash_field_select;
2467 /* Enable TIR LRO only if all the queues were configured for. */
2468 for (i = 0; i < queues_n; ++i) {
2469 if (!(*priv->rxqs)[queues[i]]->lro) {
2474 memset(&tir_attr, 0, sizeof(tir_attr));
2475 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2476 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2477 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2478 tir_attr.tunneled_offload_en = !!tunnel;
2479 /* Translate hash_fields bitmap to PRM format. */
2480 rx_hash_field_select = hash_fields & IBV_RX_HASH_INNER ?
2481 &tir_attr.rx_hash_field_selector_inner :
2482 &tir_attr.rx_hash_field_selector_outer;
2484 rx_hash_field_select = &tir_attr.rx_hash_field_selector_outer;
2486 /* 1 bit: 0: IPv4, 1: IPv6. */
2487 rx_hash_field_select->l3_prot_type =
2488 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2489 /* 1 bit: 0: TCP, 1: UDP. */
2490 rx_hash_field_select->l4_prot_type =
2491 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2492 /* Bitmask which sets which fields to use in RX Hash. */
2493 rx_hash_field_select->selected_fields =
2494 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2495 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2496 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2497 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2498 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2499 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2500 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2501 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2502 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2503 tir_attr.transport_domain = priv->sh->td->id;
2505 tir_attr.transport_domain = priv->sh->tdn;
2506 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2507 tir_attr.indirect_table = ind_tbl->rqt->id;
2508 if (dev->data->dev_conf.lpbk_mode)
2509 tir_attr.self_lb_block =
2510 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2512 tir_attr.lro_timeout_period_usecs =
2513 priv->config.lro.timeout;
2514 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2515 tir_attr.lro_enable_mask =
2516 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2517 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2519 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2521 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2522 dev->data->port_id);
2527 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2530 hrxq->ind_table = ind_tbl;
2531 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2533 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2535 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2536 if (!hrxq->action) {
2541 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2543 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2544 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2546 if (!hrxq->action) {
2552 hrxq->rss_key_len = rss_key_len;
2553 hrxq->hash_fields = hash_fields;
2554 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2555 rte_atomic32_inc(&hrxq->refcnt);
2556 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2559 err = rte_errno; /* Save rte_errno before cleanup. */
2560 mlx5_ind_table_obj_release(dev, ind_tbl);
2562 claim_zero(mlx5_glue->destroy_qp(qp));
2564 claim_zero(mlx5_devx_cmd_destroy(tir));
2565 rte_errno = err; /* Restore rte_errno. */
2570 * Get an Rx Hash queue.
2573 * Pointer to Ethernet device.
2575 * RSS configuration for the Rx hash queue.
2577 * Queues entering in hash queue. In case of empty hash_fields only the
2578 * first queue index will be taken for the indirection table.
2583 * An hash Rx queue on success.
2586 mlx5_hrxq_get(struct rte_eth_dev *dev,
2587 const uint8_t *rss_key, uint32_t rss_key_len,
2588 uint64_t hash_fields,
2589 const uint16_t *queues, uint32_t queues_n)
2591 struct mlx5_priv *priv = dev->data->dev_private;
2592 struct mlx5_hrxq *hrxq;
2594 queues_n = hash_fields ? queues_n : 1;
2595 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2596 struct mlx5_ind_table_obj *ind_tbl;
2598 if (hrxq->rss_key_len != rss_key_len)
2600 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2602 if (hrxq->hash_fields != hash_fields)
2604 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2607 if (ind_tbl != hrxq->ind_table) {
2608 mlx5_ind_table_obj_release(dev, ind_tbl);
2611 rte_atomic32_inc(&hrxq->refcnt);
2618 * Release the hash Rx queue.
2621 * Pointer to Ethernet device.
2623 * Pointer to Hash Rx queue to release.
2626 * 1 while a reference on it exists, 0 when freed.
2629 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2631 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2632 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2633 mlx5_glue->destroy_flow_action(hrxq->action);
2635 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2636 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2637 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2638 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2639 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2640 LIST_REMOVE(hrxq, next);
2644 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2649 * Verify the Rx Queue list is empty
2652 * Pointer to Ethernet device.
2655 * The number of object not released.
2658 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2660 struct mlx5_priv *priv = dev->data->dev_private;
2661 struct mlx5_hrxq *hrxq;
2664 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2666 "port %u hash Rx queue %p still referenced",
2667 dev->data->port_id, (void *)hrxq);
2674 * Create a drop Rx queue Verbs/DevX object.
2677 * Pointer to Ethernet device.
2680 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2682 static struct mlx5_rxq_obj *
2683 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2685 struct mlx5_priv *priv = dev->data->dev_private;
2686 struct ibv_context *ctx = priv->sh->ctx;
2688 struct ibv_wq *wq = NULL;
2689 struct mlx5_rxq_obj *rxq;
2691 if (priv->drop_queue.rxq)
2692 return priv->drop_queue.rxq;
2693 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2695 DEBUG("port %u cannot allocate CQ for drop queue",
2696 dev->data->port_id);
2700 wq = mlx5_glue->create_wq(ctx,
2701 &(struct ibv_wq_init_attr){
2702 .wq_type = IBV_WQT_RQ,
2709 DEBUG("port %u cannot allocate WQ for drop queue",
2710 dev->data->port_id);
2714 rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2716 DEBUG("port %u cannot allocate drop Rx queue memory",
2717 dev->data->port_id);
2723 priv->drop_queue.rxq = rxq;
2727 claim_zero(mlx5_glue->destroy_wq(wq));
2729 claim_zero(mlx5_glue->destroy_cq(cq));
2734 * Release a drop Rx queue Verbs/DevX object.
2737 * Pointer to Ethernet device.
2740 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2743 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2745 struct mlx5_priv *priv = dev->data->dev_private;
2746 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2749 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2751 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2753 priv->drop_queue.rxq = NULL;
2757 * Create a drop indirection table.
2760 * Pointer to Ethernet device.
2763 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2765 static struct mlx5_ind_table_obj *
2766 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2768 struct mlx5_priv *priv = dev->data->dev_private;
2769 struct mlx5_ind_table_obj *ind_tbl;
2770 struct mlx5_rxq_obj *rxq;
2771 struct mlx5_ind_table_obj tmpl;
2773 rxq = mlx5_rxq_obj_drop_new(dev);
2776 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2778 &(struct ibv_rwq_ind_table_init_attr){
2779 .log_ind_tbl_size = 0,
2780 .ind_tbl = &rxq->wq,
2783 if (!tmpl.ind_table) {
2784 DEBUG("port %u cannot allocate indirection table for drop"
2786 dev->data->port_id);
2790 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2795 ind_tbl->ind_table = tmpl.ind_table;
2798 mlx5_rxq_obj_drop_release(dev);
2803 * Release a drop indirection table.
2806 * Pointer to Ethernet device.
2809 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2811 struct mlx5_priv *priv = dev->data->dev_private;
2812 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2814 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2815 mlx5_rxq_obj_drop_release(dev);
2817 priv->drop_queue.hrxq->ind_table = NULL;
2821 * Create a drop Rx Hash queue.
2824 * Pointer to Ethernet device.
2827 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2830 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2832 struct mlx5_priv *priv = dev->data->dev_private;
2833 struct mlx5_ind_table_obj *ind_tbl = NULL;
2834 struct ibv_qp *qp = NULL;
2835 struct mlx5_hrxq *hrxq = NULL;
2837 if (priv->drop_queue.hrxq) {
2838 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2839 return priv->drop_queue.hrxq;
2841 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2844 "port %u cannot allocate memory for drop queue",
2845 dev->data->port_id);
2849 priv->drop_queue.hrxq = hrxq;
2850 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2853 hrxq->ind_table = ind_tbl;
2854 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2855 &(struct ibv_qp_init_attr_ex){
2856 .qp_type = IBV_QPT_RAW_PACKET,
2858 IBV_QP_INIT_ATTR_PD |
2859 IBV_QP_INIT_ATTR_IND_TABLE |
2860 IBV_QP_INIT_ATTR_RX_HASH,
2861 .rx_hash_conf = (struct ibv_rx_hash_conf){
2863 IBV_RX_HASH_FUNC_TOEPLITZ,
2864 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2865 .rx_hash_key = rss_hash_default_key,
2866 .rx_hash_fields_mask = 0,
2868 .rwq_ind_tbl = ind_tbl->ind_table,
2872 DEBUG("port %u cannot allocate QP for drop queue",
2873 dev->data->port_id);
2878 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2879 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2880 if (!hrxq->action) {
2885 rte_atomic32_set(&hrxq->refcnt, 1);
2888 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2889 if (hrxq && hrxq->action)
2890 mlx5_glue->destroy_flow_action(hrxq->action);
2893 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2895 mlx5_ind_table_obj_drop_release(dev);
2897 priv->drop_queue.hrxq = NULL;
2904 * Release a drop hash Rx queue.
2907 * Pointer to Ethernet device.
2910 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2912 struct mlx5_priv *priv = dev->data->dev_private;
2913 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2915 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2916 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2917 mlx5_glue->destroy_flow_action(hrxq->action);
2919 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2920 mlx5_ind_table_obj_drop_release(dev);
2922 priv->drop_queue.hrxq = NULL;