1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 #include <sys/queue.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
29 #include <rte_interrupts.h>
30 #include <rte_debug.h>
34 #include "mlx5_rxtx.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
38 #include "mlx5_glue.h"
40 /* Default RSS hash key also used for ConnectX-3. */
41 uint8_t rss_hash_default_key[] = {
42 0x2c, 0xc6, 0x81, 0xd1,
43 0x5b, 0xdb, 0xf4, 0xf7,
44 0xfc, 0xa2, 0x83, 0x19,
45 0xdb, 0x1a, 0x3e, 0x94,
46 0x6b, 0x9e, 0x38, 0xd9,
47 0x2c, 0x9c, 0x03, 0xd1,
48 0xad, 0x99, 0x44, 0xa7,
49 0xd9, 0x56, 0x3d, 0x59,
50 0x06, 0x3c, 0x25, 0xf3,
51 0xfc, 0x1f, 0xdc, 0x2a,
54 /* Length of the default RSS hash key. */
55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
56 (unsigned int)sizeof(rss_hash_default_key),
57 "wrong RSS default key size.");
60 * Check whether Multi-Packet RQ can be enabled for the device.
63 * Pointer to Ethernet device.
66 * 1 if supported, negative errno value if not.
69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
71 struct mlx5_priv *priv = dev->data->dev_private;
73 if (priv->config.mprq.enabled &&
74 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
80 * Check whether Multi-Packet RQ is enabled for the Rx queue.
83 * Pointer to receive queue structure.
86 * 0 if disabled, otherwise enabled.
89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
91 return rxq->strd_num_n > 0;
95 * Check whether Multi-Packet RQ is enabled for the device.
96 * MPRQ can be enabled explicitly, or implicitly by enabling LRO.
99 * Pointer to Ethernet device.
102 * 0 if disabled, otherwise enabled.
105 mlx5_mprq_enabled(struct rte_eth_dev *dev)
107 struct mlx5_priv *priv = dev->data->dev_private;
111 if (mlx5_check_mprq_support(dev) < 0)
113 /* All the configured queues should be enabled. */
114 for (i = 0; i < priv->rxqs_n; ++i) {
115 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
119 if (mlx5_rxq_mprq_enabled(rxq))
122 /* Multi-Packet RQ can't be partially configured. */
123 assert(n == 0 || n == priv->rxqs_n);
124 return n == priv->rxqs_n;
128 * Check whether LRO is supported and enabled for the device.
131 * Pointer to Ethernet device.
134 * 0 if disabled, 1 if enabled.
137 mlx5_lro_on(struct rte_eth_dev *dev)
139 return (MLX5_LRO_SUPPORTED(dev) && MLX5_LRO_ENABLED(dev));
143 * Allocate RX queue elements for Multi-Packet RQ.
146 * Pointer to RX queue structure.
149 * 0 on success, a negative errno value otherwise and rte_errno is set.
152 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
154 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
155 unsigned int wqe_n = 1 << rxq->elts_n;
159 /* Iterate on segments. */
160 for (i = 0; i <= wqe_n; ++i) {
161 struct mlx5_mprq_buf *buf;
163 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
164 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
169 (*rxq->mprq_bufs)[i] = buf;
171 rxq->mprq_repl = buf;
174 "port %u Rx queue %u allocated and configured %u segments",
175 rxq->port_id, rxq->idx, wqe_n);
178 err = rte_errno; /* Save rte_errno before cleanup. */
180 for (i = 0; (i != wqe_n); ++i) {
181 if ((*rxq->mprq_bufs)[i] != NULL)
182 rte_mempool_put(rxq->mprq_mp,
183 (*rxq->mprq_bufs)[i]);
184 (*rxq->mprq_bufs)[i] = NULL;
186 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
187 rxq->port_id, rxq->idx);
188 rte_errno = err; /* Restore rte_errno. */
193 * Allocate RX queue elements for Single-Packet RQ.
196 * Pointer to RX queue structure.
199 * 0 on success, errno value on failure.
202 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
204 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
205 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
209 /* Iterate on segments. */
210 for (i = 0; (i != elts_n); ++i) {
211 struct rte_mbuf *buf;
213 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
215 DRV_LOG(ERR, "port %u empty mbuf pool",
216 PORT_ID(rxq_ctrl->priv));
220 /* Headroom is reserved by rte_pktmbuf_alloc(). */
221 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
222 /* Buffer is supposed to be empty. */
223 assert(rte_pktmbuf_data_len(buf) == 0);
224 assert(rte_pktmbuf_pkt_len(buf) == 0);
226 /* Only the first segment keeps headroom. */
228 SET_DATA_OFF(buf, 0);
229 PORT(buf) = rxq_ctrl->rxq.port_id;
230 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
231 PKT_LEN(buf) = DATA_LEN(buf);
233 (*rxq_ctrl->rxq.elts)[i] = buf;
235 /* If Rx vector is activated. */
236 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
237 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
238 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
241 /* Initialize default rearm_data for vPMD. */
242 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
243 rte_mbuf_refcnt_set(mbuf_init, 1);
244 mbuf_init->nb_segs = 1;
245 mbuf_init->port = rxq->port_id;
247 * prevent compiler reordering:
248 * rearm_data covers previous fields.
250 rte_compiler_barrier();
251 rxq->mbuf_initializer =
252 *(uint64_t *)&mbuf_init->rearm_data;
253 /* Padding with a fake mbuf for vectorized Rx. */
254 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
255 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
258 "port %u Rx queue %u allocated and configured %u segments"
260 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
261 elts_n / (1 << rxq_ctrl->rxq.sges_n));
264 err = rte_errno; /* Save rte_errno before cleanup. */
266 for (i = 0; (i != elts_n); ++i) {
267 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
268 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
269 (*rxq_ctrl->rxq.elts)[i] = NULL;
271 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
272 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
273 rte_errno = err; /* Restore rte_errno. */
278 * Allocate RX queue elements.
281 * Pointer to RX queue structure.
284 * 0 on success, errno value on failure.
287 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
289 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
290 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
294 * Free RX queue elements for Multi-Packet RQ.
297 * Pointer to RX queue structure.
300 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
302 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
305 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
306 rxq->port_id, rxq->idx);
307 if (rxq->mprq_bufs == NULL)
309 assert(mlx5_rxq_check_vec_support(rxq) < 0);
310 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
311 if ((*rxq->mprq_bufs)[i] != NULL)
312 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
313 (*rxq->mprq_bufs)[i] = NULL;
315 if (rxq->mprq_repl != NULL) {
316 mlx5_mprq_buf_free(rxq->mprq_repl);
317 rxq->mprq_repl = NULL;
322 * Free RX queue elements for Single-Packet RQ.
325 * Pointer to RX queue structure.
328 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
330 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
331 const uint16_t q_n = (1 << rxq->elts_n);
332 const uint16_t q_mask = q_n - 1;
333 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
336 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
337 PORT_ID(rxq_ctrl->priv), rxq->idx);
338 if (rxq->elts == NULL)
341 * Some mbuf in the Ring belongs to the application. They cannot be
344 if (mlx5_rxq_check_vec_support(rxq) > 0) {
345 for (i = 0; i < used; ++i)
346 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
347 rxq->rq_pi = rxq->rq_ci;
349 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
350 if ((*rxq->elts)[i] != NULL)
351 rte_pktmbuf_free_seg((*rxq->elts)[i]);
352 (*rxq->elts)[i] = NULL;
357 * Free RX queue elements.
360 * Pointer to RX queue structure.
363 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
365 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
366 rxq_free_elts_mprq(rxq_ctrl);
368 rxq_free_elts_sprq(rxq_ctrl);
372 * Returns the per-queue supported offloads.
375 * Pointer to Ethernet device.
378 * Supported Rx offloads.
381 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
383 struct mlx5_priv *priv = dev->data->dev_private;
384 struct mlx5_dev_config *config = &priv->config;
385 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
386 DEV_RX_OFFLOAD_TIMESTAMP |
387 DEV_RX_OFFLOAD_JUMBO_FRAME);
389 if (config->hw_fcs_strip)
390 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
393 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
394 DEV_RX_OFFLOAD_UDP_CKSUM |
395 DEV_RX_OFFLOAD_TCP_CKSUM);
396 if (config->hw_vlan_strip)
397 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
403 * Returns the per-port supported offloads.
406 * Pointer to Ethernet device.
409 * Supported Rx offloads.
412 mlx5_get_rx_port_offloads(struct rte_eth_dev *dev)
414 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
416 if (MLX5_LRO_SUPPORTED(dev))
417 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
422 * Verify if the queue can be released.
425 * Pointer to Ethernet device.
430 * 1 if the queue can be released
431 * 0 if the queue can not be released, there are references to it.
432 * Negative errno and rte_errno is set if queue doesn't exist.
435 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
437 struct mlx5_priv *priv = dev->data->dev_private;
438 struct mlx5_rxq_ctrl *rxq_ctrl;
440 if (!(*priv->rxqs)[idx]) {
444 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
445 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
451 * Pointer to Ethernet device structure.
455 * Number of descriptors to configure in queue.
457 * NUMA socket on which memory must be allocated.
459 * Thresholds parameters.
461 * Memory pool for buffer allocations.
464 * 0 on success, a negative errno value otherwise and rte_errno is set.
467 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
468 unsigned int socket, const struct rte_eth_rxconf *conf,
469 struct rte_mempool *mp)
471 struct mlx5_priv *priv = dev->data->dev_private;
472 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
473 struct mlx5_rxq_ctrl *rxq_ctrl =
474 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
476 if (!rte_is_power_of_2(desc)) {
477 desc = 1 << log2above(desc);
479 "port %u increased number of descriptors in Rx queue %u"
480 " to the next power of two (%d)",
481 dev->data->port_id, idx, desc);
483 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
484 dev->data->port_id, idx, desc);
485 if (idx >= priv->rxqs_n) {
486 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
487 dev->data->port_id, idx, priv->rxqs_n);
488 rte_errno = EOVERFLOW;
491 if (!mlx5_rxq_releasable(dev, idx)) {
492 DRV_LOG(ERR, "port %u unable to release queue index %u",
493 dev->data->port_id, idx);
497 mlx5_rxq_release(dev, idx);
498 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
500 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
501 dev->data->port_id, idx);
505 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
506 dev->data->port_id, idx);
507 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
512 * DPDK callback to release a RX queue.
515 * Generic RX queue pointer.
518 mlx5_rx_queue_release(void *dpdk_rxq)
520 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
521 struct mlx5_rxq_ctrl *rxq_ctrl;
522 struct mlx5_priv *priv;
526 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
527 priv = rxq_ctrl->priv;
528 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
529 rte_panic("port %u Rx queue %u is still used by a flow and"
530 " cannot be removed\n",
531 PORT_ID(priv), rxq->idx);
532 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
536 * Get an Rx queue Verbs/DevX object.
539 * Pointer to Ethernet device.
541 * Queue index in DPDK Rx queue array
544 * The Verbs/DevX object if it exists.
546 static struct mlx5_rxq_obj *
547 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
549 struct mlx5_priv *priv = dev->data->dev_private;
550 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
551 struct mlx5_rxq_ctrl *rxq_ctrl;
553 if (idx >= priv->rxqs_n)
557 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
559 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
560 return rxq_ctrl->obj;
564 * Release the resources allocated for an RQ DevX object.
567 * DevX Rx queue object.
570 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
572 if (rxq_ctrl->rxq.wqes) {
573 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
574 rxq_ctrl->rxq.wqes = NULL;
576 if (rxq_ctrl->wq_umem)
577 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
581 * Release an Rx verbs/DevX queue object.
584 * Verbs/DevX Rx queue object.
587 * 1 while a reference on it exists, 0 when freed.
590 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
593 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV)
596 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
597 rxq_free_elts(rxq_obj->rxq_ctrl);
598 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
599 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
600 } else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
601 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
602 rxq_release_rq_resources(rxq_obj->rxq_ctrl);
604 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
605 if (rxq_obj->channel)
606 claim_zero(mlx5_glue->destroy_comp_channel
608 LIST_REMOVE(rxq_obj, next);
616 * Allocate queue vector and fill epoll fd list for Rx interrupts.
619 * Pointer to Ethernet device.
622 * 0 on success, a negative errno value otherwise and rte_errno is set.
625 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
627 struct mlx5_priv *priv = dev->data->dev_private;
629 unsigned int rxqs_n = priv->rxqs_n;
630 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
631 unsigned int count = 0;
632 struct rte_intr_handle *intr_handle = dev->intr_handle;
634 if (!dev->data->dev_conf.intr_conf.rxq)
636 mlx5_rx_intr_vec_disable(dev);
637 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
638 if (intr_handle->intr_vec == NULL) {
640 "port %u failed to allocate memory for interrupt"
641 " vector, Rx interrupts will not be supported",
646 intr_handle->type = RTE_INTR_HANDLE_EXT;
647 for (i = 0; i != n; ++i) {
648 /* This rxq obj must not be released in this function. */
649 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
654 /* Skip queues that cannot request interrupts. */
655 if (!rxq_obj || !rxq_obj->channel) {
656 /* Use invalid intr_vec[] index to disable entry. */
657 intr_handle->intr_vec[i] =
658 RTE_INTR_VEC_RXTX_OFFSET +
659 RTE_MAX_RXTX_INTR_VEC_ID;
662 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
664 "port %u too many Rx queues for interrupt"
665 " vector size (%d), Rx interrupts cannot be"
667 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
668 mlx5_rx_intr_vec_disable(dev);
672 fd = rxq_obj->channel->fd;
673 flags = fcntl(fd, F_GETFL);
674 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
678 "port %u failed to make Rx interrupt file"
679 " descriptor %d non-blocking for queue index"
681 dev->data->port_id, fd, i);
682 mlx5_rx_intr_vec_disable(dev);
685 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
686 intr_handle->efds[count] = fd;
690 mlx5_rx_intr_vec_disable(dev);
692 intr_handle->nb_efd = count;
697 * Clean up Rx interrupts handler.
700 * Pointer to Ethernet device.
703 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
705 struct mlx5_priv *priv = dev->data->dev_private;
706 struct rte_intr_handle *intr_handle = dev->intr_handle;
708 unsigned int rxqs_n = priv->rxqs_n;
709 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
711 if (!dev->data->dev_conf.intr_conf.rxq)
713 if (!intr_handle->intr_vec)
715 for (i = 0; i != n; ++i) {
716 struct mlx5_rxq_ctrl *rxq_ctrl;
717 struct mlx5_rxq_data *rxq_data;
719 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
720 RTE_MAX_RXTX_INTR_VEC_ID)
723 * Need to access directly the queue to release the reference
724 * kept in mlx5_rx_intr_vec_enable().
726 rxq_data = (*priv->rxqs)[i];
727 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
729 mlx5_rxq_obj_release(rxq_ctrl->obj);
732 rte_intr_free_epoll_fd(intr_handle);
733 if (intr_handle->intr_vec)
734 free(intr_handle->intr_vec);
735 intr_handle->nb_efd = 0;
736 intr_handle->intr_vec = NULL;
740 * MLX5 CQ notification .
743 * Pointer to receive queue structure.
745 * Sequence number per receive queue .
748 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
751 uint32_t doorbell_hi;
753 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
755 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
756 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
757 doorbell = (uint64_t)doorbell_hi << 32;
758 doorbell |= rxq->cqn;
759 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
760 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
761 cq_db_reg, rxq->uar_lock_cq);
765 * DPDK callback for Rx queue interrupt enable.
768 * Pointer to Ethernet device structure.
773 * 0 on success, a negative errno value otherwise and rte_errno is set.
776 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
778 struct mlx5_priv *priv = dev->data->dev_private;
779 struct mlx5_rxq_data *rxq_data;
780 struct mlx5_rxq_ctrl *rxq_ctrl;
782 rxq_data = (*priv->rxqs)[rx_queue_id];
787 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
789 struct mlx5_rxq_obj *rxq_obj;
791 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
796 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
797 mlx5_rxq_obj_release(rxq_obj);
803 * DPDK callback for Rx queue interrupt disable.
806 * Pointer to Ethernet device structure.
811 * 0 on success, a negative errno value otherwise and rte_errno is set.
814 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
816 struct mlx5_priv *priv = dev->data->dev_private;
817 struct mlx5_rxq_data *rxq_data;
818 struct mlx5_rxq_ctrl *rxq_ctrl;
819 struct mlx5_rxq_obj *rxq_obj = NULL;
820 struct ibv_cq *ev_cq;
824 rxq_data = (*priv->rxqs)[rx_queue_id];
829 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
832 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
837 ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
838 if (ret || ev_cq != rxq_obj->cq) {
842 rxq_data->cq_arm_sn++;
843 mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
844 mlx5_rxq_obj_release(rxq_obj);
847 ret = rte_errno; /* Save rte_errno before cleanup. */
849 mlx5_rxq_obj_release(rxq_obj);
850 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
851 dev->data->port_id, rx_queue_id);
852 rte_errno = ret; /* Restore rte_errno. */
857 * Create a CQ Verbs object.
860 * Pointer to Ethernet device.
862 * Pointer to device private data.
864 * Pointer to Rx queue data.
866 * Number of CQEs in CQ.
868 * Pointer to Rx queue object data.
871 * The Verbs object initialised, NULL otherwise and rte_errno is set.
873 static struct ibv_cq *
874 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
875 struct mlx5_rxq_data *rxq_data,
876 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
879 struct ibv_cq_init_attr_ex ibv;
880 struct mlx5dv_cq_init_attr mlx5;
883 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
885 .channel = rxq_obj->channel,
888 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
891 if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
892 cq_attr.mlx5.comp_mask |=
893 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
894 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
895 cq_attr.mlx5.cqe_comp_res_format =
896 mlx5_rxq_mprq_enabled(rxq_data) ?
897 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
898 MLX5DV_CQE_RES_FORMAT_HASH;
900 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
903 * For vectorized Rx, it must not be doubled in order to
904 * make cq_ci and rq_ci aligned.
906 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
907 cq_attr.ibv.cqe *= 2;
908 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
910 "port %u Rx CQE compression is disabled for HW"
914 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
915 if (priv->config.cqe_pad) {
916 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
917 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
920 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
926 * Create a WQ Verbs object.
929 * Pointer to Ethernet device.
931 * Pointer to device private data.
933 * Pointer to Rx queue data.
935 * Queue index in DPDK Rx queue array
937 * Number of WQEs in WQ.
939 * Pointer to Rx queue object data.
942 * The Verbs object initialised, NULL otherwise and rte_errno is set.
944 static struct ibv_wq *
945 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
946 struct mlx5_rxq_data *rxq_data, uint16_t idx,
947 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
950 struct ibv_wq_init_attr ibv;
951 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
952 struct mlx5dv_wq_init_attr mlx5;
956 wq_attr.ibv = (struct ibv_wq_init_attr){
957 .wq_context = NULL, /* Could be useful in the future. */
958 .wq_type = IBV_WQT_RQ,
959 /* Max number of outstanding WRs. */
960 .max_wr = wqe_n >> rxq_data->sges_n,
961 /* Max number of scatter/gather elements in a WR. */
962 .max_sge = 1 << rxq_data->sges_n,
965 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
966 .create_flags = (rxq_data->vlan_strip ?
967 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
969 /* By default, FCS (CRC) is stripped by hardware. */
970 if (rxq_data->crc_present) {
971 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
972 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
974 if (priv->config.hw_padding) {
975 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
976 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
977 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
978 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
979 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
980 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
983 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
984 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
987 if (mlx5_rxq_mprq_enabled(rxq_data)) {
988 struct mlx5dv_striding_rq_init_attr *mprq_attr =
989 &wq_attr.mlx5.striding_rq_attrs;
991 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
992 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
993 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
994 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
995 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
998 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1001 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1005 * Make sure number of WRs*SGEs match expectations since a queue
1006 * cannot allocate more than "desc" buffers.
1008 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1009 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1011 "port %u Rx queue %u requested %u*%u but got"
1013 dev->data->port_id, idx,
1014 wqe_n >> rxq_data->sges_n,
1015 (1 << rxq_data->sges_n),
1016 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1017 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1026 * Fill common fields of create RQ attributes structure.
1029 * Pointer to Rx queue data.
1031 * CQ number to use with this RQ.
1033 * RQ attributes structure to fill..
1036 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1037 struct mlx5_devx_create_rq_attr *rq_attr)
1039 rq_attr->state = MLX5_RQC_STATE_RST;
1040 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1042 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1046 * Fill common fields of DevX WQ attributes structure.
1049 * Pointer to device private data.
1051 * Pointer to Rx queue control structure.
1053 * WQ attributes structure to fill..
1056 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1057 struct mlx5_devx_wq_attr *wq_attr)
1059 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1060 MLX5_WQ_END_PAD_MODE_ALIGN :
1061 MLX5_WQ_END_PAD_MODE_NONE;
1062 wq_attr->pd = priv->sh->pdn;
1063 wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1064 wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1065 wq_attr->dbr_umem_valid = 1;
1066 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1067 wq_attr->wq_umem_valid = 1;
1071 * Create a RQ object using DevX.
1074 * Pointer to Ethernet device.
1076 * Queue index in DPDK Rx queue array
1078 * CQ number to use with this RQ.
1081 * The DevX object initialised, NULL otherwise and rte_errno is set.
1083 static struct mlx5_devx_obj *
1084 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1086 struct mlx5_priv *priv = dev->data->dev_private;
1087 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1088 struct mlx5_rxq_ctrl *rxq_ctrl =
1089 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1090 struct mlx5_devx_create_rq_attr rq_attr;
1091 uint32_t wqe_n = 1 << rxq_data->elts_n;
1092 uint32_t wq_size = 0;
1093 uint32_t wqe_size = 0;
1094 uint32_t log_wqe_size = 0;
1096 struct mlx5_devx_obj *rq;
1098 memset(&rq_attr, 0, sizeof(rq_attr));
1099 /* Fill RQ attributes. */
1100 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1101 rq_attr.flush_in_error_en = 1;
1102 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1103 /* Fill WQ attributes for this RQ. */
1104 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1105 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1107 * Number of strides in each WQE:
1108 * 512*2^single_wqe_log_num_of_strides.
1110 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1111 rxq_data->strd_num_n -
1112 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1113 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1114 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1115 rxq_data->strd_sz_n -
1116 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1117 wqe_size = sizeof(struct mlx5_wqe_mprq);
1120 int num_scatter = 0;
1122 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1123 max_sge = 1 << rxq_data->sges_n;
1124 num_scatter = RTE_MAX(max_sge, 1);
1125 wqe_size = sizeof(struct mlx5_wqe_data_seg) * num_scatter;
1127 log_wqe_size = log2above(wqe_size);
1128 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1129 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n;
1130 /* Calculate and allocate WQ memory space. */
1131 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1132 wq_size = wqe_n * wqe_size;
1133 buf = rte_calloc_socket(__func__, 1, wq_size, RTE_CACHE_LINE_SIZE,
1137 rxq_data->wqes = buf;
1138 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1140 if (!rxq_ctrl->wq_umem) {
1144 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1145 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1147 rxq_release_rq_resources(rxq_ctrl);
1152 * Create the Rx queue Verbs/DevX object.
1155 * Pointer to Ethernet device.
1157 * Queue index in DPDK Rx queue array
1159 * Type of Rx queue object to create.
1162 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1164 struct mlx5_rxq_obj *
1165 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1166 enum mlx5_rxq_obj_type type)
1168 struct mlx5_priv *priv = dev->data->dev_private;
1169 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1170 struct mlx5_rxq_ctrl *rxq_ctrl =
1171 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1172 struct ibv_wq_attr mod;
1174 unsigned int wqe_n = 1 << rxq_data->elts_n;
1175 struct mlx5_rxq_obj *tmpl = NULL;
1176 struct mlx5dv_cq cq_info;
1177 struct mlx5dv_rwq rwq;
1179 struct mlx5dv_obj obj;
1182 assert(!rxq_ctrl->obj);
1183 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1184 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1185 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1189 "port %u Rx queue %u cannot allocate verbs resources",
1190 dev->data->port_id, rxq_data->idx);
1195 tmpl->rxq_ctrl = rxq_ctrl;
1196 if (rxq_ctrl->irq) {
1197 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1198 if (!tmpl->channel) {
1199 DRV_LOG(ERR, "port %u: comp channel creation failure",
1200 dev->data->port_id);
1205 if (mlx5_rxq_mprq_enabled(rxq_data))
1206 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1209 tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1211 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1212 dev->data->port_id, idx);
1216 obj.cq.in = tmpl->cq;
1217 obj.cq.out = &cq_info;
1218 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1223 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1225 "port %u wrong MLX5_CQE_SIZE environment variable"
1226 " value: it should be set to %u",
1227 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1231 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1232 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1233 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1234 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1235 /* Allocate door-bell for types created with DevX. */
1236 if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1237 struct mlx5_devx_dbr_page *dbr_page;
1240 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1243 rxq_ctrl->dbr_offset = dbr_offset;
1244 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1245 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1246 (uintptr_t)rxq_ctrl->dbr_offset);
1248 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1249 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1252 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1253 dev->data->port_id, idx);
1257 /* Change queue state to ready. */
1258 mod = (struct ibv_wq_attr){
1259 .attr_mask = IBV_WQ_ATTR_STATE,
1260 .wq_state = IBV_WQS_RDY,
1262 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1265 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1266 " failed", dev->data->port_id, idx);
1270 obj.rwq.in = tmpl->wq;
1272 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1277 rxq_data->wqes = rwq.buf;
1278 rxq_data->rq_db = rwq.dbrec;
1279 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1280 struct mlx5_devx_modify_rq_attr rq_attr;
1282 memset(&rq_attr, 0, sizeof(rq_attr));
1283 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1285 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1286 dev->data->port_id, idx);
1290 /* Change queue state to ready. */
1291 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1292 rq_attr.state = MLX5_RQC_STATE_RDY;
1293 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1297 /* Fill the rings. */
1298 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1299 rxq_data->cq_db = cq_info.dbrec;
1300 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1301 rxq_data->cq_uar = cq_info.cq_uar;
1302 rxq_data->cqn = cq_info.cqn;
1303 rxq_data->cq_arm_sn = 0;
1304 mlx5_rxq_initialize(rxq_data);
1305 rxq_data->cq_ci = 0;
1306 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1307 idx, (void *)&tmpl);
1308 rte_atomic32_inc(&tmpl->refcnt);
1309 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1310 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1314 ret = rte_errno; /* Save rte_errno before cleanup. */
1315 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1316 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1317 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1318 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1320 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1322 claim_zero(mlx5_glue->destroy_comp_channel
1325 rte_errno = ret; /* Restore rte_errno. */
1327 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1328 rxq_release_rq_resources(rxq_ctrl);
1329 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1334 * Verify the Rx queue objects list is empty
1337 * Pointer to Ethernet device.
1340 * The number of objects not released.
1343 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1345 struct mlx5_priv *priv = dev->data->dev_private;
1347 struct mlx5_rxq_obj *rxq_obj;
1349 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1350 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1351 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1358 * Callback function to initialize mbufs for Multi-Packet RQ.
1361 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1362 void *_m, unsigned int i __rte_unused)
1364 struct mlx5_mprq_buf *buf = _m;
1365 struct rte_mbuf_ext_shared_info *shinfo;
1366 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1369 memset(_m, 0, sizeof(*buf));
1371 rte_atomic16_set(&buf->refcnt, 1);
1372 for (j = 0; j != strd_n; ++j) {
1373 shinfo = &buf->shinfos[j];
1374 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1375 shinfo->fcb_opaque = buf;
1380 * Free mempool of Multi-Packet RQ.
1383 * Pointer to Ethernet device.
1386 * 0 on success, negative errno value on failure.
1389 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1391 struct mlx5_priv *priv = dev->data->dev_private;
1392 struct rte_mempool *mp = priv->mprq_mp;
1397 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1398 dev->data->port_id, mp->name);
1400 * If a buffer in the pool has been externally attached to a mbuf and it
1401 * is still in use by application, destroying the Rx queue can spoil
1402 * the packet. It is unlikely to happen but if application dynamically
1403 * creates and destroys with holding Rx packets, this can happen.
1405 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1406 * RQ isn't provided by application but managed by PMD.
1408 if (!rte_mempool_full(mp)) {
1410 "port %u mempool for Multi-Packet RQ is still in use",
1411 dev->data->port_id);
1415 rte_mempool_free(mp);
1416 /* Unset mempool for each Rx queue. */
1417 for (i = 0; i != priv->rxqs_n; ++i) {
1418 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1422 rxq->mprq_mp = NULL;
1424 priv->mprq_mp = NULL;
1429 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1430 * mempool. If already allocated, reuse it if there're enough elements.
1431 * Otherwise, resize it.
1434 * Pointer to Ethernet device.
1437 * 0 on success, negative errno value on failure.
1440 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1442 struct mlx5_priv *priv = dev->data->dev_private;
1443 struct rte_mempool *mp = priv->mprq_mp;
1444 char name[RTE_MEMPOOL_NAMESIZE];
1445 unsigned int desc = 0;
1446 unsigned int buf_len;
1447 unsigned int obj_num;
1448 unsigned int obj_size;
1449 unsigned int strd_num_n = 0;
1450 unsigned int strd_sz_n = 0;
1453 if (!mlx5_mprq_enabled(dev))
1455 /* Count the total number of descriptors configured. */
1456 for (i = 0; i != priv->rxqs_n; ++i) {
1457 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1461 desc += 1 << rxq->elts_n;
1462 /* Get the max number of strides. */
1463 if (strd_num_n < rxq->strd_num_n)
1464 strd_num_n = rxq->strd_num_n;
1465 /* Get the max size of a stride. */
1466 if (strd_sz_n < rxq->strd_sz_n)
1467 strd_sz_n = rxq->strd_sz_n;
1469 assert(strd_num_n && strd_sz_n);
1470 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1471 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1472 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1474 * Received packets can be either memcpy'd or externally referenced. In
1475 * case that the packet is attached to an mbuf as an external buffer, as
1476 * it isn't possible to predict how the buffers will be queued by
1477 * application, there's no option to exactly pre-allocate needed buffers
1478 * in advance but to speculatively prepares enough buffers.
1480 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1481 * received packets to buffers provided by application (rxq->mp) until
1482 * this Mempool gets available again.
1485 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1487 * rte_mempool_create_empty() has sanity check to refuse large cache
1488 * size compared to the number of elements.
1489 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1490 * constant number 2 instead.
1492 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1493 /* Check a mempool is already allocated and if it can be resued. */
1494 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1495 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1496 dev->data->port_id, mp->name);
1499 } else if (mp != NULL) {
1500 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1501 dev->data->port_id, mp->name);
1503 * If failed to free, which means it may be still in use, no way
1504 * but to keep using the existing one. On buffer underrun,
1505 * packets will be memcpy'd instead of external buffer
1508 if (mlx5_mprq_free_mp(dev)) {
1509 if (mp->elt_size >= obj_size)
1515 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1516 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1517 0, NULL, NULL, mlx5_mprq_buf_init,
1518 (void *)(uintptr_t)(1 << strd_num_n),
1519 dev->device->numa_node, 0);
1522 "port %u failed to allocate a mempool for"
1523 " Multi-Packet RQ, count=%u, size=%u",
1524 dev->data->port_id, obj_num, obj_size);
1530 /* Set mempool for each Rx queue. */
1531 for (i = 0; i != priv->rxqs_n; ++i) {
1532 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1538 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1539 dev->data->port_id);
1544 * Adjust the maximum LRO massage size.
1545 * LRO massage is contained in the MPRQ strides.
1546 * While the LRO massage size cannot be bigger than 65280 according to the
1547 * PRM, the strides which contain it may be bigger.
1548 * Adjust the maximum LRO massage size to avoid the above option.
1551 * Pointer to Ethernet device.
1553 * Number of strides per WQE..
1558 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint32_t strd_n,
1561 struct mlx5_priv *priv = dev->data->dev_private;
1562 uint32_t max_buf_len = strd_sz * strd_n;
1564 if (max_buf_len > (uint64_t)UINT16_MAX)
1565 max_buf_len = RTE_ALIGN_FLOOR((uint32_t)UINT16_MAX, strd_sz);
1567 max_buf_len = RTE_MIN(max_buf_len, (uint32_t)UINT8_MAX);
1568 assert(max_buf_len);
1569 if (priv->max_lro_msg_size)
1570 priv->max_lro_msg_size =
1571 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_buf_len);
1573 priv->max_lro_msg_size = max_buf_len;
1577 * Create a DPDK Rx queue.
1580 * Pointer to Ethernet device.
1584 * Number of descriptors to configure in queue.
1586 * NUMA socket on which memory must be allocated.
1589 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1591 struct mlx5_rxq_ctrl *
1592 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1593 unsigned int socket, const struct rte_eth_rxconf *conf,
1594 struct rte_mempool *mp)
1596 struct mlx5_priv *priv = dev->data->dev_private;
1597 struct mlx5_rxq_ctrl *tmpl;
1598 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1599 unsigned int mprq_stride_size;
1600 struct mlx5_dev_config *config = &priv->config;
1602 * LRO packet may consume all the stride memory, hence we cannot
1603 * guaranty head-room. A new striding RQ feature may be added in CX6 DX
1604 * to allow head-room and tail-room for the LRO packets.
1606 unsigned int strd_headroom_en = mlx5_lro_on(dev) ? 0 : 1;
1608 * Always allocate extra slots, even if eventually
1609 * the vector Rx will not be used.
1612 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1613 uint64_t offloads = conf->offloads |
1614 dev->data->dev_conf.rxmode.offloads;
1615 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1617 tmpl = rte_calloc_socket("RXQ", 1,
1619 desc_n * sizeof(struct rte_mbuf *),
1625 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1626 MLX5_MR_BTREE_CACHE_N, socket)) {
1627 /* rte_errno is already set. */
1630 tmpl->socket = socket;
1631 if (dev->data->dev_conf.intr_conf.rxq)
1634 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1635 * following conditions are met:
1636 * - MPRQ is enabled.
1637 * - The number of descs is more than the number of strides.
1638 * - max_rx_pkt_len plus overhead is less than the max size of a
1640 * Otherwise, enable Rx scatter if necessary.
1642 assert(mb_len >= RTE_PKTMBUF_HEADROOM * strd_headroom_en);
1643 mprq_stride_size = dev->data->dev_conf.rxmode.max_rx_pkt_len +
1644 RTE_PKTMBUF_HEADROOM * strd_headroom_en;
1646 desc > (1U << config->mprq.stride_num_n) &&
1647 mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1648 /* TODO: Rx scatter isn't supported yet. */
1649 tmpl->rxq.sges_n = 0;
1650 /* Trim the number of descs needed. */
1651 desc >>= config->mprq.stride_num_n;
1652 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1653 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1654 config->mprq.min_stride_size_n);
1655 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1656 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1657 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(mb_len -
1658 RTE_PKTMBUF_HEADROOM, config->mprq.max_memcpy_len);
1659 mlx5_max_lro_msg_size_adjust(dev, (1 << tmpl->rxq.strd_num_n),
1660 (1 << tmpl->rxq.strd_sz_n));
1662 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1663 " strd_num_n = %u, strd_sz_n = %u",
1664 dev->data->port_id, idx,
1665 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1666 } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1667 (mb_len - RTE_PKTMBUF_HEADROOM)) {
1668 tmpl->rxq.sges_n = 0;
1669 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1671 RTE_PKTMBUF_HEADROOM +
1672 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1673 unsigned int sges_n;
1676 * Determine the number of SGEs needed for a full packet
1677 * and round it to the next power of two.
1679 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1680 tmpl->rxq.sges_n = sges_n;
1681 /* Make sure rxq.sges_n did not overflow. */
1682 size = mb_len * (1 << tmpl->rxq.sges_n);
1683 size -= RTE_PKTMBUF_HEADROOM;
1684 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1686 "port %u too many SGEs (%u) needed to handle"
1687 " requested maximum packet size %u",
1690 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1691 rte_errno = EOVERFLOW;
1696 "port %u the requested maximum Rx packet size (%u) is"
1697 " larger than a single mbuf (%u) and scattered mode has"
1698 " not been requested",
1700 dev->data->dev_conf.rxmode.max_rx_pkt_len,
1701 mb_len - RTE_PKTMBUF_HEADROOM);
1703 if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1705 "port %u MPRQ is requested but cannot be enabled"
1706 " (requested: desc = %u, stride_sz = %u,"
1707 " supported: min_stride_num = %u, max_stride_sz = %u).",
1708 dev->data->port_id, desc, mprq_stride_size,
1709 (1 << config->mprq.stride_num_n),
1710 (1 << config->mprq.max_stride_size_n));
1711 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1712 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1713 if (desc % (1 << tmpl->rxq.sges_n)) {
1715 "port %u number of Rx queue descriptors (%u) is not a"
1716 " multiple of SGEs per packet (%u)",
1719 1 << tmpl->rxq.sges_n);
1723 /* Toggle RX checksum offload if hardware supports it. */
1724 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1725 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1726 /* Configure VLAN stripping. */
1727 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1728 /* By default, FCS (CRC) is stripped by hardware. */
1729 tmpl->rxq.crc_present = 0;
1730 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1731 if (config->hw_fcs_strip) {
1733 * RQs used for LRO-enabled TIRs should not be
1734 * configured to scatter the FCS.
1736 if (mlx5_lro_on(dev))
1738 "port %u CRC stripping has been "
1739 "disabled but will still be performed "
1740 "by hardware, because LRO is enabled",
1741 dev->data->port_id);
1743 tmpl->rxq.crc_present = 1;
1746 "port %u CRC stripping has been disabled but will"
1747 " still be performed by hardware, make sure MLNX_OFED"
1748 " and firmware are up to date",
1749 dev->data->port_id);
1753 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1754 " incoming frames to hide it",
1756 tmpl->rxq.crc_present ? "disabled" : "enabled",
1757 tmpl->rxq.crc_present << 2);
1759 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1760 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1761 tmpl->rxq.port_id = dev->data->port_id;
1764 tmpl->rxq.elts_n = log2above(desc);
1765 tmpl->rxq.rq_repl_thresh =
1766 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1768 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1770 tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1772 tmpl->rxq.idx = idx;
1773 rte_atomic32_inc(&tmpl->refcnt);
1774 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1785 * Pointer to Ethernet device.
1790 * A pointer to the queue if it exists, NULL otherwise.
1792 struct mlx5_rxq_ctrl *
1793 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1795 struct mlx5_priv *priv = dev->data->dev_private;
1796 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1798 if ((*priv->rxqs)[idx]) {
1799 rxq_ctrl = container_of((*priv->rxqs)[idx],
1800 struct mlx5_rxq_ctrl,
1802 mlx5_rxq_obj_get(dev, idx);
1803 rte_atomic32_inc(&rxq_ctrl->refcnt);
1809 * Release a Rx queue.
1812 * Pointer to Ethernet device.
1817 * 1 while a reference on it exists, 0 when freed.
1820 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1822 struct mlx5_priv *priv = dev->data->dev_private;
1823 struct mlx5_rxq_ctrl *rxq_ctrl;
1825 if (!(*priv->rxqs)[idx])
1827 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1828 assert(rxq_ctrl->priv);
1829 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
1830 rxq_ctrl->obj = NULL;
1831 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1832 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
1833 rxq_ctrl->dbr_offset));
1834 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1835 LIST_REMOVE(rxq_ctrl, next);
1837 (*priv->rxqs)[idx] = NULL;
1844 * Verify the Rx Queue list is empty
1847 * Pointer to Ethernet device.
1850 * The number of object not released.
1853 mlx5_rxq_verify(struct rte_eth_dev *dev)
1855 struct mlx5_priv *priv = dev->data->dev_private;
1856 struct mlx5_rxq_ctrl *rxq_ctrl;
1859 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1860 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1861 dev->data->port_id, rxq_ctrl->rxq.idx);
1868 * Create an indirection table.
1871 * Pointer to Ethernet device.
1873 * Queues entering in the indirection table.
1875 * Number of queues in the array.
1878 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1880 static struct mlx5_ind_table_obj *
1881 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
1882 uint32_t queues_n, enum mlx5_ind_tbl_type type)
1884 struct mlx5_priv *priv = dev->data->dev_private;
1885 struct mlx5_ind_table_obj *ind_tbl;
1886 unsigned int i = 0, j = 0, k = 0;
1888 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1889 queues_n * sizeof(uint16_t), 0);
1894 ind_tbl->type = type;
1895 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1896 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1897 log2above(queues_n) :
1898 log2above(priv->config.ind_table_max_size);
1899 struct ibv_wq *wq[1 << wq_n];
1901 for (i = 0; i != queues_n; ++i) {
1902 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1906 wq[i] = rxq->obj->wq;
1907 ind_tbl->queues[i] = queues[i];
1909 ind_tbl->queues_n = queues_n;
1910 /* Finalise indirection table. */
1911 k = i; /* Retain value of i for use in error case. */
1912 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
1914 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1916 &(struct ibv_rwq_ind_table_init_attr){
1917 .log_ind_tbl_size = wq_n,
1921 if (!ind_tbl->ind_table) {
1925 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
1926 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
1928 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
1929 queues_n * sizeof(uint16_t), 0);
1931 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
1932 dev->data->port_id);
1936 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
1937 rqt_attr->rqt_actual_size = queues_n;
1938 for (i = 0; i != queues_n; ++i) {
1939 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1943 rqt_attr->rq_list[i] = rxq->obj->rq->id;
1944 ind_tbl->queues[i] = queues[i];
1946 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
1949 if (!ind_tbl->rqt) {
1950 DRV_LOG(ERR, "port %u cannot create DevX RQT",
1951 dev->data->port_id);
1955 ind_tbl->queues_n = queues_n;
1957 rte_atomic32_inc(&ind_tbl->refcnt);
1958 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1961 for (j = 0; j < i; j++)
1962 mlx5_rxq_release(dev, ind_tbl->queues[j]);
1964 DEBUG("port %u cannot create indirection table", dev->data->port_id);
1969 * Get an indirection table.
1972 * Pointer to Ethernet device.
1974 * Queues entering in the indirection table.
1976 * Number of queues in the array.
1979 * An indirection table if found.
1981 static struct mlx5_ind_table_obj *
1982 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
1985 struct mlx5_priv *priv = dev->data->dev_private;
1986 struct mlx5_ind_table_obj *ind_tbl;
1988 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1989 if ((ind_tbl->queues_n == queues_n) &&
1990 (memcmp(ind_tbl->queues, queues,
1991 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1998 rte_atomic32_inc(&ind_tbl->refcnt);
1999 for (i = 0; i != ind_tbl->queues_n; ++i)
2000 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2006 * Release an indirection table.
2009 * Pointer to Ethernet device.
2011 * Indirection table to release.
2014 * 1 while a reference on it exists, 0 when freed.
2017 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2018 struct mlx5_ind_table_obj *ind_tbl)
2022 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2023 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2024 claim_zero(mlx5_glue->destroy_rwq_ind_table
2025 (ind_tbl->ind_table));
2026 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2027 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2029 for (i = 0; i != ind_tbl->queues_n; ++i)
2030 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2031 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2032 LIST_REMOVE(ind_tbl, next);
2040 * Verify the Rx Queue list is empty
2043 * Pointer to Ethernet device.
2046 * The number of object not released.
2049 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2051 struct mlx5_priv *priv = dev->data->dev_private;
2052 struct mlx5_ind_table_obj *ind_tbl;
2055 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2057 "port %u indirection table obj %p still referenced",
2058 dev->data->port_id, (void *)ind_tbl);
2065 * Create an Rx Hash queue.
2068 * Pointer to Ethernet device.
2070 * RSS key for the Rx hash queue.
2071 * @param rss_key_len
2073 * @param hash_fields
2074 * Verbs protocol hash field to make the RSS on.
2076 * Queues entering in hash queue. In case of empty hash_fields only the
2077 * first queue index will be taken for the indirection table.
2083 * Flow rule is relevant for LRO, i.e. contains IPv4/IPv6 and TCP.
2086 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2089 mlx5_hrxq_new(struct rte_eth_dev *dev,
2090 const uint8_t *rss_key, uint32_t rss_key_len,
2091 uint64_t hash_fields,
2092 const uint16_t *queues, uint32_t queues_n,
2093 int tunnel __rte_unused, int lro)
2095 struct mlx5_priv *priv = dev->data->dev_private;
2096 struct mlx5_hrxq *hrxq;
2097 struct ibv_qp *qp = NULL;
2098 struct mlx5_ind_table_obj *ind_tbl;
2100 struct mlx5_devx_obj *tir = NULL;
2102 queues_n = hash_fields ? queues_n : 1;
2103 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2105 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2106 struct mlx5_rxq_ctrl *rxq_ctrl =
2107 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2108 enum mlx5_ind_tbl_type type;
2110 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2111 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2112 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2118 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2119 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2120 struct mlx5dv_qp_init_attr qp_init_attr;
2122 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2124 qp_init_attr.comp_mask =
2125 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2126 qp_init_attr.create_flags =
2127 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2129 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2130 if (dev->data->dev_conf.lpbk_mode) {
2132 * Allow packet sent from NIC loop back
2133 * w/o source MAC check.
2135 qp_init_attr.comp_mask |=
2136 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2137 qp_init_attr.create_flags |=
2138 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2141 qp = mlx5_glue->dv_create_qp
2143 &(struct ibv_qp_init_attr_ex){
2144 .qp_type = IBV_QPT_RAW_PACKET,
2146 IBV_QP_INIT_ATTR_PD |
2147 IBV_QP_INIT_ATTR_IND_TABLE |
2148 IBV_QP_INIT_ATTR_RX_HASH,
2149 .rx_hash_conf = (struct ibv_rx_hash_conf){
2151 IBV_RX_HASH_FUNC_TOEPLITZ,
2152 .rx_hash_key_len = rss_key_len,
2154 (void *)(uintptr_t)rss_key,
2155 .rx_hash_fields_mask = hash_fields,
2157 .rwq_ind_tbl = ind_tbl->ind_table,
2162 qp = mlx5_glue->create_qp_ex
2164 &(struct ibv_qp_init_attr_ex){
2165 .qp_type = IBV_QPT_RAW_PACKET,
2167 IBV_QP_INIT_ATTR_PD |
2168 IBV_QP_INIT_ATTR_IND_TABLE |
2169 IBV_QP_INIT_ATTR_RX_HASH,
2170 .rx_hash_conf = (struct ibv_rx_hash_conf){
2172 IBV_RX_HASH_FUNC_TOEPLITZ,
2173 .rx_hash_key_len = rss_key_len,
2175 (void *)(uintptr_t)rss_key,
2176 .rx_hash_fields_mask = hash_fields,
2178 .rwq_ind_tbl = ind_tbl->ind_table,
2186 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2187 struct mlx5_devx_tir_attr tir_attr;
2189 memset(&tir_attr, 0, sizeof(tir_attr));
2190 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2191 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2192 memcpy(&tir_attr.rx_hash_field_selector_outer, &hash_fields,
2194 tir_attr.transport_domain = priv->sh->tdn;
2195 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2196 tir_attr.indirect_table = ind_tbl->rqt->id;
2197 if (dev->data->dev_conf.lpbk_mode)
2198 tir_attr.self_lb_block =
2199 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2201 tir_attr.lro_timeout_period_usecs =
2202 priv->config.lro.timeout;
2203 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2204 tir_attr.lro_enable_mask = lro;
2206 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2208 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2209 dev->data->port_id);
2214 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2217 hrxq->ind_table = ind_tbl;
2218 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2220 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2222 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2223 if (!hrxq->action) {
2228 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2230 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2231 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2233 if (!hrxq->action) {
2239 hrxq->rss_key_len = rss_key_len;
2240 hrxq->hash_fields = hash_fields;
2241 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2242 rte_atomic32_inc(&hrxq->refcnt);
2243 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2246 err = rte_errno; /* Save rte_errno before cleanup. */
2247 mlx5_ind_table_obj_release(dev, ind_tbl);
2249 claim_zero(mlx5_glue->destroy_qp(qp));
2251 claim_zero(mlx5_devx_cmd_destroy(tir));
2252 rte_errno = err; /* Restore rte_errno. */
2257 * Get an Rx Hash queue.
2260 * Pointer to Ethernet device.
2262 * RSS configuration for the Rx hash queue.
2264 * Queues entering in hash queue. In case of empty hash_fields only the
2265 * first queue index will be taken for the indirection table.
2270 * An hash Rx queue on success.
2273 mlx5_hrxq_get(struct rte_eth_dev *dev,
2274 const uint8_t *rss_key, uint32_t rss_key_len,
2275 uint64_t hash_fields,
2276 const uint16_t *queues, uint32_t queues_n)
2278 struct mlx5_priv *priv = dev->data->dev_private;
2279 struct mlx5_hrxq *hrxq;
2281 queues_n = hash_fields ? queues_n : 1;
2282 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2283 struct mlx5_ind_table_obj *ind_tbl;
2285 if (hrxq->rss_key_len != rss_key_len)
2287 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2289 if (hrxq->hash_fields != hash_fields)
2291 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2294 if (ind_tbl != hrxq->ind_table) {
2295 mlx5_ind_table_obj_release(dev, ind_tbl);
2298 rte_atomic32_inc(&hrxq->refcnt);
2305 * Release the hash Rx queue.
2308 * Pointer to Ethernet device.
2310 * Pointer to Hash Rx queue to release.
2313 * 1 while a reference on it exists, 0 when freed.
2316 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2318 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2319 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2320 mlx5_glue->destroy_flow_action(hrxq->action);
2322 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2323 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2324 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2325 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2326 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2327 LIST_REMOVE(hrxq, next);
2331 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2336 * Verify the Rx Queue list is empty
2339 * Pointer to Ethernet device.
2342 * The number of object not released.
2345 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2347 struct mlx5_priv *priv = dev->data->dev_private;
2348 struct mlx5_hrxq *hrxq;
2351 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2353 "port %u hash Rx queue %p still referenced",
2354 dev->data->port_id, (void *)hrxq);
2361 * Create a drop Rx queue Verbs/DevX object.
2364 * Pointer to Ethernet device.
2367 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2369 static struct mlx5_rxq_obj *
2370 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2372 struct mlx5_priv *priv = dev->data->dev_private;
2373 struct ibv_context *ctx = priv->sh->ctx;
2375 struct ibv_wq *wq = NULL;
2376 struct mlx5_rxq_obj *rxq;
2378 if (priv->drop_queue.rxq)
2379 return priv->drop_queue.rxq;
2380 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2382 DEBUG("port %u cannot allocate CQ for drop queue",
2383 dev->data->port_id);
2387 wq = mlx5_glue->create_wq(ctx,
2388 &(struct ibv_wq_init_attr){
2389 .wq_type = IBV_WQT_RQ,
2396 DEBUG("port %u cannot allocate WQ for drop queue",
2397 dev->data->port_id);
2401 rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2403 DEBUG("port %u cannot allocate drop Rx queue memory",
2404 dev->data->port_id);
2410 priv->drop_queue.rxq = rxq;
2414 claim_zero(mlx5_glue->destroy_wq(wq));
2416 claim_zero(mlx5_glue->destroy_cq(cq));
2421 * Release a drop Rx queue Verbs/DevX object.
2424 * Pointer to Ethernet device.
2427 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2430 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2432 struct mlx5_priv *priv = dev->data->dev_private;
2433 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2436 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2438 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2440 priv->drop_queue.rxq = NULL;
2444 * Create a drop indirection table.
2447 * Pointer to Ethernet device.
2450 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2452 static struct mlx5_ind_table_obj *
2453 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2455 struct mlx5_priv *priv = dev->data->dev_private;
2456 struct mlx5_ind_table_obj *ind_tbl;
2457 struct mlx5_rxq_obj *rxq;
2458 struct mlx5_ind_table_obj tmpl;
2460 rxq = mlx5_rxq_obj_drop_new(dev);
2463 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2465 &(struct ibv_rwq_ind_table_init_attr){
2466 .log_ind_tbl_size = 0,
2467 .ind_tbl = &rxq->wq,
2470 if (!tmpl.ind_table) {
2471 DEBUG("port %u cannot allocate indirection table for drop"
2473 dev->data->port_id);
2477 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2482 ind_tbl->ind_table = tmpl.ind_table;
2485 mlx5_rxq_obj_drop_release(dev);
2490 * Release a drop indirection table.
2493 * Pointer to Ethernet device.
2496 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2498 struct mlx5_priv *priv = dev->data->dev_private;
2499 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2501 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2502 mlx5_rxq_obj_drop_release(dev);
2504 priv->drop_queue.hrxq->ind_table = NULL;
2508 * Create a drop Rx Hash queue.
2511 * Pointer to Ethernet device.
2514 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2517 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2519 struct mlx5_priv *priv = dev->data->dev_private;
2520 struct mlx5_ind_table_obj *ind_tbl;
2522 struct mlx5_hrxq *hrxq;
2524 if (priv->drop_queue.hrxq) {
2525 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2526 return priv->drop_queue.hrxq;
2528 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2531 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2532 &(struct ibv_qp_init_attr_ex){
2533 .qp_type = IBV_QPT_RAW_PACKET,
2535 IBV_QP_INIT_ATTR_PD |
2536 IBV_QP_INIT_ATTR_IND_TABLE |
2537 IBV_QP_INIT_ATTR_RX_HASH,
2538 .rx_hash_conf = (struct ibv_rx_hash_conf){
2540 IBV_RX_HASH_FUNC_TOEPLITZ,
2541 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2542 .rx_hash_key = rss_hash_default_key,
2543 .rx_hash_fields_mask = 0,
2545 .rwq_ind_tbl = ind_tbl->ind_table,
2549 DEBUG("port %u cannot allocate QP for drop queue",
2550 dev->data->port_id);
2554 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2557 "port %u cannot allocate memory for drop queue",
2558 dev->data->port_id);
2562 hrxq->ind_table = ind_tbl;
2564 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2565 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2566 if (!hrxq->action) {
2571 priv->drop_queue.hrxq = hrxq;
2572 rte_atomic32_set(&hrxq->refcnt, 1);
2576 mlx5_ind_table_obj_drop_release(dev);
2581 * Release a drop hash Rx queue.
2584 * Pointer to Ethernet device.
2587 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2589 struct mlx5_priv *priv = dev->data->dev_private;
2590 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2592 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2593 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2594 mlx5_glue->destroy_flow_action(hrxq->action);
2596 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2597 mlx5_ind_table_obj_drop_release(dev);
2599 priv->drop_queue.hrxq = NULL;