1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
31 #include "mlx5_utils.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 /* TX burst subroutines return codes. */
38 enum mlx5_txcmp_code {
39 MLX5_TXCMP_CODE_EXIT = 0,
40 MLX5_TXCMP_CODE_ERROR,
41 MLX5_TXCMP_CODE_SINGLE,
42 MLX5_TXCMP_CODE_MULTI,
48 * These defines are used to configure Tx burst routine option set
49 * supported at compile time. The not specified options are optimized out
50 * out due to if conditions can be explicitly calculated at compile time.
51 * The offloads with bigger runtime check (require more CPU cycles to
52 * skip) overhead should have the bigger index - this is needed to
53 * select the better matching routine function if no exact match and
54 * some offloads are not actually requested.
56 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
57 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
58 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
59 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
60 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
61 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
62 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
63 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
65 /* The most common offloads groups. */
66 #define MLX5_TXOFF_CONFIG_NONE 0
67 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
68 MLX5_TXOFF_CONFIG_TSO | \
69 MLX5_TXOFF_CONFIG_SWP | \
70 MLX5_TXOFF_CONFIG_CSUM | \
71 MLX5_TXOFF_CONFIG_INLINE | \
72 MLX5_TXOFF_CONFIG_VLAN | \
73 MLX5_TXOFF_CONFIG_METADATA)
75 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
77 #define MLX5_TXOFF_DECL(func, olx) \
78 static uint16_t mlx5_tx_burst_##func(void *txq, \
79 struct rte_mbuf **pkts, \
82 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
83 pkts, pkts_n, (olx)); \
86 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
88 static __rte_always_inline uint32_t
89 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
91 static __rte_always_inline int
92 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
95 static __rte_always_inline uint32_t
96 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
98 static __rte_always_inline void
99 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
100 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
102 static __rte_always_inline void
103 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
104 const unsigned int strd_n);
107 mlx5_queue_state_modify(struct rte_eth_dev *dev,
108 struct mlx5_mp_arg_queue_state_modify *sm);
110 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
111 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
114 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
115 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
118 * Build a table to translate Rx completion flags to packet type.
120 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
123 mlx5_set_ptype_table(void)
126 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
128 /* Last entry must not be overwritten, reserved for errored packet. */
129 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
130 (*p)[i] = RTE_PTYPE_UNKNOWN;
132 * The index to the array should have:
133 * bit[1:0] = l3_hdr_type
134 * bit[4:2] = l4_hdr_type
137 * bit[7] = outer_l3_type
140 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
142 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
143 RTE_PTYPE_L4_NONFRAG;
144 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_L4_NONFRAG;
147 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
152 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
154 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
156 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
158 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
160 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
162 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
165 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
167 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
169 /* Repeat with outer_l3_type being set. Just in case. */
170 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
171 RTE_PTYPE_L4_NONFRAG;
172 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_L4_NONFRAG;
174 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
178 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
180 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
184 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
186 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
190 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
192 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
196 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_NONFRAG;
199 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_NONFRAG;
202 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
203 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_NONFRAG;
206 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_NONFRAG;
209 /* Tunneled - Fragmented */
210 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L4_FRAG;
213 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_FRAG;
216 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG;
219 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_FRAG;
223 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_TCP;
226 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_TCP;
229 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_TCP;
235 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
260 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_UDP;
263 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_UDP;
266 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_UDP;
269 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_UDP;
275 * Build a table to translate packet to checksum type of Verbs.
278 mlx5_set_cksum_table(void)
284 * The index should have:
285 * bit[0] = PKT_TX_TCP_SEG
286 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
287 * bit[4] = PKT_TX_IP_CKSUM
288 * bit[8] = PKT_TX_OUTER_IP_CKSUM
291 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
294 /* Tunneled packet. */
295 if (i & (1 << 8)) /* Outer IP. */
296 v |= MLX5_ETH_WQE_L3_CSUM;
297 if (i & (1 << 4)) /* Inner IP. */
298 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
299 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
300 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
303 if (i & (1 << 4)) /* IP. */
304 v |= MLX5_ETH_WQE_L3_CSUM;
305 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
306 v |= MLX5_ETH_WQE_L4_CSUM;
308 mlx5_cksum_table[i] = v;
313 * Build a table to translate packet type of mbuf to SWP type of Verbs.
316 mlx5_set_swp_types_table(void)
322 * The index should have:
323 * bit[0:1] = PKT_TX_L4_MASK
324 * bit[4] = PKT_TX_IPV6
325 * bit[8] = PKT_TX_OUTER_IPV6
326 * bit[9] = PKT_TX_OUTER_UDP
328 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
331 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
333 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
335 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
336 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
337 v |= MLX5_ETH_WQE_L4_INNER_UDP;
338 mlx5_swp_types_table[i] = v;
343 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
344 * Flags must be preliminary initialized to zero.
347 * Pointer to burst routine local context.
349 * Pointer to store Software Parser flags
351 * Configured Tx offloads mask. It is fully defined at
352 * compile time and may be used for optimization.
355 * Software Parser offsets packed in dword.
356 * Software Parser flags are set by pointer.
358 static __rte_always_inline uint32_t
359 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
364 unsigned int idx, off;
367 if (!MLX5_TXOFF_CONFIG(SWP))
369 ol = loc->mbuf->ol_flags;
370 tunnel = ol & PKT_TX_TUNNEL_MASK;
372 * Check whether Software Parser is required.
373 * Only customized tunnels may ask for.
375 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
378 * The index should have:
379 * bit[0:1] = PKT_TX_L4_MASK
380 * bit[4] = PKT_TX_IPV6
381 * bit[8] = PKT_TX_OUTER_IPV6
382 * bit[9] = PKT_TX_OUTER_UDP
384 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
385 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
386 *swp_flags = mlx5_swp_types_table[idx];
388 * Set offsets for SW parser. Since ConnectX-5, SW parser just
389 * complements HW parser. SW parser starts to engage only if HW parser
390 * can't reach a header. For the older devices, HW parser will not kick
391 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
392 * should be set regardless of HW offload.
394 off = loc->mbuf->outer_l2_len;
395 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
396 off += sizeof(struct rte_vlan_hdr);
397 set = (off >> 1) << 8; /* Outer L3 offset. */
398 off += loc->mbuf->outer_l3_len;
399 if (tunnel == PKT_TX_TUNNEL_UDP)
400 set |= off >> 1; /* Outer L4 offset. */
401 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
402 const uint64_t csum = ol & PKT_TX_L4_MASK;
403 off += loc->mbuf->l2_len;
404 set |= (off >> 1) << 24; /* Inner L3 offset. */
405 if (csum == PKT_TX_TCP_CKSUM ||
406 csum == PKT_TX_UDP_CKSUM ||
407 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
408 off += loc->mbuf->l3_len;
409 set |= (off >> 1) << 16; /* Inner L4 offset. */
412 set = rte_cpu_to_le_32(set);
417 * Convert the Checksum offloads to Verbs.
420 * Pointer to the mbuf.
423 * Converted checksum flags.
425 static __rte_always_inline uint8_t
426 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
429 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
430 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
431 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
434 * The index should have:
435 * bit[0] = PKT_TX_TCP_SEG
436 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
437 * bit[4] = PKT_TX_IP_CKSUM
438 * bit[8] = PKT_TX_OUTER_IP_CKSUM
441 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
442 return mlx5_cksum_table[idx];
446 * Internal function to compute the number of used descriptors in an RX queue
452 * The number of used rx descriptor.
455 rx_queue_count(struct mlx5_rxq_data *rxq)
457 struct rxq_zip *zip = &rxq->zip;
458 volatile struct mlx5_cqe *cqe;
459 const unsigned int cqe_n = (1 << rxq->cqe_n);
460 const unsigned int cqe_cnt = cqe_n - 1;
464 /* if we are processing a compressed cqe */
466 used = zip->cqe_cnt - zip->ca;
472 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
473 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
477 op_own = cqe->op_own;
478 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
479 n = rte_be_to_cpu_32(cqe->byte_cnt);
484 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
486 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
491 * DPDK callback to check the status of a rx descriptor.
496 * The index of the descriptor in the ring.
499 * The status of the tx descriptor.
502 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
504 struct mlx5_rxq_data *rxq = rx_queue;
505 struct mlx5_rxq_ctrl *rxq_ctrl =
506 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
507 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
509 if (dev->rx_pkt_burst != mlx5_rx_burst) {
513 if (offset >= (1 << rxq->elts_n)) {
517 if (offset < rx_queue_count(rxq))
518 return RTE_ETH_RX_DESC_DONE;
519 return RTE_ETH_RX_DESC_AVAIL;
523 * DPDK callback to get the number of used descriptors in a RX queue
526 * Pointer to the device structure.
532 * The number of used rx descriptor.
533 * -EINVAL if the queue is invalid
536 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
538 struct mlx5_priv *priv = dev->data->dev_private;
539 struct mlx5_rxq_data *rxq;
541 if (dev->rx_pkt_burst != mlx5_rx_burst) {
545 rxq = (*priv->rxqs)[rx_queue_id];
550 return rx_queue_count(rxq);
553 #define MLX5_SYSTEM_LOG_DIR "/var/log"
555 * Dump debug information to log file.
560 * If not NULL this string is printed as a header to the output
561 * and the output will be in hexadecimal view.
563 * This is the buffer address to print out.
565 * The number of bytes to dump out.
568 mlx5_dump_debug_information(const char *fname, const char *hex_title,
569 const void *buf, unsigned int hex_len)
573 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
574 fd = fopen(path, "a+");
576 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
578 MKSTR(path2, "./%s", fname);
579 fd = fopen(path2, "a+");
581 DRV_LOG(ERR, "cannot open %s for debug dump\n",
585 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
587 DRV_LOG(INFO, "New debug dump in file %s\n", path);
590 rte_hexdump(fd, hex_title, buf, hex_len);
592 fprintf(fd, "%s", (const char *)buf);
593 fprintf(fd, "\n\n\n");
598 * Move QP from error state to running state and initialize indexes.
601 * Pointer to TX queue control structure.
604 * 0 on success, else -1.
607 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
609 struct mlx5_mp_arg_queue_state_modify sm = {
611 .queue_id = txq_ctrl->txq.idx,
614 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
616 txq_ctrl->txq.wqe_ci = 0;
617 txq_ctrl->txq.wqe_pi = 0;
618 txq_ctrl->txq.elts_comp = 0;
622 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
624 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
626 static const uint8_t magic[] = "seen";
630 for (i = 0; i < sizeof(magic); ++i)
631 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
633 err_cqe->rsvd1[i] = magic[i];
642 * Pointer to TX queue structure.
644 * Pointer to the error CQE.
647 * The last Tx buffer element to free.
650 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
651 volatile struct mlx5_err_cqe *err_cqe)
653 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
654 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
655 struct mlx5_txq_ctrl *txq_ctrl =
656 container_of(txq, struct mlx5_txq_ctrl, txq);
657 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
658 int seen = check_err_cqe_seen(err_cqe);
660 if (!seen && txq_ctrl->dump_file_n <
661 txq_ctrl->priv->config.max_dump_files_num) {
662 MKSTR(err_str, "Unexpected CQE error syndrome "
663 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
664 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
665 txq->cqe_s, txq->qp_num_8s >> 8,
666 rte_be_to_cpu_16(err_cqe->wqe_counter),
667 txq->wqe_ci, txq->cq_ci);
668 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
669 PORT_ID(txq_ctrl->priv), txq->idx,
670 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
671 mlx5_dump_debug_information(name, NULL, err_str, 0);
672 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
673 (const void *)((uintptr_t)
677 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
678 (const void *)((uintptr_t)
682 txq_ctrl->dump_file_n++;
686 * Count errors in WQEs units.
687 * Later it can be improved to count error packets,
688 * for example, by SQ parsing to find how much packets
689 * should be counted for each WQE.
691 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
693 if (tx_recover_qp(txq_ctrl) == 0) {
695 /* Release all the remaining buffers. */
696 return txq->elts_head;
698 /* Recovering failed - try again later on the same WQE. */
702 /* Do not release buffers. */
703 return txq->elts_tail;
707 * Translate RX completion flags to packet type.
710 * Pointer to RX queue structure.
714 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
717 * Packet type for struct rte_mbuf.
719 static inline uint32_t
720 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
723 uint8_t pinfo = cqe->pkt_info;
724 uint16_t ptype = cqe->hdr_type_etc;
727 * The index to the array should have:
728 * bit[1:0] = l3_hdr_type
729 * bit[4:2] = l4_hdr_type
732 * bit[7] = outer_l3_type
734 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
735 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
739 * Initialize Rx WQ and indexes.
742 * Pointer to RX queue structure.
745 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
747 const unsigned int wqe_n = 1 << rxq->elts_n;
750 for (i = 0; (i != wqe_n); ++i) {
751 volatile struct mlx5_wqe_data_seg *scat;
755 if (mlx5_rxq_mprq_enabled(rxq)) {
756 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
758 scat = &((volatile struct mlx5_wqe_mprq *)
760 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
761 1 << rxq->strd_num_n);
762 byte_count = (1 << rxq->strd_sz_n) *
763 (1 << rxq->strd_num_n);
765 struct rte_mbuf *buf = (*rxq->elts)[i];
767 scat = &((volatile struct mlx5_wqe_data_seg *)
769 addr = rte_pktmbuf_mtod(buf, uintptr_t);
770 byte_count = DATA_LEN(buf);
772 /* scat->addr must be able to store a pointer. */
773 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
774 *scat = (struct mlx5_wqe_data_seg){
775 .addr = rte_cpu_to_be_64(addr),
776 .byte_count = rte_cpu_to_be_32(byte_count),
777 .lkey = mlx5_rx_addr2mr(rxq, addr),
780 rxq->consumed_strd = 0;
781 rxq->decompressed = 0;
783 rxq->zip = (struct rxq_zip){
786 /* Update doorbell counter. */
787 rxq->rq_ci = wqe_n >> rxq->sges_n;
789 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
793 * Modify a Verbs/DevX queue state.
794 * This must be called from the primary process.
797 * Pointer to Ethernet device.
799 * State modify request parameters.
802 * 0 in case of success else non-zero value and rte_errno is set.
805 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
806 const struct mlx5_mp_arg_queue_state_modify *sm)
809 struct mlx5_priv *priv = dev->data->dev_private;
812 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
813 struct mlx5_rxq_ctrl *rxq_ctrl =
814 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
816 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
817 struct ibv_wq_attr mod = {
818 .attr_mask = IBV_WQ_ATTR_STATE,
819 .wq_state = sm->state,
822 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
823 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
824 struct mlx5_devx_modify_rq_attr rq_attr;
826 memset(&rq_attr, 0, sizeof(rq_attr));
827 if (sm->state == IBV_WQS_RESET) {
828 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
829 rq_attr.state = MLX5_RQC_STATE_RST;
830 } else if (sm->state == IBV_WQS_RDY) {
831 rq_attr.rq_state = MLX5_RQC_STATE_RST;
832 rq_attr.state = MLX5_RQC_STATE_RDY;
833 } else if (sm->state == IBV_WQS_ERR) {
834 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
835 rq_attr.state = MLX5_RQC_STATE_ERR;
837 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
841 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s\n",
842 sm->state, strerror(errno));
847 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
848 struct mlx5_txq_ctrl *txq_ctrl =
849 container_of(txq, struct mlx5_txq_ctrl, txq);
850 struct ibv_qp_attr mod = {
851 .qp_state = IBV_QPS_RESET,
852 .port_num = (uint8_t)priv->ibv_port,
854 struct ibv_qp *qp = txq_ctrl->ibv->qp;
856 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
858 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
859 "%s\n", strerror(errno));
863 mod.qp_state = IBV_QPS_INIT;
864 ret = mlx5_glue->modify_qp(qp, &mod,
865 (IBV_QP_STATE | IBV_QP_PORT));
867 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s\n",
872 mod.qp_state = IBV_QPS_RTR;
873 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
875 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s\n",
880 mod.qp_state = IBV_QPS_RTS;
881 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
883 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s\n",
893 * Modify a Verbs queue state.
896 * Pointer to Ethernet device.
898 * State modify request parameters.
901 * 0 in case of success else non-zero value.
904 mlx5_queue_state_modify(struct rte_eth_dev *dev,
905 struct mlx5_mp_arg_queue_state_modify *sm)
909 switch (rte_eal_process_type()) {
910 case RTE_PROC_PRIMARY:
911 ret = mlx5_queue_state_modify_primary(dev, sm);
913 case RTE_PROC_SECONDARY:
914 ret = mlx5_mp_req_queue_state_modify(dev, sm);
924 * The function inserts the RQ state to reset when the first error CQE is
925 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
926 * it moves the RQ state to ready and initializes the RQ.
927 * Next CQE identification and error counting are in the caller responsibility.
930 * Pointer to RX queue structure.
931 * @param[in] mbuf_prepare
932 * Whether to prepare mbufs for the RQ.
935 * -1 in case of recovery error, otherwise the CQE status.
938 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
940 const uint16_t cqe_n = 1 << rxq->cqe_n;
941 const uint16_t cqe_mask = cqe_n - 1;
942 const unsigned int wqe_n = 1 << rxq->elts_n;
943 struct mlx5_rxq_ctrl *rxq_ctrl =
944 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
946 volatile struct mlx5_cqe *cqe;
947 volatile struct mlx5_err_cqe *err_cqe;
949 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
951 struct mlx5_mp_arg_queue_state_modify sm;
954 switch (rxq->err_state) {
955 case MLX5_RXQ_ERR_STATE_NO_ERROR:
956 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
958 case MLX5_RXQ_ERR_STATE_NEED_RESET:
960 sm.queue_id = rxq->idx;
961 sm.state = IBV_WQS_RESET;
962 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
964 if (rxq_ctrl->dump_file_n <
965 rxq_ctrl->priv->config.max_dump_files_num) {
966 MKSTR(err_str, "Unexpected CQE error syndrome "
967 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
968 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
969 rxq->cqn, rxq_ctrl->wqn,
970 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
971 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
972 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
973 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
974 mlx5_dump_debug_information(name, NULL, err_str, 0);
975 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
976 (const void *)((uintptr_t)
978 sizeof(*u.cqe) * cqe_n);
979 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
980 (const void *)((uintptr_t)
983 rxq_ctrl->dump_file_n++;
985 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
987 case MLX5_RXQ_ERR_STATE_NEED_READY:
988 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
989 if (ret == MLX5_CQE_STATUS_HW_OWN) {
991 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
994 * The RQ consumer index must be zeroed while moving
995 * from RESET state to RDY state.
997 *rxq->rq_db = rte_cpu_to_be_32(0);
1000 sm.queue_id = rxq->idx;
1001 sm.state = IBV_WQS_RDY;
1002 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1006 const uint16_t q_mask = wqe_n - 1;
1008 struct rte_mbuf **elt;
1010 unsigned int n = wqe_n - (rxq->rq_ci -
1013 for (i = 0; i < (int)n; ++i) {
1014 elt_idx = (rxq->rq_ci + i) & q_mask;
1015 elt = &(*rxq->elts)[elt_idx];
1016 *elt = rte_mbuf_raw_alloc(rxq->mp);
1018 for (i--; i >= 0; --i) {
1019 elt_idx = (rxq->rq_ci +
1023 rte_pktmbuf_free_seg
1030 mlx5_rxq_initialize(rxq);
1031 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1040 * Get size of the next packet for a given CQE. For compressed CQEs, the
1041 * consumer index is updated only once all packets of the current one have
1045 * Pointer to RX queue.
1049 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1053 * 0 in case of empty CQE, otherwise the packet size in bytes.
1056 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1057 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1059 struct rxq_zip *zip = &rxq->zip;
1060 uint16_t cqe_n = cqe_cnt + 1;
1066 /* Process compressed data in the CQE and mini arrays. */
1068 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1069 (volatile struct mlx5_mini_cqe8 (*)[8])
1070 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1073 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1074 *mcqe = &(*mc)[zip->ai & 7];
1075 if ((++zip->ai & 7) == 0) {
1076 /* Invalidate consumed CQEs */
1079 while (idx != end) {
1080 (*rxq->cqes)[idx & cqe_cnt].op_own =
1081 MLX5_CQE_INVALIDATE;
1085 * Increment consumer index to skip the number
1086 * of CQEs consumed. Hardware leaves holes in
1087 * the CQ ring for software use.
1092 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1093 /* Invalidate the rest */
1097 while (idx != end) {
1098 (*rxq->cqes)[idx & cqe_cnt].op_own =
1099 MLX5_CQE_INVALIDATE;
1102 rxq->cq_ci = zip->cq_ci;
1106 * No compressed data, get next CQE and verify if it is
1113 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1114 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1115 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1117 ret = mlx5_rx_err_handle(rxq, 0);
1118 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1126 op_own = cqe->op_own;
1127 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1128 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1129 (volatile struct mlx5_mini_cqe8 (*)[8])
1130 (uintptr_t)(&(*rxq->cqes)
1134 /* Fix endianness. */
1135 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1137 * Current mini array position is the one
1138 * returned by check_cqe64().
1140 * If completion comprises several mini arrays,
1141 * as a special case the second one is located
1142 * 7 CQEs after the initial CQE instead of 8
1143 * for subsequent ones.
1145 zip->ca = rxq->cq_ci;
1146 zip->na = zip->ca + 7;
1147 /* Compute the next non compressed CQE. */
1149 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1150 /* Get packet size to return. */
1151 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1154 /* Prefetch all to be invalidated */
1157 while (idx != end) {
1158 rte_prefetch0(&(*rxq->cqes)[(idx) &
1163 len = rte_be_to_cpu_32(cqe->byte_cnt);
1166 if (unlikely(rxq->err_state)) {
1167 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1168 ++rxq->stats.idropped;
1176 * Translate RX completion flags to offload flags.
1182 * Offload flags (ol_flags) for struct rte_mbuf.
1184 static inline uint32_t
1185 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1187 uint32_t ol_flags = 0;
1188 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1192 MLX5_CQE_RX_L3_HDR_VALID,
1193 PKT_RX_IP_CKSUM_GOOD) |
1195 MLX5_CQE_RX_L4_HDR_VALID,
1196 PKT_RX_L4_CKSUM_GOOD);
1201 * Fill in mbuf fields from RX completion flags.
1202 * Note that pkt->ol_flags should be initialized outside of this function.
1205 * Pointer to RX queue.
1210 * @param rss_hash_res
1211 * Packet RSS Hash result.
1214 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1215 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1217 /* Update packet information. */
1218 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1219 if (rss_hash_res && rxq->rss_hash) {
1220 pkt->hash.rss = rss_hash_res;
1221 pkt->ol_flags |= PKT_RX_RSS_HASH;
1223 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1224 pkt->ol_flags |= PKT_RX_FDIR;
1225 if (cqe->sop_drop_qpn !=
1226 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1227 uint32_t mark = cqe->sop_drop_qpn;
1229 pkt->ol_flags |= PKT_RX_FDIR_ID;
1230 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1234 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1235 if (rxq->vlan_strip &&
1236 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1237 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1238 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1240 if (rxq->hw_timestamp) {
1241 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1242 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1247 * DPDK callback for RX.
1250 * Generic pointer to RX queue structure.
1252 * Array to store received packets.
1254 * Maximum number of packets in array.
1257 * Number of packets successfully received (<= pkts_n).
1260 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1262 struct mlx5_rxq_data *rxq = dpdk_rxq;
1263 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1264 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1265 const unsigned int sges_n = rxq->sges_n;
1266 struct rte_mbuf *pkt = NULL;
1267 struct rte_mbuf *seg = NULL;
1268 volatile struct mlx5_cqe *cqe =
1269 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1271 unsigned int rq_ci = rxq->rq_ci << sges_n;
1272 int len = 0; /* keep its value across iterations. */
1275 unsigned int idx = rq_ci & wqe_cnt;
1276 volatile struct mlx5_wqe_data_seg *wqe =
1277 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1278 struct rte_mbuf *rep = (*rxq->elts)[idx];
1279 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1280 uint32_t rss_hash_res;
1288 rep = rte_mbuf_raw_alloc(rxq->mp);
1289 if (unlikely(rep == NULL)) {
1290 ++rxq->stats.rx_nombuf;
1293 * no buffers before we even started,
1294 * bail out silently.
1298 while (pkt != seg) {
1299 assert(pkt != (*rxq->elts)[idx]);
1303 rte_mbuf_raw_free(pkt);
1309 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1310 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1312 rte_mbuf_raw_free(rep);
1316 assert(len >= (rxq->crc_present << 2));
1318 /* If compressed, take hash result from mini-CQE. */
1319 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1321 mcqe->rx_hash_result);
1322 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1323 if (rxq->crc_present)
1324 len -= RTE_ETHER_CRC_LEN;
1327 DATA_LEN(rep) = DATA_LEN(seg);
1328 PKT_LEN(rep) = PKT_LEN(seg);
1329 SET_DATA_OFF(rep, DATA_OFF(seg));
1330 PORT(rep) = PORT(seg);
1331 (*rxq->elts)[idx] = rep;
1333 * Fill NIC descriptor with the new buffer. The lkey and size
1334 * of the buffers are already known, only the buffer address
1337 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1338 /* If there's only one MR, no need to replace LKey in WQE. */
1339 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1340 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1341 if (len > DATA_LEN(seg)) {
1342 len -= DATA_LEN(seg);
1347 DATA_LEN(seg) = len;
1348 #ifdef MLX5_PMD_SOFT_COUNTERS
1349 /* Increment bytes counter. */
1350 rxq->stats.ibytes += PKT_LEN(pkt);
1352 /* Return packet. */
1357 /* Align consumer index to the next stride. */
1362 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1364 /* Update the consumer index. */
1365 rxq->rq_ci = rq_ci >> sges_n;
1367 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1369 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1370 #ifdef MLX5_PMD_SOFT_COUNTERS
1371 /* Increment packets counter. */
1372 rxq->stats.ipackets += i;
1378 * Update LRO packet TCP header.
1379 * The HW LRO feature doesn't update the TCP header after coalescing the
1380 * TCP segments but supplies information in CQE to fill it by SW.
1383 * Pointer to the TCP header.
1385 * Pointer to the completion entry..
1387 * The L3 pseudo-header checksum.
1390 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1391 volatile struct mlx5_cqe *restrict cqe,
1394 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1395 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1397 * The HW calculates only the TCP payload checksum, need to complete
1398 * the TCP header checksum and the L3 pseudo-header checksum.
1400 uint32_t csum = phcsum + cqe->csum;
1402 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1403 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1404 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1405 tcp->recv_ack = cqe->lro_ack_seq_num;
1406 tcp->rx_win = cqe->lro_tcp_win;
1408 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1409 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1411 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1412 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1413 csum = (~csum) & 0xffff;
1420 * Update LRO packet headers.
1421 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1422 * TCP segments but supply information in CQE to fill it by SW.
1425 * The packet address.
1427 * Pointer to the completion entry..
1429 * The packet length.
1432 mlx5_lro_update_hdr(uint8_t *restrict padd,
1433 volatile struct mlx5_cqe *restrict cqe,
1437 struct rte_ether_hdr *eth;
1438 struct rte_vlan_hdr *vlan;
1439 struct rte_ipv4_hdr *ipv4;
1440 struct rte_ipv6_hdr *ipv6;
1441 struct rte_tcp_hdr *tcp;
1446 uint16_t proto = h.eth->ether_type;
1450 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1451 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1452 proto = h.vlan->eth_proto;
1455 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1456 h.ipv4->time_to_live = cqe->lro_min_ttl;
1457 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1458 h.ipv4->hdr_checksum = 0;
1459 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1460 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1463 h.ipv6->hop_limits = cqe->lro_min_ttl;
1464 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1466 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1469 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1473 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1475 struct mlx5_mprq_buf *buf = opaque;
1477 if (rte_atomic16_read(&buf->refcnt) == 1) {
1478 rte_mempool_put(buf->mp, buf);
1479 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1480 rte_atomic16_set(&buf->refcnt, 1);
1481 rte_mempool_put(buf->mp, buf);
1486 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1488 mlx5_mprq_buf_free_cb(NULL, buf);
1492 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1493 const unsigned int strd_n)
1495 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1496 volatile struct mlx5_wqe_data_seg *wqe =
1497 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1500 assert(rep != NULL);
1501 /* Replace MPRQ buf. */
1502 (*rxq->mprq_bufs)[rq_idx] = rep;
1504 addr = mlx5_mprq_buf_addr(rep, strd_n);
1505 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1506 /* If there's only one MR, no need to replace LKey in WQE. */
1507 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1508 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1509 /* Stash a mbuf for next replacement. */
1510 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1511 rxq->mprq_repl = rep;
1513 rxq->mprq_repl = NULL;
1517 * DPDK callback for RX with Multi-Packet RQ support.
1520 * Generic pointer to RX queue structure.
1522 * Array to store received packets.
1524 * Maximum number of packets in array.
1527 * Number of packets successfully received (<= pkts_n).
1530 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1532 struct mlx5_rxq_data *rxq = dpdk_rxq;
1533 const unsigned int strd_n = 1 << rxq->strd_num_n;
1534 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1535 const unsigned int strd_shift =
1536 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1537 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1538 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1539 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1541 uint32_t rq_ci = rxq->rq_ci;
1542 uint16_t consumed_strd = rxq->consumed_strd;
1543 uint16_t headroom_sz = rxq->strd_headroom_en * RTE_PKTMBUF_HEADROOM;
1544 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1546 while (i < pkts_n) {
1547 struct rte_mbuf *pkt;
1555 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1556 uint32_t rss_hash_res = 0;
1557 uint8_t lro_num_seg;
1559 if (consumed_strd == strd_n) {
1560 /* Replace WQE only if the buffer is still in use. */
1561 if (rte_atomic16_read(&buf->refcnt) > 1) {
1562 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1563 /* Release the old buffer. */
1564 mlx5_mprq_buf_free(buf);
1565 } else if (unlikely(rxq->mprq_repl == NULL)) {
1566 struct mlx5_mprq_buf *rep;
1569 * Currently, the MPRQ mempool is out of buffer
1570 * and doing memcpy regardless of the size of Rx
1571 * packet. Retry allocation to get back to
1574 if (!rte_mempool_get(rxq->mprq_mp,
1576 rxq->mprq_repl = rep;
1578 /* Advance to the next WQE. */
1581 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1583 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1584 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1588 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1589 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1591 consumed_strd += strd_cnt;
1592 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1595 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1596 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1598 /* mini-CQE for MPRQ doesn't have hash result. */
1599 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1601 assert(strd_idx < strd_n);
1602 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1603 lro_num_seg = cqe->lro_num_seg;
1605 * Currently configured to receive a packet per a stride. But if
1606 * MTU is adjusted through kernel interface, device could
1607 * consume multiple strides without raising an error. In this
1608 * case, the packet should be dropped because it is bigger than
1609 * the max_rx_pkt_len.
1611 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1612 ++rxq->stats.idropped;
1615 pkt = rte_pktmbuf_alloc(rxq->mp);
1616 if (unlikely(pkt == NULL)) {
1617 ++rxq->stats.rx_nombuf;
1620 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1621 assert((int)len >= (rxq->crc_present << 2));
1622 if (rxq->crc_present)
1623 len -= RTE_ETHER_CRC_LEN;
1624 offset = strd_idx * strd_sz + strd_shift;
1625 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1626 /* Initialize the offload flag. */
1629 * Memcpy packets to the target mbuf if:
1630 * - The size of packet is smaller than mprq_max_memcpy_len.
1631 * - Out of buffer in the Mempool for Multi-Packet RQ.
1633 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1635 * When memcpy'ing packet due to out-of-buffer, the
1636 * packet must be smaller than the target mbuf.
1638 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1639 rte_pktmbuf_free_seg(pkt);
1640 ++rxq->stats.idropped;
1643 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1645 rte_iova_t buf_iova;
1646 struct rte_mbuf_ext_shared_info *shinfo;
1647 uint16_t buf_len = strd_cnt * strd_sz;
1650 /* Increment the refcnt of the whole chunk. */
1651 rte_atomic16_add_return(&buf->refcnt, 1);
1652 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1654 buf_addr = RTE_PTR_SUB(addr, headroom_sz);
1656 * MLX5 device doesn't use iova but it is necessary in a
1657 * case where the Rx packet is transmitted via a
1660 buf_iova = rte_mempool_virt2iova(buf) +
1661 RTE_PTR_DIFF(buf_addr, buf);
1662 shinfo = &buf->shinfos[strd_idx];
1663 rte_mbuf_ext_refcnt_set(shinfo, 1);
1665 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1666 * attaching the stride to mbuf and more offload flags
1667 * will be added below by calling rxq_cq_to_mbuf().
1668 * Other fields will be overwritten.
1670 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1672 /* Set mbuf head-room. */
1673 pkt->data_off = headroom_sz;
1674 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1676 * Prevent potential overflow due to MTU change through
1679 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1680 rte_pktmbuf_free_seg(pkt);
1681 ++rxq->stats.idropped;
1685 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1686 if (lro_num_seg > 1) {
1687 mlx5_lro_update_hdr(addr, cqe, len);
1688 pkt->ol_flags |= PKT_RX_LRO;
1689 pkt->tso_segsz = strd_sz;
1692 DATA_LEN(pkt) = len;
1693 PORT(pkt) = rxq->port_id;
1694 #ifdef MLX5_PMD_SOFT_COUNTERS
1695 /* Increment bytes counter. */
1696 rxq->stats.ibytes += PKT_LEN(pkt);
1698 /* Return packet. */
1702 /* Update the consumer indexes. */
1703 rxq->consumed_strd = consumed_strd;
1705 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1706 if (rq_ci != rxq->rq_ci) {
1709 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1711 #ifdef MLX5_PMD_SOFT_COUNTERS
1712 /* Increment packets counter. */
1713 rxq->stats.ipackets += i;
1719 * Dummy DPDK callback for TX.
1721 * This function is used to temporarily replace the real callback during
1722 * unsafe control operations on the queue, or in case of error.
1725 * Generic pointer to TX queue structure.
1727 * Packets to transmit.
1729 * Number of packets in array.
1732 * Number of packets successfully transmitted (<= pkts_n).
1735 removed_tx_burst(void *dpdk_txq __rte_unused,
1736 struct rte_mbuf **pkts __rte_unused,
1737 uint16_t pkts_n __rte_unused)
1744 * Dummy DPDK callback for RX.
1746 * This function is used to temporarily replace the real callback during
1747 * unsafe control operations on the queue, or in case of error.
1750 * Generic pointer to RX queue structure.
1752 * Array to store received packets.
1754 * Maximum number of packets in array.
1757 * Number of packets successfully received (<= pkts_n).
1760 removed_rx_burst(void *dpdk_txq __rte_unused,
1761 struct rte_mbuf **pkts __rte_unused,
1762 uint16_t pkts_n __rte_unused)
1769 * Vectorized Rx/Tx routines are not compiled in when required vector
1770 * instructions are not supported on a target architecture. The following null
1771 * stubs are needed for linkage when those are not included outside of this file
1772 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1776 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1777 struct rte_mbuf **pkts __rte_unused,
1778 uint16_t pkts_n __rte_unused)
1784 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1790 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1796 * Free the mbufs from the linear array of pointers.
1799 * Pointer to array of packets to be free.
1801 * Number of packets to be freed.
1803 * Configured Tx offloads mask. It is fully defined at
1804 * compile time and may be used for optimization.
1806 static __rte_always_inline void
1807 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1808 unsigned int pkts_n,
1809 unsigned int olx __rte_unused)
1811 struct rte_mempool *pool = NULL;
1812 struct rte_mbuf **p_free = NULL;
1813 struct rte_mbuf *mbuf;
1814 unsigned int n_free = 0;
1817 * The implemented algorithm eliminates
1818 * copying pointers to temporary array
1819 * for rte_mempool_put_bulk() calls.
1826 * Decrement mbuf reference counter, detach
1827 * indirect and external buffers if needed.
1829 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1830 if (likely(mbuf != NULL)) {
1831 assert(mbuf == *pkts);
1832 if (likely(n_free != 0)) {
1833 if (unlikely(pool != mbuf->pool))
1834 /* From different pool. */
1837 /* Start new scan array. */
1844 if (unlikely(pkts_n == 0)) {
1850 * This happens if mbuf is still referenced.
1851 * We can't put it back to the pool, skip.
1855 if (unlikely(n_free != 0))
1856 /* There is some array to free.*/
1858 if (unlikely(pkts_n == 0))
1859 /* Last mbuf, nothing to free. */
1865 * This loop is implemented to avoid multiple
1866 * inlining of rte_mempool_put_bulk().
1872 * Free the array of pre-freed mbufs
1873 * belonging to the same memory pool.
1875 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1876 if (unlikely(mbuf != NULL)) {
1877 /* There is the request to start new scan. */
1882 if (likely(pkts_n != 0))
1885 * This is the last mbuf to be freed.
1886 * Do one more loop iteration to complete.
1887 * This is rare case of the last unique mbuf.
1892 if (likely(pkts_n == 0))
1901 * Free the mbuf from the elts ring buffer till new tail.
1904 * Pointer to Tx queue structure.
1906 * Index in elts to free up to, becomes new elts tail.
1908 * Configured Tx offloads mask. It is fully defined at
1909 * compile time and may be used for optimization.
1911 static __rte_always_inline void
1912 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1914 unsigned int olx __rte_unused)
1916 uint16_t n_elts = tail - txq->elts_tail;
1919 assert(n_elts <= txq->elts_s);
1921 * Implement a loop to support ring buffer wraparound
1922 * with single inlining of mlx5_tx_free_mbuf().
1927 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1928 part = RTE_MIN(part, n_elts);
1930 assert(part <= txq->elts_s);
1931 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1933 txq->elts_tail += part;
1939 * Store the mbuf being sent into elts ring buffer.
1940 * On Tx completion these mbufs will be freed.
1943 * Pointer to Tx queue structure.
1945 * Pointer to array of packets to be stored.
1947 * Number of packets to be stored.
1949 * Configured Tx offloads mask. It is fully defined at
1950 * compile time and may be used for optimization.
1952 static __rte_always_inline void
1953 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
1954 struct rte_mbuf **restrict pkts,
1955 unsigned int pkts_n,
1956 unsigned int olx __rte_unused)
1959 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
1963 part = txq->elts_s - (txq->elts_head & txq->elts_m);
1965 assert(part <= txq->elts_s);
1966 /* This code is a good candidate for vectorizing with SIMD. */
1967 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
1969 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
1970 txq->elts_head += pkts_n;
1971 if (unlikely(part < pkts_n))
1972 /* The copy is wrapping around the elts array. */
1973 rte_memcpy((void *)elts, (void *)(pkts + part),
1974 (pkts_n - part) * sizeof(struct rte_mbuf *));
1978 * Manage TX completions. This routine checks the CQ for
1979 * arrived CQEs, deduces the last accomplished WQE in SQ,
1980 * updates SQ producing index and frees all completed mbufs.
1983 * Pointer to TX queue structure.
1985 * Configured Tx offloads mask. It is fully defined at
1986 * compile time and may be used for optimization.
1988 * NOTE: not inlined intentionally, it makes tx_burst
1989 * routine smaller, simple and faster - from experiments.
1992 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
1993 unsigned int olx __rte_unused)
1995 bool update = false;
1999 volatile struct mlx5_wqe_cseg *cseg;
2000 volatile struct mlx5_cqe *cqe;
2003 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2004 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2005 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2006 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2007 /* No new CQEs in completion queue. */
2008 assert(ret == MLX5_CQE_STATUS_HW_OWN);
2009 if (likely(update)) {
2010 /* Update the consumer index. */
2011 rte_compiler_barrier();
2013 rte_cpu_to_be_32(txq->cq_ci);
2017 /* Some error occurred, try to restart. */
2019 tail = mlx5_tx_error_cqe_handle
2020 (txq, (volatile struct mlx5_err_cqe *)cqe);
2022 /* Normal transmit completion. */
2025 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
2026 cseg = (volatile struct mlx5_wqe_cseg *)
2027 (txq->wqes + (txq->wqe_pi & txq->wqe_m));
2034 if (likely(tail != txq->elts_tail)) {
2035 /* Free data buffers from elts. */
2036 mlx5_tx_free_elts(txq, tail, olx);
2037 assert(tail == txq->elts_tail);
2044 * Check if the completion request flag should be set in the last WQE.
2045 * Both pushed mbufs and WQEs are monitored and the completion request
2046 * flag is set if any of thresholds is reached.
2049 * Pointer to TX queue structure.
2051 * Number of mbuf not stored yet in elts array.
2053 * Pointer to burst routine local context.
2055 * Configured Tx offloads mask. It is fully defined at
2056 * compile time and may be used for optimization.
2058 static __rte_always_inline void
2059 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2060 unsigned int n_mbuf,
2061 struct mlx5_txq_local *restrict loc,
2062 unsigned int olx __rte_unused)
2064 uint16_t head = txq->elts_head + n_mbuf;
2066 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2067 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres) {
2068 volatile struct mlx5_wqe *last = loc->wqe_last;
2070 txq->elts_comp = head;
2071 txq->wqe_comp = txq->wqe_ci;
2072 /* Request unconditional completion on last WQE. */
2073 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2074 MLX5_COMP_MODE_OFFSET);
2075 /* Save elts_head in unused "immediate" field of WQE. */
2076 last->cseg.misc = head;
2078 * A CQE slot must always be available. Count the
2079 * issued CEQ "always" request instead of production
2080 * index due to here can be CQE with errors and
2081 * difference with ci may become inconsistent.
2083 assert(txq->cqe_s > ++txq->cq_pi);
2088 * DPDK callback to check the status of a tx descriptor.
2093 * The index of the descriptor in the ring.
2096 * The status of the tx descriptor.
2099 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2101 struct mlx5_txq_data *restrict txq = tx_queue;
2104 mlx5_tx_handle_completion(txq, 0);
2105 used = txq->elts_head - txq->elts_tail;
2107 return RTE_ETH_TX_DESC_FULL;
2108 return RTE_ETH_TX_DESC_DONE;
2112 * Build the Control Segment with specified opcode:
2113 * - MLX5_OPCODE_SEND
2114 * - MLX5_OPCODE_ENHANCED_MPSW
2118 * Pointer to TX queue structure.
2120 * Pointer to burst routine local context.
2122 * Pointer to WQE to fill with built Control Segment.
2124 * Supposed length of WQE in segments.
2126 * SQ WQE opcode to put into Control Segment.
2128 * Configured Tx offloads mask. It is fully defined at
2129 * compile time and may be used for optimization.
2131 static __rte_always_inline void
2132 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2133 struct mlx5_txq_local *restrict loc __rte_unused,
2134 struct mlx5_wqe *restrict wqe,
2136 unsigned int opcode,
2137 unsigned int olx __rte_unused)
2139 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2141 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2142 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2143 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2144 MLX5_COMP_MODE_OFFSET);
2145 cs->misc = RTE_BE32(0);
2149 * Build the Ethernet Segment without inlined data.
2150 * Supports Software Parser, Checksums and VLAN
2151 * insertion Tx offload features.
2154 * Pointer to TX queue structure.
2156 * Pointer to burst routine local context.
2158 * Pointer to WQE to fill with built Ethernet Segment.
2160 * Configured Tx offloads mask. It is fully defined at
2161 * compile time and may be used for optimization.
2163 static __rte_always_inline void
2164 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2165 struct mlx5_txq_local *restrict loc,
2166 struct mlx5_wqe *restrict wqe,
2169 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2173 * Calculate and set check sum flags first, dword field
2174 * in segment may be shared with Software Parser flags.
2176 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2177 es->flags = rte_cpu_to_le_32(csum);
2179 * Calculate and set Software Parser offsets and flags.
2180 * These flags a set for custom UDP and IP tunnel packets.
2182 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2183 /* Fill metadata field if needed. */
2184 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2185 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2186 loc->mbuf->tx_metadata : 0 : 0;
2187 /* Engage VLAN tag insertion feature if requested. */
2188 if (MLX5_TXOFF_CONFIG(VLAN) &&
2189 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2191 * We should get here only if device support
2192 * this feature correctly.
2194 assert(txq->vlan_en);
2195 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2196 loc->mbuf->vlan_tci);
2198 es->inline_hdr = RTE_BE32(0);
2203 * Build the Ethernet Segment with minimal inlined data
2204 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2205 * used to fill the gap in single WQEBB WQEs.
2206 * Supports Software Parser, Checksums and VLAN
2207 * insertion Tx offload features.
2210 * Pointer to TX queue structure.
2212 * Pointer to burst routine local context.
2214 * Pointer to WQE to fill with built Ethernet Segment.
2216 * Length of VLAN tag insertion if any.
2218 * Configured Tx offloads mask. It is fully defined at
2219 * compile time and may be used for optimization.
2221 static __rte_always_inline void
2222 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2223 struct mlx5_txq_local *restrict loc,
2224 struct mlx5_wqe *restrict wqe,
2228 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2230 uint8_t *psrc, *pdst;
2233 * Calculate and set check sum flags first, dword field
2234 * in segment may be shared with Software Parser flags.
2236 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2237 es->flags = rte_cpu_to_le_32(csum);
2239 * Calculate and set Software Parser offsets and flags.
2240 * These flags a set for custom UDP and IP tunnel packets.
2242 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2243 /* Fill metadata field if needed. */
2244 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2245 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2246 loc->mbuf->tx_metadata : 0 : 0;
2247 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2249 sizeof(rte_v128u32_t)),
2250 "invalid Ethernet Segment data size");
2251 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2253 sizeof(struct rte_vlan_hdr) +
2254 2 * RTE_ETHER_ADDR_LEN),
2255 "invalid Ethernet Segment data size");
2256 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2257 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2258 es->inline_data = *(unaligned_uint16_t *)psrc;
2259 psrc += sizeof(uint16_t);
2260 pdst = (uint8_t *)(es + 1);
2261 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2262 /* Implement VLAN tag insertion as part inline data. */
2263 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2264 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2265 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2266 /* Insert VLAN ethertype + VLAN tag. */
2267 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2268 ((RTE_ETHER_TYPE_VLAN << 16) |
2269 loc->mbuf->vlan_tci);
2270 pdst += sizeof(struct rte_vlan_hdr);
2271 /* Copy the rest two bytes from packet data. */
2272 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2273 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2275 /* Fill the gap in the title WQEBB with inline data. */
2276 rte_mov16(pdst, psrc);
2281 * Build the Ethernet Segment with entire packet
2282 * data inlining. Checks the boundary of WQEBB and
2283 * ring buffer wrapping, supports Software Parser,
2284 * Checksums and VLAN insertion Tx offload features.
2287 * Pointer to TX queue structure.
2289 * Pointer to burst routine local context.
2291 * Pointer to WQE to fill with built Ethernet Segment.
2293 * Length of VLAN tag insertion if any.
2295 * Length of data to inline (VLAN included, if any).
2297 * TSO flag, set mss field from the packet.
2299 * Configured Tx offloads mask. It is fully defined at
2300 * compile time and may be used for optimization.
2303 * Pointer to the next Data Segment (aligned and wrapped around).
2305 static __rte_always_inline struct mlx5_wqe_dseg *
2306 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2307 struct mlx5_txq_local *restrict loc,
2308 struct mlx5_wqe *restrict wqe,
2314 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2316 uint8_t *psrc, *pdst;
2320 * Calculate and set check sum flags first, dword field
2321 * in segment may be shared with Software Parser flags.
2323 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2326 csum |= loc->mbuf->tso_segsz;
2327 es->flags = rte_cpu_to_be_32(csum);
2329 es->flags = rte_cpu_to_le_32(csum);
2332 * Calculate and set Software Parser offsets and flags.
2333 * These flags a set for custom UDP and IP tunnel packets.
2335 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2336 /* Fill metadata field if needed. */
2337 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2338 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2339 loc->mbuf->tx_metadata : 0 : 0;
2340 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2342 sizeof(rte_v128u32_t)),
2343 "invalid Ethernet Segment data size");
2344 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2346 sizeof(struct rte_vlan_hdr) +
2347 2 * RTE_ETHER_ADDR_LEN),
2348 "invalid Ethernet Segment data size");
2349 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2350 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2351 es->inline_data = *(unaligned_uint16_t *)psrc;
2352 psrc += sizeof(uint16_t);
2353 pdst = (uint8_t *)(es + 1);
2354 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2355 /* Implement VLAN tag insertion as part inline data. */
2356 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2357 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2358 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2359 /* Insert VLAN ethertype + VLAN tag. */
2360 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2361 ((RTE_ETHER_TYPE_VLAN << 16) |
2362 loc->mbuf->vlan_tci);
2363 pdst += sizeof(struct rte_vlan_hdr);
2364 /* Copy the rest two bytes from packet data. */
2365 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2366 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2367 psrc += sizeof(uint16_t);
2369 /* Fill the gap in the title WQEBB with inline data. */
2370 rte_mov16(pdst, psrc);
2371 psrc += sizeof(rte_v128u32_t);
2373 pdst = (uint8_t *)(es + 2);
2374 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2375 assert(pdst < (uint8_t *)txq->wqes_end);
2376 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2378 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2379 return (struct mlx5_wqe_dseg *)pdst;
2382 * The WQEBB space availability is checked by caller.
2383 * Here we should be aware of WQE ring buffer wraparound only.
2385 part = (uint8_t *)txq->wqes_end - pdst;
2386 part = RTE_MIN(part, inlen);
2388 rte_memcpy(pdst, psrc, part);
2390 if (likely(!inlen)) {
2392 * If return value is not used by the caller
2393 * the code below will be optimized out.
2396 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2397 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2398 pdst = (uint8_t *)txq->wqes;
2399 return (struct mlx5_wqe_dseg *)pdst;
2401 pdst = (uint8_t *)txq->wqes;
2408 * Copy data from chain of mbuf to the specified linear buffer.
2409 * Checksums and VLAN insertion Tx offload features. If data
2410 * from some mbuf copied completely this mbuf is freed. Local
2411 * structure is used to keep the byte stream state.
2414 * Pointer to the destination linear buffer.
2416 * Pointer to burst routine local context.
2418 * Length of data to be copied.
2420 * Configured Tx offloads mask. It is fully defined at
2421 * compile time and may be used for optimization.
2423 static __rte_always_inline void
2424 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2425 struct mlx5_txq_local *restrict loc,
2427 unsigned int olx __rte_unused)
2429 struct rte_mbuf *mbuf;
2430 unsigned int part, dlen;
2435 /* Allow zero length packets, must check first. */
2436 dlen = rte_pktmbuf_data_len(loc->mbuf);
2437 if (dlen <= loc->mbuf_off) {
2438 /* Exhausted packet, just free. */
2440 loc->mbuf = mbuf->next;
2441 rte_pktmbuf_free_seg(mbuf);
2443 assert(loc->mbuf_nseg > 1);
2448 dlen -= loc->mbuf_off;
2449 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2451 part = RTE_MIN(len, dlen);
2452 rte_memcpy(pdst, psrc, part);
2453 loc->mbuf_off += part;
2456 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2458 /* Exhausted packet, just free. */
2460 loc->mbuf = mbuf->next;
2461 rte_pktmbuf_free_seg(mbuf);
2463 assert(loc->mbuf_nseg >= 1);
2473 * Build the Ethernet Segment with inlined data from
2474 * multi-segment packet. Checks the boundary of WQEBB
2475 * and ring buffer wrapping, supports Software Parser,
2476 * Checksums and VLAN insertion Tx offload features.
2479 * Pointer to TX queue structure.
2481 * Pointer to burst routine local context.
2483 * Pointer to WQE to fill with built Ethernet Segment.
2485 * Length of VLAN tag insertion if any.
2487 * Length of data to inline (VLAN included, if any).
2489 * TSO flag, set mss field from the packet.
2491 * Configured Tx offloads mask. It is fully defined at
2492 * compile time and may be used for optimization.
2495 * Pointer to the next Data Segment (aligned and
2496 * possible NOT wrapped around - caller should do
2497 * wrapping check on its own).
2499 static __rte_always_inline struct mlx5_wqe_dseg *
2500 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2501 struct mlx5_txq_local *restrict loc,
2502 struct mlx5_wqe *restrict wqe,
2508 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2514 * Calculate and set check sum flags first, uint32_t field
2515 * in segment may be shared with Software Parser flags.
2517 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2520 csum |= loc->mbuf->tso_segsz;
2521 es->flags = rte_cpu_to_be_32(csum);
2523 es->flags = rte_cpu_to_le_32(csum);
2526 * Calculate and set Software Parser offsets and flags.
2527 * These flags a set for custom UDP and IP tunnel packets.
2529 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2530 /* Fill metadata field if needed. */
2531 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2532 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2533 loc->mbuf->tx_metadata : 0 : 0;
2534 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2536 sizeof(rte_v128u32_t)),
2537 "invalid Ethernet Segment data size");
2538 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2540 sizeof(struct rte_vlan_hdr) +
2541 2 * RTE_ETHER_ADDR_LEN),
2542 "invalid Ethernet Segment data size");
2543 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
2544 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2545 pdst = (uint8_t *)&es->inline_data;
2546 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2547 /* Implement VLAN tag insertion as part inline data. */
2548 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2549 pdst += 2 * RTE_ETHER_ADDR_LEN;
2550 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2551 ((RTE_ETHER_TYPE_VLAN << 16) |
2552 loc->mbuf->vlan_tci);
2553 pdst += sizeof(struct rte_vlan_hdr);
2554 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2556 assert(pdst < (uint8_t *)txq->wqes_end);
2558 * The WQEBB space availability is checked by caller.
2559 * Here we should be aware of WQE ring buffer wraparound only.
2561 part = (uint8_t *)txq->wqes_end - pdst;
2562 part = RTE_MIN(part, inlen);
2565 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2567 if (likely(!inlen)) {
2569 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2570 return (struct mlx5_wqe_dseg *)pdst;
2572 pdst = (uint8_t *)txq->wqes;
2578 * Build the Data Segment of pointer type.
2581 * Pointer to TX queue structure.
2583 * Pointer to burst routine local context.
2585 * Pointer to WQE to fill with built Data Segment.
2587 * Data buffer to point.
2589 * Data buffer length.
2591 * Configured Tx offloads mask. It is fully defined at
2592 * compile time and may be used for optimization.
2594 static __rte_always_inline void
2595 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2596 struct mlx5_txq_local *restrict loc,
2597 struct mlx5_wqe_dseg *restrict dseg,
2600 unsigned int olx __rte_unused)
2604 dseg->bcount = rte_cpu_to_be_32(len);
2605 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2606 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2610 * Build the Data Segment of pointer type or inline
2611 * if data length is less than buffer in minimal
2612 * Data Segment size.
2615 * Pointer to TX queue structure.
2617 * Pointer to burst routine local context.
2619 * Pointer to WQE to fill with built Data Segment.
2621 * Data buffer to point.
2623 * Data buffer length.
2625 * Configured Tx offloads mask. It is fully defined at
2626 * compile time and may be used for optimization.
2628 static __rte_always_inline void
2629 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2630 struct mlx5_txq_local *restrict loc,
2631 struct mlx5_wqe_dseg *restrict dseg,
2634 unsigned int olx __rte_unused)
2640 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2641 dseg->bcount = rte_cpu_to_be_32(len);
2642 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2643 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2647 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2648 /* Unrolled implementation of generic rte_memcpy. */
2649 dst = (uintptr_t)&dseg->inline_data[0];
2650 src = (uintptr_t)buf;
2651 #ifdef RTE_ARCH_STRICT_ALIGN
2652 memcpy(dst, src, len);
2655 *(uint64_t *)dst = *(uint64_t *)src;
2656 dst += sizeof(uint64_t);
2657 src += sizeof(uint64_t);
2660 *(uint32_t *)dst = *(uint32_t *)src;
2661 dst += sizeof(uint32_t);
2662 src += sizeof(uint32_t);
2665 *(uint16_t *)dst = *(uint16_t *)src;
2666 dst += sizeof(uint16_t);
2667 src += sizeof(uint16_t);
2670 *(uint8_t *)dst = *(uint8_t *)src;
2675 * Build the Data Segment of inlined data from single
2676 * segment packet, no VLAN insertion.
2679 * Pointer to TX queue structure.
2681 * Pointer to burst routine local context.
2683 * Pointer to WQE to fill with built Data Segment.
2685 * Data buffer to point.
2687 * Data buffer length.
2689 * Configured Tx offloads mask. It is fully defined at
2690 * compile time and may be used for optimization.
2693 * Pointer to the next Data Segment after inlined data.
2694 * Ring buffer wraparound check is needed. We do not
2695 * do it here because it may not be needed for the
2696 * last packet in the eMPW session.
2698 static __rte_always_inline struct mlx5_wqe_dseg *
2699 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2700 struct mlx5_txq_local *restrict loc __rte_unused,
2701 struct mlx5_wqe_dseg *restrict dseg,
2704 unsigned int olx __rte_unused)
2709 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2710 pdst = &dseg->inline_data[0];
2712 * The WQEBB space availability is checked by caller.
2713 * Here we should be aware of WQE ring buffer wraparound only.
2715 part = (uint8_t *)txq->wqes_end - pdst;
2716 part = RTE_MIN(part, len);
2718 rte_memcpy(pdst, buf, part);
2722 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2723 /* Note: no final wraparound check here. */
2724 return (struct mlx5_wqe_dseg *)pdst;
2726 pdst = (uint8_t *)txq->wqes;
2733 * Build the Data Segment of inlined data from single
2734 * segment packet with VLAN insertion.
2737 * Pointer to TX queue structure.
2739 * Pointer to burst routine local context.
2741 * Pointer to the dseg fill with built Data Segment.
2743 * Data buffer to point.
2745 * Data buffer length.
2747 * Configured Tx offloads mask. It is fully defined at
2748 * compile time and may be used for optimization.
2751 * Pointer to the next Data Segment after inlined data.
2752 * Ring buffer wraparound check is needed.
2754 static __rte_always_inline struct mlx5_wqe_dseg *
2755 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2756 struct mlx5_txq_local *restrict loc __rte_unused,
2757 struct mlx5_wqe_dseg *restrict dseg,
2760 unsigned int olx __rte_unused)
2766 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2767 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2768 (2 * RTE_ETHER_ADDR_LEN),
2769 "invalid Data Segment data size");
2770 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2771 MLX5_ETH_WQE_DATA_INLINE);
2772 pdst = &dseg->inline_data[0];
2773 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2774 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2775 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2776 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2777 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2778 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2779 loc->mbuf->vlan_tci);
2780 pdst += sizeof(struct rte_vlan_hdr);
2781 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2782 pdst = (uint8_t *)txq->wqes;
2784 * The WQEBB space availability is checked by caller.
2785 * Here we should be aware of WQE ring buffer wraparound only.
2787 part = (uint8_t *)txq->wqes_end - pdst;
2788 part = RTE_MIN(part, len);
2790 rte_memcpy(pdst, buf, part);
2794 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2795 /* Note: no final wraparound check here. */
2796 return (struct mlx5_wqe_dseg *)pdst;
2798 pdst = (uint8_t *)txq->wqes;
2805 * Build the Ethernet Segment with optionally inlined data with
2806 * VLAN insertion and following Data Segments (if any) from
2807 * multi-segment packet. Used by ordinary send and TSO.
2810 * Pointer to TX queue structure.
2812 * Pointer to burst routine local context.
2814 * Pointer to WQE to fill with built Ethernet/Data Segments.
2816 * Length of VLAN header to insert, 0 means no VLAN insertion.
2818 * Data length to inline. For TSO this parameter specifies
2819 * exact value, for ordinary send routine can be aligned by
2820 * caller to provide better WQE space saving and data buffer
2821 * start address alignment. This length includes VLAN header
2824 * Zero means ordinary send, inlined data can be extended,
2825 * otherwise this is TSO, inlined data length is fixed.
2827 * Configured Tx offloads mask. It is fully defined at
2828 * compile time and may be used for optimization.
2831 * Actual size of built WQE in segments.
2833 static __rte_always_inline unsigned int
2834 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2835 struct mlx5_txq_local *restrict loc,
2836 struct mlx5_wqe *restrict wqe,
2840 unsigned int olx __rte_unused)
2842 struct mlx5_wqe_dseg *restrict dseg;
2845 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2846 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2849 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2850 if (!loc->mbuf_nseg)
2853 * There are still some mbuf remaining, not inlined.
2854 * The first mbuf may be partially inlined and we
2855 * must process the possible non-zero data offset.
2857 if (loc->mbuf_off) {
2862 * Exhausted packets must be dropped before.
2863 * Non-zero offset means there are some data
2864 * remained in the packet.
2866 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2867 assert(rte_pktmbuf_data_len(loc->mbuf));
2868 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2870 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2872 * Build the pointer/minimal data Data Segment.
2873 * Do ring buffer wrapping check in advance.
2875 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2876 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2877 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2878 /* Store the mbuf to be freed on completion. */
2879 assert(loc->elts_free);
2880 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2883 if (--loc->mbuf_nseg == 0)
2885 loc->mbuf = loc->mbuf->next;
2889 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
2890 struct rte_mbuf *mbuf;
2892 /* Zero length segment found, just skip. */
2894 loc->mbuf = loc->mbuf->next;
2895 rte_pktmbuf_free_seg(mbuf);
2896 if (--loc->mbuf_nseg == 0)
2899 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2900 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2903 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
2904 rte_pktmbuf_data_len(loc->mbuf), olx);
2905 assert(loc->elts_free);
2906 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2909 if (--loc->mbuf_nseg == 0)
2911 loc->mbuf = loc->mbuf->next;
2916 /* Calculate actual segments used from the dseg pointer. */
2917 if ((uintptr_t)wqe < (uintptr_t)dseg)
2918 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
2920 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
2921 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
2926 * Tx one packet function for multi-segment TSO. Supports all
2927 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
2928 * sends one packet per WQE.
2930 * This routine is responsible for storing processed mbuf
2931 * into elts ring buffer and update elts_head.
2934 * Pointer to TX queue structure.
2936 * Pointer to burst routine local context.
2938 * Configured Tx offloads mask. It is fully defined at
2939 * compile time and may be used for optimization.
2942 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2943 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2944 * Local context variables partially updated.
2946 static __rte_always_inline enum mlx5_txcmp_code
2947 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
2948 struct mlx5_txq_local *restrict loc,
2951 struct mlx5_wqe *restrict wqe;
2952 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
2955 * Calculate data length to be inlined to estimate
2956 * the required space in WQE ring buffer.
2958 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
2959 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
2960 vlan = sizeof(struct rte_vlan_hdr);
2961 inlen = loc->mbuf->l2_len + vlan +
2962 loc->mbuf->l3_len + loc->mbuf->l4_len;
2963 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
2964 return MLX5_TXCMP_CODE_ERROR;
2965 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
2966 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
2967 /* Packet must contain all TSO headers. */
2968 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
2969 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
2970 inlen > (dlen + vlan)))
2971 return MLX5_TXCMP_CODE_ERROR;
2972 assert(inlen >= txq->inlen_mode);
2974 * Check whether there are enough free WQEBBs:
2976 * - Ethernet Segment
2977 * - First Segment of inlined Ethernet data
2978 * - ... data continued ...
2979 * - Data Segments of pointer/min inline type
2981 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
2982 MLX5_ESEG_MIN_INLINE_SIZE +
2984 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
2985 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
2986 return MLX5_TXCMP_CODE_EXIT;
2987 /* Check for maximal WQE size. */
2988 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
2989 return MLX5_TXCMP_CODE_ERROR;
2990 #ifdef MLX5_PMD_SOFT_COUNTERS
2991 /* Update sent data bytes/packets counters. */
2992 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
2993 loc->mbuf->tso_segsz;
2995 * One will be added for mbuf itself
2996 * at the end of the mlx5_tx_burst from
2997 * loc->pkts_sent field.
3000 txq->stats.opackets += ntcp;
3001 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3003 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3004 loc->wqe_last = wqe;
3005 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3006 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3007 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3008 txq->wqe_ci += (ds + 3) / 4;
3009 loc->wqe_free -= (ds + 3) / 4;
3010 return MLX5_TXCMP_CODE_MULTI;
3014 * Tx one packet function for multi-segment SEND. Supports all
3015 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3016 * sends one packet per WQE, without any data inlining in
3019 * This routine is responsible for storing processed mbuf
3020 * into elts ring buffer and update elts_head.
3023 * Pointer to TX queue structure.
3025 * Pointer to burst routine local context.
3027 * Configured Tx offloads mask. It is fully defined at
3028 * compile time and may be used for optimization.
3031 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3032 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3033 * Local context variables partially updated.
3035 static __rte_always_inline enum mlx5_txcmp_code
3036 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3037 struct mlx5_txq_local *restrict loc,
3040 struct mlx5_wqe_dseg *restrict dseg;
3041 struct mlx5_wqe *restrict wqe;
3042 unsigned int ds, nseg;
3044 assert(NB_SEGS(loc->mbuf) > 1);
3046 * No inline at all, it means the CPU cycles saving
3047 * is prioritized at configuration, we should not
3048 * copy any packet data to WQE.
3050 nseg = NB_SEGS(loc->mbuf);
3052 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3053 return MLX5_TXCMP_CODE_EXIT;
3054 /* Check for maximal WQE size. */
3055 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3056 return MLX5_TXCMP_CODE_ERROR;
3058 * Some Tx offloads may cause an error if
3059 * packet is not long enough, check against
3060 * assumed minimal length.
3062 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3063 return MLX5_TXCMP_CODE_ERROR;
3064 #ifdef MLX5_PMD_SOFT_COUNTERS
3065 /* Update sent data bytes counter. */
3066 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3067 if (MLX5_TXOFF_CONFIG(VLAN) &&
3068 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3069 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3072 * SEND WQE, one WQEBB:
3073 * - Control Segment, SEND opcode
3074 * - Ethernet Segment, optional VLAN, no inline
3075 * - Data Segments, pointer only type
3077 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3078 loc->wqe_last = wqe;
3079 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3080 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3081 dseg = &wqe->dseg[0];
3083 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3084 struct rte_mbuf *mbuf;
3087 * Zero length segment found, have to
3088 * correct total size of WQE in segments.
3089 * It is supposed to be rare occasion, so
3090 * in normal case (no zero length segments)
3091 * we avoid extra writing to the Control
3095 wqe->cseg.sq_ds -= RTE_BE32(1);
3097 loc->mbuf = mbuf->next;
3098 rte_pktmbuf_free_seg(mbuf);
3104 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3105 rte_pktmbuf_data_len(loc->mbuf), olx);
3106 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3111 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3112 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3113 loc->mbuf = loc->mbuf->next;
3116 txq->wqe_ci += (ds + 3) / 4;
3117 loc->wqe_free -= (ds + 3) / 4;
3118 return MLX5_TXCMP_CODE_MULTI;
3122 * Tx one packet function for multi-segment SEND. Supports all
3123 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3124 * sends one packet per WQE, with data inlining in
3125 * Ethernet Segment and minimal Data Segments.
3127 * This routine is responsible for storing processed mbuf
3128 * into elts ring buffer and update elts_head.
3131 * Pointer to TX queue structure.
3133 * Pointer to burst routine local context.
3135 * Configured Tx offloads mask. It is fully defined at
3136 * compile time and may be used for optimization.
3139 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3140 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3141 * Local context variables partially updated.
3143 static __rte_always_inline enum mlx5_txcmp_code
3144 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3145 struct mlx5_txq_local *restrict loc,
3148 struct mlx5_wqe *restrict wqe;
3149 unsigned int ds, inlen, dlen, vlan = 0;
3151 assert(MLX5_TXOFF_CONFIG(INLINE));
3152 assert(NB_SEGS(loc->mbuf) > 1);
3154 * First calculate data length to be inlined
3155 * to estimate the required space for WQE.
3157 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3158 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3159 vlan = sizeof(struct rte_vlan_hdr);
3160 inlen = dlen + vlan;
3161 /* Check against minimal length. */
3162 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3163 return MLX5_TXCMP_CODE_ERROR;
3164 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3165 if (inlen > txq->inlen_send) {
3166 struct rte_mbuf *mbuf;
3171 * Packet length exceeds the allowed inline
3172 * data length, check whether the minimal
3173 * inlining is required.
3175 if (txq->inlen_mode) {
3176 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3177 assert(txq->inlen_mode <= txq->inlen_send);
3178 inlen = txq->inlen_mode;
3180 if (!vlan || txq->vlan_en) {
3182 * VLAN insertion will be done inside by HW.
3183 * It is not utmost effective - VLAN flag is
3184 * checked twice, but we should proceed the
3185 * inlining length correctly and take into
3186 * account the VLAN header being inserted.
3188 return mlx5_tx_packet_multi_send
3191 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3194 * Now we know the minimal amount of data is requested
3195 * to inline. Check whether we should inline the buffers
3196 * from the chain beginning to eliminate some mbufs.
3199 nxlen = rte_pktmbuf_data_len(mbuf);
3200 if (unlikely(nxlen <= txq->inlen_send)) {
3201 /* We can inline first mbuf at least. */
3202 if (nxlen < inlen) {
3205 /* Scan mbufs till inlen filled. */
3210 nxlen = rte_pktmbuf_data_len(mbuf);
3212 } while (unlikely(nxlen < inlen));
3213 if (unlikely(nxlen > txq->inlen_send)) {
3214 /* We cannot inline entire mbuf. */
3215 smlen = inlen - smlen;
3216 start = rte_pktmbuf_mtod_offset
3217 (mbuf, uintptr_t, smlen);
3224 /* There should be not end of packet. */
3226 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3227 } while (unlikely(nxlen < txq->inlen_send));
3229 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3231 * Check whether we can do inline to align start
3232 * address of data buffer to cacheline.
3235 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3236 if (unlikely(start)) {
3238 if (start <= txq->inlen_send)
3243 * Check whether there are enough free WQEBBs:
3245 * - Ethernet Segment
3246 * - First Segment of inlined Ethernet data
3247 * - ... data continued ...
3248 * - Data Segments of pointer/min inline type
3250 * Estimate the number of Data Segments conservatively,
3251 * supposing no any mbufs is being freed during inlining.
3253 assert(inlen <= txq->inlen_send);
3254 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3255 MLX5_ESEG_MIN_INLINE_SIZE +
3257 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3258 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3259 return MLX5_TXCMP_CODE_EXIT;
3260 /* Check for maximal WQE size. */
3261 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3262 return MLX5_TXCMP_CODE_ERROR;
3263 #ifdef MLX5_PMD_SOFT_COUNTERS
3264 /* Update sent data bytes/packets counters. */
3265 txq->stats.obytes += dlen + vlan;
3267 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3268 loc->wqe_last = wqe;
3269 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3270 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3271 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3272 txq->wqe_ci += (ds + 3) / 4;
3273 loc->wqe_free -= (ds + 3) / 4;
3274 return MLX5_TXCMP_CODE_MULTI;
3278 * Tx burst function for multi-segment packets. Supports all
3279 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3280 * sends one packet per WQE. Function stops sending if it
3281 * encounters the single-segment packet.
3283 * This routine is responsible for storing processed mbuf
3284 * into elts ring buffer and update elts_head.
3287 * Pointer to TX queue structure.
3289 * Packets to transmit.
3291 * Number of packets in array.
3293 * Pointer to burst routine local context.
3295 * Configured Tx offloads mask. It is fully defined at
3296 * compile time and may be used for optimization.
3299 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3300 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3301 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3302 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3303 * Local context variables updated.
3305 static __rte_always_inline enum mlx5_txcmp_code
3306 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3307 struct rte_mbuf **restrict pkts,
3308 unsigned int pkts_n,
3309 struct mlx5_txq_local *restrict loc,
3312 assert(loc->elts_free && loc->wqe_free);
3313 assert(pkts_n > loc->pkts_sent);
3314 pkts += loc->pkts_sent + 1;
3315 pkts_n -= loc->pkts_sent;
3317 enum mlx5_txcmp_code ret;
3319 assert(NB_SEGS(loc->mbuf) > 1);
3321 * Estimate the number of free elts quickly but
3322 * conservatively. Some segment may be fully inlined
3323 * and freed, ignore this here - precise estimation
3326 if (loc->elts_free < NB_SEGS(loc->mbuf))
3327 return MLX5_TXCMP_CODE_EXIT;
3328 if (MLX5_TXOFF_CONFIG(TSO) &&
3329 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3330 /* Proceed with multi-segment TSO. */
3331 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3332 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3333 /* Proceed with multi-segment SEND with inlining. */
3334 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3336 /* Proceed with multi-segment SEND w/o inlining. */
3337 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3339 if (ret == MLX5_TXCMP_CODE_EXIT)
3340 return MLX5_TXCMP_CODE_EXIT;
3341 if (ret == MLX5_TXCMP_CODE_ERROR)
3342 return MLX5_TXCMP_CODE_ERROR;
3343 /* WQE is built, go to the next packet. */
3346 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3347 return MLX5_TXCMP_CODE_EXIT;
3348 loc->mbuf = *pkts++;
3350 rte_prefetch0(*pkts);
3351 if (likely(NB_SEGS(loc->mbuf) > 1))
3353 /* Here ends the series of multi-segment packets. */
3354 if (MLX5_TXOFF_CONFIG(TSO) &&
3355 unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3356 return MLX5_TXCMP_CODE_TSO;
3357 return MLX5_TXCMP_CODE_SINGLE;
3363 * Tx burst function for single-segment packets with TSO.
3364 * Supports all types of Tx offloads, except multi-packets.
3365 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3366 * Function stops sending if it encounters the multi-segment
3367 * packet or packet without TSO requested.
3369 * The routine is responsible for storing processed mbuf
3370 * into elts ring buffer and update elts_head if inline
3371 * offloads is requested due to possible early freeing
3372 * of the inlined mbufs (can not store pkts array in elts
3376 * Pointer to TX queue structure.
3378 * Packets to transmit.
3380 * Number of packets in array.
3382 * Pointer to burst routine local context.
3384 * Configured Tx offloads mask. It is fully defined at
3385 * compile time and may be used for optimization.
3388 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3389 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3390 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3391 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3392 * Local context variables updated.
3394 static __rte_always_inline enum mlx5_txcmp_code
3395 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3396 struct rte_mbuf **restrict pkts,
3397 unsigned int pkts_n,
3398 struct mlx5_txq_local *restrict loc,
3401 assert(loc->elts_free && loc->wqe_free);
3402 assert(pkts_n > loc->pkts_sent);
3403 pkts += loc->pkts_sent + 1;
3404 pkts_n -= loc->pkts_sent;
3406 struct mlx5_wqe_dseg *restrict dseg;
3407 struct mlx5_wqe *restrict wqe;
3408 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3411 assert(NB_SEGS(loc->mbuf) == 1);
3412 dlen = rte_pktmbuf_data_len(loc->mbuf);
3413 if (MLX5_TXOFF_CONFIG(VLAN) &&
3414 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3415 vlan = sizeof(struct rte_vlan_hdr);
3418 * First calculate the WQE size to check
3419 * whether we have enough space in ring buffer.
3421 hlen = loc->mbuf->l2_len + vlan +
3422 loc->mbuf->l3_len + loc->mbuf->l4_len;
3423 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3424 return MLX5_TXCMP_CODE_ERROR;
3425 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3426 hlen += loc->mbuf->outer_l2_len +
3427 loc->mbuf->outer_l3_len;
3428 /* Segment must contain all TSO headers. */
3429 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3430 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3431 hlen > (dlen + vlan)))
3432 return MLX5_TXCMP_CODE_ERROR;
3434 * Check whether there are enough free WQEBBs:
3436 * - Ethernet Segment
3437 * - First Segment of inlined Ethernet data
3438 * - ... data continued ...
3439 * - Finishing Data Segment of pointer type
3441 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3442 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3443 if (loc->wqe_free < ((ds + 3) / 4))
3444 return MLX5_TXCMP_CODE_EXIT;
3445 #ifdef MLX5_PMD_SOFT_COUNTERS
3446 /* Update sent data bytes/packets counters. */
3447 ntcp = (dlen + vlan - hlen +
3448 loc->mbuf->tso_segsz - 1) /
3449 loc->mbuf->tso_segsz;
3451 * One will be added for mbuf itself at the end
3452 * of the mlx5_tx_burst from loc->pkts_sent field.
3455 txq->stats.opackets += ntcp;
3456 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3459 * Build the TSO WQE:
3461 * - Ethernet Segment with hlen bytes inlined
3462 * - Data Segment of pointer type
3464 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3465 loc->wqe_last = wqe;
3466 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3467 MLX5_OPCODE_TSO, olx);
3468 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3469 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3470 dlen -= hlen - vlan;
3471 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3473 * WQE is built, update the loop parameters
3474 * and go to the next packet.
3476 txq->wqe_ci += (ds + 3) / 4;
3477 loc->wqe_free -= (ds + 3) / 4;
3478 if (MLX5_TXOFF_CONFIG(INLINE))
3479 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3483 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3484 return MLX5_TXCMP_CODE_EXIT;
3485 loc->mbuf = *pkts++;
3487 rte_prefetch0(*pkts);
3488 if (MLX5_TXOFF_CONFIG(MULTI) &&
3489 unlikely(NB_SEGS(loc->mbuf) > 1))
3490 return MLX5_TXCMP_CODE_MULTI;
3491 if (unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3492 return MLX5_TXCMP_CODE_SINGLE;
3493 /* Continue with the next TSO packet. */
3499 * Analyze the packet and select the best method to send.
3502 * Pointer to TX queue structure.
3504 * Pointer to burst routine local context.
3506 * Configured Tx offloads mask. It is fully defined at
3507 * compile time and may be used for optimization.
3509 * The predefined flag whether do complete check for
3510 * multi-segment packets and TSO.
3513 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3514 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3515 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3516 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3518 static __rte_always_inline enum mlx5_txcmp_code
3519 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3520 struct mlx5_txq_local *restrict loc,
3524 /* Check for multi-segment packet. */
3526 MLX5_TXOFF_CONFIG(MULTI) &&
3527 unlikely(NB_SEGS(loc->mbuf) > 1))
3528 return MLX5_TXCMP_CODE_MULTI;
3529 /* Check for TSO packet. */
3531 MLX5_TXOFF_CONFIG(TSO) &&
3532 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3533 return MLX5_TXCMP_CODE_TSO;
3534 /* Check if eMPW is enabled at all. */
3535 if (!MLX5_TXOFF_CONFIG(EMPW))
3536 return MLX5_TXCMP_CODE_SINGLE;
3537 /* Check if eMPW can be engaged. */
3538 if (MLX5_TXOFF_CONFIG(VLAN) &&
3539 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3540 (!MLX5_TXOFF_CONFIG(INLINE) ||
3541 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3542 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3544 * eMPW does not support VLAN insertion offload,
3545 * we have to inline the entire packet but
3546 * packet is too long for inlining.
3548 return MLX5_TXCMP_CODE_SINGLE;
3550 return MLX5_TXCMP_CODE_EMPW;
3554 * Check the next packet attributes to match with the eMPW batch ones.
3557 * Pointer to TX queue structure.
3559 * Pointer to Ethernet Segment of eMPW batch.
3561 * Pointer to burst routine local context.
3563 * Configured Tx offloads mask. It is fully defined at
3564 * compile time and may be used for optimization.
3567 * true - packet match with eMPW batch attributes.
3568 * false - no match, eMPW should be restarted.
3570 static __rte_always_inline bool
3571 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3572 struct mlx5_wqe_eseg *restrict es,
3573 struct mlx5_txq_local *restrict loc,
3576 uint8_t swp_flags = 0;
3578 /* Compare the checksum flags, if any. */
3579 if (MLX5_TXOFF_CONFIG(CSUM) &&
3580 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3582 /* Compare the Software Parser offsets and flags. */
3583 if (MLX5_TXOFF_CONFIG(SWP) &&
3584 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3585 es->swp_flags != swp_flags))
3587 /* Fill metadata field if needed. */
3588 if (MLX5_TXOFF_CONFIG(METADATA) &&
3589 es->metadata != (loc->mbuf->ol_flags & PKT_TX_METADATA ?
3590 loc->mbuf->tx_metadata : 0))
3592 /* There must be no VLAN packets in eMPW loop. */
3593 if (MLX5_TXOFF_CONFIG(VLAN))
3594 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3599 * Update send loop variables and WQE for eMPW loop
3600 * without data inlining. Number of Data Segments is
3601 * equal to the number of sent packets.
3604 * Pointer to TX queue structure.
3606 * Pointer to burst routine local context.
3608 * Number of packets/Data Segments/Packets.
3610 * Accumulated statistics, bytes sent
3612 * Configured Tx offloads mask. It is fully defined at
3613 * compile time and may be used for optimization.
3616 * true - packet match with eMPW batch attributes.
3617 * false - no match, eMPW should be restarted.
3619 static __rte_always_inline void
3620 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3621 struct mlx5_txq_local *restrict loc,
3624 unsigned int olx __rte_unused)
3626 assert(!MLX5_TXOFF_CONFIG(INLINE));
3627 #ifdef MLX5_PMD_SOFT_COUNTERS
3628 /* Update sent data bytes counter. */
3629 txq->stats.obytes += slen;
3633 loc->elts_free -= ds;
3634 loc->pkts_sent += ds;
3636 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3637 txq->wqe_ci += (ds + 3) / 4;
3638 loc->wqe_free -= (ds + 3) / 4;
3642 * Update send loop variables and WQE for eMPW loop
3643 * with data inlining. Gets the size of pushed descriptors
3644 * and data to the WQE.
3647 * Pointer to TX queue structure.
3649 * Pointer to burst routine local context.
3651 * Total size of descriptor/data in bytes.
3653 * Accumulated statistics, data bytes sent.
3655 * Configured Tx offloads mask. It is fully defined at
3656 * compile time and may be used for optimization.
3659 * true - packet match with eMPW batch attributes.
3660 * false - no match, eMPW should be restarted.
3662 static __rte_always_inline void
3663 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3664 struct mlx5_txq_local *restrict loc,
3667 unsigned int olx __rte_unused)
3669 assert(MLX5_TXOFF_CONFIG(INLINE));
3670 assert((len % MLX5_WSEG_SIZE) == 0);
3671 #ifdef MLX5_PMD_SOFT_COUNTERS
3672 /* Update sent data bytes counter. */
3673 txq->stats.obytes += slen;
3677 len = len / MLX5_WSEG_SIZE + 2;
3678 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3679 txq->wqe_ci += (len + 3) / 4;
3680 loc->wqe_free -= (len + 3) / 4;
3684 * The set of Tx burst functions for single-segment packets
3685 * without TSO and with Multi-Packet Writing feature support.
3686 * Supports all types of Tx offloads, except multi-packets
3689 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3690 * as many packet per WQE as it can. If eMPW is not configured
3691 * or packet can not be sent with eMPW (VLAN insertion) the
3692 * ordinary SEND opcode is used and only one packet placed
3695 * Functions stop sending if it encounters the multi-segment
3696 * packet or packet with TSO requested.
3698 * The routines are responsible for storing processed mbuf
3699 * into elts ring buffer and update elts_head if inlining
3700 * offload is requested. Otherwise the copying mbufs to elts
3701 * can be postponed and completed at the end of burst routine.
3704 * Pointer to TX queue structure.
3706 * Packets to transmit.
3708 * Number of packets in array.
3710 * Pointer to burst routine local context.
3712 * Configured Tx offloads mask. It is fully defined at
3713 * compile time and may be used for optimization.
3716 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3717 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3718 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3719 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3720 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3721 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3723 * Local context variables updated.
3726 * The routine sends packets with MLX5_OPCODE_EMPW
3727 * without inlining, this is dedicated optimized branch.
3728 * No VLAN insertion is supported.
3730 static __rte_always_inline enum mlx5_txcmp_code
3731 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3732 struct rte_mbuf **restrict pkts,
3733 unsigned int pkts_n,
3734 struct mlx5_txq_local *restrict loc,
3738 * Subroutine is the part of mlx5_tx_burst_single()
3739 * and sends single-segment packet with eMPW opcode
3740 * without data inlining.
3742 assert(!MLX5_TXOFF_CONFIG(INLINE));
3743 assert(MLX5_TXOFF_CONFIG(EMPW));
3744 assert(loc->elts_free && loc->wqe_free);
3745 assert(pkts_n > loc->pkts_sent);
3746 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3747 pkts += loc->pkts_sent + 1;
3748 pkts_n -= loc->pkts_sent;
3750 struct mlx5_wqe_dseg *restrict dseg;
3751 struct mlx5_wqe_eseg *restrict eseg;
3752 enum mlx5_txcmp_code ret;
3753 unsigned int part, loop;
3754 unsigned int slen = 0;
3757 part = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
3758 if (unlikely(loc->elts_free < part)) {
3759 /* We have no enough elts to save all mbufs. */
3760 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3761 return MLX5_TXCMP_CODE_EXIT;
3762 /* But we still able to send at least minimal eMPW. */
3763 part = loc->elts_free;
3765 /* Check whether we have enough WQEs */
3766 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3767 if (unlikely(loc->wqe_free <
3768 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3769 return MLX5_TXCMP_CODE_EXIT;
3770 part = (loc->wqe_free * 4) - 2;
3772 if (likely(part > 1))
3773 rte_prefetch0(*pkts);
3774 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3776 * Build eMPW title WQEBB:
3777 * - Control Segment, eMPW opcode
3778 * - Ethernet Segment, no inline
3780 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3781 MLX5_OPCODE_ENHANCED_MPSW, olx);
3782 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3783 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3784 eseg = &loc->wqe_last->eseg;
3785 dseg = &loc->wqe_last->dseg[0];
3788 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3789 #ifdef MLX5_PMD_SOFT_COUNTERS
3790 /* Update sent data bytes counter. */
3795 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3797 if (unlikely(--loop == 0))
3799 loc->mbuf = *pkts++;
3800 if (likely(loop > 1))
3801 rte_prefetch0(*pkts);
3802 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3804 * Unroll the completion code to avoid
3805 * returning variable value - it results in
3806 * unoptimized sequent checking in caller.
3808 if (ret == MLX5_TXCMP_CODE_MULTI) {
3810 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3811 if (unlikely(!loc->elts_free ||
3813 return MLX5_TXCMP_CODE_EXIT;
3814 return MLX5_TXCMP_CODE_MULTI;
3816 if (ret == MLX5_TXCMP_CODE_TSO) {
3818 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3819 if (unlikely(!loc->elts_free ||
3821 return MLX5_TXCMP_CODE_EXIT;
3822 return MLX5_TXCMP_CODE_TSO;
3824 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3826 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3827 if (unlikely(!loc->elts_free ||
3829 return MLX5_TXCMP_CODE_EXIT;
3830 return MLX5_TXCMP_CODE_SINGLE;
3832 if (ret != MLX5_TXCMP_CODE_EMPW) {
3835 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3836 return MLX5_TXCMP_CODE_ERROR;
3839 * Check whether packet parameters coincide
3840 * within assumed eMPW batch:
3841 * - check sum settings
3843 * - software parser settings
3845 if (!mlx5_tx_match_empw(txq, eseg, loc, olx)) {
3848 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3849 if (unlikely(!loc->elts_free ||
3851 return MLX5_TXCMP_CODE_EXIT;
3854 /* Packet attributes match, continue the same eMPW. */
3856 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3857 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3859 /* eMPW is built successfully, update loop parameters. */
3861 assert(pkts_n >= part);
3862 #ifdef MLX5_PMD_SOFT_COUNTERS
3863 /* Update sent data bytes counter. */
3864 txq->stats.obytes += slen;
3866 loc->elts_free -= part;
3867 loc->pkts_sent += part;
3868 txq->wqe_ci += (2 + part + 3) / 4;
3869 loc->wqe_free -= (2 + part + 3) / 4;
3871 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3872 return MLX5_TXCMP_CODE_EXIT;
3873 loc->mbuf = *pkts++;
3874 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3875 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
3877 /* Continue sending eMPW batches. */
3883 * The routine sends packets with MLX5_OPCODE_EMPW
3884 * with inlining, optionally supports VLAN insertion.
3886 static __rte_always_inline enum mlx5_txcmp_code
3887 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
3888 struct rte_mbuf **restrict pkts,
3889 unsigned int pkts_n,
3890 struct mlx5_txq_local *restrict loc,
3894 * Subroutine is the part of mlx5_tx_burst_single()
3895 * and sends single-segment packet with eMPW opcode
3896 * with data inlining.
3898 assert(MLX5_TXOFF_CONFIG(INLINE));
3899 assert(MLX5_TXOFF_CONFIG(EMPW));
3900 assert(loc->elts_free && loc->wqe_free);
3901 assert(pkts_n > loc->pkts_sent);
3902 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3903 pkts += loc->pkts_sent + 1;
3904 pkts_n -= loc->pkts_sent;
3906 struct mlx5_wqe_dseg *restrict dseg;
3907 struct mlx5_wqe_eseg *restrict eseg;
3908 enum mlx5_txcmp_code ret;
3909 unsigned int room, part;
3910 unsigned int slen = 0;
3913 /* Check whether we have minimal amount WQEs */
3914 if (unlikely(loc->wqe_free <
3915 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3916 return MLX5_TXCMP_CODE_EXIT;
3917 if (likely(pkts_n > 1))
3918 rte_prefetch0(*pkts);
3919 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3921 * Build eMPW title WQEBB:
3922 * - Control Segment, eMPW opcode, zero DS
3923 * - Ethernet Segment, no inline
3925 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
3926 MLX5_OPCODE_ENHANCED_MPSW, olx);
3927 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3928 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3929 eseg = &loc->wqe_last->eseg;
3930 dseg = &loc->wqe_last->dseg[0];
3931 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
3932 loc->wqe_free) * MLX5_WQE_SIZE -
3933 MLX5_WQE_CSEG_SIZE -
3935 /* Build WQE till we have space, packets and resources. */
3938 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3939 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
3942 assert(room >= MLX5_WQE_DSEG_SIZE);
3943 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
3944 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
3946 * Some Tx offloads may cause an error if
3947 * packet is not long enough, check against
3948 * assumed minimal length.
3950 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
3952 if (unlikely(!part))
3953 return MLX5_TXCMP_CODE_ERROR;
3955 * We have some successfully built
3956 * packet Data Segments to send.
3958 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3959 return MLX5_TXCMP_CODE_ERROR;
3961 /* Inline or not inline - that's the Question. */
3962 if (dlen > txq->inlen_empw)
3964 /* Inline entire packet, optional VLAN insertion. */
3965 tlen = sizeof(dseg->bcount) + dlen;
3966 if (MLX5_TXOFF_CONFIG(VLAN) &&
3967 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3969 * The packet length must be checked in
3970 * mlx5_tx_able_to_empw() and packet
3971 * fits into inline length guaranteed.
3973 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
3975 tlen += sizeof(struct rte_vlan_hdr);
3978 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
3980 #ifdef MLX5_PMD_SOFT_COUNTERS
3981 /* Update sent data bytes counter. */
3982 slen += sizeof(struct rte_vlan_hdr);
3987 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
3990 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
3991 assert(room >= tlen);
3994 * Packet data are completely inlined,
3995 * free the packet immediately.
3997 rte_pktmbuf_free_seg(loc->mbuf);
4001 * Not inlinable VLAN packets are
4002 * proceeded outside of this routine.
4004 assert(room >= MLX5_WQE_DSEG_SIZE);
4005 if (MLX5_TXOFF_CONFIG(VLAN))
4006 assert(!(loc->mbuf->ol_flags &
4008 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4009 /* We have to store mbuf in elts.*/
4010 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4011 room -= MLX5_WQE_DSEG_SIZE;
4012 /* Ring buffer wraparound is checked at the loop end.*/
4015 #ifdef MLX5_PMD_SOFT_COUNTERS
4016 /* Update sent data bytes counter. */
4022 if (unlikely(!pkts_n || !loc->elts_free)) {
4024 * We have no resources/packets to
4025 * continue build descriptors.
4028 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4029 return MLX5_TXCMP_CODE_EXIT;
4031 /* Check if we have minimal room left. */
4032 if (room < MLX5_WQE_DSEG_SIZE) {
4034 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4037 loc->mbuf = *pkts++;
4038 if (likely(pkts_n > 1))
4039 rte_prefetch0(*pkts);
4040 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4042 * Unroll the completion code to avoid
4043 * returning variable value - it results in
4044 * unoptimized sequent checking in caller.
4046 if (ret == MLX5_TXCMP_CODE_MULTI) {
4048 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4049 if (unlikely(!loc->elts_free ||
4051 return MLX5_TXCMP_CODE_EXIT;
4052 return MLX5_TXCMP_CODE_MULTI;
4054 if (ret == MLX5_TXCMP_CODE_TSO) {
4056 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4057 if (unlikely(!loc->elts_free ||
4059 return MLX5_TXCMP_CODE_EXIT;
4060 return MLX5_TXCMP_CODE_TSO;
4062 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4064 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4065 if (unlikely(!loc->elts_free ||
4067 return MLX5_TXCMP_CODE_EXIT;
4068 return MLX5_TXCMP_CODE_SINGLE;
4070 if (ret != MLX5_TXCMP_CODE_EMPW) {
4073 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4074 return MLX5_TXCMP_CODE_ERROR;
4077 * Check whether packet parameters coincide
4078 * within assumed eMPW batch:
4079 * - check sum settings
4081 * - software parser settings
4083 if (!mlx5_tx_match_empw(txq, eseg, loc, olx))
4085 /* Packet attributes match, continue the same eMPW. */
4086 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4087 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4090 * We get here to close an existing eMPW
4091 * session and start the new one.
4095 if (unlikely(!part))
4096 return MLX5_TXCMP_CODE_EXIT;
4097 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4098 if (unlikely(!loc->elts_free ||
4100 return MLX5_TXCMP_CODE_EXIT;
4107 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4108 * Data inlining and VLAN insertion are supported.
4110 static __rte_always_inline enum mlx5_txcmp_code
4111 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4112 struct rte_mbuf **restrict pkts,
4113 unsigned int pkts_n,
4114 struct mlx5_txq_local *restrict loc,
4118 * Subroutine is the part of mlx5_tx_burst_single()
4119 * and sends single-segment packet with SEND opcode.
4121 assert(loc->elts_free && loc->wqe_free);
4122 assert(pkts_n > loc->pkts_sent);
4123 pkts += loc->pkts_sent + 1;
4124 pkts_n -= loc->pkts_sent;
4126 struct mlx5_wqe *restrict wqe;
4127 enum mlx5_txcmp_code ret;
4129 assert(NB_SEGS(loc->mbuf) == 1);
4130 if (MLX5_TXOFF_CONFIG(INLINE)) {
4131 unsigned int inlen, vlan = 0;
4133 inlen = rte_pktmbuf_data_len(loc->mbuf);
4134 if (MLX5_TXOFF_CONFIG(VLAN) &&
4135 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4136 vlan = sizeof(struct rte_vlan_hdr);
4138 static_assert((sizeof(struct rte_vlan_hdr) +
4139 sizeof(struct rte_ether_hdr)) ==
4140 MLX5_ESEG_MIN_INLINE_SIZE,
4141 "invalid min inline data size");
4144 * If inlining is enabled at configuration time
4145 * the limit must be not less than minimal size.
4146 * Otherwise we would do extra check for data
4147 * size to avoid crashes due to length overflow.
4149 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4150 if (inlen <= txq->inlen_send) {
4151 unsigned int seg_n, wqe_n;
4153 rte_prefetch0(rte_pktmbuf_mtod
4154 (loc->mbuf, uint8_t *));
4155 /* Check against minimal length. */
4156 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4157 return MLX5_TXCMP_CODE_ERROR;
4159 * Completely inlined packet data WQE:
4160 * - Control Segment, SEND opcode
4161 * - Ethernet Segment, no VLAN insertion
4162 * - Data inlined, VLAN optionally inserted
4163 * - Alignment to MLX5_WSEG_SIZE
4164 * Have to estimate amount of WQEBBs
4166 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4167 MLX5_ESEG_MIN_INLINE_SIZE +
4168 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4169 /* Check if there are enough WQEBBs. */
4170 wqe_n = (seg_n + 3) / 4;
4171 if (wqe_n > loc->wqe_free)
4172 return MLX5_TXCMP_CODE_EXIT;
4173 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4174 loc->wqe_last = wqe;
4175 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4176 MLX5_OPCODE_SEND, olx);
4177 mlx5_tx_eseg_data(txq, loc, wqe,
4178 vlan, inlen, 0, olx);
4179 txq->wqe_ci += wqe_n;
4180 loc->wqe_free -= wqe_n;
4182 * Packet data are completely inlined,
4183 * free the packet immediately.
4185 rte_pktmbuf_free_seg(loc->mbuf);
4186 } else if (!MLX5_TXOFF_CONFIG(EMPW) &&
4189 * If minimal inlining is requested the eMPW
4190 * feature should be disabled due to data is
4191 * inlined into Ethernet Segment, which can
4192 * not contain inlined data for eMPW due to
4193 * segment shared for all packets.
4195 struct mlx5_wqe_dseg *restrict dseg;
4200 * The inline-mode settings require
4201 * to inline the specified amount of
4202 * data bytes to the Ethernet Segment.
4203 * We should check the free space in
4204 * WQE ring buffer to inline partially.
4206 assert(txq->inlen_send >= txq->inlen_mode);
4207 assert(inlen > txq->inlen_mode);
4208 assert(txq->inlen_mode >=
4209 MLX5_ESEG_MIN_INLINE_SIZE);
4211 * Check whether there are enough free WQEBBs:
4213 * - Ethernet Segment
4214 * - First Segment of inlined Ethernet data
4215 * - ... data continued ...
4216 * - Finishing Data Segment of pointer type
4218 ds = (MLX5_WQE_CSEG_SIZE +
4219 MLX5_WQE_ESEG_SIZE +
4220 MLX5_WQE_DSEG_SIZE +
4222 MLX5_ESEG_MIN_INLINE_SIZE +
4223 MLX5_WQE_DSEG_SIZE +
4224 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4225 if (loc->wqe_free < ((ds + 3) / 4))
4226 return MLX5_TXCMP_CODE_EXIT;
4228 * Build the ordinary SEND WQE:
4230 * - Ethernet Segment, inline inlen_mode bytes
4231 * - Data Segment of pointer type
4233 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4234 loc->wqe_last = wqe;
4235 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4236 MLX5_OPCODE_SEND, olx);
4237 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4240 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4241 txq->inlen_mode - vlan;
4242 inlen -= txq->inlen_mode;
4243 mlx5_tx_dseg_ptr(txq, loc, dseg,
4246 * WQE is built, update the loop parameters
4247 * and got to the next packet.
4249 txq->wqe_ci += (ds + 3) / 4;
4250 loc->wqe_free -= (ds + 3) / 4;
4251 /* We have to store mbuf in elts.*/
4252 assert(MLX5_TXOFF_CONFIG(INLINE));
4253 txq->elts[txq->elts_head++ & txq->elts_m] =
4261 * Partially inlined packet data WQE, we have
4262 * some space in title WQEBB, we can fill it
4263 * with some packet data. It takes one WQEBB,
4264 * it is available, no extra space check:
4265 * - Control Segment, SEND opcode
4266 * - Ethernet Segment, no VLAN insertion
4267 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4268 * - Data Segment, pointer type
4270 * We also get here if VLAN insertion is not
4271 * supported by HW, the inline is enabled.
4273 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4274 loc->wqe_last = wqe;
4275 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4276 MLX5_OPCODE_SEND, olx);
4277 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4278 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4279 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4281 * The length check is performed above, by
4282 * comparing with txq->inlen_send. We should
4283 * not get overflow here.
4285 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4286 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4287 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4291 /* We have to store mbuf in elts.*/
4292 assert(MLX5_TXOFF_CONFIG(INLINE));
4293 txq->elts[txq->elts_head++ & txq->elts_m] =
4297 #ifdef MLX5_PMD_SOFT_COUNTERS
4298 /* Update sent data bytes counter. */
4299 txq->stats.obytes += vlan +
4300 rte_pktmbuf_data_len(loc->mbuf);
4304 * No inline at all, it means the CPU cycles saving
4305 * is prioritized at configuration, we should not
4306 * copy any packet data to WQE.
4308 * SEND WQE, one WQEBB:
4309 * - Control Segment, SEND opcode
4310 * - Ethernet Segment, optional VLAN, no inline
4311 * - Data Segment, pointer type
4313 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4314 loc->wqe_last = wqe;
4315 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4316 MLX5_OPCODE_SEND, olx);
4317 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4319 (txq, loc, &wqe->dseg[0],
4320 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4321 rte_pktmbuf_data_len(loc->mbuf), olx);
4325 * We should not store mbuf pointer in elts
4326 * if no inlining is configured, this is done
4327 * by calling routine in a batch copy.
4329 assert(!MLX5_TXOFF_CONFIG(INLINE));
4331 #ifdef MLX5_PMD_SOFT_COUNTERS
4332 /* Update sent data bytes counter. */
4333 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4334 if (MLX5_TXOFF_CONFIG(VLAN) &&
4335 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4336 txq->stats.obytes +=
4337 sizeof(struct rte_vlan_hdr);
4342 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4343 return MLX5_TXCMP_CODE_EXIT;
4344 loc->mbuf = *pkts++;
4346 rte_prefetch0(*pkts);
4347 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4348 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4354 static __rte_always_inline enum mlx5_txcmp_code
4355 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4356 struct rte_mbuf **restrict pkts,
4357 unsigned int pkts_n,
4358 struct mlx5_txq_local *restrict loc,
4361 enum mlx5_txcmp_code ret;
4363 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4364 if (ret == MLX5_TXCMP_CODE_SINGLE)
4366 assert(ret == MLX5_TXCMP_CODE_EMPW);
4368 /* Optimize for inline/no inline eMPW send. */
4369 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4370 mlx5_tx_burst_empw_inline
4371 (txq, pkts, pkts_n, loc, olx) :
4372 mlx5_tx_burst_empw_simple
4373 (txq, pkts, pkts_n, loc, olx);
4374 if (ret != MLX5_TXCMP_CODE_SINGLE)
4376 /* The resources to send one packet should remain. */
4377 assert(loc->elts_free && loc->wqe_free);
4379 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4380 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4381 if (ret != MLX5_TXCMP_CODE_EMPW)
4383 /* The resources to send one packet should remain. */
4384 assert(loc->elts_free && loc->wqe_free);
4389 * DPDK Tx callback template. This is configured template
4390 * used to generate routines optimized for specified offload setup.
4391 * One of this generated functions is chosen at SQ configuration
4395 * Generic pointer to TX queue structure.
4397 * Packets to transmit.
4399 * Number of packets in array.
4401 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4402 * values. Should be static to take compile time static configuration
4406 * Number of packets successfully transmitted (<= pkts_n).
4408 static __rte_always_inline uint16_t
4409 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4410 struct rte_mbuf **restrict pkts,
4414 struct mlx5_txq_local loc;
4415 enum mlx5_txcmp_code ret;
4418 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4419 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4421 * Check if there are some CQEs, if any:
4422 * - process an encountered errors
4423 * - process the completed WQEs
4424 * - free related mbufs
4425 * - doorbell the NIC about processed CQEs
4427 if (unlikely(!pkts_n))
4429 rte_prefetch0(*pkts);
4430 mlx5_tx_handle_completion(txq, olx);
4432 * Calculate the number of available resources - elts and WQEs.
4433 * There are two possible different scenarios:
4434 * - no data inlining into WQEs, one WQEBB may contains upto
4435 * four packets, in this case elts become scarce resource
4436 * - data inlining into WQEs, one packet may require multiple
4437 * WQEBBs, the WQEs become the limiting factor.
4439 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4440 loc.elts_free = txq->elts_s -
4441 (uint16_t)(txq->elts_head - txq->elts_tail);
4442 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4443 loc.wqe_free = txq->wqe_s -
4444 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4445 if (unlikely(!loc.elts_free || !loc.wqe_free))
4449 loc.wqe_last = NULL;
4452 * Fetch the packet from array. Usually this is
4453 * the first packet in series of multi/single
4456 loc.mbuf = *(pkts + loc.pkts_sent);
4457 /* Dedicated branch for multi-segment packets. */
4458 if (MLX5_TXOFF_CONFIG(MULTI) &&
4459 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4461 * Multi-segment packet encountered.
4462 * Hardware is able to process it only
4463 * with SEND/TSO opcodes, one packet
4464 * per WQE, do it in dedicated routine.
4467 assert(loc.pkts_sent >= loc.pkts_copy);
4468 part = loc.pkts_sent - loc.pkts_copy;
4469 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4471 * There are some single-segment mbufs not
4472 * stored in elts. The mbufs must be in the
4473 * same order as WQEs, so we must copy the
4474 * mbufs to elts here, before the coming
4475 * multi-segment packet mbufs is appended.
4477 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4479 loc.pkts_copy = loc.pkts_sent;
4481 assert(pkts_n > loc.pkts_sent);
4482 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4483 if (!MLX5_TXOFF_CONFIG(INLINE))
4484 loc.pkts_copy = loc.pkts_sent;
4486 * These returned code checks are supposed
4487 * to be optimized out due to routine inlining.
4489 if (ret == MLX5_TXCMP_CODE_EXIT) {
4491 * The routine returns this code when
4492 * all packets are sent or there is no
4493 * enough resources to complete request.
4497 if (ret == MLX5_TXCMP_CODE_ERROR) {
4499 * The routine returns this code when
4500 * some error in the incoming packets
4503 txq->stats.oerrors++;
4506 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4508 * The single-segment packet was encountered
4509 * in the array, try to send it with the
4510 * best optimized way, possible engaging eMPW.
4512 goto enter_send_single;
4514 if (MLX5_TXOFF_CONFIG(TSO) &&
4515 ret == MLX5_TXCMP_CODE_TSO) {
4517 * The single-segment TSO packet was
4518 * encountered in the array.
4520 goto enter_send_tso;
4522 /* We must not get here. Something is going wrong. */
4524 txq->stats.oerrors++;
4527 /* Dedicated branch for single-segment TSO packets. */
4528 if (MLX5_TXOFF_CONFIG(TSO) &&
4529 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4531 * TSO might require special way for inlining
4532 * (dedicated parameters) and is sent with
4533 * MLX5_OPCODE_TSO opcode only, provide this
4534 * in dedicated branch.
4537 assert(NB_SEGS(loc.mbuf) == 1);
4538 assert(pkts_n > loc.pkts_sent);
4539 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4541 * These returned code checks are supposed
4542 * to be optimized out due to routine inlining.
4544 if (ret == MLX5_TXCMP_CODE_EXIT)
4546 if (ret == MLX5_TXCMP_CODE_ERROR) {
4547 txq->stats.oerrors++;
4550 if (ret == MLX5_TXCMP_CODE_SINGLE)
4551 goto enter_send_single;
4552 if (MLX5_TXOFF_CONFIG(MULTI) &&
4553 ret == MLX5_TXCMP_CODE_MULTI) {
4555 * The multi-segment packet was
4556 * encountered in the array.
4558 goto enter_send_multi;
4560 /* We must not get here. Something is going wrong. */
4562 txq->stats.oerrors++;
4566 * The dedicated branch for the single-segment packets
4567 * without TSO. Often these ones can be sent using
4568 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4569 * The routine builds the WQEs till it encounters
4570 * the TSO or multi-segment packet (in case if these
4571 * offloads are requested at SQ configuration time).
4574 assert(pkts_n > loc.pkts_sent);
4575 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4577 * These returned code checks are supposed
4578 * to be optimized out due to routine inlining.
4580 if (ret == MLX5_TXCMP_CODE_EXIT)
4582 if (ret == MLX5_TXCMP_CODE_ERROR) {
4583 txq->stats.oerrors++;
4586 if (MLX5_TXOFF_CONFIG(MULTI) &&
4587 ret == MLX5_TXCMP_CODE_MULTI) {
4589 * The multi-segment packet was
4590 * encountered in the array.
4592 goto enter_send_multi;
4594 if (MLX5_TXOFF_CONFIG(TSO) &&
4595 ret == MLX5_TXCMP_CODE_TSO) {
4597 * The single-segment TSO packet was
4598 * encountered in the array.
4600 goto enter_send_tso;
4602 /* We must not get here. Something is going wrong. */
4604 txq->stats.oerrors++;
4608 * Main Tx loop is completed, do the rest:
4609 * - set completion request if thresholds are reached
4610 * - doorbell the hardware
4611 * - copy the rest of mbufs to elts (if any)
4613 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4614 /* Take a shortcut if nothing is sent. */
4615 if (unlikely(loc.pkts_sent == 0))
4617 /* Not all of the mbufs may be stored into elts yet. */
4618 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
4619 mlx5_tx_request_completion(txq, part, &loc, olx);
4621 * Ring QP doorbell immediately after WQE building completion
4622 * to improve latencies. The pure software related data treatment
4623 * can be completed after doorbell. Tx CQEs for this SQ are
4624 * processed in this thread only by the polling.
4626 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);
4627 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4629 * There are some single-segment mbufs not stored in elts.
4630 * It can be only if last packet was single-segment.
4631 * The copying is gathered into one place due to it is
4632 * a good opportunity to optimize that with SIMD.
4633 * Unfortunately if inlining is enabled the gaps in
4634 * pointer array may happen due to early freeing of the
4637 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4639 #ifdef MLX5_PMD_SOFT_COUNTERS
4640 /* Increment sent packets counter. */
4641 txq->stats.opackets += loc.pkts_sent;
4643 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4644 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4645 return loc.pkts_sent;
4648 /* Generate routines with Enhanced Multi-Packet Write support. */
4649 MLX5_TXOFF_DECL(full_empw,
4650 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4652 MLX5_TXOFF_DECL(none_empw,
4653 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4655 MLX5_TXOFF_DECL(md_empw,
4656 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4658 MLX5_TXOFF_DECL(mt_empw,
4659 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4660 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4662 MLX5_TXOFF_DECL(mtsc_empw,
4663 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4664 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4665 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4667 MLX5_TXOFF_DECL(mti_empw,
4668 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4669 MLX5_TXOFF_CONFIG_INLINE |
4670 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4672 MLX5_TXOFF_DECL(mtv_empw,
4673 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4674 MLX5_TXOFF_CONFIG_VLAN |
4675 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4677 MLX5_TXOFF_DECL(mtiv_empw,
4678 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4679 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4680 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4682 MLX5_TXOFF_DECL(sc_empw,
4683 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4684 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4686 MLX5_TXOFF_DECL(sci_empw,
4687 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4688 MLX5_TXOFF_CONFIG_INLINE |
4689 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4691 MLX5_TXOFF_DECL(scv_empw,
4692 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4693 MLX5_TXOFF_CONFIG_VLAN |
4694 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4696 MLX5_TXOFF_DECL(sciv_empw,
4697 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4698 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4699 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4701 MLX5_TXOFF_DECL(i_empw,
4702 MLX5_TXOFF_CONFIG_INLINE |
4703 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4705 MLX5_TXOFF_DECL(v_empw,
4706 MLX5_TXOFF_CONFIG_VLAN |
4707 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4709 MLX5_TXOFF_DECL(iv_empw,
4710 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4711 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4713 /* Generate routines without Enhanced Multi-Packet Write support. */
4714 MLX5_TXOFF_DECL(full,
4715 MLX5_TXOFF_CONFIG_FULL)
4717 MLX5_TXOFF_DECL(none,
4718 MLX5_TXOFF_CONFIG_NONE)
4721 MLX5_TXOFF_CONFIG_METADATA)
4724 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4725 MLX5_TXOFF_CONFIG_METADATA)
4727 MLX5_TXOFF_DECL(mtsc,
4728 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4729 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4730 MLX5_TXOFF_CONFIG_METADATA)
4732 MLX5_TXOFF_DECL(mti,
4733 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4734 MLX5_TXOFF_CONFIG_INLINE |
4735 MLX5_TXOFF_CONFIG_METADATA)
4738 MLX5_TXOFF_DECL(mtv,
4739 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4740 MLX5_TXOFF_CONFIG_VLAN |
4741 MLX5_TXOFF_CONFIG_METADATA)
4744 MLX5_TXOFF_DECL(mtiv,
4745 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4746 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4747 MLX5_TXOFF_CONFIG_METADATA)
4750 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4751 MLX5_TXOFF_CONFIG_METADATA)
4753 MLX5_TXOFF_DECL(sci,
4754 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4755 MLX5_TXOFF_CONFIG_INLINE |
4756 MLX5_TXOFF_CONFIG_METADATA)
4759 MLX5_TXOFF_DECL(scv,
4760 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4761 MLX5_TXOFF_CONFIG_VLAN |
4762 MLX5_TXOFF_CONFIG_METADATA)
4765 MLX5_TXOFF_DECL(sciv,
4766 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4767 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4768 MLX5_TXOFF_CONFIG_METADATA)
4771 MLX5_TXOFF_CONFIG_INLINE |
4772 MLX5_TXOFF_CONFIG_METADATA)
4775 MLX5_TXOFF_CONFIG_VLAN |
4776 MLX5_TXOFF_CONFIG_METADATA)
4779 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4780 MLX5_TXOFF_CONFIG_METADATA)
4783 * Array of declared and compiled Tx burst function and corresponding
4784 * supported offloads set. The array is used to select the Tx burst
4785 * function for specified offloads set at Tx queue configuration time.
4788 eth_tx_burst_t func;
4791 MLX5_TXOFF_INFO(full_empw,
4792 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4793 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4794 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4795 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4797 MLX5_TXOFF_INFO(none_empw,
4798 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4800 MLX5_TXOFF_INFO(md_empw,
4801 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4803 MLX5_TXOFF_INFO(mt_empw,
4804 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4805 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4807 MLX5_TXOFF_INFO(mtsc_empw,
4808 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4809 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4810 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4812 MLX5_TXOFF_INFO(mti_empw,
4813 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4814 MLX5_TXOFF_CONFIG_INLINE |
4815 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4817 MLX5_TXOFF_INFO(mtv_empw,
4818 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4819 MLX5_TXOFF_CONFIG_VLAN |
4820 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4822 MLX5_TXOFF_INFO(mtiv_empw,
4823 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4824 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4825 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4827 MLX5_TXOFF_INFO(sc_empw,
4828 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4829 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4831 MLX5_TXOFF_INFO(sci_empw,
4832 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4833 MLX5_TXOFF_CONFIG_INLINE |
4834 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4836 MLX5_TXOFF_INFO(scv_empw,
4837 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4838 MLX5_TXOFF_CONFIG_VLAN |
4839 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4841 MLX5_TXOFF_INFO(sciv_empw,
4842 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4843 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4844 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4846 MLX5_TXOFF_INFO(i_empw,
4847 MLX5_TXOFF_CONFIG_INLINE |
4848 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4850 MLX5_TXOFF_INFO(v_empw,
4851 MLX5_TXOFF_CONFIG_VLAN |
4852 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4854 MLX5_TXOFF_INFO(iv_empw,
4855 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4856 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4858 MLX5_TXOFF_INFO(full,
4859 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4860 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4861 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4862 MLX5_TXOFF_CONFIG_METADATA)
4864 MLX5_TXOFF_INFO(none,
4865 MLX5_TXOFF_CONFIG_NONE)
4868 MLX5_TXOFF_CONFIG_METADATA)
4871 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4872 MLX5_TXOFF_CONFIG_METADATA)
4874 MLX5_TXOFF_INFO(mtsc,
4875 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4876 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4877 MLX5_TXOFF_CONFIG_METADATA)
4879 MLX5_TXOFF_INFO(mti,
4880 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4881 MLX5_TXOFF_CONFIG_INLINE |
4882 MLX5_TXOFF_CONFIG_METADATA)
4885 MLX5_TXOFF_INFO(mtv,
4886 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4887 MLX5_TXOFF_CONFIG_VLAN |
4888 MLX5_TXOFF_CONFIG_METADATA)
4890 MLX5_TXOFF_INFO(mtiv,
4891 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4892 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4893 MLX5_TXOFF_CONFIG_METADATA)
4896 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4897 MLX5_TXOFF_CONFIG_METADATA)
4899 MLX5_TXOFF_INFO(sci,
4900 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4901 MLX5_TXOFF_CONFIG_INLINE |
4902 MLX5_TXOFF_CONFIG_METADATA)
4904 MLX5_TXOFF_INFO(scv,
4905 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4906 MLX5_TXOFF_CONFIG_VLAN |
4907 MLX5_TXOFF_CONFIG_METADATA)
4909 MLX5_TXOFF_INFO(sciv,
4910 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4911 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4912 MLX5_TXOFF_CONFIG_METADATA)
4915 MLX5_TXOFF_CONFIG_INLINE |
4916 MLX5_TXOFF_CONFIG_METADATA)
4919 MLX5_TXOFF_CONFIG_VLAN |
4920 MLX5_TXOFF_CONFIG_METADATA)
4923 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4924 MLX5_TXOFF_CONFIG_METADATA)
4928 * Configure the Tx function to use. The routine checks configured
4929 * Tx offloads for the device and selects appropriate Tx burst
4930 * routine. There are multiple Tx burst routines compiled from
4931 * the same template in the most optimal way for the dedicated
4935 * Pointer to private data structure.
4938 * Pointer to selected Tx burst function.
4941 mlx5_select_tx_function(struct rte_eth_dev *dev)
4943 struct mlx5_priv *priv = dev->data->dev_private;
4944 struct mlx5_dev_config *config = &priv->config;
4945 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
4946 unsigned int diff = 0, olx = 0, i, m;
4948 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
4949 MLX5_DSEG_MAX, "invalid WQE max size");
4950 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
4951 "invalid WQE Control Segment size");
4952 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
4953 "invalid WQE Ethernet Segment size");
4954 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
4955 "invalid WQE Data Segment size");
4956 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
4957 "invalid WQE size");
4959 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
4960 /* We should support Multi-Segment Packets. */
4961 olx |= MLX5_TXOFF_CONFIG_MULTI;
4963 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
4964 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
4965 DEV_TX_OFFLOAD_GRE_TNL_TSO |
4966 DEV_TX_OFFLOAD_IP_TNL_TSO |
4967 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
4968 /* We should support TCP Send Offload. */
4969 olx |= MLX5_TXOFF_CONFIG_TSO;
4971 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
4972 DEV_TX_OFFLOAD_UDP_TNL_TSO |
4973 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
4974 /* We should support Software Parser for Tunnels. */
4975 olx |= MLX5_TXOFF_CONFIG_SWP;
4977 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
4978 DEV_TX_OFFLOAD_UDP_CKSUM |
4979 DEV_TX_OFFLOAD_TCP_CKSUM |
4980 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
4981 /* We should support IP/TCP/UDP Checksums. */
4982 olx |= MLX5_TXOFF_CONFIG_CSUM;
4984 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
4985 /* We should support VLAN insertion. */
4986 olx |= MLX5_TXOFF_CONFIG_VLAN;
4988 if (priv->txqs_n && (*priv->txqs)[0]) {
4989 struct mlx5_txq_data *txd = (*priv->txqs)[0];
4991 if (txd->inlen_send) {
4993 * Check the data inline requirements. Data inline
4994 * is enabled on per device basis, we can check
4995 * the first Tx queue only.
4997 * If device does not support VLAN insertion in WQE
4998 * and some queues are requested to perform VLAN
4999 * insertion offload than inline must be enabled.
5001 olx |= MLX5_TXOFF_CONFIG_INLINE;
5004 if (config->mps == MLX5_MPW_ENHANCED &&
5005 config->txq_inline_min <= 0) {
5007 * The NIC supports Enhanced Multi-Packet Write.
5008 * We do not support legacy MPW due to its
5009 * hardware related problems, so we just ignore
5010 * legacy MLX5_MPW settings. There should be no
5011 * minimal required inline data.
5013 olx |= MLX5_TXOFF_CONFIG_EMPW;
5015 if (tx_offloads & DEV_TX_OFFLOAD_MATCH_METADATA) {
5016 /* We should support Flow metadata. */
5017 olx |= MLX5_TXOFF_CONFIG_METADATA;
5020 * Scan the routines table to find the minimal
5021 * satisfying routine with requested offloads.
5023 m = RTE_DIM(txoff_func);
5024 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5027 tmp = txoff_func[i].olx;
5029 /* Meets requested offloads exactly.*/
5033 if ((tmp & olx) != olx) {
5034 /* Does not meet requested offloads at all. */
5037 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5038 /* Do not enable eMPW if not configured. */
5040 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5041 /* Do not enable inlining if not configured. */
5044 * Some routine meets the requirements.
5045 * Check whether it has minimal amount
5046 * of not requested offloads.
5048 tmp = __builtin_popcountl(tmp & ~olx);
5049 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5050 /* First or better match, save and continue. */
5056 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5057 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5058 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5059 /* Lighter not requested offload. */
5064 if (m >= RTE_DIM(txoff_func)) {
5065 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5066 " for requested offloads %04X",
5067 dev->data->port_id, olx);
5070 DRV_LOG(DEBUG, "port %u has selected Tx function"
5071 " supporting offloads %04X/%04X",
5072 dev->data->port_id, olx, txoff_func[m].olx);
5073 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5074 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5075 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5076 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5077 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5078 DRV_LOG(DEBUG, "\tSWP (software parser)");
5079 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5080 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5081 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5082 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5083 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5084 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5085 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5086 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5087 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW)
5088 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5089 return txoff_func[m].func;