4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe_seen(volatile struct mlx5_cqe *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe(volatile struct mlx5_cqe *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe(volatile struct mlx5_cqe *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 * Return the address of the WQE.
159 * Pointer to TX queue structure.
161 * WQE consumer index.
166 static inline uintptr_t *
167 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
169 ci &= ((1 << txq->wqe_n) - 1);
170 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
174 txq_complete(struct txq *txq) __attribute__((always_inline));
177 * Manage TX completions.
179 * When sending a burst, mlx5_tx_burst() posts several WRs.
182 * Pointer to TX queue structure.
185 txq_complete(struct txq *txq)
187 const unsigned int elts_n = 1 << txq->elts_n;
188 const unsigned int cqe_n = 1 << txq->cqe_n;
189 const unsigned int cqe_cnt = cqe_n - 1;
190 uint16_t elts_free = txq->elts_tail;
192 uint16_t cq_ci = txq->cq_ci;
193 volatile struct mlx5_cqe *cqe = NULL;
194 volatile struct mlx5_wqe_ctrl *ctrl;
197 volatile struct mlx5_cqe *tmp;
199 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
200 if (check_cqe(tmp, cqe_n, cq_ci))
204 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
205 if (!check_cqe_seen(cqe))
206 ERROR("unexpected compressed CQE, TX stopped");
209 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
210 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
211 if (!check_cqe_seen(cqe))
212 ERROR("unexpected error CQE, TX stopped");
218 if (unlikely(cqe == NULL))
220 ctrl = (volatile struct mlx5_wqe_ctrl *)
221 tx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));
222 elts_tail = ctrl->ctrl3;
223 assert(elts_tail < (1 << txq->wqe_n));
225 while (elts_free != elts_tail) {
226 struct rte_mbuf *elt = (*txq->elts)[elts_free];
227 unsigned int elts_free_next =
228 (elts_free + 1) & (elts_n - 1);
229 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
233 memset(&(*txq->elts)[elts_free],
235 sizeof((*txq->elts)[elts_free]));
237 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
238 /* Only one segment needs to be freed. */
239 rte_pktmbuf_free_seg(elt);
240 elts_free = elts_free_next;
243 txq->elts_tail = elts_tail;
244 /* Update the consumer index. */
246 *txq->cq_db = htonl(cq_ci);
250 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
251 * the cloned mbuf is allocated is returned instead.
257 * Memory pool where data is located for given mbuf.
259 static struct rte_mempool *
260 txq_mb2mp(struct rte_mbuf *buf)
262 if (unlikely(RTE_MBUF_INDIRECT(buf)))
263 return rte_mbuf_from_indirect(buf)->pool;
267 static inline uint32_t
268 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
269 __attribute__((always_inline));
272 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
273 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
274 * remove an entry first.
277 * Pointer to TX queue structure.
279 * Memory Pool for which a Memory Region lkey must be returned.
282 * mr->lkey on success, (uint32_t)-1 on failure.
284 static inline uint32_t
285 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
288 uint32_t lkey = (uint32_t)-1;
290 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
291 if (unlikely(txq->mp2mr[i].mp == NULL)) {
292 /* Unknown MP, add a new MR for it. */
295 if (txq->mp2mr[i].mp == mp) {
296 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
297 assert(htonl(txq->mp2mr[i].mr->lkey) ==
299 lkey = txq->mp2mr[i].lkey;
303 if (unlikely(lkey == (uint32_t)-1))
304 lkey = txq_mp2mr_reg(txq, mp, i);
309 * Ring TX queue doorbell.
312 * Pointer to TX queue structure.
315 mlx5_tx_dbrec(struct txq *txq)
317 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
319 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
320 htonl(txq->qp_num_8s),
325 *txq->qp_db = htonl(txq->wqe_ci);
326 /* Ensure ordering between DB record and BF copy. */
328 memcpy(dst, (uint8_t *)data, 16);
329 txq->bf_offset ^= (1 << txq->bf_buf_size);
336 * Pointer to TX queue structure.
338 * CQE consumer index.
341 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
343 volatile struct mlx5_cqe *cqe;
345 cqe = &(*txq->cqes)[ci & ((1 << txq->cqe_n) - 1)];
350 * DPDK callback for TX.
353 * Generic pointer to TX queue structure.
355 * Packets to transmit.
357 * Number of packets in array.
360 * Number of packets successfully transmitted (<= pkts_n).
363 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
365 struct txq *txq = (struct txq *)dpdk_txq;
366 uint16_t elts_head = txq->elts_head;
367 const unsigned int elts_n = 1 << txq->elts_n;
372 volatile struct mlx5_wqe_v *wqe = NULL;
373 unsigned int segs_n = 0;
374 struct rte_mbuf *buf = NULL;
377 if (unlikely(!pkts_n))
379 /* Prefetch first packet cacheline. */
380 tx_prefetch_cqe(txq, txq->cq_ci);
381 tx_prefetch_cqe(txq, txq->cq_ci + 1);
382 rte_prefetch0(*pkts);
383 /* Start processing. */
385 max = (elts_n - (elts_head - txq->elts_tail));
389 volatile rte_v128u32_t *dseg = NULL;
394 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
396 uint8_t cs_flags = 0;
397 #ifdef MLX5_PMD_SOFT_COUNTERS
398 uint32_t total_length = 0;
403 segs_n = buf->nb_segs;
405 * Make sure there is enough room to store this packet and
406 * that one ring entry remains unused.
409 if (max < segs_n + 1)
415 wqe = (volatile struct mlx5_wqe_v *)
416 tx_mlx5_wqe(txq, txq->wqe_ci);
417 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
419 rte_prefetch0(*pkts);
420 addr = rte_pktmbuf_mtod(buf, uintptr_t);
421 length = DATA_LEN(buf);
422 ehdr[0] = ((uint8_t *)addr)[0];
423 ehdr[1] = ((uint8_t *)addr)[1];
424 #ifdef MLX5_PMD_SOFT_COUNTERS
425 total_length = length;
427 assert(length >= MLX5_WQE_DWORD_SIZE);
428 /* Update element. */
429 (*txq->elts)[elts_head] = buf;
430 elts_head = (elts_head + 1) & (elts_n - 1);
431 /* Prefetch next buffer data. */
433 volatile void *pkt_addr;
435 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
436 rte_prefetch0(pkt_addr);
438 /* Should we enable HW CKSUM offload */
440 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
441 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
443 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
445 * Start by copying the Ethernet header minus the first two
446 * bytes which will be appended at the end of the Ethernet
449 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 16);
450 length -= MLX5_WQE_DWORD_SIZE;
451 addr += MLX5_WQE_DWORD_SIZE;
452 /* Replace the Ethernet type by the VLAN if necessary. */
453 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
454 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
456 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - 2 -
458 &vlan, sizeof(vlan));
459 addr -= sizeof(vlan);
460 length += sizeof(vlan);
462 /* Inline if enough room. */
463 if (txq->max_inline != 0) {
464 uintptr_t end = (uintptr_t)
465 (((uintptr_t)txq->wqes) +
466 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
467 uint16_t max_inline =
468 txq->max_inline * RTE_CACHE_LINE_SIZE;
472 * raw starts two bytes before the boundary to
473 * continue the above copy of packet data.
475 raw += MLX5_WQE_DWORD_SIZE - 2;
476 room = end - (uintptr_t)raw;
477 if (room > max_inline) {
478 uintptr_t addr_end = (addr + max_inline) &
479 ~(RTE_CACHE_LINE_SIZE - 1);
480 uint16_t copy_b = ((addr_end - addr) > length) ?
484 rte_memcpy((void *)raw, (void *)addr, copy_b);
487 pkt_inline_sz += copy_b;
489 assert(addr <= addr_end);
492 * 2 DWORDs consumed by the WQE header + 1 DSEG +
493 * the size of the inline part of the packet.
495 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
497 dseg = (volatile rte_v128u32_t *)
499 (ds * MLX5_WQE_DWORD_SIZE));
500 if ((uintptr_t)dseg >= end)
501 dseg = (volatile rte_v128u32_t *)
504 } else if (!segs_n) {
511 * No inline has been done in the packet, only the
512 * Ethernet Header as been stored.
514 dseg = (volatile rte_v128u32_t *)
515 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
518 /* Add the remaining packet as a simple ds. */
519 naddr = htonll(addr);
520 *dseg = (rte_v128u32_t){
522 txq_mp2mr(txq, txq_mb2mp(buf)),
535 * Spill on next WQE when the current one does not have
536 * enough room left. Size of WQE must a be a multiple
537 * of data segment size.
539 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
540 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
541 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
542 ((1 << txq->wqe_n) - 1);
544 dseg = (volatile rte_v128u32_t *)
546 rte_prefetch0(tx_mlx5_wqe(txq, n + 1));
553 length = DATA_LEN(buf);
554 #ifdef MLX5_PMD_SOFT_COUNTERS
555 total_length += length;
557 /* Store segment information. */
558 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
559 *dseg = (rte_v128u32_t){
561 txq_mp2mr(txq, txq_mb2mp(buf)),
565 (*txq->elts)[elts_head] = buf;
566 elts_head = (elts_head + 1) & (elts_n - 1);
575 /* Initialize known and common part of the WQE structure. */
576 wqe->ctrl = (rte_v128u32_t){
577 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
578 htonl(txq->qp_num_8s | ds),
582 wqe->eseg = (rte_v128u32_t){
586 (ehdr[1] << 24) | (ehdr[0] << 16) |
587 htons(pkt_inline_sz),
589 txq->wqe_ci += (ds + 3) / 4;
590 #ifdef MLX5_PMD_SOFT_COUNTERS
591 /* Increment sent bytes counter. */
592 txq->stats.obytes += total_length;
595 /* Take a shortcut if nothing must be sent. */
596 if (unlikely(i == 0))
598 /* Check whether completion threshold has been reached. */
599 comp = txq->elts_comp + i + j;
600 if (comp >= MLX5_TX_COMP_THRESH) {
601 volatile struct mlx5_wqe_ctrl *w =
602 (volatile struct mlx5_wqe_ctrl *)wqe;
604 /* Request completion on last WQE. */
606 /* Save elts_head in unused "immediate" field of WQE. */
607 w->ctrl3 = elts_head;
610 txq->elts_comp = comp;
612 #ifdef MLX5_PMD_SOFT_COUNTERS
613 /* Increment sent packets counter. */
614 txq->stats.opackets += i;
616 /* Ring QP doorbell. */
618 txq->elts_head = elts_head;
623 * Open a MPW session.
626 * Pointer to TX queue structure.
628 * Pointer to MPW session structure.
633 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
635 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
636 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
637 (volatile struct mlx5_wqe_data_seg (*)[])
638 tx_mlx5_wqe(txq, idx + 1);
640 mpw->state = MLX5_MPW_STATE_OPENED;
644 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
645 mpw->wqe->eseg.mss = htons(length);
646 mpw->wqe->eseg.inline_hdr_sz = 0;
647 mpw->wqe->eseg.rsvd0 = 0;
648 mpw->wqe->eseg.rsvd1 = 0;
649 mpw->wqe->eseg.rsvd2 = 0;
650 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
651 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
652 mpw->wqe->ctrl[2] = 0;
653 mpw->wqe->ctrl[3] = 0;
654 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
655 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
656 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
657 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
658 mpw->data.dseg[2] = &(*dseg)[0];
659 mpw->data.dseg[3] = &(*dseg)[1];
660 mpw->data.dseg[4] = &(*dseg)[2];
664 * Close a MPW session.
667 * Pointer to TX queue structure.
669 * Pointer to MPW session structure.
672 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
674 unsigned int num = mpw->pkts_n;
677 * Store size in multiple of 16 bytes. Control and Ethernet segments
680 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
681 mpw->state = MLX5_MPW_STATE_CLOSED;
686 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
687 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
691 * DPDK callback for TX with MPW support.
694 * Generic pointer to TX queue structure.
696 * Packets to transmit.
698 * Number of packets in array.
701 * Number of packets successfully transmitted (<= pkts_n).
704 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
706 struct txq *txq = (struct txq *)dpdk_txq;
707 uint16_t elts_head = txq->elts_head;
708 const unsigned int elts_n = 1 << txq->elts_n;
713 struct mlx5_mpw mpw = {
714 .state = MLX5_MPW_STATE_CLOSED,
717 if (unlikely(!pkts_n))
719 /* Prefetch first packet cacheline. */
720 tx_prefetch_cqe(txq, txq->cq_ci);
721 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
722 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
723 /* Start processing. */
725 max = (elts_n - (elts_head - txq->elts_tail));
729 struct rte_mbuf *buf = *(pkts++);
730 unsigned int elts_head_next;
732 unsigned int segs_n = buf->nb_segs;
733 uint32_t cs_flags = 0;
736 * Make sure there is enough room to store this packet and
737 * that one ring entry remains unused.
740 if (max < segs_n + 1)
742 /* Do not bother with large packets MPW cannot handle. */
743 if (segs_n > MLX5_MPW_DSEG_MAX)
747 /* Should we enable HW CKSUM offload */
749 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
750 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
751 /* Retrieve packet information. */
752 length = PKT_LEN(buf);
754 /* Start new session if packet differs. */
755 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
756 ((mpw.len != length) ||
758 (mpw.wqe->eseg.cs_flags != cs_flags)))
759 mlx5_mpw_close(txq, &mpw);
760 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
761 mlx5_mpw_new(txq, &mpw, length);
762 mpw.wqe->eseg.cs_flags = cs_flags;
764 /* Multi-segment packets must be alone in their MPW. */
765 assert((segs_n == 1) || (mpw.pkts_n == 0));
766 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
770 volatile struct mlx5_wqe_data_seg *dseg;
773 elts_head_next = (elts_head + 1) & (elts_n - 1);
775 (*txq->elts)[elts_head] = buf;
776 dseg = mpw.data.dseg[mpw.pkts_n];
777 addr = rte_pktmbuf_mtod(buf, uintptr_t);
778 *dseg = (struct mlx5_wqe_data_seg){
779 .byte_count = htonl(DATA_LEN(buf)),
780 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
781 .addr = htonll(addr),
783 elts_head = elts_head_next;
784 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
785 length += DATA_LEN(buf);
791 assert(length == mpw.len);
792 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
793 mlx5_mpw_close(txq, &mpw);
794 elts_head = elts_head_next;
795 #ifdef MLX5_PMD_SOFT_COUNTERS
796 /* Increment sent bytes counter. */
797 txq->stats.obytes += length;
801 /* Take a shortcut if nothing must be sent. */
802 if (unlikely(i == 0))
804 /* Check whether completion threshold has been reached. */
805 /* "j" includes both packets and segments. */
806 comp = txq->elts_comp + j;
807 if (comp >= MLX5_TX_COMP_THRESH) {
808 volatile struct mlx5_wqe *wqe = mpw.wqe;
810 /* Request completion on last WQE. */
811 wqe->ctrl[2] = htonl(8);
812 /* Save elts_head in unused "immediate" field of WQE. */
813 wqe->ctrl[3] = elts_head;
816 txq->elts_comp = comp;
818 #ifdef MLX5_PMD_SOFT_COUNTERS
819 /* Increment sent packets counter. */
820 txq->stats.opackets += i;
822 /* Ring QP doorbell. */
823 if (mpw.state == MLX5_MPW_STATE_OPENED)
824 mlx5_mpw_close(txq, &mpw);
826 txq->elts_head = elts_head;
831 * Open a MPW inline session.
834 * Pointer to TX queue structure.
836 * Pointer to MPW session structure.
841 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
843 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
844 struct mlx5_wqe_inl_small *inl;
846 mpw->state = MLX5_MPW_INL_STATE_OPENED;
850 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
851 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
854 mpw->wqe->ctrl[2] = 0;
855 mpw->wqe->ctrl[3] = 0;
856 mpw->wqe->eseg.mss = htons(length);
857 mpw->wqe->eseg.inline_hdr_sz = 0;
858 mpw->wqe->eseg.cs_flags = 0;
859 mpw->wqe->eseg.rsvd0 = 0;
860 mpw->wqe->eseg.rsvd1 = 0;
861 mpw->wqe->eseg.rsvd2 = 0;
862 inl = (struct mlx5_wqe_inl_small *)
863 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
864 mpw->data.raw = (uint8_t *)&inl->raw;
868 * Close a MPW inline session.
871 * Pointer to TX queue structure.
873 * Pointer to MPW session structure.
876 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
879 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
880 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
882 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
884 * Store size in multiple of 16 bytes. Control and Ethernet segments
887 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
888 mpw->state = MLX5_MPW_STATE_CLOSED;
889 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
890 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
894 * DPDK callback for TX with MPW inline support.
897 * Generic pointer to TX queue structure.
899 * Packets to transmit.
901 * Number of packets in array.
904 * Number of packets successfully transmitted (<= pkts_n).
907 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
910 struct txq *txq = (struct txq *)dpdk_txq;
911 uint16_t elts_head = txq->elts_head;
912 const unsigned int elts_n = 1 << txq->elts_n;
917 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
918 struct mlx5_mpw mpw = {
919 .state = MLX5_MPW_STATE_CLOSED,
922 if (unlikely(!pkts_n))
924 /* Prefetch first packet cacheline. */
925 tx_prefetch_cqe(txq, txq->cq_ci);
926 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
927 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
928 /* Start processing. */
930 max = (elts_n - (elts_head - txq->elts_tail));
934 struct rte_mbuf *buf = *(pkts++);
935 unsigned int elts_head_next;
938 unsigned int segs_n = buf->nb_segs;
939 uint32_t cs_flags = 0;
942 * Make sure there is enough room to store this packet and
943 * that one ring entry remains unused.
946 if (max < segs_n + 1)
948 /* Do not bother with large packets MPW cannot handle. */
949 if (segs_n > MLX5_MPW_DSEG_MAX)
953 /* Should we enable HW CKSUM offload */
955 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
956 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
957 /* Retrieve packet information. */
958 length = PKT_LEN(buf);
959 /* Start new session if packet differs. */
960 if (mpw.state == MLX5_MPW_STATE_OPENED) {
961 if ((mpw.len != length) ||
963 (mpw.wqe->eseg.cs_flags != cs_flags))
964 mlx5_mpw_close(txq, &mpw);
965 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
966 if ((mpw.len != length) ||
968 (length > inline_room) ||
969 (mpw.wqe->eseg.cs_flags != cs_flags)) {
970 mlx5_mpw_inline_close(txq, &mpw);
972 txq->max_inline * RTE_CACHE_LINE_SIZE;
975 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
977 (length > inline_room)) {
978 mlx5_mpw_new(txq, &mpw, length);
979 mpw.wqe->eseg.cs_flags = cs_flags;
981 mlx5_mpw_inline_new(txq, &mpw, length);
982 mpw.wqe->eseg.cs_flags = cs_flags;
985 /* Multi-segment packets must be alone in their MPW. */
986 assert((segs_n == 1) || (mpw.pkts_n == 0));
987 if (mpw.state == MLX5_MPW_STATE_OPENED) {
988 assert(inline_room ==
989 txq->max_inline * RTE_CACHE_LINE_SIZE);
990 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
994 volatile struct mlx5_wqe_data_seg *dseg;
997 (elts_head + 1) & (elts_n - 1);
999 (*txq->elts)[elts_head] = buf;
1000 dseg = mpw.data.dseg[mpw.pkts_n];
1001 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1002 *dseg = (struct mlx5_wqe_data_seg){
1003 .byte_count = htonl(DATA_LEN(buf)),
1004 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1005 .addr = htonll(addr),
1007 elts_head = elts_head_next;
1008 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1009 length += DATA_LEN(buf);
1015 assert(length == mpw.len);
1016 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1017 mlx5_mpw_close(txq, &mpw);
1021 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1022 assert(length <= inline_room);
1023 assert(length == DATA_LEN(buf));
1024 elts_head_next = (elts_head + 1) & (elts_n - 1);
1025 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1026 (*txq->elts)[elts_head] = buf;
1027 /* Maximum number of bytes before wrapping. */
1028 max = ((((uintptr_t)(txq->wqes)) +
1031 (uintptr_t)mpw.data.raw);
1033 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1036 mpw.data.raw = (volatile void *)txq->wqes;
1037 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1038 (void *)(addr + max),
1040 mpw.data.raw += length - max;
1042 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1045 mpw.data.raw += length;
1047 if ((uintptr_t)mpw.data.raw ==
1048 (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))
1049 mpw.data.raw = (volatile void *)txq->wqes;
1052 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1053 mlx5_mpw_inline_close(txq, &mpw);
1055 txq->max_inline * RTE_CACHE_LINE_SIZE;
1057 inline_room -= length;
1060 mpw.total_len += length;
1061 elts_head = elts_head_next;
1062 #ifdef MLX5_PMD_SOFT_COUNTERS
1063 /* Increment sent bytes counter. */
1064 txq->stats.obytes += length;
1068 /* Take a shortcut if nothing must be sent. */
1069 if (unlikely(i == 0))
1071 /* Check whether completion threshold has been reached. */
1072 /* "j" includes both packets and segments. */
1073 comp = txq->elts_comp + j;
1074 if (comp >= MLX5_TX_COMP_THRESH) {
1075 volatile struct mlx5_wqe *wqe = mpw.wqe;
1077 /* Request completion on last WQE. */
1078 wqe->ctrl[2] = htonl(8);
1079 /* Save elts_head in unused "immediate" field of WQE. */
1080 wqe->ctrl[3] = elts_head;
1083 txq->elts_comp = comp;
1085 #ifdef MLX5_PMD_SOFT_COUNTERS
1086 /* Increment sent packets counter. */
1087 txq->stats.opackets += i;
1089 /* Ring QP doorbell. */
1090 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1091 mlx5_mpw_inline_close(txq, &mpw);
1092 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1093 mlx5_mpw_close(txq, &mpw);
1095 txq->elts_head = elts_head;
1100 * Translate RX completion flags to packet type.
1105 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1108 * Packet type for struct rte_mbuf.
1110 static inline uint32_t
1111 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1114 uint8_t flags = cqe->l4_hdr_type_etc;
1116 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET)
1119 MLX5_CQE_RX_OUTER_IPV4_PACKET,
1120 RTE_PTYPE_L3_IPV4) |
1122 MLX5_CQE_RX_OUTER_IPV6_PACKET,
1123 RTE_PTYPE_L3_IPV6) |
1125 MLX5_CQE_RX_IPV4_PACKET,
1126 RTE_PTYPE_INNER_L3_IPV4) |
1128 MLX5_CQE_RX_IPV6_PACKET,
1129 RTE_PTYPE_INNER_L3_IPV6);
1133 MLX5_CQE_L3_HDR_TYPE_IPV6,
1134 RTE_PTYPE_L3_IPV6) |
1136 MLX5_CQE_L3_HDR_TYPE_IPV4,
1142 * Get size of the next packet for a given CQE. For compressed CQEs, the
1143 * consumer index is updated only once all packets of the current one have
1147 * Pointer to RX queue.
1150 * @param[out] rss_hash
1151 * Packet RSS Hash result.
1154 * Packet size in bytes (0 if there is none), -1 in case of completion
1158 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1159 uint16_t cqe_cnt, uint32_t *rss_hash)
1161 struct rxq_zip *zip = &rxq->zip;
1162 uint16_t cqe_n = cqe_cnt + 1;
1165 /* Process compressed data in the CQE and mini arrays. */
1167 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1168 (volatile struct mlx5_mini_cqe8 (*)[8])
1169 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1171 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1172 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1173 if ((++zip->ai & 7) == 0) {
1175 * Increment consumer index to skip the number of
1176 * CQEs consumed. Hardware leaves holes in the CQ
1177 * ring for software use.
1182 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1183 uint16_t idx = rxq->cq_ci + 1;
1184 uint16_t end = zip->cq_ci;
1186 while (idx != end) {
1187 (*rxq->cqes)[idx & cqe_cnt].op_own =
1188 MLX5_CQE_INVALIDATE;
1191 rxq->cq_ci = zip->cq_ci;
1194 /* No compressed data, get next CQE and verify if it is compressed. */
1199 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1200 if (unlikely(ret == 1))
1203 op_own = cqe->op_own;
1204 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1205 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1206 (volatile struct mlx5_mini_cqe8 (*)[8])
1207 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1210 /* Fix endianness. */
1211 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1213 * Current mini array position is the one returned by
1216 * If completion comprises several mini arrays, as a
1217 * special case the second one is located 7 CQEs after
1218 * the initial CQE instead of 8 for subsequent ones.
1220 zip->ca = rxq->cq_ci & cqe_cnt;
1221 zip->na = zip->ca + 7;
1222 /* Compute the next non compressed CQE. */
1224 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1225 /* Get packet size to return. */
1226 len = ntohl((*mc)[0].byte_cnt);
1227 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1230 len = ntohl(cqe->byte_cnt);
1231 *rss_hash = ntohl(cqe->rx_hash_res);
1233 /* Error while receiving packet. */
1234 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1241 * Translate RX completion flags to offload flags.
1244 * Pointer to RX queue structure.
1249 * Offload flags (ol_flags) for struct rte_mbuf.
1251 static inline uint32_t
1252 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1254 uint32_t ol_flags = 0;
1255 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1256 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1258 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1259 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1260 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1262 PKT_RX_IP_CKSUM_GOOD);
1263 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1264 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1265 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1266 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1267 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1269 PKT_RX_L4_CKSUM_GOOD);
1270 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1272 TRANSPOSE(cqe->l4_hdr_type_etc,
1273 MLX5_CQE_RX_OUTER_IP_CSUM_OK,
1274 PKT_RX_IP_CKSUM_GOOD) |
1275 TRANSPOSE(cqe->l4_hdr_type_etc,
1276 MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK,
1277 PKT_RX_L4_CKSUM_GOOD);
1282 * DPDK callback for RX.
1285 * Generic pointer to RX queue structure.
1287 * Array to store received packets.
1289 * Maximum number of packets in array.
1292 * Number of packets successfully received (<= pkts_n).
1295 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1297 struct rxq *rxq = dpdk_rxq;
1298 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1299 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1300 const unsigned int sges_n = rxq->sges_n;
1301 struct rte_mbuf *pkt = NULL;
1302 struct rte_mbuf *seg = NULL;
1303 volatile struct mlx5_cqe *cqe =
1304 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1306 unsigned int rq_ci = rxq->rq_ci << sges_n;
1307 int len; /* keep its value across iterations. */
1310 unsigned int idx = rq_ci & wqe_cnt;
1311 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1312 struct rte_mbuf *rep = (*rxq->elts)[idx];
1313 uint32_t rss_hash_res = 0;
1321 rep = rte_mbuf_raw_alloc(rxq->mp);
1322 if (unlikely(rep == NULL)) {
1323 ++rxq->stats.rx_nombuf;
1326 * no buffers before we even started,
1327 * bail out silently.
1331 while (pkt != seg) {
1332 assert(pkt != (*rxq->elts)[idx]);
1334 rte_mbuf_refcnt_set(pkt, 0);
1335 __rte_mbuf_raw_free(pkt);
1341 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1342 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1345 rte_mbuf_refcnt_set(rep, 0);
1346 __rte_mbuf_raw_free(rep);
1349 if (unlikely(len == -1)) {
1350 /* RX error, packet is likely too large. */
1351 rte_mbuf_refcnt_set(rep, 0);
1352 __rte_mbuf_raw_free(rep);
1353 ++rxq->stats.idropped;
1357 assert(len >= (rxq->crc_present << 2));
1358 /* Update packet information. */
1359 pkt->packet_type = 0;
1361 if (rss_hash_res && rxq->rss_hash) {
1362 pkt->hash.rss = rss_hash_res;
1363 pkt->ol_flags = PKT_RX_RSS_HASH;
1366 ((cqe->sop_drop_qpn !=
1367 htonl(MLX5_FLOW_MARK_INVALID)) ||
1368 (cqe->sop_drop_qpn !=
1369 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1371 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1372 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1373 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1375 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1379 rxq_cq_to_pkt_type(cqe);
1381 rxq_cq_to_ol_flags(rxq, cqe);
1383 if (cqe->l4_hdr_type_etc &
1384 MLX5_CQE_VLAN_STRIPPED) {
1385 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1386 PKT_RX_VLAN_STRIPPED;
1387 pkt->vlan_tci = ntohs(cqe->vlan_info);
1389 if (rxq->crc_present)
1390 len -= ETHER_CRC_LEN;
1394 DATA_LEN(rep) = DATA_LEN(seg);
1395 PKT_LEN(rep) = PKT_LEN(seg);
1396 SET_DATA_OFF(rep, DATA_OFF(seg));
1397 NB_SEGS(rep) = NB_SEGS(seg);
1398 PORT(rep) = PORT(seg);
1400 (*rxq->elts)[idx] = rep;
1402 * Fill NIC descriptor with the new buffer. The lkey and size
1403 * of the buffers are already known, only the buffer address
1406 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1407 if (len > DATA_LEN(seg)) {
1408 len -= DATA_LEN(seg);
1413 DATA_LEN(seg) = len;
1414 #ifdef MLX5_PMD_SOFT_COUNTERS
1415 /* Increment bytes counter. */
1416 rxq->stats.ibytes += PKT_LEN(pkt);
1418 /* Return packet. */
1424 /* Align consumer index to the next stride. */
1429 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1431 /* Update the consumer index. */
1432 rxq->rq_ci = rq_ci >> sges_n;
1434 *rxq->cq_db = htonl(rxq->cq_ci);
1436 *rxq->rq_db = htonl(rxq->rq_ci);
1437 #ifdef MLX5_PMD_SOFT_COUNTERS
1438 /* Increment packets counter. */
1439 rxq->stats.ipackets += i;
1445 * Dummy DPDK callback for TX.
1447 * This function is used to temporarily replace the real callback during
1448 * unsafe control operations on the queue, or in case of error.
1451 * Generic pointer to TX queue structure.
1453 * Packets to transmit.
1455 * Number of packets in array.
1458 * Number of packets successfully transmitted (<= pkts_n).
1461 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1470 * Dummy DPDK callback for RX.
1472 * This function is used to temporarily replace the real callback during
1473 * unsafe control operations on the queue, or in case of error.
1476 * Generic pointer to RX queue structure.
1478 * Array to store received packets.
1480 * Maximum number of packets in array.
1483 * Number of packets successfully received (<= pkts_n).
1486 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)