4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Manage TX completions.
200 * When sending a burst, mlx5_tx_burst() posts several WRs.
203 * Pointer to TX queue structure.
206 txq_complete(struct txq *txq)
208 const unsigned int elts_n = 1 << txq->elts_n;
209 const unsigned int cqe_n = 1 << txq->cqe_n;
210 const unsigned int cqe_cnt = cqe_n - 1;
211 uint16_t elts_free = txq->elts_tail;
213 uint16_t cq_ci = txq->cq_ci;
214 volatile struct mlx5_cqe *cqe = NULL;
215 volatile struct mlx5_wqe_ctrl *ctrl;
218 volatile struct mlx5_cqe *tmp;
220 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
221 if (check_cqe(tmp, cqe_n, cq_ci))
225 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
226 if (!check_cqe_seen(cqe))
227 ERROR("unexpected compressed CQE, TX stopped");
230 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
231 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
232 if (!check_cqe_seen(cqe))
233 ERROR("unexpected error CQE, TX stopped");
239 if (unlikely(cqe == NULL))
241 ctrl = (volatile struct mlx5_wqe_ctrl *)
242 tx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));
243 elts_tail = ctrl->ctrl3;
244 assert(elts_tail < (1 << txq->wqe_n));
246 while (elts_free != elts_tail) {
247 struct rte_mbuf *elt = (*txq->elts)[elts_free];
248 unsigned int elts_free_next =
249 (elts_free + 1) & (elts_n - 1);
250 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
254 memset(&(*txq->elts)[elts_free],
256 sizeof((*txq->elts)[elts_free]));
258 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
259 /* Only one segment needs to be freed. */
260 rte_pktmbuf_free_seg(elt);
261 elts_free = elts_free_next;
264 txq->elts_tail = elts_tail;
265 /* Update the consumer index. */
267 *txq->cq_db = htonl(cq_ci);
271 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
272 * the cloned mbuf is allocated is returned instead.
278 * Memory pool where data is located for given mbuf.
280 static struct rte_mempool *
281 txq_mb2mp(struct rte_mbuf *buf)
283 if (unlikely(RTE_MBUF_INDIRECT(buf)))
284 return rte_mbuf_from_indirect(buf)->pool;
289 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
290 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
291 * remove an entry first.
294 * Pointer to TX queue structure.
296 * Memory Pool for which a Memory Region lkey must be returned.
299 * mr->lkey on success, (uint32_t)-1 on failure.
301 static inline uint32_t
302 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
305 uint32_t lkey = (uint32_t)-1;
307 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
308 if (unlikely(txq->mp2mr[i].mp == NULL)) {
309 /* Unknown MP, add a new MR for it. */
312 if (txq->mp2mr[i].mp == mp) {
313 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
314 assert(htonl(txq->mp2mr[i].mr->lkey) ==
316 lkey = txq->mp2mr[i].lkey;
320 if (unlikely(lkey == (uint32_t)-1))
321 lkey = txq_mp2mr_reg(txq, mp, i);
326 * Ring TX queue doorbell.
329 * Pointer to TX queue structure.
331 * Pointer to the last WQE posted in the NIC.
334 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
336 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
337 volatile uint64_t *src = ((volatile uint64_t *)wqe);
340 *txq->qp_db = htonl(txq->wqe_ci);
341 /* Ensure ordering between DB record and BF copy. */
347 * DPDK callback for TX.
350 * Generic pointer to TX queue structure.
352 * Packets to transmit.
354 * Number of packets in array.
357 * Number of packets successfully transmitted (<= pkts_n).
360 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
362 struct txq *txq = (struct txq *)dpdk_txq;
363 uint16_t elts_head = txq->elts_head;
364 const unsigned int elts_n = 1 << txq->elts_n;
369 volatile struct mlx5_wqe_v *wqe = NULL;
370 unsigned int segs_n = 0;
371 struct rte_mbuf *buf = NULL;
374 if (unlikely(!pkts_n))
376 /* Prefetch first packet cacheline. */
377 rte_prefetch0(*pkts);
378 /* Start processing. */
380 max = (elts_n - (elts_head - txq->elts_tail));
384 volatile rte_v128u32_t *dseg = NULL;
389 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
391 uint8_t cs_flags = 0;
392 #ifdef MLX5_PMD_SOFT_COUNTERS
393 uint32_t total_length = 0;
398 segs_n = buf->nb_segs;
400 * Make sure there is enough room to store this packet and
401 * that one ring entry remains unused.
404 if (max < segs_n + 1)
410 wqe = (volatile struct mlx5_wqe_v *)
411 tx_mlx5_wqe(txq, txq->wqe_ci);
412 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
414 rte_prefetch0(*pkts);
415 addr = rte_pktmbuf_mtod(buf, uintptr_t);
416 length = DATA_LEN(buf);
417 ehdr = (((uint8_t *)addr)[1] << 8) |
418 ((uint8_t *)addr)[0];
419 #ifdef MLX5_PMD_SOFT_COUNTERS
420 total_length = length;
422 assert(length >= MLX5_WQE_DWORD_SIZE);
423 /* Update element. */
424 (*txq->elts)[elts_head] = buf;
425 elts_head = (elts_head + 1) & (elts_n - 1);
426 /* Prefetch next buffer data. */
428 volatile void *pkt_addr;
430 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
431 rte_prefetch0(pkt_addr);
433 /* Should we enable HW CKSUM offload */
435 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
436 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
438 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
440 * Start by copying the Ethernet header minus the first two
441 * bytes which will be appended at the end of the Ethernet
444 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 16);
445 length -= MLX5_WQE_DWORD_SIZE;
446 addr += MLX5_WQE_DWORD_SIZE;
447 /* Replace the Ethernet type by the VLAN if necessary. */
448 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
449 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
451 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - 2 -
453 &vlan, sizeof(vlan));
454 addr -= sizeof(vlan);
455 length += sizeof(vlan);
457 /* Inline if enough room. */
458 if (txq->max_inline != 0) {
459 uintptr_t end = (uintptr_t)
460 (((uintptr_t)txq->wqes) +
461 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
462 uint16_t max_inline =
463 txq->max_inline * RTE_CACHE_LINE_SIZE;
467 * raw starts two bytes before the boundary to
468 * continue the above copy of packet data.
470 raw += MLX5_WQE_DWORD_SIZE - 2;
471 room = end - (uintptr_t)raw;
472 if (room > max_inline) {
473 uintptr_t addr_end = (addr + max_inline) &
474 ~(RTE_CACHE_LINE_SIZE - 1);
475 uint16_t copy_b = ((addr_end - addr) > length) ?
479 rte_memcpy((void *)raw, (void *)addr, copy_b);
482 pkt_inline_sz += copy_b;
484 assert(addr <= addr_end);
487 * 2 DWORDs consumed by the WQE header + 1 DSEG +
488 * the size of the inline part of the packet.
490 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
492 dseg = (volatile rte_v128u32_t *)
494 (ds * MLX5_WQE_DWORD_SIZE));
495 if ((uintptr_t)dseg >= end)
496 dseg = (volatile rte_v128u32_t *)
499 } else if (!segs_n) {
506 * No inline has been done in the packet, only the
507 * Ethernet Header as been stored.
509 dseg = (volatile rte_v128u32_t *)
510 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
513 /* Add the remaining packet as a simple ds. */
514 naddr = htonll(addr);
515 *dseg = (rte_v128u32_t){
517 txq_mp2mr(txq, txq_mb2mp(buf)),
530 * Spill on next WQE when the current one does not have
531 * enough room left. Size of WQE must a be a multiple
532 * of data segment size.
534 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
535 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
536 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
537 ((1 << txq->wqe_n) - 1);
539 dseg = (volatile rte_v128u32_t *)
541 rte_prefetch0(tx_mlx5_wqe(txq, n + 1));
548 length = DATA_LEN(buf);
549 #ifdef MLX5_PMD_SOFT_COUNTERS
550 total_length += length;
552 /* Store segment information. */
553 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
554 *dseg = (rte_v128u32_t){
556 txq_mp2mr(txq, txq_mb2mp(buf)),
560 (*txq->elts)[elts_head] = buf;
561 elts_head = (elts_head + 1) & (elts_n - 1);
570 /* Initialize known and common part of the WQE structure. */
571 wqe->ctrl = (rte_v128u32_t){
572 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
573 htonl(txq->qp_num_8s | ds),
577 wqe->eseg = (rte_v128u32_t){
581 (ehdr << 16) | htons(pkt_inline_sz),
583 txq->wqe_ci += (ds + 3) / 4;
584 #ifdef MLX5_PMD_SOFT_COUNTERS
585 /* Increment sent bytes counter. */
586 txq->stats.obytes += total_length;
589 /* Take a shortcut if nothing must be sent. */
590 if (unlikely(i == 0))
592 /* Check whether completion threshold has been reached. */
593 comp = txq->elts_comp + i + j;
594 if (comp >= MLX5_TX_COMP_THRESH) {
595 volatile struct mlx5_wqe_ctrl *w =
596 (volatile struct mlx5_wqe_ctrl *)wqe;
598 /* Request completion on last WQE. */
600 /* Save elts_head in unused "immediate" field of WQE. */
601 w->ctrl3 = elts_head;
604 txq->elts_comp = comp;
606 #ifdef MLX5_PMD_SOFT_COUNTERS
607 /* Increment sent packets counter. */
608 txq->stats.opackets += i;
610 /* Ring QP doorbell. */
611 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
612 txq->elts_head = elts_head;
617 * Open a MPW session.
620 * Pointer to TX queue structure.
622 * Pointer to MPW session structure.
627 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
629 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
630 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
631 (volatile struct mlx5_wqe_data_seg (*)[])
632 tx_mlx5_wqe(txq, idx + 1);
634 mpw->state = MLX5_MPW_STATE_OPENED;
638 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
639 mpw->wqe->eseg.mss = htons(length);
640 mpw->wqe->eseg.inline_hdr_sz = 0;
641 mpw->wqe->eseg.rsvd0 = 0;
642 mpw->wqe->eseg.rsvd1 = 0;
643 mpw->wqe->eseg.rsvd2 = 0;
644 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
645 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
646 mpw->wqe->ctrl[2] = 0;
647 mpw->wqe->ctrl[3] = 0;
648 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
649 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
650 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
651 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
652 mpw->data.dseg[2] = &(*dseg)[0];
653 mpw->data.dseg[3] = &(*dseg)[1];
654 mpw->data.dseg[4] = &(*dseg)[2];
658 * Close a MPW session.
661 * Pointer to TX queue structure.
663 * Pointer to MPW session structure.
666 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
668 unsigned int num = mpw->pkts_n;
671 * Store size in multiple of 16 bytes. Control and Ethernet segments
674 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
675 mpw->state = MLX5_MPW_STATE_CLOSED;
680 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
681 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
685 * DPDK callback for TX with MPW support.
688 * Generic pointer to TX queue structure.
690 * Packets to transmit.
692 * Number of packets in array.
695 * Number of packets successfully transmitted (<= pkts_n).
698 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
700 struct txq *txq = (struct txq *)dpdk_txq;
701 uint16_t elts_head = txq->elts_head;
702 const unsigned int elts_n = 1 << txq->elts_n;
707 struct mlx5_mpw mpw = {
708 .state = MLX5_MPW_STATE_CLOSED,
711 if (unlikely(!pkts_n))
713 /* Prefetch first packet cacheline. */
714 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
715 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
716 /* Start processing. */
718 max = (elts_n - (elts_head - txq->elts_tail));
722 struct rte_mbuf *buf = *(pkts++);
723 unsigned int elts_head_next;
725 unsigned int segs_n = buf->nb_segs;
726 uint32_t cs_flags = 0;
729 * Make sure there is enough room to store this packet and
730 * that one ring entry remains unused.
733 if (max < segs_n + 1)
735 /* Do not bother with large packets MPW cannot handle. */
736 if (segs_n > MLX5_MPW_DSEG_MAX)
740 /* Should we enable HW CKSUM offload */
742 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
743 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
744 /* Retrieve packet information. */
745 length = PKT_LEN(buf);
747 /* Start new session if packet differs. */
748 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
749 ((mpw.len != length) ||
751 (mpw.wqe->eseg.cs_flags != cs_flags)))
752 mlx5_mpw_close(txq, &mpw);
753 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
754 mlx5_mpw_new(txq, &mpw, length);
755 mpw.wqe->eseg.cs_flags = cs_flags;
757 /* Multi-segment packets must be alone in their MPW. */
758 assert((segs_n == 1) || (mpw.pkts_n == 0));
759 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
763 volatile struct mlx5_wqe_data_seg *dseg;
766 elts_head_next = (elts_head + 1) & (elts_n - 1);
768 (*txq->elts)[elts_head] = buf;
769 dseg = mpw.data.dseg[mpw.pkts_n];
770 addr = rte_pktmbuf_mtod(buf, uintptr_t);
771 *dseg = (struct mlx5_wqe_data_seg){
772 .byte_count = htonl(DATA_LEN(buf)),
773 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
774 .addr = htonll(addr),
776 elts_head = elts_head_next;
777 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
778 length += DATA_LEN(buf);
784 assert(length == mpw.len);
785 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
786 mlx5_mpw_close(txq, &mpw);
787 elts_head = elts_head_next;
788 #ifdef MLX5_PMD_SOFT_COUNTERS
789 /* Increment sent bytes counter. */
790 txq->stats.obytes += length;
794 /* Take a shortcut if nothing must be sent. */
795 if (unlikely(i == 0))
797 /* Check whether completion threshold has been reached. */
798 /* "j" includes both packets and segments. */
799 comp = txq->elts_comp + j;
800 if (comp >= MLX5_TX_COMP_THRESH) {
801 volatile struct mlx5_wqe *wqe = mpw.wqe;
803 /* Request completion on last WQE. */
804 wqe->ctrl[2] = htonl(8);
805 /* Save elts_head in unused "immediate" field of WQE. */
806 wqe->ctrl[3] = elts_head;
809 txq->elts_comp = comp;
811 #ifdef MLX5_PMD_SOFT_COUNTERS
812 /* Increment sent packets counter. */
813 txq->stats.opackets += i;
815 /* Ring QP doorbell. */
816 if (mpw.state == MLX5_MPW_STATE_OPENED)
817 mlx5_mpw_close(txq, &mpw);
818 mlx5_tx_dbrec(txq, mpw.wqe);
819 txq->elts_head = elts_head;
824 * Open a MPW inline session.
827 * Pointer to TX queue structure.
829 * Pointer to MPW session structure.
834 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
836 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
837 struct mlx5_wqe_inl_small *inl;
839 mpw->state = MLX5_MPW_INL_STATE_OPENED;
843 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
844 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
847 mpw->wqe->ctrl[2] = 0;
848 mpw->wqe->ctrl[3] = 0;
849 mpw->wqe->eseg.mss = htons(length);
850 mpw->wqe->eseg.inline_hdr_sz = 0;
851 mpw->wqe->eseg.cs_flags = 0;
852 mpw->wqe->eseg.rsvd0 = 0;
853 mpw->wqe->eseg.rsvd1 = 0;
854 mpw->wqe->eseg.rsvd2 = 0;
855 inl = (struct mlx5_wqe_inl_small *)
856 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
857 mpw->data.raw = (uint8_t *)&inl->raw;
861 * Close a MPW inline session.
864 * Pointer to TX queue structure.
866 * Pointer to MPW session structure.
869 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
872 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
873 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
875 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
877 * Store size in multiple of 16 bytes. Control and Ethernet segments
880 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
881 mpw->state = MLX5_MPW_STATE_CLOSED;
882 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
883 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
887 * DPDK callback for TX with MPW inline support.
890 * Generic pointer to TX queue structure.
892 * Packets to transmit.
894 * Number of packets in array.
897 * Number of packets successfully transmitted (<= pkts_n).
900 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
903 struct txq *txq = (struct txq *)dpdk_txq;
904 uint16_t elts_head = txq->elts_head;
905 const unsigned int elts_n = 1 << txq->elts_n;
910 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
911 struct mlx5_mpw mpw = {
912 .state = MLX5_MPW_STATE_CLOSED,
915 if (unlikely(!pkts_n))
917 /* Prefetch first packet cacheline. */
918 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
919 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
920 /* Start processing. */
922 max = (elts_n - (elts_head - txq->elts_tail));
926 struct rte_mbuf *buf = *(pkts++);
927 unsigned int elts_head_next;
930 unsigned int segs_n = buf->nb_segs;
931 uint32_t cs_flags = 0;
934 * Make sure there is enough room to store this packet and
935 * that one ring entry remains unused.
938 if (max < segs_n + 1)
940 /* Do not bother with large packets MPW cannot handle. */
941 if (segs_n > MLX5_MPW_DSEG_MAX)
945 /* Should we enable HW CKSUM offload */
947 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
948 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
949 /* Retrieve packet information. */
950 length = PKT_LEN(buf);
951 /* Start new session if packet differs. */
952 if (mpw.state == MLX5_MPW_STATE_OPENED) {
953 if ((mpw.len != length) ||
955 (mpw.wqe->eseg.cs_flags != cs_flags))
956 mlx5_mpw_close(txq, &mpw);
957 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
958 if ((mpw.len != length) ||
960 (length > inline_room) ||
961 (mpw.wqe->eseg.cs_flags != cs_flags)) {
962 mlx5_mpw_inline_close(txq, &mpw);
964 txq->max_inline * RTE_CACHE_LINE_SIZE;
967 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
969 (length > inline_room)) {
970 mlx5_mpw_new(txq, &mpw, length);
971 mpw.wqe->eseg.cs_flags = cs_flags;
973 mlx5_mpw_inline_new(txq, &mpw, length);
974 mpw.wqe->eseg.cs_flags = cs_flags;
977 /* Multi-segment packets must be alone in their MPW. */
978 assert((segs_n == 1) || (mpw.pkts_n == 0));
979 if (mpw.state == MLX5_MPW_STATE_OPENED) {
980 assert(inline_room ==
981 txq->max_inline * RTE_CACHE_LINE_SIZE);
982 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
986 volatile struct mlx5_wqe_data_seg *dseg;
989 (elts_head + 1) & (elts_n - 1);
991 (*txq->elts)[elts_head] = buf;
992 dseg = mpw.data.dseg[mpw.pkts_n];
993 addr = rte_pktmbuf_mtod(buf, uintptr_t);
994 *dseg = (struct mlx5_wqe_data_seg){
995 .byte_count = htonl(DATA_LEN(buf)),
996 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
997 .addr = htonll(addr),
999 elts_head = elts_head_next;
1000 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1001 length += DATA_LEN(buf);
1007 assert(length == mpw.len);
1008 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1009 mlx5_mpw_close(txq, &mpw);
1013 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1014 assert(length <= inline_room);
1015 assert(length == DATA_LEN(buf));
1016 elts_head_next = (elts_head + 1) & (elts_n - 1);
1017 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1018 (*txq->elts)[elts_head] = buf;
1019 /* Maximum number of bytes before wrapping. */
1020 max = ((((uintptr_t)(txq->wqes)) +
1023 (uintptr_t)mpw.data.raw);
1025 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1028 mpw.data.raw = (volatile void *)txq->wqes;
1029 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1030 (void *)(addr + max),
1032 mpw.data.raw += length - max;
1034 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1037 mpw.data.raw += length;
1039 if ((uintptr_t)mpw.data.raw ==
1040 (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))
1041 mpw.data.raw = (volatile void *)txq->wqes;
1044 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1045 mlx5_mpw_inline_close(txq, &mpw);
1047 txq->max_inline * RTE_CACHE_LINE_SIZE;
1049 inline_room -= length;
1052 mpw.total_len += length;
1053 elts_head = elts_head_next;
1054 #ifdef MLX5_PMD_SOFT_COUNTERS
1055 /* Increment sent bytes counter. */
1056 txq->stats.obytes += length;
1060 /* Take a shortcut if nothing must be sent. */
1061 if (unlikely(i == 0))
1063 /* Check whether completion threshold has been reached. */
1064 /* "j" includes both packets and segments. */
1065 comp = txq->elts_comp + j;
1066 if (comp >= MLX5_TX_COMP_THRESH) {
1067 volatile struct mlx5_wqe *wqe = mpw.wqe;
1069 /* Request completion on last WQE. */
1070 wqe->ctrl[2] = htonl(8);
1071 /* Save elts_head in unused "immediate" field of WQE. */
1072 wqe->ctrl[3] = elts_head;
1075 txq->elts_comp = comp;
1077 #ifdef MLX5_PMD_SOFT_COUNTERS
1078 /* Increment sent packets counter. */
1079 txq->stats.opackets += i;
1081 /* Ring QP doorbell. */
1082 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1083 mlx5_mpw_inline_close(txq, &mpw);
1084 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1085 mlx5_mpw_close(txq, &mpw);
1086 mlx5_tx_dbrec(txq, mpw.wqe);
1087 txq->elts_head = elts_head;
1092 * Translate RX completion flags to packet type.
1097 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1100 * Packet type for struct rte_mbuf.
1102 static inline uint32_t
1103 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1106 uint8_t flags = cqe->l4_hdr_type_etc;
1108 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET)
1111 MLX5_CQE_RX_OUTER_IPV4_PACKET,
1112 RTE_PTYPE_L3_IPV4) |
1114 MLX5_CQE_RX_OUTER_IPV6_PACKET,
1115 RTE_PTYPE_L3_IPV6) |
1117 MLX5_CQE_RX_IPV4_PACKET,
1118 RTE_PTYPE_INNER_L3_IPV4) |
1120 MLX5_CQE_RX_IPV6_PACKET,
1121 RTE_PTYPE_INNER_L3_IPV6);
1125 MLX5_CQE_L3_HDR_TYPE_IPV6,
1126 RTE_PTYPE_L3_IPV6) |
1128 MLX5_CQE_L3_HDR_TYPE_IPV4,
1134 * Get size of the next packet for a given CQE. For compressed CQEs, the
1135 * consumer index is updated only once all packets of the current one have
1139 * Pointer to RX queue.
1142 * @param[out] rss_hash
1143 * Packet RSS Hash result.
1146 * Packet size in bytes (0 if there is none), -1 in case of completion
1150 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1151 uint16_t cqe_cnt, uint32_t *rss_hash)
1153 struct rxq_zip *zip = &rxq->zip;
1154 uint16_t cqe_n = cqe_cnt + 1;
1157 /* Process compressed data in the CQE and mini arrays. */
1159 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1160 (volatile struct mlx5_mini_cqe8 (*)[8])
1161 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1163 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1164 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1165 if ((++zip->ai & 7) == 0) {
1167 * Increment consumer index to skip the number of
1168 * CQEs consumed. Hardware leaves holes in the CQ
1169 * ring for software use.
1174 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1175 uint16_t idx = rxq->cq_ci + 1;
1176 uint16_t end = zip->cq_ci;
1178 while (idx != end) {
1179 (*rxq->cqes)[idx & cqe_cnt].op_own =
1180 MLX5_CQE_INVALIDATE;
1183 rxq->cq_ci = zip->cq_ci;
1186 /* No compressed data, get next CQE and verify if it is compressed. */
1191 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1192 if (unlikely(ret == 1))
1195 op_own = cqe->op_own;
1196 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1197 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1198 (volatile struct mlx5_mini_cqe8 (*)[8])
1199 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1202 /* Fix endianness. */
1203 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1205 * Current mini array position is the one returned by
1208 * If completion comprises several mini arrays, as a
1209 * special case the second one is located 7 CQEs after
1210 * the initial CQE instead of 8 for subsequent ones.
1212 zip->ca = rxq->cq_ci & cqe_cnt;
1213 zip->na = zip->ca + 7;
1214 /* Compute the next non compressed CQE. */
1216 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1217 /* Get packet size to return. */
1218 len = ntohl((*mc)[0].byte_cnt);
1219 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1222 len = ntohl(cqe->byte_cnt);
1223 *rss_hash = ntohl(cqe->rx_hash_res);
1225 /* Error while receiving packet. */
1226 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1233 * Translate RX completion flags to offload flags.
1236 * Pointer to RX queue structure.
1241 * Offload flags (ol_flags) for struct rte_mbuf.
1243 static inline uint32_t
1244 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1246 uint32_t ol_flags = 0;
1247 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1248 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1250 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1251 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1252 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1254 PKT_RX_IP_CKSUM_GOOD);
1255 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1256 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1257 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1258 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1259 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1261 PKT_RX_L4_CKSUM_GOOD);
1262 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1264 TRANSPOSE(cqe->l4_hdr_type_etc,
1265 MLX5_CQE_RX_OUTER_IP_CSUM_OK,
1266 PKT_RX_IP_CKSUM_GOOD) |
1267 TRANSPOSE(cqe->l4_hdr_type_etc,
1268 MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK,
1269 PKT_RX_L4_CKSUM_GOOD);
1274 * DPDK callback for RX.
1277 * Generic pointer to RX queue structure.
1279 * Array to store received packets.
1281 * Maximum number of packets in array.
1284 * Number of packets successfully received (<= pkts_n).
1287 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1289 struct rxq *rxq = dpdk_rxq;
1290 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1291 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1292 const unsigned int sges_n = rxq->sges_n;
1293 struct rte_mbuf *pkt = NULL;
1294 struct rte_mbuf *seg = NULL;
1295 volatile struct mlx5_cqe *cqe =
1296 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1298 unsigned int rq_ci = rxq->rq_ci << sges_n;
1299 int len; /* keep its value across iterations. */
1302 unsigned int idx = rq_ci & wqe_cnt;
1303 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1304 struct rte_mbuf *rep = (*rxq->elts)[idx];
1305 uint32_t rss_hash_res = 0;
1313 rep = rte_mbuf_raw_alloc(rxq->mp);
1314 if (unlikely(rep == NULL)) {
1315 ++rxq->stats.rx_nombuf;
1318 * no buffers before we even started,
1319 * bail out silently.
1323 while (pkt != seg) {
1324 assert(pkt != (*rxq->elts)[idx]);
1326 rte_mbuf_refcnt_set(pkt, 0);
1327 __rte_mbuf_raw_free(pkt);
1333 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1334 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1337 rte_mbuf_refcnt_set(rep, 0);
1338 __rte_mbuf_raw_free(rep);
1341 if (unlikely(len == -1)) {
1342 /* RX error, packet is likely too large. */
1343 rte_mbuf_refcnt_set(rep, 0);
1344 __rte_mbuf_raw_free(rep);
1345 ++rxq->stats.idropped;
1349 assert(len >= (rxq->crc_present << 2));
1350 /* Update packet information. */
1351 pkt->packet_type = 0;
1353 if (rss_hash_res && rxq->rss_hash) {
1354 pkt->hash.rss = rss_hash_res;
1355 pkt->ol_flags = PKT_RX_RSS_HASH;
1358 ((cqe->sop_drop_qpn !=
1359 htonl(MLX5_FLOW_MARK_INVALID)) ||
1360 (cqe->sop_drop_qpn !=
1361 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1363 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1364 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1365 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1367 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1371 rxq_cq_to_pkt_type(cqe);
1373 rxq_cq_to_ol_flags(rxq, cqe);
1375 if (cqe->l4_hdr_type_etc &
1376 MLX5_CQE_VLAN_STRIPPED) {
1377 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1378 PKT_RX_VLAN_STRIPPED;
1379 pkt->vlan_tci = ntohs(cqe->vlan_info);
1381 if (rxq->crc_present)
1382 len -= ETHER_CRC_LEN;
1386 DATA_LEN(rep) = DATA_LEN(seg);
1387 PKT_LEN(rep) = PKT_LEN(seg);
1388 SET_DATA_OFF(rep, DATA_OFF(seg));
1389 NB_SEGS(rep) = NB_SEGS(seg);
1390 PORT(rep) = PORT(seg);
1392 (*rxq->elts)[idx] = rep;
1394 * Fill NIC descriptor with the new buffer. The lkey and size
1395 * of the buffers are already known, only the buffer address
1398 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1399 if (len > DATA_LEN(seg)) {
1400 len -= DATA_LEN(seg);
1405 DATA_LEN(seg) = len;
1406 #ifdef MLX5_PMD_SOFT_COUNTERS
1407 /* Increment bytes counter. */
1408 rxq->stats.ibytes += PKT_LEN(pkt);
1410 /* Return packet. */
1416 /* Align consumer index to the next stride. */
1421 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1423 /* Update the consumer index. */
1424 rxq->rq_ci = rq_ci >> sges_n;
1426 *rxq->cq_db = htonl(rxq->cq_ci);
1428 *rxq->rq_db = htonl(rxq->rq_ci);
1429 #ifdef MLX5_PMD_SOFT_COUNTERS
1430 /* Increment packets counter. */
1431 rxq->stats.ipackets += i;
1437 * Dummy DPDK callback for TX.
1439 * This function is used to temporarily replace the real callback during
1440 * unsafe control operations on the queue, or in case of error.
1443 * Generic pointer to TX queue structure.
1445 * Packets to transmit.
1447 * Number of packets in array.
1450 * Number of packets successfully transmitted (<= pkts_n).
1453 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1462 * Dummy DPDK callback for RX.
1464 * This function is used to temporarily replace the real callback during
1465 * unsafe control operations on the queue, or in case of error.
1468 * Generic pointer to RX queue structure.
1470 * Array to store received packets.
1472 * Maximum number of packets in array.
1475 * Number of packets successfully received (<= pkts_n).
1478 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)