1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
25 #include "mlx5_utils.h"
26 #include "mlx5_rxtx.h"
31 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
32 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
33 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
35 sizeof(rte_v128u32_t)),
36 "invalid Ethernet Segment data size");
37 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
39 sizeof(struct rte_vlan_hdr) +
40 2 * RTE_ETHER_ADDR_LEN),
41 "invalid Ethernet Segment data size");
42 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
44 sizeof(rte_v128u32_t)),
45 "invalid Ethernet Segment data size");
46 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
48 sizeof(struct rte_vlan_hdr) +
49 2 * RTE_ETHER_ADDR_LEN),
50 "invalid Ethernet Segment data size");
51 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
53 sizeof(rte_v128u32_t)),
54 "invalid Ethernet Segment data size");
55 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
57 sizeof(struct rte_vlan_hdr) +
58 2 * RTE_ETHER_ADDR_LEN),
59 "invalid Ethernet Segment data size");
60 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
61 (2 * RTE_ETHER_ADDR_LEN),
62 "invalid Data Segment data size");
63 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
64 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
65 static_assert((sizeof(struct rte_vlan_hdr) +
66 sizeof(struct rte_ether_hdr)) ==
67 MLX5_ESEG_MIN_INLINE_SIZE,
68 "invalid min inline data size");
69 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
70 MLX5_DSEG_MAX, "invalid WQE max size");
71 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
72 "invalid WQE Control Segment size");
73 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
74 "invalid WQE Ethernet Segment size");
75 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
76 "invalid WQE Data Segment size");
77 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
80 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
81 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
84 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
85 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
87 uint64_t rte_net_mlx5_dynf_inline_mask;
90 * Build a table to translate Rx completion flags to packet type.
92 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
95 mlx5_set_ptype_table(void)
98 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
100 /* Last entry must not be overwritten, reserved for errored packet. */
101 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
102 (*p)[i] = RTE_PTYPE_UNKNOWN;
104 * The index to the array should have:
105 * bit[1:0] = l3_hdr_type
106 * bit[4:2] = l4_hdr_type
109 * bit[7] = outer_l3_type
112 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
114 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 RTE_PTYPE_L4_NONFRAG;
116 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
117 RTE_PTYPE_L4_NONFRAG;
119 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
121 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
124 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
126 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
128 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
130 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
132 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
134 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
137 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
139 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
141 /* Repeat with outer_l3_type being set. Just in case. */
142 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
143 RTE_PTYPE_L4_NONFRAG;
144 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_L4_NONFRAG;
146 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
148 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
150 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
152 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
156 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
158 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
168 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
169 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L4_NONFRAG;
171 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
172 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L4_NONFRAG;
174 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
175 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_NONFRAG;
178 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_NONFRAG;
181 /* Tunneled - Fragmented */
182 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L4_FRAG;
185 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L4_FRAG;
188 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L4_FRAG;
191 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
193 RTE_PTYPE_INNER_L4_FRAG;
195 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L4_TCP;
198 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
199 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L4_TCP;
201 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
202 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
203 RTE_PTYPE_INNER_L4_TCP;
204 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
206 RTE_PTYPE_INNER_L4_TCP;
207 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
209 RTE_PTYPE_INNER_L4_TCP;
210 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L4_TCP;
213 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_TCP;
216 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_TCP;
219 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_TCP;
222 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L4_TCP;
225 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_TCP;
228 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
229 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_UDP;
235 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_UDP;
238 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_UDP;
241 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_UDP;
247 * Build a table to translate packet to checksum type of Verbs.
250 mlx5_set_cksum_table(void)
256 * The index should have:
257 * bit[0] = RTE_MBUF_F_TX_TCP_SEG
258 * bit[2:3] = RTE_MBUF_F_TX_UDP_CKSUM, RTE_MBUF_F_TX_TCP_CKSUM
259 * bit[4] = RTE_MBUF_F_TX_IP_CKSUM
260 * bit[8] = RTE_MBUF_F_TX_OUTER_IP_CKSUM
263 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
266 /* Tunneled packet. */
267 if (i & (1 << 8)) /* Outer IP. */
268 v |= MLX5_ETH_WQE_L3_CSUM;
269 if (i & (1 << 4)) /* Inner IP. */
270 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
271 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
272 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
275 if (i & (1 << 4)) /* IP. */
276 v |= MLX5_ETH_WQE_L3_CSUM;
277 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
278 v |= MLX5_ETH_WQE_L4_CSUM;
280 mlx5_cksum_table[i] = v;
285 * Build a table to translate packet type of mbuf to SWP type of Verbs.
288 mlx5_set_swp_types_table(void)
294 * The index should have:
295 * bit[0:1] = RTE_MBUF_F_TX_L4_MASK
296 * bit[4] = RTE_MBUF_F_TX_IPV6
297 * bit[8] = RTE_MBUF_F_TX_OUTER_IPV6
298 * bit[9] = RTE_MBUF_F_TX_OUTER_UDP
300 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
303 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
305 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
307 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
308 if ((i & 3) == (RTE_MBUF_F_TX_UDP_CKSUM >> 52))
309 v |= MLX5_ETH_WQE_L4_INNER_UDP;
310 mlx5_swp_types_table[i] = v;
314 #define MLX5_SYSTEM_LOG_DIR "/var/log"
316 * Dump debug information to log file.
321 * If not NULL this string is printed as a header to the output
322 * and the output will be in hexadecimal view.
324 * This is the buffer address to print out.
326 * The number of bytes to dump out.
329 mlx5_dump_debug_information(const char *fname, const char *hex_title,
330 const void *buf, unsigned int hex_len)
334 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
335 fd = fopen(path, "a+");
337 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
338 MKSTR(path2, "./%s", fname);
339 fd = fopen(path2, "a+");
341 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
344 DRV_LOG(INFO, "New debug dump in file %s", path2);
346 DRV_LOG(INFO, "New debug dump in file %s", path);
349 rte_hexdump(fd, hex_title, buf, hex_len);
351 fprintf(fd, "%s", (const char *)buf);
352 fprintf(fd, "\n\n\n");
357 * Modify a Verbs/DevX queue state.
358 * This must be called from the primary process.
361 * Pointer to Ethernet device.
363 * State modify request parameters.
366 * 0 in case of success else non-zero value and rte_errno is set.
369 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
370 const struct mlx5_mp_arg_queue_state_modify *sm)
373 struct mlx5_priv *priv = dev->data->dev_private;
376 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
377 struct mlx5_rxq_ctrl *rxq_ctrl =
378 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
380 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
382 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
383 sm->state, strerror(errno));
388 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
389 struct mlx5_txq_ctrl *txq_ctrl =
390 container_of(txq, struct mlx5_txq_ctrl, txq);
392 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
393 MLX5_TXQ_MOD_ERR2RDY,
394 (uint8_t)priv->dev_port);
402 * Modify a Verbs queue state.
405 * Pointer to Ethernet device.
407 * State modify request parameters.
410 * 0 in case of success else non-zero value.
413 mlx5_queue_state_modify(struct rte_eth_dev *dev,
414 struct mlx5_mp_arg_queue_state_modify *sm)
416 struct mlx5_priv *priv = dev->data->dev_private;
419 switch (rte_eal_process_type()) {
420 case RTE_PROC_PRIMARY:
421 ret = mlx5_queue_state_modify_primary(dev, sm);
423 case RTE_PROC_SECONDARY:
424 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);