1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
31 #include "mlx5_utils.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 /* TX burst subroutines return codes. */
38 enum mlx5_txcmp_code {
39 MLX5_TXCMP_CODE_EXIT = 0,
40 MLX5_TXCMP_CODE_ERROR,
41 MLX5_TXCMP_CODE_SINGLE,
42 MLX5_TXCMP_CODE_MULTI,
48 * These defines are used to configure Tx burst routine option set
49 * supported at compile time. The not specified options are optimized out
50 * out due to if conditions can be explicitly calculated at compile time.
51 * The offloads with bigger runtime check (require more CPU cycles to
52 * skip) overhead should have the bigger index - this is needed to
53 * select the better matching routine function if no exact match and
54 * some offloads are not actually requested.
56 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
57 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
58 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
59 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
60 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
61 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
62 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
63 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
65 /* The most common offloads groups. */
66 #define MLX5_TXOFF_CONFIG_NONE 0
67 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
68 MLX5_TXOFF_CONFIG_TSO | \
69 MLX5_TXOFF_CONFIG_SWP | \
70 MLX5_TXOFF_CONFIG_CSUM | \
71 MLX5_TXOFF_CONFIG_INLINE | \
72 MLX5_TXOFF_CONFIG_VLAN | \
73 MLX5_TXOFF_CONFIG_METADATA)
75 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
77 #define MLX5_TXOFF_DECL(func, olx) \
78 static uint16_t mlx5_tx_burst_##func(void *txq, \
79 struct rte_mbuf **pkts, \
82 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
83 pkts, pkts_n, (olx)); \
86 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
88 static __rte_always_inline uint32_t
89 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
91 static __rte_always_inline int
92 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
95 static __rte_always_inline uint32_t
96 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
98 static __rte_always_inline void
99 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
100 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
102 static __rte_always_inline void
103 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
104 const unsigned int strd_n);
107 mlx5_queue_state_modify(struct rte_eth_dev *dev,
108 struct mlx5_mp_arg_queue_state_modify *sm);
111 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
112 volatile struct mlx5_cqe *restrict cqe,
116 mlx5_lro_update_hdr(uint8_t *restrict padd,
117 volatile struct mlx5_cqe *restrict cqe,
120 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
121 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
124 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
125 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
128 * Build a table to translate Rx completion flags to packet type.
130 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
133 mlx5_set_ptype_table(void)
136 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
138 /* Last entry must not be overwritten, reserved for errored packet. */
139 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
140 (*p)[i] = RTE_PTYPE_UNKNOWN;
142 * The index to the array should have:
143 * bit[1:0] = l3_hdr_type
144 * bit[4:2] = l4_hdr_type
147 * bit[7] = outer_l3_type
150 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
152 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
153 RTE_PTYPE_L4_NONFRAG;
154 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_L4_NONFRAG;
157 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
159 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
172 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 /* Repeat with outer_l3_type being set. Just in case. */
180 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_L4_NONFRAG;
182 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_L4_NONFRAG;
184 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
202 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
206 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_NONFRAG;
209 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_NONFRAG;
212 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
213 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_NONFRAG;
216 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_NONFRAG;
219 /* Tunneled - Fragmented */
220 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L4_FRAG;
223 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_FRAG;
226 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_FRAG;
229 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_FRAG;
233 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L4_TCP;
236 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L4_TCP;
239 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L4_TCP;
242 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L4_TCP;
245 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
247 RTE_PTYPE_INNER_L4_TCP;
248 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
250 RTE_PTYPE_INNER_L4_TCP;
251 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L4_TCP;
254 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L4_TCP;
257 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
259 RTE_PTYPE_INNER_L4_TCP;
260 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_TCP;
263 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_TCP;
266 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_TCP;
270 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L4_UDP;
273 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
275 RTE_PTYPE_INNER_L4_UDP;
276 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
278 RTE_PTYPE_INNER_L4_UDP;
279 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L4_UDP;
285 * Build a table to translate packet to checksum type of Verbs.
288 mlx5_set_cksum_table(void)
294 * The index should have:
295 * bit[0] = PKT_TX_TCP_SEG
296 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
297 * bit[4] = PKT_TX_IP_CKSUM
298 * bit[8] = PKT_TX_OUTER_IP_CKSUM
301 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
304 /* Tunneled packet. */
305 if (i & (1 << 8)) /* Outer IP. */
306 v |= MLX5_ETH_WQE_L3_CSUM;
307 if (i & (1 << 4)) /* Inner IP. */
308 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
309 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
310 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
313 if (i & (1 << 4)) /* IP. */
314 v |= MLX5_ETH_WQE_L3_CSUM;
315 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
316 v |= MLX5_ETH_WQE_L4_CSUM;
318 mlx5_cksum_table[i] = v;
323 * Build a table to translate packet type of mbuf to SWP type of Verbs.
326 mlx5_set_swp_types_table(void)
332 * The index should have:
333 * bit[0:1] = PKT_TX_L4_MASK
334 * bit[4] = PKT_TX_IPV6
335 * bit[8] = PKT_TX_OUTER_IPV6
336 * bit[9] = PKT_TX_OUTER_UDP
338 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
341 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
343 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
345 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
346 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
347 v |= MLX5_ETH_WQE_L4_INNER_UDP;
348 mlx5_swp_types_table[i] = v;
353 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
354 * Flags must be preliminary initialized to zero.
357 * Pointer to burst routine local context.
359 * Pointer to store Software Parser flags
361 * Configured Tx offloads mask. It is fully defined at
362 * compile time and may be used for optimization.
365 * Software Parser offsets packed in dword.
366 * Software Parser flags are set by pointer.
368 static __rte_always_inline uint32_t
369 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
374 unsigned int idx, off;
377 if (!MLX5_TXOFF_CONFIG(SWP))
379 ol = loc->mbuf->ol_flags;
380 tunnel = ol & PKT_TX_TUNNEL_MASK;
382 * Check whether Software Parser is required.
383 * Only customized tunnels may ask for.
385 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
388 * The index should have:
389 * bit[0:1] = PKT_TX_L4_MASK
390 * bit[4] = PKT_TX_IPV6
391 * bit[8] = PKT_TX_OUTER_IPV6
392 * bit[9] = PKT_TX_OUTER_UDP
394 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
395 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
396 *swp_flags = mlx5_swp_types_table[idx];
398 * Set offsets for SW parser. Since ConnectX-5, SW parser just
399 * complements HW parser. SW parser starts to engage only if HW parser
400 * can't reach a header. For the older devices, HW parser will not kick
401 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
402 * should be set regardless of HW offload.
404 off = loc->mbuf->outer_l2_len;
405 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
406 off += sizeof(struct rte_vlan_hdr);
407 set = (off >> 1) << 8; /* Outer L3 offset. */
408 off += loc->mbuf->outer_l3_len;
409 if (tunnel == PKT_TX_TUNNEL_UDP)
410 set |= off >> 1; /* Outer L4 offset. */
411 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
412 const uint64_t csum = ol & PKT_TX_L4_MASK;
413 off += loc->mbuf->l2_len;
414 set |= (off >> 1) << 24; /* Inner L3 offset. */
415 if (csum == PKT_TX_TCP_CKSUM ||
416 csum == PKT_TX_UDP_CKSUM ||
417 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
418 off += loc->mbuf->l3_len;
419 set |= (off >> 1) << 16; /* Inner L4 offset. */
422 set = rte_cpu_to_le_32(set);
427 * Convert the Checksum offloads to Verbs.
430 * Pointer to the mbuf.
433 * Converted checksum flags.
435 static __rte_always_inline uint8_t
436 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
439 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
440 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
441 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
444 * The index should have:
445 * bit[0] = PKT_TX_TCP_SEG
446 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
447 * bit[4] = PKT_TX_IP_CKSUM
448 * bit[8] = PKT_TX_OUTER_IP_CKSUM
451 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
452 return mlx5_cksum_table[idx];
456 * Internal function to compute the number of used descriptors in an RX queue
462 * The number of used rx descriptor.
465 rx_queue_count(struct mlx5_rxq_data *rxq)
467 struct rxq_zip *zip = &rxq->zip;
468 volatile struct mlx5_cqe *cqe;
469 const unsigned int cqe_n = (1 << rxq->cqe_n);
470 const unsigned int cqe_cnt = cqe_n - 1;
474 /* if we are processing a compressed cqe */
476 used = zip->cqe_cnt - zip->ca;
482 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
483 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
487 op_own = cqe->op_own;
488 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
489 n = rte_be_to_cpu_32(cqe->byte_cnt);
494 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
496 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
501 * DPDK callback to check the status of a rx descriptor.
506 * The index of the descriptor in the ring.
509 * The status of the tx descriptor.
512 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
514 struct mlx5_rxq_data *rxq = rx_queue;
515 struct mlx5_rxq_ctrl *rxq_ctrl =
516 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
517 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
519 if (dev->rx_pkt_burst != mlx5_rx_burst) {
523 if (offset >= (1 << rxq->elts_n)) {
527 if (offset < rx_queue_count(rxq))
528 return RTE_ETH_RX_DESC_DONE;
529 return RTE_ETH_RX_DESC_AVAIL;
533 * DPDK callback to get the number of used descriptors in a RX queue
536 * Pointer to the device structure.
542 * The number of used rx descriptor.
543 * -EINVAL if the queue is invalid
546 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
548 struct mlx5_priv *priv = dev->data->dev_private;
549 struct mlx5_rxq_data *rxq;
551 if (dev->rx_pkt_burst != mlx5_rx_burst) {
555 rxq = (*priv->rxqs)[rx_queue_id];
560 return rx_queue_count(rxq);
563 #define MLX5_SYSTEM_LOG_DIR "/var/log"
565 * Dump debug information to log file.
570 * If not NULL this string is printed as a header to the output
571 * and the output will be in hexadecimal view.
573 * This is the buffer address to print out.
575 * The number of bytes to dump out.
578 mlx5_dump_debug_information(const char *fname, const char *hex_title,
579 const void *buf, unsigned int hex_len)
583 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
584 fd = fopen(path, "a+");
586 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
588 MKSTR(path2, "./%s", fname);
589 fd = fopen(path2, "a+");
591 DRV_LOG(ERR, "cannot open %s for debug dump\n",
595 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
597 DRV_LOG(INFO, "New debug dump in file %s\n", path);
600 rte_hexdump(fd, hex_title, buf, hex_len);
602 fprintf(fd, "%s", (const char *)buf);
603 fprintf(fd, "\n\n\n");
608 * Move QP from error state to running state and initialize indexes.
611 * Pointer to TX queue control structure.
614 * 0 on success, else -1.
617 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
619 struct mlx5_mp_arg_queue_state_modify sm = {
621 .queue_id = txq_ctrl->txq.idx,
624 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
626 txq_ctrl->txq.wqe_ci = 0;
627 txq_ctrl->txq.wqe_pi = 0;
628 txq_ctrl->txq.elts_comp = 0;
632 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
634 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
636 static const uint8_t magic[] = "seen";
640 for (i = 0; i < sizeof(magic); ++i)
641 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
643 err_cqe->rsvd1[i] = magic[i];
652 * Pointer to TX queue structure.
654 * Pointer to the error CQE.
657 * Negative value if queue recovery failed,
658 * the last Tx buffer element to free otherwise.
661 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
662 volatile struct mlx5_err_cqe *err_cqe)
664 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
665 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
666 struct mlx5_txq_ctrl *txq_ctrl =
667 container_of(txq, struct mlx5_txq_ctrl, txq);
668 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
669 int seen = check_err_cqe_seen(err_cqe);
671 if (!seen && txq_ctrl->dump_file_n <
672 txq_ctrl->priv->config.max_dump_files_num) {
673 MKSTR(err_str, "Unexpected CQE error syndrome "
674 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
675 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
676 txq->cqe_s, txq->qp_num_8s >> 8,
677 rte_be_to_cpu_16(err_cqe->wqe_counter),
678 txq->wqe_ci, txq->cq_ci);
679 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
680 PORT_ID(txq_ctrl->priv), txq->idx,
681 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
682 mlx5_dump_debug_information(name, NULL, err_str, 0);
683 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
684 (const void *)((uintptr_t)
688 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
689 (const void *)((uintptr_t)
693 txq_ctrl->dump_file_n++;
697 * Count errors in WQEs units.
698 * Later it can be improved to count error packets,
699 * for example, by SQ parsing to find how much packets
700 * should be counted for each WQE.
702 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
704 if (tx_recover_qp(txq_ctrl) == 0) {
706 /* Release all the remaining buffers. */
707 return txq->elts_head;
709 /* Recovering failed - try again later on the same WQE. */
714 /* Do not release buffers. */
715 return txq->elts_tail;
719 * Translate RX completion flags to packet type.
722 * Pointer to RX queue structure.
726 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
729 * Packet type for struct rte_mbuf.
731 static inline uint32_t
732 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
735 uint8_t pinfo = cqe->pkt_info;
736 uint16_t ptype = cqe->hdr_type_etc;
739 * The index to the array should have:
740 * bit[1:0] = l3_hdr_type
741 * bit[4:2] = l4_hdr_type
744 * bit[7] = outer_l3_type
746 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
747 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
751 * Initialize Rx WQ and indexes.
754 * Pointer to RX queue structure.
757 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
759 const unsigned int wqe_n = 1 << rxq->elts_n;
762 for (i = 0; (i != wqe_n); ++i) {
763 volatile struct mlx5_wqe_data_seg *scat;
767 if (mlx5_rxq_mprq_enabled(rxq)) {
768 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
770 scat = &((volatile struct mlx5_wqe_mprq *)
772 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
773 1 << rxq->strd_num_n);
774 byte_count = (1 << rxq->strd_sz_n) *
775 (1 << rxq->strd_num_n);
777 struct rte_mbuf *buf = (*rxq->elts)[i];
779 scat = &((volatile struct mlx5_wqe_data_seg *)
781 addr = rte_pktmbuf_mtod(buf, uintptr_t);
782 byte_count = DATA_LEN(buf);
784 /* scat->addr must be able to store a pointer. */
785 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
786 *scat = (struct mlx5_wqe_data_seg){
787 .addr = rte_cpu_to_be_64(addr),
788 .byte_count = rte_cpu_to_be_32(byte_count),
789 .lkey = mlx5_rx_addr2mr(rxq, addr),
792 rxq->consumed_strd = 0;
793 rxq->decompressed = 0;
795 rxq->zip = (struct rxq_zip){
798 /* Update doorbell counter. */
799 rxq->rq_ci = wqe_n >> rxq->sges_n;
801 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
805 * Modify a Verbs/DevX queue state.
806 * This must be called from the primary process.
809 * Pointer to Ethernet device.
811 * State modify request parameters.
814 * 0 in case of success else non-zero value and rte_errno is set.
817 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
818 const struct mlx5_mp_arg_queue_state_modify *sm)
821 struct mlx5_priv *priv = dev->data->dev_private;
824 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
825 struct mlx5_rxq_ctrl *rxq_ctrl =
826 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
828 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
829 struct ibv_wq_attr mod = {
830 .attr_mask = IBV_WQ_ATTR_STATE,
831 .wq_state = sm->state,
834 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
835 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
836 struct mlx5_devx_modify_rq_attr rq_attr;
838 memset(&rq_attr, 0, sizeof(rq_attr));
839 if (sm->state == IBV_WQS_RESET) {
840 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
841 rq_attr.state = MLX5_RQC_STATE_RST;
842 } else if (sm->state == IBV_WQS_RDY) {
843 rq_attr.rq_state = MLX5_RQC_STATE_RST;
844 rq_attr.state = MLX5_RQC_STATE_RDY;
845 } else if (sm->state == IBV_WQS_ERR) {
846 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
847 rq_attr.state = MLX5_RQC_STATE_ERR;
849 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
853 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s\n",
854 sm->state, strerror(errno));
859 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
860 struct mlx5_txq_ctrl *txq_ctrl =
861 container_of(txq, struct mlx5_txq_ctrl, txq);
862 struct ibv_qp_attr mod = {
863 .qp_state = IBV_QPS_RESET,
864 .port_num = (uint8_t)priv->ibv_port,
866 struct ibv_qp *qp = txq_ctrl->ibv->qp;
868 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
870 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
871 "%s\n", strerror(errno));
875 mod.qp_state = IBV_QPS_INIT;
876 ret = mlx5_glue->modify_qp(qp, &mod,
877 (IBV_QP_STATE | IBV_QP_PORT));
879 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s\n",
884 mod.qp_state = IBV_QPS_RTR;
885 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
887 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s\n",
892 mod.qp_state = IBV_QPS_RTS;
893 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
895 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s\n",
905 * Modify a Verbs queue state.
908 * Pointer to Ethernet device.
910 * State modify request parameters.
913 * 0 in case of success else non-zero value.
916 mlx5_queue_state_modify(struct rte_eth_dev *dev,
917 struct mlx5_mp_arg_queue_state_modify *sm)
921 switch (rte_eal_process_type()) {
922 case RTE_PROC_PRIMARY:
923 ret = mlx5_queue_state_modify_primary(dev, sm);
925 case RTE_PROC_SECONDARY:
926 ret = mlx5_mp_req_queue_state_modify(dev, sm);
936 * The function inserts the RQ state to reset when the first error CQE is
937 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
938 * it moves the RQ state to ready and initializes the RQ.
939 * Next CQE identification and error counting are in the caller responsibility.
942 * Pointer to RX queue structure.
943 * @param[in] mbuf_prepare
944 * Whether to prepare mbufs for the RQ.
947 * -1 in case of recovery error, otherwise the CQE status.
950 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
952 const uint16_t cqe_n = 1 << rxq->cqe_n;
953 const uint16_t cqe_mask = cqe_n - 1;
954 const unsigned int wqe_n = 1 << rxq->elts_n;
955 struct mlx5_rxq_ctrl *rxq_ctrl =
956 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
958 volatile struct mlx5_cqe *cqe;
959 volatile struct mlx5_err_cqe *err_cqe;
961 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
963 struct mlx5_mp_arg_queue_state_modify sm;
966 switch (rxq->err_state) {
967 case MLX5_RXQ_ERR_STATE_NO_ERROR:
968 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
970 case MLX5_RXQ_ERR_STATE_NEED_RESET:
972 sm.queue_id = rxq->idx;
973 sm.state = IBV_WQS_RESET;
974 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
976 if (rxq_ctrl->dump_file_n <
977 rxq_ctrl->priv->config.max_dump_files_num) {
978 MKSTR(err_str, "Unexpected CQE error syndrome "
979 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
980 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
981 rxq->cqn, rxq_ctrl->wqn,
982 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
983 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
984 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
985 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
986 mlx5_dump_debug_information(name, NULL, err_str, 0);
987 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
988 (const void *)((uintptr_t)
990 sizeof(*u.cqe) * cqe_n);
991 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
992 (const void *)((uintptr_t)
995 rxq_ctrl->dump_file_n++;
997 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
999 case MLX5_RXQ_ERR_STATE_NEED_READY:
1000 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1001 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1003 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1006 * The RQ consumer index must be zeroed while moving
1007 * from RESET state to RDY state.
1009 *rxq->rq_db = rte_cpu_to_be_32(0);
1012 sm.queue_id = rxq->idx;
1013 sm.state = IBV_WQS_RDY;
1014 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1018 const uint16_t q_mask = wqe_n - 1;
1020 struct rte_mbuf **elt;
1022 unsigned int n = wqe_n - (rxq->rq_ci -
1025 for (i = 0; i < (int)n; ++i) {
1026 elt_idx = (rxq->rq_ci + i) & q_mask;
1027 elt = &(*rxq->elts)[elt_idx];
1028 *elt = rte_mbuf_raw_alloc(rxq->mp);
1030 for (i--; i >= 0; --i) {
1031 elt_idx = (rxq->rq_ci +
1035 rte_pktmbuf_free_seg
1042 mlx5_rxq_initialize(rxq);
1043 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1052 * Get size of the next packet for a given CQE. For compressed CQEs, the
1053 * consumer index is updated only once all packets of the current one have
1057 * Pointer to RX queue.
1061 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1065 * 0 in case of empty CQE, otherwise the packet size in bytes.
1068 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1069 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1071 struct rxq_zip *zip = &rxq->zip;
1072 uint16_t cqe_n = cqe_cnt + 1;
1078 /* Process compressed data in the CQE and mini arrays. */
1080 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1081 (volatile struct mlx5_mini_cqe8 (*)[8])
1082 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1085 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1086 *mcqe = &(*mc)[zip->ai & 7];
1087 if ((++zip->ai & 7) == 0) {
1088 /* Invalidate consumed CQEs */
1091 while (idx != end) {
1092 (*rxq->cqes)[idx & cqe_cnt].op_own =
1093 MLX5_CQE_INVALIDATE;
1097 * Increment consumer index to skip the number
1098 * of CQEs consumed. Hardware leaves holes in
1099 * the CQ ring for software use.
1104 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1105 /* Invalidate the rest */
1109 while (idx != end) {
1110 (*rxq->cqes)[idx & cqe_cnt].op_own =
1111 MLX5_CQE_INVALIDATE;
1114 rxq->cq_ci = zip->cq_ci;
1118 * No compressed data, get next CQE and verify if it is
1125 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1126 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1127 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1129 ret = mlx5_rx_err_handle(rxq, 0);
1130 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1138 op_own = cqe->op_own;
1139 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1140 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1141 (volatile struct mlx5_mini_cqe8 (*)[8])
1142 (uintptr_t)(&(*rxq->cqes)
1146 /* Fix endianness. */
1147 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1149 * Current mini array position is the one
1150 * returned by check_cqe64().
1152 * If completion comprises several mini arrays,
1153 * as a special case the second one is located
1154 * 7 CQEs after the initial CQE instead of 8
1155 * for subsequent ones.
1157 zip->ca = rxq->cq_ci;
1158 zip->na = zip->ca + 7;
1159 /* Compute the next non compressed CQE. */
1161 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1162 /* Get packet size to return. */
1163 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1166 /* Prefetch all to be invalidated */
1169 while (idx != end) {
1170 rte_prefetch0(&(*rxq->cqes)[(idx) &
1175 len = rte_be_to_cpu_32(cqe->byte_cnt);
1178 if (unlikely(rxq->err_state)) {
1179 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1180 ++rxq->stats.idropped;
1188 * Translate RX completion flags to offload flags.
1194 * Offload flags (ol_flags) for struct rte_mbuf.
1196 static inline uint32_t
1197 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1199 uint32_t ol_flags = 0;
1200 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1204 MLX5_CQE_RX_L3_HDR_VALID,
1205 PKT_RX_IP_CKSUM_GOOD) |
1207 MLX5_CQE_RX_L4_HDR_VALID,
1208 PKT_RX_L4_CKSUM_GOOD);
1213 * Fill in mbuf fields from RX completion flags.
1214 * Note that pkt->ol_flags should be initialized outside of this function.
1217 * Pointer to RX queue.
1222 * @param rss_hash_res
1223 * Packet RSS Hash result.
1226 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1227 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1229 /* Update packet information. */
1230 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1231 if (rss_hash_res && rxq->rss_hash) {
1232 pkt->hash.rss = rss_hash_res;
1233 pkt->ol_flags |= PKT_RX_RSS_HASH;
1235 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1236 pkt->ol_flags |= PKT_RX_FDIR;
1237 if (cqe->sop_drop_qpn !=
1238 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1239 uint32_t mark = cqe->sop_drop_qpn;
1241 pkt->ol_flags |= PKT_RX_FDIR_ID;
1242 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1246 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1247 if (rxq->vlan_strip &&
1248 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1249 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1250 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1252 if (rxq->hw_timestamp) {
1253 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1254 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1259 * DPDK callback for RX.
1262 * Generic pointer to RX queue structure.
1264 * Array to store received packets.
1266 * Maximum number of packets in array.
1269 * Number of packets successfully received (<= pkts_n).
1272 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1274 struct mlx5_rxq_data *rxq = dpdk_rxq;
1275 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1276 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1277 const unsigned int sges_n = rxq->sges_n;
1278 struct rte_mbuf *pkt = NULL;
1279 struct rte_mbuf *seg = NULL;
1280 volatile struct mlx5_cqe *cqe =
1281 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1283 unsigned int rq_ci = rxq->rq_ci << sges_n;
1284 int len = 0; /* keep its value across iterations. */
1287 unsigned int idx = rq_ci & wqe_cnt;
1288 volatile struct mlx5_wqe_data_seg *wqe =
1289 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1290 struct rte_mbuf *rep = (*rxq->elts)[idx];
1291 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1292 uint32_t rss_hash_res;
1300 rep = rte_mbuf_raw_alloc(rxq->mp);
1301 if (unlikely(rep == NULL)) {
1302 ++rxq->stats.rx_nombuf;
1305 * no buffers before we even started,
1306 * bail out silently.
1310 while (pkt != seg) {
1311 assert(pkt != (*rxq->elts)[idx]);
1315 rte_mbuf_raw_free(pkt);
1321 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1322 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1324 rte_mbuf_raw_free(rep);
1328 assert(len >= (rxq->crc_present << 2));
1330 /* If compressed, take hash result from mini-CQE. */
1331 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1333 mcqe->rx_hash_result);
1334 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1335 if (rxq->crc_present)
1336 len -= RTE_ETHER_CRC_LEN;
1338 if (cqe->lro_num_seg > 1) {
1340 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1342 pkt->ol_flags |= PKT_RX_LRO;
1343 pkt->tso_segsz = len / cqe->lro_num_seg;
1346 DATA_LEN(rep) = DATA_LEN(seg);
1347 PKT_LEN(rep) = PKT_LEN(seg);
1348 SET_DATA_OFF(rep, DATA_OFF(seg));
1349 PORT(rep) = PORT(seg);
1350 (*rxq->elts)[idx] = rep;
1352 * Fill NIC descriptor with the new buffer. The lkey and size
1353 * of the buffers are already known, only the buffer address
1356 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1357 /* If there's only one MR, no need to replace LKey in WQE. */
1358 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1359 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1360 if (len > DATA_LEN(seg)) {
1361 len -= DATA_LEN(seg);
1366 DATA_LEN(seg) = len;
1367 #ifdef MLX5_PMD_SOFT_COUNTERS
1368 /* Increment bytes counter. */
1369 rxq->stats.ibytes += PKT_LEN(pkt);
1371 /* Return packet. */
1376 /* Align consumer index to the next stride. */
1381 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1383 /* Update the consumer index. */
1384 rxq->rq_ci = rq_ci >> sges_n;
1386 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1388 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1389 #ifdef MLX5_PMD_SOFT_COUNTERS
1390 /* Increment packets counter. */
1391 rxq->stats.ipackets += i;
1397 * Update LRO packet TCP header.
1398 * The HW LRO feature doesn't update the TCP header after coalescing the
1399 * TCP segments but supplies information in CQE to fill it by SW.
1402 * Pointer to the TCP header.
1404 * Pointer to the completion entry..
1406 * The L3 pseudo-header checksum.
1409 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1410 volatile struct mlx5_cqe *restrict cqe,
1413 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1414 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1416 * The HW calculates only the TCP payload checksum, need to complete
1417 * the TCP header checksum and the L3 pseudo-header checksum.
1419 uint32_t csum = phcsum + cqe->csum;
1421 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1422 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1423 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1424 tcp->recv_ack = cqe->lro_ack_seq_num;
1425 tcp->rx_win = cqe->lro_tcp_win;
1427 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1428 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1430 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1431 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1432 csum = (~csum) & 0xffff;
1439 * Update LRO packet headers.
1440 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1441 * TCP segments but supply information in CQE to fill it by SW.
1444 * The packet address.
1446 * Pointer to the completion entry..
1448 * The packet length.
1451 mlx5_lro_update_hdr(uint8_t *restrict padd,
1452 volatile struct mlx5_cqe *restrict cqe,
1456 struct rte_ether_hdr *eth;
1457 struct rte_vlan_hdr *vlan;
1458 struct rte_ipv4_hdr *ipv4;
1459 struct rte_ipv6_hdr *ipv6;
1460 struct rte_tcp_hdr *tcp;
1465 uint16_t proto = h.eth->ether_type;
1469 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1470 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1471 proto = h.vlan->eth_proto;
1474 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1475 h.ipv4->time_to_live = cqe->lro_min_ttl;
1476 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1477 h.ipv4->hdr_checksum = 0;
1478 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1479 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1482 h.ipv6->hop_limits = cqe->lro_min_ttl;
1483 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1485 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1488 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1492 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1494 struct mlx5_mprq_buf *buf = opaque;
1496 if (rte_atomic16_read(&buf->refcnt) == 1) {
1497 rte_mempool_put(buf->mp, buf);
1498 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1499 rte_atomic16_set(&buf->refcnt, 1);
1500 rte_mempool_put(buf->mp, buf);
1505 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1507 mlx5_mprq_buf_free_cb(NULL, buf);
1511 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1512 const unsigned int strd_n)
1514 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1515 volatile struct mlx5_wqe_data_seg *wqe =
1516 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1519 assert(rep != NULL);
1520 /* Replace MPRQ buf. */
1521 (*rxq->mprq_bufs)[rq_idx] = rep;
1523 addr = mlx5_mprq_buf_addr(rep, strd_n);
1524 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1525 /* If there's only one MR, no need to replace LKey in WQE. */
1526 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1527 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1528 /* Stash a mbuf for next replacement. */
1529 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1530 rxq->mprq_repl = rep;
1532 rxq->mprq_repl = NULL;
1536 * DPDK callback for RX with Multi-Packet RQ support.
1539 * Generic pointer to RX queue structure.
1541 * Array to store received packets.
1543 * Maximum number of packets in array.
1546 * Number of packets successfully received (<= pkts_n).
1549 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1551 struct mlx5_rxq_data *rxq = dpdk_rxq;
1552 const unsigned int strd_n = 1 << rxq->strd_num_n;
1553 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1554 const unsigned int strd_shift =
1555 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1556 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1557 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1558 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1560 uint32_t rq_ci = rxq->rq_ci;
1561 uint16_t consumed_strd = rxq->consumed_strd;
1562 uint16_t headroom_sz = rxq->strd_headroom_en * RTE_PKTMBUF_HEADROOM;
1563 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1565 while (i < pkts_n) {
1566 struct rte_mbuf *pkt;
1574 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1575 uint32_t rss_hash_res = 0;
1576 uint8_t lro_num_seg;
1578 if (consumed_strd == strd_n) {
1579 /* Replace WQE only if the buffer is still in use. */
1580 if (rte_atomic16_read(&buf->refcnt) > 1) {
1581 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1582 /* Release the old buffer. */
1583 mlx5_mprq_buf_free(buf);
1584 } else if (unlikely(rxq->mprq_repl == NULL)) {
1585 struct mlx5_mprq_buf *rep;
1588 * Currently, the MPRQ mempool is out of buffer
1589 * and doing memcpy regardless of the size of Rx
1590 * packet. Retry allocation to get back to
1593 if (!rte_mempool_get(rxq->mprq_mp,
1595 rxq->mprq_repl = rep;
1597 /* Advance to the next WQE. */
1600 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1602 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1603 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1607 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1608 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1610 consumed_strd += strd_cnt;
1611 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1614 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1615 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1617 /* mini-CQE for MPRQ doesn't have hash result. */
1618 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1620 assert(strd_idx < strd_n);
1621 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1622 lro_num_seg = cqe->lro_num_seg;
1624 * Currently configured to receive a packet per a stride. But if
1625 * MTU is adjusted through kernel interface, device could
1626 * consume multiple strides without raising an error. In this
1627 * case, the packet should be dropped because it is bigger than
1628 * the max_rx_pkt_len.
1630 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1631 ++rxq->stats.idropped;
1634 pkt = rte_pktmbuf_alloc(rxq->mp);
1635 if (unlikely(pkt == NULL)) {
1636 ++rxq->stats.rx_nombuf;
1639 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1640 assert((int)len >= (rxq->crc_present << 2));
1641 if (rxq->crc_present)
1642 len -= RTE_ETHER_CRC_LEN;
1643 offset = strd_idx * strd_sz + strd_shift;
1644 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1646 * Memcpy packets to the target mbuf if:
1647 * - The size of packet is smaller than mprq_max_memcpy_len.
1648 * - Out of buffer in the Mempool for Multi-Packet RQ.
1650 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1652 * When memcpy'ing packet due to out-of-buffer, the
1653 * packet must be smaller than the target mbuf.
1655 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1656 rte_pktmbuf_free_seg(pkt);
1657 ++rxq->stats.idropped;
1660 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1661 DATA_LEN(pkt) = len;
1663 rte_iova_t buf_iova;
1664 struct rte_mbuf_ext_shared_info *shinfo;
1665 uint16_t buf_len = strd_cnt * strd_sz;
1668 /* Increment the refcnt of the whole chunk. */
1669 rte_atomic16_add_return(&buf->refcnt, 1);
1670 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1672 buf_addr = RTE_PTR_SUB(addr, headroom_sz);
1674 * MLX5 device doesn't use iova but it is necessary in a
1675 * case where the Rx packet is transmitted via a
1678 buf_iova = rte_mempool_virt2iova(buf) +
1679 RTE_PTR_DIFF(buf_addr, buf);
1680 shinfo = &buf->shinfos[strd_idx];
1681 rte_mbuf_ext_refcnt_set(shinfo, 1);
1683 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1684 * attaching the stride to mbuf and more offload flags
1685 * will be added below by calling rxq_cq_to_mbuf().
1686 * Other fields will be overwritten.
1688 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1690 /* Set mbuf head-room. */
1691 pkt->data_off = headroom_sz;
1692 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1694 * Prevent potential overflow due to MTU change through
1697 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1698 rte_pktmbuf_free_seg(pkt);
1699 ++rxq->stats.idropped;
1702 DATA_LEN(pkt) = len;
1704 * LRO packet may consume all the stride memory, in this
1705 * case packet head-room space is not guaranteed so must
1706 * to add an empty mbuf for the head-room.
1708 if (!rxq->strd_headroom_en) {
1709 struct rte_mbuf *headroom_mbuf =
1710 rte_pktmbuf_alloc(rxq->mp);
1712 if (unlikely(headroom_mbuf == NULL)) {
1713 rte_pktmbuf_free_seg(pkt);
1714 ++rxq->stats.rx_nombuf;
1717 PORT(pkt) = rxq->port_id;
1718 NEXT(headroom_mbuf) = pkt;
1719 pkt = headroom_mbuf;
1723 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1724 if (lro_num_seg > 1) {
1725 mlx5_lro_update_hdr(addr, cqe, len);
1726 pkt->ol_flags |= PKT_RX_LRO;
1727 pkt->tso_segsz = strd_sz;
1730 PORT(pkt) = rxq->port_id;
1731 #ifdef MLX5_PMD_SOFT_COUNTERS
1732 /* Increment bytes counter. */
1733 rxq->stats.ibytes += PKT_LEN(pkt);
1735 /* Return packet. */
1739 /* Update the consumer indexes. */
1740 rxq->consumed_strd = consumed_strd;
1742 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1743 if (rq_ci != rxq->rq_ci) {
1746 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1748 #ifdef MLX5_PMD_SOFT_COUNTERS
1749 /* Increment packets counter. */
1750 rxq->stats.ipackets += i;
1756 * Dummy DPDK callback for TX.
1758 * This function is used to temporarily replace the real callback during
1759 * unsafe control operations on the queue, or in case of error.
1762 * Generic pointer to TX queue structure.
1764 * Packets to transmit.
1766 * Number of packets in array.
1769 * Number of packets successfully transmitted (<= pkts_n).
1772 removed_tx_burst(void *dpdk_txq __rte_unused,
1773 struct rte_mbuf **pkts __rte_unused,
1774 uint16_t pkts_n __rte_unused)
1781 * Dummy DPDK callback for RX.
1783 * This function is used to temporarily replace the real callback during
1784 * unsafe control operations on the queue, or in case of error.
1787 * Generic pointer to RX queue structure.
1789 * Array to store received packets.
1791 * Maximum number of packets in array.
1794 * Number of packets successfully received (<= pkts_n).
1797 removed_rx_burst(void *dpdk_txq __rte_unused,
1798 struct rte_mbuf **pkts __rte_unused,
1799 uint16_t pkts_n __rte_unused)
1806 * Vectorized Rx/Tx routines are not compiled in when required vector
1807 * instructions are not supported on a target architecture. The following null
1808 * stubs are needed for linkage when those are not included outside of this file
1809 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1813 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1814 struct rte_mbuf **pkts __rte_unused,
1815 uint16_t pkts_n __rte_unused)
1821 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1827 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1833 * Free the mbufs from the linear array of pointers.
1836 * Pointer to array of packets to be free.
1838 * Number of packets to be freed.
1840 * Configured Tx offloads mask. It is fully defined at
1841 * compile time and may be used for optimization.
1843 static __rte_always_inline void
1844 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1845 unsigned int pkts_n,
1846 unsigned int olx __rte_unused)
1848 struct rte_mempool *pool = NULL;
1849 struct rte_mbuf **p_free = NULL;
1850 struct rte_mbuf *mbuf;
1851 unsigned int n_free = 0;
1854 * The implemented algorithm eliminates
1855 * copying pointers to temporary array
1856 * for rte_mempool_put_bulk() calls.
1863 * Decrement mbuf reference counter, detach
1864 * indirect and external buffers if needed.
1866 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1867 if (likely(mbuf != NULL)) {
1868 assert(mbuf == *pkts);
1869 if (likely(n_free != 0)) {
1870 if (unlikely(pool != mbuf->pool))
1871 /* From different pool. */
1874 /* Start new scan array. */
1881 if (unlikely(pkts_n == 0)) {
1887 * This happens if mbuf is still referenced.
1888 * We can't put it back to the pool, skip.
1892 if (unlikely(n_free != 0))
1893 /* There is some array to free.*/
1895 if (unlikely(pkts_n == 0))
1896 /* Last mbuf, nothing to free. */
1902 * This loop is implemented to avoid multiple
1903 * inlining of rte_mempool_put_bulk().
1909 * Free the array of pre-freed mbufs
1910 * belonging to the same memory pool.
1912 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1913 if (unlikely(mbuf != NULL)) {
1914 /* There is the request to start new scan. */
1919 if (likely(pkts_n != 0))
1922 * This is the last mbuf to be freed.
1923 * Do one more loop iteration to complete.
1924 * This is rare case of the last unique mbuf.
1929 if (likely(pkts_n == 0))
1938 * Free the mbuf from the elts ring buffer till new tail.
1941 * Pointer to Tx queue structure.
1943 * Index in elts to free up to, becomes new elts tail.
1945 * Configured Tx offloads mask. It is fully defined at
1946 * compile time and may be used for optimization.
1948 static __rte_always_inline void
1949 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1951 unsigned int olx __rte_unused)
1953 uint16_t n_elts = tail - txq->elts_tail;
1956 assert(n_elts <= txq->elts_s);
1958 * Implement a loop to support ring buffer wraparound
1959 * with single inlining of mlx5_tx_free_mbuf().
1964 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1965 part = RTE_MIN(part, n_elts);
1967 assert(part <= txq->elts_s);
1968 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1970 txq->elts_tail += part;
1976 * Store the mbuf being sent into elts ring buffer.
1977 * On Tx completion these mbufs will be freed.
1980 * Pointer to Tx queue structure.
1982 * Pointer to array of packets to be stored.
1984 * Number of packets to be stored.
1986 * Configured Tx offloads mask. It is fully defined at
1987 * compile time and may be used for optimization.
1989 static __rte_always_inline void
1990 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
1991 struct rte_mbuf **restrict pkts,
1992 unsigned int pkts_n,
1993 unsigned int olx __rte_unused)
1996 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2000 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2002 assert(part <= txq->elts_s);
2003 /* This code is a good candidate for vectorizing with SIMD. */
2004 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2006 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2007 txq->elts_head += pkts_n;
2008 if (unlikely(part < pkts_n))
2009 /* The copy is wrapping around the elts array. */
2010 rte_memcpy((void *)elts, (void *)(pkts + part),
2011 (pkts_n - part) * sizeof(struct rte_mbuf *));
2015 * Update completion queue consuming index via doorbell
2016 * and flush the completed data buffers.
2019 * Pointer to TX queue structure.
2020 * @param valid CQE pointer
2021 * if not NULL update txq->wqe_pi and flush the buffers
2023 * if not negative - flush the buffers till this index.
2025 * Configured Tx offloads mask. It is fully defined at
2026 * compile time and may be used for optimization.
2028 static __rte_always_inline void
2029 mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,
2030 volatile struct mlx5_cqe *last_cqe,
2032 unsigned int olx __rte_unused)
2036 if (likely(last_cqe != NULL)) {
2037 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2038 tail = ((volatile struct mlx5_wqe_cseg *)
2039 (txq->wqes + (txq->wqe_pi & txq->wqe_m)))->misc;
2040 } else if (itail >= 0) {
2041 tail = (uint16_t)itail;
2045 rte_compiler_barrier();
2046 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2047 if (likely(tail != txq->elts_tail)) {
2048 mlx5_tx_free_elts(txq, tail, olx);
2049 assert(tail == txq->elts_tail);
2054 * Manage TX completions. This routine checks the CQ for
2055 * arrived CQEs, deduces the last accomplished WQE in SQ,
2056 * updates SQ producing index and frees all completed mbufs.
2059 * Pointer to TX queue structure.
2061 * Configured Tx offloads mask. It is fully defined at
2062 * compile time and may be used for optimization.
2064 * NOTE: not inlined intentionally, it makes tx_burst
2065 * routine smaller, simple and faster - from experiments.
2068 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
2069 unsigned int olx __rte_unused)
2071 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2072 volatile struct mlx5_cqe *last_cqe = NULL;
2075 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2076 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2078 volatile struct mlx5_cqe *cqe;
2080 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2081 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2082 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2083 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2084 /* No new CQEs in completion queue. */
2085 assert(ret == MLX5_CQE_STATUS_HW_OWN);
2089 * Some error occurred, try to restart.
2090 * We have no barrier after WQE related Doorbell
2091 * written, make sure all writes are completed
2092 * here, before we might perform SQ reset.
2095 ret = mlx5_tx_error_cqe_handle
2096 (txq, (volatile struct mlx5_err_cqe *)cqe);
2098 * Flush buffers, update consuming index
2099 * if recovery succeeded. Otherwise
2100 * just try to recover later.
2105 /* Normal transmit completion. */
2113 * We have to restrict the amount of processed CQEs
2114 * in one tx_burst routine call. The CQ may be large
2115 * and many CQEs may be updated by the NIC in one
2116 * transaction. Buffers freeing is time consuming,
2117 * multiple iterations may introduce significant
2121 mlx5_tx_comp_flush(txq, last_cqe, ret, olx);
2125 * Check if the completion request flag should be set in the last WQE.
2126 * Both pushed mbufs and WQEs are monitored and the completion request
2127 * flag is set if any of thresholds is reached.
2130 * Pointer to TX queue structure.
2132 * Pointer to burst routine local context.
2134 * Configured Tx offloads mask. It is fully defined at
2135 * compile time and may be used for optimization.
2137 static __rte_always_inline void
2138 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2139 struct mlx5_txq_local *restrict loc,
2142 uint16_t head = txq->elts_head;
2145 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc->pkts_sent -
2146 (MLX5_TXOFF_CONFIG(MULTI) ? loc->pkts_copy : 0);
2148 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2149 (MLX5_TXOFF_CONFIG(INLINE) &&
2150 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2151 volatile struct mlx5_wqe *last = loc->wqe_last;
2153 txq->elts_comp = head;
2154 if (MLX5_TXOFF_CONFIG(INLINE))
2155 txq->wqe_comp = txq->wqe_ci;
2156 /* Request unconditional completion on last WQE. */
2157 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2158 MLX5_COMP_MODE_OFFSET);
2159 /* Save elts_head in unused "immediate" field of WQE. */
2160 last->cseg.misc = head;
2162 * A CQE slot must always be available. Count the
2163 * issued CEQ "always" request instead of production
2164 * index due to here can be CQE with errors and
2165 * difference with ci may become inconsistent.
2167 assert(txq->cqe_s > ++txq->cq_pi);
2172 * DPDK callback to check the status of a tx descriptor.
2177 * The index of the descriptor in the ring.
2180 * The status of the tx descriptor.
2183 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2185 struct mlx5_txq_data *restrict txq = tx_queue;
2188 mlx5_tx_handle_completion(txq, 0);
2189 used = txq->elts_head - txq->elts_tail;
2191 return RTE_ETH_TX_DESC_FULL;
2192 return RTE_ETH_TX_DESC_DONE;
2196 * Build the Control Segment with specified opcode:
2197 * - MLX5_OPCODE_SEND
2198 * - MLX5_OPCODE_ENHANCED_MPSW
2202 * Pointer to TX queue structure.
2204 * Pointer to burst routine local context.
2206 * Pointer to WQE to fill with built Control Segment.
2208 * Supposed length of WQE in segments.
2210 * SQ WQE opcode to put into Control Segment.
2212 * Configured Tx offloads mask. It is fully defined at
2213 * compile time and may be used for optimization.
2215 static __rte_always_inline void
2216 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2217 struct mlx5_txq_local *restrict loc __rte_unused,
2218 struct mlx5_wqe *restrict wqe,
2220 unsigned int opcode,
2221 unsigned int olx __rte_unused)
2223 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2225 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2226 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2227 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2228 MLX5_COMP_MODE_OFFSET);
2229 cs->misc = RTE_BE32(0);
2233 * Build the Ethernet Segment without inlined data.
2234 * Supports Software Parser, Checksums and VLAN
2235 * insertion Tx offload features.
2238 * Pointer to TX queue structure.
2240 * Pointer to burst routine local context.
2242 * Pointer to WQE to fill with built Ethernet Segment.
2244 * Configured Tx offloads mask. It is fully defined at
2245 * compile time and may be used for optimization.
2247 static __rte_always_inline void
2248 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2249 struct mlx5_txq_local *restrict loc,
2250 struct mlx5_wqe *restrict wqe,
2253 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2257 * Calculate and set check sum flags first, dword field
2258 * in segment may be shared with Software Parser flags.
2260 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2261 es->flags = rte_cpu_to_le_32(csum);
2263 * Calculate and set Software Parser offsets and flags.
2264 * These flags a set for custom UDP and IP tunnel packets.
2266 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2267 /* Fill metadata field if needed. */
2268 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2269 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2270 loc->mbuf->tx_metadata : 0 : 0;
2271 /* Engage VLAN tag insertion feature if requested. */
2272 if (MLX5_TXOFF_CONFIG(VLAN) &&
2273 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2275 * We should get here only if device support
2276 * this feature correctly.
2278 assert(txq->vlan_en);
2279 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2280 loc->mbuf->vlan_tci);
2282 es->inline_hdr = RTE_BE32(0);
2287 * Build the Ethernet Segment with minimal inlined data
2288 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2289 * used to fill the gap in single WQEBB WQEs.
2290 * Supports Software Parser, Checksums and VLAN
2291 * insertion Tx offload features.
2294 * Pointer to TX queue structure.
2296 * Pointer to burst routine local context.
2298 * Pointer to WQE to fill with built Ethernet Segment.
2300 * Length of VLAN tag insertion if any.
2302 * Configured Tx offloads mask. It is fully defined at
2303 * compile time and may be used for optimization.
2305 static __rte_always_inline void
2306 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2307 struct mlx5_txq_local *restrict loc,
2308 struct mlx5_wqe *restrict wqe,
2312 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2314 uint8_t *psrc, *pdst;
2317 * Calculate and set check sum flags first, dword field
2318 * in segment may be shared with Software Parser flags.
2320 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2321 es->flags = rte_cpu_to_le_32(csum);
2323 * Calculate and set Software Parser offsets and flags.
2324 * These flags a set for custom UDP and IP tunnel packets.
2326 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2327 /* Fill metadata field if needed. */
2328 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2329 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2330 loc->mbuf->tx_metadata : 0 : 0;
2331 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2333 sizeof(rte_v128u32_t)),
2334 "invalid Ethernet Segment data size");
2335 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2337 sizeof(struct rte_vlan_hdr) +
2338 2 * RTE_ETHER_ADDR_LEN),
2339 "invalid Ethernet Segment data size");
2340 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2341 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2342 es->inline_data = *(unaligned_uint16_t *)psrc;
2343 psrc += sizeof(uint16_t);
2344 pdst = (uint8_t *)(es + 1);
2345 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2346 /* Implement VLAN tag insertion as part inline data. */
2347 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2348 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2349 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2350 /* Insert VLAN ethertype + VLAN tag. */
2351 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2352 ((RTE_ETHER_TYPE_VLAN << 16) |
2353 loc->mbuf->vlan_tci);
2354 pdst += sizeof(struct rte_vlan_hdr);
2355 /* Copy the rest two bytes from packet data. */
2356 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2357 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2359 /* Fill the gap in the title WQEBB with inline data. */
2360 rte_mov16(pdst, psrc);
2365 * Build the Ethernet Segment with entire packet
2366 * data inlining. Checks the boundary of WQEBB and
2367 * ring buffer wrapping, supports Software Parser,
2368 * Checksums and VLAN insertion Tx offload features.
2371 * Pointer to TX queue structure.
2373 * Pointer to burst routine local context.
2375 * Pointer to WQE to fill with built Ethernet Segment.
2377 * Length of VLAN tag insertion if any.
2379 * Length of data to inline (VLAN included, if any).
2381 * TSO flag, set mss field from the packet.
2383 * Configured Tx offloads mask. It is fully defined at
2384 * compile time and may be used for optimization.
2387 * Pointer to the next Data Segment (aligned and wrapped around).
2389 static __rte_always_inline struct mlx5_wqe_dseg *
2390 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2391 struct mlx5_txq_local *restrict loc,
2392 struct mlx5_wqe *restrict wqe,
2398 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2400 uint8_t *psrc, *pdst;
2404 * Calculate and set check sum flags first, dword field
2405 * in segment may be shared with Software Parser flags.
2407 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2410 csum |= loc->mbuf->tso_segsz;
2411 es->flags = rte_cpu_to_be_32(csum);
2413 es->flags = rte_cpu_to_le_32(csum);
2416 * Calculate and set Software Parser offsets and flags.
2417 * These flags a set for custom UDP and IP tunnel packets.
2419 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2420 /* Fill metadata field if needed. */
2421 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2422 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2423 loc->mbuf->tx_metadata : 0 : 0;
2424 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2426 sizeof(rte_v128u32_t)),
2427 "invalid Ethernet Segment data size");
2428 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2430 sizeof(struct rte_vlan_hdr) +
2431 2 * RTE_ETHER_ADDR_LEN),
2432 "invalid Ethernet Segment data size");
2433 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2434 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2435 es->inline_data = *(unaligned_uint16_t *)psrc;
2436 psrc += sizeof(uint16_t);
2437 pdst = (uint8_t *)(es + 1);
2438 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2439 /* Implement VLAN tag insertion as part inline data. */
2440 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2441 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2442 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2443 /* Insert VLAN ethertype + VLAN tag. */
2444 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2445 ((RTE_ETHER_TYPE_VLAN << 16) |
2446 loc->mbuf->vlan_tci);
2447 pdst += sizeof(struct rte_vlan_hdr);
2448 /* Copy the rest two bytes from packet data. */
2449 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2450 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2451 psrc += sizeof(uint16_t);
2453 /* Fill the gap in the title WQEBB with inline data. */
2454 rte_mov16(pdst, psrc);
2455 psrc += sizeof(rte_v128u32_t);
2457 pdst = (uint8_t *)(es + 2);
2458 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2459 assert(pdst < (uint8_t *)txq->wqes_end);
2460 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2462 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2463 return (struct mlx5_wqe_dseg *)pdst;
2466 * The WQEBB space availability is checked by caller.
2467 * Here we should be aware of WQE ring buffer wraparound only.
2469 part = (uint8_t *)txq->wqes_end - pdst;
2470 part = RTE_MIN(part, inlen);
2472 rte_memcpy(pdst, psrc, part);
2474 if (likely(!inlen)) {
2476 * If return value is not used by the caller
2477 * the code below will be optimized out.
2480 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2481 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2482 pdst = (uint8_t *)txq->wqes;
2483 return (struct mlx5_wqe_dseg *)pdst;
2485 pdst = (uint8_t *)txq->wqes;
2492 * Copy data from chain of mbuf to the specified linear buffer.
2493 * Checksums and VLAN insertion Tx offload features. If data
2494 * from some mbuf copied completely this mbuf is freed. Local
2495 * structure is used to keep the byte stream state.
2498 * Pointer to the destination linear buffer.
2500 * Pointer to burst routine local context.
2502 * Length of data to be copied.
2504 * Configured Tx offloads mask. It is fully defined at
2505 * compile time and may be used for optimization.
2507 static __rte_always_inline void
2508 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2509 struct mlx5_txq_local *restrict loc,
2511 unsigned int olx __rte_unused)
2513 struct rte_mbuf *mbuf;
2514 unsigned int part, dlen;
2519 /* Allow zero length packets, must check first. */
2520 dlen = rte_pktmbuf_data_len(loc->mbuf);
2521 if (dlen <= loc->mbuf_off) {
2522 /* Exhausted packet, just free. */
2524 loc->mbuf = mbuf->next;
2525 rte_pktmbuf_free_seg(mbuf);
2527 assert(loc->mbuf_nseg > 1);
2532 dlen -= loc->mbuf_off;
2533 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2535 part = RTE_MIN(len, dlen);
2536 rte_memcpy(pdst, psrc, part);
2537 loc->mbuf_off += part;
2540 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2542 /* Exhausted packet, just free. */
2544 loc->mbuf = mbuf->next;
2545 rte_pktmbuf_free_seg(mbuf);
2547 assert(loc->mbuf_nseg >= 1);
2557 * Build the Ethernet Segment with inlined data from
2558 * multi-segment packet. Checks the boundary of WQEBB
2559 * and ring buffer wrapping, supports Software Parser,
2560 * Checksums and VLAN insertion Tx offload features.
2563 * Pointer to TX queue structure.
2565 * Pointer to burst routine local context.
2567 * Pointer to WQE to fill with built Ethernet Segment.
2569 * Length of VLAN tag insertion if any.
2571 * Length of data to inline (VLAN included, if any).
2573 * TSO flag, set mss field from the packet.
2575 * Configured Tx offloads mask. It is fully defined at
2576 * compile time and may be used for optimization.
2579 * Pointer to the next Data Segment (aligned and
2580 * possible NOT wrapped around - caller should do
2581 * wrapping check on its own).
2583 static __rte_always_inline struct mlx5_wqe_dseg *
2584 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2585 struct mlx5_txq_local *restrict loc,
2586 struct mlx5_wqe *restrict wqe,
2592 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2598 * Calculate and set check sum flags first, uint32_t field
2599 * in segment may be shared with Software Parser flags.
2601 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2604 csum |= loc->mbuf->tso_segsz;
2605 es->flags = rte_cpu_to_be_32(csum);
2607 es->flags = rte_cpu_to_le_32(csum);
2610 * Calculate and set Software Parser offsets and flags.
2611 * These flags a set for custom UDP and IP tunnel packets.
2613 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2614 /* Fill metadata field if needed. */
2615 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2616 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2617 loc->mbuf->tx_metadata : 0 : 0;
2618 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2620 sizeof(rte_v128u32_t)),
2621 "invalid Ethernet Segment data size");
2622 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2624 sizeof(struct rte_vlan_hdr) +
2625 2 * RTE_ETHER_ADDR_LEN),
2626 "invalid Ethernet Segment data size");
2627 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2628 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2629 pdst = (uint8_t *)&es->inline_data;
2630 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2631 /* Implement VLAN tag insertion as part inline data. */
2632 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2633 pdst += 2 * RTE_ETHER_ADDR_LEN;
2634 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2635 ((RTE_ETHER_TYPE_VLAN << 16) |
2636 loc->mbuf->vlan_tci);
2637 pdst += sizeof(struct rte_vlan_hdr);
2638 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2640 assert(pdst < (uint8_t *)txq->wqes_end);
2642 * The WQEBB space availability is checked by caller.
2643 * Here we should be aware of WQE ring buffer wraparound only.
2645 part = (uint8_t *)txq->wqes_end - pdst;
2646 part = RTE_MIN(part, inlen);
2649 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2651 if (likely(!inlen)) {
2653 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2654 return (struct mlx5_wqe_dseg *)pdst;
2656 pdst = (uint8_t *)txq->wqes;
2662 * Build the Data Segment of pointer type.
2665 * Pointer to TX queue structure.
2667 * Pointer to burst routine local context.
2669 * Pointer to WQE to fill with built Data Segment.
2671 * Data buffer to point.
2673 * Data buffer length.
2675 * Configured Tx offloads mask. It is fully defined at
2676 * compile time and may be used for optimization.
2678 static __rte_always_inline void
2679 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2680 struct mlx5_txq_local *restrict loc,
2681 struct mlx5_wqe_dseg *restrict dseg,
2684 unsigned int olx __rte_unused)
2688 dseg->bcount = rte_cpu_to_be_32(len);
2689 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2690 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2694 * Build the Data Segment of pointer type or inline
2695 * if data length is less than buffer in minimal
2696 * Data Segment size.
2699 * Pointer to TX queue structure.
2701 * Pointer to burst routine local context.
2703 * Pointer to WQE to fill with built Data Segment.
2705 * Data buffer to point.
2707 * Data buffer length.
2709 * Configured Tx offloads mask. It is fully defined at
2710 * compile time and may be used for optimization.
2712 static __rte_always_inline void
2713 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2714 struct mlx5_txq_local *restrict loc,
2715 struct mlx5_wqe_dseg *restrict dseg,
2718 unsigned int olx __rte_unused)
2724 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2725 dseg->bcount = rte_cpu_to_be_32(len);
2726 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2727 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2731 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2732 /* Unrolled implementation of generic rte_memcpy. */
2733 dst = (uintptr_t)&dseg->inline_data[0];
2734 src = (uintptr_t)buf;
2735 #ifdef RTE_ARCH_STRICT_ALIGN
2736 memcpy(dst, src, len);
2739 *(uint64_t *)dst = *(uint64_t *)src;
2740 dst += sizeof(uint64_t);
2741 src += sizeof(uint64_t);
2744 *(uint32_t *)dst = *(uint32_t *)src;
2745 dst += sizeof(uint32_t);
2746 src += sizeof(uint32_t);
2749 *(uint16_t *)dst = *(uint16_t *)src;
2750 dst += sizeof(uint16_t);
2751 src += sizeof(uint16_t);
2754 *(uint8_t *)dst = *(uint8_t *)src;
2759 * Build the Data Segment of inlined data from single
2760 * segment packet, no VLAN insertion.
2763 * Pointer to TX queue structure.
2765 * Pointer to burst routine local context.
2767 * Pointer to WQE to fill with built Data Segment.
2769 * Data buffer to point.
2771 * Data buffer length.
2773 * Configured Tx offloads mask. It is fully defined at
2774 * compile time and may be used for optimization.
2777 * Pointer to the next Data Segment after inlined data.
2778 * Ring buffer wraparound check is needed. We do not
2779 * do it here because it may not be needed for the
2780 * last packet in the eMPW session.
2782 static __rte_always_inline struct mlx5_wqe_dseg *
2783 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2784 struct mlx5_txq_local *restrict loc __rte_unused,
2785 struct mlx5_wqe_dseg *restrict dseg,
2788 unsigned int olx __rte_unused)
2793 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2794 pdst = &dseg->inline_data[0];
2796 * The WQEBB space availability is checked by caller.
2797 * Here we should be aware of WQE ring buffer wraparound only.
2799 part = (uint8_t *)txq->wqes_end - pdst;
2800 part = RTE_MIN(part, len);
2802 rte_memcpy(pdst, buf, part);
2806 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2807 /* Note: no final wraparound check here. */
2808 return (struct mlx5_wqe_dseg *)pdst;
2810 pdst = (uint8_t *)txq->wqes;
2817 * Build the Data Segment of inlined data from single
2818 * segment packet with VLAN insertion.
2821 * Pointer to TX queue structure.
2823 * Pointer to burst routine local context.
2825 * Pointer to the dseg fill with built Data Segment.
2827 * Data buffer to point.
2829 * Data buffer length.
2831 * Configured Tx offloads mask. It is fully defined at
2832 * compile time and may be used for optimization.
2835 * Pointer to the next Data Segment after inlined data.
2836 * Ring buffer wraparound check is needed.
2838 static __rte_always_inline struct mlx5_wqe_dseg *
2839 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2840 struct mlx5_txq_local *restrict loc __rte_unused,
2841 struct mlx5_wqe_dseg *restrict dseg,
2844 unsigned int olx __rte_unused)
2850 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2851 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2852 (2 * RTE_ETHER_ADDR_LEN),
2853 "invalid Data Segment data size");
2854 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2855 MLX5_ETH_WQE_DATA_INLINE);
2856 pdst = &dseg->inline_data[0];
2857 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2858 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2859 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2860 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2861 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2862 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2863 loc->mbuf->vlan_tci);
2864 pdst += sizeof(struct rte_vlan_hdr);
2865 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2866 pdst = (uint8_t *)txq->wqes;
2868 * The WQEBB space availability is checked by caller.
2869 * Here we should be aware of WQE ring buffer wraparound only.
2871 part = (uint8_t *)txq->wqes_end - pdst;
2872 part = RTE_MIN(part, len);
2874 rte_memcpy(pdst, buf, part);
2878 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2879 /* Note: no final wraparound check here. */
2880 return (struct mlx5_wqe_dseg *)pdst;
2882 pdst = (uint8_t *)txq->wqes;
2889 * Build the Ethernet Segment with optionally inlined data with
2890 * VLAN insertion and following Data Segments (if any) from
2891 * multi-segment packet. Used by ordinary send and TSO.
2894 * Pointer to TX queue structure.
2896 * Pointer to burst routine local context.
2898 * Pointer to WQE to fill with built Ethernet/Data Segments.
2900 * Length of VLAN header to insert, 0 means no VLAN insertion.
2902 * Data length to inline. For TSO this parameter specifies
2903 * exact value, for ordinary send routine can be aligned by
2904 * caller to provide better WQE space saving and data buffer
2905 * start address alignment. This length includes VLAN header
2908 * Zero means ordinary send, inlined data can be extended,
2909 * otherwise this is TSO, inlined data length is fixed.
2911 * Configured Tx offloads mask. It is fully defined at
2912 * compile time and may be used for optimization.
2915 * Actual size of built WQE in segments.
2917 static __rte_always_inline unsigned int
2918 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2919 struct mlx5_txq_local *restrict loc,
2920 struct mlx5_wqe *restrict wqe,
2924 unsigned int olx __rte_unused)
2926 struct mlx5_wqe_dseg *restrict dseg;
2929 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2930 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2933 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2934 if (!loc->mbuf_nseg)
2937 * There are still some mbuf remaining, not inlined.
2938 * The first mbuf may be partially inlined and we
2939 * must process the possible non-zero data offset.
2941 if (loc->mbuf_off) {
2946 * Exhausted packets must be dropped before.
2947 * Non-zero offset means there are some data
2948 * remained in the packet.
2950 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2951 assert(rte_pktmbuf_data_len(loc->mbuf));
2952 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2954 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2956 * Build the pointer/minimal data Data Segment.
2957 * Do ring buffer wrapping check in advance.
2959 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2960 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2961 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2962 /* Store the mbuf to be freed on completion. */
2963 assert(loc->elts_free);
2964 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2967 if (--loc->mbuf_nseg == 0)
2969 loc->mbuf = loc->mbuf->next;
2973 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
2974 struct rte_mbuf *mbuf;
2976 /* Zero length segment found, just skip. */
2978 loc->mbuf = loc->mbuf->next;
2979 rte_pktmbuf_free_seg(mbuf);
2980 if (--loc->mbuf_nseg == 0)
2983 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2984 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2987 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
2988 rte_pktmbuf_data_len(loc->mbuf), olx);
2989 assert(loc->elts_free);
2990 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2993 if (--loc->mbuf_nseg == 0)
2995 loc->mbuf = loc->mbuf->next;
3000 /* Calculate actual segments used from the dseg pointer. */
3001 if ((uintptr_t)wqe < (uintptr_t)dseg)
3002 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3004 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3005 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3010 * Tx one packet function for multi-segment TSO. Supports all
3011 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3012 * sends one packet per WQE.
3014 * This routine is responsible for storing processed mbuf
3015 * into elts ring buffer and update elts_head.
3018 * Pointer to TX queue structure.
3020 * Pointer to burst routine local context.
3022 * Configured Tx offloads mask. It is fully defined at
3023 * compile time and may be used for optimization.
3026 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3027 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3028 * Local context variables partially updated.
3030 static __rte_always_inline enum mlx5_txcmp_code
3031 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
3032 struct mlx5_txq_local *restrict loc,
3035 struct mlx5_wqe *restrict wqe;
3036 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3039 * Calculate data length to be inlined to estimate
3040 * the required space in WQE ring buffer.
3042 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3043 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3044 vlan = sizeof(struct rte_vlan_hdr);
3045 inlen = loc->mbuf->l2_len + vlan +
3046 loc->mbuf->l3_len + loc->mbuf->l4_len;
3047 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3048 return MLX5_TXCMP_CODE_ERROR;
3049 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3050 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3051 /* Packet must contain all TSO headers. */
3052 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3053 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3054 inlen > (dlen + vlan)))
3055 return MLX5_TXCMP_CODE_ERROR;
3056 assert(inlen >= txq->inlen_mode);
3058 * Check whether there are enough free WQEBBs:
3060 * - Ethernet Segment
3061 * - First Segment of inlined Ethernet data
3062 * - ... data continued ...
3063 * - Data Segments of pointer/min inline type
3065 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3066 MLX5_ESEG_MIN_INLINE_SIZE +
3068 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3069 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3070 return MLX5_TXCMP_CODE_EXIT;
3071 /* Check for maximal WQE size. */
3072 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3073 return MLX5_TXCMP_CODE_ERROR;
3074 #ifdef MLX5_PMD_SOFT_COUNTERS
3075 /* Update sent data bytes/packets counters. */
3076 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3077 loc->mbuf->tso_segsz;
3079 * One will be added for mbuf itself
3080 * at the end of the mlx5_tx_burst from
3081 * loc->pkts_sent field.
3084 txq->stats.opackets += ntcp;
3085 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3087 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3088 loc->wqe_last = wqe;
3089 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3090 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3091 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3092 txq->wqe_ci += (ds + 3) / 4;
3093 loc->wqe_free -= (ds + 3) / 4;
3094 /* Request CQE generation if limits are reached. */
3095 mlx5_tx_request_completion(txq, loc, olx);
3096 return MLX5_TXCMP_CODE_MULTI;
3100 * Tx one packet function for multi-segment SEND. Supports all
3101 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3102 * sends one packet per WQE, without any data inlining in
3105 * This routine is responsible for storing processed mbuf
3106 * into elts ring buffer and update elts_head.
3109 * Pointer to TX queue structure.
3111 * Pointer to burst routine local context.
3113 * Configured Tx offloads mask. It is fully defined at
3114 * compile time and may be used for optimization.
3117 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3118 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3119 * Local context variables partially updated.
3121 static __rte_always_inline enum mlx5_txcmp_code
3122 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3123 struct mlx5_txq_local *restrict loc,
3126 struct mlx5_wqe_dseg *restrict dseg;
3127 struct mlx5_wqe *restrict wqe;
3128 unsigned int ds, nseg;
3130 assert(NB_SEGS(loc->mbuf) > 1);
3132 * No inline at all, it means the CPU cycles saving
3133 * is prioritized at configuration, we should not
3134 * copy any packet data to WQE.
3136 nseg = NB_SEGS(loc->mbuf);
3138 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3139 return MLX5_TXCMP_CODE_EXIT;
3140 /* Check for maximal WQE size. */
3141 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3142 return MLX5_TXCMP_CODE_ERROR;
3144 * Some Tx offloads may cause an error if
3145 * packet is not long enough, check against
3146 * assumed minimal length.
3148 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3149 return MLX5_TXCMP_CODE_ERROR;
3150 #ifdef MLX5_PMD_SOFT_COUNTERS
3151 /* Update sent data bytes counter. */
3152 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3153 if (MLX5_TXOFF_CONFIG(VLAN) &&
3154 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3155 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3158 * SEND WQE, one WQEBB:
3159 * - Control Segment, SEND opcode
3160 * - Ethernet Segment, optional VLAN, no inline
3161 * - Data Segments, pointer only type
3163 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3164 loc->wqe_last = wqe;
3165 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3166 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3167 dseg = &wqe->dseg[0];
3169 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3170 struct rte_mbuf *mbuf;
3173 * Zero length segment found, have to
3174 * correct total size of WQE in segments.
3175 * It is supposed to be rare occasion, so
3176 * in normal case (no zero length segments)
3177 * we avoid extra writing to the Control
3181 wqe->cseg.sq_ds -= RTE_BE32(1);
3183 loc->mbuf = mbuf->next;
3184 rte_pktmbuf_free_seg(mbuf);
3190 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3191 rte_pktmbuf_data_len(loc->mbuf), olx);
3192 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3197 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3198 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3199 loc->mbuf = loc->mbuf->next;
3202 txq->wqe_ci += (ds + 3) / 4;
3203 loc->wqe_free -= (ds + 3) / 4;
3204 /* Request CQE generation if limits are reached. */
3205 mlx5_tx_request_completion(txq, loc, olx);
3206 return MLX5_TXCMP_CODE_MULTI;
3210 * Tx one packet function for multi-segment SEND. Supports all
3211 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3212 * sends one packet per WQE, with data inlining in
3213 * Ethernet Segment and minimal Data Segments.
3215 * This routine is responsible for storing processed mbuf
3216 * into elts ring buffer and update elts_head.
3219 * Pointer to TX queue structure.
3221 * Pointer to burst routine local context.
3223 * Configured Tx offloads mask. It is fully defined at
3224 * compile time and may be used for optimization.
3227 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3228 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3229 * Local context variables partially updated.
3231 static __rte_always_inline enum mlx5_txcmp_code
3232 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3233 struct mlx5_txq_local *restrict loc,
3236 struct mlx5_wqe *restrict wqe;
3237 unsigned int ds, inlen, dlen, vlan = 0;
3239 assert(MLX5_TXOFF_CONFIG(INLINE));
3240 assert(NB_SEGS(loc->mbuf) > 1);
3242 * First calculate data length to be inlined
3243 * to estimate the required space for WQE.
3245 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3246 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3247 vlan = sizeof(struct rte_vlan_hdr);
3248 inlen = dlen + vlan;
3249 /* Check against minimal length. */
3250 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3251 return MLX5_TXCMP_CODE_ERROR;
3252 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3253 if (inlen > txq->inlen_send) {
3254 struct rte_mbuf *mbuf;
3259 * Packet length exceeds the allowed inline
3260 * data length, check whether the minimal
3261 * inlining is required.
3263 if (txq->inlen_mode) {
3264 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3265 assert(txq->inlen_mode <= txq->inlen_send);
3266 inlen = txq->inlen_mode;
3268 if (!vlan || txq->vlan_en) {
3270 * VLAN insertion will be done inside by HW.
3271 * It is not utmost effective - VLAN flag is
3272 * checked twice, but we should proceed the
3273 * inlining length correctly and take into
3274 * account the VLAN header being inserted.
3276 return mlx5_tx_packet_multi_send
3279 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3282 * Now we know the minimal amount of data is requested
3283 * to inline. Check whether we should inline the buffers
3284 * from the chain beginning to eliminate some mbufs.
3287 nxlen = rte_pktmbuf_data_len(mbuf);
3288 if (unlikely(nxlen <= txq->inlen_send)) {
3289 /* We can inline first mbuf at least. */
3290 if (nxlen < inlen) {
3293 /* Scan mbufs till inlen filled. */
3298 nxlen = rte_pktmbuf_data_len(mbuf);
3300 } while (unlikely(nxlen < inlen));
3301 if (unlikely(nxlen > txq->inlen_send)) {
3302 /* We cannot inline entire mbuf. */
3303 smlen = inlen - smlen;
3304 start = rte_pktmbuf_mtod_offset
3305 (mbuf, uintptr_t, smlen);
3312 /* There should be not end of packet. */
3314 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3315 } while (unlikely(nxlen < txq->inlen_send));
3317 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3319 * Check whether we can do inline to align start
3320 * address of data buffer to cacheline.
3323 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3324 if (unlikely(start)) {
3326 if (start <= txq->inlen_send)
3331 * Check whether there are enough free WQEBBs:
3333 * - Ethernet Segment
3334 * - First Segment of inlined Ethernet data
3335 * - ... data continued ...
3336 * - Data Segments of pointer/min inline type
3338 * Estimate the number of Data Segments conservatively,
3339 * supposing no any mbufs is being freed during inlining.
3341 assert(inlen <= txq->inlen_send);
3342 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3343 MLX5_ESEG_MIN_INLINE_SIZE +
3345 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3346 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3347 return MLX5_TXCMP_CODE_EXIT;
3348 /* Check for maximal WQE size. */
3349 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3350 return MLX5_TXCMP_CODE_ERROR;
3351 #ifdef MLX5_PMD_SOFT_COUNTERS
3352 /* Update sent data bytes/packets counters. */
3353 txq->stats.obytes += dlen + vlan;
3355 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3356 loc->wqe_last = wqe;
3357 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3358 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3359 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3360 txq->wqe_ci += (ds + 3) / 4;
3361 loc->wqe_free -= (ds + 3) / 4;
3362 /* Request CQE generation if limits are reached. */
3363 mlx5_tx_request_completion(txq, loc, olx);
3364 return MLX5_TXCMP_CODE_MULTI;
3368 * Tx burst function for multi-segment packets. Supports all
3369 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3370 * sends one packet per WQE. Function stops sending if it
3371 * encounters the single-segment packet.
3373 * This routine is responsible for storing processed mbuf
3374 * into elts ring buffer and update elts_head.
3377 * Pointer to TX queue structure.
3379 * Packets to transmit.
3381 * Number of packets in array.
3383 * Pointer to burst routine local context.
3385 * Configured Tx offloads mask. It is fully defined at
3386 * compile time and may be used for optimization.
3389 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3390 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3391 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3392 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3393 * Local context variables updated.
3395 static __rte_always_inline enum mlx5_txcmp_code
3396 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3397 struct rte_mbuf **restrict pkts,
3398 unsigned int pkts_n,
3399 struct mlx5_txq_local *restrict loc,
3402 assert(loc->elts_free && loc->wqe_free);
3403 assert(pkts_n > loc->pkts_sent);
3404 pkts += loc->pkts_sent + 1;
3405 pkts_n -= loc->pkts_sent;
3407 enum mlx5_txcmp_code ret;
3409 assert(NB_SEGS(loc->mbuf) > 1);
3411 * Estimate the number of free elts quickly but
3412 * conservatively. Some segment may be fully inlined
3413 * and freed, ignore this here - precise estimation
3416 if (loc->elts_free < NB_SEGS(loc->mbuf))
3417 return MLX5_TXCMP_CODE_EXIT;
3418 if (MLX5_TXOFF_CONFIG(TSO) &&
3419 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3420 /* Proceed with multi-segment TSO. */
3421 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3422 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3423 /* Proceed with multi-segment SEND with inlining. */
3424 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3426 /* Proceed with multi-segment SEND w/o inlining. */
3427 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3429 if (ret == MLX5_TXCMP_CODE_EXIT)
3430 return MLX5_TXCMP_CODE_EXIT;
3431 if (ret == MLX5_TXCMP_CODE_ERROR)
3432 return MLX5_TXCMP_CODE_ERROR;
3433 /* WQE is built, go to the next packet. */
3436 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3437 return MLX5_TXCMP_CODE_EXIT;
3438 loc->mbuf = *pkts++;
3440 rte_prefetch0(*pkts);
3441 if (likely(NB_SEGS(loc->mbuf) > 1))
3443 /* Here ends the series of multi-segment packets. */
3444 if (MLX5_TXOFF_CONFIG(TSO) &&
3445 unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3446 return MLX5_TXCMP_CODE_TSO;
3447 return MLX5_TXCMP_CODE_SINGLE;
3453 * Tx burst function for single-segment packets with TSO.
3454 * Supports all types of Tx offloads, except multi-packets.
3455 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3456 * Function stops sending if it encounters the multi-segment
3457 * packet or packet without TSO requested.
3459 * The routine is responsible for storing processed mbuf
3460 * into elts ring buffer and update elts_head if inline
3461 * offloads is requested due to possible early freeing
3462 * of the inlined mbufs (can not store pkts array in elts
3466 * Pointer to TX queue structure.
3468 * Packets to transmit.
3470 * Number of packets in array.
3472 * Pointer to burst routine local context.
3474 * Configured Tx offloads mask. It is fully defined at
3475 * compile time and may be used for optimization.
3478 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3479 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3480 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3481 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3482 * Local context variables updated.
3484 static __rte_always_inline enum mlx5_txcmp_code
3485 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3486 struct rte_mbuf **restrict pkts,
3487 unsigned int pkts_n,
3488 struct mlx5_txq_local *restrict loc,
3491 assert(loc->elts_free && loc->wqe_free);
3492 assert(pkts_n > loc->pkts_sent);
3493 pkts += loc->pkts_sent + 1;
3494 pkts_n -= loc->pkts_sent;
3496 struct mlx5_wqe_dseg *restrict dseg;
3497 struct mlx5_wqe *restrict wqe;
3498 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3501 assert(NB_SEGS(loc->mbuf) == 1);
3502 dlen = rte_pktmbuf_data_len(loc->mbuf);
3503 if (MLX5_TXOFF_CONFIG(VLAN) &&
3504 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3505 vlan = sizeof(struct rte_vlan_hdr);
3508 * First calculate the WQE size to check
3509 * whether we have enough space in ring buffer.
3511 hlen = loc->mbuf->l2_len + vlan +
3512 loc->mbuf->l3_len + loc->mbuf->l4_len;
3513 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3514 return MLX5_TXCMP_CODE_ERROR;
3515 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3516 hlen += loc->mbuf->outer_l2_len +
3517 loc->mbuf->outer_l3_len;
3518 /* Segment must contain all TSO headers. */
3519 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3520 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3521 hlen > (dlen + vlan)))
3522 return MLX5_TXCMP_CODE_ERROR;
3524 * Check whether there are enough free WQEBBs:
3526 * - Ethernet Segment
3527 * - First Segment of inlined Ethernet data
3528 * - ... data continued ...
3529 * - Finishing Data Segment of pointer type
3531 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3532 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3533 if (loc->wqe_free < ((ds + 3) / 4))
3534 return MLX5_TXCMP_CODE_EXIT;
3535 #ifdef MLX5_PMD_SOFT_COUNTERS
3536 /* Update sent data bytes/packets counters. */
3537 ntcp = (dlen + vlan - hlen +
3538 loc->mbuf->tso_segsz - 1) /
3539 loc->mbuf->tso_segsz;
3541 * One will be added for mbuf itself at the end
3542 * of the mlx5_tx_burst from loc->pkts_sent field.
3545 txq->stats.opackets += ntcp;
3546 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3549 * Build the TSO WQE:
3551 * - Ethernet Segment with hlen bytes inlined
3552 * - Data Segment of pointer type
3554 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3555 loc->wqe_last = wqe;
3556 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3557 MLX5_OPCODE_TSO, olx);
3558 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3559 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3560 dlen -= hlen - vlan;
3561 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3563 * WQE is built, update the loop parameters
3564 * and go to the next packet.
3566 txq->wqe_ci += (ds + 3) / 4;
3567 loc->wqe_free -= (ds + 3) / 4;
3568 if (MLX5_TXOFF_CONFIG(INLINE))
3569 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3573 /* Request CQE generation if limits are reached. */
3574 mlx5_tx_request_completion(txq, loc, olx);
3575 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3576 return MLX5_TXCMP_CODE_EXIT;
3577 loc->mbuf = *pkts++;
3579 rte_prefetch0(*pkts);
3580 if (MLX5_TXOFF_CONFIG(MULTI) &&
3581 unlikely(NB_SEGS(loc->mbuf) > 1))
3582 return MLX5_TXCMP_CODE_MULTI;
3583 if (unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3584 return MLX5_TXCMP_CODE_SINGLE;
3585 /* Continue with the next TSO packet. */
3591 * Analyze the packet and select the best method to send.
3594 * Pointer to TX queue structure.
3596 * Pointer to burst routine local context.
3598 * Configured Tx offloads mask. It is fully defined at
3599 * compile time and may be used for optimization.
3601 * The predefined flag whether do complete check for
3602 * multi-segment packets and TSO.
3605 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3606 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3607 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3608 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3610 static __rte_always_inline enum mlx5_txcmp_code
3611 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3612 struct mlx5_txq_local *restrict loc,
3616 /* Check for multi-segment packet. */
3618 MLX5_TXOFF_CONFIG(MULTI) &&
3619 unlikely(NB_SEGS(loc->mbuf) > 1))
3620 return MLX5_TXCMP_CODE_MULTI;
3621 /* Check for TSO packet. */
3623 MLX5_TXOFF_CONFIG(TSO) &&
3624 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3625 return MLX5_TXCMP_CODE_TSO;
3626 /* Check if eMPW is enabled at all. */
3627 if (!MLX5_TXOFF_CONFIG(EMPW))
3628 return MLX5_TXCMP_CODE_SINGLE;
3629 /* Check if eMPW can be engaged. */
3630 if (MLX5_TXOFF_CONFIG(VLAN) &&
3631 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3632 (!MLX5_TXOFF_CONFIG(INLINE) ||
3633 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3634 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3636 * eMPW does not support VLAN insertion offload,
3637 * we have to inline the entire packet but
3638 * packet is too long for inlining.
3640 return MLX5_TXCMP_CODE_SINGLE;
3642 return MLX5_TXCMP_CODE_EMPW;
3646 * Check the next packet attributes to match with the eMPW batch ones.
3649 * Pointer to TX queue structure.
3651 * Pointer to Ethernet Segment of eMPW batch.
3653 * Pointer to burst routine local context.
3655 * Configured Tx offloads mask. It is fully defined at
3656 * compile time and may be used for optimization.
3659 * true - packet match with eMPW batch attributes.
3660 * false - no match, eMPW should be restarted.
3662 static __rte_always_inline bool
3663 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3664 struct mlx5_wqe_eseg *restrict es,
3665 struct mlx5_txq_local *restrict loc,
3668 uint8_t swp_flags = 0;
3670 /* Compare the checksum flags, if any. */
3671 if (MLX5_TXOFF_CONFIG(CSUM) &&
3672 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3674 /* Compare the Software Parser offsets and flags. */
3675 if (MLX5_TXOFF_CONFIG(SWP) &&
3676 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3677 es->swp_flags != swp_flags))
3679 /* Fill metadata field if needed. */
3680 if (MLX5_TXOFF_CONFIG(METADATA) &&
3681 es->metadata != (loc->mbuf->ol_flags & PKT_TX_METADATA ?
3682 loc->mbuf->tx_metadata : 0))
3684 /* There must be no VLAN packets in eMPW loop. */
3685 if (MLX5_TXOFF_CONFIG(VLAN))
3686 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3691 * Update send loop variables and WQE for eMPW loop
3692 * without data inlining. Number of Data Segments is
3693 * equal to the number of sent packets.
3696 * Pointer to TX queue structure.
3698 * Pointer to burst routine local context.
3700 * Number of packets/Data Segments/Packets.
3702 * Accumulated statistics, bytes sent
3704 * Configured Tx offloads mask. It is fully defined at
3705 * compile time and may be used for optimization.
3708 * true - packet match with eMPW batch attributes.
3709 * false - no match, eMPW should be restarted.
3711 static __rte_always_inline void
3712 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3713 struct mlx5_txq_local *restrict loc,
3718 assert(!MLX5_TXOFF_CONFIG(INLINE));
3719 #ifdef MLX5_PMD_SOFT_COUNTERS
3720 /* Update sent data bytes counter. */
3721 txq->stats.obytes += slen;
3725 loc->elts_free -= ds;
3726 loc->pkts_sent += ds;
3728 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3729 txq->wqe_ci += (ds + 3) / 4;
3730 loc->wqe_free -= (ds + 3) / 4;
3731 /* Request CQE generation if limits are reached. */
3732 mlx5_tx_request_completion(txq, loc, olx);
3736 * Update send loop variables and WQE for eMPW loop
3737 * with data inlining. Gets the size of pushed descriptors
3738 * and data to the WQE.
3741 * Pointer to TX queue structure.
3743 * Pointer to burst routine local context.
3745 * Total size of descriptor/data in bytes.
3747 * Accumulated statistics, data bytes sent.
3749 * Configured Tx offloads mask. It is fully defined at
3750 * compile time and may be used for optimization.
3753 * true - packet match with eMPW batch attributes.
3754 * false - no match, eMPW should be restarted.
3756 static __rte_always_inline void
3757 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3758 struct mlx5_txq_local *restrict loc,
3761 unsigned int olx __rte_unused)
3763 assert(MLX5_TXOFF_CONFIG(INLINE));
3764 assert((len % MLX5_WSEG_SIZE) == 0);
3765 #ifdef MLX5_PMD_SOFT_COUNTERS
3766 /* Update sent data bytes counter. */
3767 txq->stats.obytes += slen;
3771 len = len / MLX5_WSEG_SIZE + 2;
3772 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3773 txq->wqe_ci += (len + 3) / 4;
3774 loc->wqe_free -= (len + 3) / 4;
3775 /* Request CQE generation if limits are reached. */
3776 mlx5_tx_request_completion(txq, loc, olx);
3780 * The set of Tx burst functions for single-segment packets
3781 * without TSO and with Multi-Packet Writing feature support.
3782 * Supports all types of Tx offloads, except multi-packets
3785 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3786 * as many packet per WQE as it can. If eMPW is not configured
3787 * or packet can not be sent with eMPW (VLAN insertion) the
3788 * ordinary SEND opcode is used and only one packet placed
3791 * Functions stop sending if it encounters the multi-segment
3792 * packet or packet with TSO requested.
3794 * The routines are responsible for storing processed mbuf
3795 * into elts ring buffer and update elts_head if inlining
3796 * offload is requested. Otherwise the copying mbufs to elts
3797 * can be postponed and completed at the end of burst routine.
3800 * Pointer to TX queue structure.
3802 * Packets to transmit.
3804 * Number of packets in array.
3806 * Pointer to burst routine local context.
3808 * Configured Tx offloads mask. It is fully defined at
3809 * compile time and may be used for optimization.
3812 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3813 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3814 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3815 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3816 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3817 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3819 * Local context variables updated.
3822 * The routine sends packets with MLX5_OPCODE_EMPW
3823 * without inlining, this is dedicated optimized branch.
3824 * No VLAN insertion is supported.
3826 static __rte_always_inline enum mlx5_txcmp_code
3827 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3828 struct rte_mbuf **restrict pkts,
3829 unsigned int pkts_n,
3830 struct mlx5_txq_local *restrict loc,
3834 * Subroutine is the part of mlx5_tx_burst_single()
3835 * and sends single-segment packet with eMPW opcode
3836 * without data inlining.
3838 assert(!MLX5_TXOFF_CONFIG(INLINE));
3839 assert(MLX5_TXOFF_CONFIG(EMPW));
3840 assert(loc->elts_free && loc->wqe_free);
3841 assert(pkts_n > loc->pkts_sent);
3842 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3843 pkts += loc->pkts_sent + 1;
3844 pkts_n -= loc->pkts_sent;
3846 struct mlx5_wqe_dseg *restrict dseg;
3847 struct mlx5_wqe_eseg *restrict eseg;
3848 enum mlx5_txcmp_code ret;
3849 unsigned int part, loop;
3850 unsigned int slen = 0;
3853 part = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
3854 if (unlikely(loc->elts_free < part)) {
3855 /* We have no enough elts to save all mbufs. */
3856 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3857 return MLX5_TXCMP_CODE_EXIT;
3858 /* But we still able to send at least minimal eMPW. */
3859 part = loc->elts_free;
3861 /* Check whether we have enough WQEs */
3862 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3863 if (unlikely(loc->wqe_free <
3864 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3865 return MLX5_TXCMP_CODE_EXIT;
3866 part = (loc->wqe_free * 4) - 2;
3868 if (likely(part > 1))
3869 rte_prefetch0(*pkts);
3870 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3872 * Build eMPW title WQEBB:
3873 * - Control Segment, eMPW opcode
3874 * - Ethernet Segment, no inline
3876 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3877 MLX5_OPCODE_ENHANCED_MPSW, olx);
3878 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3879 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3880 eseg = &loc->wqe_last->eseg;
3881 dseg = &loc->wqe_last->dseg[0];
3884 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3885 #ifdef MLX5_PMD_SOFT_COUNTERS
3886 /* Update sent data bytes counter. */
3891 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3893 if (unlikely(--loop == 0))
3895 loc->mbuf = *pkts++;
3896 if (likely(loop > 1))
3897 rte_prefetch0(*pkts);
3898 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3900 * Unroll the completion code to avoid
3901 * returning variable value - it results in
3902 * unoptimized sequent checking in caller.
3904 if (ret == MLX5_TXCMP_CODE_MULTI) {
3906 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3907 if (unlikely(!loc->elts_free ||
3909 return MLX5_TXCMP_CODE_EXIT;
3910 return MLX5_TXCMP_CODE_MULTI;
3912 if (ret == MLX5_TXCMP_CODE_TSO) {
3914 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3915 if (unlikely(!loc->elts_free ||
3917 return MLX5_TXCMP_CODE_EXIT;
3918 return MLX5_TXCMP_CODE_TSO;
3920 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3922 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3923 if (unlikely(!loc->elts_free ||
3925 return MLX5_TXCMP_CODE_EXIT;
3926 return MLX5_TXCMP_CODE_SINGLE;
3928 if (ret != MLX5_TXCMP_CODE_EMPW) {
3931 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3932 return MLX5_TXCMP_CODE_ERROR;
3935 * Check whether packet parameters coincide
3936 * within assumed eMPW batch:
3937 * - check sum settings
3939 * - software parser settings
3941 if (!mlx5_tx_match_empw(txq, eseg, loc, olx)) {
3944 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3945 if (unlikely(!loc->elts_free ||
3947 return MLX5_TXCMP_CODE_EXIT;
3951 /* Packet attributes match, continue the same eMPW. */
3953 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3954 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3956 /* eMPW is built successfully, update loop parameters. */
3958 assert(pkts_n >= part);
3959 #ifdef MLX5_PMD_SOFT_COUNTERS
3960 /* Update sent data bytes counter. */
3961 txq->stats.obytes += slen;
3963 loc->elts_free -= part;
3964 loc->pkts_sent += part;
3965 txq->wqe_ci += (2 + part + 3) / 4;
3966 loc->wqe_free -= (2 + part + 3) / 4;
3968 /* Request CQE generation if limits are reached. */
3969 mlx5_tx_request_completion(txq, loc, olx);
3970 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3971 return MLX5_TXCMP_CODE_EXIT;
3972 loc->mbuf = *pkts++;
3973 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3974 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
3976 /* Continue sending eMPW batches. */
3982 * The routine sends packets with MLX5_OPCODE_EMPW
3983 * with inlining, optionally supports VLAN insertion.
3985 static __rte_always_inline enum mlx5_txcmp_code
3986 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
3987 struct rte_mbuf **restrict pkts,
3988 unsigned int pkts_n,
3989 struct mlx5_txq_local *restrict loc,
3993 * Subroutine is the part of mlx5_tx_burst_single()
3994 * and sends single-segment packet with eMPW opcode
3995 * with data inlining.
3997 assert(MLX5_TXOFF_CONFIG(INLINE));
3998 assert(MLX5_TXOFF_CONFIG(EMPW));
3999 assert(loc->elts_free && loc->wqe_free);
4000 assert(pkts_n > loc->pkts_sent);
4001 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4002 pkts += loc->pkts_sent + 1;
4003 pkts_n -= loc->pkts_sent;
4005 struct mlx5_wqe_dseg *restrict dseg;
4006 struct mlx5_wqe_eseg *restrict eseg;
4007 enum mlx5_txcmp_code ret;
4008 unsigned int room, part, nlim;
4009 unsigned int slen = 0;
4012 * Limits the amount of packets in one WQE
4013 * to improve CQE latency generation.
4015 nlim = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
4016 /* Check whether we have minimal amount WQEs */
4017 if (unlikely(loc->wqe_free <
4018 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4019 return MLX5_TXCMP_CODE_EXIT;
4020 if (likely(pkts_n > 1))
4021 rte_prefetch0(*pkts);
4022 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4024 * Build eMPW title WQEBB:
4025 * - Control Segment, eMPW opcode, zero DS
4026 * - Ethernet Segment, no inline
4028 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
4029 MLX5_OPCODE_ENHANCED_MPSW, olx);
4030 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4031 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4032 eseg = &loc->wqe_last->eseg;
4033 dseg = &loc->wqe_last->dseg[0];
4034 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4035 loc->wqe_free) * MLX5_WQE_SIZE -
4036 MLX5_WQE_CSEG_SIZE -
4038 /* Build WQE till we have space, packets and resources. */
4041 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4042 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4045 assert(room >= MLX5_WQE_DSEG_SIZE);
4046 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
4047 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4049 * Some Tx offloads may cause an error if
4050 * packet is not long enough, check against
4051 * assumed minimal length.
4053 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4055 if (unlikely(!part))
4056 return MLX5_TXCMP_CODE_ERROR;
4058 * We have some successfully built
4059 * packet Data Segments to send.
4061 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4062 return MLX5_TXCMP_CODE_ERROR;
4064 /* Inline or not inline - that's the Question. */
4065 if (dlen > txq->inlen_empw)
4067 /* Inline entire packet, optional VLAN insertion. */
4068 tlen = sizeof(dseg->bcount) + dlen;
4069 if (MLX5_TXOFF_CONFIG(VLAN) &&
4070 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4072 * The packet length must be checked in
4073 * mlx5_tx_able_to_empw() and packet
4074 * fits into inline length guaranteed.
4076 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
4078 tlen += sizeof(struct rte_vlan_hdr);
4081 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4083 #ifdef MLX5_PMD_SOFT_COUNTERS
4084 /* Update sent data bytes counter. */
4085 slen += sizeof(struct rte_vlan_hdr);
4090 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4093 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4094 assert(room >= tlen);
4097 * Packet data are completely inlined,
4098 * free the packet immediately.
4100 rte_pktmbuf_free_seg(loc->mbuf);
4104 * Not inlinable VLAN packets are
4105 * proceeded outside of this routine.
4107 assert(room >= MLX5_WQE_DSEG_SIZE);
4108 if (MLX5_TXOFF_CONFIG(VLAN))
4109 assert(!(loc->mbuf->ol_flags &
4111 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4112 /* We have to store mbuf in elts.*/
4113 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4114 room -= MLX5_WQE_DSEG_SIZE;
4115 /* Ring buffer wraparound is checked at the loop end.*/
4118 #ifdef MLX5_PMD_SOFT_COUNTERS
4119 /* Update sent data bytes counter. */
4125 if (unlikely(!pkts_n || !loc->elts_free)) {
4127 * We have no resources/packets to
4128 * continue build descriptors.
4131 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4132 return MLX5_TXCMP_CODE_EXIT;
4134 loc->mbuf = *pkts++;
4135 if (likely(pkts_n > 1))
4136 rte_prefetch0(*pkts);
4137 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4139 * Unroll the completion code to avoid
4140 * returning variable value - it results in
4141 * unoptimized sequent checking in caller.
4143 if (ret == MLX5_TXCMP_CODE_MULTI) {
4145 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4146 if (unlikely(!loc->elts_free ||
4148 return MLX5_TXCMP_CODE_EXIT;
4149 return MLX5_TXCMP_CODE_MULTI;
4151 if (ret == MLX5_TXCMP_CODE_TSO) {
4153 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4154 if (unlikely(!loc->elts_free ||
4156 return MLX5_TXCMP_CODE_EXIT;
4157 return MLX5_TXCMP_CODE_TSO;
4159 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4161 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4162 if (unlikely(!loc->elts_free ||
4164 return MLX5_TXCMP_CODE_EXIT;
4165 return MLX5_TXCMP_CODE_SINGLE;
4167 if (ret != MLX5_TXCMP_CODE_EMPW) {
4170 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4171 return MLX5_TXCMP_CODE_ERROR;
4173 /* Check if we have minimal room left. */
4175 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4178 * Check whether packet parameters coincide
4179 * within assumed eMPW batch:
4180 * - check sum settings
4182 * - software parser settings
4184 if (!mlx5_tx_match_empw(txq, eseg, loc, olx))
4186 /* Packet attributes match, continue the same eMPW. */
4187 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4188 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4191 * We get here to close an existing eMPW
4192 * session and start the new one.
4196 if (unlikely(!part))
4197 return MLX5_TXCMP_CODE_EXIT;
4198 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4199 if (unlikely(!loc->elts_free ||
4201 return MLX5_TXCMP_CODE_EXIT;
4202 /* Continue the loop with new eMPW session. */
4208 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4209 * Data inlining and VLAN insertion are supported.
4211 static __rte_always_inline enum mlx5_txcmp_code
4212 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4213 struct rte_mbuf **restrict pkts,
4214 unsigned int pkts_n,
4215 struct mlx5_txq_local *restrict loc,
4219 * Subroutine is the part of mlx5_tx_burst_single()
4220 * and sends single-segment packet with SEND opcode.
4222 assert(loc->elts_free && loc->wqe_free);
4223 assert(pkts_n > loc->pkts_sent);
4224 pkts += loc->pkts_sent + 1;
4225 pkts_n -= loc->pkts_sent;
4227 struct mlx5_wqe *restrict wqe;
4228 enum mlx5_txcmp_code ret;
4230 assert(NB_SEGS(loc->mbuf) == 1);
4231 if (MLX5_TXOFF_CONFIG(INLINE)) {
4232 unsigned int inlen, vlan = 0;
4234 inlen = rte_pktmbuf_data_len(loc->mbuf);
4235 if (MLX5_TXOFF_CONFIG(VLAN) &&
4236 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4237 vlan = sizeof(struct rte_vlan_hdr);
4239 static_assert((sizeof(struct rte_vlan_hdr) +
4240 sizeof(struct rte_ether_hdr)) ==
4241 MLX5_ESEG_MIN_INLINE_SIZE,
4242 "invalid min inline data size");
4245 * If inlining is enabled at configuration time
4246 * the limit must be not less than minimal size.
4247 * Otherwise we would do extra check for data
4248 * size to avoid crashes due to length overflow.
4250 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4251 if (inlen <= txq->inlen_send) {
4252 unsigned int seg_n, wqe_n;
4254 rte_prefetch0(rte_pktmbuf_mtod
4255 (loc->mbuf, uint8_t *));
4256 /* Check against minimal length. */
4257 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4258 return MLX5_TXCMP_CODE_ERROR;
4260 * Completely inlined packet data WQE:
4261 * - Control Segment, SEND opcode
4262 * - Ethernet Segment, no VLAN insertion
4263 * - Data inlined, VLAN optionally inserted
4264 * - Alignment to MLX5_WSEG_SIZE
4265 * Have to estimate amount of WQEBBs
4267 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4268 MLX5_ESEG_MIN_INLINE_SIZE +
4269 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4270 /* Check if there are enough WQEBBs. */
4271 wqe_n = (seg_n + 3) / 4;
4272 if (wqe_n > loc->wqe_free)
4273 return MLX5_TXCMP_CODE_EXIT;
4274 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4275 loc->wqe_last = wqe;
4276 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4277 MLX5_OPCODE_SEND, olx);
4278 mlx5_tx_eseg_data(txq, loc, wqe,
4279 vlan, inlen, 0, olx);
4280 txq->wqe_ci += wqe_n;
4281 loc->wqe_free -= wqe_n;
4283 * Packet data are completely inlined,
4284 * free the packet immediately.
4286 rte_pktmbuf_free_seg(loc->mbuf);
4287 } else if (!MLX5_TXOFF_CONFIG(EMPW) &&
4290 * If minimal inlining is requested the eMPW
4291 * feature should be disabled due to data is
4292 * inlined into Ethernet Segment, which can
4293 * not contain inlined data for eMPW due to
4294 * segment shared for all packets.
4296 struct mlx5_wqe_dseg *restrict dseg;
4301 * The inline-mode settings require
4302 * to inline the specified amount of
4303 * data bytes to the Ethernet Segment.
4304 * We should check the free space in
4305 * WQE ring buffer to inline partially.
4307 assert(txq->inlen_send >= txq->inlen_mode);
4308 assert(inlen > txq->inlen_mode);
4309 assert(txq->inlen_mode >=
4310 MLX5_ESEG_MIN_INLINE_SIZE);
4312 * Check whether there are enough free WQEBBs:
4314 * - Ethernet Segment
4315 * - First Segment of inlined Ethernet data
4316 * - ... data continued ...
4317 * - Finishing Data Segment of pointer type
4319 ds = (MLX5_WQE_CSEG_SIZE +
4320 MLX5_WQE_ESEG_SIZE +
4321 MLX5_WQE_DSEG_SIZE +
4323 MLX5_ESEG_MIN_INLINE_SIZE +
4324 MLX5_WQE_DSEG_SIZE +
4325 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4326 if (loc->wqe_free < ((ds + 3) / 4))
4327 return MLX5_TXCMP_CODE_EXIT;
4329 * Build the ordinary SEND WQE:
4331 * - Ethernet Segment, inline inlen_mode bytes
4332 * - Data Segment of pointer type
4334 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4335 loc->wqe_last = wqe;
4336 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4337 MLX5_OPCODE_SEND, olx);
4338 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4341 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4342 txq->inlen_mode - vlan;
4343 inlen -= txq->inlen_mode;
4344 mlx5_tx_dseg_ptr(txq, loc, dseg,
4347 * WQE is built, update the loop parameters
4348 * and got to the next packet.
4350 txq->wqe_ci += (ds + 3) / 4;
4351 loc->wqe_free -= (ds + 3) / 4;
4352 /* We have to store mbuf in elts.*/
4353 assert(MLX5_TXOFF_CONFIG(INLINE));
4354 txq->elts[txq->elts_head++ & txq->elts_m] =
4362 * Partially inlined packet data WQE, we have
4363 * some space in title WQEBB, we can fill it
4364 * with some packet data. It takes one WQEBB,
4365 * it is available, no extra space check:
4366 * - Control Segment, SEND opcode
4367 * - Ethernet Segment, no VLAN insertion
4368 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4369 * - Data Segment, pointer type
4371 * We also get here if VLAN insertion is not
4372 * supported by HW, the inline is enabled.
4374 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4375 loc->wqe_last = wqe;
4376 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4377 MLX5_OPCODE_SEND, olx);
4378 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4379 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4380 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4382 * The length check is performed above, by
4383 * comparing with txq->inlen_send. We should
4384 * not get overflow here.
4386 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4387 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4388 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4392 /* We have to store mbuf in elts.*/
4393 assert(MLX5_TXOFF_CONFIG(INLINE));
4394 txq->elts[txq->elts_head++ & txq->elts_m] =
4398 #ifdef MLX5_PMD_SOFT_COUNTERS
4399 /* Update sent data bytes counter. */
4400 txq->stats.obytes += vlan +
4401 rte_pktmbuf_data_len(loc->mbuf);
4405 * No inline at all, it means the CPU cycles saving
4406 * is prioritized at configuration, we should not
4407 * copy any packet data to WQE.
4409 * SEND WQE, one WQEBB:
4410 * - Control Segment, SEND opcode
4411 * - Ethernet Segment, optional VLAN, no inline
4412 * - Data Segment, pointer type
4414 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4415 loc->wqe_last = wqe;
4416 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4417 MLX5_OPCODE_SEND, olx);
4418 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4420 (txq, loc, &wqe->dseg[0],
4421 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4422 rte_pktmbuf_data_len(loc->mbuf), olx);
4426 * We should not store mbuf pointer in elts
4427 * if no inlining is configured, this is done
4428 * by calling routine in a batch copy.
4430 assert(!MLX5_TXOFF_CONFIG(INLINE));
4432 #ifdef MLX5_PMD_SOFT_COUNTERS
4433 /* Update sent data bytes counter. */
4434 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4435 if (MLX5_TXOFF_CONFIG(VLAN) &&
4436 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4437 txq->stats.obytes +=
4438 sizeof(struct rte_vlan_hdr);
4443 /* Request CQE generation if limits are reached. */
4444 mlx5_tx_request_completion(txq, loc, olx);
4445 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4446 return MLX5_TXCMP_CODE_EXIT;
4447 loc->mbuf = *pkts++;
4449 rte_prefetch0(*pkts);
4450 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4451 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4457 static __rte_always_inline enum mlx5_txcmp_code
4458 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4459 struct rte_mbuf **restrict pkts,
4460 unsigned int pkts_n,
4461 struct mlx5_txq_local *restrict loc,
4464 enum mlx5_txcmp_code ret;
4466 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4467 if (ret == MLX5_TXCMP_CODE_SINGLE)
4469 assert(ret == MLX5_TXCMP_CODE_EMPW);
4471 /* Optimize for inline/no inline eMPW send. */
4472 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4473 mlx5_tx_burst_empw_inline
4474 (txq, pkts, pkts_n, loc, olx) :
4475 mlx5_tx_burst_empw_simple
4476 (txq, pkts, pkts_n, loc, olx);
4477 if (ret != MLX5_TXCMP_CODE_SINGLE)
4479 /* The resources to send one packet should remain. */
4480 assert(loc->elts_free && loc->wqe_free);
4482 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4483 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4484 if (ret != MLX5_TXCMP_CODE_EMPW)
4486 /* The resources to send one packet should remain. */
4487 assert(loc->elts_free && loc->wqe_free);
4492 * DPDK Tx callback template. This is configured template
4493 * used to generate routines optimized for specified offload setup.
4494 * One of this generated functions is chosen at SQ configuration
4498 * Generic pointer to TX queue structure.
4500 * Packets to transmit.
4502 * Number of packets in array.
4504 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4505 * values. Should be static to take compile time static configuration
4509 * Number of packets successfully transmitted (<= pkts_n).
4511 static __rte_always_inline uint16_t
4512 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4513 struct rte_mbuf **restrict pkts,
4517 struct mlx5_txq_local loc;
4518 enum mlx5_txcmp_code ret;
4521 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4522 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4524 * Check if there are some CQEs, if any:
4525 * - process an encountered errors
4526 * - process the completed WQEs
4527 * - free related mbufs
4528 * - doorbell the NIC about processed CQEs
4530 if (unlikely(!pkts_n))
4532 rte_prefetch0(*pkts);
4533 mlx5_tx_handle_completion(txq, olx);
4535 * Calculate the number of available resources - elts and WQEs.
4536 * There are two possible different scenarios:
4537 * - no data inlining into WQEs, one WQEBB may contains upto
4538 * four packets, in this case elts become scarce resource
4539 * - data inlining into WQEs, one packet may require multiple
4540 * WQEBBs, the WQEs become the limiting factor.
4542 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4543 loc.elts_free = txq->elts_s -
4544 (uint16_t)(txq->elts_head - txq->elts_tail);
4545 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4546 loc.wqe_free = txq->wqe_s -
4547 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4548 if (unlikely(!loc.elts_free || !loc.wqe_free))
4552 loc.wqe_last = NULL;
4555 * Fetch the packet from array. Usually this is
4556 * the first packet in series of multi/single
4559 loc.mbuf = *(pkts + loc.pkts_sent);
4560 /* Dedicated branch for multi-segment packets. */
4561 if (MLX5_TXOFF_CONFIG(MULTI) &&
4562 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4564 * Multi-segment packet encountered.
4565 * Hardware is able to process it only
4566 * with SEND/TSO opcodes, one packet
4567 * per WQE, do it in dedicated routine.
4570 assert(loc.pkts_sent >= loc.pkts_copy);
4571 part = loc.pkts_sent - loc.pkts_copy;
4572 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4574 * There are some single-segment mbufs not
4575 * stored in elts. The mbufs must be in the
4576 * same order as WQEs, so we must copy the
4577 * mbufs to elts here, before the coming
4578 * multi-segment packet mbufs is appended.
4580 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4582 loc.pkts_copy = loc.pkts_sent;
4584 assert(pkts_n > loc.pkts_sent);
4585 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4586 if (!MLX5_TXOFF_CONFIG(INLINE))
4587 loc.pkts_copy = loc.pkts_sent;
4589 * These returned code checks are supposed
4590 * to be optimized out due to routine inlining.
4592 if (ret == MLX5_TXCMP_CODE_EXIT) {
4594 * The routine returns this code when
4595 * all packets are sent or there is no
4596 * enough resources to complete request.
4600 if (ret == MLX5_TXCMP_CODE_ERROR) {
4602 * The routine returns this code when
4603 * some error in the incoming packets
4606 txq->stats.oerrors++;
4609 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4611 * The single-segment packet was encountered
4612 * in the array, try to send it with the
4613 * best optimized way, possible engaging eMPW.
4615 goto enter_send_single;
4617 if (MLX5_TXOFF_CONFIG(TSO) &&
4618 ret == MLX5_TXCMP_CODE_TSO) {
4620 * The single-segment TSO packet was
4621 * encountered in the array.
4623 goto enter_send_tso;
4625 /* We must not get here. Something is going wrong. */
4627 txq->stats.oerrors++;
4630 /* Dedicated branch for single-segment TSO packets. */
4631 if (MLX5_TXOFF_CONFIG(TSO) &&
4632 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4634 * TSO might require special way for inlining
4635 * (dedicated parameters) and is sent with
4636 * MLX5_OPCODE_TSO opcode only, provide this
4637 * in dedicated branch.
4640 assert(NB_SEGS(loc.mbuf) == 1);
4641 assert(pkts_n > loc.pkts_sent);
4642 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4644 * These returned code checks are supposed
4645 * to be optimized out due to routine inlining.
4647 if (ret == MLX5_TXCMP_CODE_EXIT)
4649 if (ret == MLX5_TXCMP_CODE_ERROR) {
4650 txq->stats.oerrors++;
4653 if (ret == MLX5_TXCMP_CODE_SINGLE)
4654 goto enter_send_single;
4655 if (MLX5_TXOFF_CONFIG(MULTI) &&
4656 ret == MLX5_TXCMP_CODE_MULTI) {
4658 * The multi-segment packet was
4659 * encountered in the array.
4661 goto enter_send_multi;
4663 /* We must not get here. Something is going wrong. */
4665 txq->stats.oerrors++;
4669 * The dedicated branch for the single-segment packets
4670 * without TSO. Often these ones can be sent using
4671 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4672 * The routine builds the WQEs till it encounters
4673 * the TSO or multi-segment packet (in case if these
4674 * offloads are requested at SQ configuration time).
4677 assert(pkts_n > loc.pkts_sent);
4678 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4680 * These returned code checks are supposed
4681 * to be optimized out due to routine inlining.
4683 if (ret == MLX5_TXCMP_CODE_EXIT)
4685 if (ret == MLX5_TXCMP_CODE_ERROR) {
4686 txq->stats.oerrors++;
4689 if (MLX5_TXOFF_CONFIG(MULTI) &&
4690 ret == MLX5_TXCMP_CODE_MULTI) {
4692 * The multi-segment packet was
4693 * encountered in the array.
4695 goto enter_send_multi;
4697 if (MLX5_TXOFF_CONFIG(TSO) &&
4698 ret == MLX5_TXCMP_CODE_TSO) {
4700 * The single-segment TSO packet was
4701 * encountered in the array.
4703 goto enter_send_tso;
4705 /* We must not get here. Something is going wrong. */
4707 txq->stats.oerrors++;
4711 * Main Tx loop is completed, do the rest:
4712 * - set completion request if thresholds are reached
4713 * - doorbell the hardware
4714 * - copy the rest of mbufs to elts (if any)
4716 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4717 /* Take a shortcut if nothing is sent. */
4718 if (unlikely(loc.pkts_sent == 0))
4721 * Ring QP doorbell immediately after WQE building completion
4722 * to improve latencies. The pure software related data treatment
4723 * can be completed after doorbell. Tx CQEs for this SQ are
4724 * processed in this thread only by the polling.
4726 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);
4727 /* Not all of the mbufs may be stored into elts yet. */
4728 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent -
4729 (MLX5_TXOFF_CONFIG(MULTI) ? loc.pkts_copy : 0);
4730 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4732 * There are some single-segment mbufs not stored in elts.
4733 * It can be only if the last packet was single-segment.
4734 * The copying is gathered into one place due to it is
4735 * a good opportunity to optimize that with SIMD.
4736 * Unfortunately if inlining is enabled the gaps in
4737 * pointer array may happen due to early freeing of the
4740 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4742 #ifdef MLX5_PMD_SOFT_COUNTERS
4743 /* Increment sent packets counter. */
4744 txq->stats.opackets += loc.pkts_sent;
4746 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4747 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4748 return loc.pkts_sent;
4751 /* Generate routines with Enhanced Multi-Packet Write support. */
4752 MLX5_TXOFF_DECL(full_empw,
4753 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4755 MLX5_TXOFF_DECL(none_empw,
4756 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4758 MLX5_TXOFF_DECL(md_empw,
4759 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4761 MLX5_TXOFF_DECL(mt_empw,
4762 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4763 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4765 MLX5_TXOFF_DECL(mtsc_empw,
4766 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4767 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4768 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4770 MLX5_TXOFF_DECL(mti_empw,
4771 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4772 MLX5_TXOFF_CONFIG_INLINE |
4773 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4775 MLX5_TXOFF_DECL(mtv_empw,
4776 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4777 MLX5_TXOFF_CONFIG_VLAN |
4778 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4780 MLX5_TXOFF_DECL(mtiv_empw,
4781 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4782 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4783 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4785 MLX5_TXOFF_DECL(sc_empw,
4786 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4787 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4789 MLX5_TXOFF_DECL(sci_empw,
4790 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4791 MLX5_TXOFF_CONFIG_INLINE |
4792 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4794 MLX5_TXOFF_DECL(scv_empw,
4795 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4796 MLX5_TXOFF_CONFIG_VLAN |
4797 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4799 MLX5_TXOFF_DECL(sciv_empw,
4800 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4801 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4802 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4804 MLX5_TXOFF_DECL(i_empw,
4805 MLX5_TXOFF_CONFIG_INLINE |
4806 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4808 MLX5_TXOFF_DECL(v_empw,
4809 MLX5_TXOFF_CONFIG_VLAN |
4810 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4812 MLX5_TXOFF_DECL(iv_empw,
4813 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4814 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4816 /* Generate routines without Enhanced Multi-Packet Write support. */
4817 MLX5_TXOFF_DECL(full,
4818 MLX5_TXOFF_CONFIG_FULL)
4820 MLX5_TXOFF_DECL(none,
4821 MLX5_TXOFF_CONFIG_NONE)
4824 MLX5_TXOFF_CONFIG_METADATA)
4827 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4828 MLX5_TXOFF_CONFIG_METADATA)
4830 MLX5_TXOFF_DECL(mtsc,
4831 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4832 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4833 MLX5_TXOFF_CONFIG_METADATA)
4835 MLX5_TXOFF_DECL(mti,
4836 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4837 MLX5_TXOFF_CONFIG_INLINE |
4838 MLX5_TXOFF_CONFIG_METADATA)
4841 MLX5_TXOFF_DECL(mtv,
4842 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4843 MLX5_TXOFF_CONFIG_VLAN |
4844 MLX5_TXOFF_CONFIG_METADATA)
4847 MLX5_TXOFF_DECL(mtiv,
4848 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4849 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4850 MLX5_TXOFF_CONFIG_METADATA)
4853 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4854 MLX5_TXOFF_CONFIG_METADATA)
4856 MLX5_TXOFF_DECL(sci,
4857 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4858 MLX5_TXOFF_CONFIG_INLINE |
4859 MLX5_TXOFF_CONFIG_METADATA)
4862 MLX5_TXOFF_DECL(scv,
4863 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4864 MLX5_TXOFF_CONFIG_VLAN |
4865 MLX5_TXOFF_CONFIG_METADATA)
4868 MLX5_TXOFF_DECL(sciv,
4869 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4870 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4871 MLX5_TXOFF_CONFIG_METADATA)
4874 MLX5_TXOFF_CONFIG_INLINE |
4875 MLX5_TXOFF_CONFIG_METADATA)
4878 MLX5_TXOFF_CONFIG_VLAN |
4879 MLX5_TXOFF_CONFIG_METADATA)
4882 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4883 MLX5_TXOFF_CONFIG_METADATA)
4886 * Array of declared and compiled Tx burst function and corresponding
4887 * supported offloads set. The array is used to select the Tx burst
4888 * function for specified offloads set at Tx queue configuration time.
4891 eth_tx_burst_t func;
4894 MLX5_TXOFF_INFO(full_empw,
4895 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4896 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4897 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4898 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4900 MLX5_TXOFF_INFO(none_empw,
4901 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4903 MLX5_TXOFF_INFO(md_empw,
4904 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4906 MLX5_TXOFF_INFO(mt_empw,
4907 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4908 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4910 MLX5_TXOFF_INFO(mtsc_empw,
4911 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4912 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4913 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4915 MLX5_TXOFF_INFO(mti_empw,
4916 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4917 MLX5_TXOFF_CONFIG_INLINE |
4918 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4920 MLX5_TXOFF_INFO(mtv_empw,
4921 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4922 MLX5_TXOFF_CONFIG_VLAN |
4923 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4925 MLX5_TXOFF_INFO(mtiv_empw,
4926 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4927 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4928 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4930 MLX5_TXOFF_INFO(sc_empw,
4931 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4932 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4934 MLX5_TXOFF_INFO(sci_empw,
4935 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4936 MLX5_TXOFF_CONFIG_INLINE |
4937 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4939 MLX5_TXOFF_INFO(scv_empw,
4940 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4941 MLX5_TXOFF_CONFIG_VLAN |
4942 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4944 MLX5_TXOFF_INFO(sciv_empw,
4945 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4946 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4947 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4949 MLX5_TXOFF_INFO(i_empw,
4950 MLX5_TXOFF_CONFIG_INLINE |
4951 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4953 MLX5_TXOFF_INFO(v_empw,
4954 MLX5_TXOFF_CONFIG_VLAN |
4955 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4957 MLX5_TXOFF_INFO(iv_empw,
4958 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4959 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4961 MLX5_TXOFF_INFO(full,
4962 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4963 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4964 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4965 MLX5_TXOFF_CONFIG_METADATA)
4967 MLX5_TXOFF_INFO(none,
4968 MLX5_TXOFF_CONFIG_NONE)
4971 MLX5_TXOFF_CONFIG_METADATA)
4974 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4975 MLX5_TXOFF_CONFIG_METADATA)
4977 MLX5_TXOFF_INFO(mtsc,
4978 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4979 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4980 MLX5_TXOFF_CONFIG_METADATA)
4982 MLX5_TXOFF_INFO(mti,
4983 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4984 MLX5_TXOFF_CONFIG_INLINE |
4985 MLX5_TXOFF_CONFIG_METADATA)
4988 MLX5_TXOFF_INFO(mtv,
4989 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4990 MLX5_TXOFF_CONFIG_VLAN |
4991 MLX5_TXOFF_CONFIG_METADATA)
4993 MLX5_TXOFF_INFO(mtiv,
4994 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4995 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4996 MLX5_TXOFF_CONFIG_METADATA)
4999 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5000 MLX5_TXOFF_CONFIG_METADATA)
5002 MLX5_TXOFF_INFO(sci,
5003 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5004 MLX5_TXOFF_CONFIG_INLINE |
5005 MLX5_TXOFF_CONFIG_METADATA)
5007 MLX5_TXOFF_INFO(scv,
5008 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5009 MLX5_TXOFF_CONFIG_VLAN |
5010 MLX5_TXOFF_CONFIG_METADATA)
5012 MLX5_TXOFF_INFO(sciv,
5013 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5014 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5015 MLX5_TXOFF_CONFIG_METADATA)
5018 MLX5_TXOFF_CONFIG_INLINE |
5019 MLX5_TXOFF_CONFIG_METADATA)
5022 MLX5_TXOFF_CONFIG_VLAN |
5023 MLX5_TXOFF_CONFIG_METADATA)
5026 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5027 MLX5_TXOFF_CONFIG_METADATA)
5031 * Configure the Tx function to use. The routine checks configured
5032 * Tx offloads for the device and selects appropriate Tx burst
5033 * routine. There are multiple Tx burst routines compiled from
5034 * the same template in the most optimal way for the dedicated
5038 * Pointer to private data structure.
5041 * Pointer to selected Tx burst function.
5044 mlx5_select_tx_function(struct rte_eth_dev *dev)
5046 struct mlx5_priv *priv = dev->data->dev_private;
5047 struct mlx5_dev_config *config = &priv->config;
5048 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5049 unsigned int diff = 0, olx = 0, i, m;
5051 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5052 MLX5_DSEG_MAX, "invalid WQE max size");
5053 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5054 "invalid WQE Control Segment size");
5055 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5056 "invalid WQE Ethernet Segment size");
5057 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5058 "invalid WQE Data Segment size");
5059 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5060 "invalid WQE size");
5062 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5063 /* We should support Multi-Segment Packets. */
5064 olx |= MLX5_TXOFF_CONFIG_MULTI;
5066 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5067 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5068 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5069 DEV_TX_OFFLOAD_IP_TNL_TSO |
5070 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5071 /* We should support TCP Send Offload. */
5072 olx |= MLX5_TXOFF_CONFIG_TSO;
5074 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5075 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5076 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5077 /* We should support Software Parser for Tunnels. */
5078 olx |= MLX5_TXOFF_CONFIG_SWP;
5080 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5081 DEV_TX_OFFLOAD_UDP_CKSUM |
5082 DEV_TX_OFFLOAD_TCP_CKSUM |
5083 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5084 /* We should support IP/TCP/UDP Checksums. */
5085 olx |= MLX5_TXOFF_CONFIG_CSUM;
5087 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5088 /* We should support VLAN insertion. */
5089 olx |= MLX5_TXOFF_CONFIG_VLAN;
5091 if (priv->txqs_n && (*priv->txqs)[0]) {
5092 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5094 if (txd->inlen_send) {
5096 * Check the data inline requirements. Data inline
5097 * is enabled on per device basis, we can check
5098 * the first Tx queue only.
5100 * If device does not support VLAN insertion in WQE
5101 * and some queues are requested to perform VLAN
5102 * insertion offload than inline must be enabled.
5104 olx |= MLX5_TXOFF_CONFIG_INLINE;
5107 if (config->mps == MLX5_MPW_ENHANCED &&
5108 config->txq_inline_min <= 0) {
5110 * The NIC supports Enhanced Multi-Packet Write.
5111 * We do not support legacy MPW due to its
5112 * hardware related problems, so we just ignore
5113 * legacy MLX5_MPW settings. There should be no
5114 * minimal required inline data.
5116 olx |= MLX5_TXOFF_CONFIG_EMPW;
5118 if (tx_offloads & DEV_TX_OFFLOAD_MATCH_METADATA) {
5119 /* We should support Flow metadata. */
5120 olx |= MLX5_TXOFF_CONFIG_METADATA;
5123 * Scan the routines table to find the minimal
5124 * satisfying routine with requested offloads.
5126 m = RTE_DIM(txoff_func);
5127 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5130 tmp = txoff_func[i].olx;
5132 /* Meets requested offloads exactly.*/
5136 if ((tmp & olx) != olx) {
5137 /* Does not meet requested offloads at all. */
5140 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5141 /* Do not enable eMPW if not configured. */
5143 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5144 /* Do not enable inlining if not configured. */
5147 * Some routine meets the requirements.
5148 * Check whether it has minimal amount
5149 * of not requested offloads.
5151 tmp = __builtin_popcountl(tmp & ~olx);
5152 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5153 /* First or better match, save and continue. */
5159 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5160 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5161 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5162 /* Lighter not requested offload. */
5167 if (m >= RTE_DIM(txoff_func)) {
5168 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5169 " for requested offloads %04X",
5170 dev->data->port_id, olx);
5173 DRV_LOG(DEBUG, "port %u has selected Tx function"
5174 " supporting offloads %04X/%04X",
5175 dev->data->port_id, olx, txoff_func[m].olx);
5176 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5177 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5178 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5179 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5180 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5181 DRV_LOG(DEBUG, "\tSWP (software parser)");
5182 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5183 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5184 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5185 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5186 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5187 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5188 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5189 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5190 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW)
5191 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5192 return txoff_func[m].func;