4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5dv.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_mempool.h>
52 #include <rte_prefetch.h>
53 #include <rte_common.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_ether.h>
58 #include "mlx5_utils.h"
59 #include "mlx5_rxtx.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 static __rte_always_inline uint32_t
65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
67 static __rte_always_inline int
68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
69 uint16_t cqe_cnt, uint32_t *rss_hash);
71 static __rte_always_inline uint32_t
72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
75 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
79 * Build a table to translate Rx completion flags to packet type.
81 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
84 mlx5_set_ptype_table(void)
87 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
89 /* Last entry must not be overwritten, reserved for errored packet. */
90 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
91 (*p)[i] = RTE_PTYPE_UNKNOWN;
93 * The index to the array should have:
94 * bit[1:0] = l3_hdr_type
95 * bit[4:2] = l4_hdr_type
98 * bit[7] = outer_l3_type
101 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
102 RTE_PTYPE_L4_NONFRAG;
103 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
106 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
108 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
111 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
113 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
116 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
118 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
120 /* Repeat with outer_l3_type being set. Just in case. */
121 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
122 RTE_PTYPE_L4_NONFRAG;
123 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
124 RTE_PTYPE_L4_NONFRAG;
125 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
127 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
131 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
133 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
138 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
139 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L4_NONFRAG;
141 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L4_NONFRAG;
144 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
146 RTE_PTYPE_INNER_L4_NONFRAG;
147 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
149 RTE_PTYPE_INNER_L4_NONFRAG;
150 /* Tunneled - Fragmented */
151 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
152 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
153 RTE_PTYPE_INNER_L4_FRAG;
154 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
156 RTE_PTYPE_INNER_L4_FRAG;
157 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
159 RTE_PTYPE_INNER_L4_FRAG;
160 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
162 RTE_PTYPE_INNER_L4_FRAG;
164 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
165 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
167 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
170 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
173 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
178 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
183 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
192 * Return the size of tailroom of WQ.
195 * Pointer to TX queue structure.
197 * Pointer to tail of WQ.
203 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
206 tailroom = (uintptr_t)(txq->wqes) +
207 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
213 * Copy data to tailroom of circular queue.
216 * Pointer to destination.
220 * Number of bytes to copy.
222 * Pointer to head of queue.
224 * Size of tailroom from dst.
227 * Pointer after copied data.
230 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
231 void *base, size_t tailroom)
236 rte_memcpy(dst, src, tailroom);
237 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
239 ret = (uint8_t *)base + n - tailroom;
241 rte_memcpy(dst, src, n);
242 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
248 * DPDK callback to check the status of a tx descriptor.
253 * The index of the descriptor in the ring.
256 * The status of the tx descriptor.
259 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
261 struct mlx5_txq_data *txq = tx_queue;
264 mlx5_tx_complete(txq);
265 used = txq->elts_head - txq->elts_tail;
267 return RTE_ETH_TX_DESC_FULL;
268 return RTE_ETH_TX_DESC_DONE;
272 * DPDK callback to check the status of a rx descriptor.
277 * The index of the descriptor in the ring.
280 * The status of the tx descriptor.
283 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
285 struct mlx5_rxq_data *rxq = rx_queue;
286 struct rxq_zip *zip = &rxq->zip;
287 volatile struct mlx5_cqe *cqe;
288 const unsigned int cqe_n = (1 << rxq->cqe_n);
289 const unsigned int cqe_cnt = cqe_n - 1;
293 /* if we are processing a compressed cqe */
295 used = zip->cqe_cnt - zip->ca;
301 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
302 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
306 op_own = cqe->op_own;
307 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
308 n = rte_be_to_cpu_32(cqe->byte_cnt);
313 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
315 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
317 return RTE_ETH_RX_DESC_DONE;
318 return RTE_ETH_RX_DESC_AVAIL;
322 * DPDK callback for TX.
325 * Generic pointer to TX queue structure.
327 * Packets to transmit.
329 * Number of packets in array.
332 * Number of packets successfully transmitted (<= pkts_n).
335 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
337 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
338 uint16_t elts_head = txq->elts_head;
339 const uint16_t elts_n = 1 << txq->elts_n;
340 const uint16_t elts_m = elts_n - 1;
345 unsigned int max_inline = txq->max_inline;
346 const unsigned int inline_en = !!max_inline && txq->inline_en;
349 volatile struct mlx5_wqe_v *wqe = NULL;
350 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
351 unsigned int segs_n = 0;
352 struct rte_mbuf *buf = NULL;
355 if (unlikely(!pkts_n))
357 /* Prefetch first packet cacheline. */
358 rte_prefetch0(*pkts);
359 /* Start processing. */
360 mlx5_tx_complete(txq);
361 max_elts = (elts_n - (elts_head - txq->elts_tail));
362 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
363 if (unlikely(!max_wqe))
366 volatile rte_v128u32_t *dseg = NULL;
369 unsigned int sg = 0; /* counter of additional segs attached. */
372 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
373 uint16_t tso_header_sz = 0;
375 uint8_t cs_flags = 0;
377 uint16_t tso_segsz = 0;
378 #ifdef MLX5_PMD_SOFT_COUNTERS
379 uint32_t total_length = 0;
384 segs_n = buf->nb_segs;
386 * Make sure there is enough room to store this packet and
387 * that one ring entry remains unused.
390 if (max_elts < segs_n)
394 if (unlikely(--max_wqe == 0))
396 wqe = (volatile struct mlx5_wqe_v *)
397 tx_mlx5_wqe(txq, txq->wqe_ci);
398 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
400 rte_prefetch0(*(pkts + 1));
401 addr = rte_pktmbuf_mtod(buf, uintptr_t);
402 length = DATA_LEN(buf);
403 ehdr = (((uint8_t *)addr)[1] << 8) |
404 ((uint8_t *)addr)[0];
405 #ifdef MLX5_PMD_SOFT_COUNTERS
406 total_length = length;
408 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
409 txq->stats.oerrors++;
412 /* Update element. */
413 (*txq->elts)[elts_head & elts_m] = buf;
414 /* Prefetch next buffer data. */
417 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
418 /* Should we enable HW CKSUM offload */
420 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
421 const uint64_t is_tunneled = buf->ol_flags &
423 PKT_TX_TUNNEL_VXLAN);
425 if (is_tunneled && txq->tunnel_en) {
426 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
427 MLX5_ETH_WQE_L4_INNER_CSUM;
428 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
429 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
431 cs_flags = MLX5_ETH_WQE_L3_CSUM |
432 MLX5_ETH_WQE_L4_CSUM;
435 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
436 /* Replace the Ethernet type by the VLAN if necessary. */
437 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
438 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
440 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
444 /* Copy Destination and source mac address. */
445 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
447 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
448 /* Copy missing two bytes to end the DSeg. */
449 memcpy((uint8_t *)raw + len + sizeof(vlan),
450 ((uint8_t *)addr) + len, 2);
454 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
455 MLX5_WQE_DWORD_SIZE);
456 length -= pkt_inline_sz;
457 addr += pkt_inline_sz;
459 raw += MLX5_WQE_DWORD_SIZE;
461 tso = buf->ol_flags & PKT_TX_TCP_SEG;
463 uintptr_t end = (uintptr_t)
464 (((uintptr_t)txq->wqes) +
468 uint8_t vlan_sz = (buf->ol_flags &
469 PKT_TX_VLAN_PKT) ? 4 : 0;
470 const uint64_t is_tunneled =
473 PKT_TX_TUNNEL_VXLAN);
475 tso_header_sz = buf->l2_len + vlan_sz +
476 buf->l3_len + buf->l4_len;
477 tso_segsz = buf->tso_segsz;
478 if (unlikely(tso_segsz == 0)) {
479 txq->stats.oerrors++;
482 if (is_tunneled && txq->tunnel_en) {
483 tso_header_sz += buf->outer_l2_len +
485 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
487 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
489 if (unlikely(tso_header_sz >
490 MLX5_MAX_TSO_HEADER)) {
491 txq->stats.oerrors++;
494 copy_b = tso_header_sz - pkt_inline_sz;
495 /* First seg must contain all headers. */
496 assert(copy_b <= length);
498 ((end - (uintptr_t)raw) > copy_b)) {
499 uint16_t n = (MLX5_WQE_DS(copy_b) -
502 if (unlikely(max_wqe < n))
505 rte_memcpy((void *)raw,
506 (void *)addr, copy_b);
509 /* Include padding for TSO header. */
510 copy_b = MLX5_WQE_DS(copy_b) *
512 pkt_inline_sz += copy_b;
516 wqe->ctrl = (rte_v128u32_t){
531 /* Inline if enough room. */
532 if (inline_en || tso) {
534 uintptr_t end = (uintptr_t)
535 (((uintptr_t)txq->wqes) +
536 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
537 unsigned int inline_room = max_inline *
538 RTE_CACHE_LINE_SIZE -
539 (pkt_inline_sz - 2) -
541 uintptr_t addr_end = (addr + inline_room) &
542 ~(RTE_CACHE_LINE_SIZE - 1);
543 unsigned int copy_b = (addr_end > addr) ?
544 RTE_MIN((addr_end - addr), length) :
547 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
549 * One Dseg remains in the current WQE. To
550 * keep the computation positive, it is
551 * removed after the bytes to Dseg conversion.
553 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
555 if (unlikely(max_wqe < n))
560 rte_cpu_to_be_32(copy_b |
564 MLX5_WQE_DS(tso_header_sz) *
567 rte_memcpy((void *)raw,
568 (void *)&inl, sizeof(inl));
570 pkt_inline_sz += sizeof(inl);
572 rte_memcpy((void *)raw, (void *)addr, copy_b);
575 pkt_inline_sz += copy_b;
578 * 2 DWORDs consumed by the WQE header + ETH segment +
579 * the size of the inline part of the packet.
581 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
583 if (ds % (MLX5_WQE_SIZE /
584 MLX5_WQE_DWORD_SIZE) == 0) {
585 if (unlikely(--max_wqe == 0))
587 dseg = (volatile rte_v128u32_t *)
588 tx_mlx5_wqe(txq, txq->wqe_ci +
591 dseg = (volatile rte_v128u32_t *)
593 (ds * MLX5_WQE_DWORD_SIZE));
596 } else if (!segs_n) {
599 /* dseg will be advance as part of next_seg */
600 dseg = (volatile rte_v128u32_t *)
602 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
607 * No inline has been done in the packet, only the
608 * Ethernet Header as been stored.
610 dseg = (volatile rte_v128u32_t *)
611 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
614 /* Add the remaining packet as a simple ds. */
615 naddr = rte_cpu_to_be_64(addr);
616 *dseg = (rte_v128u32_t){
617 rte_cpu_to_be_32(length),
618 mlx5_tx_mb2mr(txq, buf),
631 * Spill on next WQE when the current one does not have
632 * enough room left. Size of WQE must a be a multiple
633 * of data segment size.
635 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
636 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
637 if (unlikely(--max_wqe == 0))
639 dseg = (volatile rte_v128u32_t *)
640 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
641 rte_prefetch0(tx_mlx5_wqe(txq,
642 txq->wqe_ci + ds / 4 + 1));
649 length = DATA_LEN(buf);
650 #ifdef MLX5_PMD_SOFT_COUNTERS
651 total_length += length;
653 /* Store segment information. */
654 naddr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
655 *dseg = (rte_v128u32_t){
656 rte_cpu_to_be_32(length),
657 mlx5_tx_mb2mr(txq, buf),
661 (*txq->elts)[++elts_head & elts_m] = buf;
663 /* Advance counter only if all segs are successfully posted. */
669 if (ds > MLX5_DSEG_MAX) {
670 txq->stats.oerrors++;
676 /* Initialize known and common part of the WQE structure. */
678 wqe->ctrl = (rte_v128u32_t){
679 rte_cpu_to_be_32((txq->wqe_ci << 8) |
681 rte_cpu_to_be_32(txq->qp_num_8s | ds),
685 wqe->eseg = (rte_v128u32_t){
687 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
689 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
692 wqe->ctrl = (rte_v128u32_t){
693 rte_cpu_to_be_32((txq->wqe_ci << 8) |
695 rte_cpu_to_be_32(txq->qp_num_8s | ds),
699 wqe->eseg = (rte_v128u32_t){
703 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
707 txq->wqe_ci += (ds + 3) / 4;
708 /* Save the last successful WQE for completion request */
709 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
710 #ifdef MLX5_PMD_SOFT_COUNTERS
711 /* Increment sent bytes counter. */
712 txq->stats.obytes += total_length;
714 } while (i < pkts_n);
715 /* Take a shortcut if nothing must be sent. */
716 if (unlikely((i + k) == 0))
718 txq->elts_head += (i + j);
719 /* Check whether completion threshold has been reached. */
720 comp = txq->elts_comp + i + j + k;
721 if (comp >= MLX5_TX_COMP_THRESH) {
722 /* Request completion on last WQE. */
723 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
724 /* Save elts_head in unused "immediate" field of WQE. */
725 last_wqe->ctrl3 = txq->elts_head;
728 txq->elts_comp = comp;
730 #ifdef MLX5_PMD_SOFT_COUNTERS
731 /* Increment sent packets counter. */
732 txq->stats.opackets += i;
734 /* Ring QP doorbell. */
735 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
740 * Open a MPW session.
743 * Pointer to TX queue structure.
745 * Pointer to MPW session structure.
750 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
752 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
753 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
754 (volatile struct mlx5_wqe_data_seg (*)[])
755 tx_mlx5_wqe(txq, idx + 1);
757 mpw->state = MLX5_MPW_STATE_OPENED;
761 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
762 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
763 mpw->wqe->eseg.inline_hdr_sz = 0;
764 mpw->wqe->eseg.rsvd0 = 0;
765 mpw->wqe->eseg.rsvd1 = 0;
766 mpw->wqe->eseg.rsvd2 = 0;
767 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
770 mpw->wqe->ctrl[2] = 0;
771 mpw->wqe->ctrl[3] = 0;
772 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
773 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
774 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
775 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
776 mpw->data.dseg[2] = &(*dseg)[0];
777 mpw->data.dseg[3] = &(*dseg)[1];
778 mpw->data.dseg[4] = &(*dseg)[2];
782 * Close a MPW session.
785 * Pointer to TX queue structure.
787 * Pointer to MPW session structure.
790 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
792 unsigned int num = mpw->pkts_n;
795 * Store size in multiple of 16 bytes. Control and Ethernet segments
798 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
799 mpw->state = MLX5_MPW_STATE_CLOSED;
804 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
805 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
809 * DPDK callback for TX with MPW support.
812 * Generic pointer to TX queue structure.
814 * Packets to transmit.
816 * Number of packets in array.
819 * Number of packets successfully transmitted (<= pkts_n).
822 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
824 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
825 uint16_t elts_head = txq->elts_head;
826 const uint16_t elts_n = 1 << txq->elts_n;
827 const uint16_t elts_m = elts_n - 1;
833 struct mlx5_mpw mpw = {
834 .state = MLX5_MPW_STATE_CLOSED,
837 if (unlikely(!pkts_n))
839 /* Prefetch first packet cacheline. */
840 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
841 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
842 /* Start processing. */
843 mlx5_tx_complete(txq);
844 max_elts = (elts_n - (elts_head - txq->elts_tail));
845 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
846 if (unlikely(!max_wqe))
849 struct rte_mbuf *buf = *(pkts++);
851 unsigned int segs_n = buf->nb_segs;
852 uint32_t cs_flags = 0;
855 * Make sure there is enough room to store this packet and
856 * that one ring entry remains unused.
859 if (max_elts < segs_n)
861 /* Do not bother with large packets MPW cannot handle. */
862 if (segs_n > MLX5_MPW_DSEG_MAX) {
863 txq->stats.oerrors++;
868 /* Should we enable HW CKSUM offload */
870 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
871 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
872 /* Retrieve packet information. */
873 length = PKT_LEN(buf);
875 /* Start new session if packet differs. */
876 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
877 ((mpw.len != length) ||
879 (mpw.wqe->eseg.cs_flags != cs_flags)))
880 mlx5_mpw_close(txq, &mpw);
881 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
883 * Multi-Packet WQE consumes at most two WQE.
884 * mlx5_mpw_new() expects to be able to use such
887 if (unlikely(max_wqe < 2))
890 mlx5_mpw_new(txq, &mpw, length);
891 mpw.wqe->eseg.cs_flags = cs_flags;
893 /* Multi-segment packets must be alone in their MPW. */
894 assert((segs_n == 1) || (mpw.pkts_n == 0));
895 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
899 volatile struct mlx5_wqe_data_seg *dseg;
903 (*txq->elts)[elts_head++ & elts_m] = buf;
904 dseg = mpw.data.dseg[mpw.pkts_n];
905 addr = rte_pktmbuf_mtod(buf, uintptr_t);
906 *dseg = (struct mlx5_wqe_data_seg){
907 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
908 .lkey = mlx5_tx_mb2mr(txq, buf),
909 .addr = rte_cpu_to_be_64(addr),
911 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
912 length += DATA_LEN(buf);
918 assert(length == mpw.len);
919 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
920 mlx5_mpw_close(txq, &mpw);
921 #ifdef MLX5_PMD_SOFT_COUNTERS
922 /* Increment sent bytes counter. */
923 txq->stats.obytes += length;
927 /* Take a shortcut if nothing must be sent. */
928 if (unlikely(i == 0))
930 /* Check whether completion threshold has been reached. */
931 /* "j" includes both packets and segments. */
932 comp = txq->elts_comp + j;
933 if (comp >= MLX5_TX_COMP_THRESH) {
934 volatile struct mlx5_wqe *wqe = mpw.wqe;
936 /* Request completion on last WQE. */
937 wqe->ctrl[2] = rte_cpu_to_be_32(8);
938 /* Save elts_head in unused "immediate" field of WQE. */
939 wqe->ctrl[3] = elts_head;
942 txq->elts_comp = comp;
944 #ifdef MLX5_PMD_SOFT_COUNTERS
945 /* Increment sent packets counter. */
946 txq->stats.opackets += i;
948 /* Ring QP doorbell. */
949 if (mpw.state == MLX5_MPW_STATE_OPENED)
950 mlx5_mpw_close(txq, &mpw);
951 mlx5_tx_dbrec(txq, mpw.wqe);
952 txq->elts_head = elts_head;
957 * Open a MPW inline session.
960 * Pointer to TX queue structure.
962 * Pointer to MPW session structure.
967 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
970 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
971 struct mlx5_wqe_inl_small *inl;
973 mpw->state = MLX5_MPW_INL_STATE_OPENED;
977 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
978 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
981 mpw->wqe->ctrl[2] = 0;
982 mpw->wqe->ctrl[3] = 0;
983 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
984 mpw->wqe->eseg.inline_hdr_sz = 0;
985 mpw->wqe->eseg.cs_flags = 0;
986 mpw->wqe->eseg.rsvd0 = 0;
987 mpw->wqe->eseg.rsvd1 = 0;
988 mpw->wqe->eseg.rsvd2 = 0;
989 inl = (struct mlx5_wqe_inl_small *)
990 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
991 mpw->data.raw = (uint8_t *)&inl->raw;
995 * Close a MPW inline session.
998 * Pointer to TX queue structure.
1000 * Pointer to MPW session structure.
1003 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1006 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1007 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1009 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1011 * Store size in multiple of 16 bytes. Control and Ethernet segments
1014 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1016 mpw->state = MLX5_MPW_STATE_CLOSED;
1017 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1018 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1022 * DPDK callback for TX with MPW inline support.
1025 * Generic pointer to TX queue structure.
1027 * Packets to transmit.
1029 * Number of packets in array.
1032 * Number of packets successfully transmitted (<= pkts_n).
1035 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1038 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1039 uint16_t elts_head = txq->elts_head;
1040 const uint16_t elts_n = 1 << txq->elts_n;
1041 const uint16_t elts_m = elts_n - 1;
1047 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1048 struct mlx5_mpw mpw = {
1049 .state = MLX5_MPW_STATE_CLOSED,
1052 * Compute the maximum number of WQE which can be consumed by inline
1055 * - 1 control segment,
1056 * - 1 Ethernet segment,
1057 * - N Dseg from the inline request.
1059 const unsigned int wqe_inl_n =
1060 ((2 * MLX5_WQE_DWORD_SIZE +
1061 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1062 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1064 if (unlikely(!pkts_n))
1066 /* Prefetch first packet cacheline. */
1067 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1068 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1069 /* Start processing. */
1070 mlx5_tx_complete(txq);
1071 max_elts = (elts_n - (elts_head - txq->elts_tail));
1073 struct rte_mbuf *buf = *(pkts++);
1076 unsigned int segs_n = buf->nb_segs;
1077 uint32_t cs_flags = 0;
1080 * Make sure there is enough room to store this packet and
1081 * that one ring entry remains unused.
1084 if (max_elts < segs_n)
1086 /* Do not bother with large packets MPW cannot handle. */
1087 if (segs_n > MLX5_MPW_DSEG_MAX) {
1088 txq->stats.oerrors++;
1094 * Compute max_wqe in case less WQE were consumed in previous
1097 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1098 /* Should we enable HW CKSUM offload */
1100 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1101 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1102 /* Retrieve packet information. */
1103 length = PKT_LEN(buf);
1104 /* Start new session if packet differs. */
1105 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1106 if ((mpw.len != length) ||
1108 (mpw.wqe->eseg.cs_flags != cs_flags))
1109 mlx5_mpw_close(txq, &mpw);
1110 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1111 if ((mpw.len != length) ||
1113 (length > inline_room) ||
1114 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1115 mlx5_mpw_inline_close(txq, &mpw);
1117 txq->max_inline * RTE_CACHE_LINE_SIZE;
1120 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1121 if ((segs_n != 1) ||
1122 (length > inline_room)) {
1124 * Multi-Packet WQE consumes at most two WQE.
1125 * mlx5_mpw_new() expects to be able to use
1128 if (unlikely(max_wqe < 2))
1131 mlx5_mpw_new(txq, &mpw, length);
1132 mpw.wqe->eseg.cs_flags = cs_flags;
1134 if (unlikely(max_wqe < wqe_inl_n))
1136 max_wqe -= wqe_inl_n;
1137 mlx5_mpw_inline_new(txq, &mpw, length);
1138 mpw.wqe->eseg.cs_flags = cs_flags;
1141 /* Multi-segment packets must be alone in their MPW. */
1142 assert((segs_n == 1) || (mpw.pkts_n == 0));
1143 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1144 assert(inline_room ==
1145 txq->max_inline * RTE_CACHE_LINE_SIZE);
1146 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1150 volatile struct mlx5_wqe_data_seg *dseg;
1153 (*txq->elts)[elts_head++ & elts_m] = buf;
1154 dseg = mpw.data.dseg[mpw.pkts_n];
1155 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1156 *dseg = (struct mlx5_wqe_data_seg){
1158 rte_cpu_to_be_32(DATA_LEN(buf)),
1159 .lkey = mlx5_tx_mb2mr(txq, buf),
1160 .addr = rte_cpu_to_be_64(addr),
1162 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1163 length += DATA_LEN(buf);
1169 assert(length == mpw.len);
1170 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1171 mlx5_mpw_close(txq, &mpw);
1175 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1176 assert(length <= inline_room);
1177 assert(length == DATA_LEN(buf));
1178 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1179 (*txq->elts)[elts_head++ & elts_m] = buf;
1180 /* Maximum number of bytes before wrapping. */
1181 max = ((((uintptr_t)(txq->wqes)) +
1184 (uintptr_t)mpw.data.raw);
1186 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1189 mpw.data.raw = (volatile void *)txq->wqes;
1190 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1191 (void *)(addr + max),
1193 mpw.data.raw += length - max;
1195 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1201 (volatile void *)txq->wqes;
1203 mpw.data.raw += length;
1206 mpw.total_len += length;
1208 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1209 mlx5_mpw_inline_close(txq, &mpw);
1211 txq->max_inline * RTE_CACHE_LINE_SIZE;
1213 inline_room -= length;
1216 #ifdef MLX5_PMD_SOFT_COUNTERS
1217 /* Increment sent bytes counter. */
1218 txq->stats.obytes += length;
1222 /* Take a shortcut if nothing must be sent. */
1223 if (unlikely(i == 0))
1225 /* Check whether completion threshold has been reached. */
1226 /* "j" includes both packets and segments. */
1227 comp = txq->elts_comp + j;
1228 if (comp >= MLX5_TX_COMP_THRESH) {
1229 volatile struct mlx5_wqe *wqe = mpw.wqe;
1231 /* Request completion on last WQE. */
1232 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1233 /* Save elts_head in unused "immediate" field of WQE. */
1234 wqe->ctrl[3] = elts_head;
1237 txq->elts_comp = comp;
1239 #ifdef MLX5_PMD_SOFT_COUNTERS
1240 /* Increment sent packets counter. */
1241 txq->stats.opackets += i;
1243 /* Ring QP doorbell. */
1244 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1245 mlx5_mpw_inline_close(txq, &mpw);
1246 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1247 mlx5_mpw_close(txq, &mpw);
1248 mlx5_tx_dbrec(txq, mpw.wqe);
1249 txq->elts_head = elts_head;
1254 * Open an Enhanced MPW session.
1257 * Pointer to TX queue structure.
1259 * Pointer to MPW session structure.
1264 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1266 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1268 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1270 mpw->total_len = sizeof(struct mlx5_wqe);
1271 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1273 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1274 (txq->wqe_ci << 8) |
1275 MLX5_OPCODE_ENHANCED_MPSW);
1276 mpw->wqe->ctrl[2] = 0;
1277 mpw->wqe->ctrl[3] = 0;
1278 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1279 if (unlikely(padding)) {
1280 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1282 /* Pad the first 2 DWORDs with zero-length inline header. */
1283 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1284 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1285 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1286 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1287 /* Start from the next WQEBB. */
1288 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1290 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1295 * Close an Enhanced MPW session.
1298 * Pointer to TX queue structure.
1300 * Pointer to MPW session structure.
1303 * Number of consumed WQEs.
1305 static inline uint16_t
1306 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1310 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1313 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1314 MLX5_WQE_DS(mpw->total_len));
1315 mpw->state = MLX5_MPW_STATE_CLOSED;
1316 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1322 * DPDK callback for TX with Enhanced MPW support.
1325 * Generic pointer to TX queue structure.
1327 * Packets to transmit.
1329 * Number of packets in array.
1332 * Number of packets successfully transmitted (<= pkts_n).
1335 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1337 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1338 uint16_t elts_head = txq->elts_head;
1339 const uint16_t elts_n = 1 << txq->elts_n;
1340 const uint16_t elts_m = elts_n - 1;
1345 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1346 unsigned int mpw_room = 0;
1347 unsigned int inl_pad = 0;
1349 struct mlx5_mpw mpw = {
1350 .state = MLX5_MPW_STATE_CLOSED,
1353 if (unlikely(!pkts_n))
1355 /* Start processing. */
1356 mlx5_tx_complete(txq);
1357 max_elts = (elts_n - (elts_head - txq->elts_tail));
1358 /* A CQE slot must always be available. */
1359 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1360 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1361 if (unlikely(!max_wqe))
1364 struct rte_mbuf *buf = *(pkts++);
1368 unsigned int do_inline = 0; /* Whether inline is possible. */
1370 unsigned int segs_n = buf->nb_segs;
1371 uint32_t cs_flags = 0;
1374 * Make sure there is enough room to store this packet and
1375 * that one ring entry remains unused.
1378 if (max_elts - j < segs_n)
1380 /* Do not bother with large packets MPW cannot handle. */
1381 if (segs_n > MLX5_MPW_DSEG_MAX) {
1382 txq->stats.oerrors++;
1385 /* Should we enable HW CKSUM offload. */
1387 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1388 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1389 /* Retrieve packet information. */
1390 length = PKT_LEN(buf);
1391 /* Start new session if:
1392 * - multi-segment packet
1393 * - no space left even for a dseg
1394 * - next packet can be inlined with a new WQE
1396 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1399 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1400 if ((segs_n != 1) ||
1401 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1403 (length <= txq->inline_max_packet_sz &&
1404 inl_pad + sizeof(inl_hdr) + length >
1406 (mpw.wqe->eseg.cs_flags != cs_flags))
1407 max_wqe -= mlx5_empw_close(txq, &mpw);
1409 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1410 if (unlikely(segs_n != 1)) {
1411 /* Fall back to legacy MPW.
1412 * A MPW session consumes 2 WQEs at most to
1413 * include MLX5_MPW_DSEG_MAX pointers.
1415 if (unlikely(max_wqe < 2))
1417 mlx5_mpw_new(txq, &mpw, length);
1419 /* In Enhanced MPW, inline as much as the budget
1420 * is allowed. The remaining space is to be
1421 * filled with dsegs. If the title WQEBB isn't
1422 * padded, it will have 2 dsegs there.
1424 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1425 (max_inline ? max_inline :
1426 pkts_n * MLX5_WQE_DWORD_SIZE) +
1428 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1431 /* Don't pad the title WQEBB to not waste WQ. */
1432 mlx5_empw_new(txq, &mpw, 0);
1433 mpw_room -= mpw.total_len;
1436 length <= txq->inline_max_packet_sz &&
1437 sizeof(inl_hdr) + length <= mpw_room &&
1440 mpw.wqe->eseg.cs_flags = cs_flags;
1442 /* Evaluate whether the next packet can be inlined.
1443 * Inlininig is possible when:
1444 * - length is less than configured value
1445 * - length fits for remaining space
1446 * - not required to fill the title WQEBB with dsegs
1449 length <= txq->inline_max_packet_sz &&
1450 inl_pad + sizeof(inl_hdr) + length <=
1452 (!txq->mpw_hdr_dseg ||
1453 mpw.total_len >= MLX5_WQE_SIZE);
1455 /* Multi-segment packets must be alone in their MPW. */
1456 assert((segs_n == 1) || (mpw.pkts_n == 0));
1457 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1458 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1462 volatile struct mlx5_wqe_data_seg *dseg;
1465 (*txq->elts)[elts_head++ & elts_m] = buf;
1466 dseg = mpw.data.dseg[mpw.pkts_n];
1467 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1468 *dseg = (struct mlx5_wqe_data_seg){
1469 .byte_count = rte_cpu_to_be_32(
1471 .lkey = mlx5_tx_mb2mr(txq, buf),
1472 .addr = rte_cpu_to_be_64(addr),
1474 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1475 length += DATA_LEN(buf);
1481 /* A multi-segmented packet takes one MPW session.
1482 * TODO: Pack more multi-segmented packets if possible.
1484 mlx5_mpw_close(txq, &mpw);
1489 } else if (do_inline) {
1490 /* Inline packet into WQE. */
1493 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1494 assert(length == DATA_LEN(buf));
1495 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1496 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1497 mpw.data.raw = (volatile void *)
1498 ((uintptr_t)mpw.data.raw + inl_pad);
1499 max = tx_mlx5_wq_tailroom(txq,
1500 (void *)(uintptr_t)mpw.data.raw);
1501 /* Copy inline header. */
1502 mpw.data.raw = (volatile void *)
1504 (void *)(uintptr_t)mpw.data.raw,
1507 (void *)(uintptr_t)txq->wqes,
1509 max = tx_mlx5_wq_tailroom(txq,
1510 (void *)(uintptr_t)mpw.data.raw);
1511 /* Copy packet data. */
1512 mpw.data.raw = (volatile void *)
1514 (void *)(uintptr_t)mpw.data.raw,
1517 (void *)(uintptr_t)txq->wqes,
1520 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1521 /* No need to get completion as the entire packet is
1522 * copied to WQ. Free the buf right away.
1524 rte_pktmbuf_free_seg(buf);
1525 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1526 /* Add pad in the next packet if any. */
1527 inl_pad = (((uintptr_t)mpw.data.raw +
1528 (MLX5_WQE_DWORD_SIZE - 1)) &
1529 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1530 (uintptr_t)mpw.data.raw;
1532 /* No inline. Load a dseg of packet pointer. */
1533 volatile rte_v128u32_t *dseg;
1535 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1536 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1537 assert(length == DATA_LEN(buf));
1538 if (!tx_mlx5_wq_tailroom(txq,
1539 (void *)((uintptr_t)mpw.data.raw
1541 dseg = (volatile void *)txq->wqes;
1543 dseg = (volatile void *)
1544 ((uintptr_t)mpw.data.raw +
1546 (*txq->elts)[elts_head++ & elts_m] = buf;
1547 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1548 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1549 rte_prefetch2((void *)(addr +
1550 n * RTE_CACHE_LINE_SIZE));
1551 naddr = rte_cpu_to_be_64(addr);
1552 *dseg = (rte_v128u32_t) {
1553 rte_cpu_to_be_32(length),
1554 mlx5_tx_mb2mr(txq, buf),
1558 mpw.data.raw = (volatile void *)(dseg + 1);
1559 mpw.total_len += (inl_pad + sizeof(*dseg));
1562 mpw_room -= (inl_pad + sizeof(*dseg));
1565 #ifdef MLX5_PMD_SOFT_COUNTERS
1566 /* Increment sent bytes counter. */
1567 txq->stats.obytes += length;
1570 } while (i < pkts_n);
1571 /* Take a shortcut if nothing must be sent. */
1572 if (unlikely(i == 0))
1574 /* Check whether completion threshold has been reached. */
1575 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1576 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1577 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1578 volatile struct mlx5_wqe *wqe = mpw.wqe;
1580 /* Request completion on last WQE. */
1581 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1582 /* Save elts_head in unused "immediate" field of WQE. */
1583 wqe->ctrl[3] = elts_head;
1585 txq->mpw_comp = txq->wqe_ci;
1588 txq->elts_comp += j;
1590 #ifdef MLX5_PMD_SOFT_COUNTERS
1591 /* Increment sent packets counter. */
1592 txq->stats.opackets += i;
1594 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1595 mlx5_empw_close(txq, &mpw);
1596 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1597 mlx5_mpw_close(txq, &mpw);
1598 /* Ring QP doorbell. */
1599 mlx5_tx_dbrec(txq, mpw.wqe);
1600 txq->elts_head = elts_head;
1605 * Translate RX completion flags to packet type.
1610 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1613 * Packet type for struct rte_mbuf.
1615 static inline uint32_t
1616 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1619 uint8_t pinfo = cqe->pkt_info;
1620 uint16_t ptype = cqe->hdr_type_etc;
1623 * The index to the array should have:
1624 * bit[1:0] = l3_hdr_type
1625 * bit[4:2] = l4_hdr_type
1628 * bit[7] = outer_l3_type
1630 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1631 return mlx5_ptype_table[idx];
1635 * Get size of the next packet for a given CQE. For compressed CQEs, the
1636 * consumer index is updated only once all packets of the current one have
1640 * Pointer to RX queue.
1643 * @param[out] rss_hash
1644 * Packet RSS Hash result.
1647 * Packet size in bytes (0 if there is none), -1 in case of completion
1651 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1652 uint16_t cqe_cnt, uint32_t *rss_hash)
1654 struct rxq_zip *zip = &rxq->zip;
1655 uint16_t cqe_n = cqe_cnt + 1;
1659 /* Process compressed data in the CQE and mini arrays. */
1661 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1662 (volatile struct mlx5_mini_cqe8 (*)[8])
1663 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1665 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1666 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1667 if ((++zip->ai & 7) == 0) {
1668 /* Invalidate consumed CQEs */
1671 while (idx != end) {
1672 (*rxq->cqes)[idx & cqe_cnt].op_own =
1673 MLX5_CQE_INVALIDATE;
1677 * Increment consumer index to skip the number of
1678 * CQEs consumed. Hardware leaves holes in the CQ
1679 * ring for software use.
1684 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1685 /* Invalidate the rest */
1689 while (idx != end) {
1690 (*rxq->cqes)[idx & cqe_cnt].op_own =
1691 MLX5_CQE_INVALIDATE;
1694 rxq->cq_ci = zip->cq_ci;
1697 /* No compressed data, get next CQE and verify if it is compressed. */
1702 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1703 if (unlikely(ret == 1))
1706 op_own = cqe->op_own;
1707 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1708 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1709 (volatile struct mlx5_mini_cqe8 (*)[8])
1710 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1713 /* Fix endianness. */
1714 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1716 * Current mini array position is the one returned by
1719 * If completion comprises several mini arrays, as a
1720 * special case the second one is located 7 CQEs after
1721 * the initial CQE instead of 8 for subsequent ones.
1723 zip->ca = rxq->cq_ci;
1724 zip->na = zip->ca + 7;
1725 /* Compute the next non compressed CQE. */
1727 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1728 /* Get packet size to return. */
1729 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1730 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1732 /* Prefetch all the entries to be invalidated */
1735 while (idx != end) {
1736 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1740 len = rte_be_to_cpu_32(cqe->byte_cnt);
1741 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1743 /* Error while receiving packet. */
1744 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1751 * Translate RX completion flags to offload flags.
1754 * Pointer to RX queue structure.
1759 * Offload flags (ol_flags) for struct rte_mbuf.
1761 static inline uint32_t
1762 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1764 uint32_t ol_flags = 0;
1765 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1769 MLX5_CQE_RX_L3_HDR_VALID,
1770 PKT_RX_IP_CKSUM_GOOD) |
1772 MLX5_CQE_RX_L4_HDR_VALID,
1773 PKT_RX_L4_CKSUM_GOOD);
1774 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1777 MLX5_CQE_RX_L3_HDR_VALID,
1778 PKT_RX_IP_CKSUM_GOOD) |
1780 MLX5_CQE_RX_L4_HDR_VALID,
1781 PKT_RX_L4_CKSUM_GOOD);
1786 * DPDK callback for RX.
1789 * Generic pointer to RX queue structure.
1791 * Array to store received packets.
1793 * Maximum number of packets in array.
1796 * Number of packets successfully received (<= pkts_n).
1799 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1801 struct mlx5_rxq_data *rxq = dpdk_rxq;
1802 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1803 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1804 const unsigned int sges_n = rxq->sges_n;
1805 struct rte_mbuf *pkt = NULL;
1806 struct rte_mbuf *seg = NULL;
1807 volatile struct mlx5_cqe *cqe =
1808 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1810 unsigned int rq_ci = rxq->rq_ci << sges_n;
1811 int len = 0; /* keep its value across iterations. */
1814 unsigned int idx = rq_ci & wqe_cnt;
1815 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1816 struct rte_mbuf *rep = (*rxq->elts)[idx];
1817 uint32_t rss_hash_res = 0;
1825 rep = rte_mbuf_raw_alloc(rxq->mp);
1826 if (unlikely(rep == NULL)) {
1827 ++rxq->stats.rx_nombuf;
1830 * no buffers before we even started,
1831 * bail out silently.
1835 while (pkt != seg) {
1836 assert(pkt != (*rxq->elts)[idx]);
1840 rte_mbuf_raw_free(pkt);
1846 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1847 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1850 rte_mbuf_raw_free(rep);
1853 if (unlikely(len == -1)) {
1854 /* RX error, packet is likely too large. */
1855 rte_mbuf_raw_free(rep);
1856 ++rxq->stats.idropped;
1860 assert(len >= (rxq->crc_present << 2));
1861 /* Update packet information. */
1862 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1864 if (rss_hash_res && rxq->rss_hash) {
1865 pkt->hash.rss = rss_hash_res;
1866 pkt->ol_flags = PKT_RX_RSS_HASH;
1869 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1870 pkt->ol_flags |= PKT_RX_FDIR;
1871 if (cqe->sop_drop_qpn !=
1872 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1873 uint32_t mark = cqe->sop_drop_qpn;
1875 pkt->ol_flags |= PKT_RX_FDIR_ID;
1877 mlx5_flow_mark_get(mark);
1880 if (rxq->csum | rxq->csum_l2tun)
1881 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1882 if (rxq->vlan_strip &&
1883 (cqe->hdr_type_etc &
1884 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1885 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1886 PKT_RX_VLAN_STRIPPED;
1888 rte_be_to_cpu_16(cqe->vlan_info);
1890 if (rxq->crc_present)
1891 len -= ETHER_CRC_LEN;
1894 DATA_LEN(rep) = DATA_LEN(seg);
1895 PKT_LEN(rep) = PKT_LEN(seg);
1896 SET_DATA_OFF(rep, DATA_OFF(seg));
1897 PORT(rep) = PORT(seg);
1898 (*rxq->elts)[idx] = rep;
1900 * Fill NIC descriptor with the new buffer. The lkey and size
1901 * of the buffers are already known, only the buffer address
1904 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1905 if (len > DATA_LEN(seg)) {
1906 len -= DATA_LEN(seg);
1911 DATA_LEN(seg) = len;
1912 #ifdef MLX5_PMD_SOFT_COUNTERS
1913 /* Increment bytes counter. */
1914 rxq->stats.ibytes += PKT_LEN(pkt);
1916 /* Return packet. */
1922 /* Align consumer index to the next stride. */
1927 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1929 /* Update the consumer index. */
1930 rxq->rq_ci = rq_ci >> sges_n;
1932 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1934 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1935 #ifdef MLX5_PMD_SOFT_COUNTERS
1936 /* Increment packets counter. */
1937 rxq->stats.ipackets += i;
1943 * Dummy DPDK callback for TX.
1945 * This function is used to temporarily replace the real callback during
1946 * unsafe control operations on the queue, or in case of error.
1949 * Generic pointer to TX queue structure.
1951 * Packets to transmit.
1953 * Number of packets in array.
1956 * Number of packets successfully transmitted (<= pkts_n).
1959 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1968 * Dummy DPDK callback for RX.
1970 * This function is used to temporarily replace the real callback during
1971 * unsafe control operations on the queue, or in case of error.
1974 * Generic pointer to RX queue structure.
1976 * Array to store received packets.
1978 * Maximum number of packets in array.
1981 * Number of packets successfully received (<= pkts_n).
1984 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1993 * Vectorized Rx/Tx routines are not compiled in when required vector
1994 * instructions are not supported on a target architecture. The following null
1995 * stubs are needed for linkage when those are not included outside of this file
1996 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1999 uint16_t __attribute__((weak))
2000 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2008 uint16_t __attribute__((weak))
2009 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2017 uint16_t __attribute__((weak))
2018 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2026 int __attribute__((weak))
2027 priv_check_raw_vec_tx_support(struct priv *priv)
2033 int __attribute__((weak))
2034 priv_check_vec_tx_support(struct priv *priv)
2040 int __attribute__((weak))
2041 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2047 int __attribute__((weak))
2048 priv_check_vec_rx_support(struct priv *priv)