4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5dv.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_mempool.h>
52 #include <rte_prefetch.h>
53 #include <rte_common.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_ether.h>
58 #include "mlx5_utils.h"
59 #include "mlx5_rxtx.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 static __rte_always_inline uint32_t
65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
67 static __rte_always_inline int
68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
69 uint16_t cqe_cnt, uint32_t *rss_hash);
71 static __rte_always_inline uint32_t
72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
75 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
79 * Build a table to translate Rx completion flags to packet type.
81 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
84 mlx5_set_ptype_table(void)
87 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
89 /* Last entry must not be overwritten, reserved for errored packet. */
90 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
91 (*p)[i] = RTE_PTYPE_UNKNOWN;
93 * The index to the array should have:
94 * bit[1:0] = l3_hdr_type
95 * bit[4:2] = l4_hdr_type
98 * bit[7] = outer_l3_type
101 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
103 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
108 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 /* Repeat with outer_l3_type being set. Just in case. */
123 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 RTE_PTYPE_L4_NONFRAG;
125 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 RTE_PTYPE_L4_NONFRAG;
127 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
131 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
133 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
137 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_NONFRAG;
143 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_NONFRAG;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
179 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L4_UDP;
182 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L4_UDP;
185 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L4_UDP;
188 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L4_UDP;
194 * Return the size of tailroom of WQ.
197 * Pointer to TX queue structure.
199 * Pointer to tail of WQ.
205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
208 tailroom = (uintptr_t)(txq->wqes) +
209 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
215 * Copy data to tailroom of circular queue.
218 * Pointer to destination.
222 * Number of bytes to copy.
224 * Pointer to head of queue.
226 * Size of tailroom from dst.
229 * Pointer after copied data.
232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
233 void *base, size_t tailroom)
238 rte_memcpy(dst, src, tailroom);
239 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
241 ret = (uint8_t *)base + n - tailroom;
243 rte_memcpy(dst, src, n);
244 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
250 * DPDK callback to check the status of a tx descriptor.
255 * The index of the descriptor in the ring.
258 * The status of the tx descriptor.
261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
263 struct mlx5_txq_data *txq = tx_queue;
266 mlx5_tx_complete(txq);
267 used = txq->elts_head - txq->elts_tail;
269 return RTE_ETH_TX_DESC_FULL;
270 return RTE_ETH_TX_DESC_DONE;
274 * DPDK callback to check the status of a rx descriptor.
279 * The index of the descriptor in the ring.
282 * The status of the tx descriptor.
285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
287 struct mlx5_rxq_data *rxq = rx_queue;
288 struct rxq_zip *zip = &rxq->zip;
289 volatile struct mlx5_cqe *cqe;
290 const unsigned int cqe_n = (1 << rxq->cqe_n);
291 const unsigned int cqe_cnt = cqe_n - 1;
295 /* if we are processing a compressed cqe */
297 used = zip->cqe_cnt - zip->ca;
303 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
304 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
308 op_own = cqe->op_own;
309 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
310 n = rte_be_to_cpu_32(cqe->byte_cnt);
315 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
317 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
319 return RTE_ETH_RX_DESC_DONE;
320 return RTE_ETH_RX_DESC_AVAIL;
324 * DPDK callback for TX.
327 * Generic pointer to TX queue structure.
329 * Packets to transmit.
331 * Number of packets in array.
334 * Number of packets successfully transmitted (<= pkts_n).
337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
339 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
340 uint16_t elts_head = txq->elts_head;
341 const uint16_t elts_n = 1 << txq->elts_n;
342 const uint16_t elts_m = elts_n - 1;
349 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
350 unsigned int segs_n = 0;
351 const unsigned int max_inline = txq->max_inline;
353 if (unlikely(!pkts_n))
355 /* Prefetch first packet cacheline. */
356 rte_prefetch0(*pkts);
357 /* Start processing. */
358 mlx5_tx_complete(txq);
359 max_elts = (elts_n - (elts_head - txq->elts_tail));
360 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
361 if (unlikely(!max_wqe))
364 struct rte_mbuf *buf = NULL;
366 volatile struct mlx5_wqe_v *wqe = NULL;
367 volatile rte_v128u32_t *dseg = NULL;
370 unsigned int sg = 0; /* counter of additional segs attached. */
372 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
373 uint16_t tso_header_sz = 0;
377 uint16_t tso_segsz = 0;
378 #ifdef MLX5_PMD_SOFT_COUNTERS
379 uint32_t total_length = 0;
384 segs_n = buf->nb_segs;
386 * Make sure there is enough room to store this packet and
387 * that one ring entry remains unused.
390 if (max_elts < segs_n)
394 if (unlikely(--max_wqe == 0))
396 wqe = (volatile struct mlx5_wqe_v *)
397 tx_mlx5_wqe(txq, txq->wqe_ci);
398 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
400 rte_prefetch0(*(pkts + 1));
401 addr = rte_pktmbuf_mtod(buf, uintptr_t);
402 length = DATA_LEN(buf);
403 ehdr = (((uint8_t *)addr)[1] << 8) |
404 ((uint8_t *)addr)[0];
405 #ifdef MLX5_PMD_SOFT_COUNTERS
406 total_length = length;
408 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
409 txq->stats.oerrors++;
412 /* Update element. */
413 (*txq->elts)[elts_head & elts_m] = buf;
414 /* Prefetch next buffer data. */
417 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
418 cs_flags = txq_ol_cksum_to_cs(txq, buf);
419 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
420 /* Replace the Ethernet type by the VLAN if necessary. */
421 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
422 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
424 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
428 /* Copy Destination and source mac address. */
429 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
431 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
432 /* Copy missing two bytes to end the DSeg. */
433 memcpy((uint8_t *)raw + len + sizeof(vlan),
434 ((uint8_t *)addr) + len, 2);
438 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
439 MLX5_WQE_DWORD_SIZE);
440 length -= pkt_inline_sz;
441 addr += pkt_inline_sz;
443 raw += MLX5_WQE_DWORD_SIZE;
445 tso = buf->ol_flags & PKT_TX_TCP_SEG;
447 uintptr_t end = (uintptr_t)
448 (((uintptr_t)txq->wqes) +
452 uint8_t vlan_sz = (buf->ol_flags &
453 PKT_TX_VLAN_PKT) ? 4 : 0;
454 const uint64_t is_tunneled =
457 PKT_TX_TUNNEL_VXLAN);
459 tso_header_sz = buf->l2_len + vlan_sz +
460 buf->l3_len + buf->l4_len;
461 tso_segsz = buf->tso_segsz;
462 if (unlikely(tso_segsz == 0)) {
463 txq->stats.oerrors++;
466 if (is_tunneled && txq->tunnel_en) {
467 tso_header_sz += buf->outer_l2_len +
469 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
471 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
473 if (unlikely(tso_header_sz >
474 MLX5_MAX_TSO_HEADER)) {
475 txq->stats.oerrors++;
478 copy_b = tso_header_sz - pkt_inline_sz;
479 /* First seg must contain all headers. */
480 assert(copy_b <= length);
482 ((end - (uintptr_t)raw) > copy_b)) {
483 uint16_t n = (MLX5_WQE_DS(copy_b) -
486 if (unlikely(max_wqe < n))
489 rte_memcpy((void *)raw,
490 (void *)addr, copy_b);
493 /* Include padding for TSO header. */
494 copy_b = MLX5_WQE_DS(copy_b) *
496 pkt_inline_sz += copy_b;
500 wqe->ctrl = (rte_v128u32_t){
509 #ifdef MLX5_PMD_SOFT_COUNTERS
517 /* Inline if enough room. */
518 if (max_inline || tso) {
520 uintptr_t end = (uintptr_t)
521 (((uintptr_t)txq->wqes) +
522 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
523 unsigned int inline_room = max_inline *
524 RTE_CACHE_LINE_SIZE -
525 (pkt_inline_sz - 2) -
527 uintptr_t addr_end = (addr + inline_room) &
528 ~(RTE_CACHE_LINE_SIZE - 1);
529 unsigned int copy_b = (addr_end > addr) ?
530 RTE_MIN((addr_end - addr), length) :
533 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
535 * One Dseg remains in the current WQE. To
536 * keep the computation positive, it is
537 * removed after the bytes to Dseg conversion.
539 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
541 if (unlikely(max_wqe < n))
545 inl = rte_cpu_to_be_32(copy_b |
547 rte_memcpy((void *)raw,
548 (void *)&inl, sizeof(inl));
550 pkt_inline_sz += sizeof(inl);
552 rte_memcpy((void *)raw, (void *)addr, copy_b);
555 pkt_inline_sz += copy_b;
558 * 2 DWORDs consumed by the WQE header + ETH segment +
559 * the size of the inline part of the packet.
561 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
563 if (ds % (MLX5_WQE_SIZE /
564 MLX5_WQE_DWORD_SIZE) == 0) {
565 if (unlikely(--max_wqe == 0))
567 dseg = (volatile rte_v128u32_t *)
568 tx_mlx5_wqe(txq, txq->wqe_ci +
571 dseg = (volatile rte_v128u32_t *)
573 (ds * MLX5_WQE_DWORD_SIZE));
576 } else if (!segs_n) {
579 /* dseg will be advance as part of next_seg */
580 dseg = (volatile rte_v128u32_t *)
582 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
587 * No inline has been done in the packet, only the
588 * Ethernet Header as been stored.
590 dseg = (volatile rte_v128u32_t *)
591 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
594 /* Add the remaining packet as a simple ds. */
595 addr = rte_cpu_to_be_64(addr);
596 *dseg = (rte_v128u32_t){
597 rte_cpu_to_be_32(length),
598 mlx5_tx_mb2mr(txq, buf),
611 * Spill on next WQE when the current one does not have
612 * enough room left. Size of WQE must a be a multiple
613 * of data segment size.
615 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
616 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
617 if (unlikely(--max_wqe == 0))
619 dseg = (volatile rte_v128u32_t *)
620 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
621 rte_prefetch0(tx_mlx5_wqe(txq,
622 txq->wqe_ci + ds / 4 + 1));
629 length = DATA_LEN(buf);
630 #ifdef MLX5_PMD_SOFT_COUNTERS
631 total_length += length;
633 /* Store segment information. */
634 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
635 *dseg = (rte_v128u32_t){
636 rte_cpu_to_be_32(length),
637 mlx5_tx_mb2mr(txq, buf),
641 (*txq->elts)[++elts_head & elts_m] = buf;
643 /* Advance counter only if all segs are successfully posted. */
649 if (ds > MLX5_DSEG_MAX) {
650 txq->stats.oerrors++;
656 /* Initialize known and common part of the WQE structure. */
658 wqe->ctrl = (rte_v128u32_t){
659 rte_cpu_to_be_32((txq->wqe_ci << 8) |
661 rte_cpu_to_be_32(txq->qp_num_8s | ds),
665 wqe->eseg = (rte_v128u32_t){
667 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
669 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
672 wqe->ctrl = (rte_v128u32_t){
673 rte_cpu_to_be_32((txq->wqe_ci << 8) |
675 rte_cpu_to_be_32(txq->qp_num_8s | ds),
679 wqe->eseg = (rte_v128u32_t){
683 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
687 txq->wqe_ci += (ds + 3) / 4;
688 /* Save the last successful WQE for completion request */
689 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
690 #ifdef MLX5_PMD_SOFT_COUNTERS
691 /* Increment sent bytes counter. */
692 txq->stats.obytes += total_length;
694 } while (i < pkts_n);
695 /* Take a shortcut if nothing must be sent. */
696 if (unlikely((i + k) == 0))
698 txq->elts_head += (i + j);
699 /* Check whether completion threshold has been reached. */
700 comp = txq->elts_comp + i + j + k;
701 if (comp >= MLX5_TX_COMP_THRESH) {
702 /* Request completion on last WQE. */
703 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
704 /* Save elts_head in unused "immediate" field of WQE. */
705 last_wqe->ctrl3 = txq->elts_head;
708 txq->elts_comp = comp;
710 #ifdef MLX5_PMD_SOFT_COUNTERS
711 /* Increment sent packets counter. */
712 txq->stats.opackets += i;
714 /* Ring QP doorbell. */
715 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
720 * Open a MPW session.
723 * Pointer to TX queue structure.
725 * Pointer to MPW session structure.
730 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
732 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
733 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
734 (volatile struct mlx5_wqe_data_seg (*)[])
735 tx_mlx5_wqe(txq, idx + 1);
737 mpw->state = MLX5_MPW_STATE_OPENED;
741 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
742 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
743 mpw->wqe->eseg.inline_hdr_sz = 0;
744 mpw->wqe->eseg.rsvd0 = 0;
745 mpw->wqe->eseg.rsvd1 = 0;
746 mpw->wqe->eseg.rsvd2 = 0;
747 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
750 mpw->wqe->ctrl[2] = 0;
751 mpw->wqe->ctrl[3] = 0;
752 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
753 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
754 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
755 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
756 mpw->data.dseg[2] = &(*dseg)[0];
757 mpw->data.dseg[3] = &(*dseg)[1];
758 mpw->data.dseg[4] = &(*dseg)[2];
762 * Close a MPW session.
765 * Pointer to TX queue structure.
767 * Pointer to MPW session structure.
770 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
772 unsigned int num = mpw->pkts_n;
775 * Store size in multiple of 16 bytes. Control and Ethernet segments
778 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
779 mpw->state = MLX5_MPW_STATE_CLOSED;
784 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
785 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
789 * DPDK callback for TX with MPW support.
792 * Generic pointer to TX queue structure.
794 * Packets to transmit.
796 * Number of packets in array.
799 * Number of packets successfully transmitted (<= pkts_n).
802 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
804 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
805 uint16_t elts_head = txq->elts_head;
806 const uint16_t elts_n = 1 << txq->elts_n;
807 const uint16_t elts_m = elts_n - 1;
813 struct mlx5_mpw mpw = {
814 .state = MLX5_MPW_STATE_CLOSED,
817 if (unlikely(!pkts_n))
819 /* Prefetch first packet cacheline. */
820 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
821 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
822 /* Start processing. */
823 mlx5_tx_complete(txq);
824 max_elts = (elts_n - (elts_head - txq->elts_tail));
825 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
826 if (unlikely(!max_wqe))
829 struct rte_mbuf *buf = *(pkts++);
831 unsigned int segs_n = buf->nb_segs;
835 * Make sure there is enough room to store this packet and
836 * that one ring entry remains unused.
839 if (max_elts < segs_n)
841 /* Do not bother with large packets MPW cannot handle. */
842 if (segs_n > MLX5_MPW_DSEG_MAX) {
843 txq->stats.oerrors++;
848 cs_flags = txq_ol_cksum_to_cs(txq, buf);
849 /* Retrieve packet information. */
850 length = PKT_LEN(buf);
852 /* Start new session if packet differs. */
853 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
854 ((mpw.len != length) ||
856 (mpw.wqe->eseg.cs_flags != cs_flags)))
857 mlx5_mpw_close(txq, &mpw);
858 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
860 * Multi-Packet WQE consumes at most two WQE.
861 * mlx5_mpw_new() expects to be able to use such
864 if (unlikely(max_wqe < 2))
867 mlx5_mpw_new(txq, &mpw, length);
868 mpw.wqe->eseg.cs_flags = cs_flags;
870 /* Multi-segment packets must be alone in their MPW. */
871 assert((segs_n == 1) || (mpw.pkts_n == 0));
872 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
876 volatile struct mlx5_wqe_data_seg *dseg;
880 (*txq->elts)[elts_head++ & elts_m] = buf;
881 dseg = mpw.data.dseg[mpw.pkts_n];
882 addr = rte_pktmbuf_mtod(buf, uintptr_t);
883 *dseg = (struct mlx5_wqe_data_seg){
884 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
885 .lkey = mlx5_tx_mb2mr(txq, buf),
886 .addr = rte_cpu_to_be_64(addr),
888 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
889 length += DATA_LEN(buf);
895 assert(length == mpw.len);
896 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
897 mlx5_mpw_close(txq, &mpw);
898 #ifdef MLX5_PMD_SOFT_COUNTERS
899 /* Increment sent bytes counter. */
900 txq->stats.obytes += length;
904 /* Take a shortcut if nothing must be sent. */
905 if (unlikely(i == 0))
907 /* Check whether completion threshold has been reached. */
908 /* "j" includes both packets and segments. */
909 comp = txq->elts_comp + j;
910 if (comp >= MLX5_TX_COMP_THRESH) {
911 volatile struct mlx5_wqe *wqe = mpw.wqe;
913 /* Request completion on last WQE. */
914 wqe->ctrl[2] = rte_cpu_to_be_32(8);
915 /* Save elts_head in unused "immediate" field of WQE. */
916 wqe->ctrl[3] = elts_head;
919 txq->elts_comp = comp;
921 #ifdef MLX5_PMD_SOFT_COUNTERS
922 /* Increment sent packets counter. */
923 txq->stats.opackets += i;
925 /* Ring QP doorbell. */
926 if (mpw.state == MLX5_MPW_STATE_OPENED)
927 mlx5_mpw_close(txq, &mpw);
928 mlx5_tx_dbrec(txq, mpw.wqe);
929 txq->elts_head = elts_head;
934 * Open a MPW inline session.
937 * Pointer to TX queue structure.
939 * Pointer to MPW session structure.
944 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
947 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
948 struct mlx5_wqe_inl_small *inl;
950 mpw->state = MLX5_MPW_INL_STATE_OPENED;
954 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
955 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
958 mpw->wqe->ctrl[2] = 0;
959 mpw->wqe->ctrl[3] = 0;
960 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
961 mpw->wqe->eseg.inline_hdr_sz = 0;
962 mpw->wqe->eseg.cs_flags = 0;
963 mpw->wqe->eseg.rsvd0 = 0;
964 mpw->wqe->eseg.rsvd1 = 0;
965 mpw->wqe->eseg.rsvd2 = 0;
966 inl = (struct mlx5_wqe_inl_small *)
967 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
968 mpw->data.raw = (uint8_t *)&inl->raw;
972 * Close a MPW inline session.
975 * Pointer to TX queue structure.
977 * Pointer to MPW session structure.
980 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
983 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
984 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
986 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
988 * Store size in multiple of 16 bytes. Control and Ethernet segments
991 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
993 mpw->state = MLX5_MPW_STATE_CLOSED;
994 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
995 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
999 * DPDK callback for TX with MPW inline support.
1002 * Generic pointer to TX queue structure.
1004 * Packets to transmit.
1006 * Number of packets in array.
1009 * Number of packets successfully transmitted (<= pkts_n).
1012 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1015 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1016 uint16_t elts_head = txq->elts_head;
1017 const uint16_t elts_n = 1 << txq->elts_n;
1018 const uint16_t elts_m = elts_n - 1;
1024 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1025 struct mlx5_mpw mpw = {
1026 .state = MLX5_MPW_STATE_CLOSED,
1029 * Compute the maximum number of WQE which can be consumed by inline
1032 * - 1 control segment,
1033 * - 1 Ethernet segment,
1034 * - N Dseg from the inline request.
1036 const unsigned int wqe_inl_n =
1037 ((2 * MLX5_WQE_DWORD_SIZE +
1038 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1039 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1041 if (unlikely(!pkts_n))
1043 /* Prefetch first packet cacheline. */
1044 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1045 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1046 /* Start processing. */
1047 mlx5_tx_complete(txq);
1048 max_elts = (elts_n - (elts_head - txq->elts_tail));
1050 struct rte_mbuf *buf = *(pkts++);
1053 unsigned int segs_n = buf->nb_segs;
1057 * Make sure there is enough room to store this packet and
1058 * that one ring entry remains unused.
1061 if (max_elts < segs_n)
1063 /* Do not bother with large packets MPW cannot handle. */
1064 if (segs_n > MLX5_MPW_DSEG_MAX) {
1065 txq->stats.oerrors++;
1071 * Compute max_wqe in case less WQE were consumed in previous
1074 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1075 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1076 /* Retrieve packet information. */
1077 length = PKT_LEN(buf);
1078 /* Start new session if packet differs. */
1079 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1080 if ((mpw.len != length) ||
1082 (mpw.wqe->eseg.cs_flags != cs_flags))
1083 mlx5_mpw_close(txq, &mpw);
1084 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1085 if ((mpw.len != length) ||
1087 (length > inline_room) ||
1088 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1089 mlx5_mpw_inline_close(txq, &mpw);
1091 txq->max_inline * RTE_CACHE_LINE_SIZE;
1094 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1095 if ((segs_n != 1) ||
1096 (length > inline_room)) {
1098 * Multi-Packet WQE consumes at most two WQE.
1099 * mlx5_mpw_new() expects to be able to use
1102 if (unlikely(max_wqe < 2))
1105 mlx5_mpw_new(txq, &mpw, length);
1106 mpw.wqe->eseg.cs_flags = cs_flags;
1108 if (unlikely(max_wqe < wqe_inl_n))
1110 max_wqe -= wqe_inl_n;
1111 mlx5_mpw_inline_new(txq, &mpw, length);
1112 mpw.wqe->eseg.cs_flags = cs_flags;
1115 /* Multi-segment packets must be alone in their MPW. */
1116 assert((segs_n == 1) || (mpw.pkts_n == 0));
1117 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1118 assert(inline_room ==
1119 txq->max_inline * RTE_CACHE_LINE_SIZE);
1120 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1124 volatile struct mlx5_wqe_data_seg *dseg;
1127 (*txq->elts)[elts_head++ & elts_m] = buf;
1128 dseg = mpw.data.dseg[mpw.pkts_n];
1129 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1130 *dseg = (struct mlx5_wqe_data_seg){
1132 rte_cpu_to_be_32(DATA_LEN(buf)),
1133 .lkey = mlx5_tx_mb2mr(txq, buf),
1134 .addr = rte_cpu_to_be_64(addr),
1136 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1137 length += DATA_LEN(buf);
1143 assert(length == mpw.len);
1144 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1145 mlx5_mpw_close(txq, &mpw);
1149 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1150 assert(length <= inline_room);
1151 assert(length == DATA_LEN(buf));
1152 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1153 (*txq->elts)[elts_head++ & elts_m] = buf;
1154 /* Maximum number of bytes before wrapping. */
1155 max = ((((uintptr_t)(txq->wqes)) +
1158 (uintptr_t)mpw.data.raw);
1160 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1163 mpw.data.raw = (volatile void *)txq->wqes;
1164 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1165 (void *)(addr + max),
1167 mpw.data.raw += length - max;
1169 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1175 (volatile void *)txq->wqes;
1177 mpw.data.raw += length;
1180 mpw.total_len += length;
1182 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1183 mlx5_mpw_inline_close(txq, &mpw);
1185 txq->max_inline * RTE_CACHE_LINE_SIZE;
1187 inline_room -= length;
1190 #ifdef MLX5_PMD_SOFT_COUNTERS
1191 /* Increment sent bytes counter. */
1192 txq->stats.obytes += length;
1196 /* Take a shortcut if nothing must be sent. */
1197 if (unlikely(i == 0))
1199 /* Check whether completion threshold has been reached. */
1200 /* "j" includes both packets and segments. */
1201 comp = txq->elts_comp + j;
1202 if (comp >= MLX5_TX_COMP_THRESH) {
1203 volatile struct mlx5_wqe *wqe = mpw.wqe;
1205 /* Request completion on last WQE. */
1206 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1207 /* Save elts_head in unused "immediate" field of WQE. */
1208 wqe->ctrl[3] = elts_head;
1211 txq->elts_comp = comp;
1213 #ifdef MLX5_PMD_SOFT_COUNTERS
1214 /* Increment sent packets counter. */
1215 txq->stats.opackets += i;
1217 /* Ring QP doorbell. */
1218 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1219 mlx5_mpw_inline_close(txq, &mpw);
1220 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1221 mlx5_mpw_close(txq, &mpw);
1222 mlx5_tx_dbrec(txq, mpw.wqe);
1223 txq->elts_head = elts_head;
1228 * Open an Enhanced MPW session.
1231 * Pointer to TX queue structure.
1233 * Pointer to MPW session structure.
1238 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1240 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1242 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1244 mpw->total_len = sizeof(struct mlx5_wqe);
1245 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1247 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1248 (txq->wqe_ci << 8) |
1249 MLX5_OPCODE_ENHANCED_MPSW);
1250 mpw->wqe->ctrl[2] = 0;
1251 mpw->wqe->ctrl[3] = 0;
1252 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1253 if (unlikely(padding)) {
1254 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1256 /* Pad the first 2 DWORDs with zero-length inline header. */
1257 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1258 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1259 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1260 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1261 /* Start from the next WQEBB. */
1262 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1264 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1269 * Close an Enhanced MPW session.
1272 * Pointer to TX queue structure.
1274 * Pointer to MPW session structure.
1277 * Number of consumed WQEs.
1279 static inline uint16_t
1280 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1284 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1287 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1288 MLX5_WQE_DS(mpw->total_len));
1289 mpw->state = MLX5_MPW_STATE_CLOSED;
1290 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1296 * DPDK callback for TX with Enhanced MPW support.
1299 * Generic pointer to TX queue structure.
1301 * Packets to transmit.
1303 * Number of packets in array.
1306 * Number of packets successfully transmitted (<= pkts_n).
1309 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1311 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1312 uint16_t elts_head = txq->elts_head;
1313 const uint16_t elts_n = 1 << txq->elts_n;
1314 const uint16_t elts_m = elts_n - 1;
1319 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1320 unsigned int mpw_room = 0;
1321 unsigned int inl_pad = 0;
1323 struct mlx5_mpw mpw = {
1324 .state = MLX5_MPW_STATE_CLOSED,
1327 if (unlikely(!pkts_n))
1329 /* Start processing. */
1330 mlx5_tx_complete(txq);
1331 max_elts = (elts_n - (elts_head - txq->elts_tail));
1332 /* A CQE slot must always be available. */
1333 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1334 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1335 if (unlikely(!max_wqe))
1338 struct rte_mbuf *buf = *(pkts++);
1341 unsigned int do_inline = 0; /* Whether inline is possible. */
1343 unsigned int segs_n = buf->nb_segs;
1347 * Make sure there is enough room to store this packet and
1348 * that one ring entry remains unused.
1351 if (max_elts - j < segs_n)
1353 /* Do not bother with large packets MPW cannot handle. */
1354 if (segs_n > MLX5_MPW_DSEG_MAX) {
1355 txq->stats.oerrors++;
1358 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1359 /* Retrieve packet information. */
1360 length = PKT_LEN(buf);
1361 /* Start new session if:
1362 * - multi-segment packet
1363 * - no space left even for a dseg
1364 * - next packet can be inlined with a new WQE
1366 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1369 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1370 if ((segs_n != 1) ||
1371 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1373 (length <= txq->inline_max_packet_sz &&
1374 inl_pad + sizeof(inl_hdr) + length >
1376 (mpw.wqe->eseg.cs_flags != cs_flags))
1377 max_wqe -= mlx5_empw_close(txq, &mpw);
1379 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1380 if (unlikely(segs_n != 1)) {
1381 /* Fall back to legacy MPW.
1382 * A MPW session consumes 2 WQEs at most to
1383 * include MLX5_MPW_DSEG_MAX pointers.
1385 if (unlikely(max_wqe < 2))
1387 mlx5_mpw_new(txq, &mpw, length);
1389 /* In Enhanced MPW, inline as much as the budget
1390 * is allowed. The remaining space is to be
1391 * filled with dsegs. If the title WQEBB isn't
1392 * padded, it will have 2 dsegs there.
1394 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1395 (max_inline ? max_inline :
1396 pkts_n * MLX5_WQE_DWORD_SIZE) +
1398 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1401 /* Don't pad the title WQEBB to not waste WQ. */
1402 mlx5_empw_new(txq, &mpw, 0);
1403 mpw_room -= mpw.total_len;
1406 length <= txq->inline_max_packet_sz &&
1407 sizeof(inl_hdr) + length <= mpw_room &&
1410 mpw.wqe->eseg.cs_flags = cs_flags;
1412 /* Evaluate whether the next packet can be inlined.
1413 * Inlininig is possible when:
1414 * - length is less than configured value
1415 * - length fits for remaining space
1416 * - not required to fill the title WQEBB with dsegs
1419 length <= txq->inline_max_packet_sz &&
1420 inl_pad + sizeof(inl_hdr) + length <=
1422 (!txq->mpw_hdr_dseg ||
1423 mpw.total_len >= MLX5_WQE_SIZE);
1425 /* Multi-segment packets must be alone in their MPW. */
1426 assert((segs_n == 1) || (mpw.pkts_n == 0));
1427 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1428 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1432 volatile struct mlx5_wqe_data_seg *dseg;
1435 (*txq->elts)[elts_head++ & elts_m] = buf;
1436 dseg = mpw.data.dseg[mpw.pkts_n];
1437 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1438 *dseg = (struct mlx5_wqe_data_seg){
1439 .byte_count = rte_cpu_to_be_32(
1441 .lkey = mlx5_tx_mb2mr(txq, buf),
1442 .addr = rte_cpu_to_be_64(addr),
1444 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1445 length += DATA_LEN(buf);
1451 /* A multi-segmented packet takes one MPW session.
1452 * TODO: Pack more multi-segmented packets if possible.
1454 mlx5_mpw_close(txq, &mpw);
1459 } else if (do_inline) {
1460 /* Inline packet into WQE. */
1463 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1464 assert(length == DATA_LEN(buf));
1465 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1466 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1467 mpw.data.raw = (volatile void *)
1468 ((uintptr_t)mpw.data.raw + inl_pad);
1469 max = tx_mlx5_wq_tailroom(txq,
1470 (void *)(uintptr_t)mpw.data.raw);
1471 /* Copy inline header. */
1472 mpw.data.raw = (volatile void *)
1474 (void *)(uintptr_t)mpw.data.raw,
1477 (void *)(uintptr_t)txq->wqes,
1479 max = tx_mlx5_wq_tailroom(txq,
1480 (void *)(uintptr_t)mpw.data.raw);
1481 /* Copy packet data. */
1482 mpw.data.raw = (volatile void *)
1484 (void *)(uintptr_t)mpw.data.raw,
1487 (void *)(uintptr_t)txq->wqes,
1490 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1491 /* No need to get completion as the entire packet is
1492 * copied to WQ. Free the buf right away.
1494 rte_pktmbuf_free_seg(buf);
1495 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1496 /* Add pad in the next packet if any. */
1497 inl_pad = (((uintptr_t)mpw.data.raw +
1498 (MLX5_WQE_DWORD_SIZE - 1)) &
1499 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1500 (uintptr_t)mpw.data.raw;
1502 /* No inline. Load a dseg of packet pointer. */
1503 volatile rte_v128u32_t *dseg;
1505 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1506 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1507 assert(length == DATA_LEN(buf));
1508 if (!tx_mlx5_wq_tailroom(txq,
1509 (void *)((uintptr_t)mpw.data.raw
1511 dseg = (volatile void *)txq->wqes;
1513 dseg = (volatile void *)
1514 ((uintptr_t)mpw.data.raw +
1516 (*txq->elts)[elts_head++ & elts_m] = buf;
1517 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1518 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1519 rte_prefetch2((void *)(addr +
1520 n * RTE_CACHE_LINE_SIZE));
1521 addr = rte_cpu_to_be_64(addr);
1522 *dseg = (rte_v128u32_t) {
1523 rte_cpu_to_be_32(length),
1524 mlx5_tx_mb2mr(txq, buf),
1528 mpw.data.raw = (volatile void *)(dseg + 1);
1529 mpw.total_len += (inl_pad + sizeof(*dseg));
1532 mpw_room -= (inl_pad + sizeof(*dseg));
1535 #ifdef MLX5_PMD_SOFT_COUNTERS
1536 /* Increment sent bytes counter. */
1537 txq->stats.obytes += length;
1540 } while (i < pkts_n);
1541 /* Take a shortcut if nothing must be sent. */
1542 if (unlikely(i == 0))
1544 /* Check whether completion threshold has been reached. */
1545 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1546 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1547 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1548 volatile struct mlx5_wqe *wqe = mpw.wqe;
1550 /* Request completion on last WQE. */
1551 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1552 /* Save elts_head in unused "immediate" field of WQE. */
1553 wqe->ctrl[3] = elts_head;
1555 txq->mpw_comp = txq->wqe_ci;
1558 txq->elts_comp += j;
1560 #ifdef MLX5_PMD_SOFT_COUNTERS
1561 /* Increment sent packets counter. */
1562 txq->stats.opackets += i;
1564 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1565 mlx5_empw_close(txq, &mpw);
1566 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1567 mlx5_mpw_close(txq, &mpw);
1568 /* Ring QP doorbell. */
1569 mlx5_tx_dbrec(txq, mpw.wqe);
1570 txq->elts_head = elts_head;
1575 * Translate RX completion flags to packet type.
1580 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1583 * Packet type for struct rte_mbuf.
1585 static inline uint32_t
1586 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1589 uint8_t pinfo = cqe->pkt_info;
1590 uint16_t ptype = cqe->hdr_type_etc;
1593 * The index to the array should have:
1594 * bit[1:0] = l3_hdr_type
1595 * bit[4:2] = l4_hdr_type
1598 * bit[7] = outer_l3_type
1600 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1601 return mlx5_ptype_table[idx];
1605 * Get size of the next packet for a given CQE. For compressed CQEs, the
1606 * consumer index is updated only once all packets of the current one have
1610 * Pointer to RX queue.
1613 * @param[out] rss_hash
1614 * Packet RSS Hash result.
1617 * Packet size in bytes (0 if there is none), -1 in case of completion
1621 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1622 uint16_t cqe_cnt, uint32_t *rss_hash)
1624 struct rxq_zip *zip = &rxq->zip;
1625 uint16_t cqe_n = cqe_cnt + 1;
1629 /* Process compressed data in the CQE and mini arrays. */
1631 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1632 (volatile struct mlx5_mini_cqe8 (*)[8])
1633 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1635 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1636 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1637 if ((++zip->ai & 7) == 0) {
1638 /* Invalidate consumed CQEs */
1641 while (idx != end) {
1642 (*rxq->cqes)[idx & cqe_cnt].op_own =
1643 MLX5_CQE_INVALIDATE;
1647 * Increment consumer index to skip the number of
1648 * CQEs consumed. Hardware leaves holes in the CQ
1649 * ring for software use.
1654 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1655 /* Invalidate the rest */
1659 while (idx != end) {
1660 (*rxq->cqes)[idx & cqe_cnt].op_own =
1661 MLX5_CQE_INVALIDATE;
1664 rxq->cq_ci = zip->cq_ci;
1667 /* No compressed data, get next CQE and verify if it is compressed. */
1672 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1673 if (unlikely(ret == 1))
1676 op_own = cqe->op_own;
1677 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1678 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1679 (volatile struct mlx5_mini_cqe8 (*)[8])
1680 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1683 /* Fix endianness. */
1684 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1686 * Current mini array position is the one returned by
1689 * If completion comprises several mini arrays, as a
1690 * special case the second one is located 7 CQEs after
1691 * the initial CQE instead of 8 for subsequent ones.
1693 zip->ca = rxq->cq_ci;
1694 zip->na = zip->ca + 7;
1695 /* Compute the next non compressed CQE. */
1697 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1698 /* Get packet size to return. */
1699 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1700 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1702 /* Prefetch all the entries to be invalidated */
1705 while (idx != end) {
1706 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1710 len = rte_be_to_cpu_32(cqe->byte_cnt);
1711 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1713 /* Error while receiving packet. */
1714 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1721 * Translate RX completion flags to offload flags.
1724 * Pointer to RX queue structure.
1729 * Offload flags (ol_flags) for struct rte_mbuf.
1731 static inline uint32_t
1732 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1734 uint32_t ol_flags = 0;
1735 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1739 MLX5_CQE_RX_L3_HDR_VALID,
1740 PKT_RX_IP_CKSUM_GOOD) |
1742 MLX5_CQE_RX_L4_HDR_VALID,
1743 PKT_RX_L4_CKSUM_GOOD);
1744 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1747 MLX5_CQE_RX_L3_HDR_VALID,
1748 PKT_RX_IP_CKSUM_GOOD) |
1750 MLX5_CQE_RX_L4_HDR_VALID,
1751 PKT_RX_L4_CKSUM_GOOD);
1756 * DPDK callback for RX.
1759 * Generic pointer to RX queue structure.
1761 * Array to store received packets.
1763 * Maximum number of packets in array.
1766 * Number of packets successfully received (<= pkts_n).
1769 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1771 struct mlx5_rxq_data *rxq = dpdk_rxq;
1772 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1773 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1774 const unsigned int sges_n = rxq->sges_n;
1775 struct rte_mbuf *pkt = NULL;
1776 struct rte_mbuf *seg = NULL;
1777 volatile struct mlx5_cqe *cqe =
1778 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1780 unsigned int rq_ci = rxq->rq_ci << sges_n;
1781 int len = 0; /* keep its value across iterations. */
1784 unsigned int idx = rq_ci & wqe_cnt;
1785 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1786 struct rte_mbuf *rep = (*rxq->elts)[idx];
1787 uint32_t rss_hash_res = 0;
1795 rep = rte_mbuf_raw_alloc(rxq->mp);
1796 if (unlikely(rep == NULL)) {
1797 ++rxq->stats.rx_nombuf;
1800 * no buffers before we even started,
1801 * bail out silently.
1805 while (pkt != seg) {
1806 assert(pkt != (*rxq->elts)[idx]);
1810 rte_mbuf_raw_free(pkt);
1816 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1817 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1820 rte_mbuf_raw_free(rep);
1823 if (unlikely(len == -1)) {
1824 /* RX error, packet is likely too large. */
1825 rte_mbuf_raw_free(rep);
1826 ++rxq->stats.idropped;
1830 assert(len >= (rxq->crc_present << 2));
1831 /* Update packet information. */
1832 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1834 if (rss_hash_res && rxq->rss_hash) {
1835 pkt->hash.rss = rss_hash_res;
1836 pkt->ol_flags = PKT_RX_RSS_HASH;
1839 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1840 pkt->ol_flags |= PKT_RX_FDIR;
1841 if (cqe->sop_drop_qpn !=
1842 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1843 uint32_t mark = cqe->sop_drop_qpn;
1845 pkt->ol_flags |= PKT_RX_FDIR_ID;
1847 mlx5_flow_mark_get(mark);
1850 if (rxq->csum | rxq->csum_l2tun)
1851 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1852 if (rxq->vlan_strip &&
1853 (cqe->hdr_type_etc &
1854 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1855 pkt->ol_flags |= PKT_RX_VLAN |
1856 PKT_RX_VLAN_STRIPPED;
1858 rte_be_to_cpu_16(cqe->vlan_info);
1860 if (rxq->hw_timestamp) {
1862 rte_be_to_cpu_64(cqe->timestamp);
1863 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1865 if (rxq->crc_present)
1866 len -= ETHER_CRC_LEN;
1869 DATA_LEN(rep) = DATA_LEN(seg);
1870 PKT_LEN(rep) = PKT_LEN(seg);
1871 SET_DATA_OFF(rep, DATA_OFF(seg));
1872 PORT(rep) = PORT(seg);
1873 (*rxq->elts)[idx] = rep;
1875 * Fill NIC descriptor with the new buffer. The lkey and size
1876 * of the buffers are already known, only the buffer address
1879 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1880 if (len > DATA_LEN(seg)) {
1881 len -= DATA_LEN(seg);
1886 DATA_LEN(seg) = len;
1887 #ifdef MLX5_PMD_SOFT_COUNTERS
1888 /* Increment bytes counter. */
1889 rxq->stats.ibytes += PKT_LEN(pkt);
1891 /* Return packet. */
1897 /* Align consumer index to the next stride. */
1902 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1904 /* Update the consumer index. */
1905 rxq->rq_ci = rq_ci >> sges_n;
1907 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1909 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1910 #ifdef MLX5_PMD_SOFT_COUNTERS
1911 /* Increment packets counter. */
1912 rxq->stats.ipackets += i;
1918 * Dummy DPDK callback for TX.
1920 * This function is used to temporarily replace the real callback during
1921 * unsafe control operations on the queue, or in case of error.
1924 * Generic pointer to TX queue structure.
1926 * Packets to transmit.
1928 * Number of packets in array.
1931 * Number of packets successfully transmitted (<= pkts_n).
1934 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1943 * Dummy DPDK callback for RX.
1945 * This function is used to temporarily replace the real callback during
1946 * unsafe control operations on the queue, or in case of error.
1949 * Generic pointer to RX queue structure.
1951 * Array to store received packets.
1953 * Maximum number of packets in array.
1956 * Number of packets successfully received (<= pkts_n).
1959 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1968 * Vectorized Rx/Tx routines are not compiled in when required vector
1969 * instructions are not supported on a target architecture. The following null
1970 * stubs are needed for linkage when those are not included outside of this file
1971 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1974 uint16_t __attribute__((weak))
1975 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1983 uint16_t __attribute__((weak))
1984 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1992 uint16_t __attribute__((weak))
1993 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2001 int __attribute__((weak))
2002 priv_check_raw_vec_tx_support(struct priv *priv)
2008 int __attribute__((weak))
2009 priv_check_vec_tx_support(struct priv *priv)
2015 int __attribute__((weak))
2016 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2022 int __attribute__((weak))
2023 priv_check_vec_rx_support(struct priv *priv)