4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-pedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-pedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 * Manage TX completions.
158 * When sending a burst, mlx5_tx_burst() posts several WRs.
161 * Pointer to TX queue structure.
164 txq_complete(struct txq *txq)
166 const unsigned int elts_n = txq->elts_n;
167 const unsigned int cqe_n = txq->cqe_n;
168 const unsigned int cqe_cnt = cqe_n - 1;
169 uint16_t elts_free = txq->elts_tail;
171 uint16_t cq_ci = txq->cq_ci;
172 volatile struct mlx5_cqe64 *cqe = NULL;
173 volatile union mlx5_wqe *wqe;
176 volatile struct mlx5_cqe64 *tmp;
178 tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;
179 if (check_cqe64(tmp, cqe_n, cq_ci))
183 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
184 if (!check_cqe64_seen(cqe))
185 ERROR("unexpected compressed CQE, TX stopped");
188 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
189 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
190 if (!check_cqe64_seen(cqe))
191 ERROR("unexpected error CQE, TX stopped");
197 if (unlikely(cqe == NULL))
199 wqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)];
200 elts_tail = wqe->wqe.ctrl.data[3];
201 assert(elts_tail < txq->wqe_n);
203 while (elts_free != elts_tail) {
204 struct rte_mbuf *elt = (*txq->elts)[elts_free];
205 unsigned int elts_free_next =
206 (elts_free + 1) & (elts_n - 1);
207 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
211 memset(&(*txq->elts)[elts_free],
213 sizeof((*txq->elts)[elts_free]));
215 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
216 /* Only one segment needs to be freed. */
217 rte_pktmbuf_free_seg(elt);
218 elts_free = elts_free_next;
221 txq->elts_tail = elts_tail;
222 /* Update the consumer index. */
224 *txq->cq_db = htonl(cq_ci);
228 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
229 * the cloned mbuf is allocated is returned instead.
235 * Memory pool where data is located for given mbuf.
237 static struct rte_mempool *
238 txq_mb2mp(struct rte_mbuf *buf)
240 if (unlikely(RTE_MBUF_INDIRECT(buf)))
241 return rte_mbuf_from_indirect(buf)->pool;
245 static inline uint32_t
246 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
247 __attribute__((always_inline));
250 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
251 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
252 * remove an entry first.
255 * Pointer to TX queue structure.
257 * Memory Pool for which a Memory Region lkey must be returned.
260 * mr->lkey on success, (uint32_t)-1 on failure.
262 static inline uint32_t
263 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
266 uint32_t lkey = (uint32_t)-1;
268 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
269 if (unlikely(txq->mp2mr[i].mp == NULL)) {
270 /* Unknown MP, add a new MR for it. */
273 if (txq->mp2mr[i].mp == mp) {
274 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
275 assert(htonl(txq->mp2mr[i].mr->lkey) ==
277 lkey = txq->mp2mr[i].lkey;
281 if (unlikely(lkey == (uint32_t)-1))
282 lkey = txq_mp2mr_reg(txq, mp, i);
287 * Write a regular WQE.
290 * Pointer to TX queue structure.
292 * Pointer to the WQE to fill.
294 * Buffer data address.
298 * Memory region lkey.
301 mlx5_wqe_write(struct txq *txq, volatile union mlx5_wqe *wqe,
302 uintptr_t addr, uint32_t length, uint32_t lkey)
304 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
305 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
306 wqe->wqe.ctrl.data[3] = 0;
307 wqe->inl.eseg.rsvd0 = 0;
308 wqe->inl.eseg.rsvd1 = 0;
309 wqe->inl.eseg.mss = 0;
310 wqe->inl.eseg.rsvd2 = 0;
311 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
312 /* Copy the first 16 bytes into inline header. */
313 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
314 (uint8_t *)(uintptr_t)addr,
315 MLX5_ETH_INLINE_HEADER_SIZE);
316 addr += MLX5_ETH_INLINE_HEADER_SIZE;
317 length -= MLX5_ETH_INLINE_HEADER_SIZE;
318 /* Store remaining data in data segment. */
319 wqe->wqe.dseg.byte_count = htonl(length);
320 wqe->wqe.dseg.lkey = lkey;
321 wqe->wqe.dseg.addr = htonll(addr);
322 /* Increment consumer index. */
327 * Write a regular WQE with VLAN.
330 * Pointer to TX queue structure.
332 * Pointer to the WQE to fill.
334 * Buffer data address.
338 * Memory region lkey.
340 * VLAN field to insert in packet.
343 mlx5_wqe_write_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
344 uintptr_t addr, uint32_t length, uint32_t lkey,
347 uint32_t vlan = htonl(0x81000000 | vlan_tci);
349 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
350 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
351 wqe->wqe.ctrl.data[3] = 0;
352 wqe->inl.eseg.rsvd0 = 0;
353 wqe->inl.eseg.rsvd1 = 0;
354 wqe->inl.eseg.mss = 0;
355 wqe->inl.eseg.rsvd2 = 0;
356 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
358 * Copy 12 bytes of source & destination MAC address.
359 * Copy 4 bytes of VLAN.
360 * Copy 2 bytes of Ether type.
362 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
363 (uint8_t *)(uintptr_t)addr, 12);
364 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 12),
365 &vlan, sizeof(vlan));
366 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 16),
367 (uint8_t *)((uintptr_t)addr + 12), 2);
368 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
369 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
370 /* Store remaining data in data segment. */
371 wqe->wqe.dseg.byte_count = htonl(length);
372 wqe->wqe.dseg.lkey = lkey;
373 wqe->wqe.dseg.addr = htonll(addr);
374 /* Increment consumer index. */
379 * Write a inline WQE.
382 * Pointer to TX queue structure.
384 * Pointer to the WQE to fill.
386 * Buffer data address.
390 * Memory region lkey.
393 mlx5_wqe_write_inline(struct txq *txq, volatile union mlx5_wqe *wqe,
394 uintptr_t addr, uint32_t length)
397 uint16_t wqe_cnt = txq->wqe_n - 1;
398 uint16_t wqe_ci = txq->wqe_ci + 1;
400 /* Copy the first 16 bytes into inline header. */
401 rte_memcpy((void *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
402 (void *)(uintptr_t)addr,
403 MLX5_ETH_INLINE_HEADER_SIZE);
404 addr += MLX5_ETH_INLINE_HEADER_SIZE;
405 length -= MLX5_ETH_INLINE_HEADER_SIZE;
406 size = 3 + ((4 + length + 15) / 16);
407 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
408 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
409 (void *)addr, MLX5_WQE64_INL_DATA);
410 addr += MLX5_WQE64_INL_DATA;
411 length -= MLX5_WQE64_INL_DATA;
413 volatile union mlx5_wqe *wqe_next =
414 &(*txq->wqes)[wqe_ci & wqe_cnt];
415 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
419 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
422 length -= copy_bytes;
426 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
427 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
428 wqe->inl.ctrl.data[3] = 0;
429 wqe->inl.eseg.rsvd0 = 0;
430 wqe->inl.eseg.rsvd1 = 0;
431 wqe->inl.eseg.mss = 0;
432 wqe->inl.eseg.rsvd2 = 0;
433 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
434 /* Increment consumer index. */
435 txq->wqe_ci = wqe_ci;
439 * Write a inline WQE with VLAN.
442 * Pointer to TX queue structure.
444 * Pointer to the WQE to fill.
446 * Buffer data address.
450 * Memory region lkey.
452 * VLAN field to insert in packet.
455 mlx5_wqe_write_inline_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
456 uintptr_t addr, uint32_t length, uint16_t vlan_tci)
459 uint32_t wqe_cnt = txq->wqe_n - 1;
460 uint16_t wqe_ci = txq->wqe_ci + 1;
461 uint32_t vlan = htonl(0x81000000 | vlan_tci);
464 * Copy 12 bytes of source & destination MAC address.
465 * Copy 4 bytes of VLAN.
466 * Copy 2 bytes of Ether type.
468 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
469 (uint8_t *)addr, 12);
470 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 12,
471 &vlan, sizeof(vlan));
472 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 16,
473 ((uint8_t *)addr + 12), 2);
474 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
475 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
476 size = (sizeof(wqe->inl.ctrl.ctrl) +
477 sizeof(wqe->inl.eseg) +
478 sizeof(wqe->inl.byte_cnt) +
480 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
481 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
482 (void *)addr, MLX5_WQE64_INL_DATA);
483 addr += MLX5_WQE64_INL_DATA;
484 length -= MLX5_WQE64_INL_DATA;
486 volatile union mlx5_wqe *wqe_next =
487 &(*txq->wqes)[wqe_ci & wqe_cnt];
488 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
492 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
495 length -= copy_bytes;
499 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
500 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
501 wqe->inl.ctrl.data[3] = 0;
502 wqe->inl.eseg.rsvd0 = 0;
503 wqe->inl.eseg.rsvd1 = 0;
504 wqe->inl.eseg.mss = 0;
505 wqe->inl.eseg.rsvd2 = 0;
506 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
507 /* Increment consumer index. */
508 txq->wqe_ci = wqe_ci;
512 * Ring TX queue doorbell.
515 * Pointer to TX queue structure.
518 mlx5_tx_dbrec(struct txq *txq)
520 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
522 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
523 htonl(txq->qp_num_8s),
528 *txq->qp_db = htonl(txq->wqe_ci);
529 /* Ensure ordering between DB record and BF copy. */
531 rte_mov16(dst, (uint8_t *)data);
532 txq->bf_offset ^= txq->bf_buf_size;
539 * Pointer to TX queue structure.
541 * CQE consumer index.
544 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
546 volatile struct mlx5_cqe64 *cqe;
548 cqe = &(*txq->cqes)[ci & (txq->cqe_n - 1)].cqe64;
556 * Pointer to TX queue structure.
558 * WQE consumer index.
561 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
563 volatile union mlx5_wqe *wqe;
565 wqe = &(*txq->wqes)[ci & (txq->wqe_n - 1)];
570 * DPDK callback for TX.
573 * Generic pointer to TX queue structure.
575 * Packets to transmit.
577 * Number of packets in array.
580 * Number of packets successfully transmitted (<= pkts_n).
583 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
585 struct txq *txq = (struct txq *)dpdk_txq;
586 uint16_t elts_head = txq->elts_head;
587 const unsigned int elts_n = txq->elts_n;
591 volatile union mlx5_wqe *wqe;
592 struct rte_mbuf *buf;
594 if (unlikely(!pkts_n))
597 /* Prefetch first packet cacheline. */
598 tx_prefetch_cqe(txq, txq->cq_ci);
599 tx_prefetch_cqe(txq, txq->cq_ci + 1);
601 /* Start processing. */
603 max = (elts_n - (elts_head - txq->elts_tail));
607 assert(max <= elts_n);
608 /* Always leave one free entry in the ring. */
614 for (i = 0; (i != max); ++i) {
615 unsigned int elts_head_next = (elts_head + 1) & (elts_n - 1);
620 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
623 rte_prefetch0(pkts[i + 1]);
624 /* Retrieve buffer information. */
625 addr = rte_pktmbuf_mtod(buf, uintptr_t);
626 length = DATA_LEN(buf);
627 /* Update element. */
628 (*txq->elts)[elts_head] = buf;
629 /* Prefetch next buffer data. */
631 rte_prefetch0(rte_pktmbuf_mtod(pkts[i + 1],
633 /* Retrieve Memory Region key for this memory pool. */
634 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
635 if (buf->ol_flags & PKT_TX_VLAN_PKT)
636 mlx5_wqe_write_vlan(txq, wqe, addr, length, lkey,
639 mlx5_wqe_write(txq, wqe, addr, length, lkey);
640 wqe->wqe.ctrl.data[2] = 0;
641 /* Should we enable HW CKSUM offload */
643 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
644 wqe->wqe.eseg.cs_flags =
645 MLX5_ETH_WQE_L3_CSUM |
646 MLX5_ETH_WQE_L4_CSUM;
648 wqe->wqe.eseg.cs_flags = 0;
650 #ifdef MLX5_PMD_SOFT_COUNTERS
651 /* Increment sent bytes counter. */
652 txq->stats.obytes += length;
654 elts_head = elts_head_next;
657 /* Take a shortcut if nothing must be sent. */
658 if (unlikely(i == 0))
660 /* Check whether completion threshold has been reached. */
661 comp = txq->elts_comp + i;
662 if (comp >= MLX5_TX_COMP_THRESH) {
663 /* Request completion on last WQE. */
664 wqe->wqe.ctrl.data[2] = htonl(8);
665 /* Save elts_head in unused "immediate" field of WQE. */
666 wqe->wqe.ctrl.data[3] = elts_head;
669 txq->elts_comp = comp;
671 #ifdef MLX5_PMD_SOFT_COUNTERS
672 /* Increment sent packets counter. */
673 txq->stats.opackets += i;
675 /* Ring QP doorbell. */
677 txq->elts_head = elts_head;
682 * DPDK callback for TX with inline support.
685 * Generic pointer to TX queue structure.
687 * Packets to transmit.
689 * Number of packets in array.
692 * Number of packets successfully transmitted (<= pkts_n).
695 mlx5_tx_burst_inline(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
697 struct txq *txq = (struct txq *)dpdk_txq;
698 uint16_t elts_head = txq->elts_head;
699 const unsigned int elts_n = txq->elts_n;
703 volatile union mlx5_wqe *wqe;
704 struct rte_mbuf *buf;
705 unsigned int max_inline = txq->max_inline;
707 if (unlikely(!pkts_n))
710 /* Prefetch first packet cacheline. */
711 tx_prefetch_cqe(txq, txq->cq_ci);
712 tx_prefetch_cqe(txq, txq->cq_ci + 1);
714 /* Start processing. */
716 max = (elts_n - (elts_head - txq->elts_tail));
720 assert(max <= elts_n);
721 /* Always leave one free entry in the ring. */
727 for (i = 0; (i != max); ++i) {
728 unsigned int elts_head_next = (elts_head + 1) & (elts_n - 1);
733 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
734 tx_prefetch_wqe(txq, txq->wqe_ci);
735 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
737 rte_prefetch0(pkts[i + 1]);
738 /* Should we enable HW CKSUM offload */
740 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
741 wqe->inl.eseg.cs_flags =
742 MLX5_ETH_WQE_L3_CSUM |
743 MLX5_ETH_WQE_L4_CSUM;
745 wqe->inl.eseg.cs_flags = 0;
747 /* Retrieve buffer information. */
748 addr = rte_pktmbuf_mtod(buf, uintptr_t);
749 length = DATA_LEN(buf);
750 /* Update element. */
751 (*txq->elts)[elts_head] = buf;
752 /* Prefetch next buffer data. */
754 rte_prefetch0(rte_pktmbuf_mtod(pkts[i + 1],
756 if (length <= max_inline) {
757 if (buf->ol_flags & PKT_TX_VLAN_PKT)
758 mlx5_wqe_write_inline_vlan(txq, wqe,
762 mlx5_wqe_write_inline(txq, wqe, addr, length);
764 /* Retrieve Memory Region key for this memory pool. */
765 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
766 if (buf->ol_flags & PKT_TX_VLAN_PKT)
767 mlx5_wqe_write_vlan(txq, wqe, addr, length,
768 lkey, buf->vlan_tci);
770 mlx5_wqe_write(txq, wqe, addr, length, lkey);
772 wqe->inl.ctrl.data[2] = 0;
773 elts_head = elts_head_next;
775 #ifdef MLX5_PMD_SOFT_COUNTERS
776 /* Increment sent bytes counter. */
777 txq->stats.obytes += length;
780 /* Take a shortcut if nothing must be sent. */
781 if (unlikely(i == 0))
783 /* Check whether completion threshold has been reached. */
784 comp = txq->elts_comp + i;
785 if (comp >= MLX5_TX_COMP_THRESH) {
786 /* Request completion on last WQE. */
787 wqe->inl.ctrl.data[2] = htonl(8);
788 /* Save elts_head in unused "immediate" field of WQE. */
789 wqe->inl.ctrl.data[3] = elts_head;
792 txq->elts_comp = comp;
794 #ifdef MLX5_PMD_SOFT_COUNTERS
795 /* Increment sent packets counter. */
796 txq->stats.opackets += i;
798 /* Ring QP doorbell. */
800 txq->elts_head = elts_head;
805 * Translate RX completion flags to packet type.
810 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
813 * Packet type for struct rte_mbuf.
815 static inline uint32_t
816 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
819 uint8_t flags = cqe->l4_hdr_type_etc;
820 uint8_t info = cqe->rsvd0[0];
822 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
825 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
828 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
831 IBV_EXP_CQ_RX_IPV4_PACKET,
832 RTE_PTYPE_INNER_L3_IPV4) |
834 IBV_EXP_CQ_RX_IPV6_PACKET,
835 RTE_PTYPE_INNER_L3_IPV6);
839 MLX5_CQE_L3_HDR_TYPE_IPV6,
842 MLX5_CQE_L3_HDR_TYPE_IPV4,
848 * Get size of the next packet for a given CQE. For compressed CQEs, the
849 * consumer index is updated only once all packets of the current one have
853 * Pointer to RX queue.
858 * Packet size in bytes (0 if there is none), -1 in case of completion
862 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
865 struct rxq_zip *zip = &rxq->zip;
866 uint16_t cqe_n = cqe_cnt + 1;
869 /* Process compressed data in the CQE and mini arrays. */
871 volatile struct mlx5_mini_cqe8 (*mc)[8] =
872 (volatile struct mlx5_mini_cqe8 (*)[8])
873 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
875 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
876 if ((++zip->ai & 7) == 0) {
878 * Increment consumer index to skip the number of
879 * CQEs consumed. Hardware leaves holes in the CQ
880 * ring for software use.
885 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
886 uint16_t idx = rxq->cq_ci;
887 uint16_t end = zip->cq_ci;
890 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
894 rxq->cq_ci = zip->cq_ci;
897 /* No compressed data, get next CQE and verify if it is compressed. */
902 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
903 if (unlikely(ret == 1))
906 op_own = cqe->op_own;
907 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
908 volatile struct mlx5_mini_cqe8 (*mc)[8] =
909 (volatile struct mlx5_mini_cqe8 (*)[8])
910 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
913 /* Fix endianness. */
914 zip->cqe_cnt = ntohl(cqe->byte_cnt);
916 * Current mini array position is the one returned by
919 * If completion comprises several mini arrays, as a
920 * special case the second one is located 7 CQEs after
921 * the initial CQE instead of 8 for subsequent ones.
923 zip->ca = rxq->cq_ci & cqe_cnt;
924 zip->na = zip->ca + 7;
925 /* Compute the next non compressed CQE. */
927 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
928 /* Get packet size to return. */
929 len = ntohl((*mc)[0].byte_cnt);
932 len = ntohl(cqe->byte_cnt);
934 /* Error while receiving packet. */
935 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
942 * Translate RX completion flags to offload flags.
945 * Pointer to RX queue structure.
950 * Offload flags (ol_flags) for struct rte_mbuf.
952 static inline uint32_t
953 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
955 uint32_t ol_flags = 0;
956 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
957 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
958 uint8_t info = cqe->rsvd0[0];
960 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
961 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
963 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
964 PKT_RX_IP_CKSUM_BAD);
965 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
966 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
967 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
968 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
970 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
971 PKT_RX_L4_CKSUM_BAD);
973 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
974 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
977 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
979 TRANSPOSE(~cqe->l4_hdr_type_etc,
980 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
981 PKT_RX_IP_CKSUM_BAD) |
982 TRANSPOSE(~cqe->l4_hdr_type_etc,
983 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
984 PKT_RX_L4_CKSUM_BAD);
989 * DPDK callback for RX.
992 * Generic pointer to RX queue structure.
994 * Array to store received packets.
996 * Maximum number of packets in array.
999 * Number of packets successfully received (<= pkts_n).
1002 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1004 struct rxq *rxq = dpdk_rxq;
1005 unsigned int pkts_ret = 0;
1007 unsigned int rq_ci = rxq->rq_ci;
1008 const unsigned int elts_n = rxq->elts_n;
1009 const unsigned int wqe_cnt = elts_n - 1;
1010 const unsigned int cqe_cnt = rxq->cqe_n - 1;
1012 for (i = 0; (i != pkts_n); ++i) {
1013 unsigned int idx = rq_ci & wqe_cnt;
1015 struct rte_mbuf *rep;
1016 struct rte_mbuf *pkt;
1017 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1018 volatile struct mlx5_cqe64 *cqe =
1019 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1021 pkt = (*rxq->elts)[idx];
1023 rep = rte_mbuf_raw_alloc(rxq->mp);
1024 if (unlikely(rep == NULL)) {
1025 ++rxq->stats.rx_nombuf;
1028 SET_DATA_OFF(rep, RTE_PKTMBUF_HEADROOM);
1030 PORT(rep) = rxq->port_id;
1032 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
1033 if (unlikely(len == 0)) {
1034 rte_mbuf_refcnt_set(rep, 0);
1035 __rte_mbuf_raw_free(rep);
1038 if (unlikely(len == -1)) {
1039 /* RX error, packet is likely too large. */
1040 rte_mbuf_refcnt_set(rep, 0);
1041 __rte_mbuf_raw_free(rep);
1042 ++rxq->stats.idropped;
1047 * Fill NIC descriptor with the new buffer. The lkey and size
1048 * of the buffers are already known, only the buffer address
1051 wqe->addr = htonll((uintptr_t)rep->buf_addr +
1052 RTE_PKTMBUF_HEADROOM);
1053 (*rxq->elts)[idx] = rep;
1054 /* Update pkt information. */
1055 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1058 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1059 pkt->ol_flags = rxq_cq_to_ol_flags(rxq, cqe);
1061 if (cqe->l4_hdr_type_etc & MLX5_CQE_VLAN_STRIPPED) {
1062 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1063 PKT_RX_VLAN_STRIPPED;
1064 pkt->vlan_tci = ntohs(cqe->vlan_info);
1066 if (rxq->crc_present)
1067 len -= ETHER_CRC_LEN;
1070 DATA_LEN(pkt) = len;
1071 #ifdef MLX5_PMD_SOFT_COUNTERS
1072 /* Increment bytes counter. */
1073 rxq->stats.ibytes += len;
1075 /* Return packet. */
1081 if (unlikely((i == 0) && (rq_ci == rxq->rq_ci)))
1085 DEBUG("%p: reposting %u WRs", (void *)rxq, i);
1087 /* Update the consumer index. */
1090 *rxq->cq_db = htonl(rxq->cq_ci);
1092 *rxq->rq_db = htonl(rxq->rq_ci);
1093 #ifdef MLX5_PMD_SOFT_COUNTERS
1094 /* Increment packets counter. */
1095 rxq->stats.ipackets += pkts_ret;
1101 * Dummy DPDK callback for TX.
1103 * This function is used to temporarily replace the real callback during
1104 * unsafe control operations on the queue, or in case of error.
1107 * Generic pointer to TX queue structure.
1109 * Packets to transmit.
1111 * Number of packets in array.
1114 * Number of packets successfully transmitted (<= pkts_n).
1117 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1126 * Dummy DPDK callback for RX.
1128 * This function is used to temporarily replace the real callback during
1129 * unsafe control operations on the queue, or in case of error.
1132 * Generic pointer to RX queue structure.
1134 * Array to store received packets.
1136 * Maximum number of packets in array.
1139 * Number of packets successfully received (<= pkts_n).
1142 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)