1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
29 /* TX burst subroutines return codes. */
30 enum mlx5_txcmp_code {
31 MLX5_TXCMP_CODE_EXIT = 0,
32 MLX5_TXCMP_CODE_ERROR,
33 MLX5_TXCMP_CODE_SINGLE,
34 MLX5_TXCMP_CODE_MULTI,
40 * These defines are used to configure Tx burst routine option set
41 * supported at compile time. The not specified options are optimized out
42 * out due to if conditions can be explicitly calculated at compile time.
43 * The offloads with bigger runtime check (require more CPU cycles to
44 * skip) overhead should have the bigger index - this is needed to
45 * select the better matching routine function if no exact match and
46 * some offloads are not actually requested.
48 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
49 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
50 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
51 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
52 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
53 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
54 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
55 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
56 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
57 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
59 /* The most common offloads groups. */
60 #define MLX5_TXOFF_CONFIG_NONE 0
61 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
62 MLX5_TXOFF_CONFIG_TSO | \
63 MLX5_TXOFF_CONFIG_SWP | \
64 MLX5_TXOFF_CONFIG_CSUM | \
65 MLX5_TXOFF_CONFIG_INLINE | \
66 MLX5_TXOFF_CONFIG_VLAN | \
67 MLX5_TXOFF_CONFIG_METADATA)
69 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
71 #define MLX5_TXOFF_DECL(func, olx) \
72 static uint16_t mlx5_tx_burst_##func(void *txq, \
73 struct rte_mbuf **pkts, \
76 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
77 pkts, pkts_n, (olx)); \
80 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
83 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
84 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
85 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
87 sizeof(rte_v128u32_t)),
88 "invalid Ethernet Segment data size");
89 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
91 sizeof(struct rte_vlan_hdr) +
92 2 * RTE_ETHER_ADDR_LEN),
93 "invalid Ethernet Segment data size");
94 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
96 sizeof(rte_v128u32_t)),
97 "invalid Ethernet Segment data size");
98 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
100 sizeof(struct rte_vlan_hdr) +
101 2 * RTE_ETHER_ADDR_LEN),
102 "invalid Ethernet Segment data size");
103 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
105 sizeof(rte_v128u32_t)),
106 "invalid Ethernet Segment data size");
107 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
109 sizeof(struct rte_vlan_hdr) +
110 2 * RTE_ETHER_ADDR_LEN),
111 "invalid Ethernet Segment data size");
112 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
113 (2 * RTE_ETHER_ADDR_LEN),
114 "invalid Data Segment data size");
115 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
116 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
117 static_assert((sizeof(struct rte_vlan_hdr) +
118 sizeof(struct rte_ether_hdr)) ==
119 MLX5_ESEG_MIN_INLINE_SIZE,
120 "invalid min inline data size");
121 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
122 MLX5_DSEG_MAX, "invalid WQE max size");
123 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
124 "invalid WQE Control Segment size");
125 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
126 "invalid WQE Ethernet Segment size");
127 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
128 "invalid WQE Data Segment size");
129 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
132 static __rte_always_inline uint32_t
133 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
134 volatile struct mlx5_mini_cqe8 *mcqe);
136 static __rte_always_inline int
137 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
138 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
140 static __rte_always_inline uint32_t
141 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
143 static __rte_always_inline void
144 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
145 volatile struct mlx5_cqe *cqe,
146 volatile struct mlx5_mini_cqe8 *mcqe);
149 mlx5_queue_state_modify(struct rte_eth_dev *dev,
150 struct mlx5_mp_arg_queue_state_modify *sm);
153 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
154 volatile struct mlx5_cqe *__rte_restrict cqe,
155 uint32_t phcsum, uint8_t l4_type);
158 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
159 volatile struct mlx5_cqe *__rte_restrict cqe,
160 volatile struct mlx5_mini_cqe8 *mcqe,
161 struct mlx5_rxq_data *rxq, uint32_t len);
163 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
164 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
167 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
168 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
170 uint64_t rte_net_mlx5_dynf_inline_mask;
171 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
174 * Build a table to translate Rx completion flags to packet type.
176 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
179 mlx5_set_ptype_table(void)
182 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
184 /* Last entry must not be overwritten, reserved for errored packet. */
185 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
186 (*p)[i] = RTE_PTYPE_UNKNOWN;
188 * The index to the array should have:
189 * bit[1:0] = l3_hdr_type
190 * bit[4:2] = l4_hdr_type
193 * bit[7] = outer_l3_type
196 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
198 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
199 RTE_PTYPE_L4_NONFRAG;
200 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_L4_NONFRAG;
203 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
205 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
208 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
212 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
214 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
216 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
218 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
221 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
225 /* Repeat with outer_l3_type being set. Just in case. */
226 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_L4_NONFRAG;
228 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
229 RTE_PTYPE_L4_NONFRAG;
230 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
232 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
236 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
238 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
240 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
244 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
246 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
251 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
252 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L4_NONFRAG;
255 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L4_NONFRAG;
258 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
259 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_NONFRAG;
262 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_NONFRAG;
265 /* Tunneled - Fragmented */
266 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_FRAG;
269 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_FRAG;
272 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_FRAG;
275 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_FRAG;
279 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L4_TCP;
282 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
284 RTE_PTYPE_INNER_L4_TCP;
285 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
286 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
287 RTE_PTYPE_INNER_L4_TCP;
288 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
289 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
290 RTE_PTYPE_INNER_L4_TCP;
291 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
292 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
293 RTE_PTYPE_INNER_L4_TCP;
294 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
295 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
296 RTE_PTYPE_INNER_L4_TCP;
297 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
298 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
299 RTE_PTYPE_INNER_L4_TCP;
300 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
301 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
302 RTE_PTYPE_INNER_L4_TCP;
303 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
304 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
305 RTE_PTYPE_INNER_L4_TCP;
306 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
307 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
308 RTE_PTYPE_INNER_L4_TCP;
309 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
310 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
311 RTE_PTYPE_INNER_L4_TCP;
312 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
313 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
314 RTE_PTYPE_INNER_L4_TCP;
316 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
317 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
318 RTE_PTYPE_INNER_L4_UDP;
319 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
320 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
321 RTE_PTYPE_INNER_L4_UDP;
322 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
323 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
324 RTE_PTYPE_INNER_L4_UDP;
325 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
326 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
327 RTE_PTYPE_INNER_L4_UDP;
331 * Build a table to translate packet to checksum type of Verbs.
334 mlx5_set_cksum_table(void)
340 * The index should have:
341 * bit[0] = PKT_TX_TCP_SEG
342 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
343 * bit[4] = PKT_TX_IP_CKSUM
344 * bit[8] = PKT_TX_OUTER_IP_CKSUM
347 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
350 /* Tunneled packet. */
351 if (i & (1 << 8)) /* Outer IP. */
352 v |= MLX5_ETH_WQE_L3_CSUM;
353 if (i & (1 << 4)) /* Inner IP. */
354 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
355 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
356 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
359 if (i & (1 << 4)) /* IP. */
360 v |= MLX5_ETH_WQE_L3_CSUM;
361 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
362 v |= MLX5_ETH_WQE_L4_CSUM;
364 mlx5_cksum_table[i] = v;
369 * Build a table to translate packet type of mbuf to SWP type of Verbs.
372 mlx5_set_swp_types_table(void)
378 * The index should have:
379 * bit[0:1] = PKT_TX_L4_MASK
380 * bit[4] = PKT_TX_IPV6
381 * bit[8] = PKT_TX_OUTER_IPV6
382 * bit[9] = PKT_TX_OUTER_UDP
384 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
387 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
389 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
391 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
392 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
393 v |= MLX5_ETH_WQE_L4_INNER_UDP;
394 mlx5_swp_types_table[i] = v;
399 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
400 * Flags must be preliminary initialized to zero.
403 * Pointer to burst routine local context.
405 * Pointer to store Software Parser flags
407 * Configured Tx offloads mask. It is fully defined at
408 * compile time and may be used for optimization.
411 * Software Parser offsets packed in dword.
412 * Software Parser flags are set by pointer.
414 static __rte_always_inline uint32_t
415 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
420 unsigned int idx, off;
423 if (!MLX5_TXOFF_CONFIG(SWP))
425 ol = loc->mbuf->ol_flags;
426 tunnel = ol & PKT_TX_TUNNEL_MASK;
428 * Check whether Software Parser is required.
429 * Only customized tunnels may ask for.
431 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
434 * The index should have:
435 * bit[0:1] = PKT_TX_L4_MASK
436 * bit[4] = PKT_TX_IPV6
437 * bit[8] = PKT_TX_OUTER_IPV6
438 * bit[9] = PKT_TX_OUTER_UDP
440 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
441 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
442 *swp_flags = mlx5_swp_types_table[idx];
444 * Set offsets for SW parser. Since ConnectX-5, SW parser just
445 * complements HW parser. SW parser starts to engage only if HW parser
446 * can't reach a header. For the older devices, HW parser will not kick
447 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
448 * should be set regardless of HW offload.
450 off = loc->mbuf->outer_l2_len;
451 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
452 off += sizeof(struct rte_vlan_hdr);
453 set = (off >> 1) << 8; /* Outer L3 offset. */
454 off += loc->mbuf->outer_l3_len;
455 if (tunnel == PKT_TX_TUNNEL_UDP)
456 set |= off >> 1; /* Outer L4 offset. */
457 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
458 const uint64_t csum = ol & PKT_TX_L4_MASK;
459 off += loc->mbuf->l2_len;
460 set |= (off >> 1) << 24; /* Inner L3 offset. */
461 if (csum == PKT_TX_TCP_CKSUM ||
462 csum == PKT_TX_UDP_CKSUM ||
463 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
464 off += loc->mbuf->l3_len;
465 set |= (off >> 1) << 16; /* Inner L4 offset. */
468 set = rte_cpu_to_le_32(set);
473 * Convert the Checksum offloads to Verbs.
476 * Pointer to the mbuf.
479 * Converted checksum flags.
481 static __rte_always_inline uint8_t
482 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
485 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
486 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
487 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
490 * The index should have:
491 * bit[0] = PKT_TX_TCP_SEG
492 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
493 * bit[4] = PKT_TX_IP_CKSUM
494 * bit[8] = PKT_TX_OUTER_IP_CKSUM
497 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
498 return mlx5_cksum_table[idx];
502 * Internal function to compute the number of used descriptors in an RX queue
508 * The number of used rx descriptor.
511 rx_queue_count(struct mlx5_rxq_data *rxq)
513 struct rxq_zip *zip = &rxq->zip;
514 volatile struct mlx5_cqe *cqe;
515 const unsigned int cqe_n = (1 << rxq->cqe_n);
516 const unsigned int sges_n = (1 << rxq->sges_n);
517 const unsigned int elts_n = (1 << rxq->elts_n);
518 const unsigned int strd_n = (1 << rxq->strd_num_n);
519 const unsigned int cqe_cnt = cqe_n - 1;
520 unsigned int cq_ci, used;
522 /* if we are processing a compressed cqe */
524 used = zip->cqe_cnt - zip->ai;
530 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
531 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
535 op_own = cqe->op_own;
536 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
537 n = rte_be_to_cpu_32(cqe->byte_cnt);
542 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
544 used = RTE_MIN(used * sges_n, elts_n * strd_n);
549 * DPDK callback to check the status of a rx descriptor.
554 * The index of the descriptor in the ring.
557 * The status of the tx descriptor.
560 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
562 struct mlx5_rxq_data *rxq = rx_queue;
563 struct mlx5_rxq_ctrl *rxq_ctrl =
564 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
565 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
567 if (dev->rx_pkt_burst == NULL ||
568 dev->rx_pkt_burst == removed_rx_burst) {
572 if (offset >= (1 << rxq->cqe_n)) {
576 if (offset < rx_queue_count(rxq))
577 return RTE_ETH_RX_DESC_DONE;
578 return RTE_ETH_RX_DESC_AVAIL;
582 * DPDK callback to get the RX queue information
585 * Pointer to the device structure.
588 * Rx queue identificator.
591 * Pointer to the RX queue information structure.
598 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
599 struct rte_eth_rxq_info *qinfo)
601 struct mlx5_priv *priv = dev->data->dev_private;
602 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
603 struct mlx5_rxq_ctrl *rxq_ctrl =
604 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
608 qinfo->mp = mlx5_rxq_mprq_enabled(rxq) ?
609 rxq->mprq_mp : rxq->mp;
610 qinfo->conf.rx_thresh.pthresh = 0;
611 qinfo->conf.rx_thresh.hthresh = 0;
612 qinfo->conf.rx_thresh.wthresh = 0;
613 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
614 qinfo->conf.rx_drop_en = 1;
615 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
616 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
617 qinfo->scattered_rx = dev->data->scattered_rx;
618 qinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?
619 (1 << rxq->elts_n) * (1 << rxq->strd_num_n) :
624 * DPDK callback to get the RX packet burst mode information
627 * Pointer to the device structure.
630 * Rx queue identificatior.
633 * Pointer to the burts mode information.
636 * 0 as success, -EINVAL as failure.
640 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
641 uint16_t rx_queue_id __rte_unused,
642 struct rte_eth_burst_mode *mode)
644 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
645 struct mlx5_priv *priv = dev->data->dev_private;
646 struct mlx5_rxq_data *rxq;
648 rxq = (*priv->rxqs)[rx_queue_id];
653 if (pkt_burst == mlx5_rx_burst) {
654 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
655 } else if (pkt_burst == mlx5_rx_burst_mprq) {
656 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
657 } else if (pkt_burst == mlx5_rx_burst_vec) {
658 #if defined RTE_ARCH_X86_64
659 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
660 #elif defined RTE_ARCH_ARM64
661 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
662 #elif defined RTE_ARCH_PPC_64
663 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
667 } else if (pkt_burst == mlx5_rx_burst_mprq_vec) {
668 #if defined RTE_ARCH_X86_64
669 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector SSE");
670 #elif defined RTE_ARCH_ARM64
671 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector Neon");
672 #elif defined RTE_ARCH_PPC_64
673 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector AltiVec");
684 * DPDK callback to get the number of used descriptors in a RX queue
687 * Pointer to the device structure.
693 * The number of used rx descriptor.
694 * -EINVAL if the queue is invalid
697 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
699 struct mlx5_priv *priv = dev->data->dev_private;
700 struct mlx5_rxq_data *rxq;
702 if (dev->rx_pkt_burst == NULL ||
703 dev->rx_pkt_burst == removed_rx_burst) {
707 rxq = (*priv->rxqs)[rx_queue_id];
712 return rx_queue_count(rxq);
715 #define MLX5_SYSTEM_LOG_DIR "/var/log"
717 * Dump debug information to log file.
722 * If not NULL this string is printed as a header to the output
723 * and the output will be in hexadecimal view.
725 * This is the buffer address to print out.
727 * The number of bytes to dump out.
730 mlx5_dump_debug_information(const char *fname, const char *hex_title,
731 const void *buf, unsigned int hex_len)
735 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
736 fd = fopen(path, "a+");
738 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
739 MKSTR(path2, "./%s", fname);
740 fd = fopen(path2, "a+");
742 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
745 DRV_LOG(INFO, "New debug dump in file %s", path2);
747 DRV_LOG(INFO, "New debug dump in file %s", path);
750 rte_hexdump(fd, hex_title, buf, hex_len);
752 fprintf(fd, "%s", (const char *)buf);
753 fprintf(fd, "\n\n\n");
758 * Move QP from error state to running state and initialize indexes.
761 * Pointer to TX queue control structure.
764 * 0 on success, else -1.
767 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
769 struct mlx5_mp_arg_queue_state_modify sm = {
771 .queue_id = txq_ctrl->txq.idx,
774 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
776 txq_ctrl->txq.wqe_ci = 0;
777 txq_ctrl->txq.wqe_pi = 0;
778 txq_ctrl->txq.elts_comp = 0;
782 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
784 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
786 static const uint8_t magic[] = "seen";
790 for (i = 0; i < sizeof(magic); ++i)
791 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
793 err_cqe->rsvd1[i] = magic[i];
802 * Pointer to TX queue structure.
804 * Pointer to the error CQE.
807 * Negative value if queue recovery failed, otherwise
808 * the error completion entry is handled successfully.
811 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
812 volatile struct mlx5_err_cqe *err_cqe)
814 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
815 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
816 struct mlx5_txq_ctrl *txq_ctrl =
817 container_of(txq, struct mlx5_txq_ctrl, txq);
818 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
819 int seen = check_err_cqe_seen(err_cqe);
821 if (!seen && txq_ctrl->dump_file_n <
822 txq_ctrl->priv->config.max_dump_files_num) {
823 MKSTR(err_str, "Unexpected CQE error syndrome "
824 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
825 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
826 txq->cqe_s, txq->qp_num_8s >> 8,
827 rte_be_to_cpu_16(err_cqe->wqe_counter),
828 txq->wqe_ci, txq->cq_ci);
829 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
830 PORT_ID(txq_ctrl->priv), txq->idx,
831 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
832 mlx5_dump_debug_information(name, NULL, err_str, 0);
833 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
834 (const void *)((uintptr_t)
838 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
839 (const void *)((uintptr_t)
843 txq_ctrl->dump_file_n++;
847 * Count errors in WQEs units.
848 * Later it can be improved to count error packets,
849 * for example, by SQ parsing to find how much packets
850 * should be counted for each WQE.
852 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
854 if (tx_recover_qp(txq_ctrl)) {
855 /* Recovering failed - retry later on the same WQE. */
858 /* Release all the remaining buffers. */
859 txq_free_elts(txq_ctrl);
865 * Translate RX completion flags to packet type.
868 * Pointer to RX queue structure.
872 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
875 * Packet type for struct rte_mbuf.
877 static inline uint32_t
878 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
879 volatile struct mlx5_mini_cqe8 *mcqe)
883 uint8_t pinfo = (cqe->pkt_info & 0x3) << 6;
885 /* Get l3/l4 header from mini-CQE in case L3/L4 format*/
887 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
888 ptype = (cqe->hdr_type_etc & 0xfc00) >> 10;
890 ptype = mcqe->hdr_type >> 2;
892 * The index to the array should have:
893 * bit[1:0] = l3_hdr_type
894 * bit[4:2] = l4_hdr_type
897 * bit[7] = outer_l3_type
900 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
904 * Initialize Rx WQ and indexes.
907 * Pointer to RX queue structure.
910 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
912 const unsigned int wqe_n = 1 << rxq->elts_n;
915 for (i = 0; (i != wqe_n); ++i) {
916 volatile struct mlx5_wqe_data_seg *scat;
920 if (mlx5_rxq_mprq_enabled(rxq)) {
921 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
923 scat = &((volatile struct mlx5_wqe_mprq *)
925 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
926 1 << rxq->strd_num_n);
927 byte_count = (1 << rxq->strd_sz_n) *
928 (1 << rxq->strd_num_n);
930 struct rte_mbuf *buf = (*rxq->elts)[i];
932 scat = &((volatile struct mlx5_wqe_data_seg *)
934 addr = rte_pktmbuf_mtod(buf, uintptr_t);
935 byte_count = DATA_LEN(buf);
937 /* scat->addr must be able to store a pointer. */
938 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
939 *scat = (struct mlx5_wqe_data_seg){
940 .addr = rte_cpu_to_be_64(addr),
941 .byte_count = rte_cpu_to_be_32(byte_count),
942 .lkey = mlx5_rx_addr2mr(rxq, addr),
945 rxq->consumed_strd = 0;
946 rxq->decompressed = 0;
948 rxq->zip = (struct rxq_zip){
951 rxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?
952 (wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;
953 /* Update doorbell counter. */
954 rxq->rq_ci = wqe_n >> rxq->sges_n;
956 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
960 * Modify a Verbs/DevX queue state.
961 * This must be called from the primary process.
964 * Pointer to Ethernet device.
966 * State modify request parameters.
969 * 0 in case of success else non-zero value and rte_errno is set.
972 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
973 const struct mlx5_mp_arg_queue_state_modify *sm)
976 struct mlx5_priv *priv = dev->data->dev_private;
979 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
980 struct mlx5_rxq_ctrl *rxq_ctrl =
981 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
983 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
985 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
986 sm->state, strerror(errno));
991 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
992 struct mlx5_txq_ctrl *txq_ctrl =
993 container_of(txq, struct mlx5_txq_ctrl, txq);
995 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
996 MLX5_TXQ_MOD_ERR2RDY,
997 (uint8_t)priv->dev_port);
1005 * Modify a Verbs queue state.
1008 * Pointer to Ethernet device.
1010 * State modify request parameters.
1013 * 0 in case of success else non-zero value.
1016 mlx5_queue_state_modify(struct rte_eth_dev *dev,
1017 struct mlx5_mp_arg_queue_state_modify *sm)
1019 struct mlx5_priv *priv = dev->data->dev_private;
1022 switch (rte_eal_process_type()) {
1023 case RTE_PROC_PRIMARY:
1024 ret = mlx5_queue_state_modify_primary(dev, sm);
1026 case RTE_PROC_SECONDARY:
1027 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
1036 * Handle a Rx error.
1037 * The function inserts the RQ state to reset when the first error CQE is
1038 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
1039 * it moves the RQ state to ready and initializes the RQ.
1040 * Next CQE identification and error counting are in the caller responsibility.
1043 * Pointer to RX queue structure.
1045 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
1046 * 0 when called from non-vectorized Rx burst.
1049 * -1 in case of recovery error, otherwise the CQE status.
1052 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
1054 const uint16_t cqe_n = 1 << rxq->cqe_n;
1055 const uint16_t cqe_mask = cqe_n - 1;
1056 const uint16_t wqe_n = 1 << rxq->elts_n;
1057 const uint16_t strd_n = 1 << rxq->strd_num_n;
1058 struct mlx5_rxq_ctrl *rxq_ctrl =
1059 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1061 volatile struct mlx5_cqe *cqe;
1062 volatile struct mlx5_err_cqe *err_cqe;
1064 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1066 struct mlx5_mp_arg_queue_state_modify sm;
1069 switch (rxq->err_state) {
1070 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1071 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1073 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1075 sm.queue_id = rxq->idx;
1076 sm.state = IBV_WQS_RESET;
1077 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1079 if (rxq_ctrl->dump_file_n <
1080 rxq_ctrl->priv->config.max_dump_files_num) {
1081 MKSTR(err_str, "Unexpected CQE error syndrome "
1082 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1083 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1084 rxq->cqn, rxq_ctrl->wqn,
1085 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1086 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1087 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1088 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1089 mlx5_dump_debug_information(name, NULL, err_str, 0);
1090 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1091 (const void *)((uintptr_t)
1093 sizeof(*u.cqe) * cqe_n);
1094 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1095 (const void *)((uintptr_t)
1098 rxq_ctrl->dump_file_n++;
1100 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1102 case MLX5_RXQ_ERR_STATE_NEED_READY:
1103 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1104 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1106 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1109 * The RQ consumer index must be zeroed while moving
1110 * from RESET state to RDY state.
1112 *rxq->rq_db = rte_cpu_to_be_32(0);
1115 sm.queue_id = rxq->idx;
1116 sm.state = IBV_WQS_RDY;
1117 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1121 const uint32_t elts_n =
1122 mlx5_rxq_mprq_enabled(rxq) ?
1123 wqe_n * strd_n : wqe_n;
1124 const uint32_t e_mask = elts_n - 1;
1126 mlx5_rxq_mprq_enabled(rxq) ?
1127 rxq->elts_ci : rxq->rq_ci;
1129 struct rte_mbuf **elt;
1131 unsigned int n = elts_n - (elts_ci -
1134 for (i = 0; i < (int)n; ++i) {
1135 elt_idx = (elts_ci + i) & e_mask;
1136 elt = &(*rxq->elts)[elt_idx];
1137 *elt = rte_mbuf_raw_alloc(rxq->mp);
1139 for (i--; i >= 0; --i) {
1140 elt_idx = (elts_ci +
1144 rte_pktmbuf_free_seg
1150 for (i = 0; i < (int)elts_n; ++i) {
1151 elt = &(*rxq->elts)[i];
1153 (uint16_t)((*elt)->buf_len -
1154 rte_pktmbuf_headroom(*elt));
1156 /* Padding with a fake mbuf for vec Rx. */
1157 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1158 (*rxq->elts)[elts_n + i] =
1161 mlx5_rxq_initialize(rxq);
1162 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1171 * Get size of the next packet for a given CQE. For compressed CQEs, the
1172 * consumer index is updated only once all packets of the current one have
1176 * Pointer to RX queue.
1180 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1184 * 0 in case of empty CQE, otherwise the packet size in bytes.
1187 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1188 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1190 struct rxq_zip *zip = &rxq->zip;
1191 uint16_t cqe_n = cqe_cnt + 1;
1197 /* Process compressed data in the CQE and mini arrays. */
1199 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1200 (volatile struct mlx5_mini_cqe8 (*)[8])
1201 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1203 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt &
1205 *mcqe = &(*mc)[zip->ai & 7];
1206 if ((++zip->ai & 7) == 0) {
1207 /* Invalidate consumed CQEs */
1210 while (idx != end) {
1211 (*rxq->cqes)[idx & cqe_cnt].op_own =
1212 MLX5_CQE_INVALIDATE;
1216 * Increment consumer index to skip the number
1217 * of CQEs consumed. Hardware leaves holes in
1218 * the CQ ring for software use.
1223 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1224 /* Invalidate the rest */
1228 while (idx != end) {
1229 (*rxq->cqes)[idx & cqe_cnt].op_own =
1230 MLX5_CQE_INVALIDATE;
1233 rxq->cq_ci = zip->cq_ci;
1237 * No compressed data, get next CQE and verify if it is
1245 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1246 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1247 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1249 ret = mlx5_rx_err_handle(rxq, 0);
1250 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1258 * Introduce the local variable to have queue cq_ci
1259 * index in queue structure always consistent with
1260 * actual CQE boundary (not pointing to the middle
1261 * of compressed CQE session).
1263 cq_ci = rxq->cq_ci + 1;
1264 op_own = cqe->op_own;
1265 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1266 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1267 (volatile struct mlx5_mini_cqe8 (*)[8])
1268 (uintptr_t)(&(*rxq->cqes)
1269 [cq_ci & cqe_cnt].pkt_info);
1271 /* Fix endianness. */
1272 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1274 * Current mini array position is the one
1275 * returned by check_cqe64().
1277 * If completion comprises several mini arrays,
1278 * as a special case the second one is located
1279 * 7 CQEs after the initial CQE instead of 8
1280 * for subsequent ones.
1283 zip->na = zip->ca + 7;
1284 /* Compute the next non compressed CQE. */
1285 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1286 /* Get packet size to return. */
1287 len = rte_be_to_cpu_32((*mc)[0].byte_cnt &
1291 /* Prefetch all to be invalidated */
1294 while (idx != end) {
1295 rte_prefetch0(&(*rxq->cqes)[(idx) &
1301 len = rte_be_to_cpu_32(cqe->byte_cnt);
1304 if (unlikely(rxq->err_state)) {
1305 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1306 ++rxq->stats.idropped;
1314 * Translate RX completion flags to offload flags.
1320 * Offload flags (ol_flags) for struct rte_mbuf.
1322 static inline uint32_t
1323 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1325 uint32_t ol_flags = 0;
1326 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1330 MLX5_CQE_RX_L3_HDR_VALID,
1331 PKT_RX_IP_CKSUM_GOOD) |
1333 MLX5_CQE_RX_L4_HDR_VALID,
1334 PKT_RX_L4_CKSUM_GOOD);
1339 * Fill in mbuf fields from RX completion flags.
1340 * Note that pkt->ol_flags should be initialized outside of this function.
1343 * Pointer to RX queue.
1348 * @param rss_hash_res
1349 * Packet RSS Hash result.
1352 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1353 volatile struct mlx5_cqe *cqe,
1354 volatile struct mlx5_mini_cqe8 *mcqe)
1356 /* Update packet information. */
1357 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe);
1359 if (rxq->rss_hash) {
1360 uint32_t rss_hash_res = 0;
1362 /* If compressed, take hash result from mini-CQE. */
1364 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_HASH)
1365 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1367 rss_hash_res = rte_be_to_cpu_32(mcqe->rx_hash_result);
1369 pkt->hash.rss = rss_hash_res;
1370 pkt->ol_flags |= PKT_RX_RSS_HASH;
1376 /* If compressed, take flow tag from mini-CQE. */
1378 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1379 mark = cqe->sop_drop_qpn;
1381 mark = ((mcqe->byte_cnt_flow & 0xff) << 8) |
1382 (mcqe->flow_tag_high << 16);
1383 if (MLX5_FLOW_MARK_IS_VALID(mark)) {
1384 pkt->ol_flags |= PKT_RX_FDIR;
1385 if (mark != RTE_BE32(MLX5_FLOW_MARK_DEFAULT)) {
1386 pkt->ol_flags |= PKT_RX_FDIR_ID;
1387 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1391 if (rxq->dynf_meta && cqe->flow_table_metadata) {
1392 pkt->ol_flags |= rxq->flow_meta_mask;
1393 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset, uint32_t *) =
1394 cqe->flow_table_metadata;
1397 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1398 if (rxq->vlan_strip) {
1402 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1403 vlan_strip = cqe->hdr_type_etc &
1404 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1406 vlan_strip = mcqe->hdr_type &
1407 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1409 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1410 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1413 if (rxq->hw_timestamp) {
1414 uint64_t ts = rte_be_to_cpu_64(cqe->timestamp);
1416 if (rxq->rt_timestamp)
1417 ts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);
1418 mlx5_timestamp_set(pkt, rxq->timestamp_offset, ts);
1419 pkt->ol_flags |= rxq->timestamp_rx_flag;
1424 * DPDK callback for RX.
1427 * Generic pointer to RX queue structure.
1429 * Array to store received packets.
1431 * Maximum number of packets in array.
1434 * Number of packets successfully received (<= pkts_n).
1437 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1439 struct mlx5_rxq_data *rxq = dpdk_rxq;
1440 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1441 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1442 const unsigned int sges_n = rxq->sges_n;
1443 struct rte_mbuf *pkt = NULL;
1444 struct rte_mbuf *seg = NULL;
1445 volatile struct mlx5_cqe *cqe =
1446 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1448 unsigned int rq_ci = rxq->rq_ci << sges_n;
1449 int len = 0; /* keep its value across iterations. */
1452 unsigned int idx = rq_ci & wqe_cnt;
1453 volatile struct mlx5_wqe_data_seg *wqe =
1454 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1455 struct rte_mbuf *rep = (*rxq->elts)[idx];
1456 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1464 /* Allocate the buf from the same pool. */
1465 rep = rte_mbuf_raw_alloc(seg->pool);
1466 if (unlikely(rep == NULL)) {
1467 ++rxq->stats.rx_nombuf;
1470 * no buffers before we even started,
1471 * bail out silently.
1475 while (pkt != seg) {
1476 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1480 rte_mbuf_raw_free(pkt);
1486 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1487 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1489 rte_mbuf_raw_free(rep);
1493 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1494 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1495 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1496 if (rxq->crc_present)
1497 len -= RTE_ETHER_CRC_LEN;
1499 if (cqe->lro_num_seg > 1) {
1501 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1503 pkt->ol_flags |= PKT_RX_LRO;
1504 pkt->tso_segsz = len / cqe->lro_num_seg;
1507 DATA_LEN(rep) = DATA_LEN(seg);
1508 PKT_LEN(rep) = PKT_LEN(seg);
1509 SET_DATA_OFF(rep, DATA_OFF(seg));
1510 PORT(rep) = PORT(seg);
1511 (*rxq->elts)[idx] = rep;
1513 * Fill NIC descriptor with the new buffer. The lkey and size
1514 * of the buffers are already known, only the buffer address
1517 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1518 /* If there's only one MR, no need to replace LKey in WQE. */
1519 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1520 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1521 if (len > DATA_LEN(seg)) {
1522 len -= DATA_LEN(seg);
1527 DATA_LEN(seg) = len;
1528 #ifdef MLX5_PMD_SOFT_COUNTERS
1529 /* Increment bytes counter. */
1530 rxq->stats.ibytes += PKT_LEN(pkt);
1532 /* Return packet. */
1537 /* Align consumer index to the next stride. */
1542 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1544 /* Update the consumer index. */
1545 rxq->rq_ci = rq_ci >> sges_n;
1547 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1549 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1550 #ifdef MLX5_PMD_SOFT_COUNTERS
1551 /* Increment packets counter. */
1552 rxq->stats.ipackets += i;
1558 * Update LRO packet TCP header.
1559 * The HW LRO feature doesn't update the TCP header after coalescing the
1560 * TCP segments but supplies information in CQE to fill it by SW.
1563 * Pointer to the TCP header.
1565 * Pointer to the completion entry..
1567 * The L3 pseudo-header checksum.
1570 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1571 volatile struct mlx5_cqe *__rte_restrict cqe,
1572 uint32_t phcsum, uint8_t l4_type)
1575 * The HW calculates only the TCP payload checksum, need to complete
1576 * the TCP header checksum and the L3 pseudo-header checksum.
1578 uint32_t csum = phcsum + cqe->csum;
1580 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1581 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1582 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1583 tcp->recv_ack = cqe->lro_ack_seq_num;
1584 tcp->rx_win = cqe->lro_tcp_win;
1586 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1587 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1589 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1590 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1591 csum = (~csum) & 0xffff;
1598 * Update LRO packet headers.
1599 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1600 * TCP segments but supply information in CQE to fill it by SW.
1603 * The packet address.
1605 * Pointer to the completion entry..
1607 * The packet length.
1610 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1611 volatile struct mlx5_cqe *__rte_restrict cqe,
1612 volatile struct mlx5_mini_cqe8 *mcqe,
1613 struct mlx5_rxq_data *rxq, uint32_t len)
1616 struct rte_ether_hdr *eth;
1617 struct rte_vlan_hdr *vlan;
1618 struct rte_ipv4_hdr *ipv4;
1619 struct rte_ipv6_hdr *ipv6;
1620 struct rte_tcp_hdr *tcp;
1625 uint16_t proto = h.eth->ether_type;
1630 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1631 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1632 proto = h.vlan->eth_proto;
1635 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1636 h.ipv4->time_to_live = cqe->lro_min_ttl;
1637 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1638 h.ipv4->hdr_checksum = 0;
1639 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1640 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1643 h.ipv6->hop_limits = cqe->lro_min_ttl;
1644 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1646 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1650 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1651 l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1652 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1654 l4_type = (rte_be_to_cpu_16(mcqe->hdr_type) &
1655 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1656 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum, l4_type);
1660 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1662 struct mlx5_mprq_buf *buf = opaque;
1664 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {
1665 rte_mempool_put(buf->mp, buf);
1666 } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
1667 __ATOMIC_RELAXED) == 0)) {
1668 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1669 rte_mempool_put(buf->mp, buf);
1674 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1676 mlx5_mprq_buf_free_cb(NULL, buf);
1680 * DPDK callback for RX with Multi-Packet RQ support.
1683 * Generic pointer to RX queue structure.
1685 * Array to store received packets.
1687 * Maximum number of packets in array.
1690 * Number of packets successfully received (<= pkts_n).
1693 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1695 struct mlx5_rxq_data *rxq = dpdk_rxq;
1696 const uint32_t strd_n = 1 << rxq->strd_num_n;
1697 const uint32_t strd_sz = 1 << rxq->strd_sz_n;
1698 const uint32_t cq_mask = (1 << rxq->cqe_n) - 1;
1699 const uint32_t wq_mask = (1 << rxq->elts_n) - 1;
1700 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1702 uint32_t rq_ci = rxq->rq_ci;
1703 uint16_t consumed_strd = rxq->consumed_strd;
1704 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1706 while (i < pkts_n) {
1707 struct rte_mbuf *pkt;
1713 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1714 enum mlx5_rqx_code rxq_code;
1716 if (consumed_strd == strd_n) {
1717 /* Replace WQE if the buffer is still in use. */
1718 mprq_buf_replace(rxq, rq_ci & wq_mask);
1719 /* Advance to the next WQE. */
1722 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1724 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1725 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1729 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1730 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1731 if (rxq->crc_present)
1732 len -= RTE_ETHER_CRC_LEN;
1734 rxq->mcqe_format == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1735 strd_cnt = (len / strd_sz) + !!(len % strd_sz);
1737 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1738 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1739 MLX5_ASSERT(strd_cnt);
1740 consumed_strd += strd_cnt;
1741 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1743 strd_idx = rte_be_to_cpu_16(mcqe == NULL ?
1746 MLX5_ASSERT(strd_idx < strd_n);
1747 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1749 pkt = rte_pktmbuf_alloc(rxq->mp);
1750 if (unlikely(pkt == NULL)) {
1751 ++rxq->stats.rx_nombuf;
1754 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1755 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1756 if (rxq->crc_present)
1757 len -= RTE_ETHER_CRC_LEN;
1758 rxq_code = mprq_buf_to_pkt(rxq, pkt, len, buf,
1759 strd_idx, strd_cnt);
1760 if (unlikely(rxq_code != MLX5_RXQ_CODE_EXIT)) {
1761 rte_pktmbuf_free_seg(pkt);
1762 if (rxq_code == MLX5_RXQ_CODE_DROPPED) {
1763 ++rxq->stats.idropped;
1766 if (rxq_code == MLX5_RXQ_CODE_NOMBUF) {
1767 ++rxq->stats.rx_nombuf;
1771 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1772 if (cqe->lro_num_seg > 1) {
1773 mlx5_lro_update_hdr(rte_pktmbuf_mtod(pkt, uint8_t *),
1774 cqe, mcqe, rxq, len);
1775 pkt->ol_flags |= PKT_RX_LRO;
1776 pkt->tso_segsz = len / cqe->lro_num_seg;
1779 PORT(pkt) = rxq->port_id;
1780 #ifdef MLX5_PMD_SOFT_COUNTERS
1781 /* Increment bytes counter. */
1782 rxq->stats.ibytes += PKT_LEN(pkt);
1784 /* Return packet. */
1788 /* Update the consumer indexes. */
1789 rxq->consumed_strd = consumed_strd;
1791 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1792 if (rq_ci != rxq->rq_ci) {
1795 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1797 #ifdef MLX5_PMD_SOFT_COUNTERS
1798 /* Increment packets counter. */
1799 rxq->stats.ipackets += i;
1805 * Dummy DPDK callback for TX.
1807 * This function is used to temporarily replace the real callback during
1808 * unsafe control operations on the queue, or in case of error.
1811 * Generic pointer to TX queue structure.
1813 * Packets to transmit.
1815 * Number of packets in array.
1818 * Number of packets successfully transmitted (<= pkts_n).
1821 removed_tx_burst(void *dpdk_txq __rte_unused,
1822 struct rte_mbuf **pkts __rte_unused,
1823 uint16_t pkts_n __rte_unused)
1830 * Dummy DPDK callback for RX.
1832 * This function is used to temporarily replace the real callback during
1833 * unsafe control operations on the queue, or in case of error.
1836 * Generic pointer to RX queue structure.
1838 * Array to store received packets.
1840 * Maximum number of packets in array.
1843 * Number of packets successfully received (<= pkts_n).
1846 removed_rx_burst(void *dpdk_txq __rte_unused,
1847 struct rte_mbuf **pkts __rte_unused,
1848 uint16_t pkts_n __rte_unused)
1855 * Vectorized Rx/Tx routines are not compiled in when required vector
1856 * instructions are not supported on a target architecture. The following null
1857 * stubs are needed for linkage when those are not included outside of this file
1858 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1862 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1863 struct rte_mbuf **pkts __rte_unused,
1864 uint16_t pkts_n __rte_unused)
1870 mlx5_rx_burst_mprq_vec(void *dpdk_txq __rte_unused,
1871 struct rte_mbuf **pkts __rte_unused,
1872 uint16_t pkts_n __rte_unused)
1878 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1884 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1890 * Free the mbufs from the linear array of pointers.
1893 * Pointer to Tx queue structure.
1895 * Pointer to array of packets to be free.
1897 * Number of packets to be freed.
1899 * Configured Tx offloads mask. It is fully defined at
1900 * compile time and may be used for optimization.
1902 static __rte_always_inline void
1903 mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
1904 struct rte_mbuf **__rte_restrict pkts,
1905 unsigned int pkts_n,
1906 unsigned int olx __rte_unused)
1908 struct rte_mempool *pool = NULL;
1909 struct rte_mbuf **p_free = NULL;
1910 struct rte_mbuf *mbuf;
1911 unsigned int n_free = 0;
1914 * The implemented algorithm eliminates
1915 * copying pointers to temporary array
1916 * for rte_mempool_put_bulk() calls.
1919 MLX5_ASSERT(pkts_n);
1921 * Free mbufs directly to the pool in bulk
1922 * if fast free offload is engaged
1924 if (!MLX5_TXOFF_CONFIG(MULTI) && txq->fast_free) {
1927 rte_mempool_put_bulk(pool, (void *)pkts, pkts_n);
1933 * Decrement mbuf reference counter, detach
1934 * indirect and external buffers if needed.
1936 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1937 if (likely(mbuf != NULL)) {
1938 MLX5_ASSERT(mbuf == *pkts);
1939 if (likely(n_free != 0)) {
1940 if (unlikely(pool != mbuf->pool))
1941 /* From different pool. */
1944 /* Start new scan array. */
1951 if (unlikely(pkts_n == 0)) {
1957 * This happens if mbuf is still referenced.
1958 * We can't put it back to the pool, skip.
1962 if (unlikely(n_free != 0))
1963 /* There is some array to free.*/
1965 if (unlikely(pkts_n == 0))
1966 /* Last mbuf, nothing to free. */
1972 * This loop is implemented to avoid multiple
1973 * inlining of rte_mempool_put_bulk().
1976 MLX5_ASSERT(p_free);
1977 MLX5_ASSERT(n_free);
1979 * Free the array of pre-freed mbufs
1980 * belonging to the same memory pool.
1982 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1983 if (unlikely(mbuf != NULL)) {
1984 /* There is the request to start new scan. */
1989 if (likely(pkts_n != 0))
1992 * This is the last mbuf to be freed.
1993 * Do one more loop iteration to complete.
1994 * This is rare case of the last unique mbuf.
1999 if (likely(pkts_n == 0))
2007 * No inline version to free buffers for optimal call
2008 * on the tx_burst completion.
2010 static __rte_noinline void
2011 __mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
2012 struct rte_mbuf **__rte_restrict pkts,
2013 unsigned int pkts_n,
2014 unsigned int olx __rte_unused)
2016 mlx5_tx_free_mbuf(txq, pkts, pkts_n, olx);
2020 * Free the mbuf from the elts ring buffer till new tail.
2023 * Pointer to Tx queue structure.
2025 * Index in elts to free up to, becomes new elts tail.
2027 * Configured Tx offloads mask. It is fully defined at
2028 * compile time and may be used for optimization.
2030 static __rte_always_inline void
2031 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
2033 unsigned int olx __rte_unused)
2035 uint16_t n_elts = tail - txq->elts_tail;
2037 MLX5_ASSERT(n_elts);
2038 MLX5_ASSERT(n_elts <= txq->elts_s);
2040 * Implement a loop to support ring buffer wraparound
2041 * with single inlining of mlx5_tx_free_mbuf().
2046 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
2047 part = RTE_MIN(part, n_elts);
2049 MLX5_ASSERT(part <= txq->elts_s);
2050 mlx5_tx_free_mbuf(txq,
2051 &txq->elts[txq->elts_tail & txq->elts_m],
2053 txq->elts_tail += part;
2059 * Store the mbuf being sent into elts ring buffer.
2060 * On Tx completion these mbufs will be freed.
2063 * Pointer to Tx queue structure.
2065 * Pointer to array of packets to be stored.
2067 * Number of packets to be stored.
2069 * Configured Tx offloads mask. It is fully defined at
2070 * compile time and may be used for optimization.
2072 static __rte_always_inline void
2073 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
2074 struct rte_mbuf **__rte_restrict pkts,
2075 unsigned int pkts_n,
2076 unsigned int olx __rte_unused)
2079 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2082 MLX5_ASSERT(pkts_n);
2083 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2085 MLX5_ASSERT(part <= txq->elts_s);
2086 /* This code is a good candidate for vectorizing with SIMD. */
2087 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2089 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2090 txq->elts_head += pkts_n;
2091 if (unlikely(part < pkts_n))
2092 /* The copy is wrapping around the elts array. */
2093 rte_memcpy((void *)elts, (void *)(pkts + part),
2094 (pkts_n - part) * sizeof(struct rte_mbuf *));
2098 * Update completion queue consuming index via doorbell
2099 * and flush the completed data buffers.
2102 * Pointer to TX queue structure.
2103 * @param valid CQE pointer
2104 * if not NULL update txq->wqe_pi and flush the buffers
2106 * Configured Tx offloads mask. It is fully defined at
2107 * compile time and may be used for optimization.
2109 static __rte_always_inline void
2110 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
2111 volatile struct mlx5_cqe *last_cqe,
2112 unsigned int olx __rte_unused)
2114 if (likely(last_cqe != NULL)) {
2117 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2118 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2119 if (likely(tail != txq->elts_tail)) {
2120 mlx5_tx_free_elts(txq, tail, olx);
2121 MLX5_ASSERT(tail == txq->elts_tail);
2127 * Manage TX completions. This routine checks the CQ for
2128 * arrived CQEs, deduces the last accomplished WQE in SQ,
2129 * updates SQ producing index and frees all completed mbufs.
2132 * Pointer to TX queue structure.
2134 * Configured Tx offloads mask. It is fully defined at
2135 * compile time and may be used for optimization.
2137 * NOTE: not inlined intentionally, it makes tx_burst
2138 * routine smaller, simple and faster - from experiments.
2141 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2142 unsigned int olx __rte_unused)
2144 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2145 volatile struct mlx5_cqe *last_cqe = NULL;
2146 bool ring_doorbell = false;
2150 volatile struct mlx5_cqe *cqe;
2152 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2153 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2154 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2155 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2156 /* No new CQEs in completion queue. */
2157 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2161 * Some error occurred, try to restart.
2162 * We have no barrier after WQE related Doorbell
2163 * written, make sure all writes are completed
2164 * here, before we might perform SQ reset.
2167 ret = mlx5_tx_error_cqe_handle
2168 (txq, (volatile struct mlx5_err_cqe *)cqe);
2169 if (unlikely(ret < 0)) {
2171 * Some error occurred on queue error
2172 * handling, we do not advance the index
2173 * here, allowing to retry on next call.
2178 * We are going to fetch all entries with
2179 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2180 * The send queue is supposed to be empty.
2182 ring_doorbell = true;
2184 txq->cq_pi = txq->cq_ci;
2188 /* Normal transmit completion. */
2189 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2190 #ifdef RTE_LIBRTE_MLX5_DEBUG
2191 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2194 ring_doorbell = true;
2198 * We have to restrict the amount of processed CQEs
2199 * in one tx_burst routine call. The CQ may be large
2200 * and many CQEs may be updated by the NIC in one
2201 * transaction. Buffers freeing is time consuming,
2202 * multiple iterations may introduce significant
2205 if (likely(--count == 0))
2208 if (likely(ring_doorbell)) {
2209 /* Ring doorbell to notify hardware. */
2210 rte_compiler_barrier();
2211 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2212 mlx5_tx_comp_flush(txq, last_cqe, olx);
2217 * Check if the completion request flag should be set in the last WQE.
2218 * Both pushed mbufs and WQEs are monitored and the completion request
2219 * flag is set if any of thresholds is reached.
2222 * Pointer to TX queue structure.
2224 * Pointer to burst routine local context.
2226 * Configured Tx offloads mask. It is fully defined at
2227 * compile time and may be used for optimization.
2229 static __rte_always_inline void
2230 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2231 struct mlx5_txq_local *__rte_restrict loc,
2234 uint16_t head = txq->elts_head;
2237 part = MLX5_TXOFF_CONFIG(INLINE) ?
2238 0 : loc->pkts_sent - loc->pkts_copy;
2240 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2241 (MLX5_TXOFF_CONFIG(INLINE) &&
2242 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2243 volatile struct mlx5_wqe *last = loc->wqe_last;
2246 txq->elts_comp = head;
2247 if (MLX5_TXOFF_CONFIG(INLINE))
2248 txq->wqe_comp = txq->wqe_ci;
2249 /* Request unconditional completion on last WQE. */
2250 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2251 MLX5_COMP_MODE_OFFSET);
2252 /* Save elts_head in dedicated free on completion queue. */
2253 #ifdef RTE_LIBRTE_MLX5_DEBUG
2254 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2255 (last->cseg.opcode >> 8) << 16;
2257 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2259 /* A CQE slot must always be available. */
2260 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2265 * DPDK callback to check the status of a tx descriptor.
2270 * The index of the descriptor in the ring.
2273 * The status of the tx descriptor.
2276 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2278 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2281 mlx5_tx_handle_completion(txq, 0);
2282 used = txq->elts_head - txq->elts_tail;
2284 return RTE_ETH_TX_DESC_FULL;
2285 return RTE_ETH_TX_DESC_DONE;
2289 * Build the Control Segment with specified opcode:
2290 * - MLX5_OPCODE_SEND
2291 * - MLX5_OPCODE_ENHANCED_MPSW
2295 * Pointer to TX queue structure.
2297 * Pointer to burst routine local context.
2299 * Pointer to WQE to fill with built Control Segment.
2301 * Supposed length of WQE in segments.
2303 * SQ WQE opcode to put into Control Segment.
2305 * Configured Tx offloads mask. It is fully defined at
2306 * compile time and may be used for optimization.
2308 static __rte_always_inline void
2309 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2310 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2311 struct mlx5_wqe *__rte_restrict wqe,
2313 unsigned int opcode,
2314 unsigned int olx __rte_unused)
2316 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2318 /* For legacy MPW replace the EMPW by TSO with modifier. */
2319 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2320 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2321 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2322 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2323 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2324 MLX5_COMP_MODE_OFFSET);
2325 cs->misc = RTE_BE32(0);
2329 * Build the Synchronize Queue Segment with specified completion index.
2332 * Pointer to TX queue structure.
2334 * Pointer to burst routine local context.
2336 * Pointer to WQE to fill with built Control Segment.
2338 * Completion index in Clock Queue to wait.
2340 * Configured Tx offloads mask. It is fully defined at
2341 * compile time and may be used for optimization.
2343 static __rte_always_inline void
2344 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
2345 struct mlx5_txq_local *restrict loc __rte_unused,
2346 struct mlx5_wqe *restrict wqe,
2348 unsigned int olx __rte_unused)
2350 struct mlx5_wqe_qseg *qs;
2352 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
2353 qs->max_index = rte_cpu_to_be_32(wci);
2354 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq_obj.cq->id);
2355 qs->reserved0 = RTE_BE32(0);
2356 qs->reserved1 = RTE_BE32(0);
2360 * Build the Ethernet Segment without inlined data.
2361 * Supports Software Parser, Checksums and VLAN
2362 * insertion Tx offload features.
2365 * Pointer to TX queue structure.
2367 * Pointer to burst routine local context.
2369 * Pointer to WQE to fill with built Ethernet Segment.
2371 * Configured Tx offloads mask. It is fully defined at
2372 * compile time and may be used for optimization.
2374 static __rte_always_inline void
2375 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2376 struct mlx5_txq_local *__rte_restrict loc,
2377 struct mlx5_wqe *__rte_restrict wqe,
2380 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2384 * Calculate and set check sum flags first, dword field
2385 * in segment may be shared with Software Parser flags.
2387 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2388 es->flags = rte_cpu_to_le_32(csum);
2390 * Calculate and set Software Parser offsets and flags.
2391 * These flags a set for custom UDP and IP tunnel packets.
2393 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2394 /* Fill metadata field if needed. */
2395 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2396 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2397 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2398 /* Engage VLAN tag insertion feature if requested. */
2399 if (MLX5_TXOFF_CONFIG(VLAN) &&
2400 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2402 * We should get here only if device support
2403 * this feature correctly.
2405 MLX5_ASSERT(txq->vlan_en);
2406 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2407 loc->mbuf->vlan_tci);
2409 es->inline_hdr = RTE_BE32(0);
2414 * Build the Ethernet Segment with minimal inlined data
2415 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2416 * used to fill the gap in single WQEBB WQEs.
2417 * Supports Software Parser, Checksums and VLAN
2418 * insertion Tx offload features.
2421 * Pointer to TX queue structure.
2423 * Pointer to burst routine local context.
2425 * Pointer to WQE to fill with built Ethernet Segment.
2427 * Length of VLAN tag insertion if any.
2429 * Configured Tx offloads mask. It is fully defined at
2430 * compile time and may be used for optimization.
2432 static __rte_always_inline void
2433 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2434 struct mlx5_txq_local *__rte_restrict loc,
2435 struct mlx5_wqe *__rte_restrict wqe,
2439 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2441 uint8_t *psrc, *pdst;
2444 * Calculate and set check sum flags first, dword field
2445 * in segment may be shared with Software Parser flags.
2447 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2448 es->flags = rte_cpu_to_le_32(csum);
2450 * Calculate and set Software Parser offsets and flags.
2451 * These flags a set for custom UDP and IP tunnel packets.
2453 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2454 /* Fill metadata field if needed. */
2455 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2456 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2457 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2458 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2459 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2460 es->inline_data = *(unaligned_uint16_t *)psrc;
2461 psrc += sizeof(uint16_t);
2462 pdst = (uint8_t *)(es + 1);
2463 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2464 /* Implement VLAN tag insertion as part inline data. */
2465 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2466 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2467 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2468 /* Insert VLAN ethertype + VLAN tag. */
2469 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2470 ((RTE_ETHER_TYPE_VLAN << 16) |
2471 loc->mbuf->vlan_tci);
2472 pdst += sizeof(struct rte_vlan_hdr);
2473 /* Copy the rest two bytes from packet data. */
2474 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2475 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2477 /* Fill the gap in the title WQEBB with inline data. */
2478 rte_mov16(pdst, psrc);
2483 * Build the Ethernet Segment with entire packet
2484 * data inlining. Checks the boundary of WQEBB and
2485 * ring buffer wrapping, supports Software Parser,
2486 * Checksums and VLAN insertion Tx offload features.
2489 * Pointer to TX queue structure.
2491 * Pointer to burst routine local context.
2493 * Pointer to WQE to fill with built Ethernet Segment.
2495 * Length of VLAN tag insertion if any.
2497 * Length of data to inline (VLAN included, if any).
2499 * TSO flag, set mss field from the packet.
2501 * Configured Tx offloads mask. It is fully defined at
2502 * compile time and may be used for optimization.
2505 * Pointer to the next Data Segment (aligned and wrapped around).
2507 static __rte_always_inline struct mlx5_wqe_dseg *
2508 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2509 struct mlx5_txq_local *__rte_restrict loc,
2510 struct mlx5_wqe *__rte_restrict wqe,
2516 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2518 uint8_t *psrc, *pdst;
2522 * Calculate and set check sum flags first, dword field
2523 * in segment may be shared with Software Parser flags.
2525 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2528 csum |= loc->mbuf->tso_segsz;
2529 es->flags = rte_cpu_to_be_32(csum);
2531 es->flags = rte_cpu_to_le_32(csum);
2534 * Calculate and set Software Parser offsets and flags.
2535 * These flags a set for custom UDP and IP tunnel packets.
2537 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2538 /* Fill metadata field if needed. */
2539 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2540 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2541 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2542 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2543 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2544 es->inline_data = *(unaligned_uint16_t *)psrc;
2545 psrc += sizeof(uint16_t);
2546 pdst = (uint8_t *)(es + 1);
2547 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2548 /* Implement VLAN tag insertion as part inline data. */
2549 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2550 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2551 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2552 /* Insert VLAN ethertype + VLAN tag. */
2553 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2554 ((RTE_ETHER_TYPE_VLAN << 16) |
2555 loc->mbuf->vlan_tci);
2556 pdst += sizeof(struct rte_vlan_hdr);
2557 /* Copy the rest two bytes from packet data. */
2558 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2559 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2560 psrc += sizeof(uint16_t);
2562 /* Fill the gap in the title WQEBB with inline data. */
2563 rte_mov16(pdst, psrc);
2564 psrc += sizeof(rte_v128u32_t);
2566 pdst = (uint8_t *)(es + 2);
2567 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2568 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2569 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2571 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2572 return (struct mlx5_wqe_dseg *)pdst;
2575 * The WQEBB space availability is checked by caller.
2576 * Here we should be aware of WQE ring buffer wraparound only.
2578 part = (uint8_t *)txq->wqes_end - pdst;
2579 part = RTE_MIN(part, inlen);
2581 rte_memcpy(pdst, psrc, part);
2583 if (likely(!inlen)) {
2585 * If return value is not used by the caller
2586 * the code below will be optimized out.
2589 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2590 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2591 pdst = (uint8_t *)txq->wqes;
2592 return (struct mlx5_wqe_dseg *)pdst;
2594 pdst = (uint8_t *)txq->wqes;
2601 * Copy data from chain of mbuf to the specified linear buffer.
2602 * Checksums and VLAN insertion Tx offload features. If data
2603 * from some mbuf copied completely this mbuf is freed. Local
2604 * structure is used to keep the byte stream state.
2607 * Pointer to the destination linear buffer.
2609 * Pointer to burst routine local context.
2611 * Length of data to be copied.
2613 * Length of data to be copied ignoring no inline hint.
2615 * Configured Tx offloads mask. It is fully defined at
2616 * compile time and may be used for optimization.
2619 * Number of actual copied data bytes. This is always greater than or
2620 * equal to must parameter and might be lesser than len in no inline
2621 * hint flag is encountered.
2623 static __rte_always_inline unsigned int
2624 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2625 struct mlx5_txq_local *__rte_restrict loc,
2628 unsigned int olx __rte_unused)
2630 struct rte_mbuf *mbuf;
2631 unsigned int part, dlen, copy = 0;
2635 MLX5_ASSERT(must <= len);
2637 /* Allow zero length packets, must check first. */
2638 dlen = rte_pktmbuf_data_len(loc->mbuf);
2639 if (dlen <= loc->mbuf_off) {
2640 /* Exhausted packet, just free. */
2642 loc->mbuf = mbuf->next;
2643 rte_pktmbuf_free_seg(mbuf);
2645 MLX5_ASSERT(loc->mbuf_nseg > 1);
2646 MLX5_ASSERT(loc->mbuf);
2648 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2653 * We already copied the minimal
2654 * requested amount of data.
2659 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2661 * Copy only the minimal required
2662 * part of the data buffer.
2669 dlen -= loc->mbuf_off;
2670 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2672 part = RTE_MIN(len, dlen);
2673 rte_memcpy(pdst, psrc, part);
2675 loc->mbuf_off += part;
2678 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2680 /* Exhausted packet, just free. */
2682 loc->mbuf = mbuf->next;
2683 rte_pktmbuf_free_seg(mbuf);
2685 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2695 * Build the Ethernet Segment with inlined data from
2696 * multi-segment packet. Checks the boundary of WQEBB
2697 * and ring buffer wrapping, supports Software Parser,
2698 * Checksums and VLAN insertion Tx offload features.
2701 * Pointer to TX queue structure.
2703 * Pointer to burst routine local context.
2705 * Pointer to WQE to fill with built Ethernet Segment.
2707 * Length of VLAN tag insertion if any.
2709 * Length of data to inline (VLAN included, if any).
2711 * TSO flag, set mss field from the packet.
2713 * Configured Tx offloads mask. It is fully defined at
2714 * compile time and may be used for optimization.
2717 * Pointer to the next Data Segment (aligned and
2718 * possible NOT wrapped around - caller should do
2719 * wrapping check on its own).
2721 static __rte_always_inline struct mlx5_wqe_dseg *
2722 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2723 struct mlx5_txq_local *__rte_restrict loc,
2724 struct mlx5_wqe *__rte_restrict wqe,
2730 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2733 unsigned int part, tlen = 0;
2736 * Calculate and set check sum flags first, uint32_t field
2737 * in segment may be shared with Software Parser flags.
2739 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2742 csum |= loc->mbuf->tso_segsz;
2743 es->flags = rte_cpu_to_be_32(csum);
2745 es->flags = rte_cpu_to_le_32(csum);
2748 * Calculate and set Software Parser offsets and flags.
2749 * These flags a set for custom UDP and IP tunnel packets.
2751 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2752 /* Fill metadata field if needed. */
2753 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2754 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2755 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2756 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2757 pdst = (uint8_t *)&es->inline_data;
2758 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2759 /* Implement VLAN tag insertion as part inline data. */
2760 mlx5_tx_mseg_memcpy(pdst, loc,
2761 2 * RTE_ETHER_ADDR_LEN,
2762 2 * RTE_ETHER_ADDR_LEN, olx);
2763 pdst += 2 * RTE_ETHER_ADDR_LEN;
2764 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2765 ((RTE_ETHER_TYPE_VLAN << 16) |
2766 loc->mbuf->vlan_tci);
2767 pdst += sizeof(struct rte_vlan_hdr);
2768 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2770 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2772 * The WQEBB space availability is checked by caller.
2773 * Here we should be aware of WQE ring buffer wraparound only.
2775 part = (uint8_t *)txq->wqes_end - pdst;
2776 part = RTE_MIN(part, inlen - tlen);
2782 * Copying may be interrupted inside the routine
2783 * if run into no inline hint flag.
2785 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2786 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2788 if (likely(inlen <= tlen) || copy < part) {
2789 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2791 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2792 return (struct mlx5_wqe_dseg *)pdst;
2794 pdst = (uint8_t *)txq->wqes;
2795 part = inlen - tlen;
2800 * Build the Data Segment of pointer type.
2803 * Pointer to TX queue structure.
2805 * Pointer to burst routine local context.
2807 * Pointer to WQE to fill with built Data Segment.
2809 * Data buffer to point.
2811 * Data buffer length.
2813 * Configured Tx offloads mask. It is fully defined at
2814 * compile time and may be used for optimization.
2816 static __rte_always_inline void
2817 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2818 struct mlx5_txq_local *__rte_restrict loc,
2819 struct mlx5_wqe_dseg *__rte_restrict dseg,
2822 unsigned int olx __rte_unused)
2826 dseg->bcount = rte_cpu_to_be_32(len);
2827 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2828 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2832 * Build the Data Segment of pointer type or inline
2833 * if data length is less than buffer in minimal
2834 * Data Segment size.
2837 * Pointer to TX queue structure.
2839 * Pointer to burst routine local context.
2841 * Pointer to WQE to fill with built Data Segment.
2843 * Data buffer to point.
2845 * Data buffer length.
2847 * Configured Tx offloads mask. It is fully defined at
2848 * compile time and may be used for optimization.
2850 static __rte_always_inline void
2851 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2852 struct mlx5_txq_local *__rte_restrict loc,
2853 struct mlx5_wqe_dseg *__rte_restrict dseg,
2856 unsigned int olx __rte_unused)
2862 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2863 dseg->bcount = rte_cpu_to_be_32(len);
2864 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2865 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2869 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2870 /* Unrolled implementation of generic rte_memcpy. */
2871 dst = (uintptr_t)&dseg->inline_data[0];
2872 src = (uintptr_t)buf;
2874 #ifdef RTE_ARCH_STRICT_ALIGN
2875 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2876 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2877 dst += sizeof(uint32_t);
2878 src += sizeof(uint32_t);
2879 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2880 dst += sizeof(uint32_t);
2881 src += sizeof(uint32_t);
2883 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2884 dst += sizeof(uint64_t);
2885 src += sizeof(uint64_t);
2889 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2890 dst += sizeof(uint32_t);
2891 src += sizeof(uint32_t);
2894 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2895 dst += sizeof(uint16_t);
2896 src += sizeof(uint16_t);
2899 *(uint8_t *)dst = *(uint8_t *)src;
2903 * Build the Data Segment of inlined data from single
2904 * segment packet, no VLAN insertion.
2907 * Pointer to TX queue structure.
2909 * Pointer to burst routine local context.
2911 * Pointer to WQE to fill with built Data Segment.
2913 * Data buffer to point.
2915 * Data buffer length.
2917 * Configured Tx offloads mask. It is fully defined at
2918 * compile time and may be used for optimization.
2921 * Pointer to the next Data Segment after inlined data.
2922 * Ring buffer wraparound check is needed. We do not
2923 * do it here because it may not be needed for the
2924 * last packet in the eMPW session.
2926 static __rte_always_inline struct mlx5_wqe_dseg *
2927 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
2928 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2929 struct mlx5_wqe_dseg *__rte_restrict dseg,
2932 unsigned int olx __rte_unused)
2937 if (!MLX5_TXOFF_CONFIG(MPW)) {
2938 /* Store the descriptor byte counter for eMPW sessions. */
2939 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2940 pdst = &dseg->inline_data[0];
2942 /* The entire legacy MPW session counter is stored on close. */
2943 pdst = (uint8_t *)dseg;
2946 * The WQEBB space availability is checked by caller.
2947 * Here we should be aware of WQE ring buffer wraparound only.
2949 part = (uint8_t *)txq->wqes_end - pdst;
2950 part = RTE_MIN(part, len);
2952 rte_memcpy(pdst, buf, part);
2956 if (!MLX5_TXOFF_CONFIG(MPW))
2957 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2958 /* Note: no final wraparound check here. */
2959 return (struct mlx5_wqe_dseg *)pdst;
2961 pdst = (uint8_t *)txq->wqes;
2968 * Build the Data Segment of inlined data from single
2969 * segment packet with VLAN insertion.
2972 * Pointer to TX queue structure.
2974 * Pointer to burst routine local context.
2976 * Pointer to the dseg fill with built Data Segment.
2978 * Data buffer to point.
2980 * Data buffer length.
2982 * Configured Tx offloads mask. It is fully defined at
2983 * compile time and may be used for optimization.
2986 * Pointer to the next Data Segment after inlined data.
2987 * Ring buffer wraparound check is needed.
2989 static __rte_always_inline struct mlx5_wqe_dseg *
2990 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
2991 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2992 struct mlx5_wqe_dseg *__rte_restrict dseg,
2995 unsigned int olx __rte_unused)
3001 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
3002 if (!MLX5_TXOFF_CONFIG(MPW)) {
3003 /* Store the descriptor byte counter for eMPW sessions. */
3004 dseg->bcount = rte_cpu_to_be_32
3005 ((len + sizeof(struct rte_vlan_hdr)) |
3006 MLX5_ETH_WQE_DATA_INLINE);
3007 pdst = &dseg->inline_data[0];
3009 /* The entire legacy MPW session counter is stored on close. */
3010 pdst = (uint8_t *)dseg;
3012 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
3013 buf += MLX5_DSEG_MIN_INLINE_SIZE;
3014 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
3015 len -= MLX5_DSEG_MIN_INLINE_SIZE;
3016 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
3017 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
3018 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
3019 pdst = (uint8_t *)txq->wqes;
3020 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
3021 loc->mbuf->vlan_tci);
3022 pdst += sizeof(struct rte_vlan_hdr);
3024 * The WQEBB space availability is checked by caller.
3025 * Here we should be aware of WQE ring buffer wraparound only.
3027 part = (uint8_t *)txq->wqes_end - pdst;
3028 part = RTE_MIN(part, len);
3030 rte_memcpy(pdst, buf, part);
3034 if (!MLX5_TXOFF_CONFIG(MPW))
3035 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
3036 /* Note: no final wraparound check here. */
3037 return (struct mlx5_wqe_dseg *)pdst;
3039 pdst = (uint8_t *)txq->wqes;
3046 * Build the Ethernet Segment with optionally inlined data with
3047 * VLAN insertion and following Data Segments (if any) from
3048 * multi-segment packet. Used by ordinary send and TSO.
3051 * Pointer to TX queue structure.
3053 * Pointer to burst routine local context.
3055 * Pointer to WQE to fill with built Ethernet/Data Segments.
3057 * Length of VLAN header to insert, 0 means no VLAN insertion.
3059 * Data length to inline. For TSO this parameter specifies
3060 * exact value, for ordinary send routine can be aligned by
3061 * caller to provide better WQE space saving and data buffer
3062 * start address alignment. This length includes VLAN header
3065 * Zero means ordinary send, inlined data can be extended,
3066 * otherwise this is TSO, inlined data length is fixed.
3068 * Configured Tx offloads mask. It is fully defined at
3069 * compile time and may be used for optimization.
3072 * Actual size of built WQE in segments.
3074 static __rte_always_inline unsigned int
3075 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
3076 struct mlx5_txq_local *__rte_restrict loc,
3077 struct mlx5_wqe *__rte_restrict wqe,
3081 unsigned int olx __rte_unused)
3083 struct mlx5_wqe_dseg *__rte_restrict dseg;
3086 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3087 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3090 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3091 if (!loc->mbuf_nseg)
3094 * There are still some mbuf remaining, not inlined.
3095 * The first mbuf may be partially inlined and we
3096 * must process the possible non-zero data offset.
3098 if (loc->mbuf_off) {
3103 * Exhausted packets must be dropped before.
3104 * Non-zero offset means there are some data
3105 * remained in the packet.
3107 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3108 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3109 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3111 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3113 * Build the pointer/minimal data Data Segment.
3114 * Do ring buffer wrapping check in advance.
3116 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3117 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3118 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3119 /* Store the mbuf to be freed on completion. */
3120 MLX5_ASSERT(loc->elts_free);
3121 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3124 if (--loc->mbuf_nseg == 0)
3126 loc->mbuf = loc->mbuf->next;
3130 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3131 struct rte_mbuf *mbuf;
3133 /* Zero length segment found, just skip. */
3135 loc->mbuf = loc->mbuf->next;
3136 rte_pktmbuf_free_seg(mbuf);
3137 if (--loc->mbuf_nseg == 0)
3140 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3141 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3144 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3145 rte_pktmbuf_data_len(loc->mbuf), olx);
3146 MLX5_ASSERT(loc->elts_free);
3147 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3150 if (--loc->mbuf_nseg == 0)
3152 loc->mbuf = loc->mbuf->next;
3157 /* Calculate actual segments used from the dseg pointer. */
3158 if ((uintptr_t)wqe < (uintptr_t)dseg)
3159 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3161 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3162 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3167 * The routine checks timestamp flag in the current packet,
3168 * and push WAIT WQE into the queue if scheduling is required.
3171 * Pointer to TX queue structure.
3173 * Pointer to burst routine local context.
3175 * Configured Tx offloads mask. It is fully defined at
3176 * compile time and may be used for optimization.
3179 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3180 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
3181 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
3182 * Local context variables partially updated.
3184 static __rte_always_inline enum mlx5_txcmp_code
3185 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
3186 struct mlx5_txq_local *restrict loc,
3189 if (MLX5_TXOFF_CONFIG(TXPP) &&
3190 loc->mbuf->ol_flags & txq->ts_mask) {
3191 struct mlx5_wqe *wqe;
3196 * Estimate the required space quickly and roughly.
3197 * We would like to ensure the packet can be pushed
3198 * to the queue and we won't get the orphan WAIT WQE.
3200 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
3201 loc->elts_free < NB_SEGS(loc->mbuf))
3202 return MLX5_TXCMP_CODE_EXIT;
3203 /* Convert the timestamp into completion to wait. */
3204 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
3205 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
3206 if (unlikely(wci < 0))
3207 return MLX5_TXCMP_CODE_SINGLE;
3208 /* Build the WAIT WQE with specified completion. */
3209 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3210 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
3211 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
3214 return MLX5_TXCMP_CODE_MULTI;
3216 return MLX5_TXCMP_CODE_SINGLE;
3220 * Tx one packet function for multi-segment TSO. Supports all
3221 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3222 * sends one packet per WQE.
3224 * This routine is responsible for storing processed mbuf
3225 * into elts ring buffer and update elts_head.
3228 * Pointer to TX queue structure.
3230 * Pointer to burst routine local context.
3232 * Configured Tx offloads mask. It is fully defined at
3233 * compile time and may be used for optimization.
3236 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3237 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3238 * Local context variables partially updated.
3240 static __rte_always_inline enum mlx5_txcmp_code
3241 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3242 struct mlx5_txq_local *__rte_restrict loc,
3245 struct mlx5_wqe *__rte_restrict wqe;
3246 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3248 if (MLX5_TXOFF_CONFIG(TXPP)) {
3249 enum mlx5_txcmp_code wret;
3251 /* Generate WAIT for scheduling if requested. */
3252 wret = mlx5_tx_schedule_send(txq, loc, olx);
3253 if (wret == MLX5_TXCMP_CODE_EXIT)
3254 return MLX5_TXCMP_CODE_EXIT;
3255 if (wret == MLX5_TXCMP_CODE_ERROR)
3256 return MLX5_TXCMP_CODE_ERROR;
3259 * Calculate data length to be inlined to estimate
3260 * the required space in WQE ring buffer.
3262 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3263 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3264 vlan = sizeof(struct rte_vlan_hdr);
3265 inlen = loc->mbuf->l2_len + vlan +
3266 loc->mbuf->l3_len + loc->mbuf->l4_len;
3267 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3268 return MLX5_TXCMP_CODE_ERROR;
3269 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3270 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3271 /* Packet must contain all TSO headers. */
3272 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3273 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3274 inlen > (dlen + vlan)))
3275 return MLX5_TXCMP_CODE_ERROR;
3276 MLX5_ASSERT(inlen >= txq->inlen_mode);
3278 * Check whether there are enough free WQEBBs:
3280 * - Ethernet Segment
3281 * - First Segment of inlined Ethernet data
3282 * - ... data continued ...
3283 * - Data Segments of pointer/min inline type
3285 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3286 MLX5_ESEG_MIN_INLINE_SIZE +
3288 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3289 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3290 return MLX5_TXCMP_CODE_EXIT;
3291 /* Check for maximal WQE size. */
3292 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3293 return MLX5_TXCMP_CODE_ERROR;
3294 #ifdef MLX5_PMD_SOFT_COUNTERS
3295 /* Update sent data bytes/packets counters. */
3296 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3297 loc->mbuf->tso_segsz;
3299 * One will be added for mbuf itself
3300 * at the end of the mlx5_tx_burst from
3301 * loc->pkts_sent field.
3304 txq->stats.opackets += ntcp;
3305 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3307 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3308 loc->wqe_last = wqe;
3309 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3310 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3311 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3312 txq->wqe_ci += (ds + 3) / 4;
3313 loc->wqe_free -= (ds + 3) / 4;
3314 return MLX5_TXCMP_CODE_MULTI;
3318 * Tx one packet function for multi-segment SEND. Supports all
3319 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3320 * sends one packet per WQE, without any data inlining in
3323 * This routine is responsible for storing processed mbuf
3324 * into elts ring buffer and update elts_head.
3327 * Pointer to TX queue structure.
3329 * Pointer to burst routine local context.
3331 * Configured Tx offloads mask. It is fully defined at
3332 * compile time and may be used for optimization.
3335 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3336 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3337 * Local context variables partially updated.
3339 static __rte_always_inline enum mlx5_txcmp_code
3340 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3341 struct mlx5_txq_local *__rte_restrict loc,
3344 struct mlx5_wqe_dseg *__rte_restrict dseg;
3345 struct mlx5_wqe *__rte_restrict wqe;
3346 unsigned int ds, nseg;
3348 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3349 if (MLX5_TXOFF_CONFIG(TXPP)) {
3350 enum mlx5_txcmp_code wret;
3352 /* Generate WAIT for scheduling if requested. */
3353 wret = mlx5_tx_schedule_send(txq, loc, olx);
3354 if (wret == MLX5_TXCMP_CODE_EXIT)
3355 return MLX5_TXCMP_CODE_EXIT;
3356 if (wret == MLX5_TXCMP_CODE_ERROR)
3357 return MLX5_TXCMP_CODE_ERROR;
3360 * No inline at all, it means the CPU cycles saving
3361 * is prioritized at configuration, we should not
3362 * copy any packet data to WQE.
3364 nseg = NB_SEGS(loc->mbuf);
3366 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3367 return MLX5_TXCMP_CODE_EXIT;
3368 /* Check for maximal WQE size. */
3369 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3370 return MLX5_TXCMP_CODE_ERROR;
3372 * Some Tx offloads may cause an error if
3373 * packet is not long enough, check against
3374 * assumed minimal length.
3376 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3377 return MLX5_TXCMP_CODE_ERROR;
3378 #ifdef MLX5_PMD_SOFT_COUNTERS
3379 /* Update sent data bytes counter. */
3380 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3381 if (MLX5_TXOFF_CONFIG(VLAN) &&
3382 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3383 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3386 * SEND WQE, one WQEBB:
3387 * - Control Segment, SEND opcode
3388 * - Ethernet Segment, optional VLAN, no inline
3389 * - Data Segments, pointer only type
3391 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3392 loc->wqe_last = wqe;
3393 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3394 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3395 dseg = &wqe->dseg[0];
3397 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3398 struct rte_mbuf *mbuf;
3401 * Zero length segment found, have to
3402 * correct total size of WQE in segments.
3403 * It is supposed to be rare occasion, so
3404 * in normal case (no zero length segments)
3405 * we avoid extra writing to the Control
3409 wqe->cseg.sq_ds -= RTE_BE32(1);
3411 loc->mbuf = mbuf->next;
3412 rte_pktmbuf_free_seg(mbuf);
3418 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3419 rte_pktmbuf_data_len(loc->mbuf), olx);
3420 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3425 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3426 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3427 loc->mbuf = loc->mbuf->next;
3430 txq->wqe_ci += (ds + 3) / 4;
3431 loc->wqe_free -= (ds + 3) / 4;
3432 return MLX5_TXCMP_CODE_MULTI;
3436 * Tx one packet function for multi-segment SEND. Supports all
3437 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3438 * sends one packet per WQE, with data inlining in
3439 * Ethernet Segment and minimal Data Segments.
3441 * This routine is responsible for storing processed mbuf
3442 * into elts ring buffer and update elts_head.
3445 * Pointer to TX queue structure.
3447 * Pointer to burst routine local context.
3449 * Configured Tx offloads mask. It is fully defined at
3450 * compile time and may be used for optimization.
3453 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3454 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3455 * Local context variables partially updated.
3457 static __rte_always_inline enum mlx5_txcmp_code
3458 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3459 struct mlx5_txq_local *__rte_restrict loc,
3462 struct mlx5_wqe *__rte_restrict wqe;
3463 unsigned int ds, inlen, dlen, vlan = 0;
3465 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3466 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3467 if (MLX5_TXOFF_CONFIG(TXPP)) {
3468 enum mlx5_txcmp_code wret;
3470 /* Generate WAIT for scheduling if requested. */
3471 wret = mlx5_tx_schedule_send(txq, loc, olx);
3472 if (wret == MLX5_TXCMP_CODE_EXIT)
3473 return MLX5_TXCMP_CODE_EXIT;
3474 if (wret == MLX5_TXCMP_CODE_ERROR)
3475 return MLX5_TXCMP_CODE_ERROR;
3478 * First calculate data length to be inlined
3479 * to estimate the required space for WQE.
3481 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3482 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3483 vlan = sizeof(struct rte_vlan_hdr);
3484 inlen = dlen + vlan;
3485 /* Check against minimal length. */
3486 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3487 return MLX5_TXCMP_CODE_ERROR;
3488 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3489 if (inlen > txq->inlen_send ||
3490 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3491 struct rte_mbuf *mbuf;
3496 * Packet length exceeds the allowed inline
3497 * data length, check whether the minimal
3498 * inlining is required.
3500 if (txq->inlen_mode) {
3501 MLX5_ASSERT(txq->inlen_mode >=
3502 MLX5_ESEG_MIN_INLINE_SIZE);
3503 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3504 inlen = txq->inlen_mode;
3506 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3507 !vlan || txq->vlan_en) {
3509 * VLAN insertion will be done inside by HW.
3510 * It is not utmost effective - VLAN flag is
3511 * checked twice, but we should proceed the
3512 * inlining length correctly and take into
3513 * account the VLAN header being inserted.
3515 return mlx5_tx_packet_multi_send
3518 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3521 * Now we know the minimal amount of data is requested
3522 * to inline. Check whether we should inline the buffers
3523 * from the chain beginning to eliminate some mbufs.
3526 nxlen = rte_pktmbuf_data_len(mbuf);
3527 if (unlikely(nxlen <= txq->inlen_send)) {
3528 /* We can inline first mbuf at least. */
3529 if (nxlen < inlen) {
3532 /* Scan mbufs till inlen filled. */
3537 nxlen = rte_pktmbuf_data_len(mbuf);
3539 } while (unlikely(nxlen < inlen));
3540 if (unlikely(nxlen > txq->inlen_send)) {
3541 /* We cannot inline entire mbuf. */
3542 smlen = inlen - smlen;
3543 start = rte_pktmbuf_mtod_offset
3544 (mbuf, uintptr_t, smlen);
3551 /* There should be not end of packet. */
3553 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3554 } while (unlikely(nxlen < txq->inlen_send));
3556 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3558 * Check whether we can do inline to align start
3559 * address of data buffer to cacheline.
3562 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3563 if (unlikely(start)) {
3565 if (start <= txq->inlen_send)
3570 * Check whether there are enough free WQEBBs:
3572 * - Ethernet Segment
3573 * - First Segment of inlined Ethernet data
3574 * - ... data continued ...
3575 * - Data Segments of pointer/min inline type
3577 * Estimate the number of Data Segments conservatively,
3578 * supposing no any mbufs is being freed during inlining.
3580 MLX5_ASSERT(inlen <= txq->inlen_send);
3581 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3582 MLX5_ESEG_MIN_INLINE_SIZE +
3584 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3585 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3586 return MLX5_TXCMP_CODE_EXIT;
3587 /* Check for maximal WQE size. */
3588 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3589 return MLX5_TXCMP_CODE_ERROR;
3590 #ifdef MLX5_PMD_SOFT_COUNTERS
3591 /* Update sent data bytes/packets counters. */
3592 txq->stats.obytes += dlen + vlan;
3594 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3595 loc->wqe_last = wqe;
3596 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3597 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3598 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3599 txq->wqe_ci += (ds + 3) / 4;
3600 loc->wqe_free -= (ds + 3) / 4;
3601 return MLX5_TXCMP_CODE_MULTI;
3605 * Tx burst function for multi-segment packets. Supports all
3606 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3607 * sends one packet per WQE. Function stops sending if it
3608 * encounters the single-segment packet.
3610 * This routine is responsible for storing processed mbuf
3611 * into elts ring buffer and update elts_head.
3614 * Pointer to TX queue structure.
3616 * Packets to transmit.
3618 * Number of packets in array.
3620 * Pointer to burst routine local context.
3622 * Configured Tx offloads mask. It is fully defined at
3623 * compile time and may be used for optimization.
3626 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3627 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3628 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3629 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3630 * Local context variables updated.
3632 static __rte_always_inline enum mlx5_txcmp_code
3633 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3634 struct rte_mbuf **__rte_restrict pkts,
3635 unsigned int pkts_n,
3636 struct mlx5_txq_local *__rte_restrict loc,
3639 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3640 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3641 pkts += loc->pkts_sent + 1;
3642 pkts_n -= loc->pkts_sent;
3644 enum mlx5_txcmp_code ret;
3646 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3648 * Estimate the number of free elts quickly but
3649 * conservatively. Some segment may be fully inlined
3650 * and freed, ignore this here - precise estimation
3653 if (loc->elts_free < NB_SEGS(loc->mbuf))
3654 return MLX5_TXCMP_CODE_EXIT;
3655 if (MLX5_TXOFF_CONFIG(TSO) &&
3656 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3657 /* Proceed with multi-segment TSO. */
3658 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3659 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3660 /* Proceed with multi-segment SEND with inlining. */
3661 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3663 /* Proceed with multi-segment SEND w/o inlining. */
3664 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3666 if (ret == MLX5_TXCMP_CODE_EXIT)
3667 return MLX5_TXCMP_CODE_EXIT;
3668 if (ret == MLX5_TXCMP_CODE_ERROR)
3669 return MLX5_TXCMP_CODE_ERROR;
3670 /* WQE is built, go to the next packet. */
3673 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3674 return MLX5_TXCMP_CODE_EXIT;
3675 loc->mbuf = *pkts++;
3677 rte_prefetch0(*pkts);
3678 if (likely(NB_SEGS(loc->mbuf) > 1))
3680 /* Here ends the series of multi-segment packets. */
3681 if (MLX5_TXOFF_CONFIG(TSO) &&
3682 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3683 return MLX5_TXCMP_CODE_TSO;
3684 return MLX5_TXCMP_CODE_SINGLE;
3690 * Tx burst function for single-segment packets with TSO.
3691 * Supports all types of Tx offloads, except multi-packets.
3692 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3693 * Function stops sending if it encounters the multi-segment
3694 * packet or packet without TSO requested.
3696 * The routine is responsible for storing processed mbuf
3697 * into elts ring buffer and update elts_head if inline
3698 * offloads is requested due to possible early freeing
3699 * of the inlined mbufs (can not store pkts array in elts
3703 * Pointer to TX queue structure.
3705 * Packets to transmit.
3707 * Number of packets in array.
3709 * Pointer to burst routine local context.
3711 * Configured Tx offloads mask. It is fully defined at
3712 * compile time and may be used for optimization.
3715 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3716 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3717 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3718 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3719 * Local context variables updated.
3721 static __rte_always_inline enum mlx5_txcmp_code
3722 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3723 struct rte_mbuf **__rte_restrict pkts,
3724 unsigned int pkts_n,
3725 struct mlx5_txq_local *__rte_restrict loc,
3728 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3729 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3730 pkts += loc->pkts_sent + 1;
3731 pkts_n -= loc->pkts_sent;
3733 struct mlx5_wqe_dseg *__rte_restrict dseg;
3734 struct mlx5_wqe *__rte_restrict wqe;
3735 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3738 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3739 if (MLX5_TXOFF_CONFIG(TXPP)) {
3740 enum mlx5_txcmp_code wret;
3742 /* Generate WAIT for scheduling if requested. */
3743 wret = mlx5_tx_schedule_send(txq, loc, olx);
3744 if (wret == MLX5_TXCMP_CODE_EXIT)
3745 return MLX5_TXCMP_CODE_EXIT;
3746 if (wret == MLX5_TXCMP_CODE_ERROR)
3747 return MLX5_TXCMP_CODE_ERROR;
3749 dlen = rte_pktmbuf_data_len(loc->mbuf);
3750 if (MLX5_TXOFF_CONFIG(VLAN) &&
3751 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3752 vlan = sizeof(struct rte_vlan_hdr);
3755 * First calculate the WQE size to check
3756 * whether we have enough space in ring buffer.
3758 hlen = loc->mbuf->l2_len + vlan +
3759 loc->mbuf->l3_len + loc->mbuf->l4_len;
3760 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3761 return MLX5_TXCMP_CODE_ERROR;
3762 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3763 hlen += loc->mbuf->outer_l2_len +
3764 loc->mbuf->outer_l3_len;
3765 /* Segment must contain all TSO headers. */
3766 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3767 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3768 hlen > (dlen + vlan)))
3769 return MLX5_TXCMP_CODE_ERROR;
3771 * Check whether there are enough free WQEBBs:
3773 * - Ethernet Segment
3774 * - First Segment of inlined Ethernet data
3775 * - ... data continued ...
3776 * - Finishing Data Segment of pointer type
3778 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3779 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3780 if (loc->wqe_free < ((ds + 3) / 4))
3781 return MLX5_TXCMP_CODE_EXIT;
3782 #ifdef MLX5_PMD_SOFT_COUNTERS
3783 /* Update sent data bytes/packets counters. */
3784 ntcp = (dlen + vlan - hlen +
3785 loc->mbuf->tso_segsz - 1) /
3786 loc->mbuf->tso_segsz;
3788 * One will be added for mbuf itself at the end
3789 * of the mlx5_tx_burst from loc->pkts_sent field.
3792 txq->stats.opackets += ntcp;
3793 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3796 * Build the TSO WQE:
3798 * - Ethernet Segment with hlen bytes inlined
3799 * - Data Segment of pointer type
3801 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3802 loc->wqe_last = wqe;
3803 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3804 MLX5_OPCODE_TSO, olx);
3805 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3806 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3807 dlen -= hlen - vlan;
3808 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3810 * WQE is built, update the loop parameters
3811 * and go to the next packet.
3813 txq->wqe_ci += (ds + 3) / 4;
3814 loc->wqe_free -= (ds + 3) / 4;
3815 if (MLX5_TXOFF_CONFIG(INLINE))
3816 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3820 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3821 return MLX5_TXCMP_CODE_EXIT;
3822 loc->mbuf = *pkts++;
3824 rte_prefetch0(*pkts);
3825 if (MLX5_TXOFF_CONFIG(MULTI) &&
3826 unlikely(NB_SEGS(loc->mbuf) > 1))
3827 return MLX5_TXCMP_CODE_MULTI;
3828 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3829 return MLX5_TXCMP_CODE_SINGLE;
3830 /* Continue with the next TSO packet. */
3836 * Analyze the packet and select the best method to send.
3839 * Pointer to TX queue structure.
3841 * Pointer to burst routine local context.
3843 * Configured Tx offloads mask. It is fully defined at
3844 * compile time and may be used for optimization.
3846 * The predefined flag whether do complete check for
3847 * multi-segment packets and TSO.
3850 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3851 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3852 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3853 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3855 static __rte_always_inline enum mlx5_txcmp_code
3856 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3857 struct mlx5_txq_local *__rte_restrict loc,
3861 /* Check for multi-segment packet. */
3863 MLX5_TXOFF_CONFIG(MULTI) &&
3864 unlikely(NB_SEGS(loc->mbuf) > 1))
3865 return MLX5_TXCMP_CODE_MULTI;
3866 /* Check for TSO packet. */
3868 MLX5_TXOFF_CONFIG(TSO) &&
3869 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3870 return MLX5_TXCMP_CODE_TSO;
3871 /* Check if eMPW is enabled at all. */
3872 if (!MLX5_TXOFF_CONFIG(EMPW))
3873 return MLX5_TXCMP_CODE_SINGLE;
3874 /* Check if eMPW can be engaged. */
3875 if (MLX5_TXOFF_CONFIG(VLAN) &&
3876 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3877 (!MLX5_TXOFF_CONFIG(INLINE) ||
3878 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3879 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3881 * eMPW does not support VLAN insertion offload,
3882 * we have to inline the entire packet but
3883 * packet is too long for inlining.
3885 return MLX5_TXCMP_CODE_SINGLE;
3887 return MLX5_TXCMP_CODE_EMPW;
3891 * Check the next packet attributes to match with the eMPW batch ones.
3892 * In addition, for legacy MPW the packet length is checked either.
3895 * Pointer to TX queue structure.
3897 * Pointer to Ethernet Segment of eMPW batch.
3899 * Pointer to burst routine local context.
3901 * Length of previous packet in MPW descriptor.
3903 * Configured Tx offloads mask. It is fully defined at
3904 * compile time and may be used for optimization.
3907 * true - packet match with eMPW batch attributes.
3908 * false - no match, eMPW should be restarted.
3910 static __rte_always_inline bool
3911 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
3912 struct mlx5_wqe_eseg *__rte_restrict es,
3913 struct mlx5_txq_local *__rte_restrict loc,
3917 uint8_t swp_flags = 0;
3919 /* Compare the checksum flags, if any. */
3920 if (MLX5_TXOFF_CONFIG(CSUM) &&
3921 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3923 /* Compare the Software Parser offsets and flags. */
3924 if (MLX5_TXOFF_CONFIG(SWP) &&
3925 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3926 es->swp_flags != swp_flags))
3928 /* Fill metadata field if needed. */
3929 if (MLX5_TXOFF_CONFIG(METADATA) &&
3930 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3931 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3933 /* Legacy MPW can send packets with the same lengt only. */
3934 if (MLX5_TXOFF_CONFIG(MPW) &&
3935 dlen != rte_pktmbuf_data_len(loc->mbuf))
3937 /* There must be no VLAN packets in eMPW loop. */
3938 if (MLX5_TXOFF_CONFIG(VLAN))
3939 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3940 /* Check if the scheduling is requested. */
3941 if (MLX5_TXOFF_CONFIG(TXPP) &&
3942 loc->mbuf->ol_flags & txq->ts_mask)
3948 * Update send loop variables and WQE for eMPW loop
3949 * without data inlining. Number of Data Segments is
3950 * equal to the number of sent packets.
3953 * Pointer to TX queue structure.
3955 * Pointer to burst routine local context.
3957 * Number of packets/Data Segments/Packets.
3959 * Accumulated statistics, bytes sent
3961 * Configured Tx offloads mask. It is fully defined at
3962 * compile time and may be used for optimization.
3965 * true - packet match with eMPW batch attributes.
3966 * false - no match, eMPW should be restarted.
3968 static __rte_always_inline void
3969 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3970 struct mlx5_txq_local *__rte_restrict loc,
3973 unsigned int olx __rte_unused)
3975 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3976 #ifdef MLX5_PMD_SOFT_COUNTERS
3977 /* Update sent data bytes counter. */
3978 txq->stats.obytes += slen;
3982 loc->elts_free -= ds;
3983 loc->pkts_sent += ds;
3985 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3986 txq->wqe_ci += (ds + 3) / 4;
3987 loc->wqe_free -= (ds + 3) / 4;
3991 * Update send loop variables and WQE for eMPW loop
3992 * with data inlining. Gets the size of pushed descriptors
3993 * and data to the WQE.
3996 * Pointer to TX queue structure.
3998 * Pointer to burst routine local context.
4000 * Total size of descriptor/data in bytes.
4002 * Accumulated statistics, data bytes sent.
4004 * The base WQE for the eMPW/MPW descriptor.
4006 * Configured Tx offloads mask. It is fully defined at
4007 * compile time and may be used for optimization.
4010 * true - packet match with eMPW batch attributes.
4011 * false - no match, eMPW should be restarted.
4013 static __rte_always_inline void
4014 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
4015 struct mlx5_txq_local *__rte_restrict loc,
4018 struct mlx5_wqe *__rte_restrict wqem,
4019 unsigned int olx __rte_unused)
4021 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
4023 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4024 #ifdef MLX5_PMD_SOFT_COUNTERS
4025 /* Update sent data bytes counter. */
4026 txq->stats.obytes += slen;
4030 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
4032 * If the legacy MPW session contains the inline packets
4033 * we should set the only inline data segment length
4034 * and align the total length to the segment size.
4036 MLX5_ASSERT(len > sizeof(dseg->bcount));
4037 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
4038 MLX5_ETH_WQE_DATA_INLINE);
4039 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
4042 * The session is not legacy MPW or contains the
4043 * data buffer pointer segments.
4045 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
4046 len = len / MLX5_WSEG_SIZE + 2;
4048 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
4049 txq->wqe_ci += (len + 3) / 4;
4050 loc->wqe_free -= (len + 3) / 4;
4051 loc->wqe_last = wqem;
4055 * The set of Tx burst functions for single-segment packets
4056 * without TSO and with Multi-Packet Writing feature support.
4057 * Supports all types of Tx offloads, except multi-packets
4060 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4061 * as many packet per WQE as it can. If eMPW is not configured
4062 * or packet can not be sent with eMPW (VLAN insertion) the
4063 * ordinary SEND opcode is used and only one packet placed
4066 * Functions stop sending if it encounters the multi-segment
4067 * packet or packet with TSO requested.
4069 * The routines are responsible for storing processed mbuf
4070 * into elts ring buffer and update elts_head if inlining
4071 * offload is requested. Otherwise the copying mbufs to elts
4072 * can be postponed and completed at the end of burst routine.
4075 * Pointer to TX queue structure.
4077 * Packets to transmit.
4079 * Number of packets in array.
4081 * Pointer to burst routine local context.
4083 * Configured Tx offloads mask. It is fully defined at
4084 * compile time and may be used for optimization.
4087 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4088 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4089 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4090 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4091 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4092 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4094 * Local context variables updated.
4097 * The routine sends packets with MLX5_OPCODE_EMPW
4098 * without inlining, this is dedicated optimized branch.
4099 * No VLAN insertion is supported.
4101 static __rte_always_inline enum mlx5_txcmp_code
4102 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
4103 struct rte_mbuf **__rte_restrict pkts,
4104 unsigned int pkts_n,
4105 struct mlx5_txq_local *__rte_restrict loc,
4109 * Subroutine is the part of mlx5_tx_burst_single()
4110 * and sends single-segment packet with eMPW opcode
4111 * without data inlining.
4113 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4114 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4115 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4116 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4117 pkts += loc->pkts_sent + 1;
4118 pkts_n -= loc->pkts_sent;
4120 struct mlx5_wqe_dseg *__rte_restrict dseg;
4121 struct mlx5_wqe_eseg *__rte_restrict eseg;
4122 enum mlx5_txcmp_code ret;
4123 unsigned int part, loop;
4124 unsigned int slen = 0;
4127 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4128 if (MLX5_TXOFF_CONFIG(TXPP)) {
4129 enum mlx5_txcmp_code wret;
4131 /* Generate WAIT for scheduling if requested. */
4132 wret = mlx5_tx_schedule_send(txq, loc, olx);
4133 if (wret == MLX5_TXCMP_CODE_EXIT)
4134 return MLX5_TXCMP_CODE_EXIT;
4135 if (wret == MLX5_TXCMP_CODE_ERROR)
4136 return MLX5_TXCMP_CODE_ERROR;
4138 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4139 MLX5_MPW_MAX_PACKETS :
4140 MLX5_EMPW_MAX_PACKETS);
4141 if (unlikely(loc->elts_free < part)) {
4142 /* We have no enough elts to save all mbufs. */
4143 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4144 return MLX5_TXCMP_CODE_EXIT;
4145 /* But we still able to send at least minimal eMPW. */
4146 part = loc->elts_free;
4148 /* Check whether we have enough WQEs */
4149 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4150 if (unlikely(loc->wqe_free <
4151 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4152 return MLX5_TXCMP_CODE_EXIT;
4153 part = (loc->wqe_free * 4) - 2;
4155 if (likely(part > 1))
4156 rte_prefetch0(*pkts);
4157 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4159 * Build eMPW title WQEBB:
4160 * - Control Segment, eMPW opcode
4161 * - Ethernet Segment, no inline
4163 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4164 MLX5_OPCODE_ENHANCED_MPSW, olx);
4165 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4166 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4167 eseg = &loc->wqe_last->eseg;
4168 dseg = &loc->wqe_last->dseg[0];
4170 /* Store the packet length for legacy MPW. */
4171 if (MLX5_TXOFF_CONFIG(MPW))
4172 eseg->mss = rte_cpu_to_be_16
4173 (rte_pktmbuf_data_len(loc->mbuf));
4175 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4176 #ifdef MLX5_PMD_SOFT_COUNTERS
4177 /* Update sent data bytes counter. */
4182 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4184 if (unlikely(--loop == 0))
4186 loc->mbuf = *pkts++;
4187 if (likely(loop > 1))
4188 rte_prefetch0(*pkts);
4189 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4191 * Unroll the completion code to avoid
4192 * returning variable value - it results in
4193 * unoptimized sequent checking in caller.
4195 if (ret == MLX5_TXCMP_CODE_MULTI) {
4197 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4198 if (unlikely(!loc->elts_free ||
4200 return MLX5_TXCMP_CODE_EXIT;
4201 return MLX5_TXCMP_CODE_MULTI;
4203 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4204 if (ret == MLX5_TXCMP_CODE_TSO) {
4206 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4207 if (unlikely(!loc->elts_free ||
4209 return MLX5_TXCMP_CODE_EXIT;
4210 return MLX5_TXCMP_CODE_TSO;
4212 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4214 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4215 if (unlikely(!loc->elts_free ||
4217 return MLX5_TXCMP_CODE_EXIT;
4218 return MLX5_TXCMP_CODE_SINGLE;
4220 if (ret != MLX5_TXCMP_CODE_EMPW) {
4223 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4224 return MLX5_TXCMP_CODE_ERROR;
4227 * Check whether packet parameters coincide
4228 * within assumed eMPW batch:
4229 * - check sum settings
4231 * - software parser settings
4232 * - packets length (legacy MPW only)
4233 * - scheduling is not required
4235 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4238 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4239 if (unlikely(!loc->elts_free ||
4241 return MLX5_TXCMP_CODE_EXIT;
4245 /* Packet attributes match, continue the same eMPW. */
4247 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4248 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4250 /* eMPW is built successfully, update loop parameters. */
4252 MLX5_ASSERT(pkts_n >= part);
4253 #ifdef MLX5_PMD_SOFT_COUNTERS
4254 /* Update sent data bytes counter. */
4255 txq->stats.obytes += slen;
4257 loc->elts_free -= part;
4258 loc->pkts_sent += part;
4259 txq->wqe_ci += (2 + part + 3) / 4;
4260 loc->wqe_free -= (2 + part + 3) / 4;
4262 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4263 return MLX5_TXCMP_CODE_EXIT;
4264 loc->mbuf = *pkts++;
4265 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4266 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4268 /* Continue sending eMPW batches. */
4274 * The routine sends packets with MLX5_OPCODE_EMPW
4275 * with inlining, optionally supports VLAN insertion.
4277 static __rte_always_inline enum mlx5_txcmp_code
4278 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4279 struct rte_mbuf **__rte_restrict pkts,
4280 unsigned int pkts_n,
4281 struct mlx5_txq_local *__rte_restrict loc,
4285 * Subroutine is the part of mlx5_tx_burst_single()
4286 * and sends single-segment packet with eMPW opcode
4287 * with data inlining.
4289 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4290 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4291 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4292 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4293 pkts += loc->pkts_sent + 1;
4294 pkts_n -= loc->pkts_sent;
4296 struct mlx5_wqe_dseg *__rte_restrict dseg;
4297 struct mlx5_wqe *__rte_restrict wqem;
4298 enum mlx5_txcmp_code ret;
4299 unsigned int room, part, nlim;
4300 unsigned int slen = 0;
4302 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4303 if (MLX5_TXOFF_CONFIG(TXPP)) {
4304 enum mlx5_txcmp_code wret;
4306 /* Generate WAIT for scheduling if requested. */
4307 wret = mlx5_tx_schedule_send(txq, loc, olx);
4308 if (wret == MLX5_TXCMP_CODE_EXIT)
4309 return MLX5_TXCMP_CODE_EXIT;
4310 if (wret == MLX5_TXCMP_CODE_ERROR)
4311 return MLX5_TXCMP_CODE_ERROR;
4314 * Limits the amount of packets in one WQE
4315 * to improve CQE latency generation.
4317 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4318 MLX5_MPW_INLINE_MAX_PACKETS :
4319 MLX5_EMPW_MAX_PACKETS);
4320 /* Check whether we have minimal amount WQEs */
4321 if (unlikely(loc->wqe_free <
4322 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4323 return MLX5_TXCMP_CODE_EXIT;
4324 if (likely(pkts_n > 1))
4325 rte_prefetch0(*pkts);
4326 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4328 * Build eMPW title WQEBB:
4329 * - Control Segment, eMPW opcode, zero DS
4330 * - Ethernet Segment, no inline
4332 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4333 MLX5_OPCODE_ENHANCED_MPSW, olx);
4334 mlx5_tx_eseg_none(txq, loc, wqem,
4335 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4336 dseg = &wqem->dseg[0];
4337 /* Store the packet length for legacy MPW. */
4338 if (MLX5_TXOFF_CONFIG(MPW))
4339 wqem->eseg.mss = rte_cpu_to_be_16
4340 (rte_pktmbuf_data_len(loc->mbuf));
4341 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4342 loc->wqe_free) * MLX5_WQE_SIZE -
4343 MLX5_WQE_CSEG_SIZE -
4345 /* Limit the room for legacy MPW sessions for performance. */
4346 if (MLX5_TXOFF_CONFIG(MPW))
4347 room = RTE_MIN(room,
4348 RTE_MAX(txq->inlen_empw +
4349 sizeof(dseg->bcount) +
4350 (MLX5_TXOFF_CONFIG(VLAN) ?
4351 sizeof(struct rte_vlan_hdr) : 0),
4352 MLX5_MPW_INLINE_MAX_PACKETS *
4353 MLX5_WQE_DSEG_SIZE));
4354 /* Build WQE till we have space, packets and resources. */
4357 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4358 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4361 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4362 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4363 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4365 * Some Tx offloads may cause an error if
4366 * packet is not long enough, check against
4367 * assumed minimal length.
4369 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4371 if (unlikely(!part))
4372 return MLX5_TXCMP_CODE_ERROR;
4374 * We have some successfully built
4375 * packet Data Segments to send.
4377 mlx5_tx_idone_empw(txq, loc, part,
4379 return MLX5_TXCMP_CODE_ERROR;
4381 /* Inline or not inline - that's the Question. */
4382 if (dlen > txq->inlen_empw ||
4383 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4385 if (MLX5_TXOFF_CONFIG(MPW)) {
4386 if (dlen > txq->inlen_send)
4390 /* Open new inline MPW session. */
4391 tlen += sizeof(dseg->bcount);
4392 dseg->bcount = RTE_BE32(0);
4394 (dseg, sizeof(dseg->bcount));
4397 * No pointer and inline descriptor
4398 * intermix for legacy MPW sessions.
4400 if (wqem->dseg[0].bcount)
4404 tlen = sizeof(dseg->bcount) + dlen;
4406 /* Inline entire packet, optional VLAN insertion. */
4407 if (MLX5_TXOFF_CONFIG(VLAN) &&
4408 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4410 * The packet length must be checked in
4411 * mlx5_tx_able_to_empw() and packet
4412 * fits into inline length guaranteed.
4415 sizeof(struct rte_vlan_hdr)) <=
4417 tlen += sizeof(struct rte_vlan_hdr);
4420 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4422 #ifdef MLX5_PMD_SOFT_COUNTERS
4423 /* Update sent data bytes counter. */
4424 slen += sizeof(struct rte_vlan_hdr);
4429 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4432 if (!MLX5_TXOFF_CONFIG(MPW))
4433 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4434 MLX5_ASSERT(room >= tlen);
4437 * Packet data are completely inline,
4438 * we can try to free the packet.
4440 if (likely(loc->pkts_sent == loc->mbuf_free)) {
4442 * All the packets from the burst beginning
4443 * are inline, we can free mbufs directly
4444 * from the origin array on tx_burst exit().
4450 * In order no to call rte_pktmbuf_free_seg() here,
4451 * in the most inner loop (that might be very
4452 * expensive) we just save the mbuf in elts.
4454 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4459 * No pointer and inline descriptor
4460 * intermix for legacy MPW sessions.
4462 if (MLX5_TXOFF_CONFIG(MPW) &&
4464 wqem->dseg[0].bcount == RTE_BE32(0))
4467 * Not inlinable VLAN packets are
4468 * proceeded outside of this routine.
4470 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4471 if (MLX5_TXOFF_CONFIG(VLAN))
4472 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4474 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4475 /* We have to store mbuf in elts.*/
4476 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4478 room -= MLX5_WQE_DSEG_SIZE;
4479 /* Ring buffer wraparound is checked at the loop end.*/
4482 #ifdef MLX5_PMD_SOFT_COUNTERS
4483 /* Update sent data bytes counter. */
4488 if (unlikely(!pkts_n || !loc->elts_free)) {
4490 * We have no resources/packets to
4491 * continue build descriptors.
4494 mlx5_tx_idone_empw(txq, loc, part,
4496 return MLX5_TXCMP_CODE_EXIT;
4498 loc->mbuf = *pkts++;
4499 if (likely(pkts_n > 1))
4500 rte_prefetch0(*pkts);
4501 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4503 * Unroll the completion code to avoid
4504 * returning variable value - it results in
4505 * unoptimized sequent checking in caller.
4507 if (ret == MLX5_TXCMP_CODE_MULTI) {
4509 mlx5_tx_idone_empw(txq, loc, part,
4511 if (unlikely(!loc->elts_free ||
4513 return MLX5_TXCMP_CODE_EXIT;
4514 return MLX5_TXCMP_CODE_MULTI;
4516 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4517 if (ret == MLX5_TXCMP_CODE_TSO) {
4519 mlx5_tx_idone_empw(txq, loc, part,
4521 if (unlikely(!loc->elts_free ||
4523 return MLX5_TXCMP_CODE_EXIT;
4524 return MLX5_TXCMP_CODE_TSO;
4526 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4528 mlx5_tx_idone_empw(txq, loc, part,
4530 if (unlikely(!loc->elts_free ||
4532 return MLX5_TXCMP_CODE_EXIT;
4533 return MLX5_TXCMP_CODE_SINGLE;
4535 if (ret != MLX5_TXCMP_CODE_EMPW) {
4538 mlx5_tx_idone_empw(txq, loc, part,
4540 return MLX5_TXCMP_CODE_ERROR;
4542 /* Check if we have minimal room left. */
4544 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4547 * Check whether packet parameters coincide
4548 * within assumed eMPW batch:
4549 * - check sum settings
4551 * - software parser settings
4552 * - packets length (legacy MPW only)
4553 * - scheduling is not required
4555 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4558 /* Packet attributes match, continue the same eMPW. */
4559 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4560 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4563 * We get here to close an existing eMPW
4564 * session and start the new one.
4566 MLX5_ASSERT(pkts_n);
4568 if (unlikely(!part))
4569 return MLX5_TXCMP_CODE_EXIT;
4570 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4571 if (unlikely(!loc->elts_free ||
4573 return MLX5_TXCMP_CODE_EXIT;
4574 /* Continue the loop with new eMPW session. */
4580 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4581 * Data inlining and VLAN insertion are supported.
4583 static __rte_always_inline enum mlx5_txcmp_code
4584 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4585 struct rte_mbuf **__rte_restrict pkts,
4586 unsigned int pkts_n,
4587 struct mlx5_txq_local *__rte_restrict loc,
4591 * Subroutine is the part of mlx5_tx_burst_single()
4592 * and sends single-segment packet with SEND opcode.
4594 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4595 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4596 pkts += loc->pkts_sent + 1;
4597 pkts_n -= loc->pkts_sent;
4599 struct mlx5_wqe *__rte_restrict wqe;
4600 enum mlx5_txcmp_code ret;
4602 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4603 if (MLX5_TXOFF_CONFIG(TXPP)) {
4604 enum mlx5_txcmp_code wret;
4606 /* Generate WAIT for scheduling if requested. */
4607 wret = mlx5_tx_schedule_send(txq, loc, olx);
4608 if (wret == MLX5_TXCMP_CODE_EXIT)
4609 return MLX5_TXCMP_CODE_EXIT;
4610 if (wret == MLX5_TXCMP_CODE_ERROR)
4611 return MLX5_TXCMP_CODE_ERROR;
4613 if (MLX5_TXOFF_CONFIG(INLINE)) {
4614 unsigned int inlen, vlan = 0;
4616 inlen = rte_pktmbuf_data_len(loc->mbuf);
4617 if (MLX5_TXOFF_CONFIG(VLAN) &&
4618 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4619 vlan = sizeof(struct rte_vlan_hdr);
4623 * If inlining is enabled at configuration time
4624 * the limit must be not less than minimal size.
4625 * Otherwise we would do extra check for data
4626 * size to avoid crashes due to length overflow.
4628 MLX5_ASSERT(txq->inlen_send >=
4629 MLX5_ESEG_MIN_INLINE_SIZE);
4630 if (inlen <= txq->inlen_send) {
4631 unsigned int seg_n, wqe_n;
4633 rte_prefetch0(rte_pktmbuf_mtod
4634 (loc->mbuf, uint8_t *));
4635 /* Check against minimal length. */
4636 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4637 return MLX5_TXCMP_CODE_ERROR;
4638 if (loc->mbuf->ol_flags &
4639 PKT_TX_DYNF_NOINLINE) {
4641 * The hint flag not to inline packet
4642 * data is set. Check whether we can
4645 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4647 (MLX5_TXOFF_CONFIG(MPW) &&
4649 if (inlen <= txq->inlen_send)
4652 * The hardware requires the
4653 * minimal inline data header.
4655 goto single_min_inline;
4657 if (MLX5_TXOFF_CONFIG(VLAN) &&
4658 vlan && !txq->vlan_en) {
4660 * We must insert VLAN tag
4661 * by software means.
4663 goto single_part_inline;
4665 goto single_no_inline;
4669 * Completely inlined packet data WQE:
4670 * - Control Segment, SEND opcode
4671 * - Ethernet Segment, no VLAN insertion
4672 * - Data inlined, VLAN optionally inserted
4673 * - Alignment to MLX5_WSEG_SIZE
4674 * Have to estimate amount of WQEBBs
4676 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4677 MLX5_ESEG_MIN_INLINE_SIZE +
4678 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4679 /* Check if there are enough WQEBBs. */
4680 wqe_n = (seg_n + 3) / 4;
4681 if (wqe_n > loc->wqe_free)
4682 return MLX5_TXCMP_CODE_EXIT;
4683 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4684 loc->wqe_last = wqe;
4685 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4686 MLX5_OPCODE_SEND, olx);
4687 mlx5_tx_eseg_data(txq, loc, wqe,
4688 vlan, inlen, 0, olx);
4689 txq->wqe_ci += wqe_n;
4690 loc->wqe_free -= wqe_n;
4692 * Packet data are completely inlined,
4693 * free the packet immediately.
4695 rte_pktmbuf_free_seg(loc->mbuf);
4696 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4697 MLX5_TXOFF_CONFIG(MPW)) &&
4700 * If minimal inlining is requested the eMPW
4701 * feature should be disabled due to data is
4702 * inlined into Ethernet Segment, which can
4703 * not contain inlined data for eMPW due to
4704 * segment shared for all packets.
4706 struct mlx5_wqe_dseg *__rte_restrict dseg;
4711 * The inline-mode settings require
4712 * to inline the specified amount of
4713 * data bytes to the Ethernet Segment.
4714 * We should check the free space in
4715 * WQE ring buffer to inline partially.
4718 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4719 MLX5_ASSERT(inlen > txq->inlen_mode);
4720 MLX5_ASSERT(txq->inlen_mode >=
4721 MLX5_ESEG_MIN_INLINE_SIZE);
4723 * Check whether there are enough free WQEBBs:
4725 * - Ethernet Segment
4726 * - First Segment of inlined Ethernet data
4727 * - ... data continued ...
4728 * - Finishing Data Segment of pointer type
4730 ds = (MLX5_WQE_CSEG_SIZE +
4731 MLX5_WQE_ESEG_SIZE +
4732 MLX5_WQE_DSEG_SIZE +
4734 MLX5_ESEG_MIN_INLINE_SIZE +
4735 MLX5_WQE_DSEG_SIZE +
4736 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4737 if (loc->wqe_free < ((ds + 3) / 4))
4738 return MLX5_TXCMP_CODE_EXIT;
4740 * Build the ordinary SEND WQE:
4742 * - Ethernet Segment, inline inlen_mode bytes
4743 * - Data Segment of pointer type
4745 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4746 loc->wqe_last = wqe;
4747 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4748 MLX5_OPCODE_SEND, olx);
4749 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4752 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4753 txq->inlen_mode - vlan;
4754 inlen -= txq->inlen_mode;
4755 mlx5_tx_dseg_ptr(txq, loc, dseg,
4758 * WQE is built, update the loop parameters
4759 * and got to the next packet.
4761 txq->wqe_ci += (ds + 3) / 4;
4762 loc->wqe_free -= (ds + 3) / 4;
4763 /* We have to store mbuf in elts.*/
4764 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4765 txq->elts[txq->elts_head++ & txq->elts_m] =
4773 * Partially inlined packet data WQE, we have
4774 * some space in title WQEBB, we can fill it
4775 * with some packet data. It takes one WQEBB,
4776 * it is available, no extra space check:
4777 * - Control Segment, SEND opcode
4778 * - Ethernet Segment, no VLAN insertion
4779 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4780 * - Data Segment, pointer type
4782 * We also get here if VLAN insertion is not
4783 * supported by HW, the inline is enabled.
4786 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4787 loc->wqe_last = wqe;
4788 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4789 MLX5_OPCODE_SEND, olx);
4790 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4791 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4792 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4794 * The length check is performed above, by
4795 * comparing with txq->inlen_send. We should
4796 * not get overflow here.
4798 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4799 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4800 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4804 /* We have to store mbuf in elts.*/
4805 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4806 txq->elts[txq->elts_head++ & txq->elts_m] =
4810 #ifdef MLX5_PMD_SOFT_COUNTERS
4811 /* Update sent data bytes counter. */
4812 txq->stats.obytes += vlan +
4813 rte_pktmbuf_data_len(loc->mbuf);
4817 * No inline at all, it means the CPU cycles saving
4818 * is prioritized at configuration, we should not
4819 * copy any packet data to WQE.
4821 * SEND WQE, one WQEBB:
4822 * - Control Segment, SEND opcode
4823 * - Ethernet Segment, optional VLAN, no inline
4824 * - Data Segment, pointer type
4827 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4828 loc->wqe_last = wqe;
4829 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4830 MLX5_OPCODE_SEND, olx);
4831 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4833 (txq, loc, &wqe->dseg[0],
4834 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4835 rte_pktmbuf_data_len(loc->mbuf), olx);
4839 * We should not store mbuf pointer in elts
4840 * if no inlining is configured, this is done
4841 * by calling routine in a batch copy.
4843 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4845 #ifdef MLX5_PMD_SOFT_COUNTERS
4846 /* Update sent data bytes counter. */
4847 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4848 if (MLX5_TXOFF_CONFIG(VLAN) &&
4849 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4850 txq->stats.obytes +=
4851 sizeof(struct rte_vlan_hdr);
4856 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4857 return MLX5_TXCMP_CODE_EXIT;
4858 loc->mbuf = *pkts++;
4860 rte_prefetch0(*pkts);
4861 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4862 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4868 static __rte_always_inline enum mlx5_txcmp_code
4869 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4870 struct rte_mbuf **__rte_restrict pkts,
4871 unsigned int pkts_n,
4872 struct mlx5_txq_local *__rte_restrict loc,
4875 enum mlx5_txcmp_code ret;
4877 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4878 if (ret == MLX5_TXCMP_CODE_SINGLE)
4880 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4882 /* Optimize for inline/no inline eMPW send. */
4883 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4884 mlx5_tx_burst_empw_inline
4885 (txq, pkts, pkts_n, loc, olx) :
4886 mlx5_tx_burst_empw_simple
4887 (txq, pkts, pkts_n, loc, olx);
4888 if (ret != MLX5_TXCMP_CODE_SINGLE)
4890 /* The resources to send one packet should remain. */
4891 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4893 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4894 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4895 if (ret != MLX5_TXCMP_CODE_EMPW)
4897 /* The resources to send one packet should remain. */
4898 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4903 * DPDK Tx callback template. This is configured template
4904 * used to generate routines optimized for specified offload setup.
4905 * One of this generated functions is chosen at SQ configuration
4909 * Generic pointer to TX queue structure.
4911 * Packets to transmit.
4913 * Number of packets in array.
4915 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4916 * values. Should be static to take compile time static configuration
4920 * Number of packets successfully transmitted (<= pkts_n).
4922 static __rte_always_inline uint16_t
4923 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4924 struct rte_mbuf **__rte_restrict pkts,
4928 struct mlx5_txq_local loc;
4929 enum mlx5_txcmp_code ret;
4932 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4933 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4934 if (unlikely(!pkts_n))
4936 if (MLX5_TXOFF_CONFIG(INLINE))
4940 loc.wqe_last = NULL;
4943 loc.pkts_loop = loc.pkts_sent;
4945 * Check if there are some CQEs, if any:
4946 * - process an encountered errors
4947 * - process the completed WQEs
4948 * - free related mbufs
4949 * - doorbell the NIC about processed CQEs
4951 rte_prefetch0(*(pkts + loc.pkts_sent));
4952 mlx5_tx_handle_completion(txq, olx);
4954 * Calculate the number of available resources - elts and WQEs.
4955 * There are two possible different scenarios:
4956 * - no data inlining into WQEs, one WQEBB may contains up to
4957 * four packets, in this case elts become scarce resource
4958 * - data inlining into WQEs, one packet may require multiple
4959 * WQEBBs, the WQEs become the limiting factor.
4961 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4962 loc.elts_free = txq->elts_s -
4963 (uint16_t)(txq->elts_head - txq->elts_tail);
4964 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4965 loc.wqe_free = txq->wqe_s -
4966 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4967 if (unlikely(!loc.elts_free || !loc.wqe_free))
4971 * Fetch the packet from array. Usually this is
4972 * the first packet in series of multi/single
4975 loc.mbuf = *(pkts + loc.pkts_sent);
4976 /* Dedicated branch for multi-segment packets. */
4977 if (MLX5_TXOFF_CONFIG(MULTI) &&
4978 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4980 * Multi-segment packet encountered.
4981 * Hardware is able to process it only
4982 * with SEND/TSO opcodes, one packet
4983 * per WQE, do it in dedicated routine.
4986 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4987 part = loc.pkts_sent - loc.pkts_copy;
4988 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4990 * There are some single-segment mbufs not
4991 * stored in elts. The mbufs must be in the
4992 * same order as WQEs, so we must copy the
4993 * mbufs to elts here, before the coming
4994 * multi-segment packet mbufs is appended.
4996 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4998 loc.pkts_copy = loc.pkts_sent;
5000 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5001 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
5002 if (!MLX5_TXOFF_CONFIG(INLINE))
5003 loc.pkts_copy = loc.pkts_sent;
5005 * These returned code checks are supposed
5006 * to be optimized out due to routine inlining.
5008 if (ret == MLX5_TXCMP_CODE_EXIT) {
5010 * The routine returns this code when
5011 * all packets are sent or there is no
5012 * enough resources to complete request.
5016 if (ret == MLX5_TXCMP_CODE_ERROR) {
5018 * The routine returns this code when
5019 * some error in the incoming packets
5022 txq->stats.oerrors++;
5025 if (ret == MLX5_TXCMP_CODE_SINGLE) {
5027 * The single-segment packet was encountered
5028 * in the array, try to send it with the
5029 * best optimized way, possible engaging eMPW.
5031 goto enter_send_single;
5033 if (MLX5_TXOFF_CONFIG(TSO) &&
5034 ret == MLX5_TXCMP_CODE_TSO) {
5036 * The single-segment TSO packet was
5037 * encountered in the array.
5039 goto enter_send_tso;
5041 /* We must not get here. Something is going wrong. */
5043 txq->stats.oerrors++;
5046 /* Dedicated branch for single-segment TSO packets. */
5047 if (MLX5_TXOFF_CONFIG(TSO) &&
5048 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
5050 * TSO might require special way for inlining
5051 * (dedicated parameters) and is sent with
5052 * MLX5_OPCODE_TSO opcode only, provide this
5053 * in dedicated branch.
5056 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
5057 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5058 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
5060 * These returned code checks are supposed
5061 * to be optimized out due to routine inlining.
5063 if (ret == MLX5_TXCMP_CODE_EXIT)
5065 if (ret == MLX5_TXCMP_CODE_ERROR) {
5066 txq->stats.oerrors++;
5069 if (ret == MLX5_TXCMP_CODE_SINGLE)
5070 goto enter_send_single;
5071 if (MLX5_TXOFF_CONFIG(MULTI) &&
5072 ret == MLX5_TXCMP_CODE_MULTI) {
5074 * The multi-segment packet was
5075 * encountered in the array.
5077 goto enter_send_multi;
5079 /* We must not get here. Something is going wrong. */
5081 txq->stats.oerrors++;
5085 * The dedicated branch for the single-segment packets
5086 * without TSO. Often these ones can be sent using
5087 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
5088 * The routine builds the WQEs till it encounters
5089 * the TSO or multi-segment packet (in case if these
5090 * offloads are requested at SQ configuration time).
5093 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5094 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
5096 * These returned code checks are supposed
5097 * to be optimized out due to routine inlining.
5099 if (ret == MLX5_TXCMP_CODE_EXIT)
5101 if (ret == MLX5_TXCMP_CODE_ERROR) {
5102 txq->stats.oerrors++;
5105 if (MLX5_TXOFF_CONFIG(MULTI) &&
5106 ret == MLX5_TXCMP_CODE_MULTI) {
5108 * The multi-segment packet was
5109 * encountered in the array.
5111 goto enter_send_multi;
5113 if (MLX5_TXOFF_CONFIG(TSO) &&
5114 ret == MLX5_TXCMP_CODE_TSO) {
5116 * The single-segment TSO packet was
5117 * encountered in the array.
5119 goto enter_send_tso;
5121 /* We must not get here. Something is going wrong. */
5123 txq->stats.oerrors++;
5127 * Main Tx loop is completed, do the rest:
5128 * - set completion request if thresholds are reached
5129 * - doorbell the hardware
5130 * - copy the rest of mbufs to elts (if any)
5132 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5133 loc.pkts_sent >= loc.pkts_copy);
5134 /* Take a shortcut if nothing is sent. */
5135 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5137 /* Request CQE generation if limits are reached. */
5138 mlx5_tx_request_completion(txq, &loc, olx);
5140 * Ring QP doorbell immediately after WQE building completion
5141 * to improve latencies. The pure software related data treatment
5142 * can be completed after doorbell. Tx CQEs for this SQ are
5143 * processed in this thread only by the polling.
5145 * The rdma core library can map doorbell register in two ways,
5146 * depending on the environment variable "MLX5_SHUT_UP_BF":
5148 * - as regular cached memory, the variable is either missing or
5149 * set to zero. This type of mapping may cause the significant
5150 * doorbell register writing latency and requires explicit
5151 * memory write barrier to mitigate this issue and prevent
5154 * - as non-cached memory, the variable is present and set to
5155 * not "0" value. This type of mapping may cause performance
5156 * impact under heavy loading conditions but the explicit write
5157 * memory barrier is not required and it may improve core
5160 * - the legacy behaviour (prior 19.08 release) was to use some
5161 * heuristics to decide whether write memory barrier should
5162 * be performed. This behavior is supported with specifying
5163 * tx_db_nc=2, write barrier is skipped if application
5164 * provides the full recommended burst of packets, it
5165 * supposes the next packets are coming and the write barrier
5166 * will be issued on the next burst (after descriptor writing,
5169 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5170 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5171 /* Not all of the mbufs may be stored into elts yet. */
5172 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5173 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5175 * There are some single-segment mbufs not stored in elts.
5176 * It can be only if the last packet was single-segment.
5177 * The copying is gathered into one place due to it is
5178 * a good opportunity to optimize that with SIMD.
5179 * Unfortunately if inlining is enabled the gaps in
5180 * pointer array may happen due to early freeing of the
5183 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5184 loc.pkts_copy = loc.pkts_sent;
5186 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5187 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5188 if (pkts_n > loc.pkts_sent) {
5190 * If burst size is large there might be no enough CQE
5191 * fetched from completion queue and no enough resources
5192 * freed to send all the packets.
5197 #ifdef MLX5_PMD_SOFT_COUNTERS
5198 /* Increment sent packets counter. */
5199 txq->stats.opackets += loc.pkts_sent;
5201 if (MLX5_TXOFF_CONFIG(INLINE) && loc.mbuf_free)
5202 __mlx5_tx_free_mbuf(txq, pkts, loc.mbuf_free, olx);
5203 return loc.pkts_sent;
5206 /* Generate routines with Enhanced Multi-Packet Write support. */
5207 MLX5_TXOFF_DECL(full_empw,
5208 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5210 MLX5_TXOFF_DECL(none_empw,
5211 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5213 MLX5_TXOFF_DECL(md_empw,
5214 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5216 MLX5_TXOFF_DECL(mt_empw,
5217 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5218 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5220 MLX5_TXOFF_DECL(mtsc_empw,
5221 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5222 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5223 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5225 MLX5_TXOFF_DECL(mti_empw,
5226 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5227 MLX5_TXOFF_CONFIG_INLINE |
5228 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5230 MLX5_TXOFF_DECL(mtv_empw,
5231 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5232 MLX5_TXOFF_CONFIG_VLAN |
5233 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5235 MLX5_TXOFF_DECL(mtiv_empw,
5236 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5237 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5238 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5240 MLX5_TXOFF_DECL(sc_empw,
5241 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5242 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5244 MLX5_TXOFF_DECL(sci_empw,
5245 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5246 MLX5_TXOFF_CONFIG_INLINE |
5247 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5249 MLX5_TXOFF_DECL(scv_empw,
5250 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5251 MLX5_TXOFF_CONFIG_VLAN |
5252 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5254 MLX5_TXOFF_DECL(sciv_empw,
5255 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5256 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5257 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5259 MLX5_TXOFF_DECL(i_empw,
5260 MLX5_TXOFF_CONFIG_INLINE |
5261 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5263 MLX5_TXOFF_DECL(v_empw,
5264 MLX5_TXOFF_CONFIG_VLAN |
5265 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5267 MLX5_TXOFF_DECL(iv_empw,
5268 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5269 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5271 /* Generate routines without Enhanced Multi-Packet Write support. */
5272 MLX5_TXOFF_DECL(full,
5273 MLX5_TXOFF_CONFIG_FULL)
5275 MLX5_TXOFF_DECL(none,
5276 MLX5_TXOFF_CONFIG_NONE)
5279 MLX5_TXOFF_CONFIG_METADATA)
5282 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5283 MLX5_TXOFF_CONFIG_METADATA)
5285 MLX5_TXOFF_DECL(mtsc,
5286 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5287 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5288 MLX5_TXOFF_CONFIG_METADATA)
5290 MLX5_TXOFF_DECL(mti,
5291 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5292 MLX5_TXOFF_CONFIG_INLINE |
5293 MLX5_TXOFF_CONFIG_METADATA)
5296 MLX5_TXOFF_DECL(mtv,
5297 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5298 MLX5_TXOFF_CONFIG_VLAN |
5299 MLX5_TXOFF_CONFIG_METADATA)
5302 MLX5_TXOFF_DECL(mtiv,
5303 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5304 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5305 MLX5_TXOFF_CONFIG_METADATA)
5308 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5309 MLX5_TXOFF_CONFIG_METADATA)
5311 MLX5_TXOFF_DECL(sci,
5312 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5313 MLX5_TXOFF_CONFIG_INLINE |
5314 MLX5_TXOFF_CONFIG_METADATA)
5317 MLX5_TXOFF_DECL(scv,
5318 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5319 MLX5_TXOFF_CONFIG_VLAN |
5320 MLX5_TXOFF_CONFIG_METADATA)
5323 MLX5_TXOFF_DECL(sciv,
5324 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5325 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5326 MLX5_TXOFF_CONFIG_METADATA)
5329 MLX5_TXOFF_CONFIG_INLINE |
5330 MLX5_TXOFF_CONFIG_METADATA)
5333 MLX5_TXOFF_CONFIG_VLAN |
5334 MLX5_TXOFF_CONFIG_METADATA)
5337 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5338 MLX5_TXOFF_CONFIG_METADATA)
5340 /* Generate routines with timestamp scheduling. */
5341 MLX5_TXOFF_DECL(full_ts_nompw,
5342 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5344 MLX5_TXOFF_DECL(full_ts_nompwi,
5345 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5346 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5347 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5348 MLX5_TXOFF_CONFIG_TXPP)
5350 MLX5_TXOFF_DECL(full_ts,
5351 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5352 MLX5_TXOFF_CONFIG_EMPW)
5354 MLX5_TXOFF_DECL(full_ts_noi,
5355 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5356 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5357 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5358 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5360 MLX5_TXOFF_DECL(none_ts,
5361 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5362 MLX5_TXOFF_CONFIG_EMPW)
5364 MLX5_TXOFF_DECL(mdi_ts,
5365 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5366 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5368 MLX5_TXOFF_DECL(mti_ts,
5369 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5370 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5371 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5373 MLX5_TXOFF_DECL(mtiv_ts,
5374 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5375 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5376 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5377 MLX5_TXOFF_CONFIG_EMPW)
5380 * Generate routines with Legacy Multi-Packet Write support.
5381 * This mode is supported by ConnectX-4 Lx only and imposes
5382 * offload limitations, not supported:
5383 * - ACL/Flows (metadata are becoming meaningless)
5384 * - WQE Inline headers
5385 * - SRIOV (E-Switch offloads)
5387 * - tunnel encapsulation/decapsulation
5390 MLX5_TXOFF_DECL(none_mpw,
5391 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5392 MLX5_TXOFF_CONFIG_MPW)
5394 MLX5_TXOFF_DECL(mci_mpw,
5395 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5396 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5397 MLX5_TXOFF_CONFIG_MPW)
5399 MLX5_TXOFF_DECL(mc_mpw,
5400 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5401 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5403 MLX5_TXOFF_DECL(i_mpw,
5404 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5405 MLX5_TXOFF_CONFIG_MPW)
5408 * Array of declared and compiled Tx burst function and corresponding
5409 * supported offloads set. The array is used to select the Tx burst
5410 * function for specified offloads set at Tx queue configuration time.
5413 eth_tx_burst_t func;
5416 MLX5_TXOFF_INFO(full_empw,
5417 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5418 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5419 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5420 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5422 MLX5_TXOFF_INFO(none_empw,
5423 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5425 MLX5_TXOFF_INFO(md_empw,
5426 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5428 MLX5_TXOFF_INFO(mt_empw,
5429 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5430 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5432 MLX5_TXOFF_INFO(mtsc_empw,
5433 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5434 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5435 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5437 MLX5_TXOFF_INFO(mti_empw,
5438 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5439 MLX5_TXOFF_CONFIG_INLINE |
5440 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5442 MLX5_TXOFF_INFO(mtv_empw,
5443 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5444 MLX5_TXOFF_CONFIG_VLAN |
5445 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5447 MLX5_TXOFF_INFO(mtiv_empw,
5448 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5449 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5450 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5452 MLX5_TXOFF_INFO(sc_empw,
5453 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5454 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5456 MLX5_TXOFF_INFO(sci_empw,
5457 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5458 MLX5_TXOFF_CONFIG_INLINE |
5459 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5461 MLX5_TXOFF_INFO(scv_empw,
5462 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5463 MLX5_TXOFF_CONFIG_VLAN |
5464 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5466 MLX5_TXOFF_INFO(sciv_empw,
5467 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5468 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5469 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5471 MLX5_TXOFF_INFO(i_empw,
5472 MLX5_TXOFF_CONFIG_INLINE |
5473 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5475 MLX5_TXOFF_INFO(v_empw,
5476 MLX5_TXOFF_CONFIG_VLAN |
5477 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5479 MLX5_TXOFF_INFO(iv_empw,
5480 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5481 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5483 MLX5_TXOFF_INFO(full_ts_nompw,
5484 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5486 MLX5_TXOFF_INFO(full_ts_nompwi,
5487 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5488 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5489 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5490 MLX5_TXOFF_CONFIG_TXPP)
5492 MLX5_TXOFF_INFO(full_ts,
5493 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5494 MLX5_TXOFF_CONFIG_EMPW)
5496 MLX5_TXOFF_INFO(full_ts_noi,
5497 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5498 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5499 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5500 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5502 MLX5_TXOFF_INFO(none_ts,
5503 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5504 MLX5_TXOFF_CONFIG_EMPW)
5506 MLX5_TXOFF_INFO(mdi_ts,
5507 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5508 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5510 MLX5_TXOFF_INFO(mti_ts,
5511 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5512 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5513 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5515 MLX5_TXOFF_INFO(mtiv_ts,
5516 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5517 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5518 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5519 MLX5_TXOFF_CONFIG_EMPW)
5521 MLX5_TXOFF_INFO(full,
5522 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5523 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5524 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5525 MLX5_TXOFF_CONFIG_METADATA)
5527 MLX5_TXOFF_INFO(none,
5528 MLX5_TXOFF_CONFIG_NONE)
5531 MLX5_TXOFF_CONFIG_METADATA)
5534 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5535 MLX5_TXOFF_CONFIG_METADATA)
5537 MLX5_TXOFF_INFO(mtsc,
5538 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5539 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5540 MLX5_TXOFF_CONFIG_METADATA)
5542 MLX5_TXOFF_INFO(mti,
5543 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5544 MLX5_TXOFF_CONFIG_INLINE |
5545 MLX5_TXOFF_CONFIG_METADATA)
5547 MLX5_TXOFF_INFO(mtv,
5548 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5549 MLX5_TXOFF_CONFIG_VLAN |
5550 MLX5_TXOFF_CONFIG_METADATA)
5552 MLX5_TXOFF_INFO(mtiv,
5553 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5554 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5555 MLX5_TXOFF_CONFIG_METADATA)
5558 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5559 MLX5_TXOFF_CONFIG_METADATA)
5561 MLX5_TXOFF_INFO(sci,
5562 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5563 MLX5_TXOFF_CONFIG_INLINE |
5564 MLX5_TXOFF_CONFIG_METADATA)
5566 MLX5_TXOFF_INFO(scv,
5567 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5568 MLX5_TXOFF_CONFIG_VLAN |
5569 MLX5_TXOFF_CONFIG_METADATA)
5571 MLX5_TXOFF_INFO(sciv,
5572 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5573 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5574 MLX5_TXOFF_CONFIG_METADATA)
5577 MLX5_TXOFF_CONFIG_INLINE |
5578 MLX5_TXOFF_CONFIG_METADATA)
5581 MLX5_TXOFF_CONFIG_VLAN |
5582 MLX5_TXOFF_CONFIG_METADATA)
5585 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5586 MLX5_TXOFF_CONFIG_METADATA)
5588 MLX5_TXOFF_INFO(none_mpw,
5589 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5590 MLX5_TXOFF_CONFIG_MPW)
5592 MLX5_TXOFF_INFO(mci_mpw,
5593 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5594 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5595 MLX5_TXOFF_CONFIG_MPW)
5597 MLX5_TXOFF_INFO(mc_mpw,
5598 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5599 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5601 MLX5_TXOFF_INFO(i_mpw,
5602 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5603 MLX5_TXOFF_CONFIG_MPW)
5607 * Configure the Tx function to use. The routine checks configured
5608 * Tx offloads for the device and selects appropriate Tx burst
5609 * routine. There are multiple Tx burst routines compiled from
5610 * the same template in the most optimal way for the dedicated
5614 * Pointer to private data structure.
5617 * Pointer to selected Tx burst function.
5620 mlx5_select_tx_function(struct rte_eth_dev *dev)
5622 struct mlx5_priv *priv = dev->data->dev_private;
5623 struct mlx5_dev_config *config = &priv->config;
5624 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5625 unsigned int diff = 0, olx = 0, i, m;
5628 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5629 /* We should support Multi-Segment Packets. */
5630 olx |= MLX5_TXOFF_CONFIG_MULTI;
5632 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5633 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5634 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5635 DEV_TX_OFFLOAD_IP_TNL_TSO |
5636 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5637 /* We should support TCP Send Offload. */
5638 olx |= MLX5_TXOFF_CONFIG_TSO;
5640 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5641 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5642 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5643 /* We should support Software Parser for Tunnels. */
5644 olx |= MLX5_TXOFF_CONFIG_SWP;
5646 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5647 DEV_TX_OFFLOAD_UDP_CKSUM |
5648 DEV_TX_OFFLOAD_TCP_CKSUM |
5649 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5650 /* We should support IP/TCP/UDP Checksums. */
5651 olx |= MLX5_TXOFF_CONFIG_CSUM;
5653 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5654 /* We should support VLAN insertion. */
5655 olx |= MLX5_TXOFF_CONFIG_VLAN;
5657 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5658 rte_mbuf_dynflag_lookup
5659 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
5660 rte_mbuf_dynfield_lookup
5661 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
5662 /* Offload configured, dynamic entities registered. */
5663 olx |= MLX5_TXOFF_CONFIG_TXPP;
5665 if (priv->txqs_n && (*priv->txqs)[0]) {
5666 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5668 if (txd->inlen_send) {
5670 * Check the data inline requirements. Data inline
5671 * is enabled on per device basis, we can check
5672 * the first Tx queue only.
5674 * If device does not support VLAN insertion in WQE
5675 * and some queues are requested to perform VLAN
5676 * insertion offload than inline must be enabled.
5678 olx |= MLX5_TXOFF_CONFIG_INLINE;
5681 if (config->mps == MLX5_MPW_ENHANCED &&
5682 config->txq_inline_min <= 0) {
5684 * The NIC supports Enhanced Multi-Packet Write
5685 * and does not require minimal inline data.
5687 olx |= MLX5_TXOFF_CONFIG_EMPW;
5689 if (rte_flow_dynf_metadata_avail()) {
5690 /* We should support Flow metadata. */
5691 olx |= MLX5_TXOFF_CONFIG_METADATA;
5693 if (config->mps == MLX5_MPW) {
5695 * The NIC supports Legacy Multi-Packet Write.
5696 * The MLX5_TXOFF_CONFIG_MPW controls the
5697 * descriptor building method in combination
5698 * with MLX5_TXOFF_CONFIG_EMPW.
5700 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5701 MLX5_TXOFF_CONFIG_SWP |
5702 MLX5_TXOFF_CONFIG_VLAN |
5703 MLX5_TXOFF_CONFIG_METADATA)))
5704 olx |= MLX5_TXOFF_CONFIG_EMPW |
5705 MLX5_TXOFF_CONFIG_MPW;
5708 * Scan the routines table to find the minimal
5709 * satisfying routine with requested offloads.
5711 m = RTE_DIM(txoff_func);
5712 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5715 tmp = txoff_func[i].olx;
5717 /* Meets requested offloads exactly.*/
5721 if ((tmp & olx) != olx) {
5722 /* Does not meet requested offloads at all. */
5725 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5726 /* Do not enable legacy MPW if not configured. */
5728 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5729 /* Do not enable eMPW if not configured. */
5731 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5732 /* Do not enable inlining if not configured. */
5734 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5735 /* Do not enable scheduling if not configured. */
5738 * Some routine meets the requirements.
5739 * Check whether it has minimal amount
5740 * of not requested offloads.
5742 tmp = __builtin_popcountl(tmp & ~olx);
5743 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5744 /* First or better match, save and continue. */
5750 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5751 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5752 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5753 /* Lighter not requested offload. */
5758 if (m >= RTE_DIM(txoff_func)) {
5759 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5760 " for requested offloads %04X",
5761 dev->data->port_id, olx);
5764 DRV_LOG(DEBUG, "port %u has selected Tx function"
5765 " supporting offloads %04X/%04X",
5766 dev->data->port_id, olx, txoff_func[m].olx);
5767 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5768 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5769 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5770 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5771 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5772 DRV_LOG(DEBUG, "\tSWP (software parser)");
5773 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5774 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5775 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5776 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5777 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5778 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5779 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5780 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5781 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5782 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5783 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5784 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5785 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5787 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5789 return txoff_func[m].func;
5793 * DPDK callback to get the TX queue information
5796 * Pointer to the device structure.
5798 * @param tx_queue_id
5799 * Tx queue identificator.
5802 * Pointer to the TX queue information structure.
5809 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5810 struct rte_eth_txq_info *qinfo)
5812 struct mlx5_priv *priv = dev->data->dev_private;
5813 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5814 struct mlx5_txq_ctrl *txq_ctrl =
5815 container_of(txq, struct mlx5_txq_ctrl, txq);
5819 qinfo->nb_desc = txq->elts_s;
5820 qinfo->conf.tx_thresh.pthresh = 0;
5821 qinfo->conf.tx_thresh.hthresh = 0;
5822 qinfo->conf.tx_thresh.wthresh = 0;
5823 qinfo->conf.tx_rs_thresh = 0;
5824 qinfo->conf.tx_free_thresh = 0;
5825 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5826 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5830 * DPDK callback to get the TX packet burst mode information
5833 * Pointer to the device structure.
5835 * @param tx_queue_id
5836 * Tx queue identificatior.
5839 * Pointer to the burts mode information.
5842 * 0 as success, -EINVAL as failure.
5846 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5847 uint16_t tx_queue_id,
5848 struct rte_eth_burst_mode *mode)
5850 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5851 struct mlx5_priv *priv = dev->data->dev_private;
5852 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5853 unsigned int i, olx;
5855 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5856 if (pkt_burst == txoff_func[i].func) {
5857 olx = txoff_func[i].olx;
5858 snprintf(mode->info, sizeof(mode->info),
5859 "%s%s%s%s%s%s%s%s%s%s",
5860 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5861 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5862 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5863 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5865 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5867 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5869 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5871 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5873 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5875 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5877 (olx & MLX5_TXOFF_CONFIG_TXPP) ?
5879 (txq && txq->fast_free) ?
5880 " + Fast Free" : "");