1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
32 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
33 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
34 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
36 sizeof(rte_v128u32_t)),
37 "invalid Ethernet Segment data size");
38 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
40 sizeof(struct rte_vlan_hdr) +
41 2 * RTE_ETHER_ADDR_LEN),
42 "invalid Ethernet Segment data size");
43 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
45 sizeof(rte_v128u32_t)),
46 "invalid Ethernet Segment data size");
47 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
49 sizeof(struct rte_vlan_hdr) +
50 2 * RTE_ETHER_ADDR_LEN),
51 "invalid Ethernet Segment data size");
52 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
54 sizeof(rte_v128u32_t)),
55 "invalid Ethernet Segment data size");
56 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
58 sizeof(struct rte_vlan_hdr) +
59 2 * RTE_ETHER_ADDR_LEN),
60 "invalid Ethernet Segment data size");
61 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
62 (2 * RTE_ETHER_ADDR_LEN),
63 "invalid Data Segment data size");
64 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
65 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
66 static_assert((sizeof(struct rte_vlan_hdr) +
67 sizeof(struct rte_ether_hdr)) ==
68 MLX5_ESEG_MIN_INLINE_SIZE,
69 "invalid min inline data size");
70 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
71 MLX5_DSEG_MAX, "invalid WQE max size");
72 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
73 "invalid WQE Control Segment size");
74 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
75 "invalid WQE Ethernet Segment size");
76 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
77 "invalid WQE Data Segment size");
78 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
81 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
82 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
85 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
86 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
88 uint64_t rte_net_mlx5_dynf_inline_mask;
91 * Build a table to translate Rx completion flags to packet type.
93 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
96 mlx5_set_ptype_table(void)
99 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
101 /* Last entry must not be overwritten, reserved for errored packet. */
102 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
103 (*p)[i] = RTE_PTYPE_UNKNOWN;
105 * The index to the array should have:
106 * bit[1:0] = l3_hdr_type
107 * bit[4:2] = l4_hdr_type
110 * bit[7] = outer_l3_type
113 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
115 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
116 RTE_PTYPE_L4_NONFRAG;
117 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 RTE_PTYPE_L4_NONFRAG;
120 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
122 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
125 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
127 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
131 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
133 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
138 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
140 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
142 /* Repeat with outer_l3_type being set. Just in case. */
143 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
144 RTE_PTYPE_L4_NONFRAG;
145 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
146 RTE_PTYPE_L4_NONFRAG;
147 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
151 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
153 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
157 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
159 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
161 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
163 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
165 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
168 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
169 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_NONFRAG;
172 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_NONFRAG;
175 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
176 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
178 RTE_PTYPE_INNER_L4_NONFRAG;
179 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L4_NONFRAG;
182 /* Tunneled - Fragmented */
183 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L4_FRAG;
186 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L4_FRAG;
189 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
191 RTE_PTYPE_INNER_L4_FRAG;
192 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
193 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
194 RTE_PTYPE_INNER_L4_FRAG;
196 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_TCP;
199 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_TCP;
202 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L4_TCP;
205 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
206 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L4_TCP;
208 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
209 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L4_TCP;
211 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L4_TCP;
214 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
216 RTE_PTYPE_INNER_L4_TCP;
217 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
219 RTE_PTYPE_INNER_L4_TCP;
220 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L4_TCP;
223 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_TCP;
226 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_TCP;
229 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
233 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L4_UDP;
236 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L4_UDP;
239 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L4_UDP;
242 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L4_UDP;
248 * Build a table to translate packet to checksum type of Verbs.
251 mlx5_set_cksum_table(void)
257 * The index should have:
258 * bit[0] = PKT_TX_TCP_SEG
259 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
260 * bit[4] = PKT_TX_IP_CKSUM
261 * bit[8] = PKT_TX_OUTER_IP_CKSUM
264 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
267 /* Tunneled packet. */
268 if (i & (1 << 8)) /* Outer IP. */
269 v |= MLX5_ETH_WQE_L3_CSUM;
270 if (i & (1 << 4)) /* Inner IP. */
271 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
272 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
273 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
276 if (i & (1 << 4)) /* IP. */
277 v |= MLX5_ETH_WQE_L3_CSUM;
278 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
279 v |= MLX5_ETH_WQE_L4_CSUM;
281 mlx5_cksum_table[i] = v;
286 * Build a table to translate packet type of mbuf to SWP type of Verbs.
289 mlx5_set_swp_types_table(void)
295 * The index should have:
296 * bit[0:1] = PKT_TX_L4_MASK
297 * bit[4] = PKT_TX_IPV6
298 * bit[8] = PKT_TX_OUTER_IPV6
299 * bit[9] = PKT_TX_OUTER_UDP
301 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
304 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
306 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
308 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
309 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
310 v |= MLX5_ETH_WQE_L4_INNER_UDP;
311 mlx5_swp_types_table[i] = v;
315 #define MLX5_SYSTEM_LOG_DIR "/var/log"
317 * Dump debug information to log file.
322 * If not NULL this string is printed as a header to the output
323 * and the output will be in hexadecimal view.
325 * This is the buffer address to print out.
327 * The number of bytes to dump out.
330 mlx5_dump_debug_information(const char *fname, const char *hex_title,
331 const void *buf, unsigned int hex_len)
335 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
336 fd = fopen(path, "a+");
338 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
339 MKSTR(path2, "./%s", fname);
340 fd = fopen(path2, "a+");
342 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
345 DRV_LOG(INFO, "New debug dump in file %s", path2);
347 DRV_LOG(INFO, "New debug dump in file %s", path);
350 rte_hexdump(fd, hex_title, buf, hex_len);
352 fprintf(fd, "%s", (const char *)buf);
353 fprintf(fd, "\n\n\n");
358 * Modify a Verbs/DevX queue state.
359 * This must be called from the primary process.
362 * Pointer to Ethernet device.
364 * State modify request parameters.
367 * 0 in case of success else non-zero value and rte_errno is set.
370 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
371 const struct mlx5_mp_arg_queue_state_modify *sm)
374 struct mlx5_priv *priv = dev->data->dev_private;
377 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
378 struct mlx5_rxq_ctrl *rxq_ctrl =
379 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
381 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
383 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
384 sm->state, strerror(errno));
389 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
390 struct mlx5_txq_ctrl *txq_ctrl =
391 container_of(txq, struct mlx5_txq_ctrl, txq);
393 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
394 MLX5_TXQ_MOD_ERR2RDY,
395 (uint8_t)priv->dev_port);
403 * Modify a Verbs queue state.
406 * Pointer to Ethernet device.
408 * State modify request parameters.
411 * 0 in case of success else non-zero value.
414 mlx5_queue_state_modify(struct rte_eth_dev *dev,
415 struct mlx5_mp_arg_queue_state_modify *sm)
417 struct mlx5_priv *priv = dev->data->dev_private;
420 switch (rte_eal_process_type()) {
421 case RTE_PROC_PRIMARY:
422 ret = mlx5_queue_state_modify_primary(dev, sm);
424 case RTE_PROC_SECONDARY:
425 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
433 /* Generate routines with Enhanced Multi-Packet Write support. */
434 MLX5_TXOFF_DECL(full_empw,
435 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
437 MLX5_TXOFF_DECL(none_empw,
438 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
440 MLX5_TXOFF_DECL(md_empw,
441 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
443 MLX5_TXOFF_DECL(mt_empw,
444 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
445 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
447 MLX5_TXOFF_DECL(mtsc_empw,
448 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
449 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
450 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
452 MLX5_TXOFF_DECL(mti_empw,
453 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
454 MLX5_TXOFF_CONFIG_INLINE |
455 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
457 MLX5_TXOFF_DECL(mtv_empw,
458 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
459 MLX5_TXOFF_CONFIG_VLAN |
460 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
462 MLX5_TXOFF_DECL(mtiv_empw,
463 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
464 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
465 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
467 MLX5_TXOFF_DECL(sc_empw,
468 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
469 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
471 MLX5_TXOFF_DECL(sci_empw,
472 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
473 MLX5_TXOFF_CONFIG_INLINE |
474 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
476 MLX5_TXOFF_DECL(scv_empw,
477 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
478 MLX5_TXOFF_CONFIG_VLAN |
479 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
481 MLX5_TXOFF_DECL(sciv_empw,
482 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
483 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
484 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
486 MLX5_TXOFF_DECL(i_empw,
487 MLX5_TXOFF_CONFIG_INLINE |
488 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
490 MLX5_TXOFF_DECL(v_empw,
491 MLX5_TXOFF_CONFIG_VLAN |
492 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
494 MLX5_TXOFF_DECL(iv_empw,
495 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
496 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
498 /* Generate routines without Enhanced Multi-Packet Write support. */
499 MLX5_TXOFF_DECL(full,
500 MLX5_TXOFF_CONFIG_FULL)
502 MLX5_TXOFF_DECL(none,
503 MLX5_TXOFF_CONFIG_NONE)
506 MLX5_TXOFF_CONFIG_METADATA)
509 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
510 MLX5_TXOFF_CONFIG_METADATA)
512 MLX5_TXOFF_DECL(mtsc,
513 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
514 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
515 MLX5_TXOFF_CONFIG_METADATA)
518 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
519 MLX5_TXOFF_CONFIG_INLINE |
520 MLX5_TXOFF_CONFIG_METADATA)
524 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
525 MLX5_TXOFF_CONFIG_VLAN |
526 MLX5_TXOFF_CONFIG_METADATA)
529 MLX5_TXOFF_DECL(mtiv,
530 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
531 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
532 MLX5_TXOFF_CONFIG_METADATA)
535 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
536 MLX5_TXOFF_CONFIG_METADATA)
539 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
540 MLX5_TXOFF_CONFIG_INLINE |
541 MLX5_TXOFF_CONFIG_METADATA)
545 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
546 MLX5_TXOFF_CONFIG_VLAN |
547 MLX5_TXOFF_CONFIG_METADATA)
550 MLX5_TXOFF_DECL(sciv,
551 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
552 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
553 MLX5_TXOFF_CONFIG_METADATA)
556 MLX5_TXOFF_CONFIG_INLINE |
557 MLX5_TXOFF_CONFIG_METADATA)
560 MLX5_TXOFF_CONFIG_VLAN |
561 MLX5_TXOFF_CONFIG_METADATA)
564 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
565 MLX5_TXOFF_CONFIG_METADATA)
567 /* Generate routines with timestamp scheduling. */
568 MLX5_TXOFF_DECL(full_ts_nompw,
569 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
571 MLX5_TXOFF_DECL(full_ts_nompwi,
572 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
573 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
574 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
575 MLX5_TXOFF_CONFIG_TXPP)
577 MLX5_TXOFF_DECL(full_ts,
578 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
579 MLX5_TXOFF_CONFIG_EMPW)
581 MLX5_TXOFF_DECL(full_ts_noi,
582 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
583 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
584 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
585 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
587 MLX5_TXOFF_DECL(none_ts,
588 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
589 MLX5_TXOFF_CONFIG_EMPW)
591 MLX5_TXOFF_DECL(mdi_ts,
592 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
593 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
595 MLX5_TXOFF_DECL(mti_ts,
596 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
597 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
598 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
600 MLX5_TXOFF_DECL(mtiv_ts,
601 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
602 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
603 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
604 MLX5_TXOFF_CONFIG_EMPW)
607 * Generate routines with Legacy Multi-Packet Write support.
608 * This mode is supported by ConnectX-4 Lx only and imposes
609 * offload limitations, not supported:
610 * - ACL/Flows (metadata are becoming meaningless)
611 * - WQE Inline headers
612 * - SRIOV (E-Switch offloads)
614 * - tunnel encapsulation/decapsulation
617 MLX5_TXOFF_DECL(none_mpw,
618 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
619 MLX5_TXOFF_CONFIG_MPW)
621 MLX5_TXOFF_DECL(mci_mpw,
622 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
623 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
624 MLX5_TXOFF_CONFIG_MPW)
626 MLX5_TXOFF_DECL(mc_mpw,
627 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
628 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
630 MLX5_TXOFF_DECL(i_mpw,
631 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
632 MLX5_TXOFF_CONFIG_MPW)